drivers/net/s2io.c

   1 /************************************************************************
   2  * s2io.c: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC
   3  * Copyright(c) 2002-2010 Exar Corp.
   4  *
   5  * This software may be used and distributed according to the terms of
   6  * the GNU General Public License (GPL), incorporated herein by reference.
   7  * Drivers based on or derived from this code fall under the GPL and must
   8  * retain the authorship, copyright and license notice.  This file is not
   9  * a complete program and may only be used when the entire operating
  10  * system is licensed under the GPL.
  11  * See the file COPYING in this distribution for more information.
  12  *
  13  * Credits:
  14  * Jeff Garzik          : For pointing out the improper error condition
  15  *                        check in the s2io_xmit routine and also some
  16  *                        issues in the Tx watch dog function. Also for
  17  *                        patiently answering all those innumerable
  18  *                        questions regaring the 2.6 porting issues.
  19  * Stephen Hemminger    : Providing proper 2.6 porting mechanism for some
  20  *                        macros available only in 2.6 Kernel.
  21  * Francois Romieu      : For pointing out all code part that were
  22  *                        deprecated and also styling related comments.
  23  * Grant Grundler       : For helping me get rid of some Architecture
  24  *                        dependent code.
  25  * Christopher Hellwig  : Some more 2.6 specific issues in the driver.
  26  *
  27  * The module loadable parameters that are supported by the driver and a brief
  28  * explanation of all the variables.
  29  *
  30  * rx_ring_num : This can be used to program the number of receive rings used
  31  * in the driver.
  32  * rx_ring_sz: This defines the number of receive blocks each ring can have.
  33  *     This is also an array of size 8.
  34  * rx_ring_mode: This defines the operation mode of all 8 rings. The valid
  35  *              values are 1, 2.
  36  * tx_fifo_num: This defines the number of Tx FIFOs thats used int the driver.
  37  * tx_fifo_len: This too is an array of 8. Each element defines the number of
  38  * Tx descriptors that can be associated with each corresponding FIFO.
  39  * intr_type: This defines the type of interrupt. The values can be 0(INTA),
  40  *     2(MSI_X). Default value is '2(MSI_X)'
  41  * lro: Specifies whether to enable Large Receive Offload (LRO) or not.
  42  *     Possible values '1' for enable '0' for disable. Default is '0'
  43  * lro_max_pkts: This parameter defines maximum number of packets can be
  44  *     aggregated as a single large packet
  45  * napi: This parameter used to enable/disable NAPI (polling Rx)
  46  *     Possible values '1' for enable and '0' for disable. Default is '1'
  47  * ufo: This parameter used to enable/disable UDP Fragmentation Offload(UFO)
  48  *      Possible values '1' for enable and '0' for disable. Default is '0'
  49  * vlan_tag_strip: This can be used to enable or disable vlan stripping.
  50  *                 Possible values '1' for enable , '0' for disable.
  51  *                 Default is '2' - which means disable in promisc mode
  52  *                 and enable in non-promiscuous mode.
  53  * multiq: This parameter used to enable/disable MULTIQUEUE support.
  54  *      Possible values '1' for enable and '0' for disable. Default is '0'
  55  ************************************************************************/
  56
  57 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  58
  59 #include <linux/module.h>
  60 #include <linux/types.h>
  61 #include <linux/errno.h>
  62 #include <linux/ioport.h>
  63 #include <linux/pci.h>
  64 #include <linux/dma-mapping.h>
  65 #include <linux/kernel.h>
  66 #include <linux/netdevice.h>
  67 #include <linux/etherdevice.h>
  68 #include <linux/mdio.h>
  69 #include <linux/skbuff.h>
  70 #include <linux/init.h>
  71 #include <linux/delay.h>
  72 #include <linux/stddef.h>
  73 #include <linux/ioctl.h>
  74 #include <linux/timex.h>
  75 #include <linux/ethtool.h>
  76 #include <linux/workqueue.h>
  77 #include <linux/if_vlan.h>
  78 #include <linux/ip.h>
  79 #include <linux/tcp.h>
  80 #include <linux/uaccess.h>
  81 #include <linux/io.h>
  82 #include <linux/slab.h>
  83 #include <net/tcp.h>
  84
  85 #include <asm/system.h>
  86 #include <asm/div64.h>
  87 #include <asm/irq.h>
  88
  89 /* local include */
  90 #include "s2io.h"
  91 #include "s2io-regs.h"
  92
  93 #define DRV_VERSION "2.0.26.26"
  94
  95 /* S2io Driver name & version. */
  96 static char s2io_driver_name[] = "Neterion";
  97 static char s2io_driver_version[] = DRV_VERSION;
  98
  99 static int rxd_size[2] = {32, 48};
 100 static int rxd_count[2] = {127, 85};
 101
 102 static inline int RXD_IS_UP2DT(struct RxD_t *rxdp)
 103 {
 104         int ret;
 105
 106         ret = ((!(rxdp->Control_1 & RXD_OWN_XENA)) &&
 107                (GET_RXD_MARKER(rxdp->Control_2) != THE_RXD_MARK));
 108
 109         return ret;
 110 }
 111
 112 /*
 113  * Cards with following subsystem_id have a link state indication
 114  * problem, 600B, 600C, 600D, 640B, 640C and 640D.
 115  * macro below identifies these cards given the subsystem_id.
 116  */
 117 #define CARDS_WITH_FAULTY_LINK_INDICATORS(dev_type, subid)              \
 118         (dev_type == XFRAME_I_DEVICE) ?                                 \
 119         ((((subid >= 0x600B) && (subid <= 0x600D)) ||                   \
 120           ((subid >= 0x640B) && (subid <= 0x640D))) ? 1 : 0) : 0
 121
 122 #define LINK_IS_UP(val64) (!(val64 & (ADAPTER_STATUS_RMAC_REMOTE_FAULT | \
 123                                       ADAPTER_STATUS_RMAC_LOCAL_FAULT)))
 124
 125 static inline int is_s2io_card_up(const struct s2io_nic *sp)
 126 {
 127         return test_bit(__S2IO_STATE_CARD_UP, &sp->state);
 128 }
 129
 130 /* Ethtool related variables and Macros. */
 131 static const char s2io_gstrings[][ETH_GSTRING_LEN] = {
 132         "Register test\t(offline)",
 133         "Eeprom test\t(offline)",
 134         "Link test\t(online)",
 135         "RLDRAM test\t(offline)",
 136         "BIST Test\t(offline)"
 137 };
 138
 139 static const char ethtool_xena_stats_keys[][ETH_GSTRING_LEN] = {
 140         {"tmac_frms"},
 141         {"tmac_data_octets"},
 142         {"tmac_drop_frms"},
 143         {"tmac_mcst_frms"},
 144         {"tmac_bcst_frms"},
 145         {"tmac_pause_ctrl_frms"},
 146         {"tmac_ttl_octets"},
 147         {"tmac_ucst_frms"},
 148         {"tmac_nucst_frms"},
 149         {"tmac_any_err_frms"},
 150         {"tmac_ttl_less_fb_octets"},
 151         {"tmac_vld_ip_octets"},
 152         {"tmac_vld_ip"},
 153         {"tmac_drop_ip"},
 154         {"tmac_icmp"},
 155         {"tmac_rst_tcp"},
 156         {"tmac_tcp"},
 157         {"tmac_udp"},
 158         {"rmac_vld_frms"},
 159         {"rmac_data_octets"},
 160         {"rmac_fcs_err_frms"},
 161         {"rmac_drop_frms"},
 162         {"rmac_vld_mcst_frms"},
 163         {"rmac_vld_bcst_frms"},
 164         {"rmac_in_rng_len_err_frms"},
 165         {"rmac_out_rng_len_err_frms"},
 166         {"rmac_long_frms"},
 167         {"rmac_pause_ctrl_frms"},
 168         {"rmac_unsup_ctrl_frms"},
 169         {"rmac_ttl_octets"},
 170         {"rmac_accepted_ucst_frms"},
 171         {"rmac_accepted_nucst_frms"},
 172         {"rmac_discarded_frms"},
 173         {"rmac_drop_events"},
 174         {"rmac_ttl_less_fb_octets"},
 175         {"rmac_ttl_frms"},
 176         {"rmac_usized_frms"},
 177         {"rmac_osized_frms"},
 178         {"rmac_frag_frms"},
 179         {"rmac_jabber_frms"},
 180         {"rmac_ttl_64_frms"},
 181         {"rmac_ttl_65_127_frms"},
 182         {"rmac_ttl_128_255_frms"},
 183         {"rmac_ttl_256_511_frms"},
 184         {"rmac_ttl_512_1023_frms"},
 185         {"rmac_ttl_1024_1518_frms"},
 186         {"rmac_ip"},
 187         {"rmac_ip_octets"},
 188         {"rmac_hdr_err_ip"},
 189         {"rmac_drop_ip"},
 190         {"rmac_icmp"},
 191         {"rmac_tcp"},
 192         {"rmac_udp"},
 193         {"rmac_err_drp_udp"},
 194         {"rmac_xgmii_err_sym"},
 195         {"rmac_frms_q0"},
 196         {"rmac_frms_q1"},
 197         {"rmac_frms_q2"},
 198         {"rmac_frms_q3"},
 199         {"rmac_frms_q4"},
 200         {"rmac_frms_q5"},
 201         {"rmac_frms_q6"},
 202         {"rmac_frms_q7"},
 203         {"rmac_full_q0"},
 204         {"rmac_full_q1"},
 205         {"rmac_full_q2"},
 206         {"rmac_full_q3"},
 207         {"rmac_full_q4"},
 208         {"rmac_full_q5"},
 209         {"rmac_full_q6"},
 210         {"rmac_full_q7"},
 211         {"rmac_pause_cnt"},
 212         {"rmac_xgmii_data_err_cnt"},
 213         {"rmac_xgmii_ctrl_err_cnt"},
 214         {"rmac_accepted_ip"},
 215         {"rmac_err_tcp"},
 216         {"rd_req_cnt"},
 217         {"new_rd_req_cnt"},
 218         {"new_rd_req_rtry_cnt"},
 219         {"rd_rtry_cnt"},
 220         {"wr_rtry_rd_ack_cnt"},
 221         {"wr_req_cnt"},
 222         {"new_wr_req_cnt"},
 223         {"new_wr_req_rtry_cnt"},
 224         {"wr_rtry_cnt"},
 225         {"wr_disc_cnt"},
 226         {"rd_rtry_wr_ack_cnt"},
 227         {"txp_wr_cnt"},
 228         {"txd_rd_cnt"},
 229         {"txd_wr_cnt"},
 230         {"rxd_rd_cnt"},
 231         {"rxd_wr_cnt"},
 232         {"txf_rd_cnt"},
 233         {"rxf_wr_cnt"}
 234 };
 235
 236 static const char ethtool_enhanced_stats_keys[][ETH_GSTRING_LEN] = {
 237         {"rmac_ttl_1519_4095_frms"},
 238         {"rmac_ttl_4096_8191_frms"},
 239         {"rmac_ttl_8192_max_frms"},
 240         {"rmac_ttl_gt_max_frms"},
 241         {"rmac_osized_alt_frms"},
 242         {"rmac_jabber_alt_frms"},
 243         {"rmac_gt_max_alt_frms"},
 244         {"rmac_vlan_frms"},
 245         {"rmac_len_discard"},
 246         {"rmac_fcs_discard"},
 247         {"rmac_pf_discard"},
 248         {"rmac_da_discard"},
 249         {"rmac_red_discard"},
 250         {"rmac_rts_discard"},
 251         {"rmac_ingm_full_discard"},
 252         {"link_fault_cnt"}
 253 };
 254
 255 static const char ethtool_driver_stats_keys[][ETH_GSTRING_LEN] = {
 256         {"\n DRIVER STATISTICS"},
 257         {"single_bit_ecc_errs"},
 258         {"double_bit_ecc_errs"},
 259         {"parity_err_cnt"},
 260         {"serious_err_cnt"},
 261         {"soft_reset_cnt"},
 262         {"fifo_full_cnt"},
 263         {"ring_0_full_cnt"},
 264         {"ring_1_full_cnt"},
 265         {"ring_2_full_cnt"},
 266         {"ring_3_full_cnt"},
 267         {"ring_4_full_cnt"},
 268         {"ring_5_full_cnt"},
 269         {"ring_6_full_cnt"},
 270         {"ring_7_full_cnt"},
 271         {"alarm_transceiver_temp_high"},
 272         {"alarm_transceiver_temp_low"},
 273         {"alarm_laser_bias_current_high"},
 274         {"alarm_laser_bias_current_low"},
 275         {"alarm_laser_output_power_high"},
 276         {"alarm_laser_output_power_low"},
 277         {"warn_transceiver_temp_high"},
 278         {"warn_transceiver_temp_low"},
 279         {"warn_laser_bias_current_high"},
 280         {"warn_laser_bias_current_low"},
 281         {"warn_laser_output_power_high"},
 282         {"warn_laser_output_power_low"},
 283         {"lro_aggregated_pkts"},
 284         {"lro_flush_both_count"},
 285         {"lro_out_of_sequence_pkts"},
 286         {"lro_flush_due_to_max_pkts"},
 287         {"lro_avg_aggr_pkts"},
 288         {"mem_alloc_fail_cnt"},
 289         {"pci_map_fail_cnt"},
 290         {"watchdog_timer_cnt"},
 291         {"mem_allocated"},
 292         {"mem_freed"},
 293         {"link_up_cnt"},
 294         {"link_down_cnt"},
 295         {"link_up_time"},
 296         {"link_down_time"},
 297         {"tx_tcode_buf_abort_cnt"},
 298         {"tx_tcode_desc_abort_cnt"},
 299         {"tx_tcode_parity_err_cnt"},
 300         {"tx_tcode_link_loss_cnt"},
 301         {"tx_tcode_list_proc_err_cnt"},
 302         {"rx_tcode_parity_err_cnt"},
 303         {"rx_tcode_abort_cnt"},
 304         {"rx_tcode_parity_abort_cnt"},
 305         {"rx_tcode_rda_fail_cnt"},
 306         {"rx_tcode_unkn_prot_cnt"},
 307         {"rx_tcode_fcs_err_cnt"},
 308         {"rx_tcode_buf_size_err_cnt"},
 309         {"rx_tcode_rxd_corrupt_cnt"},
 310         {"rx_tcode_unkn_err_cnt"},
 311         {"tda_err_cnt"},
 312         {"pfc_err_cnt"},
 313         {"pcc_err_cnt"},
 314         {"tti_err_cnt"},
 315         {"tpa_err_cnt"},
 316         {"sm_err_cnt"},
 317         {"lso_err_cnt"},
 318         {"mac_tmac_err_cnt"},
 319         {"mac_rmac_err_cnt"},
 320         {"xgxs_txgxs_err_cnt"},
 321         {"xgxs_rxgxs_err_cnt"},
 322         {"rc_err_cnt"},
 323         {"prc_pcix_err_cnt"},
 324         {"rpa_err_cnt"},
 325         {"rda_err_cnt"},
 326         {"rti_err_cnt"},
 327         {"mc_err_cnt"}
 328 };
 329
 330 #define S2IO_XENA_STAT_LEN      ARRAY_SIZE(ethtool_xena_stats_keys)
 331 #define S2IO_ENHANCED_STAT_LEN  ARRAY_SIZE(ethtool_enhanced_stats_keys)
 332 #define S2IO_DRIVER_STAT_LEN    ARRAY_SIZE(ethtool_driver_stats_keys)
 333
 334 #define XFRAME_I_STAT_LEN (S2IO_XENA_STAT_LEN + S2IO_DRIVER_STAT_LEN)
 335 #define XFRAME_II_STAT_LEN (XFRAME_I_STAT_LEN + S2IO_ENHANCED_STAT_LEN)
 336
 337 #define XFRAME_I_STAT_STRINGS_LEN (XFRAME_I_STAT_LEN * ETH_GSTRING_LEN)
 338 #define XFRAME_II_STAT_STRINGS_LEN (XFRAME_II_STAT_LEN * ETH_GSTRING_LEN)
 339
 340 #define S2IO_TEST_LEN   ARRAY_SIZE(s2io_gstrings)
 341 #define S2IO_STRINGS_LEN        (S2IO_TEST_LEN * ETH_GSTRING_LEN)
 342
 343 #define S2IO_TIMER_CONF(timer, handle, arg, exp)        \
 344         init_timer(&timer);                             \
 345         timer.function = handle;                        \
 346         timer.data = (unsigned long)arg;                \
 347         mod_timer(&timer, (jiffies + exp))              \
 348
 349 /* copy mac addr to def_mac_addr array */
 350 static void do_s2io_copy_mac_addr(struct s2io_nic *sp, int offset, u64 mac_addr)
 351 {
 352         sp->def_mac_addr[offset].mac_addr[5] = (u8) (mac_addr);
 353         sp->def_mac_addr[offset].mac_addr[4] = (u8) (mac_addr >> 8);
 354         sp->def_mac_addr[offset].mac_addr[3] = (u8) (mac_addr >> 16);
 355         sp->def_mac_addr[offset].mac_addr[2] = (u8) (mac_addr >> 24);
 356         sp->def_mac_addr[offset].mac_addr[1] = (u8) (mac_addr >> 32);
 357         sp->def_mac_addr[offset].mac_addr[0] = (u8) (mac_addr >> 40);
 358 }
 359
 360 /* Add the vlan */
 361 static void s2io_vlan_rx_register(struct net_device *dev,
 362                                   struct vlan_group *grp)
 363 {
 364         int i;
 365         struct s2io_nic *nic = netdev_priv(dev);
 366         unsigned long flags[MAX_TX_FIFOS];
 367         struct config_param *config = &nic->config;
 368         struct mac_info *mac_control = &nic->mac_control;
 369
 370         for (i = 0; i < config->tx_fifo_num; i++) {
 371                 struct fifo_info *fifo = &mac_control->fifos[i];
 372
 373                 spin_lock_irqsave(&fifo->tx_lock, flags[i]);
 374         }
 375
 376         nic->vlgrp = grp;
 377
 378         for (i = config->tx_fifo_num - 1; i >= 0; i--) {
 379                 struct fifo_info *fifo = &mac_control->fifos[i];
 380
 381                 spin_unlock_irqrestore(&fifo->tx_lock, flags[i]);
 382         }
 383 }
 384
 385 /* Unregister the vlan */
 386 static void s2io_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
 387 {
 388         int i;
 389         struct s2io_nic *nic = netdev_priv(dev);
 390         unsigned long flags[MAX_TX_FIFOS];
 391         struct config_param *config = &nic->config;
 392         struct mac_info *mac_control = &nic->mac_control;
 393
 394         for (i = 0; i < config->tx_fifo_num; i++) {
 395                 struct fifo_info *fifo = &mac_control->fifos[i];
 396
 397                 spin_lock_irqsave(&fifo->tx_lock, flags[i]);
 398         }
 399
 400         if (nic->vlgrp)
 401                 vlan_group_set_device(nic->vlgrp, vid, NULL);
 402
 403         for (i = config->tx_fifo_num - 1; i >= 0; i--) {
 404                 struct fifo_info *fifo = &mac_control->fifos[i];
 405
 406                 spin_unlock_irqrestore(&fifo->tx_lock, flags[i]);
 407         }
 408 }
 409
 410 /*
 411  * Constants to be programmed into the Xena's registers, to configure
 412  * the XAUI.
 413  */
 414
 415 #define END_SIGN        0x0
 416 static const u64 herc_act_dtx_cfg[] = {
 417         /* Set address */
 418         0x8000051536750000ULL, 0x80000515367500E0ULL,
 419         /* Write data */
 420         0x8000051536750004ULL, 0x80000515367500E4ULL,
 421         /* Set address */
 422         0x80010515003F0000ULL, 0x80010515003F00E0ULL,
 423         /* Write data */
 424         0x80010515003F0004ULL, 0x80010515003F00E4ULL,
 425         /* Set address */
 426         0x801205150D440000ULL, 0x801205150D4400E0ULL,
 427         /* Write data */
 428         0x801205150D440004ULL, 0x801205150D4400E4ULL,
 429         /* Set address */
 430         0x80020515F2100000ULL, 0x80020515F21000E0ULL,
 431         /* Write data */
 432         0x80020515F2100004ULL, 0x80020515F21000E4ULL,
 433         /* Done */
 434         END_SIGN
 435 };
 436
 437 static const u64 xena_dtx_cfg[] = {
 438         /* Set address */
 439         0x8000051500000000ULL, 0x80000515000000E0ULL,
 440         /* Write data */
 441         0x80000515D9350004ULL, 0x80000515D93500E4ULL,
 442         /* Set address */
 443         0x8001051500000000ULL, 0x80010515000000E0ULL,
 444         /* Write data */
 445         0x80010515001E0004ULL, 0x80010515001E00E4ULL,
 446         /* Set address */
 447         0x8002051500000000ULL, 0x80020515000000E0ULL,
 448         /* Write data */
 449         0x80020515F2100004ULL, 0x80020515F21000E4ULL,
 450         END_SIGN
 451 };
 452
 453 /*
 454  * Constants for Fixing the MacAddress problem seen mostly on
 455  * Alpha machines.
 456  */
 457 static const u64 fix_mac[] = {
 458         0x0060000000000000ULL, 0x0060600000000000ULL,
 459         0x0040600000000000ULL, 0x0000600000000000ULL,
 460         0x0020600000000000ULL, 0x0060600000000000ULL,
 461         0x0020600000000000ULL, 0x0060600000000000ULL,
 462         0x0020600000000000ULL, 0x0060600000000000ULL,
 463         0x0020600000000000ULL, 0x0060600000000000ULL,
 464         0x0020600000000000ULL, 0x0060600000000000ULL,
 465         0x0020600000000000ULL, 0x0060600000000000ULL,
 466         0x0020600000000000ULL, 0x0060600000000000ULL,
 467         0x0020600000000000ULL, 0x0060600000000000ULL,
 468         0x0020600000000000ULL, 0x0060600000000000ULL,
 469         0x0020600000000000ULL, 0x0060600000000000ULL,
 470         0x0020600000000000ULL, 0x0000600000000000ULL,
 471         0x0040600000000000ULL, 0x0060600000000000ULL,
 472         END_SIGN
 473 };
 474
 475 MODULE_LICENSE("GPL");
 476 MODULE_VERSION(DRV_VERSION);
 477
 478
 479 /* Module Loadable parameters. */
 480 S2IO_PARM_INT(tx_fifo_num, FIFO_DEFAULT_NUM);
 481 S2IO_PARM_INT(rx_ring_num, 1);
 482 S2IO_PARM_INT(multiq, 0);
 483 S2IO_PARM_INT(rx_ring_mode, 1);
 484 S2IO_PARM_INT(use_continuous_tx_intrs, 1);
 485 S2IO_PARM_INT(rmac_pause_time, 0x100);
 486 S2IO_PARM_INT(mc_pause_threshold_q0q3, 187);
 487 S2IO_PARM_INT(mc_pause_threshold_q4q7, 187);
 488 S2IO_PARM_INT(shared_splits, 0);
 489 S2IO_PARM_INT(tmac_util_period, 5);
 490 S2IO_PARM_INT(rmac_util_period, 5);
 491 S2IO_PARM_INT(l3l4hdr_size, 128);
 492 /* 0 is no steering, 1 is Priority steering, 2 is Default steering */
 493 S2IO_PARM_INT(tx_steering_type, TX_DEFAULT_STEERING);
 494 /* Frequency of Rx desc syncs expressed as power of 2 */
 495 S2IO_PARM_INT(rxsync_frequency, 3);
 496 /* Interrupt type. Values can be 0(INTA), 2(MSI_X) */
 497 S2IO_PARM_INT(intr_type, 2);
 498 /* Large receive offload feature */
 499 static unsigned int lro_enable = 1;
 500 module_param_named(lro, lro_enable, uint, 0);
 501
 502 /* Max pkts to be aggregated by LRO at one time. If not specified,
 503  * aggregation happens until we hit max IP pkt size(64K)
 504  */
 505 S2IO_PARM_INT(lro_max_pkts, 0xFFFF);
 506 S2IO_PARM_INT(indicate_max_pkts, 0);
 507
 508 S2IO_PARM_INT(napi, 1);
 509 S2IO_PARM_INT(ufo, 0);
 510 S2IO_PARM_INT(vlan_tag_strip, NO_STRIP_IN_PROMISC);
 511
 512 static unsigned int tx_fifo_len[MAX_TX_FIFOS] =
 513 {DEFAULT_FIFO_0_LEN, [1 ...(MAX_TX_FIFOS - 1)] = DEFAULT_FIFO_1_7_LEN};
 514 static unsigned int rx_ring_sz[MAX_RX_RINGS] =
 515 {[0 ...(MAX_RX_RINGS - 1)] = SMALL_BLK_CNT};
 516 static unsigned int rts_frm_len[MAX_RX_RINGS] =
 517 {[0 ...(MAX_RX_RINGS - 1)] = 0 };
 518
 519 module_param_array(tx_fifo_len, uint, NULL, 0);
 520 module_param_array(rx_ring_sz, uint, NULL, 0);
 521 module_param_array(rts_frm_len, uint, NULL, 0);
 522
 523 /*
 524  * S2IO device table.
 525  * This table lists all the devices that this driver supports.
 526  */
 527 static DEFINE_PCI_DEVICE_TABLE(s2io_tbl) = {
 528         {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_WIN,
 529          PCI_ANY_ID, PCI_ANY_ID},
 530         {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_UNI,
 531          PCI_ANY_ID, PCI_ANY_ID},
 532         {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_WIN,
 533          PCI_ANY_ID, PCI_ANY_ID},
 534         {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_UNI,
 535          PCI_ANY_ID, PCI_ANY_ID},
 536         {0,}
 537 };
 538
 539 MODULE_DEVICE_TABLE(pci, s2io_tbl);
 540
 541 static struct pci_error_handlers s2io_err_handler = {
 542         .error_detected = s2io_io_error_detected,
 543         .slot_reset = s2io_io_slot_reset,
 544         .resume = s2io_io_resume,
 545 };
 546
 547 static struct pci_driver s2io_driver = {
 548         .name = "S2IO",
 549         .id_table = s2io_tbl,
 550         .probe = s2io_init_nic,
 551         .remove = __devexit_p(s2io_rem_nic),
 552         .err_handler = &s2io_err_handler,
 553 };
 554
 555 /* A simplifier macro used both by init and free shared_mem Fns(). */
 556 #define TXD_MEM_PAGE_CNT(len, per_each) ((len+per_each - 1) / per_each)
 557
 558 /* netqueue manipulation helper functions */
 559 static inline void s2io_stop_all_tx_queue(struct s2io_nic *sp)
 560 {
 561         if (!sp->config.multiq) {
 562                 int i;
 563
 564                 for (i = 0; i < sp->config.tx_fifo_num; i++)
 565                         sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_STOP;
 566         }
 567         netif_tx_stop_all_queues(sp->dev);
 568 }
 569
 570 static inline void s2io_stop_tx_queue(struct s2io_nic *sp, int fifo_no)
 571 {
 572         if (!sp->config.multiq)
 573                 sp->mac_control.fifos[fifo_no].queue_state =
 574                         FIFO_QUEUE_STOP;
 575
 576         netif_tx_stop_all_queues(sp->dev);
 577 }
 578
 579 static inline void s2io_start_all_tx_queue(struct s2io_nic *sp)
 580 {
 581         if (!sp->config.multiq) {
 582                 int i;
 583
 584                 for (i = 0; i < sp->config.tx_fifo_num; i++)
 585                         sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_START;
 586         }
 587         netif_tx_start_all_queues(sp->dev);
 588 }
 589
 590 static inline void s2io_start_tx_queue(struct s2io_nic *sp, int fifo_no)
 591 {
 592         if (!sp->config.multiq)
 593                 sp->mac_control.fifos[fifo_no].queue_state =
 594                         FIFO_QUEUE_START;
 595
 596         netif_tx_start_all_queues(sp->dev);
 597 }
 598
 599 static inline void s2io_wake_all_tx_queue(struct s2io_nic *sp)
 600 {
 601         if (!sp->config.multiq) {
 602                 int i;
 603
 604                 for (i = 0; i < sp->config.tx_fifo_num; i++)
 605                         sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_START;
 606         }
 607         netif_tx_wake_all_queues(sp->dev);
 608 }
 609
 610 static inline void s2io_wake_tx_queue(
 611         struct fifo_info *fifo, int cnt, u8 multiq)
 612 {
 613
 614         if (multiq) {
 615                 if (cnt && __netif_subqueue_stopped(fifo->dev, fifo->fifo_no))
 616                         netif_wake_subqueue(fifo->dev, fifo->fifo_no);
 617         } else if (cnt && (fifo->queue_state == FIFO_QUEUE_STOP)) {
 618                 if (netif_queue_stopped(fifo->dev)) {
 619                         fifo->queue_state = FIFO_QUEUE_START;
 620                         netif_wake_queue(fifo->dev);
 621                 }
 622         }
 623 }
 624
 625 /**
 626  * init_shared_mem - Allocation and Initialization of Memory
 627  * @nic: Device private variable.
 628  * Description: The function allocates all the memory areas shared
 629  * between the NIC and the driver. This includes Tx descriptors,
 630  * Rx descriptors and the statistics block.
 631  */
 632
 633 static int init_shared_mem(struct s2io_nic *nic)
 634 {
 635         u32 size;
 636         void *tmp_v_addr, *tmp_v_addr_next;
 637         dma_addr_t tmp_p_addr, tmp_p_addr_next;
 638         struct RxD_block *pre_rxd_blk = NULL;
 639         int i, j, blk_cnt;
 640         int lst_size, lst_per_page;
 641         struct net_device *dev = nic->dev;
 642         unsigned long tmp;
 643         struct buffAdd *ba;
 644         struct config_param *config = &nic->config;
 645         struct mac_info *mac_control = &nic->mac_control;
 646         unsigned long long mem_allocated = 0;
 647
 648         /* Allocation and initialization of TXDLs in FIFOs */
 649         size = 0;
 650         for (i = 0; i < config->tx_fifo_num; i++) {
 651                 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
 652
 653                 size += tx_cfg->fifo_len;
 654         }
 655         if (size > MAX_AVAILABLE_TXDS) {
 656                 DBG_PRINT(ERR_DBG,
 657                           "Too many TxDs requested: %d, max supported: %d\n",
 658                           size, MAX_AVAILABLE_TXDS);
 659                 return -EINVAL;
 660         }
 661
 662         size = 0;
 663         for (i = 0; i < config->tx_fifo_num; i++) {
 664                 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
 665
 666                 size = tx_cfg->fifo_len;
 667                 /*
 668                  * Legal values are from 2 to 8192
 669                  */
 670                 if (size < 2) {
 671                         DBG_PRINT(ERR_DBG, "Fifo %d: Invalid length (%d) - "
 672                                   "Valid lengths are 2 through 8192\n",
 673                                   i, size);
 674                         return -EINVAL;
 675                 }
 676         }
 677
 678         lst_size = (sizeof(struct TxD) * config->max_txds);
 679         lst_per_page = PAGE_SIZE / lst_size;
 680
 681         for (i = 0; i < config->tx_fifo_num; i++) {
 682                 struct fifo_info *fifo = &mac_control->fifos[i];
 683                 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
 684                 int fifo_len = tx_cfg->fifo_len;
 685                 int list_holder_size = fifo_len * sizeof(struct list_info_hold);
 686
 687                 fifo->list_info = kzalloc(list_holder_size, GFP_KERNEL);
 688                 if (!fifo->list_info) {
 689                         DBG_PRINT(INFO_DBG, "Malloc failed for list_info\n");
 690                         return -ENOMEM;
 691                 }
 692                 mem_allocated += list_holder_size;
 693         }
 694         for (i = 0; i < config->tx_fifo_num; i++) {
 695                 int page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
 696                                                 lst_per_page);
 697                 struct fifo_info *fifo = &mac_control->fifos[i];
 698                 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
 699
 700                 fifo->tx_curr_put_info.offset = 0;
 701                 fifo->tx_curr_put_info.fifo_len = tx_cfg->fifo_len - 1;
 702                 fifo->tx_curr_get_info.offset = 0;
 703                 fifo->tx_curr_get_info.fifo_len = tx_cfg->fifo_len - 1;
 704                 fifo->fifo_no = i;
 705                 fifo->nic = nic;
 706                 fifo->max_txds = MAX_SKB_FRAGS + 2;
 707                 fifo->dev = dev;
 708
 709                 for (j = 0; j < page_num; j++) {
 710                         int k = 0;
 711                         dma_addr_t tmp_p;
 712                         void *tmp_v;
 713                         tmp_v = pci_alloc_consistent(nic->pdev,
 714                                                      PAGE_SIZE, &tmp_p);
 715                         if (!tmp_v) {
 716                                 DBG_PRINT(INFO_DBG,
 717                                           "pci_alloc_consistent failed for TxDL\n");
 718                                 return -ENOMEM;
 719                         }
 720                         /* If we got a zero DMA address(can happen on
 721                          * certain platforms like PPC), reallocate.
 722                          * Store virtual address of page we don't want,
 723                          * to be freed later.
 724                          */
 725                         if (!tmp_p) {
 726                                 mac_control->zerodma_virt_addr = tmp_v;
 727                                 DBG_PRINT(INIT_DBG,
 728                                           "%s: Zero DMA address for TxDL. "
 729                                           "Virtual address %p\n",
 730                                           dev->name, tmp_v);
 731                                 tmp_v = pci_alloc_consistent(nic->pdev,
 732                                                              PAGE_SIZE, &tmp_p);
 733                                 if (!tmp_v) {
 734                                         DBG_PRINT(INFO_DBG,
 735                                                   "pci_alloc_consistent failed for TxDL\n");
 736                                         return -ENOMEM;
 737                                 }
 738                                 mem_allocated += PAGE_SIZE;
 739                         }
 740                         while (k < lst_per_page) {
 741                                 int l = (j * lst_per_page) + k;
 742                                 if (l == tx_cfg->fifo_len)
 743                                         break;
 744                                 fifo->list_info[l].list_virt_addr =
 745                                         tmp_v + (k * lst_size);
 746                                 fifo->list_info[l].list_phy_addr =
 747                                         tmp_p + (k * lst_size);
 748                                 k++;
 749                         }
 750                 }
 751         }
 752
 753         for (i = 0; i < config->tx_fifo_num; i++) {
 754                 struct fifo_info *fifo = &mac_control->fifos[i];
 755                 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
 756
 757                 size = tx_cfg->fifo_len;
 758                 fifo->ufo_in_band_v = kcalloc(size, sizeof(u64), GFP_KERNEL);
 759                 if (!fifo->ufo_in_band_v)
 760                         return -ENOMEM;
 761                 mem_allocated += (size * sizeof(u64));
 762         }
 763
 764         /* Allocation and initialization of RXDs in Rings */
 765         size = 0;
 766         for (i = 0; i < config->rx_ring_num; i++) {
 767                 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
 768                 struct ring_info *ring = &mac_control->rings[i];
 769
 770                 if (rx_cfg->num_rxd % (rxd_count[nic->rxd_mode] + 1)) {
 771                         DBG_PRINT(ERR_DBG, "%s: Ring%d RxD count is not a "
 772                                   "multiple of RxDs per Block\n",
 773                                   dev->name, i);
 774                         return FAILURE;
 775                 }
 776                 size += rx_cfg->num_rxd;
 777                 ring->block_count = rx_cfg->num_rxd /
 778                         (rxd_count[nic->rxd_mode] + 1);
 779                 ring->pkt_cnt = rx_cfg->num_rxd - ring->block_count;
 780         }
 781         if (nic->rxd_mode == RXD_MODE_1)
 782                 size = (size * (sizeof(struct RxD1)));
 783         else
 784                 size = (size * (sizeof(struct RxD3)));
 785
 786         for (i = 0; i < config->rx_ring_num; i++) {
 787                 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
 788                 struct ring_info *ring = &mac_control->rings[i];
 789
 790                 ring->rx_curr_get_info.block_index = 0;
 791                 ring->rx_curr_get_info.offset = 0;
 792                 ring->rx_curr_get_info.ring_len = rx_cfg->num_rxd - 1;
 793                 ring->rx_curr_put_info.block_index = 0;
 794                 ring->rx_curr_put_info.offset = 0;
 795                 ring->rx_curr_put_info.ring_len = rx_cfg->num_rxd - 1;
 796                 ring->nic = nic;
 797                 ring->ring_no = i;
 798
 799                 blk_cnt = rx_cfg->num_rxd / (rxd_count[nic->rxd_mode] + 1);
 800                 /*  Allocating all the Rx blocks */
 801                 for (j = 0; j < blk_cnt; j++) {
 802                         struct rx_block_info *rx_blocks;
 803                         int l;
 804
 805                         rx_blocks = &ring->rx_blocks[j];
 806                         size = SIZE_OF_BLOCK;   /* size is always page size */
 807                         tmp_v_addr = pci_alloc_consistent(nic->pdev, size,
 808                                                           &tmp_p_addr);
 809                         if (tmp_v_addr == NULL) {
 810                                 /*
 811                                  * In case of failure, free_shared_mem()
 812                                  * is called, which should free any
 813                                  * memory that was alloced till the
 814                                  * failure happened.
 815                                  */
 816                                 rx_blocks->block_virt_addr = tmp_v_addr;
 817                                 return -ENOMEM;
 818                         }
 819                         mem_allocated += size;
 820                         memset(tmp_v_addr, 0, size);
 821
 822                         size = sizeof(struct rxd_info) *
 823                                 rxd_count[nic->rxd_mode];
 824                         rx_blocks->block_virt_addr = tmp_v_addr;
 825                         rx_blocks->block_dma_addr = tmp_p_addr;
 826                         rx_blocks->rxds = kmalloc(size,  GFP_KERNEL);
 827                         if (!rx_blocks->rxds)
 828                                 return -ENOMEM;
 829                         mem_allocated += size;
 830                         for (l = 0; l < rxd_count[nic->rxd_mode]; l++) {
 831                                 rx_blocks->rxds[l].virt_addr =
 832                                         rx_blocks->block_virt_addr +
 833                                         (rxd_size[nic->rxd_mode] * l);
 834                                 rx_blocks->rxds[l].dma_addr =
 835                                         rx_blocks->block_dma_addr +
 836                                         (rxd_size[nic->rxd_mode] * l);
 837                         }
 838                 }
 839                 /* Interlinking all Rx Blocks */
 840                 for (j = 0; j < blk_cnt; j++) {
 841                         int next = (j + 1) % blk_cnt;
 842                         tmp_v_addr = ring->rx_blocks[j].block_virt_addr;
 843                         tmp_v_addr_next = ring->rx_blocks[next].block_virt_addr;
 844                         tmp_p_addr = ring->rx_blocks[j].block_dma_addr;
 845                         tmp_p_addr_next = ring->rx_blocks[next].block_dma_addr;
 846
 847                         pre_rxd_blk = (struct RxD_block *)tmp_v_addr;
 848                         pre_rxd_blk->reserved_2_pNext_RxD_block =
 849                                 (unsigned long)tmp_v_addr_next;
 850                         pre_rxd_blk->pNext_RxD_Blk_physical =
 851                                 (u64)tmp_p_addr_next;
 852                 }
 853         }
 854         if (nic->rxd_mode == RXD_MODE_3B) {
 855                 /*
 856                  * Allocation of Storages for buffer addresses in 2BUFF mode
 857                  * and the buffers as well.
 858                  */
 859                 for (i = 0; i < config->rx_ring_num; i++) {
 860                         struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
 861                         struct ring_info *ring = &mac_control->rings[i];
 862
 863                         blk_cnt = rx_cfg->num_rxd /
 864                                 (rxd_count[nic->rxd_mode] + 1);
 865                         size = sizeof(struct buffAdd *) * blk_cnt;
 866                         ring->ba = kmalloc(size, GFP_KERNEL);
 867                         if (!ring->ba)
 868                                 return -ENOMEM;
 869                         mem_allocated += size;
 870                         for (j = 0; j < blk_cnt; j++) {
 871                                 int k = 0;
 872
 873                                 size = sizeof(struct buffAdd) *
 874                                         (rxd_count[nic->rxd_mode] + 1);
 875                                 ring->ba[j] = kmalloc(size, GFP_KERNEL);
 876                                 if (!ring->ba[j])
 877                                         return -ENOMEM;
 878                                 mem_allocated += size;
 879                                 while (k != rxd_count[nic->rxd_mode]) {
 880                                         ba = &ring->ba[j][k];
 881                                         size = BUF0_LEN + ALIGN_SIZE;
 882                                         ba->ba_0_org = kmalloc(size, GFP_KERNEL);
 883                                         if (!ba->ba_0_org)
 884                                                 return -ENOMEM;
 885                                         mem_allocated += size;
 886                                         tmp = (unsigned long)ba->ba_0_org;
 887                                         tmp += ALIGN_SIZE;
 888                                         tmp &= ~((unsigned long)ALIGN_SIZE);
 889                                         ba->ba_0 = (void *)tmp;
 890
 891                                         size = BUF1_LEN + ALIGN_SIZE;
 892                                         ba->ba_1_org = kmalloc(size, GFP_KERNEL);
 893                                         if (!ba->ba_1_org)
 894                                                 return -ENOMEM;
 895                                         mem_allocated += size;
 896                                         tmp = (unsigned long)ba->ba_1_org;
 897                                         tmp += ALIGN_SIZE;
 898                                         tmp &= ~((unsigned long)ALIGN_SIZE);
 899                                         ba->ba_1 = (void *)tmp;
 900                                         k++;
 901                                 }
 902                         }
 903                 }
 904         }
 905
 906         /* Allocation and initialization of Statistics block */
 907         size = sizeof(struct stat_block);
 908         mac_control->stats_mem =
 909                 pci_alloc_consistent(nic->pdev, size,
 910                                      &mac_control->stats_mem_phy);
 911
 912         if (!mac_control->stats_mem) {
 913                 /*
 914                  * In case of failure, free_shared_mem() is called, which
 915                  * should free any memory that was alloced till the
 916                  * failure happened.
 917                  */
 918                 return -ENOMEM;
 919         }
 920         mem_allocated += size;
 921         mac_control->stats_mem_sz = size;
 922
 923         tmp_v_addr = mac_control->stats_mem;
 924         mac_control->stats_info = (struct stat_block *)tmp_v_addr;
 925         memset(tmp_v_addr, 0, size);
 926         DBG_PRINT(INIT_DBG, "%s: Ring Mem PHY: 0x%llx\n",
 927                 dev_name(&nic->pdev->dev), (unsigned long long)tmp_p_addr);
 928         mac_control->stats_info->sw_stat.mem_allocated += mem_allocated;
 929         return SUCCESS;
 930 }
 931
 932 /**
 933  * free_shared_mem - Free the allocated Memory
 934  * @nic:  Device private variable.
 935  * Description: This function is to free all memory locations allocated by
 936  * the init_shared_mem() function and return it to the kernel.
 937  */
 938
 939 static void free_shared_mem(struct s2io_nic *nic)
 940 {
 941         int i, j, blk_cnt, size;
 942         void *tmp_v_addr;
 943         dma_addr_t tmp_p_addr;
 944         int lst_size, lst_per_page;
 945         struct net_device *dev;
 946         int page_num = 0;
 947         struct config_param *config;
 948         struct mac_info *mac_control;
 949         struct stat_block *stats;
 950         struct swStat *swstats;
 951
 952         if (!nic)
 953                 return;
 954
 955         dev = nic->dev;
 956
 957         config = &nic->config;
 958         mac_control = &nic->mac_control;
 959         stats = mac_control->stats_info;
 960         swstats = &stats->sw_stat;
 961
 962         lst_size = sizeof(struct TxD) * config->max_txds;
 963         lst_per_page = PAGE_SIZE / lst_size;
 964
 965         for (i = 0; i < config->tx_fifo_num; i++) {
 966                 struct fifo_info *fifo = &mac_control->fifos[i];
 967                 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
 968
 969                 page_num = TXD_MEM_PAGE_CNT(tx_cfg->fifo_len, lst_per_page);
 970                 for (j = 0; j < page_num; j++) {
 971                         int mem_blks = (j * lst_per_page);
 972                         struct list_info_hold *fli;
 973
 974                         if (!fifo->list_info)
 975                                 return;
 976
 977                         fli = &fifo->list_info[mem_blks];
 978                         if (!fli->list_virt_addr)
 979                                 break;
 980                         pci_free_consistent(nic->pdev, PAGE_SIZE,
 981                                             fli->list_virt_addr,
 982                                             fli->list_phy_addr);
 983                         swstats->mem_freed += PAGE_SIZE;
 984                 }
 985                 /* If we got a zero DMA address during allocation,
 986                  * free the page now
 987                  */
 988                 if (mac_control->zerodma_virt_addr) {
 989                         pci_free_consistent(nic->pdev, PAGE_SIZE,
 990                                             mac_control->zerodma_virt_addr,
 991                                             (dma_addr_t)0);
 992                         DBG_PRINT(INIT_DBG,
 993                                   "%s: Freeing TxDL with zero DMA address. "
 994                                   "Virtual address %p\n",
 995                                   dev->name, mac_control->zerodma_virt_addr);
 996                         swstats->mem_freed += PAGE_SIZE;
 997                 }
 998                 kfree(fifo->list_info);
 999                 swstats->mem_freed += tx_cfg->fifo_len *
1000                         sizeof(struct list_info_hold);
1001         }
1002
1003         size = SIZE_OF_BLOCK;
1004         for (i = 0; i < config->rx_ring_num; i++) {
1005                 struct ring_info *ring = &mac_control->rings[i];
1006
1007                 blk_cnt = ring->block_count;
1008                 for (j = 0; j < blk_cnt; j++) {
1009                         tmp_v_addr = ring->rx_blocks[j].block_virt_addr;
1010                         tmp_p_addr = ring->rx_blocks[j].block_dma_addr;
1011                         if (tmp_v_addr == NULL)
1012                                 break;
1013                         pci_free_consistent(nic->pdev, size,
1014                                             tmp_v_addr, tmp_p_addr);
1015                         swstats->mem_freed += size;
1016                         kfree(ring->rx_blocks[j].rxds);
1017                         swstats->mem_freed += sizeof(struct rxd_info) *
1018                                 rxd_count[nic->rxd_mode];
1019                 }
1020         }
1021
1022         if (nic->rxd_mode == RXD_MODE_3B) {
1023                 /* Freeing buffer storage addresses in 2BUFF mode. */
1024                 for (i = 0; i < config->rx_ring_num; i++) {
1025                         struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
1026                         struct ring_info *ring = &mac_control->rings[i];
1027
1028                         blk_cnt = rx_cfg->num_rxd /
1029                                 (rxd_count[nic->rxd_mode] + 1);
1030                         for (j = 0; j < blk_cnt; j++) {
1031                                 int k = 0;
1032                                 if (!ring->ba[j])
1033                                         continue;
1034                                 while (k != rxd_count[nic->rxd_mode]) {
1035                                         struct buffAdd *ba = &ring->ba[j][k];
1036                                         kfree(ba->ba_0_org);
1037                                         swstats->mem_freed +=
1038                                                 BUF0_LEN + ALIGN_SIZE;
1039                                         kfree(ba->ba_1_org);
1040                                         swstats->mem_freed +=
1041                                                 BUF1_LEN + ALIGN_SIZE;
1042                                         k++;
1043                                 }
1044                                 kfree(ring->ba[j]);
1045                                 swstats->mem_freed += sizeof(struct buffAdd) *
1046                                         (rxd_count[nic->rxd_mode] + 1);
1047                         }
1048                         kfree(ring->ba);
1049                         swstats->mem_freed += sizeof(struct buffAdd *) *
1050                                 blk_cnt;
1051                 }
1052         }
1053
1054         for (i = 0; i < nic->config.tx_fifo_num; i++) {
1055                 struct fifo_info *fifo = &mac_control->fifos[i];
1056                 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
1057
1058                 if (fifo->ufo_in_band_v) {
1059                         swstats->mem_freed += tx_cfg->fifo_len *
1060                                 sizeof(u64);
1061                         kfree(fifo->ufo_in_band_v);
1062                 }
1063         }
1064
1065         if (mac_control->stats_mem) {
1066                 swstats->mem_freed += mac_control->stats_mem_sz;
1067                 pci_free_consistent(nic->pdev,
1068                                     mac_control->stats_mem_sz,
1069                                     mac_control->stats_mem,
1070                                     mac_control->stats_mem_phy);
1071         }
1072 }
1073
1074 /**
1075  * s2io_verify_pci_mode -
1076  */
1077
1078 static int s2io_verify_pci_mode(struct s2io_nic *nic)
1079 {
1080         struct XENA_dev_config __iomem *bar0 = nic->bar0;
1081         register u64 val64 = 0;
1082         int     mode;
1083
1084         val64 = readq(&bar0->pci_mode);
1085         mode = (u8)GET_PCI_MODE(val64);
1086
1087         if (val64 & PCI_MODE_UNKNOWN_MODE)
1088                 return -1;      /* Unknown PCI mode */
1089         return mode;
1090 }
1091
1092 #define NEC_VENID   0x1033
1093 #define NEC_DEVID   0x0125
1094 static int s2io_on_nec_bridge(struct pci_dev *s2io_pdev)
1095 {
1096         struct pci_dev *tdev = NULL;
1097         while ((tdev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, tdev)) != NULL) {
1098                 if (tdev->vendor == NEC_VENID && tdev->device == NEC_DEVID) {
1099                         if (tdev->bus == s2io_pdev->bus->parent) {
1100                                 pci_dev_put(tdev);
1101                                 return 1;
1102                         }
1103                 }
1104         }
1105         return 0;
1106 }
1107
1108 static int bus_speed[8] = {33, 133, 133, 200, 266, 133, 200, 266};
1109 /**
1110  * s2io_print_pci_mode -
1111  */
1112 static int s2io_print_pci_mode(struct s2io_nic *nic)
1113 {
1114         struct XENA_dev_config __iomem *bar0 = nic->bar0;
1115         register u64 val64 = 0;
1116         int     mode;
1117         struct config_param *config = &nic->config;
1118         const char *pcimode;
1119
1120         val64 = readq(&bar0->pci_mode);
1121         mode = (u8)GET_PCI_MODE(val64);
1122
1123         if (val64 & PCI_MODE_UNKNOWN_MODE)
1124                 return -1;      /* Unknown PCI mode */
1125
1126         config->bus_speed = bus_speed[mode];
1127
1128         if (s2io_on_nec_bridge(nic->pdev)) {
1129                 DBG_PRINT(ERR_DBG, "%s: Device is on PCI-E bus\n",
1130                           nic->dev->name);
1131                 return mode;
1132         }
1133
1134         switch (mode) {
1135         case PCI_MODE_PCI_33:
1136                 pcimode = "33MHz PCI bus";
1137                 break;
1138         case PCI_MODE_PCI_66:
1139                 pcimode = "66MHz PCI bus";
1140                 break;
1141         case PCI_MODE_PCIX_M1_66:
1142                 pcimode = "66MHz PCIX(M1) bus";
1143                 break;
1144         case PCI_MODE_PCIX_M1_100:
1145                 pcimode = "100MHz PCIX(M1) bus";
1146                 break;
1147         case PCI_MODE_PCIX_M1_133:
1148                 pcimode = "133MHz PCIX(M1) bus";
1149                 break;
1150         case PCI_MODE_PCIX_M2_66:
1151                 pcimode = "133MHz PCIX(M2) bus";
1152                 break;
1153         case PCI_MODE_PCIX_M2_100:
1154                 pcimode = "200MHz PCIX(M2) bus";
1155                 break;
1156         case PCI_MODE_PCIX_M2_133:
1157                 pcimode = "266MHz PCIX(M2) bus";
1158                 break;
1159         default:
1160                 pcimode = "unsupported bus!";
1161                 mode = -1;
1162         }
1163
1164         DBG_PRINT(ERR_DBG, "%s: Device is on %d bit %s\n",
1165                   nic->dev->name, val64 & PCI_MODE_32_BITS ? 32 : 64, pcimode);
1166
1167         return mode;
1168 }
1169
1170 /**
1171  *  init_tti - Initialization transmit traffic interrupt scheme
1172  *  @nic: device private variable
1173  *  @link: link status (UP/DOWN) used to enable/disable continuous
1174  *  transmit interrupts
1175  *  Description: The function configures transmit traffic interrupts
1176  *  Return Value:  SUCCESS on success and
1177  *  '-1' on failure
1178  */
1179
1180 static int init_tti(struct s2io_nic *nic, int link)
1181 {
1182         struct XENA_dev_config __iomem *bar0 = nic->bar0;
1183         register u64 val64 = 0;
1184         int i;
1185         struct config_param *config = &nic->config;
1186
1187         for (i = 0; i < config->tx_fifo_num; i++) {
1188                 /*
1189                  * TTI Initialization. Default Tx timer gets us about
1190                  * 250 interrupts per sec. Continuous interrupts are enabled
1191                  * by default.
1192                  */
1193                 if (nic->device_type == XFRAME_II_DEVICE) {
1194                         int count = (nic->config.bus_speed * 125)/2;
1195                         val64 = TTI_DATA1_MEM_TX_TIMER_VAL(count);
1196                 } else
1197                         val64 = TTI_DATA1_MEM_TX_TIMER_VAL(0x2078);
1198
1199                 val64 |= TTI_DATA1_MEM_TX_URNG_A(0xA) |
1200                         TTI_DATA1_MEM_TX_URNG_B(0x10) |
1201                         TTI_DATA1_MEM_TX_URNG_C(0x30) |
1202                         TTI_DATA1_MEM_TX_TIMER_AC_EN;
1203                 if (i == 0)
1204                         if (use_continuous_tx_intrs && (link == LINK_UP))
1205                                 val64 |= TTI_DATA1_MEM_TX_TIMER_CI_EN;
1206                 writeq(val64, &bar0->tti_data1_mem);
1207
1208                 if (nic->config.intr_type == MSI_X) {
1209                         val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) |
1210                                 TTI_DATA2_MEM_TX_UFC_B(0x100) |
1211                                 TTI_DATA2_MEM_TX_UFC_C(0x200) |
1212                                 TTI_DATA2_MEM_TX_UFC_D(0x300);
1213                 } else {
1214                         if ((nic->config.tx_steering_type ==
1215                              TX_DEFAULT_STEERING) &&
1216                             (config->tx_fifo_num > 1) &&
1217                             (i >= nic->udp_fifo_idx) &&
1218                             (i < (nic->udp_fifo_idx +
1219                                   nic->total_udp_fifos)))
1220                                 val64 = TTI_DATA2_MEM_TX_UFC_A(0x50) |
1221                                         TTI_DATA2_MEM_TX_UFC_B(0x80) |
1222                                         TTI_DATA2_MEM_TX_UFC_C(0x100) |
1223                                         TTI_DATA2_MEM_TX_UFC_D(0x120);
1224                         else
1225                                 val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) |
1226                                         TTI_DATA2_MEM_TX_UFC_B(0x20) |
1227                                         TTI_DATA2_MEM_TX_UFC_C(0x40) |
1228                                         TTI_DATA2_MEM_TX_UFC_D(0x80);
1229                 }
1230
1231                 writeq(val64, &bar0->tti_data2_mem);
1232
1233                 val64 = TTI_CMD_MEM_WE |
1234                         TTI_CMD_MEM_STROBE_NEW_CMD |
1235                         TTI_CMD_MEM_OFFSET(i);
1236                 writeq(val64, &bar0->tti_command_mem);
1237
1238                 if (wait_for_cmd_complete(&bar0->tti_command_mem,
1239                                           TTI_CMD_MEM_STROBE_NEW_CMD,
1240                                           S2IO_BIT_RESET) != SUCCESS)
1241                         return FAILURE;
1242         }
1243
1244         return SUCCESS;
1245 }
1246
1247 /**
1248  *  init_nic - Initialization of hardware
1249  *  @nic: device private variable
1250  *  Description: The function sequentially configures every block
1251  *  of the H/W from their reset values.
1252  *  Return Value:  SUCCESS on success and
1253  *  '-1' on failure (endian settings incorrect).
1254  */
1255
1256 static int init_nic(struct s2io_nic *nic)
1257 {
1258         struct XENA_dev_config __iomem *bar0 = nic->bar0;
1259         struct net_device *dev = nic->dev;
1260         register u64 val64 = 0;
1261         void __iomem *add;
1262         u32 time;
1263         int i, j;
1264         int dtx_cnt = 0;
1265         unsigned long long mem_share;
1266         int mem_size;
1267         struct config_param *config = &nic->config;
1268         struct mac_info *mac_control = &nic->mac_control;
1269
1270         /* to set the swapper controle on the card */
1271         if (s2io_set_swapper(nic)) {
1272                 DBG_PRINT(ERR_DBG, "ERROR: Setting Swapper failed\n");
1273                 return -EIO;
1274         }
1275
1276         /*
1277          * Herc requires EOI to be removed from reset before XGXS, so..
1278          */
1279         if (nic->device_type & XFRAME_II_DEVICE) {
1280                 val64 = 0xA500000000ULL;
1281                 writeq(val64, &bar0->sw_reset);
1282                 msleep(500);
1283                 val64 = readq(&bar0->sw_reset);
1284         }
1285
1286         /* Remove XGXS from reset state */
1287         val64 = 0;
1288         writeq(val64, &bar0->sw_reset);
1289         msleep(500);
1290         val64 = readq(&bar0->sw_reset);
1291
1292         /* Ensure that it's safe to access registers by checking
1293          * RIC_RUNNING bit is reset. Check is valid only for XframeII.
1294          */
1295         if (nic->device_type == XFRAME_II_DEVICE) {
1296                 for (i = 0; i < 50; i++) {
1297                         val64 = readq(&bar0->adapter_status);
1298                         if (!(val64 & ADAPTER_STATUS_RIC_RUNNING))
1299                                 break;
1300                         msleep(10);
1301                 }
1302                 if (i == 50)
1303                         return -ENODEV;
1304         }
1305
1306         /*  Enable Receiving broadcasts */
1307         add = &bar0->mac_cfg;
1308         val64 = readq(&bar0->mac_cfg);
1309         val64 |= MAC_RMAC_BCAST_ENABLE;
1310         writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1311         writel((u32)val64, add);
1312         writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1313         writel((u32) (val64 >> 32), (add + 4));
1314
1315         /* Read registers in all blocks */
1316         val64 = readq(&bar0->mac_int_mask);
1317         val64 = readq(&bar0->mc_int_mask);
1318         val64 = readq(&bar0->xgxs_int_mask);
1319
1320         /*  Set MTU */
1321         val64 = dev->mtu;
1322         writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
1323
1324         if (nic->device_type & XFRAME_II_DEVICE) {
1325                 while (herc_act_dtx_cfg[dtx_cnt] != END_SIGN) {
1326                         SPECIAL_REG_WRITE(herc_act_dtx_cfg[dtx_cnt],
1327                                           &bar0->dtx_control, UF);
1328                         if (dtx_cnt & 0x1)
1329                                 msleep(1); /* Necessary!! */
1330                         dtx_cnt++;
1331                 }
1332         } else {
1333                 while (xena_dtx_cfg[dtx_cnt] != END_SIGN) {
1334                         SPECIAL_REG_WRITE(xena_dtx_cfg[dtx_cnt],
1335                                           &bar0->dtx_control, UF);
1336                         val64 = readq(&bar0->dtx_control);
1337                         dtx_cnt++;
1338                 }
1339         }
1340
1341         /*  Tx DMA Initialization */
1342         val64 = 0;
1343         writeq(val64, &bar0->tx_fifo_partition_0);
1344         writeq(val64, &bar0->tx_fifo_partition_1);
1345         writeq(val64, &bar0->tx_fifo_partition_2);
1346         writeq(val64, &bar0->tx_fifo_partition_3);
1347
1348         for (i = 0, j = 0; i < config->tx_fifo_num; i++) {
1349                 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
1350
1351                 val64 |= vBIT(tx_cfg->fifo_len - 1, ((j * 32) + 19), 13) |
1352                         vBIT(tx_cfg->fifo_priority, ((j * 32) + 5), 3);
1353
1354                 if (i == (config->tx_fifo_num - 1)) {
1355                         if (i % 2 == 0)
1356                                 i++;
1357                 }
1358
1359                 switch (i) {
1360                 case 1:
1361                         writeq(val64, &bar0->tx_fifo_partition_0);
1362                         val64 = 0;
1363                         j = 0;
1364                         break;
1365                 case 3:
1366                         writeq(val64, &bar0->tx_fifo_partition_1);
1367                         val64 = 0;
1368                         j = 0;
1369                         break;
1370                 case 5:
1371                         writeq(val64, &bar0->tx_fifo_partition_2);
1372                         val64 = 0;
1373                         j = 0;
1374                         break;
1375                 case 7:
1376                         writeq(val64, &bar0->tx_fifo_partition_3);
1377                         val64 = 0;
1378                         j = 0;
1379                         break;
1380                 default:
1381                         j++;
1382                         break;
1383                 }
1384         }
1385
1386         /*
1387          * Disable 4 PCCs for Xena1, 2 and 3 as per H/W bug
1388          * SXE-008 TRANSMIT DMA ARBITRATION ISSUE.
1389          */
1390         if ((nic->device_type == XFRAME_I_DEVICE) && (nic->pdev->revision < 4))
1391                 writeq(PCC_ENABLE_FOUR, &bar0->pcc_enable);
1392
1393         val64 = readq(&bar0->tx_fifo_partition_0);
1394         DBG_PRINT(INIT_DBG, "Fifo partition at: 0x%p is: 0x%llx\n",
1395                   &bar0->tx_fifo_partition_0, (unsigned long long)val64);
1396
1397         /*
1398          * Initialization of Tx_PA_CONFIG register to ignore packet
1399          * integrity checking.
1400          */
1401         val64 = readq(&bar0->tx_pa_cfg);
1402         val64 |= TX_PA_CFG_IGNORE_FRM_ERR |
1403                 TX_PA_CFG_IGNORE_SNAP_OUI |
1404                 TX_PA_CFG_IGNORE_LLC_CTRL |
1405                 TX_PA_CFG_IGNORE_L2_ERR;
1406         writeq(val64, &bar0->tx_pa_cfg);
1407
1408         /* Rx DMA intialization. */
1409         val64 = 0;
1410         for (i = 0; i < config->rx_ring_num; i++) {
1411                 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
1412
1413                 val64 |= vBIT(rx_cfg->ring_priority, (5 + (i * 8)), 3);
1414         }
1415         writeq(val64, &bar0->rx_queue_priority);
1416
1417         /*
1418          * Allocating equal share of memory to all the
1419          * configured Rings.
1420          */
1421         val64 = 0;
1422         if (nic->device_type & XFRAME_II_DEVICE)
1423                 mem_size = 32;
1424         else
1425                 mem_size = 64;
1426
1427         for (i = 0; i < config->rx_ring_num; i++) {
1428                 switch (i) {
1429                 case 0:
1430                         mem_share = (mem_size / config->rx_ring_num +
1431                                      mem_size % config->rx_ring_num);
1432                         val64 |= RX_QUEUE_CFG_Q0_SZ(mem_share);
1433                         continue;
1434                 case 1:
1435                         mem_share = (mem_size / config->rx_ring_num);
1436                         val64 |= RX_QUEUE_CFG_Q1_SZ(mem_share);
1437                         continue;
1438                 case 2:
1439                         mem_share = (mem_size / config->rx_ring_num);
1440                         val64 |= RX_QUEUE_CFG_Q2_SZ(mem_share);
1441                         continue;
1442                 case 3:
1443                         mem_share = (mem_size / config->rx_ring_num);
1444                         val64 |= RX_QUEUE_CFG_Q3_SZ(mem_share);
1445                         continue;
1446                 case 4:
1447                         mem_share = (mem_size / config->rx_ring_num);
1448                         val64 |= RX_QUEUE_CFG_Q4_SZ(mem_share);
1449                         continue;
1450                 case 5:
1451                         mem_share = (mem_size / config->rx_ring_num);
1452                         val64 |= RX_QUEUE_CFG_Q5_SZ(mem_share);
1453                         continue;
1454                 case 6:
1455                         mem_share = (mem_size / config->rx_ring_num);
1456                         val64 |= RX_QUEUE_CFG_Q6_SZ(mem_share);
1457                         continue;
1458                 case 7:
1459                         mem_share = (mem_size / config->rx_ring_num);
1460                         val64 |= RX_QUEUE_CFG_Q7_SZ(mem_share);
1461                         continue;
1462                 }
1463         }
1464         writeq(val64, &bar0->rx_queue_cfg);
1465
1466         /*
1467          * Filling Tx round robin registers
1468          * as per the number of FIFOs for equal scheduling priority
1469          */
1470         switch (config->tx_fifo_num) {
1471         case 1:
1472                 val64 = 0x0;
1473                 writeq(val64, &bar0->tx_w_round_robin_0);
1474                 writeq(val64, &bar0->tx_w_round_robin_1);
1475                 writeq(val64, &bar0->tx_w_round_robin_2);
1476                 writeq(val64, &bar0->tx_w_round_robin_3);
1477                 writeq(val64, &bar0->tx_w_round_robin_4);
1478                 break;
1479         case 2:
1480                 val64 = 0x0001000100010001ULL;
1481                 writeq(val64, &bar0->tx_w_round_robin_0);
1482                 writeq(val64, &bar0->tx_w_round_robin_1);
1483                 writeq(val64, &bar0->tx_w_round_robin_2);
1484                 writeq(val64, &bar0->tx_w_round_robin_3);
1485                 val64 = 0x0001000100000000ULL;
1486                 writeq(val64, &bar0->tx_w_round_robin_4);
1487                 break;
1488         case 3:
1489                 val64 = 0x0001020001020001ULL;
1490                 writeq(val64, &bar0->tx_w_round_robin_0);
1491                 val64 = 0x0200010200010200ULL;
1492                 writeq(val64, &bar0->tx_w_round_robin_1);
1493                 val64 = 0x0102000102000102ULL;
1494                 writeq(val64, &bar0->tx_w_round_robin_2);
1495                 val64 = 0x0001020001020001ULL;
1496                 writeq(val64, &bar0->tx_w_round_robin_3);
1497                 val64 = 0x0200010200000000ULL;
1498                 writeq(val64, &bar0->tx_w_round_robin_4);
1499                 break;
1500         case 4:
1501                 val64 = 0x0001020300010203ULL;
1502                 writeq(val64, &bar0->tx_w_round_robin_0);
1503                 writeq(val64, &bar0->tx_w_round_robin_1);
1504                 writeq(val64, &bar0->tx_w_round_robin_2);
1505                 writeq(val64, &bar0->tx_w_round_robin_3);
1506                 val64 = 0x0001020300000000ULL;
1507                 writeq(val64, &bar0->tx_w_round_robin_4);
1508                 break;
1509         case 5:
1510                 val64 = 0x0001020304000102ULL;
1511                 writeq(val64, &bar0->tx_w_round_robin_0);
1512                 val64 = 0x0304000102030400ULL;
1513                 writeq(val64, &bar0->tx_w_round_robin_1);
1514                 val64 = 0x0102030400010203ULL;
1515                 writeq(val64, &bar0->tx_w_round_robin_2);
1516                 val64 = 0x0400010203040001ULL;
1517                 writeq(val64, &bar0->tx_w_round_robin_3);
1518                 val64 = 0x0203040000000000ULL;
1519                 writeq(val64, &bar0->tx_w_round_robin_4);
1520                 break;
1521         case 6:
1522                 val64 = 0x0001020304050001ULL;
1523                 writeq(val64, &bar0->tx_w_round_robin_0);
1524                 val64 = 0x0203040500010203ULL;
1525                 writeq(val64, &bar0->tx_w_round_robin_1);
1526                 val64 = 0x0405000102030405ULL;
1527                 writeq(val64, &bar0->tx_w_round_robin_2);
1528                 val64 = 0x0001020304050001ULL;
1529                 writeq(val64, &bar0->tx_w_round_robin_3);
1530                 val64 = 0x0203040500000000ULL;
1531                 writeq(val64, &bar0->tx_w_round_robin_4);
1532                 break;
1533         case 7:
1534                 val64 = 0x0001020304050600ULL;
1535                 writeq(val64, &bar0->tx_w_round_robin_0);
1536                 val64 = 0x0102030405060001ULL;
1537                 writeq(val64, &bar0->tx_w_round_robin_1);
1538                 val64 = 0x0203040506000102ULL;
1539                 writeq(val64, &bar0->tx_w_round_robin_2);
1540                 val64 = 0x0304050600010203ULL;
1541                 writeq(val64, &bar0->tx_w_round_robin_3);
1542                 val64 = 0x0405060000000000ULL;
1543                 writeq(val64, &bar0->tx_w_round_robin_4);
1544                 break;
1545         case 8:
1546                 val64 = 0x0001020304050607ULL;
1547                 writeq(val64, &bar0->tx_w_round_robin_0);
1548                 writeq(val64, &bar0->tx_w_round_robin_1);
1549                 writeq(val64, &bar0->tx_w_round_robin_2);
1550                 writeq(val64, &bar0->tx_w_round_robin_3);
1551                 val64 = 0x0001020300000000ULL;
1552                 writeq(val64, &bar0->tx_w_round_robin_4);
1553                 break;
1554         }
1555
1556         /* Enable all configured Tx FIFO partitions */
1557         val64 = readq(&bar0->tx_fifo_partition_0);
1558         val64 |= (TX_FIFO_PARTITION_EN);
1559         writeq(val64, &bar0->tx_fifo_partition_0);
1560
1561         /* Filling the Rx round robin registers as per the
1562          * number of Rings and steering based on QoS with
1563          * equal priority.
1564          */
1565         switch (config->rx_ring_num) {
1566         case 1:
1567                 val64 = 0x0;
1568                 writeq(val64, &bar0->rx_w_round_robin_0);
1569                 writeq(val64, &bar0->rx_w_round_robin_1);
1570                 writeq(val64, &bar0->rx_w_round_robin_2);
1571                 writeq(val64, &bar0->rx_w_round_robin_3);
1572                 writeq(val64, &bar0->rx_w_round_robin_4);
1573
1574                 val64 = 0x8080808080808080ULL;
1575                 writeq(val64, &bar0->rts_qos_steering);
1576                 break;
1577         case 2:
1578                 val64 = 0x0001000100010001ULL;
1579                 writeq(val64, &bar0->rx_w_round_robin_0);
1580                 writeq(val64, &bar0->rx_w_round_robin_1);
1581                 writeq(val64, &bar0->rx_w_round_robin_2);
1582                 writeq(val64, &bar0->rx_w_round_robin_3);
1583                 val64 = 0x0001000100000000ULL;
1584                 writeq(val64, &bar0->rx_w_round_robin_4);
1585
1586                 val64 = 0x8080808040404040ULL;
1587                 writeq(val64, &bar0->rts_qos_steering);
1588                 break;
1589         case 3:
1590                 val64 = 0x0001020001020001ULL;
1591                 writeq(val64, &bar0->rx_w_round_robin_0);
1592                 val64 = 0x0200010200010200ULL;
1593                 writeq(val64, &bar0->rx_w_round_robin_1);
1594                 val64 = 0x0102000102000102ULL;
1595                 writeq(val64, &bar0->rx_w_round_robin_2);
1596                 val64 = 0x0001020001020001ULL;
1597                 writeq(val64, &bar0->rx_w_round_robin_3);
1598                 val64 = 0x0200010200000000ULL;
1599                 writeq(val64, &bar0->rx_w_round_robin_4);
1600
1601                 val64 = 0x8080804040402020ULL;
1602                 writeq(val64, &bar0->rts_qos_steering);
1603                 break;
1604         case 4:
1605                 val64 = 0x0001020300010203ULL;
1606                 writeq(val64, &bar0->rx_w_round_robin_0);
1607                 writeq(val64, &bar0->rx_w_round_robin_1);
1608                 writeq(val64, &bar0->rx_w_round_robin_2);
1609                 writeq(val64, &bar0->rx_w_round_robin_3);
1610                 val64 = 0x0001020300000000ULL;
1611                 writeq(val64, &bar0->rx_w_round_robin_4);
1612
1613                 val64 = 0x8080404020201010ULL;
1614                 writeq(val64, &bar0->rts_qos_steering);
1615                 break;
1616         case 5:
1617                 val64 = 0x0001020304000102ULL;
1618                 writeq(val64, &bar0->rx_w_round_robin_0);
1619                 val64 = 0x0304000102030400ULL;
1620                 writeq(val64, &bar0->rx_w_round_robin_1);
1621                 val64 = 0x0102030400010203ULL;
1622                 writeq(val64, &bar0->rx_w_round_robin_2);
1623                 val64 = 0x0400010203040001ULL;
1624                 writeq(val64, &bar0->rx_w_round_robin_3);
1625                 val64 = 0x0203040000000000ULL;
1626                 writeq(val64, &bar0->rx_w_round_robin_4);
1627
1628                 val64 = 0x8080404020201008ULL;
1629                 writeq(val64, &bar0->rts_qos_steering);
1630                 break;
1631         case 6:
1632                 val64 = 0x0001020304050001ULL;
1633                 writeq(val64, &bar0->rx_w_round_robin_0);
1634                 val64 = 0x0203040500010203ULL;
1635                 writeq(val64, &bar0->rx_w_round_robin_1);
1636                 val64 = 0x0405000102030405ULL;
1637                 writeq(val64, &bar0->rx_w_round_robin_2);
1638                 val64 = 0x0001020304050001ULL;
1639                 writeq(val64, &bar0->rx_w_round_robin_3);
1640                 val64 = 0x0203040500000000ULL;
1641                 writeq(val64, &bar0->rx_w_round_robin_4);
1642
1643                 val64 = 0x8080404020100804ULL;
1644                 writeq(val64, &bar0->rts_qos_steering);
1645                 break;
1646         case 7:
1647                 val64 = 0x0001020304050600ULL;
1648                 writeq(val64, &bar0->rx_w_round_robin_0);
1649                 val64 = 0x0102030405060001ULL;
1650                 writeq(val64, &bar0->rx_w_round_robin_1);
1651                 val64 = 0x0203040506000102ULL;
1652                 writeq(val64, &bar0->rx_w_round_robin_2);
1653                 val64 = 0x0304050600010203ULL;
1654                 writeq(val64, &bar0->rx_w_round_robin_3);
1655                 val64 = 0x0405060000000000ULL;
1656                 writeq(val64, &bar0->rx_w_round_robin_4);
1657
1658                 val64 = 0x8080402010080402ULL;
1659                 writeq(val64, &bar0->rts_qos_steering);
1660                 break;
1661         case 8:
1662                 val64 = 0x0001020304050607ULL;
1663                 writeq(val64, &bar0->rx_w_round_robin_0);
1664                 writeq(val64, &bar0->rx_w_round_robin_1);
1665                 writeq(val64, &bar0->rx_w_round_robin_2);
1666                 writeq(val64, &bar0->rx_w_round_robin_3);
1667                 val64 = 0x0001020300000000ULL;
1668                 writeq(val64, &bar0->rx_w_round_robin_4);
1669
1670                 val64 = 0x8040201008040201ULL;
1671                 writeq(val64, &bar0->rts_qos_steering);
1672                 break;
1673         }
1674
1675         /* UDP Fix */
1676         val64 = 0;
1677         for (i = 0; i < 8; i++)
1678                 writeq(val64, &bar0->rts_frm_len_n[i]);
1679
1680         /* Set the default rts frame length for the rings configured */
1681         val64 = MAC_RTS_FRM_LEN_SET(dev->mtu+22);
1682         for (i = 0 ; i < config->rx_ring_num ; i++)
1683                 writeq(val64, &bar0->rts_frm_len_n[i]);
1684
1685         /* Set the frame length for the configured rings
1686          * desired by the user
1687          */
1688         for (i = 0; i < config->rx_ring_num; i++) {
1689                 /* If rts_frm_len[i] == 0 then it is assumed that user not
1690                  * specified frame length steering.
1691                  * If the user provides the frame length then program
1692                  * the rts_frm_len register for those values or else
1693                  * leave it as it is.
1694                  */
1695                 if (rts_frm_len[i] != 0) {
1696                         writeq(MAC_RTS_FRM_LEN_SET(rts_frm_len[i]),
1697                                &bar0->rts_frm_len_n[i]);
1698                 }
1699         }
1700
1701         /* Disable differentiated services steering logic */
1702         for (i = 0; i < 64; i++) {
1703                 if (rts_ds_steer(nic, i, 0) == FAILURE) {
1704                         DBG_PRINT(ERR_DBG,
1705                                   "%s: rts_ds_steer failed on codepoint %d\n",
1706                                   dev->name, i);
1707                         return -ENODEV;
1708                 }
1709         }
1710
1711         /* Program statistics memory */
1712         writeq(mac_control->stats_mem_phy, &bar0->stat_addr);
1713
1714         if (nic->device_type == XFRAME_II_DEVICE) {
1715                 val64 = STAT_BC(0x320);
1716                 writeq(val64, &bar0->stat_byte_cnt);
1717         }
1718
1719         /*
1720          * Initializing the sampling rate for the device to calculate the
1721          * bandwidth utilization.
1722          */
1723         val64 = MAC_TX_LINK_UTIL_VAL(tmac_util_period) |
1724                 MAC_RX_LINK_UTIL_VAL(rmac_util_period);
1725         writeq(val64, &bar0->mac_link_util);
1726
1727         /*
1728          * Initializing the Transmit and Receive Traffic Interrupt
1729          * Scheme.
1730          */
1731
1732         /* Initialize TTI */
1733         if (SUCCESS != init_tti(nic, nic->last_link_state))
1734                 return -ENODEV;
1735
1736         /* RTI Initialization */
1737         if (nic->device_type == XFRAME_II_DEVICE) {
1738                 /*
1739                  * Programmed to generate Apprx 500 Intrs per
1740                  * second
1741                  */
1742                 int count = (nic->config.bus_speed * 125)/4;
1743                 val64 = RTI_DATA1_MEM_RX_TIMER_VAL(count);
1744         } else
1745                 val64 = RTI_DATA1_MEM_RX_TIMER_VAL(0xFFF);
1746         val64 |= RTI_DATA1_MEM_RX_URNG_A(0xA) |
1747                 RTI_DATA1_MEM_RX_URNG_B(0x10) |
1748                 RTI_DATA1_MEM_RX_URNG_C(0x30) |
1749                 RTI_DATA1_MEM_RX_TIMER_AC_EN;
1750
1751         writeq(val64, &bar0->rti_data1_mem);
1752
1753         val64 = RTI_DATA2_MEM_RX_UFC_A(0x1) |
1754                 RTI_DATA2_MEM_RX_UFC_B(0x2) ;
1755         if (nic->config.intr_type == MSI_X)
1756                 val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x20) |
1757                           RTI_DATA2_MEM_RX_UFC_D(0x40));
1758         else
1759                 val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x40) |
1760                           RTI_DATA2_MEM_RX_UFC_D(0x80));
1761         writeq(val64, &bar0->rti_data2_mem);
1762
1763         for (i = 0; i < config->rx_ring_num; i++) {
1764                 val64 = RTI_CMD_MEM_WE |
1765                         RTI_CMD_MEM_STROBE_NEW_CMD |
1766                         RTI_CMD_MEM_OFFSET(i);
1767                 writeq(val64, &bar0->rti_command_mem);
1768
1769                 /*
1770                  * Once the operation completes, the Strobe bit of the
1771                  * command register will be reset. We poll for this
1772                  * particular condition. We wait for a maximum of 500ms
1773                  * for the operation to complete, if it's not complete
1774                  * by then we return error.
1775                  */
1776                 time = 0;
1777                 while (true) {
1778                         val64 = readq(&bar0->rti_command_mem);
1779                         if (!(val64 & RTI_CMD_MEM_STROBE_NEW_CMD))
1780                                 break;
1781
1782                         if (time > 10) {
1783                                 DBG_PRINT(ERR_DBG, "%s: RTI init failed\n",
1784                                           dev->name);
1785                                 return -ENODEV;
1786                         }
1787                         time++;
1788                         msleep(50);
1789                 }
1790         }
1791
1792         /*
1793          * Initializing proper values as Pause threshold into all
1794          * the 8 Queues on Rx side.
1795          */
1796         writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q0q3);
1797         writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q4q7);
1798
1799         /* Disable RMAC PAD STRIPPING */
1800         add = &bar0->mac_cfg;
1801         val64 = readq(&bar0->mac_cfg);
1802         val64 &= ~(MAC_CFG_RMAC_STRIP_PAD);
1803         writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1804         writel((u32) (val64), add);
1805         writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1806         writel((u32) (val64 >> 32), (add + 4));
1807         val64 = readq(&bar0->mac_cfg);
1808
1809         /* Enable FCS stripping by adapter */
1810         add = &bar0->mac_cfg;
1811         val64 = readq(&bar0->mac_cfg);
1812         val64 |= MAC_CFG_RMAC_STRIP_FCS;
1813         if (nic->device_type == XFRAME_II_DEVICE)
1814                 writeq(val64, &bar0->mac_cfg);
1815         else {
1816                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1817                 writel((u32) (val64), add);
1818                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1819                 writel((u32) (val64 >> 32), (add + 4));
1820         }
1821
1822         /*
1823          * Set the time value to be inserted in the pause frame
1824          * generated by xena.
1825          */
1826         val64 = readq(&bar0->rmac_pause_cfg);
1827         val64 &= ~(RMAC_PAUSE_HG_PTIME(0xffff));
1828         val64 |= RMAC_PAUSE_HG_PTIME(nic->mac_control.rmac_pause_time);
1829         writeq(val64, &bar0->rmac_pause_cfg);
1830
1831         /*
1832          * Set the Threshold Limit for Generating the pause frame
1833          * If the amount of data in any Queue exceeds ratio of
1834          * (mac_control.mc_pause_threshold_q0q3 or q4q7)/256
1835          * pause frame is generated
1836          */
1837         val64 = 0;
1838         for (i = 0; i < 4; i++) {
1839                 val64 |= (((u64)0xFF00 |
1840                            nic->mac_control.mc_pause_threshold_q0q3)
1841                           << (i * 2 * 8));
1842         }
1843         writeq(val64, &bar0->mc_pause_thresh_q0q3);
1844
1845         val64 = 0;
1846         for (i = 0; i < 4; i++) {
1847                 val64 |= (((u64)0xFF00 |
1848                            nic->mac_control.mc_pause_threshold_q4q7)
1849                           << (i * 2 * 8));
1850         }
1851         writeq(val64, &bar0->mc_pause_thresh_q4q7);
1852
1853         /*
1854          * TxDMA will stop Read request if the number of read split has
1855          * exceeded the limit pointed by shared_splits
1856          */
1857         val64 = readq(&bar0->pic_control);
1858         val64 |= PIC_CNTL_SHARED_SPLITS(shared_splits);
1859         writeq(val64, &bar0->pic_control);
1860
1861         if (nic->config.bus_speed == 266) {
1862                 writeq(TXREQTO_VAL(0x7f) | TXREQTO_EN, &bar0->txreqtimeout);
1863                 writeq(0x0, &bar0->read_retry_delay);
1864                 writeq(0x0, &bar0->write_retry_delay);
1865         }
1866
1867         /*
1868          * Programming the Herc to split every write transaction
1869          * that does not start on an ADB to reduce disconnects.
1870          */
1871         if (nic->device_type == XFRAME_II_DEVICE) {
1872                 val64 = FAULT_BEHAVIOUR | EXT_REQ_EN |
1873                         MISC_LINK_STABILITY_PRD(3);
1874                 writeq(val64, &bar0->misc_control);
1875                 val64 = readq(&bar0->pic_control2);
1876                 val64 &= ~(s2BIT(13)|s2BIT(14)|s2BIT(15));
1877                 writeq(val64, &bar0->pic_control2);
1878         }
1879         if (strstr(nic->product_name, "CX4")) {
1880                 val64 = TMAC_AVG_IPG(0x17);
1881                 writeq(val64, &bar0->tmac_avg_ipg);
1882         }
1883
1884         return SUCCESS;
1885 }
1886 #define LINK_UP_DOWN_INTERRUPT          1
1887 #define MAC_RMAC_ERR_TIMER              2
1888
1889 static int s2io_link_fault_indication(struct s2io_nic *nic)
1890 {
1891         if (nic->device_type == XFRAME_II_DEVICE)
1892                 return LINK_UP_DOWN_INTERRUPT;
1893         else
1894                 return MAC_RMAC_ERR_TIMER;
1895 }
1896
1897 /**
1898  *  do_s2io_write_bits -  update alarm bits in alarm register
1899  *  @value: alarm bits
1900  *  @flag: interrupt status
1901  *  @addr: address value
1902  *  Description: update alarm bits in alarm register
1903  *  Return Value:
1904  *  NONE.
1905  */
1906 static void do_s2io_write_bits(u64 value, int flag, void __iomem *addr)
1907 {
1908         u64 temp64;
1909
1910         temp64 = readq(addr);
1911
1912         if (flag == ENABLE_INTRS)
1913                 temp64 &= ~((u64)value);
1914         else
1915                 temp64 |= ((u64)value);
1916         writeq(temp64, addr);
1917 }
1918
1919 static void en_dis_err_alarms(struct s2io_nic *nic, u16 mask, int flag)
1920 {
1921         struct XENA_dev_config __iomem *bar0 = nic->bar0;
1922         register u64 gen_int_mask = 0;
1923         u64 interruptible;
1924
1925         writeq(DISABLE_ALL_INTRS, &bar0->general_int_mask);
1926         if (mask & TX_DMA_INTR) {
1927                 gen_int_mask |= TXDMA_INT_M;
1928
1929                 do_s2io_write_bits(TXDMA_TDA_INT | TXDMA_PFC_INT |
1930                                    TXDMA_PCC_INT | TXDMA_TTI_INT |
1931                                    TXDMA_LSO_INT | TXDMA_TPA_INT |
1932                                    TXDMA_SM_INT, flag, &bar0->txdma_int_mask);
1933
1934                 do_s2io_write_bits(PFC_ECC_DB_ERR | PFC_SM_ERR_ALARM |
1935                                    PFC_MISC_0_ERR | PFC_MISC_1_ERR |
1936                                    PFC_PCIX_ERR | PFC_ECC_SG_ERR, flag,
1937                                    &bar0->pfc_err_mask);
1938
1939                 do_s2io_write_bits(TDA_Fn_ECC_DB_ERR | TDA_SM0_ERR_ALARM |
1940                                    TDA_SM1_ERR_ALARM | TDA_Fn_ECC_SG_ERR |
1941                                    TDA_PCIX_ERR, flag, &bar0->tda_err_mask);
1942
1943                 do_s2io_write_bits(PCC_FB_ECC_DB_ERR | PCC_TXB_ECC_DB_ERR |
1944                                    PCC_SM_ERR_ALARM | PCC_WR_ERR_ALARM |
1945                                    PCC_N_SERR | PCC_6_COF_OV_ERR |
1946                                    PCC_7_COF_OV_ERR | PCC_6_LSO_OV_ERR |
1947                                    PCC_7_LSO_OV_ERR | PCC_FB_ECC_SG_ERR |
1948                                    PCC_TXB_ECC_SG_ERR,
1949                                    flag, &bar0->pcc_err_mask);
1950
1951                 do_s2io_write_bits(TTI_SM_ERR_ALARM | TTI_ECC_SG_ERR |
1952                                    TTI_ECC_DB_ERR, flag, &bar0->tti_err_mask);
1953
1954                 do_s2io_write_bits(LSO6_ABORT | LSO7_ABORT |
1955                                    LSO6_SM_ERR_ALARM | LSO7_SM_ERR_ALARM |
1956                                    LSO6_SEND_OFLOW | LSO7_SEND_OFLOW,
1957                                    flag, &bar0->lso_err_mask);
1958
1959                 do_s2io_write_bits(TPA_SM_ERR_ALARM | TPA_TX_FRM_DROP,
1960                                    flag, &bar0->tpa_err_mask);
1961
1962                 do_s2io_write_bits(SM_SM_ERR_ALARM, flag, &bar0->sm_err_mask);
1963         }
1964
1965         if (mask & TX_MAC_INTR) {
1966                 gen_int_mask |= TXMAC_INT_M;
1967                 do_s2io_write_bits(MAC_INT_STATUS_TMAC_INT, flag,
1968                                    &bar0->mac_int_mask);
1969                 do_s2io_write_bits(TMAC_TX_BUF_OVRN | TMAC_TX_SM_ERR |
1970                                    TMAC_ECC_SG_ERR | TMAC_ECC_DB_ERR |
1971                                    TMAC_DESC_ECC_SG_ERR | TMAC_DESC_ECC_DB_ERR,
1972                                    flag, &bar0->mac_tmac_err_mask);
1973         }
1974
1975         if (mask & TX_XGXS_INTR) {
1976                 gen_int_mask |= TXXGXS_INT_M;
1977                 do_s2io_write_bits(XGXS_INT_STATUS_TXGXS, flag,
1978                                    &bar0->xgxs_int_mask);
1979                 do_s2io_write_bits(TXGXS_ESTORE_UFLOW | TXGXS_TX_SM_ERR |
1980                                    TXGXS_ECC_SG_ERR | TXGXS_ECC_DB_ERR,
1981                                    flag, &bar0->xgxs_txgxs_err_mask);
1982         }
1983
1984         if (mask & RX_DMA_INTR) {
1985                 gen_int_mask |= RXDMA_INT_M;
1986                 do_s2io_write_bits(RXDMA_INT_RC_INT_M | RXDMA_INT_RPA_INT_M |
1987                                    RXDMA_INT_RDA_INT_M | RXDMA_INT_RTI_INT_M,
1988                                    flag, &bar0->rxdma_int_mask);
1989                 do_s2io_write_bits(RC_PRCn_ECC_DB_ERR | RC_FTC_ECC_DB_ERR |
1990                                    RC_PRCn_SM_ERR_ALARM | RC_FTC_SM_ERR_ALARM |
1991                                    RC_PRCn_ECC_SG_ERR | RC_FTC_ECC_SG_ERR |
1992                                    RC_RDA_FAIL_WR_Rn, flag, &bar0->rc_err_mask);
1993                 do_s2io_write_bits(PRC_PCI_AB_RD_Rn | PRC_PCI_AB_WR_Rn |
1994                                    PRC_PCI_AB_F_WR_Rn | PRC_PCI_DP_RD_Rn |
1995                                    PRC_PCI_DP_WR_Rn | PRC_PCI_DP_F_WR_Rn, flag,
1996                                    &bar0->prc_pcix_err_mask);
1997                 do_s2io_write_bits(RPA_SM_ERR_ALARM | RPA_CREDIT_ERR |
1998                                    RPA_ECC_SG_ERR | RPA_ECC_DB_ERR, flag,
1999                                    &bar0->rpa_err_mask);
2000                 do_s2io_write_bits(RDA_RXDn_ECC_DB_ERR | RDA_FRM_ECC_DB_N_AERR |
2001                                    RDA_SM1_ERR_ALARM | RDA_SM0_ERR_ALARM |
2002                                    RDA_RXD_ECC_DB_SERR | RDA_RXDn_ECC_SG_ERR |
2003                                    RDA_FRM_ECC_SG_ERR |
2004                                    RDA_MISC_ERR|RDA_PCIX_ERR,
2005                                    flag, &bar0->rda_err_mask);
2006                 do_s2io_write_bits(RTI_SM_ERR_ALARM |
2007                                    RTI_ECC_SG_ERR | RTI_ECC_DB_ERR,
2008                                    flag, &bar0->rti_err_mask);
2009         }
2010
2011         if (mask & RX_MAC_INTR) {
2012                 gen_int_mask |= RXMAC_INT_M;
2013                 do_s2io_write_bits(MAC_INT_STATUS_RMAC_INT, flag,
2014                                    &bar0->mac_int_mask);
2015                 interruptible = (RMAC_RX_BUFF_OVRN | RMAC_RX_SM_ERR |
2016                                  RMAC_UNUSED_INT | RMAC_SINGLE_ECC_ERR |
2017                                  RMAC_DOUBLE_ECC_ERR);
2018                 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER)
2019                         interruptible |= RMAC_LINK_STATE_CHANGE_INT;
2020                 do_s2io_write_bits(interruptible,
2021                                    flag, &bar0->mac_rmac_err_mask);
2022         }
2023
2024         if (mask & RX_XGXS_INTR) {
2025                 gen_int_mask |= RXXGXS_INT_M;
2026                 do_s2io_write_bits(XGXS_INT_STATUS_RXGXS, flag,
2027                                    &bar0->xgxs_int_mask);
2028                 do_s2io_write_bits(RXGXS_ESTORE_OFLOW | RXGXS_RX_SM_ERR, flag,
2029                                    &bar0->xgxs_rxgxs_err_mask);
2030         }
2031
2032         if (mask & MC_INTR) {
2033                 gen_int_mask |= MC_INT_M;
2034                 do_s2io_write_bits(MC_INT_MASK_MC_INT,
2035                                    flag, &bar0->mc_int_mask);
2036                 do_s2io_write_bits(MC_ERR_REG_SM_ERR | MC_ERR_REG_ECC_ALL_SNG |
2037                                    MC_ERR_REG_ECC_ALL_DBL | PLL_LOCK_N, flag,
2038                                    &bar0->mc_err_mask);
2039         }
2040         nic->general_int_mask = gen_int_mask;
2041
2042         /* Remove this line when alarm interrupts are enabled */
2043         nic->general_int_mask = 0;
2044 }
2045
2046 /**
2047  *  en_dis_able_nic_intrs - Enable or Disable the interrupts
2048  *  @nic: device private variable,
2049  *  @mask: A mask indicating which Intr block must be modified and,
2050  *  @flag: A flag indicating whether to enable or disable the Intrs.
2051  *  Description: This function will either disable or enable the interrupts
2052  *  depending on the flag argument. The mask argument can be used to
2053  *  enable/disable any Intr block.
2054  *  Return Value: NONE.
2055  */
2056
2057 static void en_dis_able_nic_intrs(struct s2io_nic *nic, u16 mask, int flag)
2058 {
2059         struct XENA_dev_config __iomem *bar0 = nic->bar0;
2060         register u64 temp64 = 0, intr_mask = 0;
2061
2062         intr_mask = nic->general_int_mask;
2063
2064         /*  Top level interrupt classification */
2065         /*  PIC Interrupts */
2066         if (mask & TX_PIC_INTR) {
2067                 /*  Enable PIC Intrs in the general intr mask register */
2068                 intr_mask |= TXPIC_INT_M;
2069                 if (flag == ENABLE_INTRS) {
2070                         /*
2071                          * If Hercules adapter enable GPIO otherwise
2072                          * disable all PCIX, Flash, MDIO, IIC and GPIO
2073                          * interrupts for now.
2074                          * TODO
2075                          */
2076                         if (s2io_link_fault_indication(nic) ==
2077                             LINK_UP_DOWN_INTERRUPT) {
2078                                 do_s2io_write_bits(PIC_INT_GPIO, flag,
2079                                                    &bar0->pic_int_mask);
2080                                 do_s2io_write_bits(GPIO_INT_MASK_LINK_UP, flag,
2081                                                    &bar0->gpio_int_mask);
2082                         } else
2083                                 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
2084                 } else if (flag == DISABLE_INTRS) {
2085                         /*
2086                          * Disable PIC Intrs in the general
2087                          * intr mask register
2088                          */
2089                         writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
2090                 }
2091         }
2092
2093         /*  Tx traffic interrupts */
2094         if (mask & TX_TRAFFIC_INTR) {
2095                 intr_mask |= TXTRAFFIC_INT_M;
2096                 if (flag == ENABLE_INTRS) {
2097                         /*
2098                          * Enable all the Tx side interrupts
2099                          * writing 0 Enables all 64 TX interrupt levels
2100                          */
2101                         writeq(0x0, &bar0->tx_traffic_mask);
2102                 } else if (flag == DISABLE_INTRS) {
2103                         /*
2104                          * Disable Tx Traffic Intrs in the general intr mask
2105                          * register.
2106                          */
2107                         writeq(DISABLE_ALL_INTRS, &bar0->tx_traffic_mask);
2108                 }
2109         }
2110
2111         /*  Rx traffic interrupts */
2112         if (mask & RX_TRAFFIC_INTR) {
2113                 intr_mask |= RXTRAFFIC_INT_M;
2114                 if (flag == ENABLE_INTRS) {
2115                         /* writing 0 Enables all 8 RX interrupt levels */
2116                         writeq(0x0, &bar0->rx_traffic_mask);
2117                 } else if (flag == DISABLE_INTRS) {
2118                         /*
2119                          * Disable Rx Traffic Intrs in the general intr mask
2120                          * register.
2121                          */
2122                         writeq(DISABLE_ALL_INTRS, &bar0->rx_traffic_mask);
2123                 }
2124         }
2125
2126         temp64 = readq(&bar0->general_int_mask);
2127         if (flag == ENABLE_INTRS)
2128                 temp64 &= ~((u64)intr_mask);
2129         else
2130                 temp64 = DISABLE_ALL_INTRS;
2131         writeq(temp64, &bar0->general_int_mask);
2132
2133         nic->general_int_mask = readq(&bar0->general_int_mask);
2134 }
2135
2136 /**
2137  *  verify_pcc_quiescent- Checks for PCC quiescent state
2138  *  Return: 1 If PCC is quiescence
2139  *          0 If PCC is not quiescence
2140  */
2141 static int verify_pcc_quiescent(struct s2io_nic *sp, int flag)
2142 {
2143         int ret = 0, herc;
2144         struct XENA_dev_config __iomem *bar0 = sp->bar0;
2145         u64 val64 = readq(&bar0->adapter_status);
2146
2147         herc = (sp->device_type == XFRAME_II_DEVICE);
2148
2149         if (flag == false) {
2150                 if ((!herc && (sp->pdev->revision >= 4)) || herc) {
2151                         if (!(val64 & ADAPTER_STATUS_RMAC_PCC_IDLE))
2152                                 ret = 1;
2153                 } else {
2154                         if (!(val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))
2155                                 ret = 1;
2156                 }
2157         } else {
2158                 if ((!herc && (sp->pdev->revision >= 4)) || herc) {
2159                         if (((val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) ==
2160                              ADAPTER_STATUS_RMAC_PCC_IDLE))
2161                                 ret = 1;
2162                 } else {
2163                         if (((val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) ==
2164                              ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))
2165                                 ret = 1;
2166                 }
2167         }
2168
2169         return ret;
2170 }
2171 /**
2172  *  verify_xena_quiescence - Checks whether the H/W is ready
2173  *  Description: Returns whether the H/W is ready to go or not. Depending
2174  *  on whether adapter enable bit was written or not the comparison
2175  *  differs and the calling function passes the input argument flag to
2176  *  indicate this.
2177  *  Return: 1 If xena is quiescence
2178  *          0 If Xena is not quiescence
2179  */
2180
2181 static int verify_xena_quiescence(struct s2io_nic *sp)
2182 {
2183         int  mode;
2184         struct XENA_dev_config __iomem *bar0 = sp->bar0;
2185         u64 val64 = readq(&bar0->adapter_status);
2186         mode = s2io_verify_pci_mode(sp);
2187
2188         if (!(val64 & ADAPTER_STATUS_TDMA_READY)) {
2189                 DBG_PRINT(ERR_DBG, "TDMA is not ready!\n");
2190                 return 0;
2191         }
2192         if (!(val64 & ADAPTER_STATUS_RDMA_READY)) {
2193                 DBG_PRINT(ERR_DBG, "RDMA is not ready!\n");
2194                 return 0;
2195         }
2196         if (!(val64 & ADAPTER_STATUS_PFC_READY)) {
2197                 DBG_PRINT(ERR_DBG, "PFC is not ready!\n");
2198                 return 0;
2199         }
2200         if (!(val64 & ADAPTER_STATUS_TMAC_BUF_EMPTY)) {
2201                 DBG_PRINT(ERR_DBG, "TMAC BUF is not empty!\n");
2202                 return 0;
2203         }
2204         if (!(val64 & ADAPTER_STATUS_PIC_QUIESCENT)) {
2205                 DBG_PRINT(ERR_DBG, "PIC is not QUIESCENT!\n");
2206                 return 0;
2207         }
2208         if (!(val64 & ADAPTER_STATUS_MC_DRAM_READY)) {
2209                 DBG_PRINT(ERR_DBG, "MC_DRAM is not ready!\n");
2210                 return 0;
2211         }
2212         if (!(val64 & ADAPTER_STATUS_MC_QUEUES_READY)) {
2213                 DBG_PRINT(ERR_DBG, "MC_QUEUES is not ready!\n");
2214                 return 0;
2215         }
2216         if (!(val64 & ADAPTER_STATUS_M_PLL_LOCK)) {
2217                 DBG_PRINT(ERR_DBG, "M_PLL is not locked!\n");
2218                 return 0;
2219         }
2220
2221         /*
2222          * In PCI 33 mode, the P_PLL is not used, and therefore,
2223          * the the P_PLL_LOCK bit in the adapter_status register will
2224          * not be asserted.
2225          */
2226         if (!(val64 & ADAPTER_STATUS_P_PLL_LOCK) &&
2227             sp->device_type == XFRAME_II_DEVICE &&
2228             mode != PCI_MODE_PCI_33) {
2229                 DBG_PRINT(ERR_DBG, "P_PLL is not locked!\n");
2230                 return 0;
2231         }
2232         if (!((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
2233               ADAPTER_STATUS_RC_PRC_QUIESCENT)) {
2234                 DBG_PRINT(ERR_DBG, "RC_PRC is not QUIESCENT!\n");
2235                 return 0;
2236         }
2237         return 1;
2238 }
2239
2240 /**
2241  * fix_mac_address -  Fix for Mac addr problem on Alpha platforms
2242  * @sp: Pointer to device specifc structure
2243  * Description :
2244  * New procedure to clear mac address reading  problems on Alpha platforms
2245  *
2246  */
2247
2248 static void fix_mac_address(struct s2io_nic *sp)
2249 {
2250         struct XENA_dev_config __iomem *bar0 = sp->bar0;
2251         u64 val64;
2252         int i = 0;
2253
2254         while (fix_mac[i] != END_SIGN) {
2255                 writeq(fix_mac[i++], &bar0->gpio_control);
2256                 udelay(10);
2257                 val64 = readq(&bar0->gpio_control);
2258         }
2259 }
2260
2261 /**
2262  *  start_nic - Turns the device on
2263  *  @nic : device private variable.
2264  *  Description:
2265  *  This function actually turns the device on. Before this  function is
2266  *  called,all Registers are configured from their reset states
2267  *  and shared memory is allocated but the NIC is still quiescent. On
2268  *  calling this function, the device interrupts are cleared and the NIC is
2269  *  literally switched on by writing into the adapter control register.
2270  *  Return Value:
2271  *  SUCCESS on success and -1 on failure.
2272  */
2273
2274 static int start_nic(struct s2io_nic *nic)
2275 {
2276         struct XENA_dev_config __iomem *bar0 = nic->bar0;
2277         struct net_device *dev = nic->dev;
2278         register u64 val64 = 0;
2279         u16 subid, i;
2280         struct config_param *config = &nic->config;
2281         struct mac_info *mac_control = &nic->mac_control;
2282
2283         /*  PRC Initialization and configuration */
2284         for (i = 0; i < config->rx_ring_num; i++) {
2285                 struct ring_info *ring = &mac_control->rings[i];
2286
2287                 writeq((u64)ring->rx_blocks[0].block_dma_addr,
2288                        &bar0->prc_rxd0_n[i]);
2289
2290                 val64 = readq(&bar0->prc_ctrl_n[i]);
2291                 if (nic->rxd_mode == RXD_MODE_1)
2292                         val64 |= PRC_CTRL_RC_ENABLED;
2293                 else
2294                         val64 |= PRC_CTRL_RC_ENABLED | PRC_CTRL_RING_MODE_3;
2295                 if (nic->device_type == XFRAME_II_DEVICE)
2296                         val64 |= PRC_CTRL_GROUP_READS;
2297                 val64 &= ~PRC_CTRL_RXD_BACKOFF_INTERVAL(0xFFFFFF);
2298                 val64 |= PRC_CTRL_RXD_BACKOFF_INTERVAL(0x1000);
2299                 writeq(val64, &bar0->prc_ctrl_n[i]);
2300         }
2301
2302         if (nic->rxd_mode == RXD_MODE_3B) {
2303                 /* Enabling 2 buffer mode by writing into Rx_pa_cfg reg. */
2304                 val64 = readq(&bar0->rx_pa_cfg);
2305                 val64 |= RX_PA_CFG_IGNORE_L2_ERR;
2306                 writeq(val64, &bar0->rx_pa_cfg);
2307         }
2308
2309         if (vlan_tag_strip == 0) {
2310                 val64 = readq(&bar0->rx_pa_cfg);
2311                 val64 &= ~RX_PA_CFG_STRIP_VLAN_TAG;
2312                 writeq(val64, &bar0->rx_pa_cfg);
2313                 nic->vlan_strip_flag = 0;
2314         }
2315
2316         /*
2317          * Enabling MC-RLDRAM. After enabling the device, we timeout
2318          * for around 100ms, which is approximately the time required
2319          * for the device to be ready for operation.
2320          */
2321         val64 = readq(&bar0->mc_rldram_mrs);
2322         val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE | MC_RLDRAM_MRS_ENABLE;
2323         SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
2324         val64 = readq(&bar0->mc_rldram_mrs);
2325
2326         msleep(100);    /* Delay by around 100 ms. */
2327
2328         /* Enabling ECC Protection. */
2329         val64 = readq(&bar0->adapter_control);
2330         val64 &= ~ADAPTER_ECC_EN;
2331         writeq(val64, &bar0->adapter_control);
2332
2333         /*
2334          * Verify if the device is ready to be enabled, if so enable
2335          * it.
2336          */
2337         val64 = readq(&bar0->adapter_status);
2338         if (!verify_xena_quiescence(nic)) {
2339                 DBG_PRINT(ERR_DBG, "%s: device is not ready, "
2340                           "Adapter status reads: 0x%llx\n",
2341                           dev->name, (unsigned long long)val64);
2342                 return FAILURE;
2343         }
2344
2345         /*
2346          * With some switches, link might be already up at this point.
2347          * Because of this weird behavior, when we enable laser,
2348          * we may not get link. We need to handle this. We cannot
2349          * figure out which switch is misbehaving. So we are forced to
2350          * make a global change.
2351          */
2352
2353         /* Enabling Laser. */
2354         val64 = readq(&bar0->adapter_control);
2355         val64 |= ADAPTER_EOI_TX_ON;
2356         writeq(val64, &bar0->adapter_control);
2357
2358         if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
2359                 /*
2360                  * Dont see link state interrupts initally on some switches,
2361                  * so directly scheduling the link state task here.
2362                  */
2363                 schedule_work(&nic->set_link_task);
2364         }
2365         /* SXE-002: Initialize link and activity LED */
2366         subid = nic->pdev->subsystem_device;
2367         if (((subid & 0xFF) >= 0x07) &&
2368             (nic->device_type == XFRAME_I_DEVICE)) {
2369                 val64 = readq(&bar0->gpio_control);
2370                 val64 |= 0x0000800000000000ULL;
2371                 writeq(val64, &bar0->gpio_control);
2372                 val64 = 0x0411040400000000ULL;
2373                 writeq(val64, (void __iomem *)bar0 + 0x2700);
2374         }
2375
2376         return SUCCESS;
2377 }
2378 /**
2379  * s2io_txdl_getskb - Get the skb from txdl, unmap and return skb
2380  */
2381 static struct sk_buff *s2io_txdl_getskb(struct fifo_info *fifo_data,
2382                                         struct TxD *txdlp, int get_off)
2383 {
2384         struct s2io_nic *nic = fifo_data->nic;
2385         struct sk_buff *skb;
2386         struct TxD *txds;
2387         u16 j, frg_cnt;
2388
2389         txds = txdlp;
2390         if (txds->Host_Control == (u64)(long)fifo_data->ufo_in_band_v) {
2391                 pci_unmap_single(nic->pdev, (dma_addr_t)txds->Buffer_Pointer,
2392                                  sizeof(u64), PCI_DMA_TODEVICE);
2393                 txds++;
2394         }
2395
2396         skb = (struct sk_buff *)((unsigned long)txds->Host_Control);
2397         if (!skb) {
2398                 memset(txdlp, 0, (sizeof(struct TxD) * fifo_data->max_txds));
2399                 return NULL;
2400         }
2401         pci_unmap_single(nic->pdev, (dma_addr_t)txds->Buffer_Pointer,
2402                          skb_headlen(skb), PCI_DMA_TODEVICE);
2403         frg_cnt = skb_shinfo(skb)->nr_frags;
2404         if (frg_cnt) {
2405                 txds++;
2406                 for (j = 0; j < frg_cnt; j++, txds++) {
2407                         skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
2408                         if (!txds->Buffer_Pointer)
2409                                 break;
2410                         pci_unmap_page(nic->pdev,
2411                                        (dma_addr_t)txds->Buffer_Pointer,
2412                                        frag->size, PCI_DMA_TODEVICE);
2413                 }
2414         }
2415         memset(txdlp, 0, (sizeof(struct TxD) * fifo_data->max_txds));
2416         return skb;
2417 }
2418
2419 /**
2420  *  free_tx_buffers - Free all queued Tx buffers
2421  *  @nic : device private variable.
2422  *  Description:
2423  *  Free all queued Tx buffers.
2424  *  Return Value: void
2425  */
2426
2427 static void free_tx_buffers(struct s2io_nic *nic)
2428 {
2429         struct net_device *dev = nic->dev;
2430         struct sk_buff *skb;
2431         struct TxD *txdp;
2432         int i, j;
2433         int cnt = 0;
2434         struct config_param *config = &nic->config;
2435         struct mac_info *mac_control = &nic->mac_control;
2436         struct stat_block *stats = mac_control->stats_info;
2437         struct swStat *swstats = &stats->sw_stat;
2438
2439         for (i = 0; i < config->tx_fifo_num; i++) {
2440                 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
2441                 struct fifo_info *fifo = &mac_control->fifos[i];
2442                 unsigned long flags;
2443
2444                 spin_lock_irqsave(&fifo->tx_lock, flags);
2445                 for (j = 0; j < tx_cfg->fifo_len; j++) {
2446                         txdp = (struct TxD *)fifo->list_info[j].list_virt_addr;
2447                         skb = s2io_txdl_getskb(&mac_control->fifos[i], txdp, j);
2448                         if (skb) {
2449                                 swstats->mem_freed += skb->truesize;
2450                                 dev_kfree_skb(skb);
2451                                 cnt++;
2452                         }
2453                 }
2454                 DBG_PRINT(INTR_DBG,
2455                           "%s: forcibly freeing %d skbs on FIFO%d\n",
2456                           dev->name, cnt, i);
2457                 fifo->tx_curr_get_info.offset = 0;
2458                 fifo->tx_curr_put_info.offset = 0;
2459                 spin_unlock_irqrestore(&fifo->tx_lock, flags);
2460         }
2461 }
2462
2463 /**
2464  *   stop_nic -  To stop the nic
2465  *   @nic ; device private variable.
2466  *   Description:
2467  *   This function does exactly the opposite of what the start_nic()
2468  *   function does. This function is called to stop the device.
2469  *   Return Value:
2470  *   void.
2471  */
2472
2473 static void stop_nic(struct s2io_nic *nic)
2474 {
2475         struct XENA_dev_config __iomem *bar0 = nic->bar0;
2476         register u64 val64 = 0;
2477         u16 interruptible;
2478
2479         /*  Disable all interrupts */
2480         en_dis_err_alarms(nic, ENA_ALL_INTRS, DISABLE_INTRS);
2481         interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
2482         interruptible |= TX_PIC_INTR;
2483         en_dis_able_nic_intrs(nic, interruptible, DISABLE_INTRS);
2484
2485         /* Clearing Adapter_En bit of ADAPTER_CONTROL Register */
2486         val64 = readq(&bar0->adapter_control);
2487         val64 &= ~(ADAPTER_CNTL_EN);
2488         writeq(val64, &bar0->adapter_control);
2489 }
2490
2491 /**
2492  *  fill_rx_buffers - Allocates the Rx side skbs
2493  *  @ring_info: per ring structure
2494  *  @from_card_up: If this is true, we will map the buffer to get
2495  *     the dma address for buf0 and buf1 to give it to the card.
2496  *     Else we will sync the already mapped buffer to give it to the card.
2497  *  Description:
2498  *  The function allocates Rx side skbs and puts the physical
2499  *  address of these buffers into the RxD buffer pointers, so that the NIC
2500  *  can DMA the received frame into these locations.
2501  *  The NIC supports 3 receive modes, viz
2502  *  1. single buffer,
2503  *  2. three buffer and
2504  *  3. Five buffer modes.
2505  *  Each mode defines how many fragments the received frame will be split
2506  *  up into by the NIC. The frame is split into L3 header, L4 Header,
2507  *  L4 payload in three buffer mode and in 5 buffer mode, L4 payload itself
2508  *  is split into 3 fragments. As of now only single buffer mode is
2509  *  supported.
2510  *   Return Value:
2511  *  SUCCESS on success or an appropriate -ve value on failure.
2512  */
2513 static int fill_rx_buffers(struct s2io_nic *nic, struct ring_info *ring,
2514                            int from_card_up)
2515 {
2516         struct sk_buff *skb;
2517         struct RxD_t *rxdp;
2518         int off, size, block_no, block_no1;
2519         u32 alloc_tab = 0;
2520         u32 alloc_cnt;
2521         u64 tmp;
2522         struct buffAdd *ba;
2523         struct RxD_t *first_rxdp = NULL;
2524         u64 Buffer0_ptr = 0, Buffer1_ptr = 0;
2525         int rxd_index = 0;
2526         struct RxD1 *rxdp1;
2527         struct RxD3 *rxdp3;
2528         struct swStat *swstats = &ring->nic->mac_control.stats_info->sw_stat;
2529
2530         alloc_cnt = ring->pkt_cnt - ring->rx_bufs_left;
2531
2532         block_no1 = ring->rx_curr_get_info.block_index;
2533         while (alloc_tab < alloc_cnt) {
2534                 block_no = ring->rx_curr_put_info.block_index;
2535
2536                 off = ring->rx_curr_put_info.offset;
2537
2538                 rxdp = ring->rx_blocks[block_no].rxds[off].virt_addr;
2539
2540                 rxd_index = off + 1;
2541                 if (block_no)
2542                         rxd_index += (block_no * ring->rxd_count);
2543
2544                 if ((block_no == block_no1) &&
2545                     (off == ring->rx_curr_get_info.offset) &&
2546                     (rxdp->Host_Control)) {
2547                         DBG_PRINT(INTR_DBG, "%s: Get and Put info equated\n",
2548                                   ring->dev->name);
2549                         goto end;
2550                 }
2551                 if (off && (off == ring->rxd_count)) {
2552                         ring->rx_curr_put_info.block_index++;
2553                         if (ring->rx_curr_put_info.block_index ==
2554                             ring->block_count)
2555                                 ring->rx_curr_put_info.block_index = 0;
2556                         block_no = ring->rx_curr_put_info.block_index;
2557                         off = 0;
2558                         ring->rx_curr_put_info.offset = off;
2559                         rxdp = ring->rx_blocks[block_no].block_virt_addr;
2560                         DBG_PRINT(INTR_DBG, "%s: Next block at: %p\n",
2561                                   ring->dev->name, rxdp);
2562
2563                 }
2564
2565                 if ((rxdp->Control_1 & RXD_OWN_XENA) &&
2566                     ((ring->rxd_mode == RXD_MODE_3B) &&
2567                      (rxdp->Control_2 & s2BIT(0)))) {
2568                         ring->rx_curr_put_info.offset = off;
2569                         goto end;
2570                 }
2571                 /* calculate size of skb based on ring mode */
2572                 size = ring->mtu +
2573                         HEADER_ETHERNET_II_802_3_SIZE +
2574                         HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
2575                 if (ring->rxd_mode == RXD_MODE_1)
2576                         size += NET_IP_ALIGN;
2577                 else
2578                         size = ring->mtu + ALIGN_SIZE + BUF0_LEN + 4;
2579
2580                 /* allocate skb */
2581                 skb = dev_alloc_skb(size);
2582                 if (!skb) {
2583                         DBG_PRINT(INFO_DBG, "%s: Could not allocate skb\n",
2584                                   ring->dev->name);
2585                         if (first_rxdp) {
2586                                 wmb();
2587                                 first_rxdp->Control_1 |= RXD_OWN_XENA;
2588                         }
2589                         swstats->mem_alloc_fail_cnt++;
2590
2591                         return -ENOMEM ;
2592                 }
2593                 swstats->mem_allocated += skb->truesize;
2594
2595                 if (ring->rxd_mode == RXD_MODE_1) {
2596                         /* 1 buffer mode - normal operation mode */
2597                         rxdp1 = (struct RxD1 *)rxdp;
2598                         memset(rxdp, 0, sizeof(struct RxD1));
2599                         skb_reserve(skb, NET_IP_ALIGN);
2600                         rxdp1->Buffer0_ptr =
2601                                 pci_map_single(ring->pdev, skb->data,
2602                                                size - NET_IP_ALIGN,
2603                                                PCI_DMA_FROMDEVICE);
2604                         if (pci_dma_mapping_error(nic->pdev,
2605                                                   rxdp1->Buffer0_ptr))
2606                                 goto pci_map_failed;
2607
2608                         rxdp->Control_2 =
2609                                 SET_BUFFER0_SIZE_1(size - NET_IP_ALIGN);
2610                         rxdp->Host_Control = (unsigned long)skb;
2611                 } else if (ring->rxd_mode == RXD_MODE_3B) {
2612                         /*
2613                          * 2 buffer mode -
2614                          * 2 buffer mode provides 128
2615                          * byte aligned receive buffers.
2616                          */
2617
2618                         rxdp3 = (struct RxD3 *)rxdp;
2619                         /* save buffer pointers to avoid frequent dma mapping */
2620                         Buffer0_ptr = rxdp3->Buffer0_ptr;
2621                         Buffer1_ptr = rxdp3->Buffer1_ptr;
2622                         memset(rxdp, 0, sizeof(struct RxD3));
2623                         /* restore the buffer pointers for dma sync*/
2624                         rxdp3->Buffer0_ptr = Buffer0_ptr;
2625                         rxdp3->Buffer1_ptr = Buffer1_ptr;
2626
2627                         ba = &ring->ba[block_no][off];
2628                         skb_reserve(skb, BUF0_LEN);
2629                         tmp = (u64)(unsigned long)skb->data;
2630                         tmp += ALIGN_SIZE;
2631                         tmp &= ~ALIGN_SIZE;
2632                         skb->data = (void *) (unsigned long)tmp;
2633                         skb_reset_tail_pointer(skb);
2634
2635                         if (from_card_up) {
2636                                 rxdp3->Buffer0_ptr =
2637                                         pci_map_single(ring->pdev, ba->ba_0,
2638                                                        BUF0_LEN,
2639                                                        PCI_DMA_FROMDEVICE);
2640                                 if (pci_dma_mapping_error(nic->pdev,
2641                                                           rxdp3->Buffer0_ptr))
2642                                         goto pci_map_failed;
2643                         } else
2644                                 pci_dma_sync_single_for_device(ring->pdev,
2645                                                                (dma_addr_t)rxdp3->Buffer0_ptr,
2646                                                                BUF0_LEN,
2647                                                                PCI_DMA_FROMDEVICE);
2648
2649                         rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
2650                         if (ring->rxd_mode == RXD_MODE_3B) {
2651                                 /* Two buffer mode */
2652
2653                                 /*
2654                                  * Buffer2 will have L3/L4 header plus
2655                                  * L4 payload
2656                                  */
2657                                 rxdp3->Buffer2_ptr = pci_map_single(ring->pdev,
2658                                                                     skb->data,
2659                                                                     ring->mtu + 4,
2660                                                                     PCI_DMA_FROMDEVICE);
2661
2662                                 if (pci_dma_mapping_error(nic->pdev,
2663                                                           rxdp3->Buffer2_ptr))
2664                                         goto pci_map_failed;
2665
2666                                 if (from_card_up) {
2667                                         rxdp3->Buffer1_ptr =
2668                                                 pci_map_single(ring->pdev,
2669                                                                ba->ba_1,
2670                                                                BUF1_LEN,
2671                                                                PCI_DMA_FROMDEVICE);
2672
2673                                         if (pci_dma_mapping_error(nic->pdev,
2674                                                                   rxdp3->Buffer1_ptr)) {
2675                                                 pci_unmap_single(ring->pdev,
2676                                                                  (dma_addr_t)(unsigned long)
2677                                                                  skb->data,
2678                                                                  ring->mtu + 4,
2679                                                                  PCI_DMA_FROMDEVICE);
2680                                                 goto pci_map_failed;
2681                                         }
2682                                 }
2683                                 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
2684                                 rxdp->Control_2 |= SET_BUFFER2_SIZE_3
2685                                         (ring->mtu + 4);
2686                         }
2687                         rxdp->Control_2 |= s2BIT(0);
2688                         rxdp->Host_Control = (unsigned long) (skb);
2689                 }
2690                 if (alloc_tab & ((1 << rxsync_frequency) - 1))
2691                         rxdp->Control_1 |= RXD_OWN_XENA;
2692                 off++;
2693                 if (off == (ring->rxd_count + 1))
2694                         off = 0;
2695                 ring->rx_curr_put_info.offset = off;
2696
2697                 rxdp->Control_2 |= SET_RXD_MARKER;
2698                 if (!(alloc_tab & ((1 << rxsync_frequency) - 1))) {
2699                         if (first_rxdp) {
2700                                 wmb();
2701                                 first_rxdp->Control_1 |= RXD_OWN_XENA;
2702                         }
2703                         first_rxdp = rxdp;
2704                 }
2705                 ring->rx_bufs_left += 1;
2706                 alloc_tab++;
2707         }
2708
2709 end:
2710         /* Transfer ownership of first descriptor to adapter just before
2711          * exiting. Before that, use memory barrier so that ownership
2712          * and other fields are seen by adapter correctly.
2713          */
2714         if (first_rxdp) {
2715                 wmb();
2716                 first_rxdp->Control_1 |= RXD_OWN_XENA;
2717         }
2718
2719         return SUCCESS;
2720
2721 pci_map_failed:
2722         swstats->pci_map_fail_cnt++;
2723         swstats->mem_freed += skb->truesize;
2724         dev_kfree_skb_irq(skb);
2725         return -ENOMEM;
2726 }
2727
2728 static void free_rxd_blk(struct s2io_nic *sp, int ring_no, int blk)
2729 {
2730         struct net_device *dev = sp->dev;
2731         int j;
2732         struct sk_buff *skb;
2733         struct RxD_t *rxdp;
2734         struct buffAdd *ba;
2735         struct RxD1 *rxdp1;
2736         struct RxD3 *rxdp3;
2737         struct mac_info *mac_control = &sp->mac_control;
2738         struct stat_block *stats = mac_control->stats_info;
2739         struct swStat *swstats = &stats->sw_stat;
2740
2741         for (j = 0 ; j < rxd_count[sp->rxd_mode]; j++) {
2742                 rxdp = mac_control->rings[ring_no].
2743                         rx_blocks[blk].rxds[j].virt_addr;
2744                 skb = (struct sk_buff *)((unsigned long)rxdp->Host_Control);
2745                 if (!skb)
2746                         continue;
2747                 if (sp->rxd_mode == RXD_MODE_1) {
2748                         rxdp1 = (struct RxD1 *)rxdp;
2749                         pci_unmap_single(sp->pdev,
2750                                          (dma_addr_t)rxdp1->Buffer0_ptr,
2751                                          dev->mtu +
2752                                          HEADER_ETHERNET_II_802_3_SIZE +
2753                                          HEADER_802_2_SIZE + HEADER_SNAP_SIZE,
2754                                          PCI_DMA_FROMDEVICE);
2755                         memset(rxdp, 0, sizeof(struct RxD1));
2756                 } else if (sp->rxd_mode == RXD_MODE_3B) {
2757                         rxdp3 = (struct RxD3 *)rxdp;
2758                         ba = &mac_control->rings[ring_no].ba[blk][j];
2759                         pci_unmap_single(sp->pdev,
2760                                          (dma_addr_t)rxdp3->Buffer0_ptr,
2761                                          BUF0_LEN,
2762                                          PCI_DMA_FROMDEVICE);
2763                         pci_unmap_single(sp->pdev,
2764                                          (dma_addr_t)rxdp3->Buffer1_ptr,
2765                                          BUF1_LEN,
2766                                          PCI_DMA_FROMDEVICE);
2767                         pci_unmap_single(sp->pdev,
2768                                          (dma_addr_t)rxdp3->Buffer2_ptr,
2769                                          dev->mtu + 4,
2770                                          PCI_DMA_FROMDEVICE);
2771                         memset(rxdp, 0, sizeof(struct RxD3));
2772                 }
2773                 swstats->mem_freed += skb->truesize;
2774                 dev_kfree_skb(skb);
2775                 mac_control->rings[ring_no].rx_bufs_left -= 1;
2776         }
2777 }
2778
2779 /**
2780  *  free_rx_buffers - Frees all Rx buffers
2781  *  @sp: device private variable.
2782  *  Description:
2783  *  This function will free all Rx buffers allocated by host.
2784  *  Return Value:
2785  *  NONE.
2786  */
2787
2788 static void free_rx_buffers(struct s2io_nic *sp)
2789 {
2790         struct net_device *dev = sp->dev;
2791         int i, blk = 0, buf_cnt = 0;
2792         struct config_param *config = &sp->config;
2793         struct mac_info *mac_control = &sp->mac_control;
2794
2795         for (i = 0; i < config->rx_ring_num; i++) {
2796                 struct ring_info *ring = &mac_control->rings[i];
2797
2798                 for (blk = 0; blk < rx_ring_sz[i]; blk++)
2799                         free_rxd_blk(sp, i, blk);
2800
2801                 ring->rx_curr_put_info.block_index = 0;
2802                 ring->rx_curr_get_info.block_index = 0;
2803                 ring->rx_curr_put_info.offset = 0;
2804                 ring->rx_curr_get_info.offset = 0;
2805                 ring->rx_bufs_left = 0;
2806                 DBG_PRINT(INIT_DBG, "%s: Freed 0x%x Rx Buffers on ring%d\n",
2807                           dev->name, buf_cnt, i);
2808         }
2809 }
2810
2811 static int s2io_chk_rx_buffers(struct s2io_nic *nic, struct ring_info *ring)
2812 {
2813         if (fill_rx_buffers(nic, ring, 0) == -ENOMEM) {
2814                 DBG_PRINT(INFO_DBG, "%s: Out of memory in Rx Intr!!\n",
2815                           ring->dev->name);
2816         }
2817         return 0;
2818 }
2819
2820 /**
2821  * s2io_poll - Rx interrupt handler for NAPI support
2822  * @napi : pointer to the napi structure.
2823  * @budget : The number of packets that were budgeted to be processed
2824  * during  one pass through the 'Poll" function.
2825  * Description:
2826  * Comes into picture only if NAPI support has been incorporated. It does
2827  * the same thing that rx_intr_handler does, but not in a interrupt context
2828  * also It will process only a given number of packets.
2829  * Return value:
2830  * 0 on success and 1 if there are No Rx packets to be processed.
2831  */
2832
2833 static int s2io_poll_msix(struct napi_struct *napi, int budget)
2834 {
2835         struct ring_info *ring = container_of(napi, struct ring_info, napi);
2836         struct net_device *dev = ring->dev;
2837         int pkts_processed = 0;
2838         u8 __iomem *addr = NULL;
2839         u8 val8 = 0;
2840         struct s2io_nic *nic = netdev_priv(dev);
2841         struct XENA_dev_config __iomem *bar0 = nic->bar0;
2842         int budget_org = budget;
2843
2844         if (unlikely(!is_s2io_card_up(nic)))
2845                 return 0;
2846
2847         pkts_processed = rx_intr_handler(ring, budget);
2848         s2io_chk_rx_buffers(nic, ring);
2849
2850         if (pkts_processed < budget_org) {
2851                 napi_complete(napi);
2852                 /*Re Enable MSI-Rx Vector*/
2853                 addr = (u8 __iomem *)&bar0->xmsi_mask_reg;
2854                 addr += 7 - ring->ring_no;
2855                 val8 = (ring->ring_no == 0) ? 0x3f : 0xbf;
2856                 writeb(val8, addr);
2857                 val8 = readb(addr);
2858         }
2859         return pkts_processed;
2860 }
2861
2862 static int s2io_poll_inta(struct napi_struct *napi, int budget)
2863 {
2864         struct s2io_nic *nic = container_of(napi, struct s2io_nic, napi);
2865         int pkts_processed = 0;
2866         int ring_pkts_processed, i;
2867         struct XENA_dev_config __iomem *bar0 = nic->bar0;
2868         int budget_org = budget;
2869         struct config_param *config = &nic->config;
2870         struct mac_info *mac_control = &nic->mac_control;
2871
2872         if (unlikely(!is_s2io_card_up(nic)))
2873                 return 0;
2874
2875         for (i = 0; i < config->rx_ring_num; i++) {
2876                 struct ring_info *ring = &mac_control->rings[i];
2877                 ring_pkts_processed = rx_intr_handler(ring, budget);
2878                 s2io_chk_rx_buffers(nic, ring);
2879                 pkts_processed += ring_pkts_processed;
2880                 budget -= ring_pkts_processed;
2881                 if (budget <= 0)
2882                         break;
2883         }
2884         if (pkts_processed < budget_org) {
2885                 napi_complete(napi);
2886                 /* Re enable the Rx interrupts for the ring */
2887                 writeq(0, &bar0->rx_traffic_mask);
2888                 readl(&bar0->rx_traffic_mask);
2889         }
2890         return pkts_processed;
2891 }
2892
2893 #ifdef CONFIG_NET_POLL_CONTROLLER
2894 /**
2895  * s2io_netpoll - netpoll event handler entry point
2896  * @dev : pointer to the device structure.
2897  * Description:
2898  *      This function will be called by upper layer to check for events on the
2899  * interface in situations where interrupts are disabled. It is used for
2900  * specific in-kernel networking tasks, such as remote consoles and kernel
2901  * debugging over the network (example netdump in RedHat).
2902  */
2903 static void s2io_netpoll(struct net_device *dev)
2904 {
2905         struct s2io_nic *nic = netdev_priv(dev);
2906         struct XENA_dev_config __iomem *bar0 = nic->bar0;
2907         u64 val64 = 0xFFFFFFFFFFFFFFFFULL;
2908         int i;
2909         struct config_param *config = &nic->config;
2910         struct mac_info *mac_control = &nic->mac_control;
2911
2912         if (pci_channel_offline(nic->pdev))
2913                 return;
2914
2915         disable_irq(dev->irq);
2916
2917         writeq(val64, &bar0->rx_traffic_int);
2918         writeq(val64, &bar0->tx_traffic_int);
2919
2920         /* we need to free up the transmitted skbufs or else netpoll will
2921          * run out of skbs and will fail and eventually netpoll application such
2922          * as netdump will fail.
2923          */
2924         for (i = 0; i < config->tx_fifo_num; i++)
2925                 tx_intr_handler(&mac_control->fifos[i]);
2926
2927         /* check for received packet and indicate up to network */
2928         for (i = 0; i < config->rx_ring_num; i++) {
2929                 struct ring_info *ring = &mac_control->rings[i];
2930
2931                 rx_intr_handler(ring, 0);
2932         }
2933
2934         for (i = 0; i < config->rx_ring_num; i++) {
2935                 struct ring_info *ring = &mac_control->rings[i];
2936
2937                 if (fill_rx_buffers(nic, ring, 0) == -ENOMEM) {
2938                         DBG_PRINT(INFO_DBG,
2939                                   "%s: Out of memory in Rx Netpoll!!\n",
2940                                   dev->name);
2941                         break;
2942                 }
2943         }
2944         enable_irq(dev->irq);
2945 }
2946 #endif
2947
2948 /**
2949  *  rx_intr_handler - Rx interrupt handler
2950  *  @ring_info: per ring structure.
2951  *  @budget: budget for napi processing.
2952  *  Description:
2953  *  If the interrupt is because of a received frame or if the
2954  *  receive ring contains fresh as yet un-processed frames,this function is
2955  *  called. It picks out the RxD at which place the last Rx processing had
2956  *  stopped and sends the skb to the OSM's Rx handler and then increments
2957  *  the offset.
2958  *  Return Value:
2959  *  No. of napi packets processed.
2960  */
2961 static int rx_intr_handler(struct ring_info *ring_data, int budget)
2962 {
2963         int get_block, put_block;
2964         struct rx_curr_get_info get_info, put_info;
2965         struct RxD_t *rxdp;
2966         struct sk_buff *skb;
2967         int pkt_cnt = 0, napi_pkts = 0;
2968         int i;
2969         struct RxD1 *rxdp1;
2970         struct RxD3 *rxdp3;
2971
2972         get_info = ring_data->rx_curr_get_info;
2973         get_block = get_info.block_index;
2974         memcpy(&put_info, &ring_data->rx_curr_put_info, sizeof(put_info));
2975         put_block = put_info.block_index;
2976         rxdp = ring_data->rx_blocks[get_block].rxds[get_info.offset].virt_addr;
2977
2978         while (RXD_IS_UP2DT(rxdp)) {
2979                 /*
2980                  * If your are next to put index then it's
2981                  * FIFO full condition
2982                  */
2983                 if ((get_block == put_block) &&
2984                     (get_info.offset + 1) == put_info.offset) {
2985                         DBG_PRINT(INTR_DBG, "%s: Ring Full\n",
2986                                   ring_data->dev->name);
2987                         break;
2988                 }
2989                 skb = (struct sk_buff *)((unsigned long)rxdp->Host_Control);
2990                 if (skb == NULL) {
2991                         DBG_PRINT(ERR_DBG, "%s: NULL skb in Rx Intr\n",
2992                                   ring_data->dev->name);
2993                         return 0;
2994                 }
2995                 if (ring_data->rxd_mode == RXD_MODE_1) {
2996                         rxdp1 = (struct RxD1 *)rxdp;
2997                         pci_unmap_single(ring_data->pdev, (dma_addr_t)
2998                                          rxdp1->Buffer0_ptr,
2999                                          ring_data->mtu +
3000                                          HEADER_ETHERNET_II_802_3_SIZE +
3001                                          HEADER_802_2_SIZE +
3002                                          HEADER_SNAP_SIZE,
3003                                          PCI_DMA_FROMDEVICE);
3004                 } else if (ring_data->rxd_mode == RXD_MODE_3B) {
3005                         rxdp3 = (struct RxD3 *)rxdp;
3006                         pci_dma_sync_single_for_cpu(ring_data->pdev,
3007                                                     (dma_addr_t)rxdp3->Buffer0_ptr,
3008                                                     BUF0_LEN,
3009                                                     PCI_DMA_FROMDEVICE);
3010                         pci_unmap_single(ring_data->pdev,
3011                                          (dma_addr_t)rxdp3->Buffer2_ptr,
3012                                          ring_data->mtu + 4,
3013                                          PCI_DMA_FROMDEVICE);
3014                 }
3015                 prefetch(skb->data);
3016                 rx_osm_handler(ring_data, rxdp);
3017                 get_info.offset++;
3018                 ring_data->rx_curr_get_info.offset = get_info.offset;
3019                 rxdp = ring_data->rx_blocks[get_block].
3020                         rxds[get_info.offset].virt_addr;
3021                 if (get_info.offset == rxd_count[ring_data->rxd_mode]) {
3022                         get_info.offset = 0;
3023                         ring_data->rx_curr_get_info.offset = get_info.offset;
3024                         get_block++;
3025                         if (get_block == ring_data->block_count)
3026                                 get_block = 0;
3027                         ring_data->rx_curr_get_info.block_index = get_block;
3028                         rxdp = ring_data->rx_blocks[get_block].block_virt_addr;
3029                 }
3030
3031                 if (ring_data->nic->config.napi) {
3032                         budget--;
3033                         napi_pkts++;
3034                         if (!budget)
3035                                 break;
3036                 }
3037                 pkt_cnt++;
3038                 if ((indicate_max_pkts) && (pkt_cnt > indicate_max_pkts))
3039                         break;
3040         }
3041         if (ring_data->lro) {
3042                 /* Clear all LRO sessions before exiting */
3043                 for (i = 0; i < MAX_LRO_SESSIONS; i++) {
3044                         struct lro *lro = &ring_data->lro0_n[i];
3045                         if (lro->in_use) {
3046                                 update_L3L4_header(ring_data->nic, lro);
3047                                 queue_rx_frame(lro->parent, lro->vlan_tag);
3048                                 clear_lro_session(lro);
3049                         }
3050                 }
3051         }
3052         return napi_pkts;
3053 }
3054
3055 /**
3056  *  tx_intr_handler - Transmit interrupt handler
3057  *  @nic : device private variable
3058  *  Description:
3059  *  If an interrupt was raised to indicate DMA complete of the
3060  *  Tx packet, this function is called. It identifies the last TxD
3061  *  whose buffer was freed and frees all skbs whose data have already
3062  *  DMA'ed into the NICs internal memory.
3063  *  Return Value:
3064  *  NONE
3065  */
3066
3067 static void tx_intr_handler(struct fifo_info *fifo_data)
3068 {
3069         struct s2io_nic *nic = fifo_data->nic;
3070         struct tx_curr_get_info get_info, put_info;
3071         struct sk_buff *skb = NULL;
3072         struct TxD *txdlp;
3073         int pkt_cnt = 0;
3074         unsigned long flags = 0;
3075         u8 err_mask;
3076         struct stat_block *stats = nic->mac_control.stats_info;
3077         struct swStat *swstats = &stats->sw_stat;
3078
3079         if (!spin_trylock_irqsave(&fifo_data->tx_lock, flags))
3080                 return;
3081
3082         get_info = fifo_data->tx_curr_get_info;
3083         memcpy(&put_info, &fifo_data->tx_curr_put_info, sizeof(put_info));
3084         txdlp = (struct TxD *)
3085                 fifo_data->list_info[get_info.offset].list_virt_addr;
3086         while ((!(txdlp->Control_1 & TXD_LIST_OWN_XENA)) &&
3087                (get_info.offset != put_info.offset) &&
3088                (txdlp->Host_Control)) {
3089                 /* Check for TxD errors */
3090                 if (txdlp->Control_1 & TXD_T_CODE) {
3091                         unsigned long long err;
3092                         err = txdlp->Control_1 & TXD_T_CODE;
3093                         if (err & 0x1) {
3094                                 swstats->parity_err_cnt++;
3095                         }
3096
3097                         /* update t_code statistics */
3098                         err_mask = err >> 48;
3099                         switch (err_mask) {
3100                         case 2:
3101                                 swstats->tx_buf_abort_cnt++;
3102                                 break;
3103
3104                         case 3:
3105                                 swstats->tx_desc_abort_cnt++;
3106                                 break;
3107
3108                         case 7:
3109                                 swstats->tx_parity_err_cnt++;
3110                                 break;
3111
3112                         case 10:
3113                                 swstats->tx_link_loss_cnt++;
3114                                 break;
3115
3116                         case 15:
3117                                 swstats->tx_list_proc_err_cnt++;
3118                                 break;
3119                         }
3120                 }
3121
3122                 skb = s2io_txdl_getskb(fifo_data, txdlp, get_info.offset);
3123                 if (skb == NULL) {
3124                         spin_unlock_irqrestore(&fifo_data->tx_lock, flags);
3125                         DBG_PRINT(ERR_DBG, "%s: NULL skb in Tx Free Intr\n",
3126                                   __func__);
3127                         return;
3128                 }
3129                 pkt_cnt++;
3130
3131                 /* Updating the statistics block */
3132                 swstats->mem_freed += skb->truesize;
3133                 dev_kfree_skb_irq(skb);
3134
3135                 get_info.offset++;
3136                 if (get_info.offset == get_info.fifo_len + 1)
3137                         get_info.offset = 0;
3138                 txdlp = (struct TxD *)
3139                         fifo_data->list_info[get_info.offset].list_virt_addr;
3140                 fifo_data->tx_curr_get_info.offset = get_info.offset;
3141         }
3142
3143         s2io_wake_tx_queue(fifo_data, pkt_cnt, nic->config.multiq);
3144
3145         spin_unlock_irqrestore(&fifo_data->tx_lock, flags);
3146 }
3147
3148 /**
3149  *  s2io_mdio_write - Function to write in to MDIO registers
3150  *  @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
3151  *  @addr     : address value
3152  *  @value    : data value
3153  *  @dev      : pointer to net_device structure
3154  *  Description:
3155  *  This function is used to write values to the MDIO registers
3156  *  NONE
3157  */
3158 static void s2io_mdio_write(u32 mmd_type, u64 addr, u16 value,
3159                             struct net_device *dev)
3160 {
3161         u64 val64;
3162         struct s2io_nic *sp = netdev_priv(dev);
3163         struct XENA_dev_config __iomem *bar0 = sp->bar0;
3164
3165         /* address transaction */
3166         val64 = MDIO_MMD_INDX_ADDR(addr) |
3167                 MDIO_MMD_DEV_ADDR(mmd_type) |
3168                 MDIO_MMS_PRT_ADDR(0x0);
3169         writeq(val64, &bar0->mdio_control);
3170         val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3171         writeq(val64, &bar0->mdio_control);
3172         udelay(100);
3173
3174         /* Data transaction */
3175         val64 = MDIO_MMD_INDX_ADDR(addr) |
3176                 MDIO_MMD_DEV_ADDR(mmd_type) |
3177                 MDIO_MMS_PRT_ADDR(0x0) |
3178                 MDIO_MDIO_DATA(value) |
3179                 MDIO_OP(MDIO_OP_WRITE_TRANS);
3180         writeq(val64, &bar0->mdio_control);
3181         val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3182         writeq(val64, &bar0->mdio_control);
3183         udelay(100);
3184
3185         val64 = MDIO_MMD_INDX_ADDR(addr) |
3186                 MDIO_MMD_DEV_ADDR(mmd_type) |
3187                 MDIO_MMS_PRT_ADDR(0x0) |
3188                 MDIO_OP(MDIO_OP_READ_TRANS);
3189         writeq(val64, &bar0->mdio_control);
3190         val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3191         writeq(val64, &bar0->mdio_control);
3192         udelay(100);
3193 }
3194
3195 /**
3196  *  s2io_mdio_read - Function to write in to MDIO registers
3197  *  @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
3198  *  @addr     : address value
3199  *  @dev      : pointer to net_device structure
3200  *  Description:
3201  *  This function is used to read values to the MDIO registers
3202  *  NONE
3203  */
3204 static u64 s2io_mdio_read(u32 mmd_type, u64 addr, struct net_device *dev)
3205 {
3206         u64 val64 = 0x0;
3207         u64 rval64 = 0x0;
3208         struct s2io_nic *sp = netdev_priv(dev);
3209         struct XENA_dev_config __iomem *bar0 = sp->bar0;
3210
3211         /* address transaction */
3212         val64 = val64 | (MDIO_MMD_INDX_ADDR(addr)
3213                          | MDIO_MMD_DEV_ADDR(mmd_type)
3214                          | MDIO_MMS_PRT_ADDR(0x0));
3215         writeq(val64, &bar0->mdio_control);
3216         val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3217         writeq(val64, &bar0->mdio_control);
3218         udelay(100);
3219
3220         /* Data transaction */
3221         val64 = MDIO_MMD_INDX_ADDR(addr) |
3222                 MDIO_MMD_DEV_ADDR(mmd_type) |
3223                 MDIO_MMS_PRT_ADDR(0x0) |
3224                 MDIO_OP(MDIO_OP_READ_TRANS);
3225         writeq(val64, &bar0->mdio_control);
3226         val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3227         writeq(val64, &bar0->mdio_control);
3228         udelay(100);
3229
3230         /* Read the value from regs */
3231         rval64 = readq(&bar0->mdio_control);
3232         rval64 = rval64 & 0xFFFF0000;
3233         rval64 = rval64 >> 16;
3234         return rval64;
3235 }
3236
3237 /**
3238  *  s2io_chk_xpak_counter - Function to check the status of the xpak counters
3239  *  @counter      : counter value to be updated
3240  *  @flag         : flag to indicate the status
3241  *  @type         : counter type
3242  *  Description:
3243  *  This function is to check the status of the xpak counters value
3244  *  NONE
3245  */
3246
3247 static void s2io_chk_xpak_counter(u64 *counter, u64 * regs_stat, u32 index,
3248                                   u16 flag, u16 type)
3249 {
3250         u64 mask = 0x3;
3251         u64 val64;
3252         int i;
3253         for (i = 0; i < index; i++)
3254                 mask = mask << 0x2;
3255
3256         if (flag > 0) {
3257                 *counter = *counter + 1;
3258                 val64 = *regs_stat & mask;
3259                 val64 = val64 >> (index * 0x2);
3260                 val64 = val64 + 1;
3261                 if (val64 == 3) {
3262                         switch (type) {
3263                         case 1:
3264                                 DBG_PRINT(ERR_DBG,
3265                                           "Take Xframe NIC out of service.\n");
3266                                 DBG_PRINT(ERR_DBG,
3267 "Excessive temperatures may result in premature transceiver failure.\n");
3268                                 break;
3269                         case 2:
3270                                 DBG_PRINT(ERR_DBG,
3271                                           "Take Xframe NIC out of service.\n");
3272                                 DBG_PRINT(ERR_DBG,
3273 "Excessive bias currents may indicate imminent laser diode failure.\n");
3274                                 break;
3275                         case 3:
3276                                 DBG_PRINT(ERR_DBG,
3277                                           "Take Xframe NIC out of service.\n");
3278                                 DBG_PRINT(ERR_DBG,
3279 "Excessive laser output power may saturate far-end receiver.\n");
3280                                 break;
3281                         default:
3282                                 DBG_PRINT(ERR_DBG,
3283                                           "Incorrect XPAK Alarm type\n");
3284                         }
3285                         val64 = 0x0;
3286                 }
3287                 val64 = val64 << (index * 0x2);
3288                 *regs_stat = (*regs_stat & (~mask)) | (val64);
3289
3290         } else {
3291                 *regs_stat = *regs_stat & (~mask);
3292         }
3293 }
3294
3295 /**
3296  *  s2io_updt_xpak_counter - Function to update the xpak counters
3297  *  @dev         : pointer to net_device struct
3298  *  Description:
3299  *  This function is to upate the status of the xpak counters value
3300  *  NONE
3301  */
3302 static void s2io_updt_xpak_counter(struct net_device *dev)
3303 {
3304         u16 flag  = 0x0;
3305         u16 type  = 0x0;
3306         u16 val16 = 0x0;
3307         u64 val64 = 0x0;
3308         u64 addr  = 0x0;
3309
3310         struct s2io_nic *sp = netdev_priv(dev);
3311         struct stat_block *stats = sp->mac_control.stats_info;
3312         struct xpakStat *xstats = &stats->xpak_stat;
3313
3314         /* Check the communication with the MDIO slave */
3315         addr = MDIO_CTRL1;
3316         val64 = 0x0;
3317         val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
3318         if ((val64 == 0xFFFF) || (val64 == 0x0000)) {
3319                 DBG_PRINT(ERR_DBG,
3320                           "ERR: MDIO slave access failed - Returned %llx\n",
3321                           (unsigned long long)val64);
3322                 return;
3323         }
3324
3325         /* Check for the expected value of control reg 1 */
3326         if (val64 != MDIO_CTRL1_SPEED10G) {
3327                 DBG_PRINT(ERR_DBG, "Incorrect value at PMA address 0x0000 - "
3328                           "Returned: %llx- Expected: 0x%x\n",
3329                           (unsigned long long)val64, MDIO_CTRL1_SPEED10G);
3330                 return;
3331         }
3332
3333         /* Loading the DOM register to MDIO register */
3334         addr = 0xA100;
3335         s2io_mdio_write(MDIO_MMD_PMAPMD, addr, val16, dev);
3336         val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
3337
3338         /* Reading the Alarm flags */
3339         addr = 0xA070;
3340         val64 = 0x0;
3341         val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
3342
3343         flag = CHECKBIT(val64, 0x7);
3344         type = 1;
3345         s2io_chk_xpak_counter(&xstats->alarm_transceiver_temp_high,
3346                               &xstats->xpak_regs_stat,
3347                               0x0, flag, type);
3348
3349         if (CHECKBIT(val64, 0x6))
3350                 xstats->alarm_transceiver_temp_low++;
3351
3352         flag = CHECKBIT(val64, 0x3);
3353         type = 2;
3354         s2io_chk_xpak_counter(&xstats->alarm_laser_bias_current_high,
3355                               &xstats->xpak_regs_stat,
3356                               0x2, flag, type);
3357
3358         if (CHECKBIT(val64, 0x2))
3359                 xstats->alarm_laser_bias_current_low++;
3360
3361         flag = CHECKBIT(val64, 0x1);
3362         type = 3;
3363         s2io_chk_xpak_counter(&xstats->alarm_laser_output_power_high,
3364                               &xstats->xpak_regs_stat,
3365                               0x4, flag, type);
3366
3367         if (CHECKBIT(val64, 0x0))
3368                 xstats->alarm_laser_output_power_low++;
3369
3370         /* Reading the Warning flags */
3371         addr = 0xA074;
3372         val64 = 0x0;
3373         val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
3374
3375         if (CHECKBIT(val64, 0x7))
3376                 xstats->warn_transceiver_temp_high++;
3377
3378         if (CHECKBIT(val64, 0x6))
3379                 xstats->warn_transceiver_temp_low++;
3380
3381         if (CHECKBIT(val64, 0x3))
3382                 xstats->warn_laser_bias_current_high++;
3383
3384         if (CHECKBIT(val64, 0x2))
3385                 xstats->warn_laser_bias_current_low++;
3386
3387         if (CHECKBIT(val64, 0x1))
3388                 xstats->warn_laser_output_power_high++;
3389
3390         if (CHECKBIT(val64, 0x0))
3391                 xstats->warn_laser_output_power_low++;
3392 }
3393
3394 /**
3395  *  wait_for_cmd_complete - waits for a command to complete.
3396  *  @sp : private member of the device structure, which is a pointer to the
3397  *  s2io_nic structure.
3398  *  Description: Function that waits for a command to Write into RMAC
3399  *  ADDR DATA registers to be completed and returns either success or
3400  *  error depending on whether the command was complete or not.
3401  *  Return value:
3402  *   SUCCESS on success and FAILURE on failure.
3403  */
3404
3405 static int wait_for_cmd_complete(void __iomem *addr, u64 busy_bit,
3406                                  int bit_state)
3407 {
3408         int ret = FAILURE, cnt = 0, delay = 1;
3409         u64 val64;
3410
3411         if ((bit_state != S2IO_BIT_RESET) && (bit_state != S2IO_BIT_SET))
3412                 return FAILURE;
3413
3414         do {
3415                 val64 = readq(addr);
3416                 if (bit_state == S2IO_BIT_RESET) {
3417                         if (!(val64 & busy_bit)) {
3418                                 ret = SUCCESS;
3419                                 break;
3420                         }
3421                 } else {
3422                         if (val64 & busy_bit) {
3423                                 ret = SUCCESS;
3424                                 break;
3425                         }
3426                 }
3427
3428                 if (in_interrupt())
3429                         mdelay(delay);
3430                 else
3431                         msleep(delay);
3432
3433                 if (++cnt >= 10)
3434                         delay = 50;
3435         } while (cnt < 20);
3436         return ret;
3437 }
3438 /*
3439  * check_pci_device_id - Checks if the device id is supported
3440  * @id : device id
3441  * Description: Function to check if the pci device id is supported by driver.
3442  * Return value: Actual device id if supported else PCI_ANY_ID
3443  */
3444 static u16 check_pci_device_id(u16 id)
3445 {
3446         switch (id) {
3447         case PCI_DEVICE_ID_HERC_WIN:
3448         case PCI_DEVICE_ID_HERC_UNI:
3449                 return XFRAME_II_DEVICE;
3450         case PCI_DEVICE_ID_S2IO_UNI:
3451         case PCI_DEVICE_ID_S2IO_WIN:
3452                 return XFRAME_I_DEVICE;
3453         default:
3454                 return PCI_ANY_ID;
3455         }
3456 }
3457
3458 /**
3459  *  s2io_reset - Resets the card.
3460  *  @sp : private member of the device structure.
3461  *  Description: Function to Reset the card. This function then also
3462  *  restores the previously saved PCI configuration space registers as
3463  *  the card reset also resets the configuration space.
3464  *  Return value:
3465  *  void.
3466  */
3467
3468 static void s2io_reset(struct s2io_nic *sp)
3469 {
3470         struct XENA_dev_config __iomem *bar0 = sp->bar0;
3471         u64 val64;
3472         u16 subid, pci_cmd;
3473         int i;
3474         u16 val16;
3475         unsigned long long up_cnt, down_cnt, up_time, down_time, reset_cnt;
3476         unsigned long long mem_alloc_cnt, mem_free_cnt, watchdog_cnt;
3477         struct stat_block *stats;
3478         struct swStat *swstats;
3479
3480         DBG_PRINT(INIT_DBG, "%s: Resetting XFrame card %s\n",
3481                   __func__, pci_name(sp->pdev));
3482
3483         /* Back up  the PCI-X CMD reg, dont want to lose MMRBC, OST settings */
3484         pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER, &(pci_cmd));
3485
3486         val64 = SW_RESET_ALL;
3487         writeq(val64, &bar0->sw_reset);
3488         if (strstr(sp->product_name, "CX4"))
3489                 msleep(750);
3490         msleep(250);
3491         for (i = 0; i < S2IO_MAX_PCI_CONFIG_SPACE_REINIT; i++) {
3492
3493                 /* Restore the PCI state saved during initialization. */
3494                 pci_restore_state(sp->pdev);
3495                 pci_save_state(sp->pdev);
3496                 pci_read_config_word(sp->pdev, 0x2, &val16);
3497                 if (check_pci_device_id(val16) != (u16)PCI_ANY_ID)
3498                         break;
3499                 msleep(200);
3500         }
3501
3502         if (check_pci_device_id(val16) == (u16)PCI_ANY_ID)
3503                 DBG_PRINT(ERR_DBG, "%s SW_Reset failed!\n", __func__);
3504
3505         pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER, pci_cmd);
3506
3507         s2io_init_pci(sp);
3508
3509         /* Set swapper to enable I/O register access */
3510         s2io_set_swapper(sp);
3511
3512         /* restore mac_addr entries */
3513         do_s2io_restore_unicast_mc(sp);
3514
3515         /* Restore the MSIX table entries from local variables */
3516         restore_xmsi_data(sp);
3517
3518         /* Clear certain PCI/PCI-X fields after reset */
3519         if (sp->device_type == XFRAME_II_DEVICE) {
3520                 /* Clear "detected parity error" bit */
3521                 pci_write_config_word(sp->pdev, PCI_STATUS, 0x8000);
3522
3523                 /* Clearing PCIX Ecc status register */
3524                 pci_write_config_dword(sp->pdev, 0x68, 0x7C);
3525
3526                 /* Clearing PCI_STATUS error reflected here */
3527                 writeq(s2BIT(62), &bar0->txpic_int_reg);
3528         }
3529
3530         /* Reset device statistics maintained by OS */
3531         memset(&sp->stats, 0, sizeof(struct net_device_stats));
3532
3533         stats = sp->mac_control.stats_info;
3534         swstats = &stats->sw_stat;
3535
3536         /* save link up/down time/cnt, reset/memory/watchdog cnt */
3537         up_cnt = swstats->link_up_cnt;
3538         down_cnt = swstats->link_down_cnt;
3539         up_time = swstats->link_up_time;
3540         down_time = swstats->link_down_time;
3541         reset_cnt = swstats->soft_reset_cnt;
3542         mem_alloc_cnt = swstats->mem_allocated;
3543         mem_free_cnt = swstats->mem_freed;
3544         watchdog_cnt = swstats->watchdog_timer_cnt;
3545
3546         memset(stats, 0, sizeof(struct stat_block));
3547
3548         /* restore link up/down time/cnt, reset/memory/watchdog cnt */
3549         swstats->link_up_cnt = up_cnt;
3550         swstats->link_down_cnt = down_cnt;
3551         swstats->link_up_time = up_time;
3552         swstats->link_down_time = down_time;
3553         swstats->soft_reset_cnt = reset_cnt;
3554         swstats->mem_allocated = mem_alloc_cnt;
3555         swstats->mem_freed = mem_free_cnt;
3556         swstats->watchdog_timer_cnt = watchdog_cnt;
3557
3558         /* SXE-002: Configure link and activity LED to turn it off */
3559         subid = sp->pdev->subsystem_device;
3560         if (((subid & 0xFF) >= 0x07) &&
3561             (sp->device_type == XFRAME_I_DEVICE)) {
3562                 val64 = readq(&bar0->gpio_control);
3563                 val64 |= 0x0000800000000000ULL;
3564                 writeq(val64, &bar0->gpio_control);
3565                 val64 = 0x0411040400000000ULL;
3566                 writeq(val64, (void __iomem *)bar0 + 0x2700);
3567         }
3568
3569         /*
3570          * Clear spurious ECC interrupts that would have occured on
3571          * XFRAME II cards after reset.
3572          */
3573         if (sp->device_type == XFRAME_II_DEVICE) {
3574                 val64 = readq(&bar0->pcc_err_reg);
3575                 writeq(val64, &bar0->pcc_err_reg);
3576         }
3577
3578         sp->device_enabled_once = false;
3579 }
3580
3581 /**
3582  *  s2io_set_swapper - to set the swapper controle on the card
3583  *  @sp : private member of the device structure,
3584  *  pointer to the s2io_nic structure.
3585  *  Description: Function to set the swapper control on the card
3586  *  correctly depending on the 'endianness' of the system.
3587  *  Return value:
3588  *  SUCCESS on success and FAILURE on failure.
3589  */
3590
3591 static int s2io_set_swapper(struct s2io_nic *sp)
3592 {
3593         struct net_device *dev = sp->dev;
3594         struct XENA_dev_config __iomem *bar0 = sp->bar0;
3595         u64 val64, valt, valr;
3596
3597         /*
3598          * Set proper endian settings and verify the same by reading
3599          * the PIF Feed-back register.
3600          */
3601
3602         val64 = readq(&bar0->pif_rd_swapper_fb);
3603         if (val64 != 0x0123456789ABCDEFULL) {
3604                 int i = 0;
3605                 u64 value[] = { 0xC30000C3C30000C3ULL,   /* FE=1, SE=1 */
3606                                 0x8100008181000081ULL,  /* FE=1, SE=0 */
3607                                 0x4200004242000042ULL,  /* FE=0, SE=1 */
3608                                 0};                     /* FE=0, SE=0 */
3609
3610                 while (i < 4) {
3611                         writeq(value[i], &bar0->swapper_ctrl);
3612                         val64 = readq(&bar0->pif_rd_swapper_fb);
3613                         if (val64 == 0x0123456789ABCDEFULL)
3614                                 break;
3615                         i++;
3616                 }
3617                 if (i == 4) {
3618                         DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, "
3619                                   "feedback read %llx\n",
3620                                   dev->name, (unsigned long long)val64);
3621                         return FAILURE;
3622                 }
3623                 valr = value[i];
3624         } else {
3625                 valr = readq(&bar0->swapper_ctrl);
3626         }
3627
3628         valt = 0x0123456789ABCDEFULL;
3629         writeq(valt, &bar0->xmsi_address);
3630         val64 = readq(&bar0->xmsi_address);
3631
3632         if (val64 != valt) {
3633                 int i = 0;
3634                 u64 value[] = { 0x00C3C30000C3C300ULL,  /* FE=1, SE=1 */
3635                                 0x0081810000818100ULL,  /* FE=1, SE=0 */
3636                                 0x0042420000424200ULL,  /* FE=0, SE=1 */
3637                                 0};                     /* FE=0, SE=0 */
3638
3639                 while (i < 4) {
3640                         writeq((value[i] | valr), &bar0->swapper_ctrl);
3641                         writeq(valt, &bar0->xmsi_address);
3642                         val64 = readq(&bar0->xmsi_address);
3643                         if (val64 == valt)
3644                                 break;
3645                         i++;
3646                 }
3647                 if (i == 4) {
3648                         unsigned long long x = val64;
3649                         DBG_PRINT(ERR_DBG,
3650                                   "Write failed, Xmsi_addr reads:0x%llx\n", x);
3651                         return FAILURE;
3652                 }
3653         }
3654         val64 = readq(&bar0->swapper_ctrl);
3655         val64 &= 0xFFFF000000000000ULL;
3656
3657 #ifdef __BIG_ENDIAN
3658         /*
3659          * The device by default set to a big endian format, so a
3660          * big endian driver need not set anything.
3661          */
3662         val64 |= (SWAPPER_CTRL_TXP_FE |
3663                   SWAPPER_CTRL_TXP_SE |
3664                   SWAPPER_CTRL_TXD_R_FE |
3665                   SWAPPER_CTRL_TXD_W_FE |
3666                   SWAPPER_CTRL_TXF_R_FE |
3667                   SWAPPER_CTRL_RXD_R_FE |
3668                   SWAPPER_CTRL_RXD_W_FE |
3669                   SWAPPER_CTRL_RXF_W_FE |
3670                   SWAPPER_CTRL_XMSI_FE |
3671                   SWAPPER_CTRL_STATS_FE |
3672                   SWAPPER_CTRL_STATS_SE);
3673         if (sp->config.intr_type == INTA)
3674                 val64 |= SWAPPER_CTRL_XMSI_SE;
3675         writeq(val64, &bar0->swapper_ctrl);
3676 #else
3677         /*
3678          * Initially we enable all bits to make it accessible by the
3679          * driver, then we selectively enable only those bits that
3680          * we want to set.
3681          */
3682         val64 |= (SWAPPER_CTRL_TXP_FE |
3683                   SWAPPER_CTRL_TXP_SE |
3684                   SWAPPER_CTRL_TXD_R_FE |
3685                   SWAPPER_CTRL_TXD_R_SE |
3686                   SWAPPER_CTRL_TXD_W_FE |
3687                   SWAPPER_CTRL_TXD_W_SE |
3688                   SWAPPER_CTRL_TXF_R_FE |
3689                   SWAPPER_CTRL_RXD_R_FE |
3690                   SWAPPER_CTRL_RXD_R_SE |
3691                   SWAPPER_CTRL_RXD_W_FE |
3692                   SWAPPER_CTRL_RXD_W_SE |
3693                   SWAPPER_CTRL_RXF_W_FE |
3694                   SWAPPER_CTRL_XMSI_FE |
3695                   SWAPPER_CTRL_STATS_FE |
3696                   SWAPPER_CTRL_STATS_SE);
3697         if (sp->config.intr_type == INTA)
3698                 val64 |= SWAPPER_CTRL_XMSI_SE;
3699         writeq(val64, &bar0->swapper_ctrl);
3700 #endif
3701         val64 = readq(&bar0->swapper_ctrl);
3702
3703         /*
3704          * Verifying if endian settings are accurate by reading a
3705          * feedback register.
3706          */
3707         val64 = readq(&bar0->pif_rd_swapper_fb);
3708         if (val64 != 0x0123456789ABCDEFULL) {
3709                 /* Endian settings are incorrect, calls for another dekko. */
3710                 DBG_PRINT(ERR_DBG,
3711                           "%s: Endian settings are wrong, feedback read %llx\n",
3712                           dev->name, (unsigned long long)val64);
3713                 return FAILURE;
3714         }
3715
3716         return SUCCESS;
3717 }
3718
3719 static int wait_for_msix_trans(struct s2io_nic *nic, int i)
3720 {
3721         struct XENA_dev_config __iomem *bar0 = nic->bar0;
3722         u64 val64;
3723         int ret = 0, cnt = 0;
3724
3725         do {
3726                 val64 = readq(&bar0->xmsi_access);
3727                 if (!(val64 & s2BIT(15)))
3728                         break;
3729                 mdelay(1);
3730                 cnt++;
3731         } while (cnt < 5);
3732         if (cnt == 5) {
3733                 DBG_PRINT(ERR_DBG, "XMSI # %d Access failed\n", i);
3734                 ret = 1;
3735         }
3736
3737         return ret;
3738 }
3739
3740 static void restore_xmsi_data(struct s2io_nic *nic)
3741 {
3742         struct XENA_dev_config __iomem *bar0 = nic->bar0;
3743         u64 val64;
3744         int i, msix_index;
3745
3746         if (nic->device_type == XFRAME_I_DEVICE)
3747                 return;
3748
3749         for (i = 0; i < MAX_REQUESTED_MSI_X; i++) {
3750                 msix_index = (i) ? ((i-1) * 8 + 1) : 0;
3751                 writeq(nic->msix_info[i].addr, &bar0->xmsi_address);
3752                 writeq(nic->msix_info[i].data, &bar0->xmsi_data);
3753                 val64 = (s2BIT(7) | s2BIT(15) | vBIT(msix_index, 26, 6));
3754                 writeq(val64, &bar0->xmsi_access);
3755                 if (wait_for_msix_trans(nic, msix_index)) {
3756                         DBG_PRINT(ERR_DBG, "%s: index: %d failed\n",
3757                                   __func__, msix_index);
3758                         continue;
3759                 }
3760         }
3761 }
3762
3763 static void store_xmsi_data(struct s2io_nic *nic)
3764 {
3765         struct XENA_dev_config __iomem *bar0 = nic->bar0;
3766         u64 val64, addr, data;
3767         int i, msix_index;
3768
3769         if (nic->device_type == XFRAME_I_DEVICE)
3770                 return;
3771
3772         /* Store and display */
3773         for (i = 0; i < MAX_REQUESTED_MSI_X; i++) {
3774                 msix_index = (i) ? ((i-1) * 8 + 1) : 0;
3775                 val64 = (s2BIT(15) | vBIT(msix_index, 26, 6));
3776                 writeq(val64, &bar0->xmsi_access);
3777                 if (wait_for_msix_trans(nic, msix_index)) {
3778                         DBG_PRINT(ERR_DBG, "%s: index: %d failed\n",
3779                                   __func__, msix_index);
3780                         continue;
3781                 }
3782                 addr = readq(&bar0->xmsi_address);
3783                 data = readq(&bar0->xmsi_data);
3784                 if (addr && data) {
3785                         nic->msix_info[i].addr = addr;
3786                         nic->msix_info[i].data = data;
3787                 }
3788         }
3789 }
3790
3791 static int s2io_enable_msi_x(struct s2io_nic *nic)
3792 {
3793         struct XENA_dev_config __iomem *bar0 = nic->bar0;
3794         u64 rx_mat;
3795         u16 msi_control; /* Temp variable */
3796         int ret, i, j, msix_indx = 1;
3797         int size;
3798         struct stat_block *stats = nic->mac_control.stats_info;
3799         struct swStat *swstats = &stats->sw_stat;
3800
3801         size = nic->num_entries * sizeof(struct msix_entry);
3802         nic->entries = kzalloc(size, GFP_KERNEL);
3803         if (!nic->entries) {
3804                 DBG_PRINT(INFO_DBG, "%s: Memory allocation failed\n",
3805                           __func__);
3806                 swstats->mem_alloc_fail_cnt++;
3807                 return -ENOMEM;
3808         }
3809         swstats->mem_allocated += size;
3810
3811         size = nic->num_entries * sizeof(struct s2io_msix_entry);
3812         nic->s2io_entries = kzalloc(size, GFP_KERNEL);
3813         if (!nic->s2io_entries) {
3814                 DBG_PRINT(INFO_DBG, "%s: Memory allocation failed\n",
3815                           __func__);
3816                 swstats->mem_alloc_fail_cnt++;
3817                 kfree(nic->entries);
3818                 swstats->mem_freed
3819                         += (nic->num_entries * sizeof(struct msix_entry));
3820                 return -ENOMEM;
3821         }
3822         swstats->mem_allocated += size;
3823
3824         nic->entries[0].entry = 0;
3825         nic->s2io_entries[0].entry = 0;
3826         nic->s2io_entries[0].in_use = MSIX_FLG;
3827         nic->s2io_entries[0].type = MSIX_ALARM_TYPE;
3828         nic->s2io_entries[0].arg = &nic->mac_control.fifos;
3829
3830         for (i = 1; i < nic->num_entries; i++) {
3831                 nic->entries[i].entry = ((i - 1) * 8) + 1;
3832                 nic->s2io_entries[i].entry = ((i - 1) * 8) + 1;
3833                 nic->s2io_entries[i].arg = NULL;
3834                 nic->s2io_entries[i].in_use = 0;
3835         }
3836
3837         rx_mat = readq(&bar0->rx_mat);
3838         for (j = 0; j < nic->config.rx_ring_num; j++) {
3839                 rx_mat |= RX_MAT_SET(j, msix_indx);
3840                 nic->s2io_entries[j+1].arg = &nic->mac_control.rings[j];
3841                 nic->s2io_entries[j+1].type = MSIX_RING_TYPE;
3842                 nic->s2io_entries[j+1].in_use = MSIX_FLG;
3843                 msix_indx += 8;
3844         }
3845         writeq(rx_mat, &bar0->rx_mat);
3846         readq(&bar0->rx_mat);
3847
3848         ret = pci_enable_msix(nic->pdev, nic->entries, nic->num_entries);
3849         /* We fail init if error or we get less vectors than min required */
3850         if (ret) {
3851                 DBG_PRINT(ERR_DBG, "Enabling MSI-X failed\n");
3852                 kfree(nic->entries);
3853                 swstats->mem_freed += nic->num_entries *
3854                         sizeof(struct msix_entry);
3855                 kfree(nic->s2io_entries);
3856                 swstats->mem_freed += nic->num_entries *
3857                         sizeof(struct s2io_msix_entry);
3858                 nic->entries = NULL;
3859                 nic->s2io_entries = NULL;
3860                 return -ENOMEM;
3861         }
3862
3863         /*
3864          * To enable MSI-X, MSI also needs to be enabled, due to a bug
3865          * in the herc NIC. (Temp change, needs to be removed later)
3866          */
3867         pci_read_config_word(nic->pdev, 0x42, &msi_control);
3868         msi_control |= 0x1; /* Enable MSI */
3869         pci_write_config_word(nic->pdev, 0x42, msi_control);
3870
3871         return 0;
3872 }
3873
3874 /* Handle software interrupt used during MSI(X) test */
3875 static irqreturn_t s2io_test_intr(int irq, void *dev_id)
3876 {
3877         struct s2io_nic *sp = dev_id;
3878
3879         sp->msi_detected = 1;
3880         wake_up(&sp->msi_wait);
3881
3882         return IRQ_HANDLED;
3883 }
3884
3885 /* Test interrupt path by forcing a a software IRQ */
3886 static int s2io_test_msi(struct s2io_nic *sp)
3887 {
3888         struct pci_dev *pdev = sp->pdev;
3889         struct XENA_dev_config __iomem *bar0 = sp->bar0;
3890         int err;
3891         u64 val64, saved64;
3892
3893         err = request_irq(sp->entries[1].vector, s2io_test_intr, 0,
3894                           sp->name, sp);
3895         if (err) {
3896                 DBG_PRINT(ERR_DBG, "%s: PCI %s: cannot assign irq %d\n",
3897                           sp->dev->name, pci_name(pdev), pdev->irq);
3898                 return err;
3899         }
3900
3901         init_waitqueue_head(&sp->msi_wait);
3902         sp->msi_detected = 0;
3903
3904         saved64 = val64 = readq(&bar0->scheduled_int_ctrl);
3905         val64 |= SCHED_INT_CTRL_ONE_SHOT;
3906         val64 |= SCHED_INT_CTRL_TIMER_EN;
3907         val64 |= SCHED_INT_CTRL_INT2MSI(1);
3908         writeq(val64, &bar0->scheduled_int_ctrl);
3909
3910         wait_event_timeout(sp->msi_wait, sp->msi_detected, HZ/10);
3911
3912         if (!sp->msi_detected) {
3913                 /* MSI(X) test failed, go back to INTx mode */
3914                 DBG_PRINT(ERR_DBG, "%s: PCI %s: No interrupt was generated "
3915                           "using MSI(X) during test\n",
3916                           sp->dev->name, pci_name(pdev));
3917
3918                 err = -EOPNOTSUPP;
3919         }
3920
3921         free_irq(sp->entries[1].vector, sp);
3922
3923         writeq(saved64, &bar0->scheduled_int_ctrl);
3924
3925         return err;
3926 }
3927
3928 static void remove_msix_isr(struct s2io_nic *sp)
3929 {
3930         int i;
3931         u16 msi_control;
3932
3933         for (i = 0; i < sp->num_entries; i++) {
3934                 if (sp->s2io_entries[i].in_use == MSIX_REGISTERED_SUCCESS) {
3935                         int vector = sp->entries[i].vector;
3936                         void *arg = sp->s2io_entries[i].arg;
3937                         free_irq(vector, arg);
3938                 }
3939         }
3940
3941         kfree(sp->entries);
3942         kfree(sp->s2io_entries);
3943         sp->entries = NULL;
3944         sp->s2io_entries = NULL;
3945
3946         pci_read_config_word(sp->pdev, 0x42, &msi_control);
3947         msi_control &= 0xFFFE; /* Disable MSI */
3948         pci_write_config_word(sp->pdev, 0x42, msi_control);
3949
3950         pci_disable_msix(sp->pdev);
3951 }
3952
3953 static void remove_inta_isr(struct s2io_nic *sp)
3954 {
3955         struct net_device *dev = sp->dev;
3956
3957         free_irq(sp->pdev->irq, dev);
3958 }
3959
3960 /* ********************************************************* *
3961  * Functions defined below concern the OS part of the driver *
3962  * ********************************************************* */
3963
3964 /**
3965  *  s2io_open - open entry point of the driver
3966  *  @dev : pointer to the device structure.
3967  *  Description:
3968  *  This function is the open entry point of the driver. It mainly calls a
3969  *  function to allocate Rx buffers and inserts them into the buffer
3970  *  descriptors and then enables the Rx part of the NIC.
3971  *  Return value:
3972  *  0 on success and an appropriate (-)ve integer as defined in errno.h
3973  *   file on failure.
3974  */
3975
3976 static int s2io_open(struct net_device *dev)
3977 {
3978         struct s2io_nic *sp = netdev_priv(dev);
3979         struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
3980         int err = 0;
3981
3982         /*
3983          * Make sure you have link off by default every time
3984          * Nic is initialized
3985          */
3986         netif_carrier_off(dev);
3987         sp->last_link_state = 0;
3988
3989         /* Initialize H/W and enable interrupts */
3990         err = s2io_card_up(sp);
3991         if (err) {
3992                 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
3993                           dev->name);
3994                 goto hw_init_failed;
3995         }
3996
3997         if (do_s2io_prog_unicast(dev, dev->dev_addr) == FAILURE) {
3998                 DBG_PRINT(ERR_DBG, "Set Mac Address Failed\n");
3999                 s2io_card_down(sp);
4000                 err = -ENODEV;
4001                 goto hw_init_failed;
4002         }
4003         s2io_start_all_tx_queue(sp);
4004         return 0;
4005
4006 hw_init_failed:
4007         if (sp->config.intr_type == MSI_X) {
4008                 if (sp->entries) {
4009                         kfree(sp->entries);
4010                         swstats->mem_freed += sp->num_entries *
4011                                 sizeof(struct msix_entry);
4012                 }
4013                 if (sp->s2io_entries) {
4014                         kfree(sp->s2io_entries);
4015                         swstats->mem_freed += sp->num_entries *
4016                                 sizeof(struct s2io_msix_entry);
4017                 }
4018         }
4019         return err;
4020 }
4021
4022 /**
4023  *  s2io_close -close entry point of the driver
4024  *  @dev : device pointer.
4025  *  Description:
4026  *  This is the stop entry point of the driver. It needs to undo exactly
4027  *  whatever was done by the open entry point,thus it's usually referred to
4028  *  as the close function.Among other things this function mainly stops the
4029  *  Rx side of the NIC and frees all the Rx buffers in the Rx rings.
4030  *  Return value:
4031  *  0 on success and an appropriate (-)ve integer as defined in errno.h
4032  *  file on failure.
4033  */
4034
4035 static int s2io_close(struct net_device *dev)
4036 {
4037         struct s2io_nic *sp = netdev_priv(dev);
4038         struct config_param *config = &sp->config;
4039         u64 tmp64;
4040         int offset;
4041
4042         /* Return if the device is already closed               *
4043          *  Can happen when s2io_card_up failed in change_mtu    *
4044          */
4045         if (!is_s2io_card_up(sp))
4046                 return 0;
4047
4048         s2io_stop_all_tx_queue(sp);
4049         /* delete all populated mac entries */
4050         for (offset = 1; offset < config->max_mc_addr; offset++) {
4051                 tmp64 = do_s2io_read_unicast_mc(sp, offset);
4052                 if (tmp64 != S2IO_DISABLE_MAC_ENTRY)
4053                         do_s2io_delete_unicast_mc(sp, tmp64);
4054         }
4055
4056         s2io_card_down(sp);
4057
4058         return 0;
4059 }
4060
4061 /**
4062  *  s2io_xmit - Tx entry point of te driver
4063  *  @skb : the socket buffer containing the Tx data.
4064  *  @dev : device pointer.
4065  *  Description :
4066  *  This function is the Tx entry point of the driver. S2IO NIC supports
4067  *  certain protocol assist features on Tx side, namely  CSO, S/G, LSO.
4068  *  NOTE: when device cant queue the pkt,just the trans_start variable will
4069  *  not be upadted.
4070  *  Return value:
4071  *  0 on success & 1 on failure.
4072  */
4073
4074 static netdev_tx_t s2io_xmit(struct sk_buff *skb, struct net_device *dev)
4075 {
4076         struct s2io_nic *sp = netdev_priv(dev);
4077         u16 frg_cnt, frg_len, i, queue, queue_len, put_off, get_off;
4078         register u64 val64;
4079         struct TxD *txdp;
4080         struct TxFIFO_element __iomem *tx_fifo;
4081         unsigned long flags = 0;
4082         u16 vlan_tag = 0;
4083         struct fifo_info *fifo = NULL;
4084         int do_spin_lock = 1;
4085         int offload_type;
4086         int enable_per_list_interrupt = 0;
4087         struct config_param *config = &sp->config;
4088         struct mac_info *mac_control = &sp->mac_control;
4089         struct stat_block *stats = mac_control->stats_info;
4090         struct swStat *swstats = &stats->sw_stat;
4091
4092         DBG_PRINT(TX_DBG, "%s: In Neterion Tx routine\n", dev->name);
4093
4094         if (unlikely(skb->len <= 0)) {
4095                 DBG_PRINT(TX_DBG, "%s: Buffer has no data..\n", dev->name);
4096                 dev_kfree_skb_any(skb);
4097                 return NETDEV_TX_OK;
4098         }
4099
4100         if (!is_s2io_card_up(sp)) {
4101                 DBG_PRINT(TX_DBG, "%s: Card going down for reset\n",
4102                           dev->name);
4103                 dev_kfree_skb(skb);
4104                 return NETDEV_TX_OK;
4105         }
4106
4107         queue = 0;
4108         if (sp->vlgrp && vlan_tx_tag_present(skb))
4109                 vlan_tag = vlan_tx_tag_get(skb);
4110         if (sp->config.tx_steering_type == TX_DEFAULT_STEERING) {
4111                 if (skb->protocol == htons(ETH_P_IP)) {
4112                         struct iphdr *ip;
4113                         struct tcphdr *th;
4114                         ip = ip_hdr(skb);
4115
4116                         if ((ip->frag_off & htons(IP_OFFSET|IP_MF)) == 0) {
4117                                 th = (struct tcphdr *)(((unsigned char *)ip) +
4118                                                        ip->ihl*4);
4119
4120                                 if (ip->protocol == IPPROTO_TCP) {
4121                                         queue_len = sp->total_tcp_fifos;
4122                                         queue = (ntohs(th->source) +
4123                                                  ntohs(th->dest)) &
4124                                                 sp->fifo_selector[queue_len - 1];
4125                                         if (queue >= queue_len)
4126                                                 queue = queue_len - 1;
4127                                 } else if (ip->protocol == IPPROTO_UDP) {
4128                                         queue_len = sp->total_udp_fifos;
4129                                         queue = (ntohs(th->source) +
4130                                                  ntohs(th->dest)) &
4131                                                 sp->fifo_selector[queue_len - 1];
4132                                         if (queue >= queue_len)
4133                                                 queue = queue_len - 1;
4134                                         queue += sp->udp_fifo_idx;
4135                                         if (skb->len > 1024)
4136                                                 enable_per_list_interrupt = 1;
4137                                         do_spin_lock = 0;
4138                                 }
4139                         }
4140                 }
4141         } else if (sp->config.tx_steering_type == TX_PRIORITY_STEERING)
4142                 /* get fifo number based on skb->priority value */
4143                 queue = config->fifo_mapping
4144                         [skb->priority & (MAX_TX_FIFOS - 1)];
4145         fifo = &mac_control->fifos[queue];
4146
4147         if (do_spin_lock)
4148                 spin_lock_irqsave(&fifo->tx_lock, flags);
4149         else {
4150                 if (unlikely(!spin_trylock_irqsave(&fifo->tx_lock, flags)))
4151                         return NETDEV_TX_LOCKED;
4152         }
4153
4154         if (sp->config.multiq) {
4155                 if (__netif_subqueue_stopped(dev, fifo->fifo_no)) {
4156                         spin_unlock_irqrestore(&fifo->tx_lock, flags);
4157                         return NETDEV_TX_BUSY;
4158                 }
4159         } else if (unlikely(fifo->queue_state == FIFO_QUEUE_STOP)) {
4160                 if (netif_queue_stopped(dev)) {
4161                         spin_unlock_irqrestore(&fifo->tx_lock, flags);
4162                         return NETDEV_TX_BUSY;
4163                 }
4164         }
4165
4166         put_off = (u16)fifo->tx_curr_put_info.offset;
4167         get_off = (u16)fifo->tx_curr_get_info.offset;
4168         txdp = (struct TxD *)fifo->list_info[put_off].list_virt_addr;
4169
4170         queue_len = fifo->tx_curr_put_info.fifo_len + 1;
4171         /* Avoid "put" pointer going beyond "get" pointer */
4172         if (txdp->Host_Control ||
4173             ((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
4174                 DBG_PRINT(TX_DBG, "Error in xmit, No free TXDs.\n");
4175                 s2io_stop_tx_queue(sp, fifo->fifo_no);
4176                 dev_kfree_skb(skb);
4177                 spin_unlock_irqrestore(&fifo->tx_lock, flags);
4178                 return NETDEV_TX_OK;
4179         }
4180
4181         offload_type = s2io_offload_type(skb);
4182         if (offload_type & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
4183                 txdp->Control_1 |= TXD_TCP_LSO_EN;
4184                 txdp->Control_1 |= TXD_TCP_LSO_MSS(s2io_tcp_mss(skb));
4185         }
4186         if (skb->ip_summed == CHECKSUM_PARTIAL) {
4187                 txdp->Control_2 |= (TXD_TX_CKO_IPV4_EN |
4188                                     TXD_TX_CKO_TCP_EN |
4189                                     TXD_TX_CKO_UDP_EN);
4190         }
4191         txdp->Control_1 |= TXD_GATHER_CODE_FIRST;
4192         txdp->Control_1 |= TXD_LIST_OWN_XENA;
4193         txdp->Control_2 |= TXD_INT_NUMBER(fifo->fifo_no);
4194         if (enable_per_list_interrupt)
4195                 if (put_off & (queue_len >> 5))
4196                         txdp->Control_2 |= TXD_INT_TYPE_PER_LIST;
4197         if (vlan_tag) {
4198                 txdp->Control_2 |= TXD_VLAN_ENABLE;
4199                 txdp->Control_2 |= TXD_VLAN_TAG(vlan_tag);
4200         }
4201
4202         frg_len = skb_headlen(skb);
4203         if (offload_type == SKB_GSO_UDP) {
4204                 int ufo_size;
4205
4206                 ufo_size = s2io_udp_mss(skb);
4207                 ufo_size &= ~7;
4208                 txdp->Control_1 |= TXD_UFO_EN;
4209                 txdp->Control_1 |= TXD_UFO_MSS(ufo_size);
4210                 txdp->Control_1 |= TXD_BUFFER0_SIZE(8);
4211 #ifdef __BIG_ENDIAN
4212                 /* both variants do cpu_to_be64(be32_to_cpu(...)) */
4213                 fifo->ufo_in_band_v[put_off] =
4214                         (__force u64)skb_shinfo(skb)->ip6_frag_id;
4215 #else
4216                 fifo->ufo_in_band_v[put_off] =
4217                         (__force u64)skb_shinfo(skb)->ip6_frag_id << 32;
4218 #endif
4219                 txdp->Host_Control = (unsigned long)fifo->ufo_in_band_v;
4220                 txdp->Buffer_Pointer = pci_map_single(sp->pdev,
4221                                                       fifo->ufo_in_band_v,
4222                                                       sizeof(u64),
4223                                                       PCI_DMA_TODEVICE);
4224                 if (pci_dma_mapping_error(sp->pdev, txdp->Buffer_Pointer))
4225                         goto pci_map_failed;
4226                 txdp++;
4227         }
4228
4229         txdp->Buffer_Pointer = pci_map_single(sp->pdev, skb->data,
4230                                               frg_len, PCI_DMA_TODEVICE);
4231         if (pci_dma_mapping_error(sp->pdev, txdp->Buffer_Pointer))
4232                 goto pci_map_failed;
4233
4234         txdp->Host_Control = (unsigned long)skb;
4235         txdp->Control_1 |= TXD_BUFFER0_SIZE(frg_len);
4236         if (offload_type == SKB_GSO_UDP)
4237                 txdp->Control_1 |= TXD_UFO_EN;
4238
4239         frg_cnt = skb_shinfo(skb)->nr_frags;
4240         /* For fragmented SKB. */
4241         for (i = 0; i < frg_cnt; i++) {
4242                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4243                 /* A '0' length fragment will be ignored */
4244                 if (!frag->size)
4245                         continue;
4246                 txdp++;
4247                 txdp->Buffer_Pointer = (u64)pci_map_page(sp->pdev, frag->page,
4248                                                          frag->page_offset,
4249                                                          frag->size,
4250                                                          PCI_DMA_TODEVICE);
4251                 txdp->Control_1 = TXD_BUFFER0_SIZE(frag->size);
4252                 if (offload_type == SKB_GSO_UDP)
4253                         txdp->Control_1 |= TXD_UFO_EN;
4254         }
4255         txdp->Control_1 |= TXD_GATHER_CODE_LAST;
4256
4257         if (offload_type == SKB_GSO_UDP)
4258                 frg_cnt++; /* as Txd0 was used for inband header */
4259
4260         tx_fifo = mac_control->tx_FIFO_start[queue];
4261         val64 = fifo->list_info[put_off].list_phy_addr;
4262         writeq(val64, &tx_fifo->TxDL_Pointer);
4263
4264         val64 = (TX_FIFO_LAST_TXD_NUM(frg_cnt) | TX_FIFO_FIRST_LIST |
4265                  TX_FIFO_LAST_LIST);
4266         if (offload_type)
4267                 val64 |= TX_FIFO_SPECIAL_FUNC;
4268
4269         writeq(val64, &tx_fifo->List_Control);
4270
4271         mmiowb();
4272
4273         put_off++;
4274         if (put_off == fifo->tx_curr_put_info.fifo_len + 1)
4275                 put_off = 0;
4276         fifo->tx_curr_put_info.offset = put_off;
4277
4278         /* Avoid "put" pointer going beyond "get" pointer */
4279         if (((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
4280                 swstats->fifo_full_cnt++;
4281                 DBG_PRINT(TX_DBG,
4282                           "No free TxDs for xmit, Put: 0x%x Get:0x%x\n",
4283                           put_off, get_off);
4284                 s2io_stop_tx_queue(sp, fifo->fifo_no);
4285         }
4286         swstats->mem_allocated += skb->truesize;
4287         spin_unlock_irqrestore(&fifo->tx_lock, flags);
4288
4289         if (sp->config.intr_type == MSI_X)
4290                 tx_intr_handler(fifo);
4291
4292         return NETDEV_TX_OK;
4293
4294 pci_map_failed:
4295         swstats->pci_map_fail_cnt++;
4296         s2io_stop_tx_queue(sp, fifo->fifo_no);
4297         swstats->mem_freed += skb->truesize;
4298         dev_kfree_skb(skb);
4299         spin_unlock_irqrestore(&fifo->tx_lock, flags);
4300         return NETDEV_TX_OK;
4301 }
4302
4303 static void
4304 s2io_alarm_handle(unsigned long data)
4305 {
4306         struct s2io_nic *sp = (struct s2io_nic *)data;
4307         struct net_device *dev = sp->dev;
4308
4309         s2io_handle_errors(dev);
4310         mod_timer(&sp->alarm_timer, jiffies + HZ / 2);
4311 }
4312
4313 static irqreturn_t s2io_msix_ring_handle(int irq, void *dev_id)
4314 {
4315         struct ring_info *ring = (struct ring_info *)dev_id;
4316         struct s2io_nic *sp = ring->nic;
4317         struct XENA_dev_config __iomem *bar0 = sp->bar0;
4318
4319         if (unlikely(!is_s2io_card_up(sp)))
4320                 return IRQ_HANDLED;
4321
4322         if (sp->config.napi) {
4323                 u8 __iomem *addr = NULL;
4324                 u8 val8 = 0;
4325
4326                 addr = (u8 __iomem *)&bar0->xmsi_mask_reg;
4327                 addr += (7 - ring->ring_no);
4328                 val8 = (ring->ring_no == 0) ? 0x7f : 0xff;
4329                 writeb(val8, addr);
4330                 val8 = readb(addr);
4331                 napi_schedule(&ring->napi);
4332         } else {
4333                 rx_intr_handler(ring, 0);
4334                 s2io_chk_rx_buffers(sp, ring);
4335         }
4336
4337         return IRQ_HANDLED;
4338 }
4339
4340 static irqreturn_t s2io_msix_fifo_handle(int irq, void *dev_id)
4341 {
4342         int i;
4343         struct fifo_info *fifos = (struct fifo_info *)dev_id;
4344         struct s2io_nic *sp = fifos->nic;
4345         struct XENA_dev_config __iomem *bar0 = sp->bar0;
4346         struct config_param *config  = &sp->config;
4347         u64 reason;
4348
4349         if (unlikely(!is_s2io_card_up(sp)))
4350                 return IRQ_NONE;
4351
4352         reason = readq(&bar0->general_int_status);
4353         if (unlikely(reason == S2IO_MINUS_ONE))
4354                 /* Nothing much can be done. Get out */
4355                 return IRQ_HANDLED;
4356
4357         if (reason & (GEN_INTR_TXPIC | GEN_INTR_TXTRAFFIC)) {
4358                 writeq(S2IO_MINUS_ONE, &bar0->general_int_mask);
4359
4360                 if (reason & GEN_INTR_TXPIC)
4361                         s2io_txpic_intr_handle(sp);
4362
4363                 if (reason & GEN_INTR_TXTRAFFIC)
4364                         writeq(S2IO_MINUS_ONE, &bar0->tx_traffic_int);
4365
4366                 for (i = 0; i < config->tx_fifo_num; i++)
4367                         tx_intr_handler(&fifos[i]);
4368
4369                 writeq(sp->general_int_mask, &bar0->general_int_mask);
4370                 readl(&bar0->general_int_status);
4371                 return IRQ_HANDLED;
4372         }
4373         /* The interrupt was not raised by us */
4374         return IRQ_NONE;
4375 }
4376
4377 static void s2io_txpic_intr_handle(struct s2io_nic *sp)
4378 {
4379         struct XENA_dev_config __iomem *bar0 = sp->bar0;
4380         u64 val64;
4381
4382         val64 = readq(&bar0->pic_int_status);
4383         if (val64 & PIC_INT_GPIO) {
4384                 val64 = readq(&bar0->gpio_int_reg);
4385                 if ((val64 & GPIO_INT_REG_LINK_DOWN) &&
4386                     (val64 & GPIO_INT_REG_LINK_UP)) {
4387                         /*
4388                          * This is unstable state so clear both up/down
4389                          * interrupt and adapter to re-evaluate the link state.
4390                          */
4391                         val64 |= GPIO_INT_REG_LINK_DOWN;
4392                         val64 |= GPIO_INT_REG_LINK_UP;
4393                         writeq(val64, &bar0->gpio_int_reg);
4394                         val64 = readq(&bar0->gpio_int_mask);
4395                         val64 &= ~(GPIO_INT_MASK_LINK_UP |
4396                                    GPIO_INT_MASK_LINK_DOWN);
4397                         writeq(val64, &bar0->gpio_int_mask);
4398                 } else if (val64 & GPIO_INT_REG_LINK_UP) {
4399                         val64 = readq(&bar0->adapter_status);
4400                         /* Enable Adapter */
4401                         val64 = readq(&bar0->adapter_control);
4402                         val64 |= ADAPTER_CNTL_EN;
4403                         writeq(val64, &bar0->adapter_control);
4404                         val64 |= ADAPTER_LED_ON;
4405                         writeq(val64, &bar0->adapter_control);
4406                         if (!sp->device_enabled_once)
4407                                 sp->device_enabled_once = 1;
4408
4409                         s2io_link(sp, LINK_UP);
4410                         /*
4411                          * unmask link down interrupt and mask link-up
4412                          * intr
4413                          */
4414                         val64 = readq(&bar0->gpio_int_mask);
4415                         val64 &= ~GPIO_INT_MASK_LINK_DOWN;
4416                         val64 |= GPIO_INT_MASK_LINK_UP;
4417                         writeq(val64, &bar0->gpio_int_mask);
4418
4419                 } else if (val64 & GPIO_INT_REG_LINK_DOWN) {
4420                         val64 = readq(&bar0->adapter_status);
4421                         s2io_link(sp, LINK_DOWN);
4422                         /* Link is down so unmaks link up interrupt */
4423                         val64 = readq(&bar0->gpio_int_mask);
4424                         val64 &= ~GPIO_INT_MASK_LINK_UP;
4425                         val64 |= GPIO_INT_MASK_LINK_DOWN;
4426                         writeq(val64, &bar0->gpio_int_mask);
4427
4428                         /* turn off LED */
4429                         val64 = readq(&bar0->adapter_control);
4430                         val64 = val64 & (~ADAPTER_LED_ON);
4431                         writeq(val64, &bar0->adapter_control);
4432                 }
4433         }
4434         val64 = readq(&bar0->gpio_int_mask);
4435 }
4436
4437 /**
4438  *  do_s2io_chk_alarm_bit - Check for alarm and incrment the counter
4439  *  @value: alarm bits
4440  *  @addr: address value
4441  *  @cnt: counter variable
4442  *  Description: Check for alarm and increment the counter
4443  *  Return Value:
4444  *  1 - if alarm bit set
4445  *  0 - if alarm bit is not set
4446  */
4447 static int do_s2io_chk_alarm_bit(u64 value, void __iomem *addr,
4448                                  unsigned long long *cnt)
4449 {
4450         u64 val64;
4451         val64 = readq(addr);
4452         if (val64 & value) {
4453                 writeq(val64, addr);
4454                 (*cnt)++;
4455                 return 1;
4456         }
4457         return 0;
4458
4459 }
4460
4461 /**
4462  *  s2io_handle_errors - Xframe error indication handler
4463  *  @nic: device private variable
4464  *  Description: Handle alarms such as loss of link, single or
4465  *  double ECC errors, critical and serious errors.
4466  *  Return Value:
4467  *  NONE
4468  */
4469 static void s2io_handle_errors(void *dev_id)
4470 {
4471         struct net_device *dev = (struct net_device *)dev_id;
4472         struct s2io_nic *sp = netdev_priv(dev);
4473         struct XENA_dev_config __iomem *bar0 = sp->bar0;
4474         u64 temp64 = 0, val64 = 0;
4475         int i = 0;
4476
4477         struct swStat *sw_stat = &sp->mac_control.stats_info->sw_stat;
4478         struct xpakStat *stats = &sp->mac_control.stats_info->xpak_stat;
4479
4480         if (!is_s2io_card_up(sp))
4481                 return;
4482
4483         if (pci_channel_offline(sp->pdev))
4484                 return;
4485
4486         memset(&sw_stat->ring_full_cnt, 0,
4487                sizeof(sw_stat->ring_full_cnt));
4488
4489         /* Handling the XPAK counters update */
4490         if (stats->xpak_timer_count < 72000) {
4491                 /* waiting for an hour */
4492                 stats->xpak_timer_count++;
4493         } else {
4494                 s2io_updt_xpak_counter(dev);
4495                 /* reset the count to zero */
4496                 stats->xpak_timer_count = 0;
4497         }
4498
4499         /* Handling link status change error Intr */
4500         if (s2io_link_fault_indication(sp) == MAC_RMAC_ERR_TIMER) {
4501                 val64 = readq(&bar0->mac_rmac_err_reg);
4502                 writeq(val64, &bar0->mac_rmac_err_reg);
4503                 if (val64 & RMAC_LINK_STATE_CHANGE_INT)
4504                         schedule_work(&sp->set_link_task);
4505         }
4506
4507         /* In case of a serious error, the device will be Reset. */
4508         if (do_s2io_chk_alarm_bit(SERR_SOURCE_ANY, &bar0->serr_source,
4509                                   &sw_stat->serious_err_cnt))
4510                 goto reset;
4511
4512         /* Check for data parity error */
4513         if (do_s2io_chk_alarm_bit(GPIO_INT_REG_DP_ERR_INT, &bar0->gpio_int_reg,
4514                                   &sw_stat->parity_err_cnt))
4515                 goto reset;
4516
4517         /* Check for ring full counter */
4518         if (sp->device_type == XFRAME_II_DEVICE) {
4519                 val64 = readq(&bar0->ring_bump_counter1);
4520                 for (i = 0; i < 4; i++) {
4521                         temp64 = (val64 & vBIT(0xFFFF, (i*16), 16));
4522                         temp64 >>= 64 - ((i+1)*16);
4523                         sw_stat->ring_full_cnt[i] += temp64;
4524                 }
4525
4526                 val64 = readq(&bar0->ring_bump_counter2);
4527                 for (i = 0; i < 4; i++) {
4528                         temp64 = (val64 & vBIT(0xFFFF, (i*16), 16));
4529                         temp64 >>= 64 - ((i+1)*16);
4530                         sw_stat->ring_full_cnt[i+4] += temp64;
4531                 }
4532         }
4533
4534         val64 = readq(&bar0->txdma_int_status);
4535         /*check for pfc_err*/
4536         if (val64 & TXDMA_PFC_INT) {
4537                 if (do_s2io_chk_alarm_bit(PFC_ECC_DB_ERR | PFC_SM_ERR_ALARM |
4538                                           PFC_MISC_0_ERR | PFC_MISC_1_ERR |
4539                                           PFC_PCIX_ERR,
4540                                           &bar0->pfc_err_reg,
4541                                           &sw_stat->pfc_err_cnt))
4542                         goto reset;
4543                 do_s2io_chk_alarm_bit(PFC_ECC_SG_ERR,
4544                                       &bar0->pfc_err_reg,
4545                                       &sw_stat->pfc_err_cnt);
4546         }
4547
4548         /*check for tda_err*/
4549         if (val64 & TXDMA_TDA_INT) {
4550                 if (do_s2io_chk_alarm_bit(TDA_Fn_ECC_DB_ERR |
4551                                           TDA_SM0_ERR_ALARM |
4552                                           TDA_SM1_ERR_ALARM,
4553                                           &bar0->tda_err_reg,
4554                                           &sw_stat->tda_err_cnt))
4555                         goto reset;
4556                 do_s2io_chk_alarm_bit(TDA_Fn_ECC_SG_ERR | TDA_PCIX_ERR,
4557                                       &bar0->tda_err_reg,
4558                                       &sw_stat->tda_err_cnt);
4559         }
4560         /*check for pcc_err*/
4561         if (val64 & TXDMA_PCC_INT) {
4562                 if (do_s2io_chk_alarm_bit(PCC_SM_ERR_ALARM | PCC_WR_ERR_ALARM |
4563                                           PCC_N_SERR | PCC_6_COF_OV_ERR |
4564                                           PCC_7_COF_OV_ERR | PCC_6_LSO_OV_ERR |
4565                                           PCC_7_LSO_OV_ERR | PCC_FB_ECC_DB_ERR |
4566                                           PCC_TXB_ECC_DB_ERR,
4567                                           &bar0->pcc_err_reg,
4568                                           &sw_stat->pcc_err_cnt))
4569                         goto reset;
4570                 do_s2io_chk_alarm_bit(PCC_FB_ECC_SG_ERR | PCC_TXB_ECC_SG_ERR,
4571                                       &bar0->pcc_err_reg,
4572                                       &sw_stat->pcc_err_cnt);
4573         }
4574
4575         /*check for tti_err*/
4576         if (val64 & TXDMA_TTI_INT) {
4577                 if (do_s2io_chk_alarm_bit(TTI_SM_ERR_ALARM,
4578                                           &bar0->tti_err_reg,
4579                                           &sw_stat->tti_err_cnt))
4580                         goto reset;
4581                 do_s2io_chk_alarm_bit(TTI_ECC_SG_ERR | TTI_ECC_DB_ERR,
4582                                       &bar0->tti_err_reg,
4583                                       &sw_stat->tti_err_cnt);
4584         }
4585
4586         /*check for lso_err*/
4587         if (val64 & TXDMA_LSO_INT) {
4588                 if (do_s2io_chk_alarm_bit(LSO6_ABORT | LSO7_ABORT |
4589                                           LSO6_SM_ERR_ALARM | LSO7_SM_ERR_ALARM,
4590                                           &bar0->lso_err_reg,
4591                                           &sw_stat->lso_err_cnt))
4592                         goto reset;
4593                 do_s2io_chk_alarm_bit(LSO6_SEND_OFLOW | LSO7_SEND_OFLOW,
4594                                       &bar0->lso_err_reg,
4595                                       &sw_stat->lso_err_cnt);
4596         }
4597
4598         /*check for tpa_err*/
4599         if (val64 & TXDMA_TPA_INT) {
4600                 if (do_s2io_chk_alarm_bit(TPA_SM_ERR_ALARM,
4601                                           &bar0->tpa_err_reg,
4602                                           &sw_stat->tpa_err_cnt))
4603                         goto reset;
4604                 do_s2io_chk_alarm_bit(TPA_TX_FRM_DROP,
4605                                       &bar0->tpa_err_reg,
4606                                       &sw_stat->tpa_err_cnt);
4607         }
4608
4609         /*check for sm_err*/
4610         if (val64 & TXDMA_SM_INT) {
4611                 if (do_s2io_chk_alarm_bit(SM_SM_ERR_ALARM,
4612                                           &bar0->sm_err_reg,
4613                                           &sw_stat->sm_err_cnt))
4614                         goto reset;
4615         }
4616
4617         val64 = readq(&bar0->mac_int_status);
4618         if (val64 & MAC_INT_STATUS_TMAC_INT) {
4619                 if (do_s2io_chk_alarm_bit(TMAC_TX_BUF_OVRN | TMAC_TX_SM_ERR,
4620                                           &bar0->mac_tmac_err_reg,
4621                                           &sw_stat->mac_tmac_err_cnt))
4622                         goto reset;
4623                 do_s2io_chk_alarm_bit(TMAC_ECC_SG_ERR | TMAC_ECC_DB_ERR |
4624                                       TMAC_DESC_ECC_SG_ERR |
4625                                       TMAC_DESC_ECC_DB_ERR,
4626                                       &bar0->mac_tmac_err_reg,
4627                                       &sw_stat->mac_tmac_err_cnt);
4628         }
4629
4630         val64 = readq(&bar0->xgxs_int_status);
4631         if (val64 & XGXS_INT_STATUS_TXGXS) {
4632                 if (do_s2io_chk_alarm_bit(TXGXS_ESTORE_UFLOW | TXGXS_TX_SM_ERR,
4633                                           &bar0->xgxs_txgxs_err_reg,
4634                                           &sw_stat->xgxs_txgxs_err_cnt))
4635                         goto reset;
4636                 do_s2io_chk_alarm_bit(TXGXS_ECC_SG_ERR | TXGXS_ECC_DB_ERR,
4637                                       &bar0->xgxs_txgxs_err_reg,
4638                                       &sw_stat->xgxs_txgxs_err_cnt);
4639         }
4640
4641         val64 = readq(&bar0->rxdma_int_status);
4642         if (val64 & RXDMA_INT_RC_INT_M) {
4643                 if (do_s2io_chk_alarm_bit(RC_PRCn_ECC_DB_ERR |
4644                                           RC_FTC_ECC_DB_ERR |
4645                                           RC_PRCn_SM_ERR_ALARM |
4646                                           RC_FTC_SM_ERR_ALARM,
4647                                           &bar0->rc_err_reg,
4648                                           &sw_stat->rc_err_cnt))
4649                         goto reset;
4650                 do_s2io_chk_alarm_bit(RC_PRCn_ECC_SG_ERR |
4651                                       RC_FTC_ECC_SG_ERR |
4652                                       RC_RDA_FAIL_WR_Rn, &bar0->rc_err_reg,
4653                                       &sw_stat->rc_err_cnt);
4654                 if (do_s2io_chk_alarm_bit(PRC_PCI_AB_RD_Rn |
4655                                           PRC_PCI_AB_WR_Rn |
4656                                           PRC_PCI_AB_F_WR_Rn,
4657                                           &bar0->prc_pcix_err_reg,
4658                                           &sw_stat->prc_pcix_err_cnt))
4659                         goto reset;
4660                 do_s2io_chk_alarm_bit(PRC_PCI_DP_RD_Rn |
4661                                       PRC_PCI_DP_WR_Rn |
4662                                       PRC_PCI_DP_F_WR_Rn,
4663                                       &bar0->prc_pcix_err_reg,
4664                                       &sw_stat->prc_pcix_err_cnt);
4665         }
4666
4667         if (val64 & RXDMA_INT_RPA_INT_M) {
4668                 if (do_s2io_chk_alarm_bit(RPA_SM_ERR_ALARM | RPA_CREDIT_ERR,
4669                                           &bar0->rpa_err_reg,
4670                                           &sw_stat->rpa_err_cnt))
4671                         goto reset;
4672                 do_s2io_chk_alarm_bit(RPA_ECC_SG_ERR | RPA_ECC_DB_ERR,
4673                                       &bar0->rpa_err_reg,
4674                                       &sw_stat->rpa_err_cnt);
4675         }
4676
4677         if (val64 & RXDMA_INT_RDA_INT_M) {
4678                 if (do_s2io_chk_alarm_bit(RDA_RXDn_ECC_DB_ERR |
4679                                           RDA_FRM_ECC_DB_N_AERR |
4680                                           RDA_SM1_ERR_ALARM |
4681                                           RDA_SM0_ERR_ALARM |
4682                                           RDA_RXD_ECC_DB_SERR,
4683                                           &bar0->rda_err_reg,
4684                                           &sw_stat->rda_err_cnt))
4685                         goto reset;
4686                 do_s2io_chk_alarm_bit(RDA_RXDn_ECC_SG_ERR |
4687                                       RDA_FRM_ECC_SG_ERR |
4688                                       RDA_MISC_ERR |
4689                                       RDA_PCIX_ERR,
4690                                       &bar0->rda_err_reg,
4691                                       &sw_stat->rda_err_cnt);
4692         }
4693
4694         if (val64 & RXDMA_INT_RTI_INT_M) {
4695                 if (do_s2io_chk_alarm_bit(RTI_SM_ERR_ALARM,
4696                                           &bar0->rti_err_reg,
4697                                           &sw_stat->rti_err_cnt))
4698                         goto reset;
4699                 do_s2io_chk_alarm_bit(RTI_ECC_SG_ERR | RTI_ECC_DB_ERR,
4700                                       &bar0->rti_err_reg,
4701                                       &sw_stat->rti_err_cnt);
4702         }
4703
4704         val64 = readq(&bar0->mac_int_status);
4705         if (val64 & MAC_INT_STATUS_RMAC_INT) {
4706                 if (do_s2io_chk_alarm_bit(RMAC_RX_BUFF_OVRN | RMAC_RX_SM_ERR,
4707                                           &bar0->mac_rmac_err_reg,
4708                                           &sw_stat->mac_rmac_err_cnt))
4709                         goto reset;
4710                 do_s2io_chk_alarm_bit(RMAC_UNUSED_INT |
4711                                       RMAC_SINGLE_ECC_ERR |
4712                                       RMAC_DOUBLE_ECC_ERR,
4713                                       &bar0->mac_rmac_err_reg,
4714                                       &sw_stat->mac_rmac_err_cnt);
4715         }
4716
4717         val64 = readq(&bar0->xgxs_int_status);
4718         if (val64 & XGXS_INT_STATUS_RXGXS) {
4719                 if (do_s2io_chk_alarm_bit(RXGXS_ESTORE_OFLOW | RXGXS_RX_SM_ERR,
4720                                           &bar0->xgxs_rxgxs_err_reg,
4721                                           &sw_stat->xgxs_rxgxs_err_cnt))
4722                         goto reset;
4723         }
4724
4725         val64 = readq(&bar0->mc_int_status);
4726         if (val64 & MC_INT_STATUS_MC_INT) {
4727                 if (do_s2io_chk_alarm_bit(MC_ERR_REG_SM_ERR,
4728                                           &bar0->mc_err_reg,
4729                                           &sw_stat->mc_err_cnt))
4730                         goto reset;
4731
4732                 /* Handling Ecc errors */
4733                 if (val64 & (MC_ERR_REG_ECC_ALL_SNG | MC_ERR_REG_ECC_ALL_DBL)) {
4734                         writeq(val64, &bar0->mc_err_reg);
4735                         if (val64 & MC_ERR_REG_ECC_ALL_DBL) {
4736                                 sw_stat->double_ecc_errs++;
4737                                 if (sp->device_type != XFRAME_II_DEVICE) {
4738                                         /*
4739                                          * Reset XframeI only if critical error
4740                                          */
4741                                         if (val64 &
4742                                             (MC_ERR_REG_MIRI_ECC_DB_ERR_0 |
4743                                              MC_ERR_REG_MIRI_ECC_DB_ERR_1))
4744                                                 goto reset;
4745                                 }
4746                         } else
4747                                 sw_stat->single_ecc_errs++;
4748                 }
4749         }
4750         return;
4751
4752 reset:
4753         s2io_stop_all_tx_queue(sp);
4754         schedule_work(&sp->rst_timer_task);
4755         sw_stat->soft_reset_cnt++;
4756 }
4757
4758 /**
4759  *  s2io_isr - ISR handler of the device .
4760  *  @irq: the irq of the device.
4761  *  @dev_id: a void pointer to the dev structure of the NIC.
4762  *  Description:  This function is the ISR handler of the device. It
4763  *  identifies the reason for the interrupt and calls the relevant
4764  *  service routines. As a contongency measure, this ISR allocates the
4765  *  recv buffers, if their numbers are below the panic value which is
4766  *  presently set to 25% of the original number of rcv buffers allocated.
4767  *  Return value:
4768  *   IRQ_HANDLED: will be returned if IRQ was handled by this routine
4769  *   IRQ_NONE: will be returned if interrupt is not from our device
4770  */
4771 static irqreturn_t s2io_isr(int irq, void *dev_id)
4772 {
4773         struct net_device *dev = (struct net_device *)dev_id;
4774         struct s2io_nic *sp = netdev_priv(dev);
4775         struct XENA_dev_config __iomem *bar0 = sp->bar0;
4776         int i;
4777         u64 reason = 0;
4778         struct mac_info *mac_control;
4779         struct config_param *config;
4780
4781         /* Pretend we handled any irq's from a disconnected card */
4782         if (pci_channel_offline(sp->pdev))
4783                 return IRQ_NONE;
4784
4785         if (!is_s2io_card_up(sp))
4786                 return IRQ_NONE;
4787
4788         config = &sp->config;
4789         mac_control = &sp->mac_control;
4790
4791         /*
4792          * Identify the cause for interrupt and call the appropriate
4793          * interrupt handler. Causes for the interrupt could be;
4794          * 1. Rx of packet.
4795          * 2. Tx complete.
4796          * 3. Link down.
4797          */
4798         reason = readq(&bar0->general_int_status);
4799
4800         if (unlikely(reason == S2IO_MINUS_ONE))
4801                 return IRQ_HANDLED;     /* Nothing much can be done. Get out */
4802
4803         if (reason &
4804             (GEN_INTR_RXTRAFFIC | GEN_INTR_TXTRAFFIC | GEN_INTR_TXPIC)) {
4805                 writeq(S2IO_MINUS_ONE, &bar0->general_int_mask);
4806
4807                 if (config->napi) {
4808                         if (reason & GEN_INTR_RXTRAFFIC) {
4809                                 napi_schedule(&sp->napi);
4810                                 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_mask);
4811                                 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
4812                                 readl(&bar0->rx_traffic_int);
4813                         }
4814                 } else {
4815                         /*
4816                          * rx_traffic_int reg is an R1 register, writing all 1's
4817                          * will ensure that the actual interrupt causing bit
4818                          * get's cleared and hence a read can be avoided.
4819                          */
4820                         if (reason & GEN_INTR_RXTRAFFIC)
4821                                 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
4822
4823                         for (i = 0; i < config->rx_ring_num; i++) {
4824                                 struct ring_info *ring = &mac_control->rings[i];
4825
4826                                 rx_intr_handler(ring, 0);
4827                         }
4828                 }
4829
4830                 /*
4831                  * tx_traffic_int reg is an R1 register, writing all 1's
4832                  * will ensure that the actual interrupt causing bit get's
4833                  * cleared and hence a read can be avoided.
4834                  */
4835                 if (reason & GEN_INTR_TXTRAFFIC)
4836                         writeq(S2IO_MINUS_ONE, &bar0->tx_traffic_int);
4837
4838                 for (i = 0; i < config->tx_fifo_num; i++)
4839                         tx_intr_handler(&mac_control->fifos[i]);
4840
4841                 if (reason & GEN_INTR_TXPIC)
4842                         s2io_txpic_intr_handle(sp);
4843
4844                 /*
4845                  * Reallocate the buffers from the interrupt handler itself.
4846                  */
4847                 if (!config->napi) {
4848                         for (i = 0; i < config->rx_ring_num; i++) {
4849                                 struct ring_info *ring = &mac_control->rings[i];
4850
4851                                 s2io_chk_rx_buffers(sp, ring);
4852                         }
4853                 }
4854                 writeq(sp->general_int_mask, &bar0->general_int_mask);
4855                 readl(&bar0->general_int_status);
4856
4857                 return IRQ_HANDLED;
4858
4859         } else if (!reason) {
4860                 /* The interrupt was not raised by us */
4861                 return IRQ_NONE;
4862         }
4863
4864         return IRQ_HANDLED;
4865 }
4866
4867 /**
4868  * s2io_updt_stats -
4869  */
4870 static void s2io_updt_stats(struct s2io_nic *sp)
4871 {
4872         struct XENA_dev_config __iomem *bar0 = sp->bar0;
4873         u64 val64;
4874         int cnt = 0;
4875
4876         if (is_s2io_card_up(sp)) {
4877                 /* Apprx 30us on a 133 MHz bus */
4878                 val64 = SET_UPDT_CLICKS(10) |
4879                         STAT_CFG_ONE_SHOT_EN | STAT_CFG_STAT_EN;
4880                 writeq(val64, &bar0->stat_cfg);
4881                 do {
4882                         udelay(100);
4883                         val64 = readq(&bar0->stat_cfg);
4884                         if (!(val64 & s2BIT(0)))
4885                                 break;
4886                         cnt++;
4887                         if (cnt == 5)
4888                                 break; /* Updt failed */
4889                 } while (1);
4890         }
4891 }
4892
4893 /**
4894  *  s2io_get_stats - Updates the device statistics structure.
4895  *  @dev : pointer to the device structure.
4896  *  Description:
4897  *  This function updates the device statistics structure in the s2io_nic
4898  *  structure and returns a pointer to the same.
4899  *  Return value:
4900  *  pointer to the updated net_device_stats structure.
4901  */
4902 static struct net_device_stats *s2io_get_stats(struct net_device *dev)
4903 {
4904         struct s2io_nic *sp = netdev_priv(dev);
4905         struct mac_info *mac_control = &sp->mac_control;
4906         struct stat_block *stats = mac_control->stats_info;
4907         u64 delta;
4908
4909         /* Configure Stats for immediate updt */
4910         s2io_updt_stats(sp);
4911
4912         /* A device reset will cause the on-adapter statistics to be zero'ed.
4913          * This can be done while running by changing the MTU.  To prevent the
4914          * system from having the stats zero'ed, the driver keeps a copy of the
4915          * last update to the system (which is also zero'ed on reset).  This
4916          * enables the driver to accurately know the delta between the last
4917          * update and the current update.
4918          */
4919         delta = ((u64) le32_to_cpu(stats->rmac_vld_frms_oflow) << 32 |
4920                 le32_to_cpu(stats->rmac_vld_frms)) - sp->stats.rx_packets;
4921         sp->stats.rx_packets += delta;
4922         dev->stats.rx_packets += delta;
4923
4924         delta = ((u64) le32_to_cpu(stats->tmac_frms_oflow) << 32 |
4925                 le32_to_cpu(stats->tmac_frms)) - sp->stats.tx_packets;
4926         sp->stats.tx_packets += delta;
4927         dev->stats.tx_packets += delta;
4928
4929         delta = ((u64) le32_to_cpu(stats->rmac_data_octets_oflow) << 32 |
4930                 le32_to_cpu(stats->rmac_data_octets)) - sp->stats.rx_bytes;
4931         sp->stats.rx_bytes += delta;
4932         dev->stats.rx_bytes += delta;
4933
4934         delta = ((u64) le32_to_cpu(stats->tmac_data_octets_oflow) << 32 |
4935                 le32_to_cpu(stats->tmac_data_octets)) - sp->stats.tx_bytes;
4936         sp->stats.tx_bytes += delta;
4937         dev->stats.tx_bytes += delta;
4938
4939         delta = le64_to_cpu(stats->rmac_drop_frms) - sp->stats.rx_errors;
4940         sp->stats.rx_errors += delta;
4941         dev->stats.rx_errors += delta;
4942
4943         delta = ((u64) le32_to_cpu(stats->tmac_any_err_frms_oflow) << 32 |
4944                 le32_to_cpu(stats->tmac_any_err_frms)) - sp->stats.tx_errors;
4945         sp->stats.tx_errors += delta;
4946         dev->stats.tx_errors += delta;
4947
4948         delta = le64_to_cpu(stats->rmac_drop_frms) - sp->stats.rx_dropped;
4949         sp->stats.rx_dropped += delta;
4950         dev->stats.rx_dropped += delta;
4951
4952         delta = le64_to_cpu(stats->tmac_drop_frms) - sp->stats.tx_dropped;
4953         sp->stats.tx_dropped += delta;
4954         dev->stats.tx_dropped += delta;
4955
4956         /* The adapter MAC interprets pause frames as multicast packets, but
4957          * does not pass them up.  This erroneously increases the multicast
4958          * packet count and needs to be deducted when the multicast frame count
4959          * is queried.
4960          */
4961         delta = (u64) le32_to_cpu(stats->rmac_vld_mcst_frms_oflow) << 32 |
4962                 le32_to_cpu(stats->rmac_vld_mcst_frms);
4963         delta -= le64_to_cpu(stats->rmac_pause_ctrl_frms);
4964         delta -= sp->stats.multicast;
4965         sp->stats.multicast += delta;
4966         dev->stats.multicast += delta;
4967
4968         delta = ((u64) le32_to_cpu(stats->rmac_usized_frms_oflow) << 32 |
4969                 le32_to_cpu(stats->rmac_usized_frms)) +
4970                 le64_to_cpu(stats->rmac_long_frms) - sp->stats.rx_length_errors;
4971         sp->stats.rx_length_errors += delta;
4972         dev->stats.rx_length_errors += delta;
4973
4974         delta = le64_to_cpu(stats->rmac_fcs_err_frms) - sp->stats.rx_crc_errors;
4975         sp->stats.rx_crc_errors += delta;
4976         dev->stats.rx_crc_errors += delta;
4977
4978         return &dev->stats;
4979 }
4980
4981 /**
4982  *  s2io_set_multicast - entry point for multicast address enable/disable.
4983  *  @dev : pointer to the device structure
4984  *  Description:
4985  *  This function is a driver entry point which gets called by the kernel
4986  *  whenever multicast addresses must be enabled/disabled. This also gets
4987  *  called to set/reset promiscuous mode. Depending on the deivce flag, we
4988  *  determine, if multicast address must be enabled or if promiscuous mode
4989  *  is to be disabled etc.
4990  *  Return value:
4991  *  void.
4992  */
4993
4994 static void s2io_set_multicast(struct net_device *dev)
4995 {
4996         int i, j, prev_cnt;
4997         struct netdev_hw_addr *ha;
4998         struct s2io_nic *sp = netdev_priv(dev);
4999         struct XENA_dev_config __iomem *bar0 = sp->bar0;
5000         u64 val64 = 0, multi_mac = 0x010203040506ULL, mask =
5001                 0xfeffffffffffULL;
5002         u64 dis_addr = S2IO_DISABLE_MAC_ENTRY, mac_addr = 0;
5003         void __iomem *add;
5004         struct config_param *config = &sp->config;
5005
5006         if ((dev->flags & IFF_ALLMULTI) && (!sp->m_cast_flg)) {
5007                 /*  Enable all Multicast addresses */
5008                 writeq(RMAC_ADDR_DATA0_MEM_ADDR(multi_mac),
5009                        &bar0->rmac_addr_data0_mem);
5010                 writeq(RMAC_ADDR_DATA1_MEM_MASK(mask),
5011                        &bar0->rmac_addr_data1_mem);
5012                 val64 = RMAC_ADDR_CMD_MEM_WE |
5013                         RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5014                         RMAC_ADDR_CMD_MEM_OFFSET(config->max_mc_addr - 1);
5015                 writeq(val64, &bar0->rmac_addr_cmd_mem);
5016                 /* Wait till command completes */
5017                 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5018                                       RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5019                                       S2IO_BIT_RESET);
5020
5021                 sp->m_cast_flg = 1;
5022                 sp->all_multi_pos = config->max_mc_addr - 1;
5023         } else if ((dev->flags & IFF_ALLMULTI) && (sp->m_cast_flg)) {
5024                 /*  Disable all Multicast addresses */
5025                 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
5026                        &bar0->rmac_addr_data0_mem);
5027                 writeq(RMAC_ADDR_DATA1_MEM_MASK(0x0),
5028                        &bar0->rmac_addr_data1_mem);
5029                 val64 = RMAC_ADDR_CMD_MEM_WE |
5030                         RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5031                         RMAC_ADDR_CMD_MEM_OFFSET(sp->all_multi_pos);
5032                 writeq(val64, &bar0->rmac_addr_cmd_mem);
5033                 /* Wait till command completes */
5034                 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5035                                       RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5036                                       S2IO_BIT_RESET);
5037
5038                 sp->m_cast_flg = 0;
5039                 sp->all_multi_pos = 0;
5040         }
5041
5042         if ((dev->flags & IFF_PROMISC) && (!sp->promisc_flg)) {
5043                 /*  Put the NIC into promiscuous mode */
5044                 add = &bar0->mac_cfg;
5045                 val64 = readq(&bar0->mac_cfg);
5046                 val64 |= MAC_CFG_RMAC_PROM_ENABLE;
5047
5048                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
5049                 writel((u32)val64, add);
5050                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
5051                 writel((u32) (val64 >> 32), (add + 4));
5052
5053                 if (vlan_tag_strip != 1) {
5054                         val64 = readq(&bar0->rx_pa_cfg);
5055                         val64 &= ~RX_PA_CFG_STRIP_VLAN_TAG;
5056                         writeq(val64, &bar0->rx_pa_cfg);
5057                         sp->vlan_strip_flag = 0;
5058                 }
5059
5060                 val64 = readq(&bar0->mac_cfg);
5061                 sp->promisc_flg = 1;
5062                 DBG_PRINT(INFO_DBG, "%s: entered promiscuous mode\n",
5063                           dev->name);
5064         } else if (!(dev->flags & IFF_PROMISC) && (sp->promisc_flg)) {
5065                 /*  Remove the NIC from promiscuous mode */
5066                 add = &bar0->mac_cfg;
5067                 val64 = readq(&bar0->mac_cfg);
5068                 val64 &= ~MAC_CFG_RMAC_PROM_ENABLE;
5069
5070                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
5071                 writel((u32)val64, add);
5072                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
5073                 writel((u32) (val64 >> 32), (add + 4));
5074
5075                 if (vlan_tag_strip != 0) {
5076                         val64 = readq(&bar0->rx_pa_cfg);
5077                         val64 |= RX_PA_CFG_STRIP_VLAN_TAG;
5078                         writeq(val64, &bar0->rx_pa_cfg);
5079                         sp->vlan_strip_flag = 1;
5080                 }
5081
5082                 val64 = readq(&bar0->mac_cfg);
5083                 sp->promisc_flg = 0;
5084                 DBG_PRINT(INFO_DBG, "%s: left promiscuous mode\n", dev->name);
5085         }
5086
5087         /*  Update individual M_CAST address list */
5088         if ((!sp->m_cast_flg) && netdev_mc_count(dev)) {
5089                 if (netdev_mc_count(dev) >
5090                     (config->max_mc_addr - config->max_mac_addr)) {
5091                         DBG_PRINT(ERR_DBG,
5092                                   "%s: No more Rx filters can be added - "
5093                                   "please enable ALL_MULTI instead\n",
5094                                   dev->name);
5095                         return;
5096                 }
5097
5098                 prev_cnt = sp->mc_addr_count;
5099                 sp->mc_addr_count = netdev_mc_count(dev);
5100
5101                 /* Clear out the previous list of Mc in the H/W. */
5102                 for (i = 0; i < prev_cnt; i++) {
5103                         writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
5104                                &bar0->rmac_addr_data0_mem);
5105                         writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
5106                                &bar0->rmac_addr_data1_mem);
5107                         val64 = RMAC_ADDR_CMD_MEM_WE |
5108                                 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5109                                 RMAC_ADDR_CMD_MEM_OFFSET
5110                                 (config->mc_start_offset + i);
5111                         writeq(val64, &bar0->rmac_addr_cmd_mem);
5112
5113                         /* Wait for command completes */
5114                         if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5115                                                   RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5116                                                   S2IO_BIT_RESET)) {
5117                                 DBG_PRINT(ERR_DBG,
5118                                           "%s: Adding Multicasts failed\n",
5119                                           dev->name);
5120                                 return;
5121                         }
5122                 }
5123
5124                 /* Create the new Rx filter list and update the same in H/W. */
5125                 i = 0;
5126                 netdev_for_each_mc_addr(ha, dev) {
5127                         memcpy(sp->usr_addrs[i].addr, ha->addr,
5128                                ETH_ALEN);
5129                         mac_addr = 0;
5130                         for (j = 0; j < ETH_ALEN; j++) {
5131                                 mac_addr |= ha->addr[j];
5132                                 mac_addr <<= 8;
5133                         }
5134                         mac_addr >>= 8;
5135                         writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr),
5136                                &bar0->rmac_addr_data0_mem);
5137                         writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
5138                                &bar0->rmac_addr_data1_mem);
5139                         val64 = RMAC_ADDR_CMD_MEM_WE |
5140                                 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5141                                 RMAC_ADDR_CMD_MEM_OFFSET
5142                                 (i + config->mc_start_offset);
5143                         writeq(val64, &bar0->rmac_addr_cmd_mem);
5144
5145                         /* Wait for command completes */
5146                         if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5147                                                   RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5148                                                   S2IO_BIT_RESET)) {
5149                                 DBG_PRINT(ERR_DBG,
5150                                           "%s: Adding Multicasts failed\n",
5151                                           dev->name);
5152                                 return;
5153                         }
5154                         i++;
5155                 }
5156         }
5157 }
5158
5159 /* read from CAM unicast & multicast addresses and store it in
5160  * def_mac_addr structure
5161  */
5162 static void do_s2io_store_unicast_mc(struct s2io_nic *sp)
5163 {
5164         int offset;
5165         u64 mac_addr = 0x0;
5166         struct config_param *config = &sp->config;
5167
5168         /* store unicast & multicast mac addresses */
5169         for (offset = 0; offset < config->max_mc_addr; offset++) {
5170                 mac_addr = do_s2io_read_unicast_mc(sp, offset);
5171                 /* if read fails disable the entry */
5172                 if (mac_addr == FAILURE)
5173                         mac_addr = S2IO_DISABLE_MAC_ENTRY;
5174                 do_s2io_copy_mac_addr(sp, offset, mac_addr);
5175         }
5176 }
5177
5178 /* restore unicast & multicast MAC to CAM from def_mac_addr structure */
5179 static void do_s2io_restore_unicast_mc(struct s2io_nic *sp)
5180 {
5181         int offset;
5182         struct config_param *config = &sp->config;
5183         /* restore unicast mac address */
5184         for (offset = 0; offset < config->max_mac_addr; offset++)
5185                 do_s2io_prog_unicast(sp->dev,
5186                                      sp->def_mac_addr[offset].mac_addr);
5187
5188         /* restore multicast mac address */
5189         for (offset = config->mc_start_offset;
5190              offset < config->max_mc_addr; offset++)
5191                 do_s2io_add_mc(sp, sp->def_mac_addr[offset].mac_addr);
5192 }
5193
5194 /* add a multicast MAC address to CAM */
5195 static int do_s2io_add_mc(struct s2io_nic *sp, u8 *addr)
5196 {
5197         int i;
5198         u64 mac_addr = 0;
5199         struct config_param *config = &sp->config;
5200
5201         for (i = 0; i < ETH_ALEN; i++) {
5202                 mac_addr <<= 8;
5203                 mac_addr |= addr[i];
5204         }
5205         if ((0ULL == mac_addr) || (mac_addr == S2IO_DISABLE_MAC_ENTRY))
5206                 return SUCCESS;
5207
5208         /* check if the multicast mac already preset in CAM */
5209         for (i = config->mc_start_offset; i < config->max_mc_addr; i++) {
5210                 u64 tmp64;
5211                 tmp64 = do_s2io_read_unicast_mc(sp, i);
5212                 if (tmp64 == S2IO_DISABLE_MAC_ENTRY) /* CAM entry is empty */
5213                         break;
5214
5215                 if (tmp64 == mac_addr)
5216                         return SUCCESS;
5217         }
5218         if (i == config->max_mc_addr) {
5219                 DBG_PRINT(ERR_DBG,
5220                           "CAM full no space left for multicast MAC\n");
5221                 return FAILURE;
5222         }
5223         /* Update the internal structure with this new mac address */
5224         do_s2io_copy_mac_addr(sp, i, mac_addr);
5225
5226         return do_s2io_add_mac(sp, mac_addr, i);
5227 }
5228
5229 /* add MAC address to CAM */
5230 static int do_s2io_add_mac(struct s2io_nic *sp, u64 addr, int off)
5231 {
5232         u64 val64;
5233         struct XENA_dev_config __iomem *bar0 = sp->bar0;
5234
5235         writeq(RMAC_ADDR_DATA0_MEM_ADDR(addr),
5236                &bar0->rmac_addr_data0_mem);
5237
5238         val64 = RMAC_ADDR_CMD_MEM_WE | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5239                 RMAC_ADDR_CMD_MEM_OFFSET(off);
5240         writeq(val64, &bar0->rmac_addr_cmd_mem);
5241
5242         /* Wait till command completes */
5243         if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5244                                   RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5245                                   S2IO_BIT_RESET)) {
5246                 DBG_PRINT(INFO_DBG, "do_s2io_add_mac failed\n");
5247                 return FAILURE;
5248         }
5249         return SUCCESS;
5250 }
5251 /* deletes a specified unicast/multicast mac entry from CAM */
5252 static int do_s2io_delete_unicast_mc(struct s2io_nic *sp, u64 addr)
5253 {
5254         int offset;
5255         u64 dis_addr = S2IO_DISABLE_MAC_ENTRY, tmp64;
5256         struct config_param *config = &sp->config;
5257
5258         for (offset = 1;
5259              offset < config->max_mc_addr; offset++) {
5260                 tmp64 = do_s2io_read_unicast_mc(sp, offset);
5261                 if (tmp64 == addr) {
5262                         /* disable the entry by writing  0xffffffffffffULL */
5263                         if (do_s2io_add_mac(sp, dis_addr, offset) ==  FAILURE)
5264                                 return FAILURE;
5265                         /* store the new mac list from CAM */
5266                         do_s2io_store_unicast_mc(sp);
5267                         return SUCCESS;
5268                 }
5269         }
5270         DBG_PRINT(ERR_DBG, "MAC address 0x%llx not found in CAM\n",
5271                   (unsigned long long)addr);
5272         return FAILURE;
5273 }
5274
5275 /* read mac entries from CAM */
5276 static u64 do_s2io_read_unicast_mc(struct s2io_nic *sp, int offset)
5277 {
5278         u64 tmp64 = 0xffffffffffff0000ULL, val64;
5279         struct XENA_dev_config __iomem *bar0 = sp->bar0;
5280
5281         /* read mac addr */
5282         val64 = RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5283                 RMAC_ADDR_CMD_MEM_OFFSET(offset);
5284         writeq(val64, &bar0->rmac_addr_cmd_mem);
5285
5286         /* Wait till command completes */
5287         if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5288                                   RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5289                                   S2IO_BIT_RESET)) {
5290                 DBG_PRINT(INFO_DBG, "do_s2io_read_unicast_mc failed\n");
5291                 return FAILURE;
5292         }
5293         tmp64 = readq(&bar0->rmac_addr_data0_mem);
5294
5295         return tmp64 >> 16;
5296 }
5297
5298 /**
5299  * s2io_set_mac_addr driver entry point
5300  */
5301
5302 static int s2io_set_mac_addr(struct net_device *dev, void *p)
5303 {
5304         struct sockaddr *addr = p;
5305
5306         if (!is_valid_ether_addr(addr->sa_data))
5307                 return -EINVAL;
5308
5309         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
5310
5311         /* store the MAC address in CAM */
5312         return do_s2io_prog_unicast(dev, dev->dev_addr);
5313 }
5314 /**
5315  *  do_s2io_prog_unicast - Programs the Xframe mac address
5316  *  @dev : pointer to the device structure.
5317  *  @addr: a uchar pointer to the new mac address which is to be set.
5318  *  Description : This procedure will program the Xframe to receive
5319  *  frames with new Mac Address
5320  *  Return value: SUCCESS on success and an appropriate (-)ve integer
5321  *  as defined in errno.h file on failure.
5322  */
5323
5324 static int do_s2io_prog_unicast(struct net_device *dev, u8 *addr)
5325 {
5326         struct s2io_nic *sp = netdev_priv(dev);
5327         register u64 mac_addr = 0, perm_addr = 0;
5328         int i;
5329         u64 tmp64;
5330         struct config_param *config = &sp->config;
5331
5332         /*
5333          * Set the new MAC address as the new unicast filter and reflect this
5334          * change on the device address registered with the OS. It will be
5335          * at offset 0.
5336          */
5337         for (i = 0; i < ETH_ALEN; i++) {
5338                 mac_addr <<= 8;
5339                 mac_addr |= addr[i];
5340                 perm_addr <<= 8;
5341                 perm_addr |= sp->def_mac_addr[0].mac_addr[i];
5342         }
5343
5344         /* check if the dev_addr is different than perm_addr */
5345         if (mac_addr == perm_addr)
5346                 return SUCCESS;
5347
5348         /* check if the mac already preset in CAM */
5349         for (i = 1; i < config->max_mac_addr; i++) {
5350                 tmp64 = do_s2io_read_unicast_mc(sp, i);
5351                 if (tmp64 == S2IO_DISABLE_MAC_ENTRY) /* CAM entry is empty */
5352                         break;
5353
5354                 if (tmp64 == mac_addr) {
5355                         DBG_PRINT(INFO_DBG,
5356                                   "MAC addr:0x%llx already present in CAM\n",
5357                                   (unsigned long long)mac_addr);
5358                         return SUCCESS;
5359                 }
5360         }
5361         if (i == config->max_mac_addr) {
5362                 DBG_PRINT(ERR_DBG, "CAM full no space left for Unicast MAC\n");
5363                 return FAILURE;
5364         }
5365         /* Update the internal structure with this new mac address */
5366         do_s2io_copy_mac_addr(sp, i, mac_addr);
5367
5368         return do_s2io_add_mac(sp, mac_addr, i);
5369 }
5370
5371 /**
5372  * s2io_ethtool_sset - Sets different link parameters.
5373  * @sp : private member of the device structure, which is a pointer to the  * s2io_nic structure.
5374  * @info: pointer to the structure with parameters given by ethtool to set
5375  * link information.
5376  * Description:
5377  * The function sets different link parameters provided by the user onto
5378  * the NIC.
5379  * Return value:
5380  * 0 on success.
5381  */
5382
5383 static int s2io_ethtool_sset(struct net_device *dev,
5384                              struct ethtool_cmd *info)
5385 {
5386         struct s2io_nic *sp = netdev_priv(dev);
5387         if ((info->autoneg == AUTONEG_ENABLE) ||
5388             (info->speed != SPEED_10000) ||
5389             (info->duplex != DUPLEX_FULL))
5390                 return -EINVAL;
5391         else {
5392                 s2io_close(sp->dev);
5393                 s2io_open(sp->dev);
5394         }
5395
5396         return 0;
5397 }
5398
5399 /**
5400  * s2io_ethtol_gset - Return link specific information.
5401  * @sp : private member of the device structure, pointer to the
5402  *      s2io_nic structure.
5403  * @info : pointer to the structure with parameters given by ethtool
5404  * to return link information.
5405  * Description:
5406  * Returns link specific information like speed, duplex etc.. to ethtool.
5407  * Return value :
5408  * return 0 on success.
5409  */
5410
5411 static int s2io_ethtool_gset(struct net_device *dev, struct ethtool_cmd *info)
5412 {
5413         struct s2io_nic *sp = netdev_priv(dev);
5414         info->supported = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
5415         info->advertising = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
5416         info->port = PORT_FIBRE;
5417
5418         /* info->transceiver */
5419         info->transceiver = XCVR_EXTERNAL;
5420
5421         if (netif_carrier_ok(sp->dev)) {
5422                 info->speed = 10000;
5423                 info->duplex = DUPLEX_FULL;
5424         } else {
5425                 info->speed = -1;
5426                 info->duplex = -1;
5427         }
5428
5429         info->autoneg = AUTONEG_DISABLE;
5430         return 0;
5431 }
5432
5433 /**
5434  * s2io_ethtool_gdrvinfo - Returns driver specific information.
5435  * @sp : private member of the device structure, which is a pointer to the
5436  * s2io_nic structure.
5437  * @info : pointer to the structure with parameters given by ethtool to
5438  * return driver information.
5439  * Description:
5440  * Returns driver specefic information like name, version etc.. to ethtool.
5441  * Return value:
5442  *  void
5443  */
5444
5445 static void s2io_ethtool_gdrvinfo(struct net_device *dev,
5446                                   struct ethtool_drvinfo *info)
5447 {
5448         struct s2io_nic *sp = netdev_priv(dev);
5449
5450         strncpy(info->driver, s2io_driver_name, sizeof(info->driver));
5451         strncpy(info->version, s2io_driver_version, sizeof(info->version));
5452         strncpy(info->fw_version, "", sizeof(info->fw_version));
5453         strncpy(info->bus_info, pci_name(sp->pdev), sizeof(info->bus_info));
5454         info->regdump_len = XENA_REG_SPACE;
5455         info->eedump_len = XENA_EEPROM_SPACE;
5456 }
5457
5458 /**
5459  *  s2io_ethtool_gregs - dumps the entire space of Xfame into the buffer.
5460  *  @sp: private member of the device structure, which is a pointer to the
5461  *  s2io_nic structure.
5462  *  @regs : pointer to the structure with parameters given by ethtool for
5463  *  dumping the registers.
5464  *  @reg_space: The input argumnet into which all the registers are dumped.
5465  *  Description:
5466  *  Dumps the entire register space of xFrame NIC into the user given
5467  *  buffer area.
5468  * Return value :
5469  * void .
5470  */
5471
5472 static void s2io_ethtool_gregs(struct net_device *dev,
5473                                struct ethtool_regs *regs, void *space)
5474 {
5475         int i;
5476         u64 reg;
5477         u8 *reg_space = (u8 *)space;
5478         struct s2io_nic *sp = netdev_priv(dev);
5479
5480         regs->len = XENA_REG_SPACE;
5481         regs->version = sp->pdev->subsystem_device;
5482
5483         for (i = 0; i < regs->len; i += 8) {
5484                 reg = readq(sp->bar0 + i);
5485                 memcpy((reg_space + i), &reg, 8);
5486         }
5487 }
5488
5489 /**
5490  *  s2io_phy_id  - timer function that alternates adapter LED.
5491  *  @data : address of the private member of the device structure, which
5492  *  is a pointer to the s2io_nic structure, provided as an u32.
5493  * Description: This is actually the timer function that alternates the
5494  * adapter LED bit of the adapter control bit to set/reset every time on
5495  * invocation. The timer is set for 1/2 a second, hence tha NIC blinks
5496  *  once every second.
5497  */
5498 static void s2io_phy_id(unsigned long data)
5499 {
5500         struct s2io_nic *sp = (struct s2io_nic *)data;
5501         struct XENA_dev_config __iomem *bar0 = sp->bar0;
5502         u64 val64 = 0;
5503         u16 subid;
5504
5505         subid = sp->pdev->subsystem_device;
5506         if ((sp->device_type == XFRAME_II_DEVICE) ||
5507             ((subid & 0xFF) >= 0x07)) {
5508                 val64 = readq(&bar0->gpio_control);
5509                 val64 ^= GPIO_CTRL_GPIO_0;
5510                 writeq(val64, &bar0->gpio_control);
5511         } else {
5512                 val64 = readq(&bar0->adapter_control);
5513                 val64 ^= ADAPTER_LED_ON;
5514                 writeq(val64, &bar0->adapter_control);
5515         }
5516
5517         mod_timer(&sp->id_timer, jiffies + HZ / 2);
5518 }
5519
5520 /**
5521  * s2io_ethtool_idnic - To physically identify the nic on the system.
5522  * @sp : private member of the device structure, which is a pointer to the
5523  * s2io_nic structure.
5524  * @id : pointer to the structure with identification parameters given by
5525  * ethtool.
5526  * Description: Used to physically identify the NIC on the system.
5527  * The Link LED will blink for a time specified by the user for
5528  * identification.
5529  * NOTE: The Link has to be Up to be able to blink the LED. Hence
5530  * identification is possible only if it's link is up.
5531  * Return value:
5532  * int , returns 0 on success
5533  */
5534
5535 static int s2io_ethtool_idnic(struct net_device *dev, u32 data)
5536 {
5537         u64 val64 = 0, last_gpio_ctrl_val;
5538         struct s2io_nic *sp = netdev_priv(dev);
5539         struct XENA_dev_config __iomem *bar0 = sp->bar0;
5540         u16 subid;
5541
5542         subid = sp->pdev->subsystem_device;
5543         last_gpio_ctrl_val = readq(&bar0->gpio_control);
5544         if ((sp->device_type == XFRAME_I_DEVICE) && ((subid & 0xFF) < 0x07)) {
5545                 val64 = readq(&bar0->adapter_control);
5546                 if (!(val64 & ADAPTER_CNTL_EN)) {
5547                         pr_err("Adapter Link down, cannot blink LED\n");
5548                         return -EFAULT;
5549                 }
5550         }
5551         if (sp->id_timer.function == NULL) {
5552                 init_timer(&sp->id_timer);
5553                 sp->id_timer.function = s2io_phy_id;
5554                 sp->id_timer.data = (unsigned long)sp;
5555         }
5556         mod_timer(&sp->id_timer, jiffies);
5557         if (data)
5558                 msleep_interruptible(data * HZ);
5559         else
5560                 msleep_interruptible(MAX_FLICKER_TIME);
5561         del_timer_sync(&sp->id_timer);
5562
5563         if (CARDS_WITH_FAULTY_LINK_INDICATORS(sp->device_type, subid)) {
5564                 writeq(last_gpio_ctrl_val, &bar0->gpio_control);
5565                 last_gpio_ctrl_val = readq(&bar0->gpio_control);
5566         }
5567
5568         return 0;
5569 }
5570
5571 static void s2io_ethtool_gringparam(struct net_device *dev,
5572                                     struct ethtool_ringparam *ering)
5573 {
5574         struct s2io_nic *sp = netdev_priv(dev);
5575         int i, tx_desc_count = 0, rx_desc_count = 0;
5576
5577         if (sp->rxd_mode == RXD_MODE_1)
5578                 ering->rx_max_pending = MAX_RX_DESC_1;
5579         else if (sp->rxd_mode == RXD_MODE_3B)
5580                 ering->rx_max_pending = MAX_RX_DESC_2;
5581
5582         ering->tx_max_pending = MAX_TX_DESC;
5583         for (i = 0 ; i < sp->config.tx_fifo_num ; i++)
5584                 tx_desc_count += sp->config.tx_cfg[i].fifo_len;
5585
5586         DBG_PRINT(INFO_DBG, "max txds: %d\n", sp->config.max_txds);
5587         ering->tx_pending = tx_desc_count;
5588         rx_desc_count = 0;
5589         for (i = 0 ; i < sp->config.rx_ring_num ; i++)
5590                 rx_desc_count += sp->config.rx_cfg[i].num_rxd;
5591
5592         ering->rx_pending = rx_desc_count;
5593
5594         ering->rx_mini_max_pending = 0;
5595         ering->rx_mini_pending = 0;
5596         if (sp->rxd_mode == RXD_MODE_1)
5597                 ering->rx_jumbo_max_pending = MAX_RX_DESC_1;
5598         else if (sp->rxd_mode == RXD_MODE_3B)
5599                 ering->rx_jumbo_max_pending = MAX_RX_DESC_2;
5600         ering->rx_jumbo_pending = rx_desc_count;
5601 }
5602
5603 /**
5604  * s2io_ethtool_getpause_data -Pause frame frame generation and reception.
5605  * @sp : private member of the device structure, which is a pointer to the
5606  *      s2io_nic structure.
5607  * @ep : pointer to the structure with pause parameters given by ethtool.
5608  * Description:
5609  * Returns the Pause frame generation and reception capability of the NIC.
5610  * Return value:
5611  *  void
5612  */
5613 static void s2io_ethtool_getpause_data(struct net_device *dev,
5614                                        struct ethtool_pauseparam *ep)
5615 {
5616         u64 val64;
5617         struct s2io_nic *sp = netdev_priv(dev);
5618         struct XENA_dev_config __iomem *bar0 = sp->bar0;
5619
5620         val64 = readq(&bar0->rmac_pause_cfg);
5621         if (val64 & RMAC_PAUSE_GEN_ENABLE)
5622                 ep->tx_pause = true;
5623         if (val64 & RMAC_PAUSE_RX_ENABLE)
5624                 ep->rx_pause = true;
5625         ep->autoneg = false;
5626 }
5627
5628 /**
5629  * s2io_ethtool_setpause_data -  set/reset pause frame generation.
5630  * @sp : private member of the device structure, which is a pointer to the
5631  *      s2io_nic structure.
5632  * @ep : pointer to the structure with pause parameters given by ethtool.
5633  * Description:
5634  * It can be used to set or reset Pause frame generation or reception
5635  * support of the NIC.
5636  * Return value:
5637  * int, returns 0 on Success
5638  */
5639
5640 static int s2io_ethtool_setpause_data(struct net_device *dev,
5641                                       struct ethtool_pauseparam *ep)
5642 {
5643         u64 val64;
5644         struct s2io_nic *sp = netdev_priv(dev);
5645         struct XENA_dev_config __iomem *bar0 = sp->bar0;
5646
5647         val64 = readq(&bar0->rmac_pause_cfg);
5648         if (ep->tx_pause)
5649                 val64 |= RMAC_PAUSE_GEN_ENABLE;
5650         else
5651                 val64 &= ~RMAC_PAUSE_GEN_ENABLE;
5652         if (ep->rx_pause)
5653                 val64 |= RMAC_PAUSE_RX_ENABLE;
5654         else
5655                 val64 &= ~RMAC_PAUSE_RX_ENABLE;
5656         writeq(val64, &bar0->rmac_pause_cfg);
5657         return 0;
5658 }
5659
5660 /**
5661  * read_eeprom - reads 4 bytes of data from user given offset.
5662  * @sp : private member of the device structure, which is a pointer to the
5663  *      s2io_nic structure.
5664  * @off : offset at which the data must be written
5665  * @data : Its an output parameter where the data read at the given
5666  *      offset is stored.
5667  * Description:
5668  * Will read 4 bytes of data from the user given offset and return the
5669  * read data.
5670  * NOTE: Will allow to read only part of the EEPROM visible through the
5671  *   I2C bus.
5672  * Return value:
5673  *  -1 on failure and 0 on success.
5674  */
5675
5676 #define S2IO_DEV_ID             5
5677 static int read_eeprom(struct s2io_nic *sp, int off, u64 *data)
5678 {
5679         int ret = -1;
5680         u32 exit_cnt = 0;
5681         u64 val64;
5682         struct XENA_dev_config __iomem *bar0 = sp->bar0;
5683
5684         if (sp->device_type == XFRAME_I_DEVICE) {
5685                 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) |
5686                         I2C_CONTROL_ADDR(off) |
5687                         I2C_CONTROL_BYTE_CNT(0x3) |
5688                         I2C_CONTROL_READ |
5689                         I2C_CONTROL_CNTL_START;
5690                 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
5691
5692                 while (exit_cnt < 5) {
5693                         val64 = readq(&bar0->i2c_control);
5694                         if (I2C_CONTROL_CNTL_END(val64)) {
5695                                 *data = I2C_CONTROL_GET_DATA(val64);
5696                                 ret = 0;
5697                                 break;
5698                         }
5699                         msleep(50);
5700                         exit_cnt++;
5701                 }
5702         }
5703
5704         if (sp->device_type == XFRAME_II_DEVICE) {
5705                 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
5706                         SPI_CONTROL_BYTECNT(0x3) |
5707                         SPI_CONTROL_CMD(0x3) | SPI_CONTROL_ADDR(off);
5708                 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5709                 val64 |= SPI_CONTROL_REQ;
5710                 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5711                 while (exit_cnt < 5) {
5712                         val64 = readq(&bar0->spi_control);
5713                         if (val64 & SPI_CONTROL_NACK) {
5714                                 ret = 1;
5715                                 break;
5716                         } else if (val64 & SPI_CONTROL_DONE) {
5717                                 *data = readq(&bar0->spi_data);
5718                                 *data &= 0xffffff;
5719                                 ret = 0;
5720                                 break;
5721                         }
5722                         msleep(50);
5723                         exit_cnt++;
5724                 }
5725         }
5726         return ret;
5727 }
5728
5729 /**
5730  *  write_eeprom - actually writes the relevant part of the data value.
5731  *  @sp : private member of the device structure, which is a pointer to the
5732  *       s2io_nic structure.
5733  *  @off : offset at which the data must be written
5734  *  @data : The data that is to be written
5735  *  @cnt : Number of bytes of the data that are actually to be written into
5736  *  the Eeprom. (max of 3)
5737  * Description:
5738  *  Actually writes the relevant part of the data value into the Eeprom
5739  *  through the I2C bus.
5740  * Return value:
5741  *  0 on success, -1 on failure.
5742  */
5743
5744 static int write_eeprom(struct s2io_nic *sp, int off, u64 data, int cnt)
5745 {
5746         int exit_cnt = 0, ret = -1;
5747         u64 val64;
5748         struct XENA_dev_config __iomem *bar0 = sp->bar0;
5749
5750         if (sp->device_type == XFRAME_I_DEVICE) {
5751                 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) |
5752                         I2C_CONTROL_ADDR(off) |
5753                         I2C_CONTROL_BYTE_CNT(cnt) |
5754                         I2C_CONTROL_SET_DATA((u32)data) |
5755                         I2C_CONTROL_CNTL_START;
5756                 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
5757
5758                 while (exit_cnt < 5) {
5759                         val64 = readq(&bar0->i2c_control);
5760                         if (I2C_CONTROL_CNTL_END(val64)) {
5761                                 if (!(val64 & I2C_CONTROL_NACK))
5762                                         ret = 0;
5763                                 break;
5764                         }
5765                         msleep(50);
5766                         exit_cnt++;
5767                 }
5768         }
5769
5770         if (sp->device_type == XFRAME_II_DEVICE) {
5771                 int write_cnt = (cnt == 8) ? 0 : cnt;
5772                 writeq(SPI_DATA_WRITE(data, (cnt << 3)), &bar0->spi_data);
5773
5774                 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
5775                         SPI_CONTROL_BYTECNT(write_cnt) |
5776                         SPI_CONTROL_CMD(0x2) | SPI_CONTROL_ADDR(off);
5777                 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5778                 val64 |= SPI_CONTROL_REQ;
5779                 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5780                 while (exit_cnt < 5) {
5781                         val64 = readq(&bar0->spi_control);
5782                         if (val64 & SPI_CONTROL_NACK) {
5783                                 ret = 1;
5784                                 break;
5785                         } else if (val64 & SPI_CONTROL_DONE) {
5786                                 ret = 0;
5787                                 break;
5788                         }
5789                         msleep(50);
5790                         exit_cnt++;
5791                 }
5792         }
5793         return ret;
5794 }
5795 static void s2io_vpd_read(struct s2io_nic *nic)
5796 {
5797         u8 *vpd_data;
5798         u8 data;
5799         int i = 0, cnt, len, fail = 0;
5800         int vpd_addr = 0x80;
5801         struct swStat *swstats = &nic->mac_control.stats_info->sw_stat;
5802
5803         if (nic->device_type == XFRAME_II_DEVICE) {
5804                 strcpy(nic->product_name, "Xframe II 10GbE network adapter");
5805                 vpd_addr = 0x80;
5806         } else {
5807                 strcpy(nic->product_name, "Xframe I 10GbE network adapter");
5808                 vpd_addr = 0x50;
5809         }
5810         strcpy(nic->serial_num, "NOT AVAILABLE");
5811
5812         vpd_data = kmalloc(256, GFP_KERNEL);
5813         if (!vpd_data) {
5814                 swstats->mem_alloc_fail_cnt++;
5815                 return;
5816         }
5817         swstats->mem_allocated += 256;
5818
5819         for (i = 0; i < 256; i += 4) {
5820                 pci_write_config_byte(nic->pdev, (vpd_addr + 2), i);
5821                 pci_read_config_byte(nic->pdev,  (vpd_addr + 2), &data);
5822                 pci_write_config_byte(nic->pdev, (vpd_addr + 3), 0);
5823                 for (cnt = 0; cnt < 5; cnt++) {
5824                         msleep(2);
5825                         pci_read_config_byte(nic->pdev, (vpd_addr + 3), &data);
5826                         if (data == 0x80)
5827                                 break;
5828                 }
5829                 if (cnt >= 5) {
5830                         DBG_PRINT(ERR_DBG, "Read of VPD data failed\n");
5831                         fail = 1;
5832                         break;
5833                 }
5834                 pci_read_config_dword(nic->pdev,  (vpd_addr + 4),
5835                                       (u32 *)&vpd_data[i]);
5836         }
5837
5838         if (!fail) {
5839                 /* read serial number of adapter */
5840                 for (cnt = 0; cnt < 252; cnt++) {
5841                         if ((vpd_data[cnt] == 'S') &&
5842                             (vpd_data[cnt+1] == 'N')) {
5843                                 len = vpd_data[cnt+2];
5844                                 if (len < min(VPD_STRING_LEN, 256-cnt-2)) {
5845                                         memcpy(nic->serial_num,
5846                                                &vpd_data[cnt + 3],
5847                                                len);
5848                                         memset(nic->serial_num+len,
5849                                                0,
5850                                                VPD_STRING_LEN-len);
5851                                         break;
5852                                 }
5853                         }
5854                 }
5855         }
5856
5857         if ((!fail) && (vpd_data[1] < VPD_STRING_LEN)) {
5858                 len = vpd_data[1];
5859                 memcpy(nic->product_name, &vpd_data[3], len);
5860                 nic->product_name[len] = 0;
5861         }
5862         kfree(vpd_data);
5863         swstats->mem_freed += 256;
5864 }
5865
5866 /**
5867  *  s2io_ethtool_geeprom  - reads the value stored in the Eeprom.
5868  *  @sp : private member of the device structure, which is a pointer to the *       s2io_nic structure.
5869  *  @eeprom : pointer to the user level structure provided by ethtool,
5870  *  containing all relevant information.
5871  *  @data_buf : user defined value to be written into Eeprom.
5872  *  Description: Reads the values stored in the Eeprom at given offset
5873  *  for a given length. Stores these values int the input argument data
5874  *  buffer 'data_buf' and returns these to the caller (ethtool.)
5875  *  Return value:
5876  *  int  0 on success
5877  */
5878
5879 static int s2io_ethtool_geeprom(struct net_device *dev,
5880                                 struct ethtool_eeprom *eeprom, u8 * data_buf)
5881 {
5882         u32 i, valid;
5883         u64 data;
5884         struct s2io_nic *sp = netdev_priv(dev);
5885
5886         eeprom->magic = sp->pdev->vendor | (sp->pdev->device << 16);
5887
5888         if ((eeprom->offset + eeprom->len) > (XENA_EEPROM_SPACE))
5889                 eeprom->len = XENA_EEPROM_SPACE - eeprom->offset;
5890
5891         for (i = 0; i < eeprom->len; i += 4) {
5892                 if (read_eeprom(sp, (eeprom->offset + i), &data)) {
5893                         DBG_PRINT(ERR_DBG, "Read of EEPROM failed\n");
5894                         return -EFAULT;
5895                 }
5896                 valid = INV(data);
5897                 memcpy((data_buf + i), &valid, 4);
5898         }
5899         return 0;
5900 }
5901
5902 /**
5903  *  s2io_ethtool_seeprom - tries to write the user provided value in Eeprom
5904  *  @sp : private member of the device structure, which is a pointer to the
5905  *  s2io_nic structure.
5906  *  @eeprom : pointer to the user level structure provided by ethtool,
5907  *  containing all relevant information.
5908  *  @data_buf ; user defined value to be written into Eeprom.
5909  *  Description:
5910  *  Tries to write the user provided value in the Eeprom, at the offset
5911  *  given by the user.
5912  *  Return value:
5913  *  0 on success, -EFAULT on failure.
5914  */
5915
5916 static int s2io_ethtool_seeprom(struct net_device *dev,
5917                                 struct ethtool_eeprom *eeprom,
5918                                 u8 *data_buf)
5919 {
5920         int len = eeprom->len, cnt = 0;
5921         u64 valid = 0, data;
5922         struct s2io_nic *sp = netdev_priv(dev);
5923
5924         if (eeprom->magic != (sp->pdev->vendor | (sp->pdev->device << 16))) {
5925                 DBG_PRINT(ERR_DBG,
5926                           "ETHTOOL_WRITE_EEPROM Err: "
5927                           "Magic value is wrong, it is 0x%x should be 0x%x\n",
5928                           (sp->pdev->vendor | (sp->pdev->device << 16)),
5929                           eeprom->magic);
5930                 return -EFAULT;
5931         }
5932
5933         while (len) {
5934                 data = (u32)data_buf[cnt] & 0x000000FF;
5935                 if (data)
5936                         valid = (u32)(data << 24);
5937                 else
5938                         valid = data;
5939
5940                 if (write_eeprom(sp, (eeprom->offset + cnt), valid, 0)) {
5941                         DBG_PRINT(ERR_DBG,
5942                                   "ETHTOOL_WRITE_EEPROM Err: "
5943                                   "Cannot write into the specified offset\n");
5944                         return -EFAULT;
5945                 }
5946                 cnt++;
5947                 len--;
5948         }
5949
5950         return 0;
5951 }
5952
5953 /**
5954  * s2io_register_test - reads and writes into all clock domains.
5955  * @sp : private member of the device structure, which is a pointer to the
5956  * s2io_nic structure.
5957  * @data : variable that returns the result of each of the test conducted b
5958  * by the driver.
5959  * Description:
5960  * Read and write into all clock domains. The NIC has 3 clock domains,
5961  * see that registers in all the three regions are accessible.
5962  * Return value:
5963  * 0 on success.
5964  */
5965
5966 static int s2io_register_test(struct s2io_nic *sp, uint64_t *data)
5967 {
5968         struct XENA_dev_config __iomem *bar0 = sp->bar0;
5969         u64 val64 = 0, exp_val;
5970         int fail = 0;
5971
5972         val64 = readq(&bar0->pif_rd_swapper_fb);
5973         if (val64 != 0x123456789abcdefULL) {
5974                 fail = 1;
5975                 DBG_PRINT(INFO_DBG, "Read Test level %d fails\n", 1);
5976         }
5977
5978         val64 = readq(&bar0->rmac_pause_cfg);
5979         if (val64 != 0xc000ffff00000000ULL) {
5980                 fail = 1;
5981                 DBG_PRINT(INFO_DBG, "Read Test level %d fails\n", 2);
5982         }
5983
5984         val64 = readq(&bar0->rx_queue_cfg);
5985         if (sp->device_type == XFRAME_II_DEVICE)
5986                 exp_val = 0x0404040404040404ULL;
5987         else
5988                 exp_val = 0x0808080808080808ULL;
5989         if (val64 != exp_val) {
5990                 fail = 1;
5991                 DBG_PRINT(INFO_DBG, "Read Test level %d fails\n", 3);
5992         }
5993
5994         val64 = readq(&bar0->xgxs_efifo_cfg);
5995         if (val64 != 0x000000001923141EULL) {
5996                 fail = 1;
5997                 DBG_PRINT(INFO_DBG, "Read Test level %d fails\n", 4);
5998         }
5999
6000         val64 = 0x5A5A5A5A5A5A5A5AULL;
6001         writeq(val64, &bar0->xmsi_data);
6002         val64 = readq(&bar0->xmsi_data);
6003         if (val64 != 0x5A5A5A5A5A5A5A5AULL) {
6004                 fail = 1;
6005                 DBG_PRINT(ERR_DBG, "Write Test level %d fails\n", 1);
6006         }
6007
6008         val64 = 0xA5A5A5A5A5A5A5A5ULL;
6009         writeq(val64, &bar0->xmsi_data);
6010         val64 = readq(&bar0->xmsi_data);
6011         if (val64 != 0xA5A5A5A5A5A5A5A5ULL) {
6012                 fail = 1;
6013                 DBG_PRINT(ERR_DBG, "Write Test level %d fails\n", 2);
6014         }
6015
6016         *data = fail;
6017         return fail;
6018 }
6019
6020 /**
6021  * s2io_eeprom_test - to verify that EEprom in the xena can be programmed.
6022  * @sp : private member of the device structure, which is a pointer to the
6023  * s2io_nic structure.
6024  * @data:variable that returns the result of each of the test conducted by
6025  * the driver.
6026  * Description:
6027  * Verify that EEPROM in the xena can be programmed using I2C_CONTROL
6028  * register.
6029  * Return value:
6030  * 0 on success.
6031  */
6032
6033 static int s2io_eeprom_test(struct s2io_nic *sp, uint64_t *data)
6034 {
6035         int fail = 0;
6036         u64 ret_data, org_4F0, org_7F0;
6037         u8 saved_4F0 = 0, saved_7F0 = 0;
6038         struct net_device *dev = sp->dev;
6039
6040         /* Test Write Error at offset 0 */
6041         /* Note that SPI interface allows write access to all areas
6042          * of EEPROM. Hence doing all negative testing only for Xframe I.
6043          */
6044         if (sp->device_type == XFRAME_I_DEVICE)
6045                 if (!write_eeprom(sp, 0, 0, 3))
6046                         fail = 1;
6047
6048         /* Save current values at offsets 0x4F0 and 0x7F0 */
6049         if (!read_eeprom(sp, 0x4F0, &org_4F0))
6050                 saved_4F0 = 1;
6051         if (!read_eeprom(sp, 0x7F0, &org_7F0))
6052                 saved_7F0 = 1;
6053
6054         /* Test Write at offset 4f0 */
6055         if (write_eeprom(sp, 0x4F0, 0x012345, 3))
6056                 fail = 1;
6057         if (read_eeprom(sp, 0x4F0, &ret_data))
6058                 fail = 1;
6059
6060         if (ret_data != 0x012345) {
6061                 DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x4F0. "
6062                           "Data written %llx Data read %llx\n",
6063                           dev->name, (unsigned long long)0x12345,
6064                           (unsigned long long)ret_data);
6065                 fail = 1;
6066         }
6067
6068         /* Reset the EEPROM data go FFFF */
6069         write_eeprom(sp, 0x4F0, 0xFFFFFF, 3);
6070
6071         /* Test Write Request Error at offset 0x7c */
6072         if (sp->device_type == XFRAME_I_DEVICE)
6073                 if (!write_eeprom(sp, 0x07C, 0, 3))
6074                         fail = 1;
6075
6076         /* Test Write Request at offset 0x7f0 */
6077         if (write_eeprom(sp, 0x7F0, 0x012345, 3))
6078                 fail = 1;
6079         if (read_eeprom(sp, 0x7F0, &ret_data))
6080                 fail = 1;
6081
6082         if (ret_data != 0x012345) {
6083                 DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x7F0. "
6084                           "Data written %llx Data read %llx\n",
6085                           dev->name, (unsigned long long)0x12345,
6086                           (unsigned long long)ret_data);
6087                 fail = 1;
6088         }
6089
6090         /* Reset the EEPROM data go FFFF */
6091         write_eeprom(sp, 0x7F0, 0xFFFFFF, 3);
6092
6093         if (sp->device_type == XFRAME_I_DEVICE) {
6094                 /* Test Write Error at offset 0x80 */
6095                 if (!write_eeprom(sp, 0x080, 0, 3))
6096                         fail = 1;
6097
6098                 /* Test Write Error at offset 0xfc */
6099                 if (!write_eeprom(sp, 0x0FC, 0, 3))
6100                         fail = 1;
6101
6102                 /* Test Write Error at offset 0x100 */
6103                 if (!write_eeprom(sp, 0x100, 0, 3))
6104                         fail = 1;
6105
6106                 /* Test Write Error at offset 4ec */
6107                 if (!write_eeprom(sp, 0x4EC, 0, 3))
6108                         fail = 1;
6109         }
6110
6111         /* Restore values at offsets 0x4F0 and 0x7F0 */
6112         if (saved_4F0)
6113                 write_eeprom(sp, 0x4F0, org_4F0, 3);
6114         if (saved_7F0)
6115                 write_eeprom(sp, 0x7F0, org_7F0, 3);
6116
6117         *data = fail;
6118         return fail;
6119 }
6120
6121 /**
6122  * s2io_bist_test - invokes the MemBist test of the card .
6123  * @sp : private member of the device structure, which is a pointer to the
6124  * s2io_nic structure.
6125  * @data:variable that returns the result of each of the test conducted by
6126  * the driver.
6127  * Description:
6128  * This invokes the MemBist test of the card. We give around
6129  * 2 secs time for the Test to complete. If it's still not complete
6130  * within this peiod, we consider that the test failed.
6131  * Return value:
6132  * 0 on success and -1 on failure.
6133  */
6134
6135 static int s2io_bist_test(struct s2io_nic *sp, uint64_t *data)
6136 {
6137         u8 bist = 0;
6138         int cnt = 0, ret = -1;
6139
6140         pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
6141         bist |= PCI_BIST_START;
6142         pci_write_config_word(sp->pdev, PCI_BIST, bist);
6143
6144         while (cnt < 20) {
6145                 pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
6146                 if (!(bist & PCI_BIST_START)) {
6147                         *data = (bist & PCI_BIST_CODE_MASK);
6148                         ret = 0;
6149                         break;
6150                 }
6151                 msleep(100);
6152                 cnt++;
6153         }
6154
6155         return ret;
6156 }
6157
6158 /**
6159  * s2io-link_test - verifies the link state of the nic
6160  * @sp ; private member of the device structure, which is a pointer to the
6161  * s2io_nic structure.
6162  * @data: variable that returns the result of each of the test conducted by
6163  * the driver.
6164  * Description:
6165  * The function verifies the link state of the NIC and updates the input
6166  * argument 'data' appropriately.
6167  * Return value:
6168  * 0 on success.
6169  */
6170
6171 static int s2io_link_test(struct s2io_nic *sp, uint64_t *data)
6172 {
6173         struct XENA_dev_config __iomem *bar0 = sp->bar0;
6174         u64 val64;
6175
6176         val64 = readq(&bar0->adapter_status);
6177         if (!(LINK_IS_UP(val64)))
6178                 *data = 1;
6179         else
6180                 *data = 0;
6181
6182         return *data;
6183 }
6184
6185 /**
6186  * s2io_rldram_test - offline test for access to the RldRam chip on the NIC
6187  * @sp - private member of the device structure, which is a pointer to the
6188  * s2io_nic structure.
6189  * @data - variable that returns the result of each of the test
6190  * conducted by the driver.
6191  * Description:
6192  *  This is one of the offline test that tests the read and write
6193  *  access to the RldRam chip on the NIC.
6194  * Return value:
6195  *  0 on success.
6196  */
6197
6198 static int s2io_rldram_test(struct s2io_nic *sp, uint64_t *data)
6199 {
6200         struct XENA_dev_config __iomem *bar0 = sp->bar0;
6201         u64 val64;
6202         int cnt, iteration = 0, test_fail = 0;
6203
6204         val64 = readq(&bar0->adapter_control);
6205         val64 &= ~ADAPTER_ECC_EN;
6206         writeq(val64, &bar0->adapter_control);
6207
6208         val64 = readq(&bar0->mc_rldram_test_ctrl);
6209         val64 |= MC_RLDRAM_TEST_MODE;
6210         SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
6211
6212         val64 = readq(&bar0->mc_rldram_mrs);
6213         val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE;
6214         SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
6215
6216         val64 |= MC_RLDRAM_MRS_ENABLE;
6217         SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
6218
6219         while (iteration < 2) {
6220                 val64 = 0x55555555aaaa0000ULL;
6221                 if (iteration == 1)
6222                         val64 ^= 0xFFFFFFFFFFFF0000ULL;
6223                 writeq(val64, &bar0->mc_rldram_test_d0);
6224
6225                 val64 = 0xaaaa5a5555550000ULL;
6226                 if (iteration == 1)
6227                         val64 ^= 0xFFFFFFFFFFFF0000ULL;
6228                 writeq(val64, &bar0->mc_rldram_test_d1);
6229
6230                 val64 = 0x55aaaaaaaa5a0000ULL;
6231                 if (iteration == 1)
6232                         val64 ^= 0xFFFFFFFFFFFF0000ULL;
6233                 writeq(val64, &bar0->mc_rldram_test_d2);
6234
6235                 val64 = (u64) (0x0000003ffffe0100ULL);
6236                 writeq(val64, &bar0->mc_rldram_test_add);
6237
6238                 val64 = MC_RLDRAM_TEST_MODE |
6239                         MC_RLDRAM_TEST_WRITE |
6240                         MC_RLDRAM_TEST_GO;
6241                 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
6242
6243                 for (cnt = 0; cnt < 5; cnt++) {
6244                         val64 = readq(&bar0->mc_rldram_test_ctrl);
6245                         if (val64 & MC_RLDRAM_TEST_DONE)
6246                                 break;
6247                         msleep(200);
6248                 }
6249
6250                 if (cnt == 5)
6251                         break;
6252
6253                 val64 = MC_RLDRAM_TEST_MODE | MC_RLDRAM_TEST_GO;
6254                 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
6255
6256                 for (cnt = 0; cnt < 5; cnt++) {
6257                         val64 = readq(&bar0->mc_rldram_test_ctrl);
6258                         if (val64 & MC_RLDRAM_TEST_DONE)
6259                                 break;
6260                         msleep(500);
6261                 }
6262
6263                 if (cnt == 5)
6264                         break;
6265
6266                 val64 = readq(&bar0->mc_rldram_test_ctrl);
6267                 if (!(val64 & MC_RLDRAM_TEST_PASS))
6268                         test_fail = 1;
6269
6270                 iteration++;
6271         }
6272
6273         *data = test_fail;
6274
6275         /* Bring the adapter out of test mode */
6276         SPECIAL_REG_WRITE(0, &bar0->mc_rldram_test_ctrl, LF);
6277
6278         return test_fail;
6279 }
6280
6281 /**
6282  *  s2io_ethtool_test - conducts 6 tsets to determine the health of card.
6283  *  @sp : private member of the device structure, which is a pointer to the
6284  *  s2io_nic structure.
6285  *  @ethtest : pointer to a ethtool command specific structure that will be
6286  *  returned to the user.
6287  *  @data : variable that returns the result of each of the test
6288  * conducted by the driver.
6289  * Description:
6290  *  This function conducts 6 tests ( 4 offline and 2 online) to determine
6291  *  the health of the card.
6292  * Return value:
6293  *  void
6294  */
6295
6296 static void s2io_ethtool_test(struct net_device *dev,
6297                               struct ethtool_test *ethtest,
6298                               uint64_t *data)
6299 {
6300         struct s2io_nic *sp = netdev_priv(dev);
6301         int orig_state = netif_running(sp->dev);
6302
6303         if (ethtest->flags == ETH_TEST_FL_OFFLINE) {
6304                 /* Offline Tests. */
6305                 if (orig_state)
6306                         s2io_close(sp->dev);
6307
6308                 if (s2io_register_test(sp, &data[0]))
6309                         ethtest->flags |= ETH_TEST_FL_FAILED;
6310
6311                 s2io_reset(sp);
6312
6313                 if (s2io_rldram_test(sp, &data[3]))
6314                         ethtest->flags |= ETH_TEST_FL_FAILED;
6315
6316                 s2io_reset(sp);
6317
6318                 if (s2io_eeprom_test(sp, &data[1]))
6319                         ethtest->flags |= ETH_TEST_FL_FAILED;
6320
6321                 if (s2io_bist_test(sp, &data[4]))
6322                         ethtest->flags |= ETH_TEST_FL_FAILED;
6323
6324                 if (orig_state)
6325                         s2io_open(sp->dev);
6326
6327                 data[2] = 0;
6328         } else {
6329                 /* Online Tests. */
6330                 if (!orig_state) {
6331                         DBG_PRINT(ERR_DBG, "%s: is not up, cannot run test\n",
6332                                   dev->name);
6333                         data[0] = -1;
6334                         data[1] = -1;
6335                         data[2] = -1;
6336                         data[3] = -1;
6337                         data[4] = -1;
6338                 }
6339
6340                 if (s2io_link_test(sp, &data[2]))
6341                         ethtest->flags |= ETH_TEST_FL_FAILED;
6342
6343                 data[0] = 0;
6344                 data[1] = 0;
6345                 data[3] = 0;
6346                 data[4] = 0;
6347         }
6348 }
6349
6350 static void s2io_get_ethtool_stats(struct net_device *dev,
6351                                    struct ethtool_stats *estats,
6352                                    u64 *tmp_stats)
6353 {
6354         int i = 0, k;
6355         struct s2io_nic *sp = netdev_priv(dev);
6356         struct stat_block *stats = sp->mac_control.stats_info;
6357         struct swStat *swstats = &stats->sw_stat;
6358         struct xpakStat *xstats = &stats->xpak_stat;
6359
6360         s2io_updt_stats(sp);
6361         tmp_stats[i++] =
6362                 (u64)le32_to_cpu(stats->tmac_frms_oflow) << 32  |
6363                 le32_to_cpu(stats->tmac_frms);
6364         tmp_stats[i++] =
6365                 (u64)le32_to_cpu(stats->tmac_data_octets_oflow) << 32 |
6366                 le32_to_cpu(stats->tmac_data_octets);
6367         tmp_stats[i++] = le64_to_cpu(stats->tmac_drop_frms);
6368         tmp_stats[i++] =
6369                 (u64)le32_to_cpu(stats->tmac_mcst_frms_oflow) << 32 |
6370                 le32_to_cpu(stats->tmac_mcst_frms);
6371         tmp_stats[i++] =
6372                 (u64)le32_to_cpu(stats->tmac_bcst_frms_oflow) << 32 |
6373                 le32_to_cpu(stats->tmac_bcst_frms);
6374         tmp_stats[i++] = le64_to_cpu(stats->tmac_pause_ctrl_frms);
6375         tmp_stats[i++] =
6376                 (u64)le32_to_cpu(stats->tmac_ttl_octets_oflow) << 32 |
6377                 le32_to_cpu(stats->tmac_ttl_octets);
6378         tmp_stats[i++] =
6379                 (u64)le32_to_cpu(stats->tmac_ucst_frms_oflow) << 32 |
6380                 le32_to_cpu(stats->tmac_ucst_frms);
6381         tmp_stats[i++] =
6382                 (u64)le32_to_cpu(stats->tmac_nucst_frms_oflow) << 32 |
6383                 le32_to_cpu(stats->tmac_nucst_frms);
6384         tmp_stats[i++] =
6385                 (u64)le32_to_cpu(stats->tmac_any_err_frms_oflow) << 32 |
6386                 le32_to_cpu(stats->tmac_any_err_frms);
6387         tmp_stats[i++] = le64_to_cpu(stats->tmac_ttl_less_fb_octets);
6388         tmp_stats[i++] = le64_to_cpu(stats->tmac_vld_ip_octets);
6389         tmp_stats[i++] =
6390                 (u64)le32_to_cpu(stats->tmac_vld_ip_oflow) << 32 |
6391                 le32_to_cpu(stats->tmac_vld_ip);
6392         tmp_stats[i++] =
6393                 (u64)le32_to_cpu(stats->tmac_drop_ip_oflow) << 32 |
6394                 le32_to_cpu(stats->tmac_drop_ip);
6395         tmp_stats[i++] =
6396                 (u64)le32_to_cpu(stats->tmac_icmp_oflow) << 32 |
6397                 le32_to_cpu(stats->tmac_icmp);
6398         tmp_stats[i++] =
6399                 (u64)le32_to_cpu(stats->tmac_rst_tcp_oflow) << 32 |
6400                 le32_to_cpu(stats->tmac_rst_tcp);
6401         tmp_stats[i++] = le64_to_cpu(stats->tmac_tcp);
6402         tmp_stats[i++] = (u64)le32_to_cpu(stats->tmac_udp_oflow) << 32 |
6403                 le32_to_cpu(stats->tmac_udp);
6404         tmp_stats[i++] =
6405                 (u64)le32_to_cpu(stats->rmac_vld_frms_oflow) << 32 |
6406                 le32_to_cpu(stats->rmac_vld_frms);
6407         tmp_stats[i++] =
6408                 (u64)le32_to_cpu(stats->rmac_data_octets_oflow) << 32 |
6409                 le32_to_cpu(stats->rmac_data_octets);
6410         tmp_stats[i++] = le64_to_cpu(stats->rmac_fcs_err_frms);
6411         tmp_stats[i++] = le64_to_cpu(stats->rmac_drop_frms);
6412         tmp_stats[i++] =
6413                 (u64)le32_to_cpu(stats->rmac_vld_mcst_frms_oflow) << 32 |
6414                 le32_to_cpu(stats->rmac_vld_mcst_frms);
6415         tmp_stats[i++] =
6416                 (u64)le32_to_cpu(stats->rmac_vld_bcst_frms_oflow) << 32 |
6417                 le32_to_cpu(stats->rmac_vld_bcst_frms);
6418         tmp_stats[i++] = le32_to_cpu(stats->rmac_in_rng_len_err_frms);
6419         tmp_stats[i++] = le32_to_cpu(stats->rmac_out_rng_len_err_frms);
6420         tmp_stats[i++] = le64_to_cpu(stats->rmac_long_frms);
6421         tmp_stats[i++] = le64_to_cpu(stats->rmac_pause_ctrl_frms);
6422         tmp_stats[i++] = le64_to_cpu(stats->rmac_unsup_ctrl_frms);
6423         tmp_stats[i++] =
6424                 (u64)le32_to_cpu(stats->rmac_ttl_octets_oflow) << 32 |
6425                 le32_to_cpu(stats->rmac_ttl_octets);
6426         tmp_stats[i++] =
6427                 (u64)le32_to_cpu(stats->rmac_accepted_ucst_frms_oflow) << 32
6428                 | le32_to_cpu(stats->rmac_accepted_ucst_frms);
6429         tmp_stats[i++] =
6430                 (u64)le32_to_cpu(stats->rmac_accepted_nucst_frms_oflow)
6431                 << 32 | le32_to_cpu(stats->rmac_accepted_nucst_frms);
6432         tmp_stats[i++] =
6433                 (u64)le32_to_cpu(stats->rmac_discarded_frms_oflow) << 32 |
6434                 le32_to_cpu(stats->rmac_discarded_frms);
6435         tmp_stats[i++] =
6436                 (u64)le32_to_cpu(stats->rmac_drop_events_oflow)
6437                 << 32 | le32_to_cpu(stats->rmac_drop_events);
6438         tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_less_fb_octets);
6439         tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_frms);
6440         tmp_stats[i++] =
6441                 (u64)le32_to_cpu(stats->rmac_usized_frms_oflow) << 32 |
6442                 le32_to_cpu(stats->rmac_usized_frms);
6443         tmp_stats[i++] =
6444                 (u64)le32_to_cpu(stats->rmac_osized_frms_oflow) << 32 |
6445                 le32_to_cpu(stats->rmac_osized_frms);
6446         tmp_stats[i++] =
6447                 (u64)le32_to_cpu(stats->rmac_frag_frms_oflow) << 32 |
6448                 le32_to_cpu(stats->rmac_frag_frms);
6449         tmp_stats[i++] =
6450                 (u64)le32_to_cpu(stats->rmac_jabber_frms_oflow) << 32 |
6451                 le32_to_cpu(stats->rmac_jabber_frms);
6452         tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_64_frms);
6453         tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_65_127_frms);
6454         tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_128_255_frms);
6455         tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_256_511_frms);
6456         tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_512_1023_frms);
6457         tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_1024_1518_frms);
6458         tmp_stats[i++] =
6459                 (u64)le32_to_cpu(stats->rmac_ip_oflow) << 32 |
6460                 le32_to_cpu(stats->rmac_ip);
6461         tmp_stats[i++] = le64_to_cpu(stats->rmac_ip_octets);
6462         tmp_stats[i++] = le32_to_cpu(stats->rmac_hdr_err_ip);
6463         tmp_stats[i++] =
6464                 (u64)le32_to_cpu(stats->rmac_drop_ip_oflow) << 32 |
6465                 le32_to_cpu(stats->rmac_drop_ip);
6466         tmp_stats[i++] =
6467                 (u64)le32_to_cpu(stats->rmac_icmp_oflow) << 32 |
6468                 le32_to_cpu(stats->rmac_icmp);
6469         tmp_stats[i++] = le64_to_cpu(stats->rmac_tcp);
6470         tmp_stats[i++] =
6471                 (u64)le32_to_cpu(stats->rmac_udp_oflow) << 32 |
6472                 le32_to_cpu(stats->rmac_udp);
6473         tmp_stats[i++] =
6474                 (u64)le32_to_cpu(stats->rmac_err_drp_udp_oflow) << 32 |
6475                 le32_to_cpu(stats->rmac_err_drp_udp);
6476         tmp_stats[i++] = le64_to_cpu(stats->rmac_xgmii_err_sym);
6477         tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q0);
6478         tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q1);
6479         tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q2);
6480         tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q3);
6481         tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q4);
6482         tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q5);
6483         tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q6);
6484         tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q7);
6485         tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q0);
6486         tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q1);
6487         tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q2);
6488         tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q3);
6489         tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q4);
6490         tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q5);
6491         tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q6);
6492         tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q7);
6493         tmp_stats[i++] =
6494                 (u64)le32_to_cpu(stats->rmac_pause_cnt_oflow) << 32 |
6495                 le32_to_cpu(stats->rmac_pause_cnt);
6496         tmp_stats[i++] = le64_to_cpu(stats->rmac_xgmii_data_err_cnt);
6497         tmp_stats[i++] = le64_to_cpu(stats->rmac_xgmii_ctrl_err_cnt);
6498         tmp_stats[i++] =
6499                 (u64)le32_to_cpu(stats->rmac_accepted_ip_oflow) << 32 |
6500                 le32_to_cpu(stats->rmac_accepted_ip);
6501         tmp_stats[i++] = le32_to_cpu(stats->rmac_err_tcp);
6502         tmp_stats[i++] = le32_to_cpu(stats->rd_req_cnt);
6503         tmp_stats[i++] = le32_to_cpu(stats->new_rd_req_cnt);
6504         tmp_stats[i++] = le32_to_cpu(stats->new_rd_req_rtry_cnt);
6505         tmp_stats[i++] = le32_to_cpu(stats->rd_rtry_cnt);
6506         tmp_stats[i++] = le32_to_cpu(stats->wr_rtry_rd_ack_cnt);
6507         tmp_stats[i++] = le32_to_cpu(stats->wr_req_cnt);
6508         tmp_stats[i++] = le32_to_cpu(stats->new_wr_req_cnt);
6509         tmp_stats[i++] = le32_to_cpu(stats->new_wr_req_rtry_cnt);
6510         tmp_stats[i++] = le32_to_cpu(stats->wr_rtry_cnt);
6511         tmp_stats[i++] = le32_to_cpu(stats->wr_disc_cnt);
6512         tmp_stats[i++] = le32_to_cpu(stats->rd_rtry_wr_ack_cnt);
6513         tmp_stats[i++] = le32_to_cpu(stats->txp_wr_cnt);
6514         tmp_stats[i++] = le32_to_cpu(stats->txd_rd_cnt);
6515         tmp_stats[i++] = le32_to_cpu(stats->txd_wr_cnt);
6516         tmp_stats[i++] = le32_to_cpu(stats->rxd_rd_cnt);
6517         tmp_stats[i++] = le32_to_cpu(stats->rxd_wr_cnt);
6518         tmp_stats[i++] = le32_to_cpu(stats->txf_rd_cnt);
6519         tmp_stats[i++] = le32_to_cpu(stats->rxf_wr_cnt);
6520
6521         /* Enhanced statistics exist only for Hercules */
6522         if (sp->device_type == XFRAME_II_DEVICE) {
6523                 tmp_stats[i++] =
6524                         le64_to_cpu(stats->rmac_ttl_1519_4095_frms);
6525                 tmp_stats[i++] =
6526                         le64_to_cpu(stats->rmac_ttl_4096_8191_frms);
6527                 tmp_stats[i++] =
6528                         le64_to_cpu(stats->rmac_ttl_8192_max_frms);
6529                 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_gt_max_frms);
6530                 tmp_stats[i++] = le64_to_cpu(stats->rmac_osized_alt_frms);
6531                 tmp_stats[i++] = le64_to_cpu(stats->rmac_jabber_alt_frms);
6532                 tmp_stats[i++] = le64_to_cpu(stats->rmac_gt_max_alt_frms);
6533                 tmp_stats[i++] = le64_to_cpu(stats->rmac_vlan_frms);
6534                 tmp_stats[i++] = le32_to_cpu(stats->rmac_len_discard);
6535                 tmp_stats[i++] = le32_to_cpu(stats->rmac_fcs_discard);
6536                 tmp_stats[i++] = le32_to_cpu(stats->rmac_pf_discard);
6537                 tmp_stats[i++] = le32_to_cpu(stats->rmac_da_discard);
6538                 tmp_stats[i++] = le32_to_cpu(stats->rmac_red_discard);
6539                 tmp_stats[i++] = le32_to_cpu(stats->rmac_rts_discard);
6540                 tmp_stats[i++] = le32_to_cpu(stats->rmac_ingm_full_discard);
6541                 tmp_stats[i++] = le32_to_cpu(stats->link_fault_cnt);
6542         }
6543
6544         tmp_stats[i++] = 0;
6545         tmp_stats[i++] = swstats->single_ecc_errs;
6546         tmp_stats[i++] = swstats->double_ecc_errs;
6547         tmp_stats[i++] = swstats->parity_err_cnt;
6548         tmp_stats[i++] = swstats->serious_err_cnt;
6549         tmp_stats[i++] = swstats->soft_reset_cnt;
6550         tmp_stats[i++] = swstats->fifo_full_cnt;
6551         for (k = 0; k < MAX_RX_RINGS; k++)
6552                 tmp_stats[i++] = swstats->ring_full_cnt[k];
6553         tmp_stats[i++] = xstats->alarm_transceiver_temp_high;
6554         tmp_stats[i++] = xstats->alarm_transceiver_temp_low;
6555         tmp_stats[i++] = xstats->alarm_laser_bias_current_high;
6556         tmp_stats[i++] = xstats->alarm_laser_bias_current_low;
6557         tmp_stats[i++] = xstats->alarm_laser_output_power_high;
6558         tmp_stats[i++] = xstats->alarm_laser_output_power_low;
6559         tmp_stats[i++] = xstats->warn_transceiver_temp_high;
6560         tmp_stats[i++] = xstats->warn_transceiver_temp_low;
6561         tmp_stats[i++] = xstats->warn_laser_bias_current_high;
6562         tmp_stats[i++] = xstats->warn_laser_bias_current_low;
6563         tmp_stats[i++] = xstats->warn_laser_output_power_high;
6564         tmp_stats[i++] = xstats->warn_laser_output_power_low;
6565         tmp_stats[i++] = swstats->clubbed_frms_cnt;
6566         tmp_stats[i++] = swstats->sending_both;
6567         tmp_stats[i++] = swstats->outof_sequence_pkts;
6568         tmp_stats[i++] = swstats->flush_max_pkts;
6569         if (swstats->num_aggregations) {
6570                 u64 tmp = swstats->sum_avg_pkts_aggregated;
6571                 int count = 0;
6572                 /*
6573                  * Since 64-bit divide does not work on all platforms,
6574                  * do repeated subtraction.
6575                  */
6576                 while (tmp >= swstats->num_aggregations) {
6577                         tmp -= swstats->num_aggregations;
6578                         count++;
6579                 }
6580                 tmp_stats[i++] = count;
6581         } else
6582                 tmp_stats[i++] = 0;
6583         tmp_stats[i++] = swstats->mem_alloc_fail_cnt;
6584         tmp_stats[i++] = swstats->pci_map_fail_cnt;
6585         tmp_stats[i++] = swstats->watchdog_timer_cnt;
6586         tmp_stats[i++] = swstats->mem_allocated;
6587         tmp_stats[i++] = swstats->mem_freed;
6588         tmp_stats[i++] = swstats->link_up_cnt;
6589         tmp_stats[i++] = swstats->link_down_cnt;
6590         tmp_stats[i++] = swstats->link_up_time;
6591         tmp_stats[i++] = swstats->link_down_time;
6592
6593         tmp_stats[i++] = swstats->tx_buf_abort_cnt;
6594         tmp_stats[i++] = swstats->tx_desc_abort_cnt;
6595         tmp_stats[i++] = swstats->tx_parity_err_cnt;
6596         tmp_stats[i++] = swstats->tx_link_loss_cnt;
6597         tmp_stats[i++] = swstats->tx_list_proc_err_cnt;
6598
6599         tmp_stats[i++] = swstats->rx_parity_err_cnt;
6600         tmp_stats[i++] = swstats->rx_abort_cnt;
6601         tmp_stats[i++] = swstats->rx_parity_abort_cnt;
6602         tmp_stats[i++] = swstats->rx_rda_fail_cnt;
6603         tmp_stats[i++] = swstats->rx_unkn_prot_cnt;
6604         tmp_stats[i++] = swstats->rx_fcs_err_cnt;
6605         tmp_stats[i++] = swstats->rx_buf_size_err_cnt;
6606         tmp_stats[i++] = swstats->rx_rxd_corrupt_cnt;
6607         tmp_stats[i++] = swstats->rx_unkn_err_cnt;
6608         tmp_stats[i++] = swstats->tda_err_cnt;
6609         tmp_stats[i++] = swstats->pfc_err_cnt;
6610         tmp_stats[i++] = swstats->pcc_err_cnt;
6611         tmp_stats[i++] = swstats->tti_err_cnt;
6612         tmp_stats[i++] = swstats->tpa_err_cnt;
6613         tmp_stats[i++] = swstats->sm_err_cnt;
6614         tmp_stats[i++] = swstats->lso_err_cnt;
6615         tmp_stats[i++] = swstats->mac_tmac_err_cnt;
6616         tmp_stats[i++] = swstats->mac_rmac_err_cnt;
6617         tmp_stats[i++] = swstats->xgxs_txgxs_err_cnt;
6618         tmp_stats[i++] = swstats->xgxs_rxgxs_err_cnt;
6619         tmp_stats[i++] = swstats->rc_err_cnt;
6620         tmp_stats[i++] = swstats->prc_pcix_err_cnt;
6621         tmp_stats[i++] = swstats->rpa_err_cnt;
6622         tmp_stats[i++] = swstats->rda_err_cnt;
6623         tmp_stats[i++] = swstats->rti_err_cnt;
6624         tmp_stats[i++] = swstats->mc_err_cnt;
6625 }
6626
6627 static int s2io_ethtool_get_regs_len(struct net_device *dev)
6628 {
6629         return XENA_REG_SPACE;
6630 }
6631
6632
6633 static u32 s2io_ethtool_get_rx_csum(struct net_device *dev)
6634 {
6635         struct s2io_nic *sp = netdev_priv(dev);
6636
6637         return sp->rx_csum;
6638 }
6639
6640 static int s2io_ethtool_set_rx_csum(struct net_device *dev, u32 data)
6641 {
6642         struct s2io_nic *sp = netdev_priv(dev);
6643
6644         if (data)
6645                 sp->rx_csum = 1;
6646         else
6647                 sp->rx_csum = 0;
6648
6649         return 0;
6650 }
6651
6652 static int s2io_get_eeprom_len(struct net_device *dev)
6653 {
6654         return XENA_EEPROM_SPACE;
6655 }
6656
6657 static int s2io_get_sset_count(struct net_device *dev, int sset)
6658 {
6659         struct s2io_nic *sp = netdev_priv(dev);
6660
6661         switch (sset) {
6662         case ETH_SS_TEST:
6663                 return S2IO_TEST_LEN;
6664         case ETH_SS_STATS:
6665                 switch (sp->device_type) {
6666                 case XFRAME_I_DEVICE:
6667                         return XFRAME_I_STAT_LEN;
6668                 case XFRAME_II_DEVICE:
6669                         return XFRAME_II_STAT_LEN;
6670                 default:
6671                         return 0;
6672                 }
6673         default:
6674                 return -EOPNOTSUPP;
6675         }
6676 }
6677
6678 static void s2io_ethtool_get_strings(struct net_device *dev,
6679                                      u32 stringset, u8 *data)
6680 {
6681         int stat_size = 0;
6682         struct s2io_nic *sp = netdev_priv(dev);
6683
6684         switch (stringset) {
6685         case ETH_SS_TEST:
6686                 memcpy(data, s2io_gstrings, S2IO_STRINGS_LEN);
6687                 break;
6688         case ETH_SS_STATS:
6689                 stat_size = sizeof(ethtool_xena_stats_keys);
6690                 memcpy(data, &ethtool_xena_stats_keys, stat_size);
6691                 if (sp->device_type == XFRAME_II_DEVICE) {
6692                         memcpy(data + stat_size,
6693                                &ethtool_enhanced_stats_keys,
6694                                sizeof(ethtool_enhanced_stats_keys));
6695                         stat_size += sizeof(ethtool_enhanced_stats_keys);
6696                 }
6697
6698                 memcpy(data + stat_size, &ethtool_driver_stats_keys,
6699                        sizeof(ethtool_driver_stats_keys));
6700         }
6701 }
6702
6703 static int s2io_ethtool_op_set_tx_csum(struct net_device *dev, u32 data)
6704 {
6705         if (data)
6706                 dev->features |= NETIF_F_IP_CSUM;
6707         else
6708                 dev->features &= ~NETIF_F_IP_CSUM;
6709
6710         return 0;
6711 }
6712
6713 static u32 s2io_ethtool_op_get_tso(struct net_device *dev)
6714 {
6715         return (dev->features & NETIF_F_TSO) != 0;
6716 }
6717
6718 static int s2io_ethtool_op_set_tso(struct net_device *dev, u32 data)
6719 {
6720         if (data)
6721                 dev->features |= (NETIF_F_TSO | NETIF_F_TSO6);
6722         else
6723                 dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
6724
6725         return 0;
6726 }
6727
6728 static int s2io_ethtool_set_flags(struct net_device *dev, u32 data)
6729 {
6730         struct s2io_nic *sp = netdev_priv(dev);
6731         int rc = 0;
6732         int changed = 0;
6733
6734         if (data & ~ETH_FLAG_LRO)
6735                 return -EINVAL;
6736
6737         if (data & ETH_FLAG_LRO) {
6738                 if (lro_enable) {
6739                         if (!(dev->features & NETIF_F_LRO)) {
6740                                 dev->features |= NETIF_F_LRO;
6741                                 changed = 1;
6742                         }
6743                 } else
6744                         rc = -EINVAL;
6745         } else if (dev->features & NETIF_F_LRO) {
6746                 dev->features &= ~NETIF_F_LRO;
6747                 changed = 1;
6748         }
6749
6750         if (changed && netif_running(dev)) {
6751                 s2io_stop_all_tx_queue(sp);
6752                 s2io_card_down(sp);
6753                 sp->lro = !!(dev->features & NETIF_F_LRO);
6754                 rc = s2io_card_up(sp);
6755                 if (rc)
6756                         s2io_reset(sp);
6757                 else
6758                         s2io_start_all_tx_queue(sp);
6759         }
6760
6761         return rc;
6762 }
6763
6764 static const struct ethtool_ops netdev_ethtool_ops = {
6765         .get_settings = s2io_ethtool_gset,
6766         .set_settings = s2io_ethtool_sset,
6767         .get_drvinfo = s2io_ethtool_gdrvinfo,
6768         .get_regs_len = s2io_ethtool_get_regs_len,
6769         .get_regs = s2io_ethtool_gregs,
6770         .get_link = ethtool_op_get_link,
6771         .get_eeprom_len = s2io_get_eeprom_len,
6772         .get_eeprom = s2io_ethtool_geeprom,
6773         .set_eeprom = s2io_ethtool_seeprom,
6774         .get_ringparam = s2io_ethtool_gringparam,
6775         .get_pauseparam = s2io_ethtool_getpause_data,
6776         .set_pauseparam = s2io_ethtool_setpause_data,
6777         .get_rx_csum = s2io_ethtool_get_rx_csum,
6778         .set_rx_csum = s2io_ethtool_set_rx_csum,
6779         .set_tx_csum = s2io_ethtool_op_set_tx_csum,
6780         .set_flags = s2io_ethtool_set_flags,
6781         .get_flags = ethtool_op_get_flags,
6782         .set_sg = ethtool_op_set_sg,
6783         .get_tso = s2io_ethtool_op_get_tso,
6784         .set_tso = s2io_ethtool_op_set_tso,
6785         .set_ufo = ethtool_op_set_ufo,
6786         .self_test = s2io_ethtool_test,
6787         .get_strings = s2io_ethtool_get_strings,
6788         .phys_id = s2io_ethtool_idnic,
6789         .get_ethtool_stats = s2io_get_ethtool_stats,
6790         .get_sset_count = s2io_get_sset_count,
6791 };
6792
6793 /**
6794  *  s2io_ioctl - Entry point for the Ioctl
6795  *  @dev :  Device pointer.
6796  *  @ifr :  An IOCTL specefic structure, that can contain a pointer to
6797  *  a proprietary structure used to pass information to the driver.
6798  *  @cmd :  This is used to distinguish between the different commands that
6799  *  can be passed to the IOCTL functions.
6800  *  Description:
6801  *  Currently there are no special functionality supported in IOCTL, hence
6802  *  function always return EOPNOTSUPPORTED
6803  */
6804
6805 static int s2io_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
6806 {
6807         return -EOPNOTSUPP;
6808 }
6809
6810 /**
6811  *  s2io_change_mtu - entry point to change MTU size for the device.
6812  *   @dev : device pointer.
6813  *   @new_mtu : the new MTU size for the device.
6814  *   Description: A driver entry point to change MTU size for the device.
6815  *   Before changing the MTU the device must be stopped.
6816  *  Return value:
6817  *   0 on success and an appropriate (-)ve integer as defined in errno.h
6818  *   file on failure.
6819  */
6820
6821 static int s2io_change_mtu(struct net_device *dev, int new_mtu)
6822 {
6823         struct s2io_nic *sp = netdev_priv(dev);
6824         int ret = 0;
6825
6826         if ((new_mtu < MIN_MTU) || (new_mtu > S2IO_JUMBO_SIZE)) {
6827                 DBG_PRINT(ERR_DBG, "%s: MTU size is invalid.\n", dev->name);
6828                 return -EPERM;
6829         }
6830
6831         dev->mtu = new_mtu;
6832         if (netif_running(dev)) {
6833                 s2io_stop_all_tx_queue(sp);
6834                 s2io_card_down(sp);
6835                 ret = s2io_card_up(sp);
6836                 if (ret) {
6837                         DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n",
6838                                   __func__);
6839                         return ret;
6840                 }
6841                 s2io_wake_all_tx_queue(sp);
6842         } else { /* Device is down */
6843                 struct XENA_dev_config __iomem *bar0 = sp->bar0;
6844                 u64 val64 = new_mtu;
6845
6846                 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
6847         }
6848
6849         return ret;
6850 }
6851
6852 /**
6853  * s2io_set_link - Set the LInk status
6854  * @data: long pointer to device private structue
6855  * Description: Sets the link status for the adapter
6856  */
6857
6858 static void s2io_set_link(struct work_struct *work)
6859 {
6860         struct s2io_nic *nic = container_of(work, struct s2io_nic,
6861                                             set_link_task);
6862         struct net_device *dev = nic->dev;
6863         struct XENA_dev_config __iomem *bar0 = nic->bar0;
6864         register u64 val64;
6865         u16 subid;
6866
6867         rtnl_lock();
6868
6869         if (!netif_running(dev))
6870                 goto out_unlock;
6871
6872         if (test_and_set_bit(__S2IO_STATE_LINK_TASK, &(nic->state))) {
6873                 /* The card is being reset, no point doing anything */
6874                 goto out_unlock;
6875         }
6876
6877         subid = nic->pdev->subsystem_device;
6878         if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
6879                 /*
6880                  * Allow a small delay for the NICs self initiated
6881                  * cleanup to complete.
6882                  */
6883                 msleep(100);
6884         }
6885
6886         val64 = readq(&bar0->adapter_status);
6887         if (LINK_IS_UP(val64)) {
6888                 if (!(readq(&bar0->adapter_control) & ADAPTER_CNTL_EN)) {
6889                         if (verify_xena_quiescence(nic)) {
6890                                 val64 = readq(&bar0->adapter_control);
6891                                 val64 |= ADAPTER_CNTL_EN;
6892                                 writeq(val64, &bar0->adapter_control);
6893                                 if (CARDS_WITH_FAULTY_LINK_INDICATORS(
6894                                             nic->device_type, subid)) {
6895                                         val64 = readq(&bar0->gpio_control);
6896                                         val64 |= GPIO_CTRL_GPIO_0;
6897                                         writeq(val64, &bar0->gpio_control);
6898                                         val64 = readq(&bar0->gpio_control);
6899                                 } else {
6900                                         val64 |= ADAPTER_LED_ON;
6901                                         writeq(val64, &bar0->adapter_control);
6902                                 }
6903                                 nic->device_enabled_once = true;
6904                         } else {
6905                                 DBG_PRINT(ERR_DBG,
6906                                           "%s: Error: device is not Quiescent\n",
6907                                           dev->name);
6908                                 s2io_stop_all_tx_queue(nic);
6909                         }
6910                 }
6911                 val64 = readq(&bar0->adapter_control);
6912                 val64 |= ADAPTER_LED_ON;
6913                 writeq(val64, &bar0->adapter_control);
6914                 s2io_link(nic, LINK_UP);
6915         } else {
6916                 if (CARDS_WITH_FAULTY_LINK_INDICATORS(nic->device_type,
6917                                                       subid)) {
6918                         val64 = readq(&bar0->gpio_control);
6919                         val64 &= ~GPIO_CTRL_GPIO_0;
6920                         writeq(val64, &bar0->gpio_control);
6921                         val64 = readq(&bar0->gpio_control);
6922                 }
6923                 /* turn off LED */
6924                 val64 = readq(&bar0->adapter_control);
6925                 val64 = val64 & (~ADAPTER_LED_ON);
6926                 writeq(val64, &bar0->adapter_control);
6927                 s2io_link(nic, LINK_DOWN);
6928         }
6929         clear_bit(__S2IO_STATE_LINK_TASK, &(nic->state));
6930
6931 out_unlock:
6932         rtnl_unlock();
6933 }
6934
6935 static int set_rxd_buffer_pointer(struct s2io_nic *sp, struct RxD_t *rxdp,
6936                                   struct buffAdd *ba,
6937                                   struct sk_buff **skb, u64 *temp0, u64 *temp1,
6938                                   u64 *temp2, int size)
6939 {
6940         struct net_device *dev = sp->dev;
6941         struct swStat *stats = &sp->mac_control.stats_info->sw_stat;
6942
6943         if ((sp->rxd_mode == RXD_MODE_1) && (rxdp->Host_Control == 0)) {
6944                 struct RxD1 *rxdp1 = (struct RxD1 *)rxdp;
6945                 /* allocate skb */
6946                 if (*skb) {
6947                         DBG_PRINT(INFO_DBG, "SKB is not NULL\n");
6948                         /*
6949                          * As Rx frame are not going to be processed,
6950                          * using same mapped address for the Rxd
6951                          * buffer pointer
6952                          */
6953                         rxdp1->Buffer0_ptr = *temp0;
6954                 } else {
6955                         *skb = dev_alloc_skb(size);
6956                         if (!(*skb)) {
6957                                 DBG_PRINT(INFO_DBG,
6958                                           "%s: Out of memory to allocate %s\n",
6959                                           dev->name, "1 buf mode SKBs");
6960                                 stats->mem_alloc_fail_cnt++;
6961                                 return -ENOMEM ;
6962                         }
6963                         stats->mem_allocated += (*skb)->truesize;
6964                         /* storing the mapped addr in a temp variable
6965                          * such it will be used for next rxd whose
6966                          * Host Control is NULL
6967                          */
6968                         rxdp1->Buffer0_ptr = *temp0 =
6969                                 pci_map_single(sp->pdev, (*skb)->data,
6970                                                size - NET_IP_ALIGN,
6971                                                PCI_DMA_FROMDEVICE);
6972                         if (pci_dma_mapping_error(sp->pdev, rxdp1->Buffer0_ptr))
6973                                 goto memalloc_failed;
6974                         rxdp->Host_Control = (unsigned long) (*skb);
6975                 }
6976         } else if ((sp->rxd_mode == RXD_MODE_3B) && (rxdp->Host_Control == 0)) {
6977                 struct RxD3 *rxdp3 = (struct RxD3 *)rxdp;
6978                 /* Two buffer Mode */
6979                 if (*skb) {
6980                         rxdp3->Buffer2_ptr = *temp2;
6981                         rxdp3->Buffer0_ptr = *temp0;
6982                         rxdp3->Buffer1_ptr = *temp1;
6983                 } else {
6984                         *skb = dev_alloc_skb(size);
6985                         if (!(*skb)) {
6986                                 DBG_PRINT(INFO_DBG,
6987                                           "%s: Out of memory to allocate %s\n",
6988                                           dev->name,
6989                                           "2 buf mode SKBs");
6990                                 stats->mem_alloc_fail_cnt++;
6991                                 return -ENOMEM;
6992                         }
6993                         stats->mem_allocated += (*skb)->truesize;
6994                         rxdp3->Buffer2_ptr = *temp2 =
6995                                 pci_map_single(sp->pdev, (*skb)->data,
6996                                                dev->mtu + 4,
6997                                                PCI_DMA_FROMDEVICE);
6998                         if (pci_dma_mapping_error(sp->pdev, rxdp3->Buffer2_ptr))
6999                                 goto memalloc_failed;
7000                         rxdp3->Buffer0_ptr = *temp0 =
7001                                 pci_map_single(sp->pdev, ba->ba_0, BUF0_LEN,
7002                                                PCI_DMA_FROMDEVICE);
7003                         if (pci_dma_mapping_error(sp->pdev,
7004                                                   rxdp3->Buffer0_ptr)) {
7005                                 pci_unmap_single(sp->pdev,
7006                                                  (dma_addr_t)rxdp3->Buffer2_ptr,
7007                                                  dev->mtu + 4,
7008                                                  PCI_DMA_FROMDEVICE);
7009                                 goto memalloc_failed;
7010                         }
7011                         rxdp->Host_Control = (unsigned long) (*skb);
7012
7013                         /* Buffer-1 will be dummy buffer not used */
7014                         rxdp3->Buffer1_ptr = *temp1 =
7015                                 pci_map_single(sp->pdev, ba->ba_1, BUF1_LEN,
7016                                                PCI_DMA_FROMDEVICE);
7017                         if (pci_dma_mapping_error(sp->pdev,
7018                                                   rxdp3->Buffer1_ptr)) {
7019                                 pci_unmap_single(sp->pdev,
7020                                                  (dma_addr_t)rxdp3->Buffer0_ptr,
7021                                                  BUF0_LEN, PCI_DMA_FROMDEVICE);
7022                                 pci_unmap_single(sp->pdev,
7023                                                  (dma_addr_t)rxdp3->Buffer2_ptr,
7024                                                  dev->mtu + 4,
7025                                                  PCI_DMA_FROMDEVICE);
7026                                 goto memalloc_failed;
7027                         }
7028                 }
7029         }
7030         return 0;
7031
7032 memalloc_failed:
7033         stats->pci_map_fail_cnt++;
7034         stats->mem_freed += (*skb)->truesize;
7035         dev_kfree_skb(*skb);
7036         return -ENOMEM;
7037 }
7038
7039 static void set_rxd_buffer_size(struct s2io_nic *sp, struct RxD_t *rxdp,
7040                                 int size)
7041 {
7042         struct net_device *dev = sp->dev;
7043         if (sp->rxd_mode == RXD_MODE_1) {
7044                 rxdp->Control_2 = SET_BUFFER0_SIZE_1(size - NET_IP_ALIGN);
7045         } else if (sp->rxd_mode == RXD_MODE_3B) {
7046                 rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
7047                 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
7048                 rxdp->Control_2 |= SET_BUFFER2_SIZE_3(dev->mtu + 4);
7049         }
7050 }
7051
7052 static  int rxd_owner_bit_reset(struct s2io_nic *sp)
7053 {
7054         int i, j, k, blk_cnt = 0, size;
7055         struct config_param *config = &sp->config;
7056         struct mac_info *mac_control = &sp->mac_control;
7057         struct net_device *dev = sp->dev;
7058         struct RxD_t *rxdp = NULL;
7059         struct sk_buff *skb = NULL;
7060         struct buffAdd *ba = NULL;
7061         u64 temp0_64 = 0, temp1_64 = 0, temp2_64 = 0;
7062
7063         /* Calculate the size based on ring mode */
7064         size = dev->mtu + HEADER_ETHERNET_II_802_3_SIZE +
7065                 HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
7066         if (sp->rxd_mode == RXD_MODE_1)
7067                 size += NET_IP_ALIGN;
7068         else if (sp->rxd_mode == RXD_MODE_3B)
7069                 size = dev->mtu + ALIGN_SIZE + BUF0_LEN + 4;
7070
7071         for (i = 0; i < config->rx_ring_num; i++) {
7072                 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
7073                 struct ring_info *ring = &mac_control->rings[i];
7074
7075                 blk_cnt = rx_cfg->num_rxd / (rxd_count[sp->rxd_mode] + 1);
7076
7077                 for (j = 0; j < blk_cnt; j++) {
7078                         for (k = 0; k < rxd_count[sp->rxd_mode]; k++) {
7079                                 rxdp = ring->rx_blocks[j].rxds[k].virt_addr;
7080                                 if (sp->rxd_mode == RXD_MODE_3B)
7081                                         ba = &ring->ba[j][k];
7082                                 if (set_rxd_buffer_pointer(sp, rxdp, ba, &skb,
7083                                                            (u64 *)&temp0_64,
7084                                                            (u64 *)&temp1_64,
7085                                                            (u64 *)&temp2_64,
7086                                                            size) == -ENOMEM) {
7087                                         return 0;
7088                                 }
7089
7090                                 set_rxd_buffer_size(sp, rxdp, size);
7091                                 wmb();
7092                                 /* flip the Ownership bit to Hardware */
7093                                 rxdp->Control_1 |= RXD_OWN_XENA;
7094                         }
7095                 }
7096         }
7097         return 0;
7098
7099 }
7100
7101 static int s2io_add_isr(struct s2io_nic *sp)
7102 {
7103         int ret = 0;
7104         struct net_device *dev = sp->dev;
7105         int err = 0;
7106
7107         if (sp->config.intr_type == MSI_X)
7108                 ret = s2io_enable_msi_x(sp);
7109         if (ret) {
7110                 DBG_PRINT(ERR_DBG, "%s: Defaulting to INTA\n", dev->name);
7111                 sp->config.intr_type = INTA;
7112         }
7113
7114         /*
7115          * Store the values of the MSIX table in
7116          * the struct s2io_nic structure
7117          */
7118         store_xmsi_data(sp);
7119
7120         /* After proper initialization of H/W, register ISR */
7121         if (sp->config.intr_type == MSI_X) {
7122                 int i, msix_rx_cnt = 0;
7123
7124                 for (i = 0; i < sp->num_entries; i++) {
7125                         if (sp->s2io_entries[i].in_use == MSIX_FLG) {
7126                                 if (sp->s2io_entries[i].type ==
7127                                     MSIX_RING_TYPE) {
7128                                         sprintf(sp->desc[i], "%s:MSI-X-%d-RX",
7129                                                 dev->name, i);
7130                                         err = request_irq(sp->entries[i].vector,
7131                                                           s2io_msix_ring_handle,
7132                                                           0,
7133                                                           sp->desc[i],
7134                                                           sp->s2io_entries[i].arg);
7135                                 } else if (sp->s2io_entries[i].type ==
7136                                            MSIX_ALARM_TYPE) {
7137                                         sprintf(sp->desc[i], "%s:MSI-X-%d-TX",
7138                                                 dev->name, i);
7139                                         err = request_irq(sp->entries[i].vector,
7140                                                           s2io_msix_fifo_handle,
7141                                                           0,
7142                                                           sp->desc[i],
7143                                                           sp->s2io_entries[i].arg);
7144
7145                                 }
7146                                 /* if either data or addr is zero print it. */
7147                                 if (!(sp->msix_info[i].addr &&
7148                                       sp->msix_info[i].data)) {
7149                                         DBG_PRINT(ERR_DBG,
7150                                                   "%s @Addr:0x%llx Data:0x%llx\n",
7151                                                   sp->desc[i],
7152                                                   (unsigned long long)
7153                                                   sp->msix_info[i].addr,
7154                                                   (unsigned long long)
7155                                                   ntohl(sp->msix_info[i].data));
7156                                 } else
7157                                         msix_rx_cnt++;
7158                                 if (err) {
7159                                         remove_msix_isr(sp);
7160
7161                                         DBG_PRINT(ERR_DBG,
7162                                                   "%s:MSI-X-%d registration "
7163                                                   "failed\n", dev->name, i);
7164
7165                                         DBG_PRINT(ERR_DBG,
7166                                                   "%s: Defaulting to INTA\n",
7167                                                   dev->name);
7168                                         sp->config.intr_type = INTA;
7169                                         break;
7170                                 }
7171                                 sp->s2io_entries[i].in_use =
7172                                         MSIX_REGISTERED_SUCCESS;
7173                         }
7174                 }
7175                 if (!err) {
7176                         pr_info("MSI-X-RX %d entries enabled\n", --msix_rx_cnt);
7177                         DBG_PRINT(INFO_DBG,
7178                                   "MSI-X-TX entries enabled through alarm vector\n");
7179                 }
7180         }
7181         if (sp->config.intr_type == INTA) {
7182                 err = request_irq((int)sp->pdev->irq, s2io_isr, IRQF_SHARED,
7183                                   sp->name, dev);
7184                 if (err) {
7185                         DBG_PRINT(ERR_DBG, "%s: ISR registration failed\n",
7186                                   dev->name);
7187                         return -1;
7188                 }
7189         }
7190         return 0;
7191 }
7192
7193 static void s2io_rem_isr(struct s2io_nic *sp)
7194 {
7195         if (sp->config.intr_type == MSI_X)
7196                 remove_msix_isr(sp);
7197         else
7198                 remove_inta_isr(sp);
7199 }
7200
7201 static void do_s2io_card_down(struct s2io_nic *sp, int do_io)
7202 {
7203         int cnt = 0;
7204         struct XENA_dev_config __iomem *bar0 = sp->bar0;
7205         register u64 val64 = 0;
7206         struct config_param *config;
7207         config = &sp->config;
7208
7209         if (!is_s2io_card_up(sp))
7210                 return;
7211
7212         del_timer_sync(&sp->alarm_timer);
7213         /* If s2io_set_link task is executing, wait till it completes. */
7214         while (test_and_set_bit(__S2IO_STATE_LINK_TASK, &(sp->state)))
7215                 msleep(50);
7216         clear_bit(__S2IO_STATE_CARD_UP, &sp->state);
7217
7218         /* Disable napi */
7219         if (sp->config.napi) {
7220                 int off = 0;
7221                 if (config->intr_type ==  MSI_X) {
7222                         for (; off < sp->config.rx_ring_num; off++)
7223                                 napi_disable(&sp->mac_control.rings[off].napi);
7224                 }
7225                 else
7226                         napi_disable(&sp->napi);
7227         }
7228
7229         /* disable Tx and Rx traffic on the NIC */
7230         if (do_io)
7231                 stop_nic(sp);
7232
7233         s2io_rem_isr(sp);
7234
7235         /* stop the tx queue, indicate link down */
7236         s2io_link(sp, LINK_DOWN);
7237
7238         /* Check if the device is Quiescent and then Reset the NIC */
7239         while (do_io) {
7240                 /* As per the HW requirement we need to replenish the
7241                  * receive buffer to avoid the ring bump. Since there is
7242                  * no intention of processing the Rx frame at this pointwe are
7243                  * just settting the ownership bit of rxd in Each Rx
7244                  * ring to HW and set the appropriate buffer size
7245                  * based on the ring mode
7246                  */
7247                 rxd_owner_bit_reset(sp);
7248
7249                 val64 = readq(&bar0->adapter_status);
7250                 if (verify_xena_quiescence(sp)) {
7251                         if (verify_pcc_quiescent(sp, sp->device_enabled_once))
7252                                 break;
7253                 }
7254
7255                 msleep(50);
7256                 cnt++;
7257                 if (cnt == 10) {
7258                         DBG_PRINT(ERR_DBG, "Device not Quiescent - "
7259                                   "adapter status reads 0x%llx\n",
7260                                   (unsigned long long)val64);
7261                         break;
7262                 }
7263         }
7264         if (do_io)
7265                 s2io_reset(sp);
7266
7267         /* Free all Tx buffers */
7268         free_tx_buffers(sp);
7269
7270         /* Free all Rx buffers */
7271         free_rx_buffers(sp);
7272
7273         clear_bit(__S2IO_STATE_LINK_TASK, &(sp->state));
7274 }
7275
7276 static void s2io_card_down(struct s2io_nic *sp)
7277 {
7278         do_s2io_card_down(sp, 1);
7279 }
7280
7281 static int s2io_card_up(struct s2io_nic *sp)
7282 {
7283         int i, ret = 0;
7284         struct config_param *config;
7285         struct mac_info *mac_control;
7286         struct net_device *dev = (struct net_device *)sp->dev;
7287         u16 interruptible;
7288
7289         /* Initialize the H/W I/O registers */
7290         ret = init_nic(sp);
7291         if (ret != 0) {
7292                 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
7293                           dev->name);
7294                 if (ret != -EIO)
7295                         s2io_reset(sp);
7296                 return ret;
7297         }
7298
7299         /*
7300          * Initializing the Rx buffers. For now we are considering only 1
7301          * Rx ring and initializing buffers into 30 Rx blocks
7302          */
7303         config = &sp->config;
7304         mac_control = &sp->mac_control;
7305
7306         for (i = 0; i < config->rx_ring_num; i++) {
7307                 struct ring_info *ring = &mac_control->rings[i];
7308
7309                 ring->mtu = dev->mtu;
7310                 ring->lro = sp->lro;
7311                 ret = fill_rx_buffers(sp, ring, 1);
7312                 if (ret) {
7313                         DBG_PRINT(ERR_DBG, "%s: Out of memory in Open\n",
7314                                   dev->name);
7315                         s2io_reset(sp);
7316                         free_rx_buffers(sp);
7317                         return -ENOMEM;
7318                 }
7319                 DBG_PRINT(INFO_DBG, "Buf in ring:%d is %d:\n", i,
7320                           ring->rx_bufs_left);
7321         }
7322
7323         /* Initialise napi */
7324         if (config->napi) {
7325                 if (config->intr_type ==  MSI_X) {
7326                         for (i = 0; i < sp->config.rx_ring_num; i++)
7327                                 napi_enable(&sp->mac_control.rings[i].napi);
7328                 } else {
7329                         napi_enable(&sp->napi);
7330                 }
7331         }
7332
7333         /* Maintain the state prior to the open */
7334         if (sp->promisc_flg)
7335                 sp->promisc_flg = 0;
7336         if (sp->m_cast_flg) {
7337                 sp->m_cast_flg = 0;
7338                 sp->all_multi_pos = 0;
7339         }
7340
7341         /* Setting its receive mode */
7342         s2io_set_multicast(dev);
7343
7344         if (sp->lro) {
7345                 /* Initialize max aggregatable pkts per session based on MTU */
7346                 sp->lro_max_aggr_per_sess = ((1<<16) - 1) / dev->mtu;
7347                 /* Check if we can use (if specified) user provided value */
7348                 if (lro_max_pkts < sp->lro_max_aggr_per_sess)
7349                         sp->lro_max_aggr_per_sess = lro_max_pkts;
7350         }
7351
7352         /* Enable Rx Traffic and interrupts on the NIC */
7353         if (start_nic(sp)) {
7354                 DBG_PRINT(ERR_DBG, "%s: Starting NIC failed\n", dev->name);
7355                 s2io_reset(sp);
7356                 free_rx_buffers(sp);
7357                 return -ENODEV;
7358         }
7359
7360         /* Add interrupt service routine */
7361         if (s2io_add_isr(sp) != 0) {
7362                 if (sp->config.intr_type == MSI_X)
7363                         s2io_rem_isr(sp);
7364                 s2io_reset(sp);
7365                 free_rx_buffers(sp);
7366                 return -ENODEV;
7367         }
7368
7369         S2IO_TIMER_CONF(sp->alarm_timer, s2io_alarm_handle, sp, (HZ/2));
7370
7371         set_bit(__S2IO_STATE_CARD_UP, &sp->state);
7372
7373         /*  Enable select interrupts */
7374         en_dis_err_alarms(sp, ENA_ALL_INTRS, ENABLE_INTRS);
7375         if (sp->config.intr_type != INTA) {
7376                 interruptible = TX_TRAFFIC_INTR | TX_PIC_INTR;
7377                 en_dis_able_nic_intrs(sp, interruptible, ENABLE_INTRS);
7378         } else {
7379                 interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
7380                 interruptible |= TX_PIC_INTR;
7381                 en_dis_able_nic_intrs(sp, interruptible, ENABLE_INTRS);
7382         }
7383
7384         return 0;
7385 }
7386
7387 /**
7388  * s2io_restart_nic - Resets the NIC.
7389  * @data : long pointer to the device private structure
7390  * Description:
7391  * This function is scheduled to be run by the s2io_tx_watchdog
7392  * function after 0.5 secs to reset the NIC. The idea is to reduce
7393  * the run time of the watch dog routine which is run holding a
7394  * spin lock.
7395  */
7396
7397 static void s2io_restart_nic(struct work_struct *work)
7398 {
7399         struct s2io_nic *sp = container_of(work, struct s2io_nic, rst_timer_task);
7400         struct net_device *dev = sp->dev;
7401
7402         rtnl_lock();
7403
7404         if (!netif_running(dev))
7405                 goto out_unlock;
7406
7407         s2io_card_down(sp);
7408         if (s2io_card_up(sp)) {
7409                 DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n", dev->name);
7410         }
7411         s2io_wake_all_tx_queue(sp);
7412         DBG_PRINT(ERR_DBG, "%s: was reset by Tx watchdog timer\n", dev->name);
7413 out_unlock:
7414         rtnl_unlock();
7415 }
7416
7417 /**
7418  *  s2io_tx_watchdog - Watchdog for transmit side.
7419  *  @dev : Pointer to net device structure
7420  *  Description:
7421  *  This function is triggered if the Tx Queue is stopped
7422  *  for a pre-defined amount of time when the Interface is still up.
7423  *  If the Interface is jammed in such a situation, the hardware is
7424  *  reset (by s2io_close) and restarted again (by s2io_open) to
7425  *  overcome any problem that might have been caused in the hardware.
7426  *  Return value:
7427  *  void
7428  */
7429
7430 static void s2io_tx_watchdog(struct net_device *dev)
7431 {
7432         struct s2io_nic *sp = netdev_priv(dev);
7433         struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
7434
7435         if (netif_carrier_ok(dev)) {
7436                 swstats->watchdog_timer_cnt++;
7437                 schedule_work(&sp->rst_timer_task);
7438                 swstats->soft_reset_cnt++;
7439         }
7440 }
7441
7442 /**
7443  *   rx_osm_handler - To perform some OS related operations on SKB.
7444  *   @sp: private member of the device structure,pointer to s2io_nic structure.
7445  *   @skb : the socket buffer pointer.
7446  *   @len : length of the packet
7447  *   @cksum : FCS checksum of the frame.
7448  *   @ring_no : the ring from which this RxD was extracted.
7449  *   Description:
7450  *   This function is called by the Rx interrupt serivce routine to perform
7451  *   some OS related operations on the SKB before passing it to the upper
7452  *   layers. It mainly checks if the checksum is OK, if so adds it to the
7453  *   SKBs cksum variable, increments the Rx packet count and passes the SKB
7454  *   to the upper layer. If the checksum is wrong, it increments the Rx
7455  *   packet error count, frees the SKB and returns error.
7456  *   Return value:
7457  *   SUCCESS on success and -1 on failure.
7458  */
7459 static int rx_osm_handler(struct ring_info *ring_data, struct RxD_t * rxdp)
7460 {
7461         struct s2io_nic *sp = ring_data->nic;
7462         struct net_device *dev = (struct net_device *)ring_data->dev;
7463         struct sk_buff *skb = (struct sk_buff *)
7464                 ((unsigned long)rxdp->Host_Control);
7465         int ring_no = ring_data->ring_no;
7466         u16 l3_csum, l4_csum;
7467         unsigned long long err = rxdp->Control_1 & RXD_T_CODE;
7468         struct lro *uninitialized_var(lro);
7469         u8 err_mask;
7470         struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
7471
7472         skb->dev = dev;
7473
7474         if (err) {
7475                 /* Check for parity error */
7476                 if (err & 0x1)
7477                         swstats->parity_err_cnt++;
7478
7479                 err_mask = err >> 48;
7480                 switch (err_mask) {
7481                 case 1:
7482                         swstats->rx_parity_err_cnt++;
7483                         break;
7484
7485                 case 2:
7486                         swstats->rx_abort_cnt++;
7487                         break;
7488
7489                 case 3:
7490                         swstats->rx_parity_abort_cnt++;
7491                         break;
7492
7493                 case 4:
7494                         swstats->rx_rda_fail_cnt++;
7495                         break;
7496
7497                 case 5:
7498                         swstats->rx_unkn_prot_cnt++;
7499                         break;
7500
7501                 case 6:
7502                         swstats->rx_fcs_err_cnt++;
7503                         break;
7504
7505                 case 7:
7506                         swstats->rx_buf_size_err_cnt++;
7507                         break;
7508
7509                 case 8:
7510                         swstats->rx_rxd_corrupt_cnt++;
7511                         break;
7512
7513                 case 15:
7514                         swstats->rx_unkn_err_cnt++;
7515                         break;
7516                 }
7517                 /*
7518                  * Drop the packet if bad transfer code. Exception being
7519                  * 0x5, which could be due to unsupported IPv6 extension header.
7520                  * In this case, we let stack handle the packet.
7521                  * Note that in this case, since checksum will be incorrect,
7522                  * stack will validate the same.
7523                  */
7524                 if (err_mask != 0x5) {
7525                         DBG_PRINT(ERR_DBG, "%s: Rx error Value: 0x%x\n",
7526                                   dev->name, err_mask);
7527                         dev->stats.rx_crc_errors++;
7528                         swstats->mem_freed
7529                                 += skb->truesize;
7530                         dev_kfree_skb(skb);
7531                         ring_data->rx_bufs_left -= 1;
7532                         rxdp->Host_Control = 0;
7533                         return 0;
7534                 }
7535         }
7536
7537         rxdp->Host_Control = 0;
7538         if (sp->rxd_mode == RXD_MODE_1) {
7539                 int len = RXD_GET_BUFFER0_SIZE_1(rxdp->Control_2);
7540
7541                 skb_put(skb, len);
7542         } else if (sp->rxd_mode == RXD_MODE_3B) {
7543                 int get_block = ring_data->rx_curr_get_info.block_index;
7544                 int get_off = ring_data->rx_curr_get_info.offset;
7545                 int buf0_len = RXD_GET_BUFFER0_SIZE_3(rxdp->Control_2);
7546                 int buf2_len = RXD_GET_BUFFER2_SIZE_3(rxdp->Control_2);
7547                 unsigned char *buff = skb_push(skb, buf0_len);
7548
7549                 struct buffAdd *ba = &ring_data->ba[get_block][get_off];
7550                 memcpy(buff, ba->ba_0, buf0_len);
7551                 skb_put(skb, buf2_len);
7552         }
7553
7554         if ((rxdp->Control_1 & TCP_OR_UDP_FRAME) &&
7555             ((!ring_data->lro) ||
7556              (ring_data->lro && (!(rxdp->Control_1 & RXD_FRAME_IP_FRAG)))) &&
7557             (sp->rx_csum)) {
7558                 l3_csum = RXD_GET_L3_CKSUM(rxdp->Control_1);
7559                 l4_csum = RXD_GET_L4_CKSUM(rxdp->Control_1);
7560                 if ((l3_csum == L3_CKSUM_OK) && (l4_csum == L4_CKSUM_OK)) {
7561                         /*
7562                          * NIC verifies if the Checksum of the received
7563                          * frame is Ok or not and accordingly returns
7564                          * a flag in the RxD.
7565                          */
7566                         skb->ip_summed = CHECKSUM_UNNECESSARY;
7567                         if (ring_data->lro) {
7568                                 u32 tcp_len;
7569                                 u8 *tcp;
7570                                 int ret = 0;
7571
7572                                 ret = s2io_club_tcp_session(ring_data,
7573                                                             skb->data, &tcp,
7574                                                             &tcp_len, &lro,
7575                                                             rxdp, sp);
7576                                 switch (ret) {
7577                                 case 3: /* Begin anew */
7578                                         lro->parent = skb;
7579                                         goto aggregate;
7580                                 case 1: /* Aggregate */
7581                                         lro_append_pkt(sp, lro, skb, tcp_len);
7582                                         goto aggregate;
7583                                 case 4: /* Flush session */
7584                                         lro_append_pkt(sp, lro, skb, tcp_len);
7585                                         queue_rx_frame(lro->parent,
7586                                                        lro->vlan_tag);
7587                                         clear_lro_session(lro);
7588                                         swstats->flush_max_pkts++;
7589                                         goto aggregate;
7590                                 case 2: /* Flush both */
7591                                         lro->parent->data_len = lro->frags_len;
7592                                         swstats->sending_both++;
7593                                         queue_rx_frame(lro->parent,
7594                                                        lro->vlan_tag);
7595                                         clear_lro_session(lro);
7596                                         goto send_up;
7597                                 case 0: /* sessions exceeded */
7598                                 case -1: /* non-TCP or not L2 aggregatable */
7599                                 case 5: /*
7600                                          * First pkt in session not
7601                                          * L3/L4 aggregatable
7602                                          */
7603                                         break;
7604                                 default:
7605                                         DBG_PRINT(ERR_DBG,
7606                                                   "%s: Samadhana!!\n",
7607                                                   __func__);
7608                                         BUG();
7609                                 }
7610                         }
7611                 } else {
7612                         /*
7613                          * Packet with erroneous checksum, let the
7614                          * upper layers deal with it.
7615                          */
7616                         skb->ip_summed = CHECKSUM_NONE;
7617                 }
7618         } else
7619                 skb->ip_summed = CHECKSUM_NONE;
7620
7621         swstats->mem_freed += skb->truesize;
7622 send_up:
7623         skb_record_rx_queue(skb, ring_no);
7624         queue_rx_frame(skb, RXD_GET_VLAN_TAG(rxdp->Control_2));
7625 aggregate:
7626         sp->mac_control.rings[ring_no].rx_bufs_left -= 1;
7627         return SUCCESS;
7628 }
7629
7630 /**
7631  *  s2io_link - stops/starts the Tx queue.
7632  *  @sp : private member of the device structure, which is a pointer to the
7633  *  s2io_nic structure.
7634  *  @link : inidicates whether link is UP/DOWN.
7635  *  Description:
7636  *  This function stops/starts the Tx queue depending on whether the link
7637  *  status of the NIC is is down or up. This is called by the Alarm
7638  *  interrupt handler whenever a link change interrupt comes up.
7639  *  Return value:
7640  *  void.
7641  */
7642
7643 static void s2io_link(struct s2io_nic *sp, int link)
7644 {
7645         struct net_device *dev = (struct net_device *)sp->dev;
7646         struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
7647
7648         if (link != sp->last_link_state) {
7649                 init_tti(sp, link);
7650                 if (link == LINK_DOWN) {
7651                         DBG_PRINT(ERR_DBG, "%s: Link down\n", dev->name);
7652                         s2io_stop_all_tx_queue(sp);
7653                         netif_carrier_off(dev);
7654                         if (swstats->link_up_cnt)
7655                                 swstats->link_up_time =
7656                                         jiffies - sp->start_time;
7657                         swstats->link_down_cnt++;
7658                 } else {
7659                         DBG_PRINT(ERR_DBG, "%s: Link Up\n", dev->name);
7660                         if (swstats->link_down_cnt)
7661                                 swstats->link_down_time =
7662                                         jiffies - sp->start_time;
7663                         swstats->link_up_cnt++;
7664                         netif_carrier_on(dev);
7665                         s2io_wake_all_tx_queue(sp);
7666                 }
7667         }
7668         sp->last_link_state = link;
7669         sp->start_time = jiffies;
7670 }
7671
7672 /**
7673  *  s2io_init_pci -Initialization of PCI and PCI-X configuration registers .
7674  *  @sp : private member of the device structure, which is a pointer to the
7675  *  s2io_nic structure.
7676  *  Description:
7677  *  This function initializes a few of the PCI and PCI-X configuration registers
7678  *  with recommended values.
7679  *  Return value:
7680  *  void
7681  */
7682
7683 static void s2io_init_pci(struct s2io_nic *sp)
7684 {
7685         u16 pci_cmd = 0, pcix_cmd = 0;
7686
7687         /* Enable Data Parity Error Recovery in PCI-X command register. */
7688         pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
7689                              &(pcix_cmd));
7690         pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
7691                               (pcix_cmd | 1));
7692         pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
7693                              &(pcix_cmd));
7694
7695         /* Set the PErr Response bit in PCI command register. */
7696         pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
7697         pci_write_config_word(sp->pdev, PCI_COMMAND,
7698                               (pci_cmd | PCI_COMMAND_PARITY));
7699         pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
7700 }
7701
7702 static int s2io_verify_parm(struct pci_dev *pdev, u8 *dev_intr_type,
7703                             u8 *dev_multiq)
7704 {
7705         if ((tx_fifo_num > MAX_TX_FIFOS) || (tx_fifo_num < 1)) {
7706                 DBG_PRINT(ERR_DBG, "Requested number of tx fifos "
7707                           "(%d) not supported\n", tx_fifo_num);
7708
7709                 if (tx_fifo_num < 1)
7710                         tx_fifo_num = 1;
7711                 else
7712                         tx_fifo_num = MAX_TX_FIFOS;
7713
7714                 DBG_PRINT(ERR_DBG, "Default to %d tx fifos\n", tx_fifo_num);
7715         }
7716
7717         if (multiq)
7718                 *dev_multiq = multiq;
7719
7720         if (tx_steering_type && (1 == tx_fifo_num)) {
7721                 if (tx_steering_type != TX_DEFAULT_STEERING)
7722                         DBG_PRINT(ERR_DBG,
7723                                   "Tx steering is not supported with "
7724                                   "one fifo. Disabling Tx steering.\n");
7725                 tx_steering_type = NO_STEERING;
7726         }
7727
7728         if ((tx_steering_type < NO_STEERING) ||
7729             (tx_steering_type > TX_DEFAULT_STEERING)) {
7730                 DBG_PRINT(ERR_DBG,
7731                           "Requested transmit steering not supported\n");
7732                 DBG_PRINT(ERR_DBG, "Disabling transmit steering\n");
7733                 tx_steering_type = NO_STEERING;
7734         }
7735
7736         if (rx_ring_num > MAX_RX_RINGS) {
7737                 DBG_PRINT(ERR_DBG,
7738                           "Requested number of rx rings not supported\n");
7739                 DBG_PRINT(ERR_DBG, "Default to %d rx rings\n",
7740                           MAX_RX_RINGS);
7741                 rx_ring_num = MAX_RX_RINGS;
7742         }
7743
7744         if ((*dev_intr_type != INTA) && (*dev_intr_type != MSI_X)) {
7745                 DBG_PRINT(ERR_DBG, "Wrong intr_type requested. "
7746                           "Defaulting to INTA\n");
7747                 *dev_intr_type = INTA;
7748         }
7749
7750         if ((*dev_intr_type == MSI_X) &&
7751             ((pdev->device != PCI_DEVICE_ID_HERC_WIN) &&
7752              (pdev->device != PCI_DEVICE_ID_HERC_UNI))) {
7753                 DBG_PRINT(ERR_DBG, "Xframe I does not support MSI_X. "
7754                           "Defaulting to INTA\n");
7755                 *dev_intr_type = INTA;
7756         }
7757
7758         if ((rx_ring_mode != 1) && (rx_ring_mode != 2)) {
7759                 DBG_PRINT(ERR_DBG, "Requested ring mode not supported\n");
7760                 DBG_PRINT(ERR_DBG, "Defaulting to 1-buffer mode\n");
7761                 rx_ring_mode = 1;
7762         }
7763         return SUCCESS;
7764 }
7765
7766 /**
7767  * rts_ds_steer - Receive traffic steering based on IPv4 or IPv6 TOS
7768  * or Traffic class respectively.
7769  * @nic: device private variable
7770  * Description: The function configures the receive steering to
7771  * desired receive ring.
7772  * Return Value:  SUCCESS on success and
7773  * '-1' on failure (endian settings incorrect).
7774  */
7775 static int rts_ds_steer(struct s2io_nic *nic, u8 ds_codepoint, u8 ring)
7776 {
7777         struct XENA_dev_config __iomem *bar0 = nic->bar0;
7778         register u64 val64 = 0;
7779
7780         if (ds_codepoint > 63)
7781                 return FAILURE;
7782
7783         val64 = RTS_DS_MEM_DATA(ring);
7784         writeq(val64, &bar0->rts_ds_mem_data);
7785
7786         val64 = RTS_DS_MEM_CTRL_WE |
7787                 RTS_DS_MEM_CTRL_STROBE_NEW_CMD |
7788                 RTS_DS_MEM_CTRL_OFFSET(ds_codepoint);
7789
7790         writeq(val64, &bar0->rts_ds_mem_ctrl);
7791
7792         return wait_for_cmd_complete(&bar0->rts_ds_mem_ctrl,
7793                                      RTS_DS_MEM_CTRL_STROBE_CMD_BEING_EXECUTED,
7794                                      S2IO_BIT_RESET);
7795 }
7796
7797 static const struct net_device_ops s2io_netdev_ops = {
7798         .ndo_open               = s2io_open,
7799         .ndo_stop               = s2io_close,
7800         .ndo_get_stats          = s2io_get_stats,
7801         .ndo_start_xmit         = s2io_xmit,
7802         .ndo_validate_addr      = eth_validate_addr,
7803         .ndo_set_multicast_list = s2io_set_multicast,
7804         .ndo_do_ioctl           = s2io_ioctl,
7805         .ndo_set_mac_address    = s2io_set_mac_addr,
7806         .ndo_change_mtu         = s2io_change_mtu,
7807         .ndo_vlan_rx_register   = s2io_vlan_rx_register,
7808         .ndo_vlan_rx_kill_vid   = s2io_vlan_rx_kill_vid,
7809         .ndo_tx_timeout         = s2io_tx_watchdog,
7810 #ifdef CONFIG_NET_POLL_CONTROLLER
7811         .ndo_poll_controller    = s2io_netpoll,
7812 #endif
7813 };
7814
7815 /**
7816  *  s2io_init_nic - Initialization of the adapter .
7817  *  @pdev : structure containing the PCI related information of the device.
7818  *  @pre: List of PCI devices supported by the driver listed in s2io_tbl.
7819  *  Description:
7820  *  The function initializes an adapter identified by the pci_dec structure.
7821  *  All OS related initialization including memory and device structure and
7822  *  initlaization of the device private variable is done. Also the swapper
7823  *  control register is initialized to enable read and write into the I/O
7824  *  registers of the device.
7825  *  Return value:
7826  *  returns 0 on success and negative on failure.
7827  */
7828
7829 static int __devinit
7830 s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
7831 {
7832         struct s2io_nic *sp;
7833         struct net_device *dev;
7834         int i, j, ret;
7835         int dma_flag = false;
7836         u32 mac_up, mac_down;
7837         u64 val64 = 0, tmp64 = 0;
7838         struct XENA_dev_config __iomem *bar0 = NULL;
7839         u16 subid;
7840         struct config_param *config;
7841         struct mac_info *mac_control;
7842         int mode;
7843         u8 dev_intr_type = intr_type;
7844         u8 dev_multiq = 0;
7845
7846         ret = s2io_verify_parm(pdev, &dev_intr_type, &dev_multiq);
7847         if (ret)
7848                 return ret;
7849
7850         ret = pci_enable_device(pdev);
7851         if (ret) {
7852                 DBG_PRINT(ERR_DBG,
7853                           "%s: pci_enable_device failed\n", __func__);
7854                 return ret;
7855         }
7856
7857         if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
7858                 DBG_PRINT(INIT_DBG, "%s: Using 64bit DMA\n", __func__);
7859                 dma_flag = true;
7860                 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
7861                         DBG_PRINT(ERR_DBG,
7862                                   "Unable to obtain 64bit DMA "
7863                                   "for consistent allocations\n");
7864                         pci_disable_device(pdev);
7865                         return -ENOMEM;
7866                 }
7867         } else if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
7868                 DBG_PRINT(INIT_DBG, "%s: Using 32bit DMA\n", __func__);
7869         } else {
7870                 pci_disable_device(pdev);
7871                 return -ENOMEM;
7872         }
7873         ret = pci_request_regions(pdev, s2io_driver_name);
7874         if (ret) {
7875                 DBG_PRINT(ERR_DBG, "%s: Request Regions failed - %x\n",
7876                           __func__, ret);
7877                 pci_disable_device(pdev);
7878                 return -ENODEV;
7879         }
7880         if (dev_multiq)
7881                 dev = alloc_etherdev_mq(sizeof(struct s2io_nic), tx_fifo_num);
7882         else
7883                 dev = alloc_etherdev(sizeof(struct s2io_nic));
7884         if (dev == NULL) {
7885                 DBG_PRINT(ERR_DBG, "Device allocation failed\n");
7886                 pci_disable_device(pdev);
7887                 pci_release_regions(pdev);
7888                 return -ENODEV;
7889         }
7890
7891         pci_set_master(pdev);
7892         pci_set_drvdata(pdev, dev);
7893         SET_NETDEV_DEV(dev, &pdev->dev);
7894
7895         /*  Private member variable initialized to s2io NIC structure */
7896         sp = netdev_priv(dev);
7897         sp->dev = dev;
7898         sp->pdev = pdev;
7899         sp->high_dma_flag = dma_flag;
7900         sp->device_enabled_once = false;
7901         if (rx_ring_mode == 1)
7902                 sp->rxd_mode = RXD_MODE_1;
7903         if (rx_ring_mode == 2)
7904                 sp->rxd_mode = RXD_MODE_3B;
7905
7906         sp->config.intr_type = dev_intr_type;
7907
7908         if ((pdev->device == PCI_DEVICE_ID_HERC_WIN) ||
7909             (pdev->device == PCI_DEVICE_ID_HERC_UNI))
7910                 sp->device_type = XFRAME_II_DEVICE;
7911         else
7912                 sp->device_type = XFRAME_I_DEVICE;
7913
7914         sp->lro = lro_enable;
7915
7916         /* Initialize some PCI/PCI-X fields of the NIC. */
7917         s2io_init_pci(sp);
7918
7919         /*
7920          * Setting the device configuration parameters.
7921          * Most of these parameters can be specified by the user during
7922          * module insertion as they are module loadable parameters. If
7923          * these parameters are not not specified during load time, they
7924          * are initialized with default values.
7925          */
7926         config = &sp->config;
7927         mac_control = &sp->mac_control;
7928
7929         config->napi = napi;
7930         config->tx_steering_type = tx_steering_type;
7931
7932         /* Tx side parameters. */
7933         if (config->tx_steering_type == TX_PRIORITY_STEERING)
7934                 config->tx_fifo_num = MAX_TX_FIFOS;
7935         else
7936                 config->tx_fifo_num = tx_fifo_num;
7937
7938         /* Initialize the fifos used for tx steering */
7939         if (config->tx_fifo_num < 5) {
7940                 if (config->tx_fifo_num  == 1)
7941                         sp->total_tcp_fifos = 1;
7942                 else
7943                         sp->total_tcp_fifos = config->tx_fifo_num - 1;
7944                 sp->udp_fifo_idx = config->tx_fifo_num - 1;
7945                 sp->total_udp_fifos = 1;
7946                 sp->other_fifo_idx = sp->total_tcp_fifos - 1;
7947         } else {
7948                 sp->total_tcp_fifos = (tx_fifo_num - FIFO_UDP_MAX_NUM -
7949                                        FIFO_OTHER_MAX_NUM);
7950                 sp->udp_fifo_idx = sp->total_tcp_fifos;
7951                 sp->total_udp_fifos = FIFO_UDP_MAX_NUM;
7952                 sp->other_fifo_idx = sp->udp_fifo_idx + FIFO_UDP_MAX_NUM;
7953         }
7954
7955         config->multiq = dev_multiq;
7956         for (i = 0; i < config->tx_fifo_num; i++) {
7957                 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
7958
7959                 tx_cfg->fifo_len = tx_fifo_len[i];
7960                 tx_cfg->fifo_priority = i;
7961         }
7962
7963         /* mapping the QoS priority to the configured fifos */
7964         for (i = 0; i < MAX_TX_FIFOS; i++)
7965                 config->fifo_mapping[i] = fifo_map[config->tx_fifo_num - 1][i];
7966
7967         /* map the hashing selector table to the configured fifos */
7968         for (i = 0; i < config->tx_fifo_num; i++)
7969                 sp->fifo_selector[i] = fifo_selector[i];
7970
7971
7972         config->tx_intr_type = TXD_INT_TYPE_UTILZ;
7973         for (i = 0; i < config->tx_fifo_num; i++) {
7974                 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
7975
7976                 tx_cfg->f_no_snoop = (NO_SNOOP_TXD | NO_SNOOP_TXD_BUFFER);
7977                 if (tx_cfg->fifo_len < 65) {
7978                         config->tx_intr_type = TXD_INT_TYPE_PER_LIST;
7979                         break;
7980                 }
7981         }
7982         /* + 2 because one Txd for skb->data and one Txd for UFO */
7983         config->max_txds = MAX_SKB_FRAGS + 2;
7984
7985         /* Rx side parameters. */
7986         config->rx_ring_num = rx_ring_num;
7987         for (i = 0; i < config->rx_ring_num; i++) {
7988                 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
7989                 struct ring_info *ring = &mac_control->rings[i];
7990
7991                 rx_cfg->num_rxd = rx_ring_sz[i] * (rxd_count[sp->rxd_mode] + 1);
7992                 rx_cfg->ring_priority = i;
7993                 ring->rx_bufs_left = 0;
7994                 ring->rxd_mode = sp->rxd_mode;
7995                 ring->rxd_count = rxd_count[sp->rxd_mode];
7996                 ring->pdev = sp->pdev;
7997                 ring->dev = sp->dev;
7998         }
7999
8000         for (i = 0; i < rx_ring_num; i++) {
8001                 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
8002
8003                 rx_cfg->ring_org = RING_ORG_BUFF1;
8004                 rx_cfg->f_no_snoop = (NO_SNOOP_RXD | NO_SNOOP_RXD_BUFFER);
8005         }
8006
8007         /*  Setting Mac Control parameters */
8008         mac_control->rmac_pause_time = rmac_pause_time;
8009         mac_control->mc_pause_threshold_q0q3 = mc_pause_threshold_q0q3;
8010         mac_control->mc_pause_threshold_q4q7 = mc_pause_threshold_q4q7;
8011
8012
8013         /*  initialize the shared memory used by the NIC and the host */
8014         if (init_shared_mem(sp)) {
8015                 DBG_PRINT(ERR_DBG, "%s: Memory allocation failed\n", dev->name);
8016                 ret = -ENOMEM;
8017                 goto mem_alloc_failed;
8018         }
8019
8020         sp->bar0 = pci_ioremap_bar(pdev, 0);
8021         if (!sp->bar0) {
8022                 DBG_PRINT(ERR_DBG, "%s: Neterion: cannot remap io mem1\n",
8023                           dev->name);
8024                 ret = -ENOMEM;
8025                 goto bar0_remap_failed;
8026         }
8027
8028         sp->bar1 = pci_ioremap_bar(pdev, 2);
8029         if (!sp->bar1) {
8030                 DBG_PRINT(ERR_DBG, "%s: Neterion: cannot remap io mem2\n",
8031                           dev->name);
8032                 ret = -ENOMEM;
8033                 goto bar1_remap_failed;
8034         }
8035
8036         dev->irq = pdev->irq;
8037         dev->base_addr = (unsigned long)sp->bar0;
8038
8039         /* Initializing the BAR1 address as the start of the FIFO pointer. */
8040         for (j = 0; j < MAX_TX_FIFOS; j++) {
8041                 mac_control->tx_FIFO_start[j] =
8042                         (struct TxFIFO_element __iomem *)
8043                         (sp->bar1 + (j * 0x00020000));
8044         }
8045
8046         /*  Driver entry points */
8047         dev->netdev_ops = &s2io_netdev_ops;
8048         SET_ETHTOOL_OPS(dev, &netdev_ethtool_ops);
8049         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
8050         if (lro_enable)
8051                 dev->features |= NETIF_F_LRO;
8052         dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM;
8053         if (sp->high_dma_flag == true)
8054                 dev->features |= NETIF_F_HIGHDMA;
8055         dev->features |= NETIF_F_TSO;
8056         dev->features |= NETIF_F_TSO6;
8057         if ((sp->device_type & XFRAME_II_DEVICE) && (ufo))  {
8058                 dev->features |= NETIF_F_UFO;
8059                 dev->features |= NETIF_F_HW_CSUM;
8060         }
8061         dev->watchdog_timeo = WATCH_DOG_TIMEOUT;
8062         INIT_WORK(&sp->rst_timer_task, s2io_restart_nic);
8063         INIT_WORK(&sp->set_link_task, s2io_set_link);
8064
8065         pci_save_state(sp->pdev);
8066
8067         /* Setting swapper control on the NIC, for proper reset operation */
8068         if (s2io_set_swapper(sp)) {
8069                 DBG_PRINT(ERR_DBG, "%s: swapper settings are wrong\n",
8070                           dev->name);
8071                 ret = -EAGAIN;
8072                 goto set_swap_failed;
8073         }
8074
8075         /* Verify if the Herc works on the slot its placed into */
8076         if (sp->device_type & XFRAME_II_DEVICE) {
8077                 mode = s2io_verify_pci_mode(sp);
8078                 if (mode < 0) {
8079                         DBG_PRINT(ERR_DBG, "%s: Unsupported PCI bus mode\n",
8080                                   __func__);
8081                         ret = -EBADSLT;
8082                         goto set_swap_failed;
8083                 }
8084         }
8085
8086         if (sp->config.intr_type == MSI_X) {
8087                 sp->num_entries = config->rx_ring_num + 1;
8088                 ret = s2io_enable_msi_x(sp);
8089
8090                 if (!ret) {
8091                         ret = s2io_test_msi(sp);
8092                         /* rollback MSI-X, will re-enable during add_isr() */
8093                         remove_msix_isr(sp);
8094                 }
8095                 if (ret) {
8096
8097                         DBG_PRINT(ERR_DBG,
8098                                   "MSI-X requested but failed to enable\n");
8099                         sp->config.intr_type = INTA;
8100                 }
8101         }
8102
8103         if (config->intr_type ==  MSI_X) {
8104                 for (i = 0; i < config->rx_ring_num ; i++) {
8105                         struct ring_info *ring = &mac_control->rings[i];
8106
8107                         netif_napi_add(dev, &ring->napi, s2io_poll_msix, 64);
8108                 }
8109         } else {
8110                 netif_napi_add(dev, &sp->napi, s2io_poll_inta, 64);
8111         }
8112
8113         /* Not needed for Herc */
8114         if (sp->device_type & XFRAME_I_DEVICE) {
8115                 /*
8116                  * Fix for all "FFs" MAC address problems observed on
8117                  * Alpha platforms
8118                  */
8119                 fix_mac_address(sp);
8120                 s2io_reset(sp);
8121         }
8122
8123         /*
8124          * MAC address initialization.
8125          * For now only one mac address will be read and used.
8126          */
8127         bar0 = sp->bar0;
8128         val64 = RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
8129                 RMAC_ADDR_CMD_MEM_OFFSET(0 + S2IO_MAC_ADDR_START_OFFSET);
8130         writeq(val64, &bar0->rmac_addr_cmd_mem);
8131         wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
8132                               RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
8133                               S2IO_BIT_RESET);
8134         tmp64 = readq(&bar0->rmac_addr_data0_mem);
8135         mac_down = (u32)tmp64;
8136         mac_up = (u32) (tmp64 >> 32);
8137
8138         sp->def_mac_addr[0].mac_addr[3] = (u8) (mac_up);
8139         sp->def_mac_addr[0].mac_addr[2] = (u8) (mac_up >> 8);
8140         sp->def_mac_addr[0].mac_addr[1] = (u8) (mac_up >> 16);
8141         sp->def_mac_addr[0].mac_addr[0] = (u8) (mac_up >> 24);
8142         sp->def_mac_addr[0].mac_addr[5] = (u8) (mac_down >> 16);
8143         sp->def_mac_addr[0].mac_addr[4] = (u8) (mac_down >> 24);
8144
8145         /*  Set the factory defined MAC address initially   */
8146         dev->addr_len = ETH_ALEN;
8147         memcpy(dev->dev_addr, sp->def_mac_addr, ETH_ALEN);
8148         memcpy(dev->perm_addr, dev->dev_addr, ETH_ALEN);
8149
8150         /* initialize number of multicast & unicast MAC entries variables */
8151         if (sp->device_type == XFRAME_I_DEVICE) {
8152                 config->max_mc_addr = S2IO_XENA_MAX_MC_ADDRESSES;
8153                 config->max_mac_addr = S2IO_XENA_MAX_MAC_ADDRESSES;
8154                 config->mc_start_offset = S2IO_XENA_MC_ADDR_START_OFFSET;
8155         } else if (sp->device_type == XFRAME_II_DEVICE) {
8156                 config->max_mc_addr = S2IO_HERC_MAX_MC_ADDRESSES;
8157                 config->max_mac_addr = S2IO_HERC_MAX_MAC_ADDRESSES;
8158                 config->mc_start_offset = S2IO_HERC_MC_ADDR_START_OFFSET;
8159         }
8160
8161         /* store mac addresses from CAM to s2io_nic structure */
8162         do_s2io_store_unicast_mc(sp);
8163
8164         /* Configure MSIX vector for number of rings configured plus one */
8165         if ((sp->device_type == XFRAME_II_DEVICE) &&
8166             (config->intr_type == MSI_X))
8167                 sp->num_entries = config->rx_ring_num + 1;
8168
8169         /* Store the values of the MSIX table in the s2io_nic structure */
8170         store_xmsi_data(sp);
8171         /* reset Nic and bring it to known state */
8172         s2io_reset(sp);
8173
8174         /*
8175          * Initialize link state flags
8176          * and the card state parameter
8177          */
8178         sp->state = 0;
8179
8180         /* Initialize spinlocks */
8181         for (i = 0; i < sp->config.tx_fifo_num; i++) {
8182                 struct fifo_info *fifo = &mac_control->fifos[i];
8183
8184                 spin_lock_init(&fifo->tx_lock);
8185         }
8186
8187         /*
8188          * SXE-002: Configure link and activity LED to init state
8189          * on driver load.
8190          */
8191         subid = sp->pdev->subsystem_device;
8192         if ((subid & 0xFF) >= 0x07) {
8193                 val64 = readq(&bar0->gpio_control);
8194                 val64 |= 0x0000800000000000ULL;
8195                 writeq(val64, &bar0->gpio_control);
8196                 val64 = 0x0411040400000000ULL;
8197                 writeq(val64, (void __iomem *)bar0 + 0x2700);
8198                 val64 = readq(&bar0->gpio_control);
8199         }
8200
8201         sp->rx_csum = 1;        /* Rx chksum verify enabled by default */
8202
8203         if (register_netdev(dev)) {
8204                 DBG_PRINT(ERR_DBG, "Device registration failed\n");
8205                 ret = -ENODEV;
8206                 goto register_failed;
8207         }
8208         s2io_vpd_read(sp);
8209         DBG_PRINT(ERR_DBG, "Copyright(c) 2002-2010 Exar Corp.\n");
8210         DBG_PRINT(ERR_DBG, "%s: Neterion %s (rev %d)\n", dev->name,
8211                   sp->product_name, pdev->revision);
8212         DBG_PRINT(ERR_DBG, "%s: Driver version %s\n", dev->name,
8213                   s2io_driver_version);
8214         DBG_PRINT(ERR_DBG, "%s: MAC Address: %pM\n", dev->name, dev->dev_addr);
8215         DBG_PRINT(ERR_DBG, "Serial number: %s\n", sp->serial_num);
8216         if (sp->device_type & XFRAME_II_DEVICE) {
8217                 mode = s2io_print_pci_mode(sp);
8218                 if (mode < 0) {
8219                         ret = -EBADSLT;
8220                         unregister_netdev(dev);
8221                         goto set_swap_failed;
8222                 }
8223         }
8224         switch (sp->rxd_mode) {
8225         case RXD_MODE_1:
8226                 DBG_PRINT(ERR_DBG, "%s: 1-Buffer receive mode enabled\n",
8227                           dev->name);
8228                 break;
8229         case RXD_MODE_3B:
8230                 DBG_PRINT(ERR_DBG, "%s: 2-Buffer receive mode enabled\n",
8231                           dev->name);
8232                 break;
8233         }
8234
8235         switch (sp->config.napi) {
8236         case 0:
8237                 DBG_PRINT(ERR_DBG, "%s: NAPI disabled\n", dev->name);
8238                 break;
8239         case 1:
8240                 DBG_PRINT(ERR_DBG, "%s: NAPI enabled\n", dev->name);
8241                 break;
8242         }
8243
8244         DBG_PRINT(ERR_DBG, "%s: Using %d Tx fifo(s)\n", dev->name,
8245                   sp->config.tx_fifo_num);
8246
8247         DBG_PRINT(ERR_DBG, "%s: Using %d Rx ring(s)\n", dev->name,
8248                   sp->config.rx_ring_num);
8249
8250         switch (sp->config.intr_type) {
8251         case INTA:
8252                 DBG_PRINT(ERR_DBG, "%s: Interrupt type INTA\n", dev->name);
8253                 break;
8254         case MSI_X:
8255                 DBG_PRINT(ERR_DBG, "%s: Interrupt type MSI-X\n", dev->name);
8256                 break;
8257         }
8258         if (sp->config.multiq) {
8259                 for (i = 0; i < sp->config.tx_fifo_num; i++) {
8260                         struct fifo_info *fifo = &mac_control->fifos[i];
8261
8262                         fifo->multiq = config->multiq;
8263                 }
8264                 DBG_PRINT(ERR_DBG, "%s: Multiqueue support enabled\n",
8265                           dev->name);
8266         } else
8267                 DBG_PRINT(ERR_DBG, "%s: Multiqueue support disabled\n",
8268                           dev->name);
8269
8270         switch (sp->config.tx_steering_type) {
8271         case NO_STEERING:
8272                 DBG_PRINT(ERR_DBG, "%s: No steering enabled for transmit\n",
8273                           dev->name);
8274                 break;
8275         case TX_PRIORITY_STEERING:
8276                 DBG_PRINT(ERR_DBG,
8277                           "%s: Priority steering enabled for transmit\n",
8278                           dev->name);
8279                 break;
8280         case TX_DEFAULT_STEERING:
8281                 DBG_PRINT(ERR_DBG,
8282                           "%s: Default steering enabled for transmit\n",
8283                           dev->name);
8284         }
8285
8286         if (sp->lro)
8287                 DBG_PRINT(ERR_DBG, "%s: Large receive offload enabled\n",
8288                           dev->name);
8289         if (ufo)
8290                 DBG_PRINT(ERR_DBG,
8291                           "%s: UDP Fragmentation Offload(UFO) enabled\n",
8292                           dev->name);
8293         /* Initialize device name */
8294         sprintf(sp->name, "%s Neterion %s", dev->name, sp->product_name);
8295
8296         if (vlan_tag_strip)
8297                 sp->vlan_strip_flag = 1;
8298         else
8299                 sp->vlan_strip_flag = 0;
8300
8301         /*
8302          * Make Link state as off at this point, when the Link change
8303          * interrupt comes the state will be automatically changed to
8304          * the right state.
8305          */
8306         netif_carrier_off(dev);
8307
8308         return 0;
8309
8310 register_failed:
8311 set_swap_failed:
8312         iounmap(sp->bar1);
8313 bar1_remap_failed:
8314         iounmap(sp->bar0);
8315 bar0_remap_failed:
8316 mem_alloc_failed:
8317         free_shared_mem(sp);
8318         pci_disable_device(pdev);
8319         pci_release_regions(pdev);
8320         pci_set_drvdata(pdev, NULL);
8321         free_netdev(dev);
8322
8323         return ret;
8324 }
8325
8326 /**
8327  * s2io_rem_nic - Free the PCI device
8328  * @pdev: structure containing the PCI related information of the device.
8329  * Description: This function is called by the Pci subsystem to release a
8330  * PCI device and free up all resource held up by the device. This could
8331  * be in response to a Hot plug event or when the driver is to be removed
8332  * from memory.
8333  */
8334
8335 static void __devexit s2io_rem_nic(struct pci_dev *pdev)
8336 {
8337         struct net_device *dev =
8338                 (struct net_device *)pci_get_drvdata(pdev);
8339         struct s2io_nic *sp;
8340
8341         if (dev == NULL) {
8342                 DBG_PRINT(ERR_DBG, "Driver Data is NULL!!\n");
8343                 return;
8344         }
8345
8346         flush_scheduled_work();
8347
8348         sp = netdev_priv(dev);
8349         unregister_netdev(dev);
8350
8351         free_shared_mem(sp);
8352         iounmap(sp->bar0);
8353         iounmap(sp->bar1);
8354         pci_release_regions(pdev);
8355         pci_set_drvdata(pdev, NULL);
8356         free_netdev(dev);
8357         pci_disable_device(pdev);
8358 }
8359
8360 /**
8361  * s2io_starter - Entry point for the driver
8362  * Description: This function is the entry point for the driver. It verifies
8363  * the module loadable parameters and initializes PCI configuration space.
8364  */
8365
8366 static int __init s2io_starter(void)
8367 {
8368         return pci_register_driver(&s2io_driver);
8369 }
8370
8371 /**
8372  * s2io_closer - Cleanup routine for the driver
8373  * Description: This function is the cleanup routine for the driver. It unregist * ers the driver.
8374  */
8375
8376 static __exit void s2io_closer(void)
8377 {
8378         pci_unregister_driver(&s2io_driver);
8379         DBG_PRINT(INIT_DBG, "cleanup done\n");
8380 }
8381
8382 module_init(s2io_starter);
8383 module_exit(s2io_closer);
8384
8385 static int check_L2_lro_capable(u8 *buffer, struct iphdr **ip,
8386                                 struct tcphdr **tcp, struct RxD_t *rxdp,
8387                                 struct s2io_nic *sp)
8388 {
8389         int ip_off;
8390         u8 l2_type = (u8)((rxdp->Control_1 >> 37) & 0x7), ip_len;
8391
8392         if (!(rxdp->Control_1 & RXD_FRAME_PROTO_TCP)) {
8393                 DBG_PRINT(INIT_DBG,
8394                           "%s: Non-TCP frames not supported for LRO\n",
8395                           __func__);
8396                 return -1;
8397         }
8398
8399         /* Checking for DIX type or DIX type with VLAN */
8400         if ((l2_type == 0) || (l2_type == 4)) {
8401                 ip_off = HEADER_ETHERNET_II_802_3_SIZE;
8402                 /*
8403                  * If vlan stripping is disabled and the frame is VLAN tagged,
8404                  * shift the offset by the VLAN header size bytes.
8405                  */
8406                 if ((!sp->vlan_strip_flag) &&
8407                     (rxdp->Control_1 & RXD_FRAME_VLAN_TAG))
8408                         ip_off += HEADER_VLAN_SIZE;
8409         } else {
8410                 /* LLC, SNAP etc are considered non-mergeable */
8411                 return -1;
8412         }
8413
8414         *ip = (struct iphdr *)((u8 *)buffer + ip_off);
8415         ip_len = (u8)((*ip)->ihl);
8416         ip_len <<= 2;
8417         *tcp = (struct tcphdr *)((unsigned long)*ip + ip_len);
8418
8419         return 0;
8420 }
8421
8422 static int check_for_socket_match(struct lro *lro, struct iphdr *ip,
8423                                   struct tcphdr *tcp)
8424 {
8425         DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__);
8426         if ((lro->iph->saddr != ip->saddr) ||
8427             (lro->iph->daddr != ip->daddr) ||
8428             (lro->tcph->source != tcp->source) ||
8429             (lro->tcph->dest != tcp->dest))
8430                 return -1;
8431         return 0;
8432 }
8433
8434 static inline int get_l4_pyld_length(struct iphdr *ip, struct tcphdr *tcp)
8435 {
8436         return ntohs(ip->tot_len) - (ip->ihl << 2) - (tcp->doff << 2);
8437 }
8438
8439 static void initiate_new_session(struct lro *lro, u8 *l2h,
8440                                  struct iphdr *ip, struct tcphdr *tcp,
8441                                  u32 tcp_pyld_len, u16 vlan_tag)
8442 {
8443         DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__);
8444         lro->l2h = l2h;
8445         lro->iph = ip;
8446         lro->tcph = tcp;
8447         lro->tcp_next_seq = tcp_pyld_len + ntohl(tcp->seq);
8448         lro->tcp_ack = tcp->ack_seq;
8449         lro->sg_num = 1;
8450         lro->total_len = ntohs(ip->tot_len);
8451         lro->frags_len = 0;
8452         lro->vlan_tag = vlan_tag;
8453         /*
8454          * Check if we saw TCP timestamp.
8455          * Other consistency checks have already been done.
8456          */
8457         if (tcp->doff == 8) {
8458                 __be32 *ptr;
8459                 ptr = (__be32 *)(tcp+1);
8460                 lro->saw_ts = 1;
8461                 lro->cur_tsval = ntohl(*(ptr+1));
8462                 lro->cur_tsecr = *(ptr+2);
8463         }
8464         lro->in_use = 1;
8465 }
8466
8467 static void update_L3L4_header(struct s2io_nic *sp, struct lro *lro)
8468 {
8469         struct iphdr *ip = lro->iph;
8470         struct tcphdr *tcp = lro->tcph;
8471         __sum16 nchk;
8472         struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
8473
8474         DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__);
8475
8476         /* Update L3 header */
8477         ip->tot_len = htons(lro->total_len);
8478         ip->check = 0;
8479         nchk = ip_fast_csum((u8 *)lro->iph, ip->ihl);
8480         ip->check = nchk;
8481
8482         /* Update L4 header */
8483         tcp->ack_seq = lro->tcp_ack;
8484         tcp->window = lro->window;
8485
8486         /* Update tsecr field if this session has timestamps enabled */
8487         if (lro->saw_ts) {
8488                 __be32 *ptr = (__be32 *)(tcp + 1);
8489                 *(ptr+2) = lro->cur_tsecr;
8490         }
8491
8492         /* Update counters required for calculation of
8493          * average no. of packets aggregated.
8494          */
8495         swstats->sum_avg_pkts_aggregated += lro->sg_num;
8496         swstats->num_aggregations++;
8497 }
8498
8499 static void aggregate_new_rx(struct lro *lro, struct iphdr *ip,
8500                              struct tcphdr *tcp, u32 l4_pyld)
8501 {
8502         DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__);
8503         lro->total_len += l4_pyld;
8504         lro->frags_len += l4_pyld;
8505         lro->tcp_next_seq += l4_pyld;
8506         lro->sg_num++;
8507
8508         /* Update ack seq no. and window ad(from this pkt) in LRO object */
8509         lro->tcp_ack = tcp->ack_seq;
8510         lro->window = tcp->window;
8511
8512         if (lro->saw_ts) {
8513                 __be32 *ptr;
8514                 /* Update tsecr and tsval from this packet */
8515                 ptr = (__be32 *)(tcp+1);
8516                 lro->cur_tsval = ntohl(*(ptr+1));
8517                 lro->cur_tsecr = *(ptr + 2);
8518         }
8519 }
8520
8521 static int verify_l3_l4_lro_capable(struct lro *l_lro, struct iphdr *ip,
8522                                     struct tcphdr *tcp, u32 tcp_pyld_len)
8523 {
8524         u8 *ptr;
8525
8526         DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__);
8527
8528         if (!tcp_pyld_len) {
8529                 /* Runt frame or a pure ack */
8530                 return -1;
8531         }
8532
8533         if (ip->ihl != 5) /* IP has options */
8534                 return -1;
8535
8536         /* If we see CE codepoint in IP header, packet is not mergeable */
8537         if (INET_ECN_is_ce(ipv4_get_dsfield(ip)))
8538                 return -1;
8539
8540         /* If we see ECE or CWR flags in TCP header, packet is not mergeable */
8541         if (tcp->urg || tcp->psh || tcp->rst ||
8542             tcp->syn || tcp->fin ||
8543             tcp->ece || tcp->cwr || !tcp->ack) {
8544                 /*
8545                  * Currently recognize only the ack control word and
8546                  * any other control field being set would result in
8547                  * flushing the LRO session
8548                  */
8549                 return -1;
8550         }
8551
8552         /*
8553          * Allow only one TCP timestamp option. Don't aggregate if
8554          * any other options are detected.
8555          */
8556         if (tcp->doff != 5 && tcp->doff != 8)
8557                 return -1;
8558
8559         if (tcp->doff == 8) {
8560                 ptr = (u8 *)(tcp + 1);
8561                 while (*ptr == TCPOPT_NOP)
8562                         ptr++;
8563                 if (*ptr != TCPOPT_TIMESTAMP || *(ptr+1) != TCPOLEN_TIMESTAMP)
8564                         return -1;
8565
8566                 /* Ensure timestamp value increases monotonically */
8567                 if (l_lro)
8568                         if (l_lro->cur_tsval > ntohl(*((__be32 *)(ptr+2))))
8569                                 return -1;
8570
8571                 /* timestamp echo reply should be non-zero */
8572                 if (*((__be32 *)(ptr+6)) == 0)
8573                         return -1;
8574         }
8575
8576         return 0;
8577 }
8578
8579 static int s2io_club_tcp_session(struct ring_info *ring_data, u8 *buffer,
8580                                  u8 **tcp, u32 *tcp_len, struct lro **lro,
8581                                  struct RxD_t *rxdp, struct s2io_nic *sp)
8582 {
8583         struct iphdr *ip;
8584         struct tcphdr *tcph;
8585         int ret = 0, i;
8586         u16 vlan_tag = 0;
8587         struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
8588
8589         ret = check_L2_lro_capable(buffer, &ip, (struct tcphdr **)tcp,
8590                                    rxdp, sp);
8591         if (ret)
8592                 return ret;
8593
8594         DBG_PRINT(INFO_DBG, "IP Saddr: %x Daddr: %x\n", ip->saddr, ip->daddr);
8595
8596         vlan_tag = RXD_GET_VLAN_TAG(rxdp->Control_2);
8597         tcph = (struct tcphdr *)*tcp;
8598         *tcp_len = get_l4_pyld_length(ip, tcph);
8599         for (i = 0; i < MAX_LRO_SESSIONS; i++) {
8600                 struct lro *l_lro = &ring_data->lro0_n[i];
8601                 if (l_lro->in_use) {
8602                         if (check_for_socket_match(l_lro, ip, tcph))
8603                                 continue;
8604                         /* Sock pair matched */
8605                         *lro = l_lro;
8606
8607                         if ((*lro)->tcp_next_seq != ntohl(tcph->seq)) {
8608                                 DBG_PRINT(INFO_DBG, "%s: Out of sequence. "
8609                                           "expected 0x%x, actual 0x%x\n",
8610                                           __func__,
8611                                           (*lro)->tcp_next_seq,
8612                                           ntohl(tcph->seq));
8613
8614                                 swstats->outof_sequence_pkts++;
8615                                 ret = 2;
8616                                 break;
8617                         }
8618
8619                         if (!verify_l3_l4_lro_capable(l_lro, ip, tcph,
8620                                                       *tcp_len))
8621                                 ret = 1; /* Aggregate */
8622                         else
8623                                 ret = 2; /* Flush both */
8624                         break;
8625                 }
8626         }
8627
8628         if (ret == 0) {
8629                 /* Before searching for available LRO objects,
8630                  * check if the pkt is L3/L4 aggregatable. If not
8631                  * don't create new LRO session. Just send this
8632                  * packet up.
8633                  */
8634                 if (verify_l3_l4_lro_capable(NULL, ip, tcph, *tcp_len))
8635                         return 5;
8636
8637                 for (i = 0; i < MAX_LRO_SESSIONS; i++) {
8638                         struct lro *l_lro = &ring_data->lro0_n[i];
8639                         if (!(l_lro->in_use)) {
8640                                 *lro = l_lro;
8641                                 ret = 3; /* Begin anew */
8642                                 break;
8643                         }
8644                 }
8645         }
8646
8647         if (ret == 0) { /* sessions exceeded */
8648                 DBG_PRINT(INFO_DBG, "%s: All LRO sessions already in use\n",
8649                           __func__);
8650                 *lro = NULL;
8651                 return ret;
8652         }
8653
8654         switch (ret) {
8655         case 3:
8656                 initiate_new_session(*lro, buffer, ip, tcph, *tcp_len,
8657                                      vlan_tag);
8658                 break;
8659         case 2:
8660                 update_L3L4_header(sp, *lro);
8661                 break;
8662         case 1:
8663                 aggregate_new_rx(*lro, ip, tcph, *tcp_len);
8664                 if ((*lro)->sg_num == sp->lro_max_aggr_per_sess) {
8665                         update_L3L4_header(sp, *lro);
8666                         ret = 4; /* Flush the LRO */
8667                 }
8668                 break;
8669         default:
8670                 DBG_PRINT(ERR_DBG, "%s: Don't know, can't say!!\n", __func__);
8671                 break;
8672         }
8673
8674         return ret;
8675 }
8676
8677 static void clear_lro_session(struct lro *lro)
8678 {
8679         static u16 lro_struct_size = sizeof(struct lro);
8680
8681         memset(lro, 0, lro_struct_size);
8682 }
8683
8684 static void queue_rx_frame(struct sk_buff *skb, u16 vlan_tag)
8685 {
8686         struct net_device *dev = skb->dev;
8687         struct s2io_nic *sp = netdev_priv(dev);
8688
8689         skb->protocol = eth_type_trans(skb, dev);
8690         if (sp->vlgrp && vlan_tag && (sp->vlan_strip_flag)) {
8691                 /* Queueing the vlan frame to the upper layer */
8692                 if (sp->config.napi)
8693                         vlan_hwaccel_receive_skb(skb, sp->vlgrp, vlan_tag);
8694                 else
8695                         vlan_hwaccel_rx(skb, sp->vlgrp, vlan_tag);
8696         } else {
8697                 if (sp->config.napi)
8698                         netif_receive_skb(skb);
8699                 else
8700                         netif_rx(skb);
8701         }
8702 }
8703
8704 static void lro_append_pkt(struct s2io_nic *sp, struct lro *lro,
8705                            struct sk_buff *skb, u32 tcp_len)
8706 {
8707         struct sk_buff *first = lro->parent;
8708         struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
8709
8710         first->len += tcp_len;
8711         first->data_len = lro->frags_len;
8712         skb_pull(skb, (skb->len - tcp_len));
8713         if (skb_shinfo(first)->frag_list)
8714                 lro->last_frag->next = skb;
8715         else
8716                 skb_shinfo(first)->frag_list = skb;
8717         first->truesize += skb->truesize;
8718         lro->last_frag = skb;
8719         swstats->clubbed_frms_cnt++;
8720 }
8721
8722 /**
8723  * s2io_io_error_detected - called when PCI error is detected
8724  * @pdev: Pointer to PCI device
8725  * @state: The current pci connection state
8726  *
8727  * This function is called after a PCI bus error affecting
8728  * this device has been detected.
8729  */
8730 static pci_ers_result_t s2io_io_error_detected(struct pci_dev *pdev,
8731                                                pci_channel_state_t state)
8732 {
8733         struct net_device *netdev = pci_get_drvdata(pdev);
8734         struct s2io_nic *sp = netdev_priv(netdev);
8735
8736         netif_device_detach(netdev);
8737
8738         if (state == pci_channel_io_perm_failure)
8739                 return PCI_ERS_RESULT_DISCONNECT;
8740
8741         if (netif_running(netdev)) {
8742                 /* Bring down the card, while avoiding PCI I/O */
8743                 do_s2io_card_down(sp, 0);
8744         }
8745         pci_disable_device(pdev);
8746
8747         return PCI_ERS_RESULT_NEED_RESET;
8748 }
8749
8750 /**
8751  * s2io_io_slot_reset - called after the pci bus has been reset.
8752  * @pdev: Pointer to PCI device
8753  *
8754  * Restart the card from scratch, as if from a cold-boot.
8755  * At this point, the card has exprienced a hard reset,
8756  * followed by fixups by BIOS, and has its config space
8757  * set up identically to what it was at cold boot.
8758  */
8759 static pci_ers_result_t s2io_io_slot_reset(struct pci_dev *pdev)
8760 {
8761         struct net_device *netdev = pci_get_drvdata(pdev);
8762         struct s2io_nic *sp = netdev_priv(netdev);
8763
8764         if (pci_enable_device(pdev)) {
8765                 pr_err("Cannot re-enable PCI device after reset.\n");
8766                 return PCI_ERS_RESULT_DISCONNECT;
8767         }
8768
8769         pci_set_master(pdev);
8770         s2io_reset(sp);
8771
8772         return PCI_ERS_RESULT_RECOVERED;
8773 }
8774
8775 /**
8776  * s2io_io_resume - called when traffic can start flowing again.
8777  * @pdev: Pointer to PCI device
8778  *
8779  * This callback is called when the error recovery driver tells
8780  * us that its OK to resume normal operation.
8781  */
8782 static void s2io_io_resume(struct pci_dev *pdev)
8783 {
8784         struct net_device *netdev = pci_get_drvdata(pdev);
8785         struct s2io_nic *sp = netdev_priv(netdev);
8786
8787         if (netif_running(netdev)) {
8788                 if (s2io_card_up(sp)) {
8789                         pr_err("Can't bring device back up after reset.\n");
8790                         return;
8791                 }
8792
8793                 if (s2io_set_mac_addr(netdev, netdev->dev_addr) == FAILURE) {
8794                         s2io_card_down(sp);
8795                         pr_err("Can't restore mac addr after reset.\n");
8796                         return;
8797                 }
8798         }
8799
8800         netif_device_attach(netdev);
8801         netif_tx_wake_all_queues(netdev);
8802 }