1 /************************************************************************
2 * s2io.c: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC
3 * Copyright(c) 2002-2005 Neterion Inc.
5 * This software may be used and distributed according to the terms of
6 * the GNU General Public License (GPL), incorporated herein by reference.
7 * Drivers based on or derived from this code fall under the GPL and must
8 * retain the authorship, copyright and license notice. This file is not
9 * a complete program and may only be used when the entire operating
10 * system is licensed under the GPL.
11 * See the file COPYING in this distribution for more information.
14 * Jeff Garzik : For pointing out the improper error condition
15 * check in the s2io_xmit routine and also some
16 * issues in the Tx watch dog function. Also for
17 * patiently answering all those innumerable
18 * questions regaring the 2.6 porting issues.
19 * Stephen Hemminger : Providing proper 2.6 porting mechanism for some
20 * macros available only in 2.6 Kernel.
21 * Francois Romieu : For pointing out all code part that were
22 * deprecated and also styling related comments.
23 * Grant Grundler : For helping me get rid of some Architecture
25 * Christopher Hellwig : Some more 2.6 specific issues in the driver.
27 * The module loadable parameters that are supported by the driver and a brief
28 * explaination of all the variables.
30 * rx_ring_num : This can be used to program the number of receive rings used
32 * rx_ring_sz: This defines the number of receive blocks each ring can have.
33 * This is also an array of size 8.
34 * rx_ring_mode: This defines the operation mode of all 8 rings. The valid
35 * values are 1, 2 and 3.
36 * tx_fifo_num: This defines the number of Tx FIFOs thats used int the driver.
37 * tx_fifo_len: This too is an array of 8. Each element defines the number of
38 * Tx descriptors that can be associated with each corresponding FIFO.
39 * intr_type: This defines the type of interrupt. The values can be 0(INTA),
40 * 1(MSI), 2(MSI_X). Default value is '0(INTA)'
41 * lro: Specifies whether to enable Large Receive Offload (LRO) or not.
42 * Possible values '1' for enable '0' for disable. Default is '0'
43 * lro_max_pkts: This parameter defines maximum number of packets can be
44 * aggregated as a single large packet
45 ************************************************************************/
47 #include <linux/module.h>
48 #include <linux/types.h>
49 #include <linux/errno.h>
50 #include <linux/ioport.h>
51 #include <linux/pci.h>
52 #include <linux/dma-mapping.h>
53 #include <linux/kernel.h>
54 #include <linux/netdevice.h>
55 #include <linux/etherdevice.h>
56 #include <linux/skbuff.h>
57 #include <linux/init.h>
58 #include <linux/delay.h>
59 #include <linux/stddef.h>
60 #include <linux/ioctl.h>
61 #include <linux/timex.h>
62 #include <linux/sched.h>
63 #include <linux/ethtool.h>
64 #include <linux/workqueue.h>
65 #include <linux/if_vlan.h>
67 #include <linux/tcp.h>
70 #include <asm/system.h>
71 #include <asm/uaccess.h>
73 #include <asm/div64.h>
78 #include "s2io-regs.h"
80 #define DRV_VERSION "2.0.15.2"
82 /* S2io Driver name & version. */
83 static char s2io_driver_name[] = "Neterion";
84 static char s2io_driver_version[] = DRV_VERSION;
86 static int rxd_size[4] = {32,48,48,64};
87 static int rxd_count[4] = {127,85,85,63};
89 static inline int RXD_IS_UP2DT(RxD_t *rxdp)
93 ret = ((!(rxdp->Control_1 & RXD_OWN_XENA)) &&
94 (GET_RXD_MARKER(rxdp->Control_2) != THE_RXD_MARK));
100 * Cards with following subsystem_id have a link state indication
101 * problem, 600B, 600C, 600D, 640B, 640C and 640D.
102 * macro below identifies these cards given the subsystem_id.
104 #define CARDS_WITH_FAULTY_LINK_INDICATORS(dev_type, subid) \
105 (dev_type == XFRAME_I_DEVICE) ? \
106 ((((subid >= 0x600B) && (subid <= 0x600D)) || \
107 ((subid >= 0x640B) && (subid <= 0x640D))) ? 1 : 0) : 0
109 #define LINK_IS_UP(val64) (!(val64 & (ADAPTER_STATUS_RMAC_REMOTE_FAULT | \
110 ADAPTER_STATUS_RMAC_LOCAL_FAULT)))
111 #define TASKLET_IN_USE test_and_set_bit(0, (&sp->tasklet_status))
114 static inline int rx_buffer_level(nic_t * sp, int rxb_size, int ring)
116 mac_info_t *mac_control;
118 mac_control = &sp->mac_control;
119 if (rxb_size <= rxd_count[sp->rxd_mode])
121 else if ((mac_control->rings[ring].pkt_cnt - rxb_size) > 16)
126 /* Ethtool related variables and Macros. */
127 static char s2io_gstrings[][ETH_GSTRING_LEN] = {
128 "Register test\t(offline)",
129 "Eeprom test\t(offline)",
130 "Link test\t(online)",
131 "RLDRAM test\t(offline)",
132 "BIST Test\t(offline)"
135 static char ethtool_stats_keys[][ETH_GSTRING_LEN] = {
137 {"tmac_data_octets"},
141 {"tmac_pause_ctrl_frms"},
145 {"tmac_any_err_frms"},
146 {"tmac_ttl_less_fb_octets"},
147 {"tmac_vld_ip_octets"},
155 {"rmac_data_octets"},
156 {"rmac_fcs_err_frms"},
158 {"rmac_vld_mcst_frms"},
159 {"rmac_vld_bcst_frms"},
160 {"rmac_in_rng_len_err_frms"},
161 {"rmac_out_rng_len_err_frms"},
163 {"rmac_pause_ctrl_frms"},
164 {"rmac_unsup_ctrl_frms"},
166 {"rmac_accepted_ucst_frms"},
167 {"rmac_accepted_nucst_frms"},
168 {"rmac_discarded_frms"},
169 {"rmac_drop_events"},
170 {"rmac_ttl_less_fb_octets"},
172 {"rmac_usized_frms"},
173 {"rmac_osized_frms"},
175 {"rmac_jabber_frms"},
176 {"rmac_ttl_64_frms"},
177 {"rmac_ttl_65_127_frms"},
178 {"rmac_ttl_128_255_frms"},
179 {"rmac_ttl_256_511_frms"},
180 {"rmac_ttl_512_1023_frms"},
181 {"rmac_ttl_1024_1518_frms"},
189 {"rmac_err_drp_udp"},
190 {"rmac_xgmii_err_sym"},
208 {"rmac_xgmii_data_err_cnt"},
209 {"rmac_xgmii_ctrl_err_cnt"},
210 {"rmac_accepted_ip"},
214 {"new_rd_req_rtry_cnt"},
216 {"wr_rtry_rd_ack_cnt"},
219 {"new_wr_req_rtry_cnt"},
222 {"rd_rtry_wr_ack_cnt"},
230 {"rmac_ttl_1519_4095_frms"},
231 {"rmac_ttl_4096_8191_frms"},
232 {"rmac_ttl_8192_max_frms"},
233 {"rmac_ttl_gt_max_frms"},
234 {"rmac_osized_alt_frms"},
235 {"rmac_jabber_alt_frms"},
236 {"rmac_gt_max_alt_frms"},
238 {"rmac_len_discard"},
239 {"rmac_fcs_discard"},
242 {"rmac_red_discard"},
243 {"rmac_rts_discard"},
244 {"rmac_ingm_full_discard"},
246 {"\n DRIVER STATISTICS"},
247 {"single_bit_ecc_errs"},
248 {"double_bit_ecc_errs"},
254 ("alarm_transceiver_temp_high"),
255 ("alarm_transceiver_temp_low"),
256 ("alarm_laser_bias_current_high"),
257 ("alarm_laser_bias_current_low"),
258 ("alarm_laser_output_power_high"),
259 ("alarm_laser_output_power_low"),
260 ("warn_transceiver_temp_high"),
261 ("warn_transceiver_temp_low"),
262 ("warn_laser_bias_current_high"),
263 ("warn_laser_bias_current_low"),
264 ("warn_laser_output_power_high"),
265 ("warn_laser_output_power_low"),
266 ("lro_aggregated_pkts"),
267 ("lro_flush_both_count"),
268 ("lro_out_of_sequence_pkts"),
269 ("lro_flush_due_to_max_pkts"),
270 ("lro_avg_aggr_pkts"),
273 #define S2IO_STAT_LEN sizeof(ethtool_stats_keys)/ ETH_GSTRING_LEN
274 #define S2IO_STAT_STRINGS_LEN S2IO_STAT_LEN * ETH_GSTRING_LEN
276 #define S2IO_TEST_LEN sizeof(s2io_gstrings) / ETH_GSTRING_LEN
277 #define S2IO_STRINGS_LEN S2IO_TEST_LEN * ETH_GSTRING_LEN
279 #define S2IO_TIMER_CONF(timer, handle, arg, exp) \
280 init_timer(&timer); \
281 timer.function = handle; \
282 timer.data = (unsigned long) arg; \
283 mod_timer(&timer, (jiffies + exp)) \
286 static void s2io_vlan_rx_register(struct net_device *dev,
287 struct vlan_group *grp)
289 nic_t *nic = dev->priv;
292 spin_lock_irqsave(&nic->tx_lock, flags);
294 spin_unlock_irqrestore(&nic->tx_lock, flags);
297 /* Unregister the vlan */
298 static void s2io_vlan_rx_kill_vid(struct net_device *dev, unsigned long vid)
300 nic_t *nic = dev->priv;
303 spin_lock_irqsave(&nic->tx_lock, flags);
305 nic->vlgrp->vlan_devices[vid] = NULL;
306 spin_unlock_irqrestore(&nic->tx_lock, flags);
310 * Constants to be programmed into the Xena's registers, to configure
315 static const u64 herc_act_dtx_cfg[] = {
317 0x8000051536750000ULL, 0x80000515367500E0ULL,
319 0x8000051536750004ULL, 0x80000515367500E4ULL,
321 0x80010515003F0000ULL, 0x80010515003F00E0ULL,
323 0x80010515003F0004ULL, 0x80010515003F00E4ULL,
325 0x801205150D440000ULL, 0x801205150D4400E0ULL,
327 0x801205150D440004ULL, 0x801205150D4400E4ULL,
329 0x80020515F2100000ULL, 0x80020515F21000E0ULL,
331 0x80020515F2100004ULL, 0x80020515F21000E4ULL,
336 static const u64 xena_dtx_cfg[] = {
338 0x8000051500000000ULL, 0x80000515000000E0ULL,
340 0x80000515D9350004ULL, 0x80000515D93500E4ULL,
342 0x8001051500000000ULL, 0x80010515000000E0ULL,
344 0x80010515001E0004ULL, 0x80010515001E00E4ULL,
346 0x8002051500000000ULL, 0x80020515000000E0ULL,
348 0x80020515F2100004ULL, 0x80020515F21000E4ULL,
353 * Constants for Fixing the MacAddress problem seen mostly on
356 static const u64 fix_mac[] = {
357 0x0060000000000000ULL, 0x0060600000000000ULL,
358 0x0040600000000000ULL, 0x0000600000000000ULL,
359 0x0020600000000000ULL, 0x0060600000000000ULL,
360 0x0020600000000000ULL, 0x0060600000000000ULL,
361 0x0020600000000000ULL, 0x0060600000000000ULL,
362 0x0020600000000000ULL, 0x0060600000000000ULL,
363 0x0020600000000000ULL, 0x0060600000000000ULL,
364 0x0020600000000000ULL, 0x0060600000000000ULL,
365 0x0020600000000000ULL, 0x0060600000000000ULL,
366 0x0020600000000000ULL, 0x0060600000000000ULL,
367 0x0020600000000000ULL, 0x0060600000000000ULL,
368 0x0020600000000000ULL, 0x0060600000000000ULL,
369 0x0020600000000000ULL, 0x0000600000000000ULL,
370 0x0040600000000000ULL, 0x0060600000000000ULL,
374 MODULE_AUTHOR("Raghavendra Koushik <raghavendra.koushik@neterion.com>");
375 MODULE_LICENSE("GPL");
376 MODULE_VERSION(DRV_VERSION);
379 /* Module Loadable parameters. */
380 S2IO_PARM_INT(tx_fifo_num, 1);
381 S2IO_PARM_INT(rx_ring_num, 1);
384 S2IO_PARM_INT(rx_ring_mode, 1);
385 S2IO_PARM_INT(use_continuous_tx_intrs, 1);
386 S2IO_PARM_INT(rmac_pause_time, 0x100);
387 S2IO_PARM_INT(mc_pause_threshold_q0q3, 187);
388 S2IO_PARM_INT(mc_pause_threshold_q4q7, 187);
389 S2IO_PARM_INT(shared_splits, 0);
390 S2IO_PARM_INT(tmac_util_period, 5);
391 S2IO_PARM_INT(rmac_util_period, 5);
392 S2IO_PARM_INT(bimodal, 0);
393 S2IO_PARM_INT(l3l4hdr_size, 128);
394 /* Frequency of Rx desc syncs expressed as power of 2 */
395 S2IO_PARM_INT(rxsync_frequency, 3);
396 /* Interrupt type. Values can be 0(INTA), 1(MSI), 2(MSI_X) */
397 S2IO_PARM_INT(intr_type, 0);
398 /* Large receive offload feature */
399 S2IO_PARM_INT(lro, 0);
400 /* Max pkts to be aggregated by LRO at one time. If not specified,
401 * aggregation happens until we hit max IP pkt size(64K)
403 S2IO_PARM_INT(lro_max_pkts, 0xFFFF);
404 S2IO_PARM_INT(indicate_max_pkts, 0);
406 S2IO_PARM_INT(napi, 1);
407 S2IO_PARM_INT(ufo, 0);
409 static unsigned int tx_fifo_len[MAX_TX_FIFOS] =
410 {DEFAULT_FIFO_0_LEN, [1 ...(MAX_TX_FIFOS - 1)] = DEFAULT_FIFO_1_7_LEN};
411 static unsigned int rx_ring_sz[MAX_RX_RINGS] =
412 {[0 ...(MAX_RX_RINGS - 1)] = SMALL_BLK_CNT};
413 static unsigned int rts_frm_len[MAX_RX_RINGS] =
414 {[0 ...(MAX_RX_RINGS - 1)] = 0 };
416 module_param_array(tx_fifo_len, uint, NULL, 0);
417 module_param_array(rx_ring_sz, uint, NULL, 0);
418 module_param_array(rts_frm_len, uint, NULL, 0);
422 * This table lists all the devices that this driver supports.
424 static struct pci_device_id s2io_tbl[] __devinitdata = {
425 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_WIN,
426 PCI_ANY_ID, PCI_ANY_ID},
427 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_UNI,
428 PCI_ANY_ID, PCI_ANY_ID},
429 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_WIN,
430 PCI_ANY_ID, PCI_ANY_ID},
431 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_UNI,
432 PCI_ANY_ID, PCI_ANY_ID},
436 MODULE_DEVICE_TABLE(pci, s2io_tbl);
438 static struct pci_driver s2io_driver = {
440 .id_table = s2io_tbl,
441 .probe = s2io_init_nic,
442 .remove = __devexit_p(s2io_rem_nic),
445 /* A simplifier macro used both by init and free shared_mem Fns(). */
446 #define TXD_MEM_PAGE_CNT(len, per_each) ((len+per_each - 1) / per_each)
449 * init_shared_mem - Allocation and Initialization of Memory
450 * @nic: Device private variable.
451 * Description: The function allocates all the memory areas shared
452 * between the NIC and the driver. This includes Tx descriptors,
453 * Rx descriptors and the statistics block.
456 static int init_shared_mem(struct s2io_nic *nic)
459 void *tmp_v_addr, *tmp_v_addr_next;
460 dma_addr_t tmp_p_addr, tmp_p_addr_next;
461 RxD_block_t *pre_rxd_blk = NULL;
463 int lst_size, lst_per_page;
464 struct net_device *dev = nic->dev;
468 mac_info_t *mac_control;
469 struct config_param *config;
471 mac_control = &nic->mac_control;
472 config = &nic->config;
475 /* Allocation and initialization of TXDLs in FIOFs */
477 for (i = 0; i < config->tx_fifo_num; i++) {
478 size += config->tx_cfg[i].fifo_len;
480 if (size > MAX_AVAILABLE_TXDS) {
481 DBG_PRINT(ERR_DBG, "s2io: Requested TxDs too high, ");
482 DBG_PRINT(ERR_DBG, "Requested: %d, max supported: 8192\n", size);
486 lst_size = (sizeof(TxD_t) * config->max_txds);
487 lst_per_page = PAGE_SIZE / lst_size;
489 for (i = 0; i < config->tx_fifo_num; i++) {
490 int fifo_len = config->tx_cfg[i].fifo_len;
491 int list_holder_size = fifo_len * sizeof(list_info_hold_t);
492 mac_control->fifos[i].list_info = kmalloc(list_holder_size,
494 if (!mac_control->fifos[i].list_info) {
496 "Malloc failed for list_info\n");
499 memset(mac_control->fifos[i].list_info, 0, list_holder_size);
501 for (i = 0; i < config->tx_fifo_num; i++) {
502 int page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
504 mac_control->fifos[i].tx_curr_put_info.offset = 0;
505 mac_control->fifos[i].tx_curr_put_info.fifo_len =
506 config->tx_cfg[i].fifo_len - 1;
507 mac_control->fifos[i].tx_curr_get_info.offset = 0;
508 mac_control->fifos[i].tx_curr_get_info.fifo_len =
509 config->tx_cfg[i].fifo_len - 1;
510 mac_control->fifos[i].fifo_no = i;
511 mac_control->fifos[i].nic = nic;
512 mac_control->fifos[i].max_txds = MAX_SKB_FRAGS + 2;
514 for (j = 0; j < page_num; j++) {
518 tmp_v = pci_alloc_consistent(nic->pdev,
522 "pci_alloc_consistent ");
523 DBG_PRINT(ERR_DBG, "failed for TxDL\n");
526 /* If we got a zero DMA address(can happen on
527 * certain platforms like PPC), reallocate.
528 * Store virtual address of page we don't want,
532 mac_control->zerodma_virt_addr = tmp_v;
534 "%s: Zero DMA address for TxDL. ", dev->name);
536 "Virtual address %p\n", tmp_v);
537 tmp_v = pci_alloc_consistent(nic->pdev,
541 "pci_alloc_consistent ");
542 DBG_PRINT(ERR_DBG, "failed for TxDL\n");
546 while (k < lst_per_page) {
547 int l = (j * lst_per_page) + k;
548 if (l == config->tx_cfg[i].fifo_len)
550 mac_control->fifos[i].list_info[l].list_virt_addr =
551 tmp_v + (k * lst_size);
552 mac_control->fifos[i].list_info[l].list_phy_addr =
553 tmp_p + (k * lst_size);
559 nic->ufo_in_band_v = kcalloc(size, sizeof(u64), GFP_KERNEL);
560 if (!nic->ufo_in_band_v)
563 /* Allocation and initialization of RXDs in Rings */
565 for (i = 0; i < config->rx_ring_num; i++) {
566 if (config->rx_cfg[i].num_rxd %
567 (rxd_count[nic->rxd_mode] + 1)) {
568 DBG_PRINT(ERR_DBG, "%s: RxD count of ", dev->name);
569 DBG_PRINT(ERR_DBG, "Ring%d is not a multiple of ",
571 DBG_PRINT(ERR_DBG, "RxDs per Block");
574 size += config->rx_cfg[i].num_rxd;
575 mac_control->rings[i].block_count =
576 config->rx_cfg[i].num_rxd /
577 (rxd_count[nic->rxd_mode] + 1 );
578 mac_control->rings[i].pkt_cnt = config->rx_cfg[i].num_rxd -
579 mac_control->rings[i].block_count;
581 if (nic->rxd_mode == RXD_MODE_1)
582 size = (size * (sizeof(RxD1_t)));
584 size = (size * (sizeof(RxD3_t)));
586 for (i = 0; i < config->rx_ring_num; i++) {
587 mac_control->rings[i].rx_curr_get_info.block_index = 0;
588 mac_control->rings[i].rx_curr_get_info.offset = 0;
589 mac_control->rings[i].rx_curr_get_info.ring_len =
590 config->rx_cfg[i].num_rxd - 1;
591 mac_control->rings[i].rx_curr_put_info.block_index = 0;
592 mac_control->rings[i].rx_curr_put_info.offset = 0;
593 mac_control->rings[i].rx_curr_put_info.ring_len =
594 config->rx_cfg[i].num_rxd - 1;
595 mac_control->rings[i].nic = nic;
596 mac_control->rings[i].ring_no = i;
598 blk_cnt = config->rx_cfg[i].num_rxd /
599 (rxd_count[nic->rxd_mode] + 1);
600 /* Allocating all the Rx blocks */
601 for (j = 0; j < blk_cnt; j++) {
602 rx_block_info_t *rx_blocks;
605 rx_blocks = &mac_control->rings[i].rx_blocks[j];
606 size = SIZE_OF_BLOCK; //size is always page size
607 tmp_v_addr = pci_alloc_consistent(nic->pdev, size,
609 if (tmp_v_addr == NULL) {
611 * In case of failure, free_shared_mem()
612 * is called, which should free any
613 * memory that was alloced till the
616 rx_blocks->block_virt_addr = tmp_v_addr;
619 memset(tmp_v_addr, 0, size);
620 rx_blocks->block_virt_addr = tmp_v_addr;
621 rx_blocks->block_dma_addr = tmp_p_addr;
622 rx_blocks->rxds = kmalloc(sizeof(rxd_info_t)*
623 rxd_count[nic->rxd_mode],
625 if (!rx_blocks->rxds)
627 for (l=0; l<rxd_count[nic->rxd_mode];l++) {
628 rx_blocks->rxds[l].virt_addr =
629 rx_blocks->block_virt_addr +
630 (rxd_size[nic->rxd_mode] * l);
631 rx_blocks->rxds[l].dma_addr =
632 rx_blocks->block_dma_addr +
633 (rxd_size[nic->rxd_mode] * l);
636 /* Interlinking all Rx Blocks */
637 for (j = 0; j < blk_cnt; j++) {
639 mac_control->rings[i].rx_blocks[j].block_virt_addr;
641 mac_control->rings[i].rx_blocks[(j + 1) %
642 blk_cnt].block_virt_addr;
644 mac_control->rings[i].rx_blocks[j].block_dma_addr;
646 mac_control->rings[i].rx_blocks[(j + 1) %
647 blk_cnt].block_dma_addr;
649 pre_rxd_blk = (RxD_block_t *) tmp_v_addr;
650 pre_rxd_blk->reserved_2_pNext_RxD_block =
651 (unsigned long) tmp_v_addr_next;
652 pre_rxd_blk->pNext_RxD_Blk_physical =
653 (u64) tmp_p_addr_next;
656 if (nic->rxd_mode >= RXD_MODE_3A) {
658 * Allocation of Storages for buffer addresses in 2BUFF mode
659 * and the buffers as well.
661 for (i = 0; i < config->rx_ring_num; i++) {
662 blk_cnt = config->rx_cfg[i].num_rxd /
663 (rxd_count[nic->rxd_mode]+ 1);
664 mac_control->rings[i].ba =
665 kmalloc((sizeof(buffAdd_t *) * blk_cnt),
667 if (!mac_control->rings[i].ba)
669 for (j = 0; j < blk_cnt; j++) {
671 mac_control->rings[i].ba[j] =
672 kmalloc((sizeof(buffAdd_t) *
673 (rxd_count[nic->rxd_mode] + 1)),
675 if (!mac_control->rings[i].ba[j])
677 while (k != rxd_count[nic->rxd_mode]) {
678 ba = &mac_control->rings[i].ba[j][k];
680 ba->ba_0_org = (void *) kmalloc
681 (BUF0_LEN + ALIGN_SIZE, GFP_KERNEL);
684 tmp = (unsigned long)ba->ba_0_org;
686 tmp &= ~((unsigned long) ALIGN_SIZE);
687 ba->ba_0 = (void *) tmp;
689 ba->ba_1_org = (void *) kmalloc
690 (BUF1_LEN + ALIGN_SIZE, GFP_KERNEL);
693 tmp = (unsigned long) ba->ba_1_org;
695 tmp &= ~((unsigned long) ALIGN_SIZE);
696 ba->ba_1 = (void *) tmp;
703 /* Allocation and initialization of Statistics block */
704 size = sizeof(StatInfo_t);
705 mac_control->stats_mem = pci_alloc_consistent
706 (nic->pdev, size, &mac_control->stats_mem_phy);
708 if (!mac_control->stats_mem) {
710 * In case of failure, free_shared_mem() is called, which
711 * should free any memory that was alloced till the
716 mac_control->stats_mem_sz = size;
718 tmp_v_addr = mac_control->stats_mem;
719 mac_control->stats_info = (StatInfo_t *) tmp_v_addr;
720 memset(tmp_v_addr, 0, size);
721 DBG_PRINT(INIT_DBG, "%s:Ring Mem PHY: 0x%llx\n", dev->name,
722 (unsigned long long) tmp_p_addr);
728 * free_shared_mem - Free the allocated Memory
729 * @nic: Device private variable.
730 * Description: This function is to free all memory locations allocated by
731 * the init_shared_mem() function and return it to the kernel.
734 static void free_shared_mem(struct s2io_nic *nic)
736 int i, j, blk_cnt, size;
738 dma_addr_t tmp_p_addr;
739 mac_info_t *mac_control;
740 struct config_param *config;
741 int lst_size, lst_per_page;
742 struct net_device *dev = nic->dev;
747 mac_control = &nic->mac_control;
748 config = &nic->config;
750 lst_size = (sizeof(TxD_t) * config->max_txds);
751 lst_per_page = PAGE_SIZE / lst_size;
753 for (i = 0; i < config->tx_fifo_num; i++) {
754 int page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
756 for (j = 0; j < page_num; j++) {
757 int mem_blks = (j * lst_per_page);
758 if (!mac_control->fifos[i].list_info)
760 if (!mac_control->fifos[i].list_info[mem_blks].
763 pci_free_consistent(nic->pdev, PAGE_SIZE,
764 mac_control->fifos[i].
767 mac_control->fifos[i].
771 /* If we got a zero DMA address during allocation,
774 if (mac_control->zerodma_virt_addr) {
775 pci_free_consistent(nic->pdev, PAGE_SIZE,
776 mac_control->zerodma_virt_addr,
779 "%s: Freeing TxDL with zero DMA addr. ",
781 DBG_PRINT(INIT_DBG, "Virtual address %p\n",
782 mac_control->zerodma_virt_addr);
784 kfree(mac_control->fifos[i].list_info);
787 size = SIZE_OF_BLOCK;
788 for (i = 0; i < config->rx_ring_num; i++) {
789 blk_cnt = mac_control->rings[i].block_count;
790 for (j = 0; j < blk_cnt; j++) {
791 tmp_v_addr = mac_control->rings[i].rx_blocks[j].
793 tmp_p_addr = mac_control->rings[i].rx_blocks[j].
795 if (tmp_v_addr == NULL)
797 pci_free_consistent(nic->pdev, size,
798 tmp_v_addr, tmp_p_addr);
799 kfree(mac_control->rings[i].rx_blocks[j].rxds);
803 if (nic->rxd_mode >= RXD_MODE_3A) {
804 /* Freeing buffer storage addresses in 2BUFF mode. */
805 for (i = 0; i < config->rx_ring_num; i++) {
806 blk_cnt = config->rx_cfg[i].num_rxd /
807 (rxd_count[nic->rxd_mode] + 1);
808 for (j = 0; j < blk_cnt; j++) {
810 if (!mac_control->rings[i].ba[j])
812 while (k != rxd_count[nic->rxd_mode]) {
814 &mac_control->rings[i].ba[j][k];
819 kfree(mac_control->rings[i].ba[j]);
821 kfree(mac_control->rings[i].ba);
825 if (mac_control->stats_mem) {
826 pci_free_consistent(nic->pdev,
827 mac_control->stats_mem_sz,
828 mac_control->stats_mem,
829 mac_control->stats_mem_phy);
831 if (nic->ufo_in_band_v)
832 kfree(nic->ufo_in_band_v);
836 * s2io_verify_pci_mode -
839 static int s2io_verify_pci_mode(nic_t *nic)
841 XENA_dev_config_t __iomem *bar0 = nic->bar0;
842 register u64 val64 = 0;
845 val64 = readq(&bar0->pci_mode);
846 mode = (u8)GET_PCI_MODE(val64);
848 if ( val64 & PCI_MODE_UNKNOWN_MODE)
849 return -1; /* Unknown PCI mode */
853 #define NEC_VENID 0x1033
854 #define NEC_DEVID 0x0125
855 static int s2io_on_nec_bridge(struct pci_dev *s2io_pdev)
857 struct pci_dev *tdev = NULL;
858 while ((tdev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, tdev)) != NULL) {
859 if (tdev->vendor == NEC_VENID && tdev->device == NEC_DEVID) {
860 if (tdev->bus == s2io_pdev->bus->parent)
868 static int bus_speed[8] = {33, 133, 133, 200, 266, 133, 200, 266};
870 * s2io_print_pci_mode -
872 static int s2io_print_pci_mode(nic_t *nic)
874 XENA_dev_config_t __iomem *bar0 = nic->bar0;
875 register u64 val64 = 0;
877 struct config_param *config = &nic->config;
879 val64 = readq(&bar0->pci_mode);
880 mode = (u8)GET_PCI_MODE(val64);
882 if ( val64 & PCI_MODE_UNKNOWN_MODE)
883 return -1; /* Unknown PCI mode */
885 config->bus_speed = bus_speed[mode];
887 if (s2io_on_nec_bridge(nic->pdev)) {
888 DBG_PRINT(ERR_DBG, "%s: Device is on PCI-E bus\n",
893 if (val64 & PCI_MODE_32_BITS) {
894 DBG_PRINT(ERR_DBG, "%s: Device is on 32 bit ", nic->dev->name);
896 DBG_PRINT(ERR_DBG, "%s: Device is on 64 bit ", nic->dev->name);
900 case PCI_MODE_PCI_33:
901 DBG_PRINT(ERR_DBG, "33MHz PCI bus\n");
903 case PCI_MODE_PCI_66:
904 DBG_PRINT(ERR_DBG, "66MHz PCI bus\n");
906 case PCI_MODE_PCIX_M1_66:
907 DBG_PRINT(ERR_DBG, "66MHz PCIX(M1) bus\n");
909 case PCI_MODE_PCIX_M1_100:
910 DBG_PRINT(ERR_DBG, "100MHz PCIX(M1) bus\n");
912 case PCI_MODE_PCIX_M1_133:
913 DBG_PRINT(ERR_DBG, "133MHz PCIX(M1) bus\n");
915 case PCI_MODE_PCIX_M2_66:
916 DBG_PRINT(ERR_DBG, "133MHz PCIX(M2) bus\n");
918 case PCI_MODE_PCIX_M2_100:
919 DBG_PRINT(ERR_DBG, "200MHz PCIX(M2) bus\n");
921 case PCI_MODE_PCIX_M2_133:
922 DBG_PRINT(ERR_DBG, "266MHz PCIX(M2) bus\n");
925 return -1; /* Unsupported bus speed */
932 * init_nic - Initialization of hardware
933 * @nic: device peivate variable
934 * Description: The function sequentially configures every block
935 * of the H/W from their reset values.
936 * Return Value: SUCCESS on success and
937 * '-1' on failure (endian settings incorrect).
940 static int init_nic(struct s2io_nic *nic)
942 XENA_dev_config_t __iomem *bar0 = nic->bar0;
943 struct net_device *dev = nic->dev;
944 register u64 val64 = 0;
948 mac_info_t *mac_control;
949 struct config_param *config;
951 unsigned long long mem_share;
954 mac_control = &nic->mac_control;
955 config = &nic->config;
957 /* to set the swapper controle on the card */
958 if(s2io_set_swapper(nic)) {
959 DBG_PRINT(ERR_DBG,"ERROR: Setting Swapper failed\n");
964 * Herc requires EOI to be removed from reset before XGXS, so..
966 if (nic->device_type & XFRAME_II_DEVICE) {
967 val64 = 0xA500000000ULL;
968 writeq(val64, &bar0->sw_reset);
970 val64 = readq(&bar0->sw_reset);
973 /* Remove XGXS from reset state */
975 writeq(val64, &bar0->sw_reset);
977 val64 = readq(&bar0->sw_reset);
979 /* Enable Receiving broadcasts */
980 add = &bar0->mac_cfg;
981 val64 = readq(&bar0->mac_cfg);
982 val64 |= MAC_RMAC_BCAST_ENABLE;
983 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
984 writel((u32) val64, add);
985 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
986 writel((u32) (val64 >> 32), (add + 4));
988 /* Read registers in all blocks */
989 val64 = readq(&bar0->mac_int_mask);
990 val64 = readq(&bar0->mc_int_mask);
991 val64 = readq(&bar0->xgxs_int_mask);
995 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
997 if (nic->device_type & XFRAME_II_DEVICE) {
998 while (herc_act_dtx_cfg[dtx_cnt] != END_SIGN) {
999 SPECIAL_REG_WRITE(herc_act_dtx_cfg[dtx_cnt],
1000 &bar0->dtx_control, UF);
1002 msleep(1); /* Necessary!! */
1006 while (xena_dtx_cfg[dtx_cnt] != END_SIGN) {
1007 SPECIAL_REG_WRITE(xena_dtx_cfg[dtx_cnt],
1008 &bar0->dtx_control, UF);
1009 val64 = readq(&bar0->dtx_control);
1014 /* Tx DMA Initialization */
1016 writeq(val64, &bar0->tx_fifo_partition_0);
1017 writeq(val64, &bar0->tx_fifo_partition_1);
1018 writeq(val64, &bar0->tx_fifo_partition_2);
1019 writeq(val64, &bar0->tx_fifo_partition_3);
1022 for (i = 0, j = 0; i < config->tx_fifo_num; i++) {
1024 vBIT(config->tx_cfg[i].fifo_len - 1, ((i * 32) + 19),
1025 13) | vBIT(config->tx_cfg[i].fifo_priority,
1028 if (i == (config->tx_fifo_num - 1)) {
1035 writeq(val64, &bar0->tx_fifo_partition_0);
1039 writeq(val64, &bar0->tx_fifo_partition_1);
1043 writeq(val64, &bar0->tx_fifo_partition_2);
1047 writeq(val64, &bar0->tx_fifo_partition_3);
1053 * Disable 4 PCCs for Xena1, 2 and 3 as per H/W bug
1054 * SXE-008 TRANSMIT DMA ARBITRATION ISSUE.
1056 if ((nic->device_type == XFRAME_I_DEVICE) &&
1057 (get_xena_rev_id(nic->pdev) < 4))
1058 writeq(PCC_ENABLE_FOUR, &bar0->pcc_enable);
1060 val64 = readq(&bar0->tx_fifo_partition_0);
1061 DBG_PRINT(INIT_DBG, "Fifo partition at: 0x%p is: 0x%llx\n",
1062 &bar0->tx_fifo_partition_0, (unsigned long long) val64);
1065 * Initialization of Tx_PA_CONFIG register to ignore packet
1066 * integrity checking.
1068 val64 = readq(&bar0->tx_pa_cfg);
1069 val64 |= TX_PA_CFG_IGNORE_FRM_ERR | TX_PA_CFG_IGNORE_SNAP_OUI |
1070 TX_PA_CFG_IGNORE_LLC_CTRL | TX_PA_CFG_IGNORE_L2_ERR;
1071 writeq(val64, &bar0->tx_pa_cfg);
1073 /* Rx DMA intialization. */
1075 for (i = 0; i < config->rx_ring_num; i++) {
1077 vBIT(config->rx_cfg[i].ring_priority, (5 + (i * 8)),
1080 writeq(val64, &bar0->rx_queue_priority);
1083 * Allocating equal share of memory to all the
1087 if (nic->device_type & XFRAME_II_DEVICE)
1092 for (i = 0; i < config->rx_ring_num; i++) {
1095 mem_share = (mem_size / config->rx_ring_num +
1096 mem_size % config->rx_ring_num);
1097 val64 |= RX_QUEUE_CFG_Q0_SZ(mem_share);
1100 mem_share = (mem_size / config->rx_ring_num);
1101 val64 |= RX_QUEUE_CFG_Q1_SZ(mem_share);
1104 mem_share = (mem_size / config->rx_ring_num);
1105 val64 |= RX_QUEUE_CFG_Q2_SZ(mem_share);
1108 mem_share = (mem_size / config->rx_ring_num);
1109 val64 |= RX_QUEUE_CFG_Q3_SZ(mem_share);
1112 mem_share = (mem_size / config->rx_ring_num);
1113 val64 |= RX_QUEUE_CFG_Q4_SZ(mem_share);
1116 mem_share = (mem_size / config->rx_ring_num);
1117 val64 |= RX_QUEUE_CFG_Q5_SZ(mem_share);
1120 mem_share = (mem_size / config->rx_ring_num);
1121 val64 |= RX_QUEUE_CFG_Q6_SZ(mem_share);
1124 mem_share = (mem_size / config->rx_ring_num);
1125 val64 |= RX_QUEUE_CFG_Q7_SZ(mem_share);
1129 writeq(val64, &bar0->rx_queue_cfg);
1132 * Filling Tx round robin registers
1133 * as per the number of FIFOs
1135 switch (config->tx_fifo_num) {
1137 val64 = 0x0000000000000000ULL;
1138 writeq(val64, &bar0->tx_w_round_robin_0);
1139 writeq(val64, &bar0->tx_w_round_robin_1);
1140 writeq(val64, &bar0->tx_w_round_robin_2);
1141 writeq(val64, &bar0->tx_w_round_robin_3);
1142 writeq(val64, &bar0->tx_w_round_robin_4);
1145 val64 = 0x0000010000010000ULL;
1146 writeq(val64, &bar0->tx_w_round_robin_0);
1147 val64 = 0x0100000100000100ULL;
1148 writeq(val64, &bar0->tx_w_round_robin_1);
1149 val64 = 0x0001000001000001ULL;
1150 writeq(val64, &bar0->tx_w_round_robin_2);
1151 val64 = 0x0000010000010000ULL;
1152 writeq(val64, &bar0->tx_w_round_robin_3);
1153 val64 = 0x0100000000000000ULL;
1154 writeq(val64, &bar0->tx_w_round_robin_4);
1157 val64 = 0x0001000102000001ULL;
1158 writeq(val64, &bar0->tx_w_round_robin_0);
1159 val64 = 0x0001020000010001ULL;
1160 writeq(val64, &bar0->tx_w_round_robin_1);
1161 val64 = 0x0200000100010200ULL;
1162 writeq(val64, &bar0->tx_w_round_robin_2);
1163 val64 = 0x0001000102000001ULL;
1164 writeq(val64, &bar0->tx_w_round_robin_3);
1165 val64 = 0x0001020000000000ULL;
1166 writeq(val64, &bar0->tx_w_round_robin_4);
1169 val64 = 0x0001020300010200ULL;
1170 writeq(val64, &bar0->tx_w_round_robin_0);
1171 val64 = 0x0100000102030001ULL;
1172 writeq(val64, &bar0->tx_w_round_robin_1);
1173 val64 = 0x0200010000010203ULL;
1174 writeq(val64, &bar0->tx_w_round_robin_2);
1175 val64 = 0x0001020001000001ULL;
1176 writeq(val64, &bar0->tx_w_round_robin_3);
1177 val64 = 0x0203000100000000ULL;
1178 writeq(val64, &bar0->tx_w_round_robin_4);
1181 val64 = 0x0001000203000102ULL;
1182 writeq(val64, &bar0->tx_w_round_robin_0);
1183 val64 = 0x0001020001030004ULL;
1184 writeq(val64, &bar0->tx_w_round_robin_1);
1185 val64 = 0x0001000203000102ULL;
1186 writeq(val64, &bar0->tx_w_round_robin_2);
1187 val64 = 0x0001020001030004ULL;
1188 writeq(val64, &bar0->tx_w_round_robin_3);
1189 val64 = 0x0001000000000000ULL;
1190 writeq(val64, &bar0->tx_w_round_robin_4);
1193 val64 = 0x0001020304000102ULL;
1194 writeq(val64, &bar0->tx_w_round_robin_0);
1195 val64 = 0x0304050001020001ULL;
1196 writeq(val64, &bar0->tx_w_round_robin_1);
1197 val64 = 0x0203000100000102ULL;
1198 writeq(val64, &bar0->tx_w_round_robin_2);
1199 val64 = 0x0304000102030405ULL;
1200 writeq(val64, &bar0->tx_w_round_robin_3);
1201 val64 = 0x0001000200000000ULL;
1202 writeq(val64, &bar0->tx_w_round_robin_4);
1205 val64 = 0x0001020001020300ULL;
1206 writeq(val64, &bar0->tx_w_round_robin_0);
1207 val64 = 0x0102030400010203ULL;
1208 writeq(val64, &bar0->tx_w_round_robin_1);
1209 val64 = 0x0405060001020001ULL;
1210 writeq(val64, &bar0->tx_w_round_robin_2);
1211 val64 = 0x0304050000010200ULL;
1212 writeq(val64, &bar0->tx_w_round_robin_3);
1213 val64 = 0x0102030000000000ULL;
1214 writeq(val64, &bar0->tx_w_round_robin_4);
1217 val64 = 0x0001020300040105ULL;
1218 writeq(val64, &bar0->tx_w_round_robin_0);
1219 val64 = 0x0200030106000204ULL;
1220 writeq(val64, &bar0->tx_w_round_robin_1);
1221 val64 = 0x0103000502010007ULL;
1222 writeq(val64, &bar0->tx_w_round_robin_2);
1223 val64 = 0x0304010002060500ULL;
1224 writeq(val64, &bar0->tx_w_round_robin_3);
1225 val64 = 0x0103020400000000ULL;
1226 writeq(val64, &bar0->tx_w_round_robin_4);
1230 /* Enable all configured Tx FIFO partitions */
1231 val64 = readq(&bar0->tx_fifo_partition_0);
1232 val64 |= (TX_FIFO_PARTITION_EN);
1233 writeq(val64, &bar0->tx_fifo_partition_0);
1235 /* Filling the Rx round robin registers as per the
1236 * number of Rings and steering based on QoS.
1238 switch (config->rx_ring_num) {
1240 val64 = 0x8080808080808080ULL;
1241 writeq(val64, &bar0->rts_qos_steering);
1244 val64 = 0x0000010000010000ULL;
1245 writeq(val64, &bar0->rx_w_round_robin_0);
1246 val64 = 0x0100000100000100ULL;
1247 writeq(val64, &bar0->rx_w_round_robin_1);
1248 val64 = 0x0001000001000001ULL;
1249 writeq(val64, &bar0->rx_w_round_robin_2);
1250 val64 = 0x0000010000010000ULL;
1251 writeq(val64, &bar0->rx_w_round_robin_3);
1252 val64 = 0x0100000000000000ULL;
1253 writeq(val64, &bar0->rx_w_round_robin_4);
1255 val64 = 0x8080808040404040ULL;
1256 writeq(val64, &bar0->rts_qos_steering);
1259 val64 = 0x0001000102000001ULL;
1260 writeq(val64, &bar0->rx_w_round_robin_0);
1261 val64 = 0x0001020000010001ULL;
1262 writeq(val64, &bar0->rx_w_round_robin_1);
1263 val64 = 0x0200000100010200ULL;
1264 writeq(val64, &bar0->rx_w_round_robin_2);
1265 val64 = 0x0001000102000001ULL;
1266 writeq(val64, &bar0->rx_w_round_robin_3);
1267 val64 = 0x0001020000000000ULL;
1268 writeq(val64, &bar0->rx_w_round_robin_4);
1270 val64 = 0x8080804040402020ULL;
1271 writeq(val64, &bar0->rts_qos_steering);
1274 val64 = 0x0001020300010200ULL;
1275 writeq(val64, &bar0->rx_w_round_robin_0);
1276 val64 = 0x0100000102030001ULL;
1277 writeq(val64, &bar0->rx_w_round_robin_1);
1278 val64 = 0x0200010000010203ULL;
1279 writeq(val64, &bar0->rx_w_round_robin_2);
1280 val64 = 0x0001020001000001ULL;
1281 writeq(val64, &bar0->rx_w_round_robin_3);
1282 val64 = 0x0203000100000000ULL;
1283 writeq(val64, &bar0->rx_w_round_robin_4);
1285 val64 = 0x8080404020201010ULL;
1286 writeq(val64, &bar0->rts_qos_steering);
1289 val64 = 0x0001000203000102ULL;
1290 writeq(val64, &bar0->rx_w_round_robin_0);
1291 val64 = 0x0001020001030004ULL;
1292 writeq(val64, &bar0->rx_w_round_robin_1);
1293 val64 = 0x0001000203000102ULL;
1294 writeq(val64, &bar0->rx_w_round_robin_2);
1295 val64 = 0x0001020001030004ULL;
1296 writeq(val64, &bar0->rx_w_round_robin_3);
1297 val64 = 0x0001000000000000ULL;
1298 writeq(val64, &bar0->rx_w_round_robin_4);
1300 val64 = 0x8080404020201008ULL;
1301 writeq(val64, &bar0->rts_qos_steering);
1304 val64 = 0x0001020304000102ULL;
1305 writeq(val64, &bar0->rx_w_round_robin_0);
1306 val64 = 0x0304050001020001ULL;
1307 writeq(val64, &bar0->rx_w_round_robin_1);
1308 val64 = 0x0203000100000102ULL;
1309 writeq(val64, &bar0->rx_w_round_robin_2);
1310 val64 = 0x0304000102030405ULL;
1311 writeq(val64, &bar0->rx_w_round_robin_3);
1312 val64 = 0x0001000200000000ULL;
1313 writeq(val64, &bar0->rx_w_round_robin_4);
1315 val64 = 0x8080404020100804ULL;
1316 writeq(val64, &bar0->rts_qos_steering);
1319 val64 = 0x0001020001020300ULL;
1320 writeq(val64, &bar0->rx_w_round_robin_0);
1321 val64 = 0x0102030400010203ULL;
1322 writeq(val64, &bar0->rx_w_round_robin_1);
1323 val64 = 0x0405060001020001ULL;
1324 writeq(val64, &bar0->rx_w_round_robin_2);
1325 val64 = 0x0304050000010200ULL;
1326 writeq(val64, &bar0->rx_w_round_robin_3);
1327 val64 = 0x0102030000000000ULL;
1328 writeq(val64, &bar0->rx_w_round_robin_4);
1330 val64 = 0x8080402010080402ULL;
1331 writeq(val64, &bar0->rts_qos_steering);
1334 val64 = 0x0001020300040105ULL;
1335 writeq(val64, &bar0->rx_w_round_robin_0);
1336 val64 = 0x0200030106000204ULL;
1337 writeq(val64, &bar0->rx_w_round_robin_1);
1338 val64 = 0x0103000502010007ULL;
1339 writeq(val64, &bar0->rx_w_round_robin_2);
1340 val64 = 0x0304010002060500ULL;
1341 writeq(val64, &bar0->rx_w_round_robin_3);
1342 val64 = 0x0103020400000000ULL;
1343 writeq(val64, &bar0->rx_w_round_robin_4);
1345 val64 = 0x8040201008040201ULL;
1346 writeq(val64, &bar0->rts_qos_steering);
1352 for (i = 0; i < 8; i++)
1353 writeq(val64, &bar0->rts_frm_len_n[i]);
1355 /* Set the default rts frame length for the rings configured */
1356 val64 = MAC_RTS_FRM_LEN_SET(dev->mtu+22);
1357 for (i = 0 ; i < config->rx_ring_num ; i++)
1358 writeq(val64, &bar0->rts_frm_len_n[i]);
1360 /* Set the frame length for the configured rings
1361 * desired by the user
1363 for (i = 0; i < config->rx_ring_num; i++) {
1364 /* If rts_frm_len[i] == 0 then it is assumed that user not
1365 * specified frame length steering.
1366 * If the user provides the frame length then program
1367 * the rts_frm_len register for those values or else
1368 * leave it as it is.
1370 if (rts_frm_len[i] != 0) {
1371 writeq(MAC_RTS_FRM_LEN_SET(rts_frm_len[i]),
1372 &bar0->rts_frm_len_n[i]);
1376 /* Program statistics memory */
1377 writeq(mac_control->stats_mem_phy, &bar0->stat_addr);
1379 if (nic->device_type == XFRAME_II_DEVICE) {
1380 val64 = STAT_BC(0x320);
1381 writeq(val64, &bar0->stat_byte_cnt);
1385 * Initializing the sampling rate for the device to calculate the
1386 * bandwidth utilization.
1388 val64 = MAC_TX_LINK_UTIL_VAL(tmac_util_period) |
1389 MAC_RX_LINK_UTIL_VAL(rmac_util_period);
1390 writeq(val64, &bar0->mac_link_util);
1394 * Initializing the Transmit and Receive Traffic Interrupt
1398 * TTI Initialization. Default Tx timer gets us about
1399 * 250 interrupts per sec. Continuous interrupts are enabled
1402 if (nic->device_type == XFRAME_II_DEVICE) {
1403 int count = (nic->config.bus_speed * 125)/2;
1404 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(count);
1407 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(0x2078);
1409 val64 |= TTI_DATA1_MEM_TX_URNG_A(0xA) |
1410 TTI_DATA1_MEM_TX_URNG_B(0x10) |
1411 TTI_DATA1_MEM_TX_URNG_C(0x30) | TTI_DATA1_MEM_TX_TIMER_AC_EN;
1412 if (use_continuous_tx_intrs)
1413 val64 |= TTI_DATA1_MEM_TX_TIMER_CI_EN;
1414 writeq(val64, &bar0->tti_data1_mem);
1416 val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) |
1417 TTI_DATA2_MEM_TX_UFC_B(0x20) |
1418 TTI_DATA2_MEM_TX_UFC_C(0x40) | TTI_DATA2_MEM_TX_UFC_D(0x80);
1419 writeq(val64, &bar0->tti_data2_mem);
1421 val64 = TTI_CMD_MEM_WE | TTI_CMD_MEM_STROBE_NEW_CMD;
1422 writeq(val64, &bar0->tti_command_mem);
1425 * Once the operation completes, the Strobe bit of the command
1426 * register will be reset. We poll for this particular condition
1427 * We wait for a maximum of 500ms for the operation to complete,
1428 * if it's not complete by then we return error.
1432 val64 = readq(&bar0->tti_command_mem);
1433 if (!(val64 & TTI_CMD_MEM_STROBE_NEW_CMD)) {
1437 DBG_PRINT(ERR_DBG, "%s: TTI init Failed\n",
1445 if (nic->config.bimodal) {
1447 for (k = 0; k < config->rx_ring_num; k++) {
1448 val64 = TTI_CMD_MEM_WE | TTI_CMD_MEM_STROBE_NEW_CMD;
1449 val64 |= TTI_CMD_MEM_OFFSET(0x38+k);
1450 writeq(val64, &bar0->tti_command_mem);
1453 * Once the operation completes, the Strobe bit of the command
1454 * register will be reset. We poll for this particular condition
1455 * We wait for a maximum of 500ms for the operation to complete,
1456 * if it's not complete by then we return error.
1460 val64 = readq(&bar0->tti_command_mem);
1461 if (!(val64 & TTI_CMD_MEM_STROBE_NEW_CMD)) {
1466 "%s: TTI init Failed\n",
1476 /* RTI Initialization */
1477 if (nic->device_type == XFRAME_II_DEVICE) {
1479 * Programmed to generate Apprx 500 Intrs per
1482 int count = (nic->config.bus_speed * 125)/4;
1483 val64 = RTI_DATA1_MEM_RX_TIMER_VAL(count);
1485 val64 = RTI_DATA1_MEM_RX_TIMER_VAL(0xFFF);
1487 val64 |= RTI_DATA1_MEM_RX_URNG_A(0xA) |
1488 RTI_DATA1_MEM_RX_URNG_B(0x10) |
1489 RTI_DATA1_MEM_RX_URNG_C(0x30) | RTI_DATA1_MEM_RX_TIMER_AC_EN;
1491 writeq(val64, &bar0->rti_data1_mem);
1493 val64 = RTI_DATA2_MEM_RX_UFC_A(0x1) |
1494 RTI_DATA2_MEM_RX_UFC_B(0x2) ;
1495 if (nic->intr_type == MSI_X)
1496 val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x20) | \
1497 RTI_DATA2_MEM_RX_UFC_D(0x40));
1499 val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x40) | \
1500 RTI_DATA2_MEM_RX_UFC_D(0x80));
1501 writeq(val64, &bar0->rti_data2_mem);
1503 for (i = 0; i < config->rx_ring_num; i++) {
1504 val64 = RTI_CMD_MEM_WE | RTI_CMD_MEM_STROBE_NEW_CMD
1505 | RTI_CMD_MEM_OFFSET(i);
1506 writeq(val64, &bar0->rti_command_mem);
1509 * Once the operation completes, the Strobe bit of the
1510 * command register will be reset. We poll for this
1511 * particular condition. We wait for a maximum of 500ms
1512 * for the operation to complete, if it's not complete
1513 * by then we return error.
1517 val64 = readq(&bar0->rti_command_mem);
1518 if (!(val64 & RTI_CMD_MEM_STROBE_NEW_CMD)) {
1522 DBG_PRINT(ERR_DBG, "%s: RTI init Failed\n",
1533 * Initializing proper values as Pause threshold into all
1534 * the 8 Queues on Rx side.
1536 writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q0q3);
1537 writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q4q7);
1539 /* Disable RMAC PAD STRIPPING */
1540 add = &bar0->mac_cfg;
1541 val64 = readq(&bar0->mac_cfg);
1542 val64 &= ~(MAC_CFG_RMAC_STRIP_PAD);
1543 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1544 writel((u32) (val64), add);
1545 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1546 writel((u32) (val64 >> 32), (add + 4));
1547 val64 = readq(&bar0->mac_cfg);
1549 /* Enable FCS stripping by adapter */
1550 add = &bar0->mac_cfg;
1551 val64 = readq(&bar0->mac_cfg);
1552 val64 |= MAC_CFG_RMAC_STRIP_FCS;
1553 if (nic->device_type == XFRAME_II_DEVICE)
1554 writeq(val64, &bar0->mac_cfg);
1556 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1557 writel((u32) (val64), add);
1558 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1559 writel((u32) (val64 >> 32), (add + 4));
1563 * Set the time value to be inserted in the pause frame
1564 * generated by xena.
1566 val64 = readq(&bar0->rmac_pause_cfg);
1567 val64 &= ~(RMAC_PAUSE_HG_PTIME(0xffff));
1568 val64 |= RMAC_PAUSE_HG_PTIME(nic->mac_control.rmac_pause_time);
1569 writeq(val64, &bar0->rmac_pause_cfg);
1572 * Set the Threshold Limit for Generating the pause frame
1573 * If the amount of data in any Queue exceeds ratio of
1574 * (mac_control.mc_pause_threshold_q0q3 or q4q7)/256
1575 * pause frame is generated
1578 for (i = 0; i < 4; i++) {
1580 (((u64) 0xFF00 | nic->mac_control.
1581 mc_pause_threshold_q0q3)
1584 writeq(val64, &bar0->mc_pause_thresh_q0q3);
1587 for (i = 0; i < 4; i++) {
1589 (((u64) 0xFF00 | nic->mac_control.
1590 mc_pause_threshold_q4q7)
1593 writeq(val64, &bar0->mc_pause_thresh_q4q7);
1596 * TxDMA will stop Read request if the number of read split has
1597 * exceeded the limit pointed by shared_splits
1599 val64 = readq(&bar0->pic_control);
1600 val64 |= PIC_CNTL_SHARED_SPLITS(shared_splits);
1601 writeq(val64, &bar0->pic_control);
1603 if (nic->config.bus_speed == 266) {
1604 writeq(TXREQTO_VAL(0x7f) | TXREQTO_EN, &bar0->txreqtimeout);
1605 writeq(0x0, &bar0->read_retry_delay);
1606 writeq(0x0, &bar0->write_retry_delay);
1610 * Programming the Herc to split every write transaction
1611 * that does not start on an ADB to reduce disconnects.
1613 if (nic->device_type == XFRAME_II_DEVICE) {
1614 val64 = FAULT_BEHAVIOUR | EXT_REQ_EN |
1615 MISC_LINK_STABILITY_PRD(3);
1616 writeq(val64, &bar0->misc_control);
1617 val64 = readq(&bar0->pic_control2);
1618 val64 &= ~(BIT(13)|BIT(14)|BIT(15));
1619 writeq(val64, &bar0->pic_control2);
1621 if (strstr(nic->product_name, "CX4")) {
1622 val64 = TMAC_AVG_IPG(0x17);
1623 writeq(val64, &bar0->tmac_avg_ipg);
1628 #define LINK_UP_DOWN_INTERRUPT 1
1629 #define MAC_RMAC_ERR_TIMER 2
1631 static int s2io_link_fault_indication(nic_t *nic)
1633 if (nic->intr_type != INTA)
1634 return MAC_RMAC_ERR_TIMER;
1635 if (nic->device_type == XFRAME_II_DEVICE)
1636 return LINK_UP_DOWN_INTERRUPT;
1638 return MAC_RMAC_ERR_TIMER;
1642 * en_dis_able_nic_intrs - Enable or Disable the interrupts
1643 * @nic: device private variable,
1644 * @mask: A mask indicating which Intr block must be modified and,
1645 * @flag: A flag indicating whether to enable or disable the Intrs.
1646 * Description: This function will either disable or enable the interrupts
1647 * depending on the flag argument. The mask argument can be used to
1648 * enable/disable any Intr block.
1649 * Return Value: NONE.
1652 static void en_dis_able_nic_intrs(struct s2io_nic *nic, u16 mask, int flag)
1654 XENA_dev_config_t __iomem *bar0 = nic->bar0;
1655 register u64 val64 = 0, temp64 = 0;
1657 /* Top level interrupt classification */
1658 /* PIC Interrupts */
1659 if ((mask & (TX_PIC_INTR | RX_PIC_INTR))) {
1660 /* Enable PIC Intrs in the general intr mask register */
1661 val64 = TXPIC_INT_M | PIC_RX_INT_M;
1662 if (flag == ENABLE_INTRS) {
1663 temp64 = readq(&bar0->general_int_mask);
1664 temp64 &= ~((u64) val64);
1665 writeq(temp64, &bar0->general_int_mask);
1667 * If Hercules adapter enable GPIO otherwise
1668 * disable all PCIX, Flash, MDIO, IIC and GPIO
1669 * interrupts for now.
1672 if (s2io_link_fault_indication(nic) ==
1673 LINK_UP_DOWN_INTERRUPT ) {
1674 temp64 = readq(&bar0->pic_int_mask);
1675 temp64 &= ~((u64) PIC_INT_GPIO);
1676 writeq(temp64, &bar0->pic_int_mask);
1677 temp64 = readq(&bar0->gpio_int_mask);
1678 temp64 &= ~((u64) GPIO_INT_MASK_LINK_UP);
1679 writeq(temp64, &bar0->gpio_int_mask);
1681 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
1684 * No MSI Support is available presently, so TTI and
1685 * RTI interrupts are also disabled.
1687 } else if (flag == DISABLE_INTRS) {
1689 * Disable PIC Intrs in the general
1690 * intr mask register
1692 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
1693 temp64 = readq(&bar0->general_int_mask);
1695 writeq(val64, &bar0->general_int_mask);
1699 /* DMA Interrupts */
1700 /* Enabling/Disabling Tx DMA interrupts */
1701 if (mask & TX_DMA_INTR) {
1702 /* Enable TxDMA Intrs in the general intr mask register */
1703 val64 = TXDMA_INT_M;
1704 if (flag == ENABLE_INTRS) {
1705 temp64 = readq(&bar0->general_int_mask);
1706 temp64 &= ~((u64) val64);
1707 writeq(temp64, &bar0->general_int_mask);
1709 * Keep all interrupts other than PFC interrupt
1710 * and PCC interrupt disabled in DMA level.
1712 val64 = DISABLE_ALL_INTRS & ~(TXDMA_PFC_INT_M |
1714 writeq(val64, &bar0->txdma_int_mask);
1716 * Enable only the MISC error 1 interrupt in PFC block
1718 val64 = DISABLE_ALL_INTRS & (~PFC_MISC_ERR_1);
1719 writeq(val64, &bar0->pfc_err_mask);
1721 * Enable only the FB_ECC error interrupt in PCC block
1723 val64 = DISABLE_ALL_INTRS & (~PCC_FB_ECC_ERR);
1724 writeq(val64, &bar0->pcc_err_mask);
1725 } else if (flag == DISABLE_INTRS) {
1727 * Disable TxDMA Intrs in the general intr mask
1730 writeq(DISABLE_ALL_INTRS, &bar0->txdma_int_mask);
1731 writeq(DISABLE_ALL_INTRS, &bar0->pfc_err_mask);
1732 temp64 = readq(&bar0->general_int_mask);
1734 writeq(val64, &bar0->general_int_mask);
1738 /* Enabling/Disabling Rx DMA interrupts */
1739 if (mask & RX_DMA_INTR) {
1740 /* Enable RxDMA Intrs in the general intr mask register */
1741 val64 = RXDMA_INT_M;
1742 if (flag == ENABLE_INTRS) {
1743 temp64 = readq(&bar0->general_int_mask);
1744 temp64 &= ~((u64) val64);
1745 writeq(temp64, &bar0->general_int_mask);
1747 * All RxDMA block interrupts are disabled for now
1750 writeq(DISABLE_ALL_INTRS, &bar0->rxdma_int_mask);
1751 } else if (flag == DISABLE_INTRS) {
1753 * Disable RxDMA Intrs in the general intr mask
1756 writeq(DISABLE_ALL_INTRS, &bar0->rxdma_int_mask);
1757 temp64 = readq(&bar0->general_int_mask);
1759 writeq(val64, &bar0->general_int_mask);
1763 /* MAC Interrupts */
1764 /* Enabling/Disabling MAC interrupts */
1765 if (mask & (TX_MAC_INTR | RX_MAC_INTR)) {
1766 val64 = TXMAC_INT_M | RXMAC_INT_M;
1767 if (flag == ENABLE_INTRS) {
1768 temp64 = readq(&bar0->general_int_mask);
1769 temp64 &= ~((u64) val64);
1770 writeq(temp64, &bar0->general_int_mask);
1772 * All MAC block error interrupts are disabled for now
1775 } else if (flag == DISABLE_INTRS) {
1777 * Disable MAC Intrs in the general intr mask register
1779 writeq(DISABLE_ALL_INTRS, &bar0->mac_int_mask);
1780 writeq(DISABLE_ALL_INTRS,
1781 &bar0->mac_rmac_err_mask);
1783 temp64 = readq(&bar0->general_int_mask);
1785 writeq(val64, &bar0->general_int_mask);
1789 /* XGXS Interrupts */
1790 if (mask & (TX_XGXS_INTR | RX_XGXS_INTR)) {
1791 val64 = TXXGXS_INT_M | RXXGXS_INT_M;
1792 if (flag == ENABLE_INTRS) {
1793 temp64 = readq(&bar0->general_int_mask);
1794 temp64 &= ~((u64) val64);
1795 writeq(temp64, &bar0->general_int_mask);
1797 * All XGXS block error interrupts are disabled for now
1800 writeq(DISABLE_ALL_INTRS, &bar0->xgxs_int_mask);
1801 } else if (flag == DISABLE_INTRS) {
1803 * Disable MC Intrs in the general intr mask register
1805 writeq(DISABLE_ALL_INTRS, &bar0->xgxs_int_mask);
1806 temp64 = readq(&bar0->general_int_mask);
1808 writeq(val64, &bar0->general_int_mask);
1812 /* Memory Controller(MC) interrupts */
1813 if (mask & MC_INTR) {
1815 if (flag == ENABLE_INTRS) {
1816 temp64 = readq(&bar0->general_int_mask);
1817 temp64 &= ~((u64) val64);
1818 writeq(temp64, &bar0->general_int_mask);
1820 * Enable all MC Intrs.
1822 writeq(0x0, &bar0->mc_int_mask);
1823 writeq(0x0, &bar0->mc_err_mask);
1824 } else if (flag == DISABLE_INTRS) {
1826 * Disable MC Intrs in the general intr mask register
1828 writeq(DISABLE_ALL_INTRS, &bar0->mc_int_mask);
1829 temp64 = readq(&bar0->general_int_mask);
1831 writeq(val64, &bar0->general_int_mask);
1836 /* Tx traffic interrupts */
1837 if (mask & TX_TRAFFIC_INTR) {
1838 val64 = TXTRAFFIC_INT_M;
1839 if (flag == ENABLE_INTRS) {
1840 temp64 = readq(&bar0->general_int_mask);
1841 temp64 &= ~((u64) val64);
1842 writeq(temp64, &bar0->general_int_mask);
1844 * Enable all the Tx side interrupts
1845 * writing 0 Enables all 64 TX interrupt levels
1847 writeq(0x0, &bar0->tx_traffic_mask);
1848 } else if (flag == DISABLE_INTRS) {
1850 * Disable Tx Traffic Intrs in the general intr mask
1853 writeq(DISABLE_ALL_INTRS, &bar0->tx_traffic_mask);
1854 temp64 = readq(&bar0->general_int_mask);
1856 writeq(val64, &bar0->general_int_mask);
1860 /* Rx traffic interrupts */
1861 if (mask & RX_TRAFFIC_INTR) {
1862 val64 = RXTRAFFIC_INT_M;
1863 if (flag == ENABLE_INTRS) {
1864 temp64 = readq(&bar0->general_int_mask);
1865 temp64 &= ~((u64) val64);
1866 writeq(temp64, &bar0->general_int_mask);
1867 /* writing 0 Enables all 8 RX interrupt levels */
1868 writeq(0x0, &bar0->rx_traffic_mask);
1869 } else if (flag == DISABLE_INTRS) {
1871 * Disable Rx Traffic Intrs in the general intr mask
1874 writeq(DISABLE_ALL_INTRS, &bar0->rx_traffic_mask);
1875 temp64 = readq(&bar0->general_int_mask);
1877 writeq(val64, &bar0->general_int_mask);
1883 * verify_pcc_quiescent- Checks for PCC quiescent state
1884 * Return: 1 If PCC is quiescence
1885 * 0 If PCC is not quiescence
1887 static int verify_pcc_quiescent(nic_t *sp, int flag)
1890 XENA_dev_config_t __iomem *bar0 = sp->bar0;
1891 u64 val64 = readq(&bar0->adapter_status);
1893 herc = (sp->device_type == XFRAME_II_DEVICE);
1895 if (flag == FALSE) {
1896 if ((!herc && (get_xena_rev_id(sp->pdev) >= 4)) || herc) {
1897 if (!(val64 & ADAPTER_STATUS_RMAC_PCC_IDLE))
1900 if (!(val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))
1904 if ((!herc && (get_xena_rev_id(sp->pdev) >= 4)) || herc) {
1905 if (((val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) ==
1906 ADAPTER_STATUS_RMAC_PCC_IDLE))
1909 if (((val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) ==
1910 ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))
1918 * verify_xena_quiescence - Checks whether the H/W is ready
1919 * Description: Returns whether the H/W is ready to go or not. Depending
1920 * on whether adapter enable bit was written or not the comparison
1921 * differs and the calling function passes the input argument flag to
1923 * Return: 1 If xena is quiescence
1924 * 0 If Xena is not quiescence
1927 static int verify_xena_quiescence(nic_t *sp)
1930 XENA_dev_config_t __iomem *bar0 = sp->bar0;
1931 u64 val64 = readq(&bar0->adapter_status);
1932 mode = s2io_verify_pci_mode(sp);
1934 if (!(val64 & ADAPTER_STATUS_TDMA_READY)) {
1935 DBG_PRINT(ERR_DBG, "%s", "TDMA is not ready!");
1938 if (!(val64 & ADAPTER_STATUS_RDMA_READY)) {
1939 DBG_PRINT(ERR_DBG, "%s", "RDMA is not ready!");
1942 if (!(val64 & ADAPTER_STATUS_PFC_READY)) {
1943 DBG_PRINT(ERR_DBG, "%s", "PFC is not ready!");
1946 if (!(val64 & ADAPTER_STATUS_TMAC_BUF_EMPTY)) {
1947 DBG_PRINT(ERR_DBG, "%s", "TMAC BUF is not empty!");
1950 if (!(val64 & ADAPTER_STATUS_PIC_QUIESCENT)) {
1951 DBG_PRINT(ERR_DBG, "%s", "PIC is not QUIESCENT!");
1954 if (!(val64 & ADAPTER_STATUS_MC_DRAM_READY)) {
1955 DBG_PRINT(ERR_DBG, "%s", "MC_DRAM is not ready!");
1958 if (!(val64 & ADAPTER_STATUS_MC_QUEUES_READY)) {
1959 DBG_PRINT(ERR_DBG, "%s", "MC_QUEUES is not ready!");
1962 if (!(val64 & ADAPTER_STATUS_M_PLL_LOCK)) {
1963 DBG_PRINT(ERR_DBG, "%s", "M_PLL is not locked!");
1968 * In PCI 33 mode, the P_PLL is not used, and therefore,
1969 * the the P_PLL_LOCK bit in the adapter_status register will
1972 if (!(val64 & ADAPTER_STATUS_P_PLL_LOCK) &&
1973 sp->device_type == XFRAME_II_DEVICE && mode !=
1975 DBG_PRINT(ERR_DBG, "%s", "P_PLL is not locked!");
1978 if (!((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
1979 ADAPTER_STATUS_RC_PRC_QUIESCENT)) {
1980 DBG_PRINT(ERR_DBG, "%s", "RC_PRC is not QUIESCENT!");
1987 * fix_mac_address - Fix for Mac addr problem on Alpha platforms
1988 * @sp: Pointer to device specifc structure
1990 * New procedure to clear mac address reading problems on Alpha platforms
1994 static void fix_mac_address(nic_t * sp)
1996 XENA_dev_config_t __iomem *bar0 = sp->bar0;
2000 while (fix_mac[i] != END_SIGN) {
2001 writeq(fix_mac[i++], &bar0->gpio_control);
2003 val64 = readq(&bar0->gpio_control);
2008 * start_nic - Turns the device on
2009 * @nic : device private variable.
2011 * This function actually turns the device on. Before this function is
2012 * called,all Registers are configured from their reset states
2013 * and shared memory is allocated but the NIC is still quiescent. On
2014 * calling this function, the device interrupts are cleared and the NIC is
2015 * literally switched on by writing into the adapter control register.
2017 * SUCCESS on success and -1 on failure.
2020 static int start_nic(struct s2io_nic *nic)
2022 XENA_dev_config_t __iomem *bar0 = nic->bar0;
2023 struct net_device *dev = nic->dev;
2024 register u64 val64 = 0;
2026 mac_info_t *mac_control;
2027 struct config_param *config;
2029 mac_control = &nic->mac_control;
2030 config = &nic->config;
2032 /* PRC Initialization and configuration */
2033 for (i = 0; i < config->rx_ring_num; i++) {
2034 writeq((u64) mac_control->rings[i].rx_blocks[0].block_dma_addr,
2035 &bar0->prc_rxd0_n[i]);
2037 val64 = readq(&bar0->prc_ctrl_n[i]);
2038 if (nic->config.bimodal)
2039 val64 |= PRC_CTRL_BIMODAL_INTERRUPT;
2040 if (nic->rxd_mode == RXD_MODE_1)
2041 val64 |= PRC_CTRL_RC_ENABLED;
2043 val64 |= PRC_CTRL_RC_ENABLED | PRC_CTRL_RING_MODE_3;
2044 if (nic->device_type == XFRAME_II_DEVICE)
2045 val64 |= PRC_CTRL_GROUP_READS;
2046 val64 &= ~PRC_CTRL_RXD_BACKOFF_INTERVAL(0xFFFFFF);
2047 val64 |= PRC_CTRL_RXD_BACKOFF_INTERVAL(0x1000);
2048 writeq(val64, &bar0->prc_ctrl_n[i]);
2051 if (nic->rxd_mode == RXD_MODE_3B) {
2052 /* Enabling 2 buffer mode by writing into Rx_pa_cfg reg. */
2053 val64 = readq(&bar0->rx_pa_cfg);
2054 val64 |= RX_PA_CFG_IGNORE_L2_ERR;
2055 writeq(val64, &bar0->rx_pa_cfg);
2059 * Enabling MC-RLDRAM. After enabling the device, we timeout
2060 * for around 100ms, which is approximately the time required
2061 * for the device to be ready for operation.
2063 val64 = readq(&bar0->mc_rldram_mrs);
2064 val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE | MC_RLDRAM_MRS_ENABLE;
2065 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
2066 val64 = readq(&bar0->mc_rldram_mrs);
2068 msleep(100); /* Delay by around 100 ms. */
2070 /* Enabling ECC Protection. */
2071 val64 = readq(&bar0->adapter_control);
2072 val64 &= ~ADAPTER_ECC_EN;
2073 writeq(val64, &bar0->adapter_control);
2076 * Clearing any possible Link state change interrupts that
2077 * could have popped up just before Enabling the card.
2079 val64 = readq(&bar0->mac_rmac_err_reg);
2081 writeq(val64, &bar0->mac_rmac_err_reg);
2084 * Verify if the device is ready to be enabled, if so enable
2087 val64 = readq(&bar0->adapter_status);
2088 if (!verify_xena_quiescence(nic)) {
2089 DBG_PRINT(ERR_DBG, "%s: device is not ready, ", dev->name);
2090 DBG_PRINT(ERR_DBG, "Adapter status reads: 0x%llx\n",
2091 (unsigned long long) val64);
2096 * With some switches, link might be already up at this point.
2097 * Because of this weird behavior, when we enable laser,
2098 * we may not get link. We need to handle this. We cannot
2099 * figure out which switch is misbehaving. So we are forced to
2100 * make a global change.
2103 /* Enabling Laser. */
2104 val64 = readq(&bar0->adapter_control);
2105 val64 |= ADAPTER_EOI_TX_ON;
2106 writeq(val64, &bar0->adapter_control);
2108 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
2110 * Dont see link state interrupts initally on some switches,
2111 * so directly scheduling the link state task here.
2113 schedule_work(&nic->set_link_task);
2115 /* SXE-002: Initialize link and activity LED */
2116 subid = nic->pdev->subsystem_device;
2117 if (((subid & 0xFF) >= 0x07) &&
2118 (nic->device_type == XFRAME_I_DEVICE)) {
2119 val64 = readq(&bar0->gpio_control);
2120 val64 |= 0x0000800000000000ULL;
2121 writeq(val64, &bar0->gpio_control);
2122 val64 = 0x0411040400000000ULL;
2123 writeq(val64, (void __iomem *)bar0 + 0x2700);
2129 * s2io_txdl_getskb - Get the skb from txdl, unmap and return skb
2131 static struct sk_buff *s2io_txdl_getskb(fifo_info_t *fifo_data, TxD_t *txdlp, int get_off)
2133 nic_t *nic = fifo_data->nic;
2134 struct sk_buff *skb;
2139 if (txds->Host_Control == (u64)(long)nic->ufo_in_band_v) {
2140 pci_unmap_single(nic->pdev, (dma_addr_t)
2141 txds->Buffer_Pointer, sizeof(u64),
2146 skb = (struct sk_buff *) ((unsigned long)
2147 txds->Host_Control);
2149 memset(txdlp, 0, (sizeof(TxD_t) * fifo_data->max_txds));
2152 pci_unmap_single(nic->pdev, (dma_addr_t)
2153 txds->Buffer_Pointer,
2154 skb->len - skb->data_len,
2156 frg_cnt = skb_shinfo(skb)->nr_frags;
2159 for (j = 0; j < frg_cnt; j++, txds++) {
2160 skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
2161 if (!txds->Buffer_Pointer)
2163 pci_unmap_page(nic->pdev, (dma_addr_t)
2164 txds->Buffer_Pointer,
2165 frag->size, PCI_DMA_TODEVICE);
2168 memset(txdlp,0, (sizeof(TxD_t) * fifo_data->max_txds));
2173 * free_tx_buffers - Free all queued Tx buffers
2174 * @nic : device private variable.
2176 * Free all queued Tx buffers.
2177 * Return Value: void
2180 static void free_tx_buffers(struct s2io_nic *nic)
2182 struct net_device *dev = nic->dev;
2183 struct sk_buff *skb;
2186 mac_info_t *mac_control;
2187 struct config_param *config;
2190 mac_control = &nic->mac_control;
2191 config = &nic->config;
2193 for (i = 0; i < config->tx_fifo_num; i++) {
2194 for (j = 0; j < config->tx_cfg[i].fifo_len - 1; j++) {
2195 txdp = (TxD_t *) mac_control->fifos[i].list_info[j].
2197 skb = s2io_txdl_getskb(&mac_control->fifos[i], txdp, j);
2204 "%s:forcibly freeing %d skbs on FIFO%d\n",
2206 mac_control->fifos[i].tx_curr_get_info.offset = 0;
2207 mac_control->fifos[i].tx_curr_put_info.offset = 0;
2212 * stop_nic - To stop the nic
2213 * @nic ; device private variable.
2215 * This function does exactly the opposite of what the start_nic()
2216 * function does. This function is called to stop the device.
2221 static void stop_nic(struct s2io_nic *nic)
2223 XENA_dev_config_t __iomem *bar0 = nic->bar0;
2224 register u64 val64 = 0;
2226 mac_info_t *mac_control;
2227 struct config_param *config;
2229 mac_control = &nic->mac_control;
2230 config = &nic->config;
2232 /* Disable all interrupts */
2233 interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
2234 interruptible |= TX_PIC_INTR | RX_PIC_INTR;
2235 interruptible |= TX_MAC_INTR | RX_MAC_INTR;
2236 en_dis_able_nic_intrs(nic, interruptible, DISABLE_INTRS);
2238 /* Clearing Adapter_En bit of ADAPTER_CONTROL Register */
2239 val64 = readq(&bar0->adapter_control);
2240 val64 &= ~(ADAPTER_CNTL_EN);
2241 writeq(val64, &bar0->adapter_control);
2244 static int fill_rxd_3buf(nic_t *nic, RxD_t *rxdp, struct sk_buff *skb)
2246 struct net_device *dev = nic->dev;
2247 struct sk_buff *frag_list;
2250 /* Buffer-1 receives L3/L4 headers */
2251 ((RxD3_t*)rxdp)->Buffer1_ptr = pci_map_single
2252 (nic->pdev, skb->data, l3l4hdr_size + 4,
2253 PCI_DMA_FROMDEVICE);
2255 /* skb_shinfo(skb)->frag_list will have L4 data payload */
2256 skb_shinfo(skb)->frag_list = dev_alloc_skb(dev->mtu + ALIGN_SIZE);
2257 if (skb_shinfo(skb)->frag_list == NULL) {
2258 DBG_PRINT(ERR_DBG, "%s: dev_alloc_skb failed\n ", dev->name);
2261 frag_list = skb_shinfo(skb)->frag_list;
2262 skb->truesize += frag_list->truesize;
2263 frag_list->next = NULL;
2264 tmp = (void *)ALIGN((long)frag_list->data, ALIGN_SIZE + 1);
2265 frag_list->data = tmp;
2266 frag_list->tail = tmp;
2268 /* Buffer-2 receives L4 data payload */
2269 ((RxD3_t*)rxdp)->Buffer2_ptr = pci_map_single(nic->pdev,
2270 frag_list->data, dev->mtu,
2271 PCI_DMA_FROMDEVICE);
2272 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(l3l4hdr_size + 4);
2273 rxdp->Control_2 |= SET_BUFFER2_SIZE_3(dev->mtu);
2279 * fill_rx_buffers - Allocates the Rx side skbs
2280 * @nic: device private variable
2281 * @ring_no: ring number
2283 * The function allocates Rx side skbs and puts the physical
2284 * address of these buffers into the RxD buffer pointers, so that the NIC
2285 * can DMA the received frame into these locations.
2286 * The NIC supports 3 receive modes, viz
2288 * 2. three buffer and
2289 * 3. Five buffer modes.
2290 * Each mode defines how many fragments the received frame will be split
2291 * up into by the NIC. The frame is split into L3 header, L4 Header,
2292 * L4 payload in three buffer mode and in 5 buffer mode, L4 payload itself
2293 * is split into 3 fragments. As of now only single buffer mode is
2296 * SUCCESS on success or an appropriate -ve value on failure.
2299 static int fill_rx_buffers(struct s2io_nic *nic, int ring_no)
2301 struct net_device *dev = nic->dev;
2302 struct sk_buff *skb;
2304 int off, off1, size, block_no, block_no1;
2307 mac_info_t *mac_control;
2308 struct config_param *config;
2311 unsigned long flags;
2312 RxD_t *first_rxdp = NULL;
2314 mac_control = &nic->mac_control;
2315 config = &nic->config;
2316 alloc_cnt = mac_control->rings[ring_no].pkt_cnt -
2317 atomic_read(&nic->rx_bufs_left[ring_no]);
2319 block_no1 = mac_control->rings[ring_no].rx_curr_get_info.block_index;
2320 off1 = mac_control->rings[ring_no].rx_curr_get_info.offset;
2321 while (alloc_tab < alloc_cnt) {
2322 block_no = mac_control->rings[ring_no].rx_curr_put_info.
2324 off = mac_control->rings[ring_no].rx_curr_put_info.offset;
2326 rxdp = mac_control->rings[ring_no].
2327 rx_blocks[block_no].rxds[off].virt_addr;
2329 if ((block_no == block_no1) && (off == off1) &&
2330 (rxdp->Host_Control)) {
2331 DBG_PRINT(INTR_DBG, "%s: Get and Put",
2333 DBG_PRINT(INTR_DBG, " info equated\n");
2336 if (off && (off == rxd_count[nic->rxd_mode])) {
2337 mac_control->rings[ring_no].rx_curr_put_info.
2339 if (mac_control->rings[ring_no].rx_curr_put_info.
2340 block_index == mac_control->rings[ring_no].
2342 mac_control->rings[ring_no].rx_curr_put_info.
2344 block_no = mac_control->rings[ring_no].
2345 rx_curr_put_info.block_index;
2346 if (off == rxd_count[nic->rxd_mode])
2348 mac_control->rings[ring_no].rx_curr_put_info.
2350 rxdp = mac_control->rings[ring_no].
2351 rx_blocks[block_no].block_virt_addr;
2352 DBG_PRINT(INTR_DBG, "%s: Next block at: %p\n",
2356 spin_lock_irqsave(&nic->put_lock, flags);
2357 mac_control->rings[ring_no].put_pos =
2358 (block_no * (rxd_count[nic->rxd_mode] + 1)) + off;
2359 spin_unlock_irqrestore(&nic->put_lock, flags);
2361 mac_control->rings[ring_no].put_pos =
2362 (block_no * (rxd_count[nic->rxd_mode] + 1)) + off;
2364 if ((rxdp->Control_1 & RXD_OWN_XENA) &&
2365 ((nic->rxd_mode >= RXD_MODE_3A) &&
2366 (rxdp->Control_2 & BIT(0)))) {
2367 mac_control->rings[ring_no].rx_curr_put_info.
2371 /* calculate size of skb based on ring mode */
2372 size = dev->mtu + HEADER_ETHERNET_II_802_3_SIZE +
2373 HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
2374 if (nic->rxd_mode == RXD_MODE_1)
2375 size += NET_IP_ALIGN;
2376 else if (nic->rxd_mode == RXD_MODE_3B)
2377 size = dev->mtu + ALIGN_SIZE + BUF0_LEN + 4;
2379 size = l3l4hdr_size + ALIGN_SIZE + BUF0_LEN + 4;
2382 skb = dev_alloc_skb(size);
2384 DBG_PRINT(ERR_DBG, "%s: Out of ", dev->name);
2385 DBG_PRINT(ERR_DBG, "memory to allocate SKBs\n");
2388 first_rxdp->Control_1 |= RXD_OWN_XENA;
2392 if (nic->rxd_mode == RXD_MODE_1) {
2393 /* 1 buffer mode - normal operation mode */
2394 memset(rxdp, 0, sizeof(RxD1_t));
2395 skb_reserve(skb, NET_IP_ALIGN);
2396 ((RxD1_t*)rxdp)->Buffer0_ptr = pci_map_single
2397 (nic->pdev, skb->data, size - NET_IP_ALIGN,
2398 PCI_DMA_FROMDEVICE);
2399 rxdp->Control_2 = SET_BUFFER0_SIZE_1(size - NET_IP_ALIGN);
2401 } else if (nic->rxd_mode >= RXD_MODE_3A) {
2403 * 2 or 3 buffer mode -
2404 * Both 2 buffer mode and 3 buffer mode provides 128
2405 * byte aligned receive buffers.
2407 * 3 buffer mode provides header separation where in
2408 * skb->data will have L3/L4 headers where as
2409 * skb_shinfo(skb)->frag_list will have the L4 data
2413 memset(rxdp, 0, sizeof(RxD3_t));
2414 ba = &mac_control->rings[ring_no].ba[block_no][off];
2415 skb_reserve(skb, BUF0_LEN);
2416 tmp = (u64)(unsigned long) skb->data;
2419 skb->data = (void *) (unsigned long)tmp;
2420 skb->tail = (void *) (unsigned long)tmp;
2422 if (!(((RxD3_t*)rxdp)->Buffer0_ptr))
2423 ((RxD3_t*)rxdp)->Buffer0_ptr =
2424 pci_map_single(nic->pdev, ba->ba_0, BUF0_LEN,
2425 PCI_DMA_FROMDEVICE);
2427 pci_dma_sync_single_for_device(nic->pdev,
2428 (dma_addr_t) ((RxD3_t*)rxdp)->Buffer0_ptr,
2429 BUF0_LEN, PCI_DMA_FROMDEVICE);
2430 rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
2431 if (nic->rxd_mode == RXD_MODE_3B) {
2432 /* Two buffer mode */
2435 * Buffer2 will have L3/L4 header plus
2438 ((RxD3_t*)rxdp)->Buffer2_ptr = pci_map_single
2439 (nic->pdev, skb->data, dev->mtu + 4,
2440 PCI_DMA_FROMDEVICE);
2442 /* Buffer-1 will be dummy buffer. Not used */
2443 if (!(((RxD3_t*)rxdp)->Buffer1_ptr)) {
2444 ((RxD3_t*)rxdp)->Buffer1_ptr =
2445 pci_map_single(nic->pdev,
2447 PCI_DMA_FROMDEVICE);
2449 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
2450 rxdp->Control_2 |= SET_BUFFER2_SIZE_3
2454 if (fill_rxd_3buf(nic, rxdp, skb) == -ENOMEM) {
2455 dev_kfree_skb_irq(skb);
2458 first_rxdp->Control_1 |=
2464 rxdp->Control_2 |= BIT(0);
2466 rxdp->Host_Control = (unsigned long) (skb);
2467 if (alloc_tab & ((1 << rxsync_frequency) - 1))
2468 rxdp->Control_1 |= RXD_OWN_XENA;
2470 if (off == (rxd_count[nic->rxd_mode] + 1))
2472 mac_control->rings[ring_no].rx_curr_put_info.offset = off;
2474 rxdp->Control_2 |= SET_RXD_MARKER;
2475 if (!(alloc_tab & ((1 << rxsync_frequency) - 1))) {
2478 first_rxdp->Control_1 |= RXD_OWN_XENA;
2482 atomic_inc(&nic->rx_bufs_left[ring_no]);
2487 /* Transfer ownership of first descriptor to adapter just before
2488 * exiting. Before that, use memory barrier so that ownership
2489 * and other fields are seen by adapter correctly.
2493 first_rxdp->Control_1 |= RXD_OWN_XENA;
2499 static void free_rxd_blk(struct s2io_nic *sp, int ring_no, int blk)
2501 struct net_device *dev = sp->dev;
2503 struct sk_buff *skb;
2505 mac_info_t *mac_control;
2508 mac_control = &sp->mac_control;
2509 for (j = 0 ; j < rxd_count[sp->rxd_mode]; j++) {
2510 rxdp = mac_control->rings[ring_no].
2511 rx_blocks[blk].rxds[j].virt_addr;
2512 skb = (struct sk_buff *)
2513 ((unsigned long) rxdp->Host_Control);
2517 if (sp->rxd_mode == RXD_MODE_1) {
2518 pci_unmap_single(sp->pdev, (dma_addr_t)
2519 ((RxD1_t*)rxdp)->Buffer0_ptr,
2521 HEADER_ETHERNET_II_802_3_SIZE
2522 + HEADER_802_2_SIZE +
2524 PCI_DMA_FROMDEVICE);
2525 memset(rxdp, 0, sizeof(RxD1_t));
2526 } else if(sp->rxd_mode == RXD_MODE_3B) {
2527 ba = &mac_control->rings[ring_no].
2529 pci_unmap_single(sp->pdev, (dma_addr_t)
2530 ((RxD3_t*)rxdp)->Buffer0_ptr,
2532 PCI_DMA_FROMDEVICE);
2533 pci_unmap_single(sp->pdev, (dma_addr_t)
2534 ((RxD3_t*)rxdp)->Buffer1_ptr,
2536 PCI_DMA_FROMDEVICE);
2537 pci_unmap_single(sp->pdev, (dma_addr_t)
2538 ((RxD3_t*)rxdp)->Buffer2_ptr,
2540 PCI_DMA_FROMDEVICE);
2541 memset(rxdp, 0, sizeof(RxD3_t));
2543 pci_unmap_single(sp->pdev, (dma_addr_t)
2544 ((RxD3_t*)rxdp)->Buffer0_ptr, BUF0_LEN,
2545 PCI_DMA_FROMDEVICE);
2546 pci_unmap_single(sp->pdev, (dma_addr_t)
2547 ((RxD3_t*)rxdp)->Buffer1_ptr,
2549 PCI_DMA_FROMDEVICE);
2550 pci_unmap_single(sp->pdev, (dma_addr_t)
2551 ((RxD3_t*)rxdp)->Buffer2_ptr, dev->mtu,
2552 PCI_DMA_FROMDEVICE);
2553 memset(rxdp, 0, sizeof(RxD3_t));
2556 atomic_dec(&sp->rx_bufs_left[ring_no]);
2561 * free_rx_buffers - Frees all Rx buffers
2562 * @sp: device private variable.
2564 * This function will free all Rx buffers allocated by host.
2569 static void free_rx_buffers(struct s2io_nic *sp)
2571 struct net_device *dev = sp->dev;
2572 int i, blk = 0, buf_cnt = 0;
2573 mac_info_t *mac_control;
2574 struct config_param *config;
2576 mac_control = &sp->mac_control;
2577 config = &sp->config;
2579 for (i = 0; i < config->rx_ring_num; i++) {
2580 for (blk = 0; blk < rx_ring_sz[i]; blk++)
2581 free_rxd_blk(sp,i,blk);
2583 mac_control->rings[i].rx_curr_put_info.block_index = 0;
2584 mac_control->rings[i].rx_curr_get_info.block_index = 0;
2585 mac_control->rings[i].rx_curr_put_info.offset = 0;
2586 mac_control->rings[i].rx_curr_get_info.offset = 0;
2587 atomic_set(&sp->rx_bufs_left[i], 0);
2588 DBG_PRINT(INIT_DBG, "%s:Freed 0x%x Rx Buffers on ring%d\n",
2589 dev->name, buf_cnt, i);
2594 * s2io_poll - Rx interrupt handler for NAPI support
2595 * @dev : pointer to the device structure.
2596 * @budget : The number of packets that were budgeted to be processed
2597 * during one pass through the 'Poll" function.
2599 * Comes into picture only if NAPI support has been incorporated. It does
2600 * the same thing that rx_intr_handler does, but not in a interrupt context
2601 * also It will process only a given number of packets.
2603 * 0 on success and 1 if there are No Rx packets to be processed.
2606 static int s2io_poll(struct net_device *dev, int *budget)
2608 nic_t *nic = dev->priv;
2609 int pkt_cnt = 0, org_pkts_to_process;
2610 mac_info_t *mac_control;
2611 struct config_param *config;
2612 XENA_dev_config_t __iomem *bar0 = nic->bar0;
2615 atomic_inc(&nic->isr_cnt);
2616 mac_control = &nic->mac_control;
2617 config = &nic->config;
2619 nic->pkts_to_process = *budget;
2620 if (nic->pkts_to_process > dev->quota)
2621 nic->pkts_to_process = dev->quota;
2622 org_pkts_to_process = nic->pkts_to_process;
2624 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
2625 readl(&bar0->rx_traffic_int);
2627 for (i = 0; i < config->rx_ring_num; i++) {
2628 rx_intr_handler(&mac_control->rings[i]);
2629 pkt_cnt = org_pkts_to_process - nic->pkts_to_process;
2630 if (!nic->pkts_to_process) {
2631 /* Quota for the current iteration has been met */
2638 dev->quota -= pkt_cnt;
2640 netif_rx_complete(dev);
2642 for (i = 0; i < config->rx_ring_num; i++) {
2643 if (fill_rx_buffers(nic, i) == -ENOMEM) {
2644 DBG_PRINT(ERR_DBG, "%s:Out of memory", dev->name);
2645 DBG_PRINT(ERR_DBG, " in Rx Poll!!\n");
2649 /* Re enable the Rx interrupts. */
2650 writeq(0x0, &bar0->rx_traffic_mask);
2651 readl(&bar0->rx_traffic_mask);
2652 atomic_dec(&nic->isr_cnt);
2656 dev->quota -= pkt_cnt;
2659 for (i = 0; i < config->rx_ring_num; i++) {
2660 if (fill_rx_buffers(nic, i) == -ENOMEM) {
2661 DBG_PRINT(ERR_DBG, "%s:Out of memory", dev->name);
2662 DBG_PRINT(ERR_DBG, " in Rx Poll!!\n");
2666 atomic_dec(&nic->isr_cnt);
2670 #ifdef CONFIG_NET_POLL_CONTROLLER
2672 * s2io_netpoll - netpoll event handler entry point
2673 * @dev : pointer to the device structure.
2675 * This function will be called by upper layer to check for events on the
2676 * interface in situations where interrupts are disabled. It is used for
2677 * specific in-kernel networking tasks, such as remote consoles and kernel
2678 * debugging over the network (example netdump in RedHat).
2680 static void s2io_netpoll(struct net_device *dev)
2682 nic_t *nic = dev->priv;
2683 mac_info_t *mac_control;
2684 struct config_param *config;
2685 XENA_dev_config_t __iomem *bar0 = nic->bar0;
2686 u64 val64 = 0xFFFFFFFFFFFFFFFFULL;
2689 disable_irq(dev->irq);
2691 atomic_inc(&nic->isr_cnt);
2692 mac_control = &nic->mac_control;
2693 config = &nic->config;
2695 writeq(val64, &bar0->rx_traffic_int);
2696 writeq(val64, &bar0->tx_traffic_int);
2698 /* we need to free up the transmitted skbufs or else netpoll will
2699 * run out of skbs and will fail and eventually netpoll application such
2700 * as netdump will fail.
2702 for (i = 0; i < config->tx_fifo_num; i++)
2703 tx_intr_handler(&mac_control->fifos[i]);
2705 /* check for received packet and indicate up to network */
2706 for (i = 0; i < config->rx_ring_num; i++)
2707 rx_intr_handler(&mac_control->rings[i]);
2709 for (i = 0; i < config->rx_ring_num; i++) {
2710 if (fill_rx_buffers(nic, i) == -ENOMEM) {
2711 DBG_PRINT(ERR_DBG, "%s:Out of memory", dev->name);
2712 DBG_PRINT(ERR_DBG, " in Rx Netpoll!!\n");
2716 atomic_dec(&nic->isr_cnt);
2717 enable_irq(dev->irq);
2723 * rx_intr_handler - Rx interrupt handler
2724 * @nic: device private variable.
2726 * If the interrupt is because of a received frame or if the
2727 * receive ring contains fresh as yet un-processed frames,this function is
2728 * called. It picks out the RxD at which place the last Rx processing had
2729 * stopped and sends the skb to the OSM's Rx handler and then increments
2734 static void rx_intr_handler(ring_info_t *ring_data)
2736 nic_t *nic = ring_data->nic;
2737 struct net_device *dev = (struct net_device *) nic->dev;
2738 int get_block, put_block, put_offset;
2739 rx_curr_get_info_t get_info, put_info;
2741 struct sk_buff *skb;
2745 spin_lock(&nic->rx_lock);
2746 if (atomic_read(&nic->card_state) == CARD_DOWN) {
2747 DBG_PRINT(INTR_DBG, "%s: %s going down for reset\n",
2748 __FUNCTION__, dev->name);
2749 spin_unlock(&nic->rx_lock);
2753 get_info = ring_data->rx_curr_get_info;
2754 get_block = get_info.block_index;
2755 put_info = ring_data->rx_curr_put_info;
2756 put_block = put_info.block_index;
2757 rxdp = ring_data->rx_blocks[get_block].rxds[get_info.offset].virt_addr;
2759 spin_lock(&nic->put_lock);
2760 put_offset = ring_data->put_pos;
2761 spin_unlock(&nic->put_lock);
2763 put_offset = ring_data->put_pos;
2765 while (RXD_IS_UP2DT(rxdp)) {
2767 * If your are next to put index then it's
2768 * FIFO full condition
2770 if ((get_block == put_block) &&
2771 (get_info.offset + 1) == put_info.offset) {
2772 DBG_PRINT(INTR_DBG, "%s: Ring Full\n",dev->name);
2775 skb = (struct sk_buff *) ((unsigned long)rxdp->Host_Control);
2777 DBG_PRINT(ERR_DBG, "%s: The skb is ",
2779 DBG_PRINT(ERR_DBG, "Null in Rx Intr\n");
2780 spin_unlock(&nic->rx_lock);
2783 if (nic->rxd_mode == RXD_MODE_1) {
2784 pci_unmap_single(nic->pdev, (dma_addr_t)
2785 ((RxD1_t*)rxdp)->Buffer0_ptr,
2787 HEADER_ETHERNET_II_802_3_SIZE +
2790 PCI_DMA_FROMDEVICE);
2791 } else if (nic->rxd_mode == RXD_MODE_3B) {
2792 pci_dma_sync_single_for_cpu(nic->pdev, (dma_addr_t)
2793 ((RxD3_t*)rxdp)->Buffer0_ptr,
2794 BUF0_LEN, PCI_DMA_FROMDEVICE);
2795 pci_unmap_single(nic->pdev, (dma_addr_t)
2796 ((RxD3_t*)rxdp)->Buffer2_ptr,
2798 PCI_DMA_FROMDEVICE);
2800 pci_dma_sync_single_for_cpu(nic->pdev, (dma_addr_t)
2801 ((RxD3_t*)rxdp)->Buffer0_ptr, BUF0_LEN,
2802 PCI_DMA_FROMDEVICE);
2803 pci_unmap_single(nic->pdev, (dma_addr_t)
2804 ((RxD3_t*)rxdp)->Buffer1_ptr,
2806 PCI_DMA_FROMDEVICE);
2807 pci_unmap_single(nic->pdev, (dma_addr_t)
2808 ((RxD3_t*)rxdp)->Buffer2_ptr,
2809 dev->mtu, PCI_DMA_FROMDEVICE);
2811 prefetch(skb->data);
2812 rx_osm_handler(ring_data, rxdp);
2814 ring_data->rx_curr_get_info.offset = get_info.offset;
2815 rxdp = ring_data->rx_blocks[get_block].
2816 rxds[get_info.offset].virt_addr;
2817 if (get_info.offset == rxd_count[nic->rxd_mode]) {
2818 get_info.offset = 0;
2819 ring_data->rx_curr_get_info.offset = get_info.offset;
2821 if (get_block == ring_data->block_count)
2823 ring_data->rx_curr_get_info.block_index = get_block;
2824 rxdp = ring_data->rx_blocks[get_block].block_virt_addr;
2827 nic->pkts_to_process -= 1;
2828 if ((napi) && (!nic->pkts_to_process))
2831 if ((indicate_max_pkts) && (pkt_cnt > indicate_max_pkts))
2835 /* Clear all LRO sessions before exiting */
2836 for (i=0; i<MAX_LRO_SESSIONS; i++) {
2837 lro_t *lro = &nic->lro0_n[i];
2839 update_L3L4_header(nic, lro);
2840 queue_rx_frame(lro->parent);
2841 clear_lro_session(lro);
2846 spin_unlock(&nic->rx_lock);
2850 * tx_intr_handler - Transmit interrupt handler
2851 * @nic : device private variable
2853 * If an interrupt was raised to indicate DMA complete of the
2854 * Tx packet, this function is called. It identifies the last TxD
2855 * whose buffer was freed and frees all skbs whose data have already
2856 * DMA'ed into the NICs internal memory.
2861 static void tx_intr_handler(fifo_info_t *fifo_data)
2863 nic_t *nic = fifo_data->nic;
2864 struct net_device *dev = (struct net_device *) nic->dev;
2865 tx_curr_get_info_t get_info, put_info;
2866 struct sk_buff *skb;
2869 get_info = fifo_data->tx_curr_get_info;
2870 put_info = fifo_data->tx_curr_put_info;
2871 txdlp = (TxD_t *) fifo_data->list_info[get_info.offset].
2873 while ((!(txdlp->Control_1 & TXD_LIST_OWN_XENA)) &&
2874 (get_info.offset != put_info.offset) &&
2875 (txdlp->Host_Control)) {
2876 /* Check for TxD errors */
2877 if (txdlp->Control_1 & TXD_T_CODE) {
2878 unsigned long long err;
2879 err = txdlp->Control_1 & TXD_T_CODE;
2881 nic->mac_control.stats_info->sw_stat.
2884 if ((err >> 48) == 0xA) {
2885 DBG_PRINT(TX_DBG, "TxD returned due \
2886 to loss of link\n");
2889 DBG_PRINT(ERR_DBG, "***TxD error %llx\n", err);
2893 skb = s2io_txdl_getskb(fifo_data, txdlp, get_info.offset);
2895 DBG_PRINT(ERR_DBG, "%s: Null skb ",
2897 DBG_PRINT(ERR_DBG, "in Tx Free Intr\n");
2901 /* Updating the statistics block */
2902 nic->stats.tx_bytes += skb->len;
2903 dev_kfree_skb_irq(skb);
2906 if (get_info.offset == get_info.fifo_len + 1)
2907 get_info.offset = 0;
2908 txdlp = (TxD_t *) fifo_data->list_info
2909 [get_info.offset].list_virt_addr;
2910 fifo_data->tx_curr_get_info.offset =
2914 spin_lock(&nic->tx_lock);
2915 if (netif_queue_stopped(dev))
2916 netif_wake_queue(dev);
2917 spin_unlock(&nic->tx_lock);
2921 * s2io_mdio_write - Function to write in to MDIO registers
2922 * @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
2923 * @addr : address value
2924 * @value : data value
2925 * @dev : pointer to net_device structure
2927 * This function is used to write values to the MDIO registers
2930 static void s2io_mdio_write(u32 mmd_type, u64 addr, u16 value, struct net_device *dev)
2933 nic_t *sp = dev->priv;
2934 XENA_dev_config_t __iomem *bar0 = sp->bar0;
2936 //address transaction
2937 val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
2938 | MDIO_MMD_DEV_ADDR(mmd_type)
2939 | MDIO_MMS_PRT_ADDR(0x0);
2940 writeq(val64, &bar0->mdio_control);
2941 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
2942 writeq(val64, &bar0->mdio_control);
2947 val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
2948 | MDIO_MMD_DEV_ADDR(mmd_type)
2949 | MDIO_MMS_PRT_ADDR(0x0)
2950 | MDIO_MDIO_DATA(value)
2951 | MDIO_OP(MDIO_OP_WRITE_TRANS);
2952 writeq(val64, &bar0->mdio_control);
2953 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
2954 writeq(val64, &bar0->mdio_control);
2958 val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
2959 | MDIO_MMD_DEV_ADDR(mmd_type)
2960 | MDIO_MMS_PRT_ADDR(0x0)
2961 | MDIO_OP(MDIO_OP_READ_TRANS);
2962 writeq(val64, &bar0->mdio_control);
2963 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
2964 writeq(val64, &bar0->mdio_control);
2970 * s2io_mdio_read - Function to write in to MDIO registers
2971 * @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
2972 * @addr : address value
2973 * @dev : pointer to net_device structure
2975 * This function is used to read values to the MDIO registers
2978 static u64 s2io_mdio_read(u32 mmd_type, u64 addr, struct net_device *dev)
2982 nic_t *sp = dev->priv;
2983 XENA_dev_config_t __iomem *bar0 = sp->bar0;
2985 /* address transaction */
2986 val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
2987 | MDIO_MMD_DEV_ADDR(mmd_type)
2988 | MDIO_MMS_PRT_ADDR(0x0);
2989 writeq(val64, &bar0->mdio_control);
2990 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
2991 writeq(val64, &bar0->mdio_control);
2994 /* Data transaction */
2996 val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
2997 | MDIO_MMD_DEV_ADDR(mmd_type)
2998 | MDIO_MMS_PRT_ADDR(0x0)
2999 | MDIO_OP(MDIO_OP_READ_TRANS);
3000 writeq(val64, &bar0->mdio_control);
3001 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3002 writeq(val64, &bar0->mdio_control);
3005 /* Read the value from regs */
3006 rval64 = readq(&bar0->mdio_control);
3007 rval64 = rval64 & 0xFFFF0000;
3008 rval64 = rval64 >> 16;
3012 * s2io_chk_xpak_counter - Function to check the status of the xpak counters
3013 * @counter : couter value to be updated
3014 * @flag : flag to indicate the status
3015 * @type : counter type
3017 * This function is to check the status of the xpak counters value
3021 static void s2io_chk_xpak_counter(u64 *counter, u64 * regs_stat, u32 index, u16 flag, u16 type)
3026 for(i = 0; i <index; i++)
3031 *counter = *counter + 1;
3032 val64 = *regs_stat & mask;
3033 val64 = val64 >> (index * 0x2);
3040 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
3041 "service. Excessive temperatures may "
3042 "result in premature transceiver "
3046 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
3047 "service Excessive bias currents may "
3048 "indicate imminent laser diode "
3052 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
3053 "service Excessive laser output "
3054 "power may saturate far-end "
3058 DBG_PRINT(ERR_DBG, "Incorrect XPAK Alarm "
3063 val64 = val64 << (index * 0x2);
3064 *regs_stat = (*regs_stat & (~mask)) | (val64);
3067 *regs_stat = *regs_stat & (~mask);
3072 * s2io_updt_xpak_counter - Function to update the xpak counters
3073 * @dev : pointer to net_device struct
3075 * This function is to upate the status of the xpak counters value
3078 static void s2io_updt_xpak_counter(struct net_device *dev)
3086 nic_t *sp = dev->priv;
3087 StatInfo_t *stat_info = sp->mac_control.stats_info;
3089 /* Check the communication with the MDIO slave */
3092 val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3093 if((val64 == 0xFFFF) || (val64 == 0x0000))
3095 DBG_PRINT(ERR_DBG, "ERR: MDIO slave access failed - "
3096 "Returned %llx\n", (unsigned long long)val64);
3100 /* Check for the expecte value of 2040 at PMA address 0x0000 */
3103 DBG_PRINT(ERR_DBG, "Incorrect value at PMA address 0x0000 - ");
3104 DBG_PRINT(ERR_DBG, "Returned: %llx- Expected: 0x2040\n",
3105 (unsigned long long)val64);
3109 /* Loading the DOM register to MDIO register */
3111 s2io_mdio_write(MDIO_MMD_PMA_DEV_ADDR, addr, val16, dev);
3112 val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3114 /* Reading the Alarm flags */
3117 val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3119 flag = CHECKBIT(val64, 0x7);
3121 s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_transceiver_temp_high,
3122 &stat_info->xpak_stat.xpak_regs_stat,
3125 if(CHECKBIT(val64, 0x6))
3126 stat_info->xpak_stat.alarm_transceiver_temp_low++;
3128 flag = CHECKBIT(val64, 0x3);
3130 s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_laser_bias_current_high,
3131 &stat_info->xpak_stat.xpak_regs_stat,
3134 if(CHECKBIT(val64, 0x2))
3135 stat_info->xpak_stat.alarm_laser_bias_current_low++;
3137 flag = CHECKBIT(val64, 0x1);
3139 s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_laser_output_power_high,
3140 &stat_info->xpak_stat.xpak_regs_stat,
3143 if(CHECKBIT(val64, 0x0))
3144 stat_info->xpak_stat.alarm_laser_output_power_low++;
3146 /* Reading the Warning flags */
3149 val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3151 if(CHECKBIT(val64, 0x7))
3152 stat_info->xpak_stat.warn_transceiver_temp_high++;
3154 if(CHECKBIT(val64, 0x6))
3155 stat_info->xpak_stat.warn_transceiver_temp_low++;
3157 if(CHECKBIT(val64, 0x3))
3158 stat_info->xpak_stat.warn_laser_bias_current_high++;
3160 if(CHECKBIT(val64, 0x2))
3161 stat_info->xpak_stat.warn_laser_bias_current_low++;
3163 if(CHECKBIT(val64, 0x1))
3164 stat_info->xpak_stat.warn_laser_output_power_high++;
3166 if(CHECKBIT(val64, 0x0))
3167 stat_info->xpak_stat.warn_laser_output_power_low++;
3171 * alarm_intr_handler - Alarm Interrrupt handler
3172 * @nic: device private variable
3173 * Description: If the interrupt was neither because of Rx packet or Tx
3174 * complete, this function is called. If the interrupt was to indicate
3175 * a loss of link, the OSM link status handler is invoked for any other
3176 * alarm interrupt the block that raised the interrupt is displayed
3177 * and a H/W reset is issued.
3182 static void alarm_intr_handler(struct s2io_nic *nic)
3184 struct net_device *dev = (struct net_device *) nic->dev;
3185 XENA_dev_config_t __iomem *bar0 = nic->bar0;
3186 register u64 val64 = 0, err_reg = 0;
3189 if (atomic_read(&nic->card_state) == CARD_DOWN)
3191 nic->mac_control.stats_info->sw_stat.ring_full_cnt = 0;
3192 /* Handling the XPAK counters update */
3193 if(nic->mac_control.stats_info->xpak_stat.xpak_timer_count < 72000) {
3194 /* waiting for an hour */
3195 nic->mac_control.stats_info->xpak_stat.xpak_timer_count++;
3197 s2io_updt_xpak_counter(dev);
3198 /* reset the count to zero */
3199 nic->mac_control.stats_info->xpak_stat.xpak_timer_count = 0;
3202 /* Handling link status change error Intr */
3203 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
3204 err_reg = readq(&bar0->mac_rmac_err_reg);
3205 writeq(err_reg, &bar0->mac_rmac_err_reg);
3206 if (err_reg & RMAC_LINK_STATE_CHANGE_INT) {
3207 schedule_work(&nic->set_link_task);
3211 /* Handling Ecc errors */
3212 val64 = readq(&bar0->mc_err_reg);
3213 writeq(val64, &bar0->mc_err_reg);
3214 if (val64 & (MC_ERR_REG_ECC_ALL_SNG | MC_ERR_REG_ECC_ALL_DBL)) {
3215 if (val64 & MC_ERR_REG_ECC_ALL_DBL) {
3216 nic->mac_control.stats_info->sw_stat.
3218 DBG_PRINT(INIT_DBG, "%s: Device indicates ",
3220 DBG_PRINT(INIT_DBG, "double ECC error!!\n");
3221 if (nic->device_type != XFRAME_II_DEVICE) {
3222 /* Reset XframeI only if critical error */
3223 if (val64 & (MC_ERR_REG_MIRI_ECC_DB_ERR_0 |
3224 MC_ERR_REG_MIRI_ECC_DB_ERR_1)) {
3225 netif_stop_queue(dev);
3226 schedule_work(&nic->rst_timer_task);
3227 nic->mac_control.stats_info->sw_stat.
3232 nic->mac_control.stats_info->sw_stat.
3237 /* In case of a serious error, the device will be Reset. */
3238 val64 = readq(&bar0->serr_source);
3239 if (val64 & SERR_SOURCE_ANY) {
3240 nic->mac_control.stats_info->sw_stat.serious_err_cnt++;
3241 DBG_PRINT(ERR_DBG, "%s: Device indicates ", dev->name);
3242 DBG_PRINT(ERR_DBG, "serious error %llx!!\n",
3243 (unsigned long long)val64);
3244 netif_stop_queue(dev);
3245 schedule_work(&nic->rst_timer_task);
3246 nic->mac_control.stats_info->sw_stat.soft_reset_cnt++;
3250 * Also as mentioned in the latest Errata sheets if the PCC_FB_ECC
3251 * Error occurs, the adapter will be recycled by disabling the
3252 * adapter enable bit and enabling it again after the device
3253 * becomes Quiescent.
3255 val64 = readq(&bar0->pcc_err_reg);
3256 writeq(val64, &bar0->pcc_err_reg);
3257 if (val64 & PCC_FB_ECC_DB_ERR) {
3258 u64 ac = readq(&bar0->adapter_control);
3259 ac &= ~(ADAPTER_CNTL_EN);
3260 writeq(ac, &bar0->adapter_control);
3261 ac = readq(&bar0->adapter_control);
3262 schedule_work(&nic->set_link_task);
3264 /* Check for data parity error */
3265 val64 = readq(&bar0->pic_int_status);
3266 if (val64 & PIC_INT_GPIO) {
3267 val64 = readq(&bar0->gpio_int_reg);
3268 if (val64 & GPIO_INT_REG_DP_ERR_INT) {
3269 nic->mac_control.stats_info->sw_stat.parity_err_cnt++;
3270 schedule_work(&nic->rst_timer_task);
3271 nic->mac_control.stats_info->sw_stat.soft_reset_cnt++;
3275 /* Check for ring full counter */
3276 if (nic->device_type & XFRAME_II_DEVICE) {
3277 val64 = readq(&bar0->ring_bump_counter1);
3278 for (i=0; i<4; i++) {
3279 cnt = ( val64 & vBIT(0xFFFF,(i*16),16));
3280 cnt >>= 64 - ((i+1)*16);
3281 nic->mac_control.stats_info->sw_stat.ring_full_cnt
3285 val64 = readq(&bar0->ring_bump_counter2);
3286 for (i=0; i<4; i++) {
3287 cnt = ( val64 & vBIT(0xFFFF,(i*16),16));
3288 cnt >>= 64 - ((i+1)*16);
3289 nic->mac_control.stats_info->sw_stat.ring_full_cnt
3294 /* Other type of interrupts are not being handled now, TODO */
3298 * wait_for_cmd_complete - waits for a command to complete.
3299 * @sp : private member of the device structure, which is a pointer to the
3300 * s2io_nic structure.
3301 * Description: Function that waits for a command to Write into RMAC
3302 * ADDR DATA registers to be completed and returns either success or
3303 * error depending on whether the command was complete or not.
3305 * SUCCESS on success and FAILURE on failure.
3308 static int wait_for_cmd_complete(void __iomem *addr, u64 busy_bit)
3310 int ret = FAILURE, cnt = 0;
3314 val64 = readq(addr);
3315 if (!(val64 & busy_bit)) {
3331 * check_pci_device_id - Checks if the device id is supported
3333 * Description: Function to check if the pci device id is supported by driver.
3334 * Return value: Actual device id if supported else PCI_ANY_ID
3336 static u16 check_pci_device_id(u16 id)
3339 case PCI_DEVICE_ID_HERC_WIN:
3340 case PCI_DEVICE_ID_HERC_UNI:
3341 return XFRAME_II_DEVICE;
3342 case PCI_DEVICE_ID_S2IO_UNI:
3343 case PCI_DEVICE_ID_S2IO_WIN:
3344 return XFRAME_I_DEVICE;
3351 * s2io_reset - Resets the card.
3352 * @sp : private member of the device structure.
3353 * Description: Function to Reset the card. This function then also
3354 * restores the previously saved PCI configuration space registers as
3355 * the card reset also resets the configuration space.
3360 static void s2io_reset(nic_t * sp)
3362 XENA_dev_config_t __iomem *bar0 = sp->bar0;
3367 DBG_PRINT(INIT_DBG,"%s - Resetting XFrame card %s\n",
3368 __FUNCTION__, sp->dev->name);
3370 /* Back up the PCI-X CMD reg, dont want to lose MMRBC, OST settings */
3371 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER, &(pci_cmd));
3373 if (sp->device_type == XFRAME_II_DEVICE) {
3375 ret = pci_set_power_state(sp->pdev, 3);
3377 ret = pci_set_power_state(sp->pdev, 0);
3379 DBG_PRINT(ERR_DBG,"%s PME based SW_Reset failed!\n",
3387 val64 = SW_RESET_ALL;
3388 writeq(val64, &bar0->sw_reset);
3390 if (strstr(sp->product_name, "CX4")) {
3394 for (i = 0; i < S2IO_MAX_PCI_CONFIG_SPACE_REINIT; i++) {
3396 /* Restore the PCI state saved during initialization. */
3397 pci_restore_state(sp->pdev);
3398 pci_read_config_word(sp->pdev, 0x2, &val16);
3399 if (check_pci_device_id(val16) != (u16)PCI_ANY_ID)
3404 if (check_pci_device_id(val16) == (u16)PCI_ANY_ID) {
3405 DBG_PRINT(ERR_DBG,"%s SW_Reset failed!\n", __FUNCTION__);
3408 pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER, pci_cmd);
3412 /* Set swapper to enable I/O register access */
3413 s2io_set_swapper(sp);
3415 /* Restore the MSIX table entries from local variables */
3416 restore_xmsi_data(sp);
3418 /* Clear certain PCI/PCI-X fields after reset */
3419 if (sp->device_type == XFRAME_II_DEVICE) {
3420 /* Clear "detected parity error" bit */
3421 pci_write_config_word(sp->pdev, PCI_STATUS, 0x8000);
3423 /* Clearing PCIX Ecc status register */
3424 pci_write_config_dword(sp->pdev, 0x68, 0x7C);
3426 /* Clearing PCI_STATUS error reflected here */
3427 writeq(BIT(62), &bar0->txpic_int_reg);
3430 /* Reset device statistics maintained by OS */
3431 memset(&sp->stats, 0, sizeof (struct net_device_stats));
3433 /* SXE-002: Configure link and activity LED to turn it off */
3434 subid = sp->pdev->subsystem_device;
3435 if (((subid & 0xFF) >= 0x07) &&
3436 (sp->device_type == XFRAME_I_DEVICE)) {
3437 val64 = readq(&bar0->gpio_control);
3438 val64 |= 0x0000800000000000ULL;
3439 writeq(val64, &bar0->gpio_control);
3440 val64 = 0x0411040400000000ULL;
3441 writeq(val64, (void __iomem *)bar0 + 0x2700);
3445 * Clear spurious ECC interrupts that would have occured on
3446 * XFRAME II cards after reset.
3448 if (sp->device_type == XFRAME_II_DEVICE) {
3449 val64 = readq(&bar0->pcc_err_reg);
3450 writeq(val64, &bar0->pcc_err_reg);
3453 sp->device_enabled_once = FALSE;
3457 * s2io_set_swapper - to set the swapper controle on the card
3458 * @sp : private member of the device structure,
3459 * pointer to the s2io_nic structure.
3460 * Description: Function to set the swapper control on the card
3461 * correctly depending on the 'endianness' of the system.
3463 * SUCCESS on success and FAILURE on failure.
3466 static int s2io_set_swapper(nic_t * sp)
3468 struct net_device *dev = sp->dev;
3469 XENA_dev_config_t __iomem *bar0 = sp->bar0;
3470 u64 val64, valt, valr;
3473 * Set proper endian settings and verify the same by reading
3474 * the PIF Feed-back register.
3477 val64 = readq(&bar0->pif_rd_swapper_fb);
3478 if (val64 != 0x0123456789ABCDEFULL) {
3480 u64 value[] = { 0xC30000C3C30000C3ULL, /* FE=1, SE=1 */
3481 0x8100008181000081ULL, /* FE=1, SE=0 */
3482 0x4200004242000042ULL, /* FE=0, SE=1 */
3483 0}; /* FE=0, SE=0 */
3486 writeq(value[i], &bar0->swapper_ctrl);
3487 val64 = readq(&bar0->pif_rd_swapper_fb);
3488 if (val64 == 0x0123456789ABCDEFULL)
3493 DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, ",
3495 DBG_PRINT(ERR_DBG, "feedback read %llx\n",
3496 (unsigned long long) val64);
3501 valr = readq(&bar0->swapper_ctrl);
3504 valt = 0x0123456789ABCDEFULL;
3505 writeq(valt, &bar0->xmsi_address);
3506 val64 = readq(&bar0->xmsi_address);
3510 u64 value[] = { 0x00C3C30000C3C300ULL, /* FE=1, SE=1 */
3511 0x0081810000818100ULL, /* FE=1, SE=0 */
3512 0x0042420000424200ULL, /* FE=0, SE=1 */
3513 0}; /* FE=0, SE=0 */
3516 writeq((value[i] | valr), &bar0->swapper_ctrl);
3517 writeq(valt, &bar0->xmsi_address);
3518 val64 = readq(&bar0->xmsi_address);
3524 unsigned long long x = val64;
3525 DBG_PRINT(ERR_DBG, "Write failed, Xmsi_addr ");
3526 DBG_PRINT(ERR_DBG, "reads:0x%llx\n", x);
3530 val64 = readq(&bar0->swapper_ctrl);
3531 val64 &= 0xFFFF000000000000ULL;
3535 * The device by default set to a big endian format, so a
3536 * big endian driver need not set anything.
3538 val64 |= (SWAPPER_CTRL_TXP_FE |
3539 SWAPPER_CTRL_TXP_SE |
3540 SWAPPER_CTRL_TXD_R_FE |
3541 SWAPPER_CTRL_TXD_W_FE |
3542 SWAPPER_CTRL_TXF_R_FE |
3543 SWAPPER_CTRL_RXD_R_FE |
3544 SWAPPER_CTRL_RXD_W_FE |
3545 SWAPPER_CTRL_RXF_W_FE |
3546 SWAPPER_CTRL_XMSI_FE |
3547 SWAPPER_CTRL_STATS_FE | SWAPPER_CTRL_STATS_SE);
3548 if (sp->intr_type == INTA)
3549 val64 |= SWAPPER_CTRL_XMSI_SE;
3550 writeq(val64, &bar0->swapper_ctrl);
3553 * Initially we enable all bits to make it accessible by the
3554 * driver, then we selectively enable only those bits that
3557 val64 |= (SWAPPER_CTRL_TXP_FE |
3558 SWAPPER_CTRL_TXP_SE |
3559 SWAPPER_CTRL_TXD_R_FE |
3560 SWAPPER_CTRL_TXD_R_SE |
3561 SWAPPER_CTRL_TXD_W_FE |
3562 SWAPPER_CTRL_TXD_W_SE |
3563 SWAPPER_CTRL_TXF_R_FE |
3564 SWAPPER_CTRL_RXD_R_FE |
3565 SWAPPER_CTRL_RXD_R_SE |
3566 SWAPPER_CTRL_RXD_W_FE |
3567 SWAPPER_CTRL_RXD_W_SE |
3568 SWAPPER_CTRL_RXF_W_FE |
3569 SWAPPER_CTRL_XMSI_FE |
3570 SWAPPER_CTRL_STATS_FE | SWAPPER_CTRL_STATS_SE);
3571 if (sp->intr_type == INTA)
3572 val64 |= SWAPPER_CTRL_XMSI_SE;
3573 writeq(val64, &bar0->swapper_ctrl);
3575 val64 = readq(&bar0->swapper_ctrl);
3578 * Verifying if endian settings are accurate by reading a
3579 * feedback register.
3581 val64 = readq(&bar0->pif_rd_swapper_fb);
3582 if (val64 != 0x0123456789ABCDEFULL) {
3583 /* Endian settings are incorrect, calls for another dekko. */
3584 DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, ",
3586 DBG_PRINT(ERR_DBG, "feedback read %llx\n",
3587 (unsigned long long) val64);
3594 static int wait_for_msix_trans(nic_t *nic, int i)
3596 XENA_dev_config_t __iomem *bar0 = nic->bar0;
3598 int ret = 0, cnt = 0;
3601 val64 = readq(&bar0->xmsi_access);
3602 if (!(val64 & BIT(15)))
3608 DBG_PRINT(ERR_DBG, "XMSI # %d Access failed\n", i);
3615 static void restore_xmsi_data(nic_t *nic)
3617 XENA_dev_config_t __iomem *bar0 = nic->bar0;
3621 for (i=0; i < MAX_REQUESTED_MSI_X; i++) {
3622 writeq(nic->msix_info[i].addr, &bar0->xmsi_address);
3623 writeq(nic->msix_info[i].data, &bar0->xmsi_data);
3624 val64 = (BIT(7) | BIT(15) | vBIT(i, 26, 6));
3625 writeq(val64, &bar0->xmsi_access);
3626 if (wait_for_msix_trans(nic, i)) {
3627 DBG_PRINT(ERR_DBG, "failed in %s\n", __FUNCTION__);
3633 static void store_xmsi_data(nic_t *nic)
3635 XENA_dev_config_t __iomem *bar0 = nic->bar0;
3636 u64 val64, addr, data;
3639 /* Store and display */
3640 for (i=0; i < MAX_REQUESTED_MSI_X; i++) {
3641 val64 = (BIT(15) | vBIT(i, 26, 6));
3642 writeq(val64, &bar0->xmsi_access);
3643 if (wait_for_msix_trans(nic, i)) {
3644 DBG_PRINT(ERR_DBG, "failed in %s\n", __FUNCTION__);
3647 addr = readq(&bar0->xmsi_address);
3648 data = readq(&bar0->xmsi_data);
3650 nic->msix_info[i].addr = addr;
3651 nic->msix_info[i].data = data;
3656 int s2io_enable_msi(nic_t *nic)
3658 XENA_dev_config_t __iomem *bar0 = nic->bar0;
3659 u16 msi_ctrl, msg_val;
3660 struct config_param *config = &nic->config;
3661 struct net_device *dev = nic->dev;
3662 u64 val64, tx_mat, rx_mat;
3665 val64 = readq(&bar0->pic_control);
3667 writeq(val64, &bar0->pic_control);
3669 err = pci_enable_msi(nic->pdev);
3671 DBG_PRINT(ERR_DBG, "%s: enabling MSI failed\n",
3677 * Enable MSI and use MSI-1 in stead of the standard MSI-0
3678 * for interrupt handling.
3680 pci_read_config_word(nic->pdev, 0x4c, &msg_val);
3682 pci_write_config_word(nic->pdev, 0x4c, msg_val);
3683 pci_read_config_word(nic->pdev, 0x4c, &msg_val);
3685 pci_read_config_word(nic->pdev, 0x42, &msi_ctrl);
3687 pci_write_config_word(nic->pdev, 0x42, msi_ctrl);
3689 /* program MSI-1 into all usable Tx_Mat and Rx_Mat fields */
3690 tx_mat = readq(&bar0->tx_mat0_n[0]);
3691 for (i=0; i<config->tx_fifo_num; i++) {
3692 tx_mat |= TX_MAT_SET(i, 1);
3694 writeq(tx_mat, &bar0->tx_mat0_n[0]);
3696 rx_mat = readq(&bar0->rx_mat);
3697 for (i=0; i<config->rx_ring_num; i++) {
3698 rx_mat |= RX_MAT_SET(i, 1);
3700 writeq(rx_mat, &bar0->rx_mat);
3702 dev->irq = nic->pdev->irq;
3706 static int s2io_enable_msi_x(nic_t *nic)
3708 XENA_dev_config_t __iomem *bar0 = nic->bar0;
3710 u16 msi_control; /* Temp variable */
3711 int ret, i, j, msix_indx = 1;
3713 nic->entries = kmalloc(MAX_REQUESTED_MSI_X * sizeof(struct msix_entry),
3715 if (nic->entries == NULL) {
3716 DBG_PRINT(ERR_DBG, "%s: Memory allocation failed\n", __FUNCTION__);
3719 memset(nic->entries, 0, MAX_REQUESTED_MSI_X * sizeof(struct msix_entry));
3722 kmalloc(MAX_REQUESTED_MSI_X * sizeof(struct s2io_msix_entry),
3724 if (nic->s2io_entries == NULL) {
3725 DBG_PRINT(ERR_DBG, "%s: Memory allocation failed\n", __FUNCTION__);
3726 kfree(nic->entries);
3729 memset(nic->s2io_entries, 0,
3730 MAX_REQUESTED_MSI_X * sizeof(struct s2io_msix_entry));
3732 for (i=0; i< MAX_REQUESTED_MSI_X; i++) {
3733 nic->entries[i].entry = i;
3734 nic->s2io_entries[i].entry = i;
3735 nic->s2io_entries[i].arg = NULL;
3736 nic->s2io_entries[i].in_use = 0;
3739 tx_mat = readq(&bar0->tx_mat0_n[0]);
3740 for (i=0; i<nic->config.tx_fifo_num; i++, msix_indx++) {
3741 tx_mat |= TX_MAT_SET(i, msix_indx);
3742 nic->s2io_entries[msix_indx].arg = &nic->mac_control.fifos[i];
3743 nic->s2io_entries[msix_indx].type = MSIX_FIFO_TYPE;
3744 nic->s2io_entries[msix_indx].in_use = MSIX_FLG;
3746 writeq(tx_mat, &bar0->tx_mat0_n[0]);
3748 if (!nic->config.bimodal) {
3749 rx_mat = readq(&bar0->rx_mat);
3750 for (j=0; j<nic->config.rx_ring_num; j++, msix_indx++) {
3751 rx_mat |= RX_MAT_SET(j, msix_indx);
3752 nic->s2io_entries[msix_indx].arg = &nic->mac_control.rings[j];
3753 nic->s2io_entries[msix_indx].type = MSIX_RING_TYPE;
3754 nic->s2io_entries[msix_indx].in_use = MSIX_FLG;
3756 writeq(rx_mat, &bar0->rx_mat);
3758 tx_mat = readq(&bar0->tx_mat0_n[7]);
3759 for (j=0; j<nic->config.rx_ring_num; j++, msix_indx++) {
3760 tx_mat |= TX_MAT_SET(i, msix_indx);
3761 nic->s2io_entries[msix_indx].arg = &nic->mac_control.rings[j];
3762 nic->s2io_entries[msix_indx].type = MSIX_RING_TYPE;
3763 nic->s2io_entries[msix_indx].in_use = MSIX_FLG;
3765 writeq(tx_mat, &bar0->tx_mat0_n[7]);
3768 nic->avail_msix_vectors = 0;
3769 ret = pci_enable_msix(nic->pdev, nic->entries, MAX_REQUESTED_MSI_X);
3770 /* We fail init if error or we get less vectors than min required */
3771 if (ret >= (nic->config.tx_fifo_num + nic->config.rx_ring_num + 1)) {
3772 nic->avail_msix_vectors = ret;
3773 ret = pci_enable_msix(nic->pdev, nic->entries, ret);
3776 DBG_PRINT(ERR_DBG, "%s: Enabling MSIX failed\n", nic->dev->name);
3777 kfree(nic->entries);
3778 kfree(nic->s2io_entries);
3779 nic->entries = NULL;
3780 nic->s2io_entries = NULL;
3781 nic->avail_msix_vectors = 0;
3784 if (!nic->avail_msix_vectors)
3785 nic->avail_msix_vectors = MAX_REQUESTED_MSI_X;
3788 * To enable MSI-X, MSI also needs to be enabled, due to a bug
3789 * in the herc NIC. (Temp change, needs to be removed later)
3791 pci_read_config_word(nic->pdev, 0x42, &msi_control);
3792 msi_control |= 0x1; /* Enable MSI */
3793 pci_write_config_word(nic->pdev, 0x42, msi_control);
3798 /* ********************************************************* *
3799 * Functions defined below concern the OS part of the driver *
3800 * ********************************************************* */
3803 * s2io_open - open entry point of the driver
3804 * @dev : pointer to the device structure.
3806 * This function is the open entry point of the driver. It mainly calls a
3807 * function to allocate Rx buffers and inserts them into the buffer
3808 * descriptors and then enables the Rx part of the NIC.
3810 * 0 on success and an appropriate (-)ve integer as defined in errno.h
3814 static int s2io_open(struct net_device *dev)
3816 nic_t *sp = dev->priv;
3820 * Make sure you have link off by default every time
3821 * Nic is initialized
3823 netif_carrier_off(dev);
3824 sp->last_link_state = 0;
3826 /* Initialize H/W and enable interrupts */
3827 err = s2io_card_up(sp);
3829 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
3831 goto hw_init_failed;
3834 if (s2io_set_mac_addr(dev, dev->dev_addr) == FAILURE) {
3835 DBG_PRINT(ERR_DBG, "Set Mac Address Failed\n");
3838 goto hw_init_failed;
3841 netif_start_queue(dev);
3845 if (sp->intr_type == MSI_X) {
3848 if (sp->s2io_entries)
3849 kfree(sp->s2io_entries);
3855 * s2io_close -close entry point of the driver
3856 * @dev : device pointer.
3858 * This is the stop entry point of the driver. It needs to undo exactly
3859 * whatever was done by the open entry point,thus it's usually referred to
3860 * as the close function.Among other things this function mainly stops the
3861 * Rx side of the NIC and frees all the Rx buffers in the Rx rings.
3863 * 0 on success and an appropriate (-)ve integer as defined in errno.h
3867 static int s2io_close(struct net_device *dev)
3869 nic_t *sp = dev->priv;
3871 flush_scheduled_work();
3872 netif_stop_queue(dev);
3873 /* Reset card, kill tasklet and free Tx and Rx buffers. */
3876 sp->device_close_flag = TRUE; /* Device is shut down. */
3881 * s2io_xmit - Tx entry point of te driver
3882 * @skb : the socket buffer containing the Tx data.
3883 * @dev : device pointer.
3885 * This function is the Tx entry point of the driver. S2IO NIC supports
3886 * certain protocol assist features on Tx side, namely CSO, S/G, LSO.
3887 * NOTE: when device cant queue the pkt,just the trans_start variable will
3890 * 0 on success & 1 on failure.
3893 static int s2io_xmit(struct sk_buff *skb, struct net_device *dev)
3895 nic_t *sp = dev->priv;
3896 u16 frg_cnt, frg_len, i, queue, queue_len, put_off, get_off;
3899 TxFIFO_element_t __iomem *tx_fifo;
3900 unsigned long flags;
3902 int vlan_priority = 0;
3903 mac_info_t *mac_control;
3904 struct config_param *config;
3907 mac_control = &sp->mac_control;
3908 config = &sp->config;
3910 DBG_PRINT(TX_DBG, "%s: In Neterion Tx routine\n", dev->name);
3911 spin_lock_irqsave(&sp->tx_lock, flags);
3912 if (atomic_read(&sp->card_state) == CARD_DOWN) {
3913 DBG_PRINT(TX_DBG, "%s: Card going down for reset\n",
3915 spin_unlock_irqrestore(&sp->tx_lock, flags);
3922 /* Get Fifo number to Transmit based on vlan priority */
3923 if (sp->vlgrp && vlan_tx_tag_present(skb)) {
3924 vlan_tag = vlan_tx_tag_get(skb);
3925 vlan_priority = vlan_tag >> 13;
3926 queue = config->fifo_mapping[vlan_priority];
3929 put_off = (u16) mac_control->fifos[queue].tx_curr_put_info.offset;
3930 get_off = (u16) mac_control->fifos[queue].tx_curr_get_info.offset;
3931 txdp = (TxD_t *) mac_control->fifos[queue].list_info[put_off].
3934 queue_len = mac_control->fifos[queue].tx_curr_put_info.fifo_len + 1;
3935 /* Avoid "put" pointer going beyond "get" pointer */
3936 if (txdp->Host_Control ||
3937 ((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
3938 DBG_PRINT(TX_DBG, "Error in xmit, No free TXDs.\n");
3939 netif_stop_queue(dev);
3941 spin_unlock_irqrestore(&sp->tx_lock, flags);
3945 /* A buffer with no data will be dropped */
3947 DBG_PRINT(TX_DBG, "%s:Buffer has no data..\n", dev->name);
3949 spin_unlock_irqrestore(&sp->tx_lock, flags);
3953 offload_type = s2io_offload_type(skb);
3954 if (offload_type & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
3955 txdp->Control_1 |= TXD_TCP_LSO_EN;
3956 txdp->Control_1 |= TXD_TCP_LSO_MSS(s2io_tcp_mss(skb));
3958 if (skb->ip_summed == CHECKSUM_PARTIAL) {
3960 (TXD_TX_CKO_IPV4_EN | TXD_TX_CKO_TCP_EN |
3963 txdp->Control_1 |= TXD_GATHER_CODE_FIRST;
3964 txdp->Control_1 |= TXD_LIST_OWN_XENA;
3965 txdp->Control_2 |= config->tx_intr_type;
3967 if (sp->vlgrp && vlan_tx_tag_present(skb)) {
3968 txdp->Control_2 |= TXD_VLAN_ENABLE;
3969 txdp->Control_2 |= TXD_VLAN_TAG(vlan_tag);
3972 frg_len = skb->len - skb->data_len;
3973 if (offload_type == SKB_GSO_UDP) {
3976 ufo_size = s2io_udp_mss(skb);
3978 txdp->Control_1 |= TXD_UFO_EN;
3979 txdp->Control_1 |= TXD_UFO_MSS(ufo_size);
3980 txdp->Control_1 |= TXD_BUFFER0_SIZE(8);
3982 sp->ufo_in_band_v[put_off] =
3983 (u64)skb_shinfo(skb)->ip6_frag_id;
3985 sp->ufo_in_band_v[put_off] =
3986 (u64)skb_shinfo(skb)->ip6_frag_id << 32;
3988 txdp->Host_Control = (unsigned long)sp->ufo_in_band_v;
3989 txdp->Buffer_Pointer = pci_map_single(sp->pdev,
3991 sizeof(u64), PCI_DMA_TODEVICE);
3995 txdp->Buffer_Pointer = pci_map_single
3996 (sp->pdev, skb->data, frg_len, PCI_DMA_TODEVICE);
3997 txdp->Host_Control = (unsigned long) skb;
3998 txdp->Control_1 |= TXD_BUFFER0_SIZE(frg_len);
3999 if (offload_type == SKB_GSO_UDP)
4000 txdp->Control_1 |= TXD_UFO_EN;
4002 frg_cnt = skb_shinfo(skb)->nr_frags;
4003 /* For fragmented SKB. */
4004 for (i = 0; i < frg_cnt; i++) {
4005 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4006 /* A '0' length fragment will be ignored */
4010 txdp->Buffer_Pointer = (u64) pci_map_page
4011 (sp->pdev, frag->page, frag->page_offset,
4012 frag->size, PCI_DMA_TODEVICE);
4013 txdp->Control_1 = TXD_BUFFER0_SIZE(frag->size);
4014 if (offload_type == SKB_GSO_UDP)
4015 txdp->Control_1 |= TXD_UFO_EN;
4017 txdp->Control_1 |= TXD_GATHER_CODE_LAST;
4019 if (offload_type == SKB_GSO_UDP)
4020 frg_cnt++; /* as Txd0 was used for inband header */
4022 tx_fifo = mac_control->tx_FIFO_start[queue];
4023 val64 = mac_control->fifos[queue].list_info[put_off].list_phy_addr;
4024 writeq(val64, &tx_fifo->TxDL_Pointer);
4026 val64 = (TX_FIFO_LAST_TXD_NUM(frg_cnt) | TX_FIFO_FIRST_LIST |
4029 val64 |= TX_FIFO_SPECIAL_FUNC;
4031 writeq(val64, &tx_fifo->List_Control);
4036 if (put_off == mac_control->fifos[queue].tx_curr_put_info.fifo_len + 1)
4038 mac_control->fifos[queue].tx_curr_put_info.offset = put_off;
4040 /* Avoid "put" pointer going beyond "get" pointer */
4041 if (((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
4042 sp->mac_control.stats_info->sw_stat.fifo_full_cnt++;
4044 "No free TxDs for xmit, Put: 0x%x Get:0x%x\n",
4046 netif_stop_queue(dev);
4049 dev->trans_start = jiffies;
4050 spin_unlock_irqrestore(&sp->tx_lock, flags);
4056 s2io_alarm_handle(unsigned long data)
4058 nic_t *sp = (nic_t *)data;
4060 alarm_intr_handler(sp);
4061 mod_timer(&sp->alarm_timer, jiffies + HZ / 2);
4064 static int s2io_chk_rx_buffers(nic_t *sp, int rng_n)
4066 int rxb_size, level;
4069 rxb_size = atomic_read(&sp->rx_bufs_left[rng_n]);
4070 level = rx_buffer_level(sp, rxb_size, rng_n);
4072 if ((level == PANIC) && (!TASKLET_IN_USE)) {
4074 DBG_PRINT(INTR_DBG, "%s: Rx BD hit ", __FUNCTION__);
4075 DBG_PRINT(INTR_DBG, "PANIC levels\n");
4076 if ((ret = fill_rx_buffers(sp, rng_n)) == -ENOMEM) {
4077 DBG_PRINT(ERR_DBG, "Out of memory in %s",
4079 clear_bit(0, (&sp->tasklet_status));
4082 clear_bit(0, (&sp->tasklet_status));
4083 } else if (level == LOW)
4084 tasklet_schedule(&sp->task);
4086 } else if (fill_rx_buffers(sp, rng_n) == -ENOMEM) {
4087 DBG_PRINT(ERR_DBG, "%s:Out of memory", sp->dev->name);
4088 DBG_PRINT(ERR_DBG, " in Rx Intr!!\n");
4093 static irqreturn_t s2io_msi_handle(int irq, void *dev_id)
4095 struct net_device *dev = (struct net_device *) dev_id;
4096 nic_t *sp = dev->priv;
4098 mac_info_t *mac_control;
4099 struct config_param *config;
4101 atomic_inc(&sp->isr_cnt);
4102 mac_control = &sp->mac_control;
4103 config = &sp->config;
4104 DBG_PRINT(INTR_DBG, "%s: MSI handler\n", __FUNCTION__);
4106 /* If Intr is because of Rx Traffic */
4107 for (i = 0; i < config->rx_ring_num; i++)
4108 rx_intr_handler(&mac_control->rings[i]);
4110 /* If Intr is because of Tx Traffic */
4111 for (i = 0; i < config->tx_fifo_num; i++)
4112 tx_intr_handler(&mac_control->fifos[i]);
4115 * If the Rx buffer count is below the panic threshold then
4116 * reallocate the buffers from the interrupt handler itself,
4117 * else schedule a tasklet to reallocate the buffers.
4119 for (i = 0; i < config->rx_ring_num; i++)
4120 s2io_chk_rx_buffers(sp, i);
4122 atomic_dec(&sp->isr_cnt);
4126 static irqreturn_t s2io_msix_ring_handle(int irq, void *dev_id)
4128 ring_info_t *ring = (ring_info_t *)dev_id;
4129 nic_t *sp = ring->nic;
4131 atomic_inc(&sp->isr_cnt);
4133 rx_intr_handler(ring);
4134 s2io_chk_rx_buffers(sp, ring->ring_no);
4136 atomic_dec(&sp->isr_cnt);
4140 static irqreturn_t s2io_msix_fifo_handle(int irq, void *dev_id)
4142 fifo_info_t *fifo = (fifo_info_t *)dev_id;
4143 nic_t *sp = fifo->nic;
4145 atomic_inc(&sp->isr_cnt);
4146 tx_intr_handler(fifo);
4147 atomic_dec(&sp->isr_cnt);
4150 static void s2io_txpic_intr_handle(nic_t *sp)
4152 XENA_dev_config_t __iomem *bar0 = sp->bar0;
4155 val64 = readq(&bar0->pic_int_status);
4156 if (val64 & PIC_INT_GPIO) {
4157 val64 = readq(&bar0->gpio_int_reg);
4158 if ((val64 & GPIO_INT_REG_LINK_DOWN) &&
4159 (val64 & GPIO_INT_REG_LINK_UP)) {
4161 * This is unstable state so clear both up/down
4162 * interrupt and adapter to re-evaluate the link state.
4164 val64 |= GPIO_INT_REG_LINK_DOWN;
4165 val64 |= GPIO_INT_REG_LINK_UP;
4166 writeq(val64, &bar0->gpio_int_reg);
4167 val64 = readq(&bar0->gpio_int_mask);
4168 val64 &= ~(GPIO_INT_MASK_LINK_UP |
4169 GPIO_INT_MASK_LINK_DOWN);
4170 writeq(val64, &bar0->gpio_int_mask);
4172 else if (val64 & GPIO_INT_REG_LINK_UP) {
4173 val64 = readq(&bar0->adapter_status);
4174 /* Enable Adapter */
4175 val64 = readq(&bar0->adapter_control);
4176 val64 |= ADAPTER_CNTL_EN;
4177 writeq(val64, &bar0->adapter_control);
4178 val64 |= ADAPTER_LED_ON;
4179 writeq(val64, &bar0->adapter_control);
4180 if (!sp->device_enabled_once)
4181 sp->device_enabled_once = 1;
4183 s2io_link(sp, LINK_UP);
4185 * unmask link down interrupt and mask link-up
4188 val64 = readq(&bar0->gpio_int_mask);
4189 val64 &= ~GPIO_INT_MASK_LINK_DOWN;
4190 val64 |= GPIO_INT_MASK_LINK_UP;
4191 writeq(val64, &bar0->gpio_int_mask);
4193 }else if (val64 & GPIO_INT_REG_LINK_DOWN) {
4194 val64 = readq(&bar0->adapter_status);
4195 s2io_link(sp, LINK_DOWN);
4196 /* Link is down so unmaks link up interrupt */
4197 val64 = readq(&bar0->gpio_int_mask);
4198 val64 &= ~GPIO_INT_MASK_LINK_UP;
4199 val64 |= GPIO_INT_MASK_LINK_DOWN;
4200 writeq(val64, &bar0->gpio_int_mask);
4203 val64 = readq(&bar0->gpio_int_mask);
4207 * s2io_isr - ISR handler of the device .
4208 * @irq: the irq of the device.
4209 * @dev_id: a void pointer to the dev structure of the NIC.
4210 * Description: This function is the ISR handler of the device. It
4211 * identifies the reason for the interrupt and calls the relevant
4212 * service routines. As a contongency measure, this ISR allocates the
4213 * recv buffers, if their numbers are below the panic value which is
4214 * presently set to 25% of the original number of rcv buffers allocated.
4216 * IRQ_HANDLED: will be returned if IRQ was handled by this routine
4217 * IRQ_NONE: will be returned if interrupt is not from our device
4219 static irqreturn_t s2io_isr(int irq, void *dev_id)
4221 struct net_device *dev = (struct net_device *) dev_id;
4222 nic_t *sp = dev->priv;
4223 XENA_dev_config_t __iomem *bar0 = sp->bar0;
4226 mac_info_t *mac_control;
4227 struct config_param *config;
4229 atomic_inc(&sp->isr_cnt);
4230 mac_control = &sp->mac_control;
4231 config = &sp->config;
4234 * Identify the cause for interrupt and call the appropriate
4235 * interrupt handler. Causes for the interrupt could be;
4239 * 4. Error in any functional blocks of the NIC.
4241 reason = readq(&bar0->general_int_status);
4244 /* The interrupt was not raised by us. */
4245 atomic_dec(&sp->isr_cnt);
4248 else if (unlikely(reason == S2IO_MINUS_ONE) ) {
4249 /* Disable device and get out */
4250 atomic_dec(&sp->isr_cnt);
4255 if (reason & GEN_INTR_RXTRAFFIC) {
4256 if ( likely ( netif_rx_schedule_prep(dev)) ) {
4257 __netif_rx_schedule(dev);
4258 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_mask);
4261 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
4265 * Rx handler is called by default, without checking for the
4266 * cause of interrupt.
4267 * rx_traffic_int reg is an R1 register, writing all 1's
4268 * will ensure that the actual interrupt causing bit get's
4269 * cleared and hence a read can be avoided.
4271 if (reason & GEN_INTR_RXTRAFFIC)
4272 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
4274 for (i = 0; i < config->rx_ring_num; i++) {
4275 rx_intr_handler(&mac_control->rings[i]);
4280 * tx_traffic_int reg is an R1 register, writing all 1's
4281 * will ensure that the actual interrupt causing bit get's
4282 * cleared and hence a read can be avoided.
4284 if (reason & GEN_INTR_TXTRAFFIC)
4285 writeq(S2IO_MINUS_ONE, &bar0->tx_traffic_int);
4287 for (i = 0; i < config->tx_fifo_num; i++)
4288 tx_intr_handler(&mac_control->fifos[i]);
4290 if (reason & GEN_INTR_TXPIC)
4291 s2io_txpic_intr_handle(sp);
4293 * If the Rx buffer count is below the panic threshold then
4294 * reallocate the buffers from the interrupt handler itself,
4295 * else schedule a tasklet to reallocate the buffers.
4298 for (i = 0; i < config->rx_ring_num; i++)
4299 s2io_chk_rx_buffers(sp, i);
4302 writeq(0, &bar0->general_int_mask);
4303 readl(&bar0->general_int_status);
4305 atomic_dec(&sp->isr_cnt);
4312 static void s2io_updt_stats(nic_t *sp)
4314 XENA_dev_config_t __iomem *bar0 = sp->bar0;
4318 if (atomic_read(&sp->card_state) == CARD_UP) {
4319 /* Apprx 30us on a 133 MHz bus */
4320 val64 = SET_UPDT_CLICKS(10) |
4321 STAT_CFG_ONE_SHOT_EN | STAT_CFG_STAT_EN;
4322 writeq(val64, &bar0->stat_cfg);
4325 val64 = readq(&bar0->stat_cfg);
4326 if (!(val64 & BIT(0)))
4330 break; /* Updt failed */
4333 memset(sp->mac_control.stats_info, 0, sizeof(StatInfo_t));
4338 * s2io_get_stats - Updates the device statistics structure.
4339 * @dev : pointer to the device structure.
4341 * This function updates the device statistics structure in the s2io_nic
4342 * structure and returns a pointer to the same.
4344 * pointer to the updated net_device_stats structure.
4347 static struct net_device_stats *s2io_get_stats(struct net_device *dev)
4349 nic_t *sp = dev->priv;
4350 mac_info_t *mac_control;
4351 struct config_param *config;
4354 mac_control = &sp->mac_control;
4355 config = &sp->config;
4357 /* Configure Stats for immediate updt */
4358 s2io_updt_stats(sp);
4360 sp->stats.tx_packets =
4361 le32_to_cpu(mac_control->stats_info->tmac_frms);
4362 sp->stats.tx_errors =
4363 le32_to_cpu(mac_control->stats_info->tmac_any_err_frms);
4364 sp->stats.rx_errors =
4365 le64_to_cpu(mac_control->stats_info->rmac_drop_frms);
4366 sp->stats.multicast =
4367 le32_to_cpu(mac_control->stats_info->rmac_vld_mcst_frms);
4368 sp->stats.rx_length_errors =
4369 le64_to_cpu(mac_control->stats_info->rmac_long_frms);
4371 return (&sp->stats);
4375 * s2io_set_multicast - entry point for multicast address enable/disable.
4376 * @dev : pointer to the device structure
4378 * This function is a driver entry point which gets called by the kernel
4379 * whenever multicast addresses must be enabled/disabled. This also gets
4380 * called to set/reset promiscuous mode. Depending on the deivce flag, we
4381 * determine, if multicast address must be enabled or if promiscuous mode
4382 * is to be disabled etc.
4387 static void s2io_set_multicast(struct net_device *dev)
4390 struct dev_mc_list *mclist;
4391 nic_t *sp = dev->priv;
4392 XENA_dev_config_t __iomem *bar0 = sp->bar0;
4393 u64 val64 = 0, multi_mac = 0x010203040506ULL, mask =
4395 u64 dis_addr = 0xffffffffffffULL, mac_addr = 0;
4398 if ((dev->flags & IFF_ALLMULTI) && (!sp->m_cast_flg)) {
4399 /* Enable all Multicast addresses */
4400 writeq(RMAC_ADDR_DATA0_MEM_ADDR(multi_mac),
4401 &bar0->rmac_addr_data0_mem);
4402 writeq(RMAC_ADDR_DATA1_MEM_MASK(mask),
4403 &bar0->rmac_addr_data1_mem);
4404 val64 = RMAC_ADDR_CMD_MEM_WE |
4405 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4406 RMAC_ADDR_CMD_MEM_OFFSET(MAC_MC_ALL_MC_ADDR_OFFSET);
4407 writeq(val64, &bar0->rmac_addr_cmd_mem);
4408 /* Wait till command completes */
4409 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
4410 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING);
4413 sp->all_multi_pos = MAC_MC_ALL_MC_ADDR_OFFSET;
4414 } else if ((dev->flags & IFF_ALLMULTI) && (sp->m_cast_flg)) {
4415 /* Disable all Multicast addresses */
4416 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
4417 &bar0->rmac_addr_data0_mem);
4418 writeq(RMAC_ADDR_DATA1_MEM_MASK(0x0),
4419 &bar0->rmac_addr_data1_mem);
4420 val64 = RMAC_ADDR_CMD_MEM_WE |
4421 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4422 RMAC_ADDR_CMD_MEM_OFFSET(sp->all_multi_pos);
4423 writeq(val64, &bar0->rmac_addr_cmd_mem);
4424 /* Wait till command completes */
4425 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
4426 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING);
4429 sp->all_multi_pos = 0;
4432 if ((dev->flags & IFF_PROMISC) && (!sp->promisc_flg)) {
4433 /* Put the NIC into promiscuous mode */
4434 add = &bar0->mac_cfg;
4435 val64 = readq(&bar0->mac_cfg);
4436 val64 |= MAC_CFG_RMAC_PROM_ENABLE;
4438 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4439 writel((u32) val64, add);
4440 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4441 writel((u32) (val64 >> 32), (add + 4));
4443 val64 = readq(&bar0->mac_cfg);
4444 sp->promisc_flg = 1;
4445 DBG_PRINT(INFO_DBG, "%s: entered promiscuous mode\n",
4447 } else if (!(dev->flags & IFF_PROMISC) && (sp->promisc_flg)) {
4448 /* Remove the NIC from promiscuous mode */
4449 add = &bar0->mac_cfg;
4450 val64 = readq(&bar0->mac_cfg);
4451 val64 &= ~MAC_CFG_RMAC_PROM_ENABLE;
4453 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4454 writel((u32) val64, add);
4455 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4456 writel((u32) (val64 >> 32), (add + 4));
4458 val64 = readq(&bar0->mac_cfg);
4459 sp->promisc_flg = 0;
4460 DBG_PRINT(INFO_DBG, "%s: left promiscuous mode\n",
4464 /* Update individual M_CAST address list */
4465 if ((!sp->m_cast_flg) && dev->mc_count) {
4467 (MAX_ADDRS_SUPPORTED - MAC_MC_ADDR_START_OFFSET - 1)) {
4468 DBG_PRINT(ERR_DBG, "%s: No more Rx filters ",
4470 DBG_PRINT(ERR_DBG, "can be added, please enable ");
4471 DBG_PRINT(ERR_DBG, "ALL_MULTI instead\n");
4475 prev_cnt = sp->mc_addr_count;
4476 sp->mc_addr_count = dev->mc_count;
4478 /* Clear out the previous list of Mc in the H/W. */
4479 for (i = 0; i < prev_cnt; i++) {
4480 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
4481 &bar0->rmac_addr_data0_mem);
4482 writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
4483 &bar0->rmac_addr_data1_mem);
4484 val64 = RMAC_ADDR_CMD_MEM_WE |
4485 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4486 RMAC_ADDR_CMD_MEM_OFFSET
4487 (MAC_MC_ADDR_START_OFFSET + i);
4488 writeq(val64, &bar0->rmac_addr_cmd_mem);
4490 /* Wait for command completes */
4491 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
4492 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING)) {
4493 DBG_PRINT(ERR_DBG, "%s: Adding ",
4495 DBG_PRINT(ERR_DBG, "Multicasts failed\n");
4500 /* Create the new Rx filter list and update the same in H/W. */
4501 for (i = 0, mclist = dev->mc_list; i < dev->mc_count;
4502 i++, mclist = mclist->next) {
4503 memcpy(sp->usr_addrs[i].addr, mclist->dmi_addr,
4506 for (j = 0; j < ETH_ALEN; j++) {
4507 mac_addr |= mclist->dmi_addr[j];
4511 writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr),
4512 &bar0->rmac_addr_data0_mem);
4513 writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
4514 &bar0->rmac_addr_data1_mem);
4515 val64 = RMAC_ADDR_CMD_MEM_WE |
4516 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4517 RMAC_ADDR_CMD_MEM_OFFSET
4518 (i + MAC_MC_ADDR_START_OFFSET);
4519 writeq(val64, &bar0->rmac_addr_cmd_mem);
4521 /* Wait for command completes */
4522 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
4523 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING)) {
4524 DBG_PRINT(ERR_DBG, "%s: Adding ",
4526 DBG_PRINT(ERR_DBG, "Multicasts failed\n");
4534 * s2io_set_mac_addr - Programs the Xframe mac address
4535 * @dev : pointer to the device structure.
4536 * @addr: a uchar pointer to the new mac address which is to be set.
4537 * Description : This procedure will program the Xframe to receive
4538 * frames with new Mac Address
4539 * Return value: SUCCESS on success and an appropriate (-)ve integer
4540 * as defined in errno.h file on failure.
4543 static int s2io_set_mac_addr(struct net_device *dev, u8 * addr)
4545 nic_t *sp = dev->priv;
4546 XENA_dev_config_t __iomem *bar0 = sp->bar0;
4547 register u64 val64, mac_addr = 0;
4551 * Set the new MAC address as the new unicast filter and reflect this
4552 * change on the device address registered with the OS. It will be
4555 for (i = 0; i < ETH_ALEN; i++) {
4557 mac_addr |= addr[i];
4560 writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr),
4561 &bar0->rmac_addr_data0_mem);
4564 RMAC_ADDR_CMD_MEM_WE | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4565 RMAC_ADDR_CMD_MEM_OFFSET(0);
4566 writeq(val64, &bar0->rmac_addr_cmd_mem);
4567 /* Wait till command completes */
4568 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
4569 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING)) {
4570 DBG_PRINT(ERR_DBG, "%s: set_mac_addr failed\n", dev->name);
4578 * s2io_ethtool_sset - Sets different link parameters.
4579 * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure.
4580 * @info: pointer to the structure with parameters given by ethtool to set
4583 * The function sets different link parameters provided by the user onto
4589 static int s2io_ethtool_sset(struct net_device *dev,
4590 struct ethtool_cmd *info)
4592 nic_t *sp = dev->priv;
4593 if ((info->autoneg == AUTONEG_ENABLE) ||
4594 (info->speed != SPEED_10000) || (info->duplex != DUPLEX_FULL))
4597 s2io_close(sp->dev);
4605 * s2io_ethtol_gset - Return link specific information.
4606 * @sp : private member of the device structure, pointer to the
4607 * s2io_nic structure.
4608 * @info : pointer to the structure with parameters given by ethtool
4609 * to return link information.
4611 * Returns link specific information like speed, duplex etc.. to ethtool.
4613 * return 0 on success.
4616 static int s2io_ethtool_gset(struct net_device *dev, struct ethtool_cmd *info)
4618 nic_t *sp = dev->priv;
4619 info->supported = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
4620 info->advertising = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
4621 info->port = PORT_FIBRE;
4622 /* info->transceiver?? TODO */
4624 if (netif_carrier_ok(sp->dev)) {
4625 info->speed = 10000;
4626 info->duplex = DUPLEX_FULL;
4632 info->autoneg = AUTONEG_DISABLE;
4637 * s2io_ethtool_gdrvinfo - Returns driver specific information.
4638 * @sp : private member of the device structure, which is a pointer to the
4639 * s2io_nic structure.
4640 * @info : pointer to the structure with parameters given by ethtool to
4641 * return driver information.
4643 * Returns driver specefic information like name, version etc.. to ethtool.
4648 static void s2io_ethtool_gdrvinfo(struct net_device *dev,
4649 struct ethtool_drvinfo *info)
4651 nic_t *sp = dev->priv;
4653 strncpy(info->driver, s2io_driver_name, sizeof(info->driver));
4654 strncpy(info->version, s2io_driver_version, sizeof(info->version));
4655 strncpy(info->fw_version, "", sizeof(info->fw_version));
4656 strncpy(info->bus_info, pci_name(sp->pdev), sizeof(info->bus_info));
4657 info->regdump_len = XENA_REG_SPACE;
4658 info->eedump_len = XENA_EEPROM_SPACE;
4659 info->testinfo_len = S2IO_TEST_LEN;
4660 info->n_stats = S2IO_STAT_LEN;
4664 * s2io_ethtool_gregs - dumps the entire space of Xfame into the buffer.
4665 * @sp: private member of the device structure, which is a pointer to the
4666 * s2io_nic structure.
4667 * @regs : pointer to the structure with parameters given by ethtool for
4668 * dumping the registers.
4669 * @reg_space: The input argumnet into which all the registers are dumped.
4671 * Dumps the entire register space of xFrame NIC into the user given
4677 static void s2io_ethtool_gregs(struct net_device *dev,
4678 struct ethtool_regs *regs, void *space)
4682 u8 *reg_space = (u8 *) space;
4683 nic_t *sp = dev->priv;
4685 regs->len = XENA_REG_SPACE;
4686 regs->version = sp->pdev->subsystem_device;
4688 for (i = 0; i < regs->len; i += 8) {
4689 reg = readq(sp->bar0 + i);
4690 memcpy((reg_space + i), ®, 8);
4695 * s2io_phy_id - timer function that alternates adapter LED.
4696 * @data : address of the private member of the device structure, which
4697 * is a pointer to the s2io_nic structure, provided as an u32.
4698 * Description: This is actually the timer function that alternates the
4699 * adapter LED bit of the adapter control bit to set/reset every time on
4700 * invocation. The timer is set for 1/2 a second, hence tha NIC blinks
4701 * once every second.
4703 static void s2io_phy_id(unsigned long data)
4705 nic_t *sp = (nic_t *) data;
4706 XENA_dev_config_t __iomem *bar0 = sp->bar0;
4710 subid = sp->pdev->subsystem_device;
4711 if ((sp->device_type == XFRAME_II_DEVICE) ||
4712 ((subid & 0xFF) >= 0x07)) {
4713 val64 = readq(&bar0->gpio_control);
4714 val64 ^= GPIO_CTRL_GPIO_0;
4715 writeq(val64, &bar0->gpio_control);
4717 val64 = readq(&bar0->adapter_control);
4718 val64 ^= ADAPTER_LED_ON;
4719 writeq(val64, &bar0->adapter_control);
4722 mod_timer(&sp->id_timer, jiffies + HZ / 2);
4726 * s2io_ethtool_idnic - To physically identify the nic on the system.
4727 * @sp : private member of the device structure, which is a pointer to the
4728 * s2io_nic structure.
4729 * @id : pointer to the structure with identification parameters given by
4731 * Description: Used to physically identify the NIC on the system.
4732 * The Link LED will blink for a time specified by the user for
4734 * NOTE: The Link has to be Up to be able to blink the LED. Hence
4735 * identification is possible only if it's link is up.
4737 * int , returns 0 on success
4740 static int s2io_ethtool_idnic(struct net_device *dev, u32 data)
4742 u64 val64 = 0, last_gpio_ctrl_val;
4743 nic_t *sp = dev->priv;
4744 XENA_dev_config_t __iomem *bar0 = sp->bar0;
4747 subid = sp->pdev->subsystem_device;
4748 last_gpio_ctrl_val = readq(&bar0->gpio_control);
4749 if ((sp->device_type == XFRAME_I_DEVICE) &&
4750 ((subid & 0xFF) < 0x07)) {
4751 val64 = readq(&bar0->adapter_control);
4752 if (!(val64 & ADAPTER_CNTL_EN)) {
4754 "Adapter Link down, cannot blink LED\n");
4758 if (sp->id_timer.function == NULL) {
4759 init_timer(&sp->id_timer);
4760 sp->id_timer.function = s2io_phy_id;
4761 sp->id_timer.data = (unsigned long) sp;
4763 mod_timer(&sp->id_timer, jiffies);
4765 msleep_interruptible(data * HZ);
4767 msleep_interruptible(MAX_FLICKER_TIME);
4768 del_timer_sync(&sp->id_timer);
4770 if (CARDS_WITH_FAULTY_LINK_INDICATORS(sp->device_type, subid)) {
4771 writeq(last_gpio_ctrl_val, &bar0->gpio_control);
4772 last_gpio_ctrl_val = readq(&bar0->gpio_control);
4779 * s2io_ethtool_getpause_data -Pause frame frame generation and reception.
4780 * @sp : private member of the device structure, which is a pointer to the
4781 * s2io_nic structure.
4782 * @ep : pointer to the structure with pause parameters given by ethtool.
4784 * Returns the Pause frame generation and reception capability of the NIC.
4788 static void s2io_ethtool_getpause_data(struct net_device *dev,
4789 struct ethtool_pauseparam *ep)
4792 nic_t *sp = dev->priv;
4793 XENA_dev_config_t __iomem *bar0 = sp->bar0;
4795 val64 = readq(&bar0->rmac_pause_cfg);
4796 if (val64 & RMAC_PAUSE_GEN_ENABLE)
4797 ep->tx_pause = TRUE;
4798 if (val64 & RMAC_PAUSE_RX_ENABLE)
4799 ep->rx_pause = TRUE;
4800 ep->autoneg = FALSE;
4804 * s2io_ethtool_setpause_data - set/reset pause frame generation.
4805 * @sp : private member of the device structure, which is a pointer to the
4806 * s2io_nic structure.
4807 * @ep : pointer to the structure with pause parameters given by ethtool.
4809 * It can be used to set or reset Pause frame generation or reception
4810 * support of the NIC.
4812 * int, returns 0 on Success
4815 static int s2io_ethtool_setpause_data(struct net_device *dev,
4816 struct ethtool_pauseparam *ep)
4819 nic_t *sp = dev->priv;
4820 XENA_dev_config_t __iomem *bar0 = sp->bar0;
4822 val64 = readq(&bar0->rmac_pause_cfg);
4824 val64 |= RMAC_PAUSE_GEN_ENABLE;
4826 val64 &= ~RMAC_PAUSE_GEN_ENABLE;
4828 val64 |= RMAC_PAUSE_RX_ENABLE;
4830 val64 &= ~RMAC_PAUSE_RX_ENABLE;
4831 writeq(val64, &bar0->rmac_pause_cfg);
4836 * read_eeprom - reads 4 bytes of data from user given offset.
4837 * @sp : private member of the device structure, which is a pointer to the
4838 * s2io_nic structure.
4839 * @off : offset at which the data must be written
4840 * @data : Its an output parameter where the data read at the given
4843 * Will read 4 bytes of data from the user given offset and return the
4845 * NOTE: Will allow to read only part of the EEPROM visible through the
4848 * -1 on failure and 0 on success.
4851 #define S2IO_DEV_ID 5
4852 static int read_eeprom(nic_t * sp, int off, u64 * data)
4857 XENA_dev_config_t __iomem *bar0 = sp->bar0;
4859 if (sp->device_type == XFRAME_I_DEVICE) {
4860 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) | I2C_CONTROL_ADDR(off) |
4861 I2C_CONTROL_BYTE_CNT(0x3) | I2C_CONTROL_READ |
4862 I2C_CONTROL_CNTL_START;
4863 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
4865 while (exit_cnt < 5) {
4866 val64 = readq(&bar0->i2c_control);
4867 if (I2C_CONTROL_CNTL_END(val64)) {
4868 *data = I2C_CONTROL_GET_DATA(val64);
4877 if (sp->device_type == XFRAME_II_DEVICE) {
4878 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
4879 SPI_CONTROL_BYTECNT(0x3) |
4880 SPI_CONTROL_CMD(0x3) | SPI_CONTROL_ADDR(off);
4881 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
4882 val64 |= SPI_CONTROL_REQ;
4883 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
4884 while (exit_cnt < 5) {
4885 val64 = readq(&bar0->spi_control);
4886 if (val64 & SPI_CONTROL_NACK) {
4889 } else if (val64 & SPI_CONTROL_DONE) {
4890 *data = readq(&bar0->spi_data);
4903 * write_eeprom - actually writes the relevant part of the data value.
4904 * @sp : private member of the device structure, which is a pointer to the
4905 * s2io_nic structure.
4906 * @off : offset at which the data must be written
4907 * @data : The data that is to be written
4908 * @cnt : Number of bytes of the data that are actually to be written into
4909 * the Eeprom. (max of 3)
4911 * Actually writes the relevant part of the data value into the Eeprom
4912 * through the I2C bus.
4914 * 0 on success, -1 on failure.
4917 static int write_eeprom(nic_t * sp, int off, u64 data, int cnt)
4919 int exit_cnt = 0, ret = -1;
4921 XENA_dev_config_t __iomem *bar0 = sp->bar0;
4923 if (sp->device_type == XFRAME_I_DEVICE) {
4924 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) | I2C_CONTROL_ADDR(off) |
4925 I2C_CONTROL_BYTE_CNT(cnt) | I2C_CONTROL_SET_DATA((u32)data) |
4926 I2C_CONTROL_CNTL_START;
4927 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
4929 while (exit_cnt < 5) {
4930 val64 = readq(&bar0->i2c_control);
4931 if (I2C_CONTROL_CNTL_END(val64)) {
4932 if (!(val64 & I2C_CONTROL_NACK))
4941 if (sp->device_type == XFRAME_II_DEVICE) {
4942 int write_cnt = (cnt == 8) ? 0 : cnt;
4943 writeq(SPI_DATA_WRITE(data,(cnt<<3)), &bar0->spi_data);
4945 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
4946 SPI_CONTROL_BYTECNT(write_cnt) |
4947 SPI_CONTROL_CMD(0x2) | SPI_CONTROL_ADDR(off);
4948 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
4949 val64 |= SPI_CONTROL_REQ;
4950 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
4951 while (exit_cnt < 5) {
4952 val64 = readq(&bar0->spi_control);
4953 if (val64 & SPI_CONTROL_NACK) {
4956 } else if (val64 & SPI_CONTROL_DONE) {
4966 static void s2io_vpd_read(nic_t *nic)
4970 int i=0, cnt, fail = 0;
4971 int vpd_addr = 0x80;
4973 if (nic->device_type == XFRAME_II_DEVICE) {
4974 strcpy(nic->product_name, "Xframe II 10GbE network adapter");
4978 strcpy(nic->product_name, "Xframe I 10GbE network adapter");
4981 strcpy(nic->serial_num, "NOT AVAILABLE");
4983 vpd_data = kmalloc(256, GFP_KERNEL);
4987 for (i = 0; i < 256; i +=4 ) {
4988 pci_write_config_byte(nic->pdev, (vpd_addr + 2), i);
4989 pci_read_config_byte(nic->pdev, (vpd_addr + 2), &data);
4990 pci_write_config_byte(nic->pdev, (vpd_addr + 3), 0);
4991 for (cnt = 0; cnt <5; cnt++) {
4993 pci_read_config_byte(nic->pdev, (vpd_addr + 3), &data);
4998 DBG_PRINT(ERR_DBG, "Read of VPD data failed\n");
5002 pci_read_config_dword(nic->pdev, (vpd_addr + 4),
5003 (u32 *)&vpd_data[i]);
5007 /* read serial number of adapter */
5008 for (cnt = 0; cnt < 256; cnt++) {
5009 if ((vpd_data[cnt] == 'S') &&
5010 (vpd_data[cnt+1] == 'N') &&
5011 (vpd_data[cnt+2] < VPD_STRING_LEN)) {
5012 memset(nic->serial_num, 0, VPD_STRING_LEN);
5013 memcpy(nic->serial_num, &vpd_data[cnt + 3],
5020 if ((!fail) && (vpd_data[1] < VPD_STRING_LEN)) {
5021 memset(nic->product_name, 0, vpd_data[1]);
5022 memcpy(nic->product_name, &vpd_data[3], vpd_data[1]);
5028 * s2io_ethtool_geeprom - reads the value stored in the Eeprom.
5029 * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure.
5030 * @eeprom : pointer to the user level structure provided by ethtool,
5031 * containing all relevant information.
5032 * @data_buf : user defined value to be written into Eeprom.
5033 * Description: Reads the values stored in the Eeprom at given offset
5034 * for a given length. Stores these values int the input argument data
5035 * buffer 'data_buf' and returns these to the caller (ethtool.)
5040 static int s2io_ethtool_geeprom(struct net_device *dev,
5041 struct ethtool_eeprom *eeprom, u8 * data_buf)
5045 nic_t *sp = dev->priv;
5047 eeprom->magic = sp->pdev->vendor | (sp->pdev->device << 16);
5049 if ((eeprom->offset + eeprom->len) > (XENA_EEPROM_SPACE))
5050 eeprom->len = XENA_EEPROM_SPACE - eeprom->offset;
5052 for (i = 0; i < eeprom->len; i += 4) {
5053 if (read_eeprom(sp, (eeprom->offset + i), &data)) {
5054 DBG_PRINT(ERR_DBG, "Read of EEPROM failed\n");
5058 memcpy((data_buf + i), &valid, 4);
5064 * s2io_ethtool_seeprom - tries to write the user provided value in Eeprom
5065 * @sp : private member of the device structure, which is a pointer to the
5066 * s2io_nic structure.
5067 * @eeprom : pointer to the user level structure provided by ethtool,
5068 * containing all relevant information.
5069 * @data_buf ; user defined value to be written into Eeprom.
5071 * Tries to write the user provided value in the Eeprom, at the offset
5072 * given by the user.
5074 * 0 on success, -EFAULT on failure.
5077 static int s2io_ethtool_seeprom(struct net_device *dev,
5078 struct ethtool_eeprom *eeprom,
5081 int len = eeprom->len, cnt = 0;
5082 u64 valid = 0, data;
5083 nic_t *sp = dev->priv;
5085 if (eeprom->magic != (sp->pdev->vendor | (sp->pdev->device << 16))) {
5087 "ETHTOOL_WRITE_EEPROM Err: Magic value ");
5088 DBG_PRINT(ERR_DBG, "is wrong, Its not 0x%x\n",
5094 data = (u32) data_buf[cnt] & 0x000000FF;
5096 valid = (u32) (data << 24);
5100 if (write_eeprom(sp, (eeprom->offset + cnt), valid, 0)) {
5102 "ETHTOOL_WRITE_EEPROM Err: Cannot ");
5104 "write into the specified offset\n");
5115 * s2io_register_test - reads and writes into all clock domains.
5116 * @sp : private member of the device structure, which is a pointer to the
5117 * s2io_nic structure.
5118 * @data : variable that returns the result of each of the test conducted b
5121 * Read and write into all clock domains. The NIC has 3 clock domains,
5122 * see that registers in all the three regions are accessible.
5127 static int s2io_register_test(nic_t * sp, uint64_t * data)
5129 XENA_dev_config_t __iomem *bar0 = sp->bar0;
5130 u64 val64 = 0, exp_val;
5133 val64 = readq(&bar0->pif_rd_swapper_fb);
5134 if (val64 != 0x123456789abcdefULL) {
5136 DBG_PRINT(INFO_DBG, "Read Test level 1 fails\n");
5139 val64 = readq(&bar0->rmac_pause_cfg);
5140 if (val64 != 0xc000ffff00000000ULL) {
5142 DBG_PRINT(INFO_DBG, "Read Test level 2 fails\n");
5145 val64 = readq(&bar0->rx_queue_cfg);
5146 if (sp->device_type == XFRAME_II_DEVICE)
5147 exp_val = 0x0404040404040404ULL;
5149 exp_val = 0x0808080808080808ULL;
5150 if (val64 != exp_val) {
5152 DBG_PRINT(INFO_DBG, "Read Test level 3 fails\n");
5155 val64 = readq(&bar0->xgxs_efifo_cfg);
5156 if (val64 != 0x000000001923141EULL) {
5158 DBG_PRINT(INFO_DBG, "Read Test level 4 fails\n");
5161 val64 = 0x5A5A5A5A5A5A5A5AULL;
5162 writeq(val64, &bar0->xmsi_data);
5163 val64 = readq(&bar0->xmsi_data);
5164 if (val64 != 0x5A5A5A5A5A5A5A5AULL) {
5166 DBG_PRINT(ERR_DBG, "Write Test level 1 fails\n");
5169 val64 = 0xA5A5A5A5A5A5A5A5ULL;
5170 writeq(val64, &bar0->xmsi_data);
5171 val64 = readq(&bar0->xmsi_data);
5172 if (val64 != 0xA5A5A5A5A5A5A5A5ULL) {
5174 DBG_PRINT(ERR_DBG, "Write Test level 2 fails\n");
5182 * s2io_eeprom_test - to verify that EEprom in the xena can be programmed.
5183 * @sp : private member of the device structure, which is a pointer to the
5184 * s2io_nic structure.
5185 * @data:variable that returns the result of each of the test conducted by
5188 * Verify that EEPROM in the xena can be programmed using I2C_CONTROL
5194 static int s2io_eeprom_test(nic_t * sp, uint64_t * data)
5197 u64 ret_data, org_4F0, org_7F0;
5198 u8 saved_4F0 = 0, saved_7F0 = 0;
5199 struct net_device *dev = sp->dev;
5201 /* Test Write Error at offset 0 */
5202 /* Note that SPI interface allows write access to all areas
5203 * of EEPROM. Hence doing all negative testing only for Xframe I.
5205 if (sp->device_type == XFRAME_I_DEVICE)
5206 if (!write_eeprom(sp, 0, 0, 3))
5209 /* Save current values at offsets 0x4F0 and 0x7F0 */
5210 if (!read_eeprom(sp, 0x4F0, &org_4F0))
5212 if (!read_eeprom(sp, 0x7F0, &org_7F0))
5215 /* Test Write at offset 4f0 */
5216 if (write_eeprom(sp, 0x4F0, 0x012345, 3))
5218 if (read_eeprom(sp, 0x4F0, &ret_data))
5221 if (ret_data != 0x012345) {
5222 DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x4F0. "
5223 "Data written %llx Data read %llx\n",
5224 dev->name, (unsigned long long)0x12345,
5225 (unsigned long long)ret_data);
5229 /* Reset the EEPROM data go FFFF */
5230 write_eeprom(sp, 0x4F0, 0xFFFFFF, 3);
5232 /* Test Write Request Error at offset 0x7c */
5233 if (sp->device_type == XFRAME_I_DEVICE)
5234 if (!write_eeprom(sp, 0x07C, 0, 3))
5237 /* Test Write Request at offset 0x7f0 */
5238 if (write_eeprom(sp, 0x7F0, 0x012345, 3))
5240 if (read_eeprom(sp, 0x7F0, &ret_data))
5243 if (ret_data != 0x012345) {
5244 DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x7F0. "
5245 "Data written %llx Data read %llx\n",
5246 dev->name, (unsigned long long)0x12345,
5247 (unsigned long long)ret_data);
5251 /* Reset the EEPROM data go FFFF */
5252 write_eeprom(sp, 0x7F0, 0xFFFFFF, 3);
5254 if (sp->device_type == XFRAME_I_DEVICE) {
5255 /* Test Write Error at offset 0x80 */
5256 if (!write_eeprom(sp, 0x080, 0, 3))
5259 /* Test Write Error at offset 0xfc */
5260 if (!write_eeprom(sp, 0x0FC, 0, 3))
5263 /* Test Write Error at offset 0x100 */
5264 if (!write_eeprom(sp, 0x100, 0, 3))
5267 /* Test Write Error at offset 4ec */
5268 if (!write_eeprom(sp, 0x4EC, 0, 3))
5272 /* Restore values at offsets 0x4F0 and 0x7F0 */
5274 write_eeprom(sp, 0x4F0, org_4F0, 3);
5276 write_eeprom(sp, 0x7F0, org_7F0, 3);
5283 * s2io_bist_test - invokes the MemBist test of the card .
5284 * @sp : private member of the device structure, which is a pointer to the
5285 * s2io_nic structure.
5286 * @data:variable that returns the result of each of the test conducted by
5289 * This invokes the MemBist test of the card. We give around
5290 * 2 secs time for the Test to complete. If it's still not complete
5291 * within this peiod, we consider that the test failed.
5293 * 0 on success and -1 on failure.
5296 static int s2io_bist_test(nic_t * sp, uint64_t * data)
5299 int cnt = 0, ret = -1;
5301 pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
5302 bist |= PCI_BIST_START;
5303 pci_write_config_word(sp->pdev, PCI_BIST, bist);
5306 pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
5307 if (!(bist & PCI_BIST_START)) {
5308 *data = (bist & PCI_BIST_CODE_MASK);
5320 * s2io-link_test - verifies the link state of the nic
5321 * @sp ; private member of the device structure, which is a pointer to the
5322 * s2io_nic structure.
5323 * @data: variable that returns the result of each of the test conducted by
5326 * The function verifies the link state of the NIC and updates the input
5327 * argument 'data' appropriately.
5332 static int s2io_link_test(nic_t * sp, uint64_t * data)
5334 XENA_dev_config_t __iomem *bar0 = sp->bar0;
5337 val64 = readq(&bar0->adapter_status);
5338 if(!(LINK_IS_UP(val64)))
5347 * s2io_rldram_test - offline test for access to the RldRam chip on the NIC
5348 * @sp - private member of the device structure, which is a pointer to the
5349 * s2io_nic structure.
5350 * @data - variable that returns the result of each of the test
5351 * conducted by the driver.
5353 * This is one of the offline test that tests the read and write
5354 * access to the RldRam chip on the NIC.
5359 static int s2io_rldram_test(nic_t * sp, uint64_t * data)
5361 XENA_dev_config_t __iomem *bar0 = sp->bar0;
5363 int cnt, iteration = 0, test_fail = 0;
5365 val64 = readq(&bar0->adapter_control);
5366 val64 &= ~ADAPTER_ECC_EN;
5367 writeq(val64, &bar0->adapter_control);
5369 val64 = readq(&bar0->mc_rldram_test_ctrl);
5370 val64 |= MC_RLDRAM_TEST_MODE;
5371 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
5373 val64 = readq(&bar0->mc_rldram_mrs);
5374 val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE;
5375 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
5377 val64 |= MC_RLDRAM_MRS_ENABLE;
5378 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
5380 while (iteration < 2) {
5381 val64 = 0x55555555aaaa0000ULL;
5382 if (iteration == 1) {
5383 val64 ^= 0xFFFFFFFFFFFF0000ULL;
5385 writeq(val64, &bar0->mc_rldram_test_d0);
5387 val64 = 0xaaaa5a5555550000ULL;
5388 if (iteration == 1) {
5389 val64 ^= 0xFFFFFFFFFFFF0000ULL;
5391 writeq(val64, &bar0->mc_rldram_test_d1);
5393 val64 = 0x55aaaaaaaa5a0000ULL;
5394 if (iteration == 1) {
5395 val64 ^= 0xFFFFFFFFFFFF0000ULL;
5397 writeq(val64, &bar0->mc_rldram_test_d2);
5399 val64 = (u64) (0x0000003ffffe0100ULL);
5400 writeq(val64, &bar0->mc_rldram_test_add);
5402 val64 = MC_RLDRAM_TEST_MODE | MC_RLDRAM_TEST_WRITE |
5404 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
5406 for (cnt = 0; cnt < 5; cnt++) {
5407 val64 = readq(&bar0->mc_rldram_test_ctrl);
5408 if (val64 & MC_RLDRAM_TEST_DONE)
5416 val64 = MC_RLDRAM_TEST_MODE | MC_RLDRAM_TEST_GO;
5417 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
5419 for (cnt = 0; cnt < 5; cnt++) {
5420 val64 = readq(&bar0->mc_rldram_test_ctrl);
5421 if (val64 & MC_RLDRAM_TEST_DONE)
5429 val64 = readq(&bar0->mc_rldram_test_ctrl);
5430 if (!(val64 & MC_RLDRAM_TEST_PASS))
5438 /* Bring the adapter out of test mode */
5439 SPECIAL_REG_WRITE(0, &bar0->mc_rldram_test_ctrl, LF);
5445 * s2io_ethtool_test - conducts 6 tsets to determine the health of card.
5446 * @sp : private member of the device structure, which is a pointer to the
5447 * s2io_nic structure.
5448 * @ethtest : pointer to a ethtool command specific structure that will be
5449 * returned to the user.
5450 * @data : variable that returns the result of each of the test
5451 * conducted by the driver.
5453 * This function conducts 6 tests ( 4 offline and 2 online) to determine
5454 * the health of the card.
5459 static void s2io_ethtool_test(struct net_device *dev,
5460 struct ethtool_test *ethtest,
5463 nic_t *sp = dev->priv;
5464 int orig_state = netif_running(sp->dev);
5466 if (ethtest->flags == ETH_TEST_FL_OFFLINE) {
5467 /* Offline Tests. */
5469 s2io_close(sp->dev);
5471 if (s2io_register_test(sp, &data[0]))
5472 ethtest->flags |= ETH_TEST_FL_FAILED;
5476 if (s2io_rldram_test(sp, &data[3]))
5477 ethtest->flags |= ETH_TEST_FL_FAILED;
5481 if (s2io_eeprom_test(sp, &data[1]))
5482 ethtest->flags |= ETH_TEST_FL_FAILED;
5484 if (s2io_bist_test(sp, &data[4]))
5485 ethtest->flags |= ETH_TEST_FL_FAILED;
5495 "%s: is not up, cannot run test\n",
5504 if (s2io_link_test(sp, &data[2]))
5505 ethtest->flags |= ETH_TEST_FL_FAILED;
5514 static void s2io_get_ethtool_stats(struct net_device *dev,
5515 struct ethtool_stats *estats,
5519 nic_t *sp = dev->priv;
5520 StatInfo_t *stat_info = sp->mac_control.stats_info;
5522 s2io_updt_stats(sp);
5524 (u64)le32_to_cpu(stat_info->tmac_frms_oflow) << 32 |
5525 le32_to_cpu(stat_info->tmac_frms);
5527 (u64)le32_to_cpu(stat_info->tmac_data_octets_oflow) << 32 |
5528 le32_to_cpu(stat_info->tmac_data_octets);
5529 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_drop_frms);
5531 (u64)le32_to_cpu(stat_info->tmac_mcst_frms_oflow) << 32 |
5532 le32_to_cpu(stat_info->tmac_mcst_frms);
5534 (u64)le32_to_cpu(stat_info->tmac_bcst_frms_oflow) << 32 |
5535 le32_to_cpu(stat_info->tmac_bcst_frms);
5536 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_pause_ctrl_frms);
5538 (u64)le32_to_cpu(stat_info->tmac_ttl_octets_oflow) << 32 |
5539 le32_to_cpu(stat_info->tmac_ttl_octets);
5541 (u64)le32_to_cpu(stat_info->tmac_ucst_frms_oflow) << 32 |
5542 le32_to_cpu(stat_info->tmac_ucst_frms);
5544 (u64)le32_to_cpu(stat_info->tmac_nucst_frms_oflow) << 32 |
5545 le32_to_cpu(stat_info->tmac_nucst_frms);
5547 (u64)le32_to_cpu(stat_info->tmac_any_err_frms_oflow) << 32 |
5548 le32_to_cpu(stat_info->tmac_any_err_frms);
5549 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_ttl_less_fb_octets);
5550 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_vld_ip_octets);
5552 (u64)le32_to_cpu(stat_info->tmac_vld_ip_oflow) << 32 |
5553 le32_to_cpu(stat_info->tmac_vld_ip);
5555 (u64)le32_to_cpu(stat_info->tmac_drop_ip_oflow) << 32 |
5556 le32_to_cpu(stat_info->tmac_drop_ip);
5558 (u64)le32_to_cpu(stat_info->tmac_icmp_oflow) << 32 |
5559 le32_to_cpu(stat_info->tmac_icmp);
5561 (u64)le32_to_cpu(stat_info->tmac_rst_tcp_oflow) << 32 |
5562 le32_to_cpu(stat_info->tmac_rst_tcp);
5563 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_tcp);
5564 tmp_stats[i++] = (u64)le32_to_cpu(stat_info->tmac_udp_oflow) << 32 |
5565 le32_to_cpu(stat_info->tmac_udp);
5567 (u64)le32_to_cpu(stat_info->rmac_vld_frms_oflow) << 32 |
5568 le32_to_cpu(stat_info->rmac_vld_frms);
5570 (u64)le32_to_cpu(stat_info->rmac_data_octets_oflow) << 32 |
5571 le32_to_cpu(stat_info->rmac_data_octets);
5572 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_fcs_err_frms);
5573 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_drop_frms);
5575 (u64)le32_to_cpu(stat_info->rmac_vld_mcst_frms_oflow) << 32 |
5576 le32_to_cpu(stat_info->rmac_vld_mcst_frms);
5578 (u64)le32_to_cpu(stat_info->rmac_vld_bcst_frms_oflow) << 32 |
5579 le32_to_cpu(stat_info->rmac_vld_bcst_frms);
5580 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_in_rng_len_err_frms);
5581 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_out_rng_len_err_frms);
5582 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_long_frms);
5583 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_pause_ctrl_frms);
5584 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_unsup_ctrl_frms);
5586 (u64)le32_to_cpu(stat_info->rmac_ttl_octets_oflow) << 32 |
5587 le32_to_cpu(stat_info->rmac_ttl_octets);
5589 (u64)le32_to_cpu(stat_info->rmac_accepted_ucst_frms_oflow)
5590 << 32 | le32_to_cpu(stat_info->rmac_accepted_ucst_frms);
5592 (u64)le32_to_cpu(stat_info->rmac_accepted_nucst_frms_oflow)
5593 << 32 | le32_to_cpu(stat_info->rmac_accepted_nucst_frms);
5595 (u64)le32_to_cpu(stat_info->rmac_discarded_frms_oflow) << 32 |
5596 le32_to_cpu(stat_info->rmac_discarded_frms);
5598 (u64)le32_to_cpu(stat_info->rmac_drop_events_oflow)
5599 << 32 | le32_to_cpu(stat_info->rmac_drop_events);
5600 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_less_fb_octets);
5601 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_frms);
5603 (u64)le32_to_cpu(stat_info->rmac_usized_frms_oflow) << 32 |
5604 le32_to_cpu(stat_info->rmac_usized_frms);
5606 (u64)le32_to_cpu(stat_info->rmac_osized_frms_oflow) << 32 |
5607 le32_to_cpu(stat_info->rmac_osized_frms);
5609 (u64)le32_to_cpu(stat_info->rmac_frag_frms_oflow) << 32 |
5610 le32_to_cpu(stat_info->rmac_frag_frms);
5612 (u64)le32_to_cpu(stat_info->rmac_jabber_frms_oflow) << 32 |
5613 le32_to_cpu(stat_info->rmac_jabber_frms);
5614 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_64_frms);
5615 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_65_127_frms);
5616 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_128_255_frms);
5617 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_256_511_frms);
5618 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_512_1023_frms);
5619 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_1024_1518_frms);
5621 (u64)le32_to_cpu(stat_info->rmac_ip_oflow) << 32 |
5622 le32_to_cpu(stat_info->rmac_ip);
5623 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ip_octets);
5624 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_hdr_err_ip);
5626 (u64)le32_to_cpu(stat_info->rmac_drop_ip_oflow) << 32 |
5627 le32_to_cpu(stat_info->rmac_drop_ip);
5629 (u64)le32_to_cpu(stat_info->rmac_icmp_oflow) << 32 |
5630 le32_to_cpu(stat_info->rmac_icmp);
5631 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_tcp);
5633 (u64)le32_to_cpu(stat_info->rmac_udp_oflow) << 32 |
5634 le32_to_cpu(stat_info->rmac_udp);
5636 (u64)le32_to_cpu(stat_info->rmac_err_drp_udp_oflow) << 32 |
5637 le32_to_cpu(stat_info->rmac_err_drp_udp);
5638 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_xgmii_err_sym);
5639 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q0);
5640 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q1);
5641 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q2);
5642 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q3);
5643 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q4);
5644 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q5);
5645 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q6);
5646 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q7);
5647 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q0);
5648 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q1);
5649 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q2);
5650 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q3);
5651 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q4);
5652 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q5);
5653 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q6);
5654 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q7);
5656 (u64)le32_to_cpu(stat_info->rmac_pause_cnt_oflow) << 32 |
5657 le32_to_cpu(stat_info->rmac_pause_cnt);
5658 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_xgmii_data_err_cnt);
5659 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_xgmii_ctrl_err_cnt);
5661 (u64)le32_to_cpu(stat_info->rmac_accepted_ip_oflow) << 32 |
5662 le32_to_cpu(stat_info->rmac_accepted_ip);
5663 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_err_tcp);
5664 tmp_stats[i++] = le32_to_cpu(stat_info->rd_req_cnt);
5665 tmp_stats[i++] = le32_to_cpu(stat_info->new_rd_req_cnt);
5666 tmp_stats[i++] = le32_to_cpu(stat_info->new_rd_req_rtry_cnt);
5667 tmp_stats[i++] = le32_to_cpu(stat_info->rd_rtry_cnt);
5668 tmp_stats[i++] = le32_to_cpu(stat_info->wr_rtry_rd_ack_cnt);
5669 tmp_stats[i++] = le32_to_cpu(stat_info->wr_req_cnt);
5670 tmp_stats[i++] = le32_to_cpu(stat_info->new_wr_req_cnt);
5671 tmp_stats[i++] = le32_to_cpu(stat_info->new_wr_req_rtry_cnt);
5672 tmp_stats[i++] = le32_to_cpu(stat_info->wr_rtry_cnt);
5673 tmp_stats[i++] = le32_to_cpu(stat_info->wr_disc_cnt);
5674 tmp_stats[i++] = le32_to_cpu(stat_info->rd_rtry_wr_ack_cnt);
5675 tmp_stats[i++] = le32_to_cpu(stat_info->txp_wr_cnt);
5676 tmp_stats[i++] = le32_to_cpu(stat_info->txd_rd_cnt);
5677 tmp_stats[i++] = le32_to_cpu(stat_info->txd_wr_cnt);
5678 tmp_stats[i++] = le32_to_cpu(stat_info->rxd_rd_cnt);
5679 tmp_stats[i++] = le32_to_cpu(stat_info->rxd_wr_cnt);
5680 tmp_stats[i++] = le32_to_cpu(stat_info->txf_rd_cnt);
5681 tmp_stats[i++] = le32_to_cpu(stat_info->rxf_wr_cnt);
5682 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_1519_4095_frms);
5683 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_4096_8191_frms);
5684 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_8192_max_frms);
5685 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_gt_max_frms);
5686 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_osized_alt_frms);
5687 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_jabber_alt_frms);
5688 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_gt_max_alt_frms);
5689 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_vlan_frms);
5690 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_len_discard);
5691 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_fcs_discard);
5692 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_pf_discard);
5693 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_da_discard);
5694 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_red_discard);
5695 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_rts_discard);
5696 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_ingm_full_discard);
5697 tmp_stats[i++] = le32_to_cpu(stat_info->link_fault_cnt);
5699 tmp_stats[i++] = stat_info->sw_stat.single_ecc_errs;
5700 tmp_stats[i++] = stat_info->sw_stat.double_ecc_errs;
5701 tmp_stats[i++] = stat_info->sw_stat.parity_err_cnt;
5702 tmp_stats[i++] = stat_info->sw_stat.serious_err_cnt;
5703 tmp_stats[i++] = stat_info->sw_stat.soft_reset_cnt;
5704 tmp_stats[i++] = stat_info->sw_stat.fifo_full_cnt;
5705 tmp_stats[i++] = stat_info->sw_stat.ring_full_cnt;
5706 tmp_stats[i++] = stat_info->xpak_stat.alarm_transceiver_temp_high;
5707 tmp_stats[i++] = stat_info->xpak_stat.alarm_transceiver_temp_low;
5708 tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_bias_current_high;
5709 tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_bias_current_low;
5710 tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_output_power_high;
5711 tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_output_power_low;
5712 tmp_stats[i++] = stat_info->xpak_stat.warn_transceiver_temp_high;
5713 tmp_stats[i++] = stat_info->xpak_stat.warn_transceiver_temp_low;
5714 tmp_stats[i++] = stat_info->xpak_stat.warn_laser_bias_current_high;
5715 tmp_stats[i++] = stat_info->xpak_stat.warn_laser_bias_current_low;
5716 tmp_stats[i++] = stat_info->xpak_stat.warn_laser_output_power_high;
5717 tmp_stats[i++] = stat_info->xpak_stat.warn_laser_output_power_low;
5718 tmp_stats[i++] = stat_info->sw_stat.clubbed_frms_cnt;
5719 tmp_stats[i++] = stat_info->sw_stat.sending_both;
5720 tmp_stats[i++] = stat_info->sw_stat.outof_sequence_pkts;
5721 tmp_stats[i++] = stat_info->sw_stat.flush_max_pkts;
5722 if (stat_info->sw_stat.num_aggregations) {
5723 u64 tmp = stat_info->sw_stat.sum_avg_pkts_aggregated;
5726 * Since 64-bit divide does not work on all platforms,
5727 * do repeated subtraction.
5729 while (tmp >= stat_info->sw_stat.num_aggregations) {
5730 tmp -= stat_info->sw_stat.num_aggregations;
5733 tmp_stats[i++] = count;
5739 static int s2io_ethtool_get_regs_len(struct net_device *dev)
5741 return (XENA_REG_SPACE);
5745 static u32 s2io_ethtool_get_rx_csum(struct net_device * dev)
5747 nic_t *sp = dev->priv;
5749 return (sp->rx_csum);
5752 static int s2io_ethtool_set_rx_csum(struct net_device *dev, u32 data)
5754 nic_t *sp = dev->priv;
5764 static int s2io_get_eeprom_len(struct net_device *dev)
5766 return (XENA_EEPROM_SPACE);
5769 static int s2io_ethtool_self_test_count(struct net_device *dev)
5771 return (S2IO_TEST_LEN);
5774 static void s2io_ethtool_get_strings(struct net_device *dev,
5775 u32 stringset, u8 * data)
5777 switch (stringset) {
5779 memcpy(data, s2io_gstrings, S2IO_STRINGS_LEN);
5782 memcpy(data, ðtool_stats_keys,
5783 sizeof(ethtool_stats_keys));
5786 static int s2io_ethtool_get_stats_count(struct net_device *dev)
5788 return (S2IO_STAT_LEN);
5791 static int s2io_ethtool_op_set_tx_csum(struct net_device *dev, u32 data)
5794 dev->features |= NETIF_F_IP_CSUM;
5796 dev->features &= ~NETIF_F_IP_CSUM;
5801 static u32 s2io_ethtool_op_get_tso(struct net_device *dev)
5803 return (dev->features & NETIF_F_TSO) != 0;
5805 static int s2io_ethtool_op_set_tso(struct net_device *dev, u32 data)
5808 dev->features |= (NETIF_F_TSO | NETIF_F_TSO6);
5810 dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
5815 static const struct ethtool_ops netdev_ethtool_ops = {
5816 .get_settings = s2io_ethtool_gset,
5817 .set_settings = s2io_ethtool_sset,
5818 .get_drvinfo = s2io_ethtool_gdrvinfo,
5819 .get_regs_len = s2io_ethtool_get_regs_len,
5820 .get_regs = s2io_ethtool_gregs,
5821 .get_link = ethtool_op_get_link,
5822 .get_eeprom_len = s2io_get_eeprom_len,
5823 .get_eeprom = s2io_ethtool_geeprom,
5824 .set_eeprom = s2io_ethtool_seeprom,
5825 .get_pauseparam = s2io_ethtool_getpause_data,
5826 .set_pauseparam = s2io_ethtool_setpause_data,
5827 .get_rx_csum = s2io_ethtool_get_rx_csum,
5828 .set_rx_csum = s2io_ethtool_set_rx_csum,
5829 .get_tx_csum = ethtool_op_get_tx_csum,
5830 .set_tx_csum = s2io_ethtool_op_set_tx_csum,
5831 .get_sg = ethtool_op_get_sg,
5832 .set_sg = ethtool_op_set_sg,
5833 .get_tso = s2io_ethtool_op_get_tso,
5834 .set_tso = s2io_ethtool_op_set_tso,
5835 .get_ufo = ethtool_op_get_ufo,
5836 .set_ufo = ethtool_op_set_ufo,
5837 .self_test_count = s2io_ethtool_self_test_count,
5838 .self_test = s2io_ethtool_test,
5839 .get_strings = s2io_ethtool_get_strings,
5840 .phys_id = s2io_ethtool_idnic,
5841 .get_stats_count = s2io_ethtool_get_stats_count,
5842 .get_ethtool_stats = s2io_get_ethtool_stats
5846 * s2io_ioctl - Entry point for the Ioctl
5847 * @dev : Device pointer.
5848 * @ifr : An IOCTL specefic structure, that can contain a pointer to
5849 * a proprietary structure used to pass information to the driver.
5850 * @cmd : This is used to distinguish between the different commands that
5851 * can be passed to the IOCTL functions.
5853 * Currently there are no special functionality supported in IOCTL, hence
5854 * function always return EOPNOTSUPPORTED
5857 static int s2io_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
5863 * s2io_change_mtu - entry point to change MTU size for the device.
5864 * @dev : device pointer.
5865 * @new_mtu : the new MTU size for the device.
5866 * Description: A driver entry point to change MTU size for the device.
5867 * Before changing the MTU the device must be stopped.
5869 * 0 on success and an appropriate (-)ve integer as defined in errno.h
5873 static int s2io_change_mtu(struct net_device *dev, int new_mtu)
5875 nic_t *sp = dev->priv;
5877 if ((new_mtu < MIN_MTU) || (new_mtu > S2IO_JUMBO_SIZE)) {
5878 DBG_PRINT(ERR_DBG, "%s: MTU size is invalid.\n",
5884 if (netif_running(dev)) {
5886 netif_stop_queue(dev);
5887 if (s2io_card_up(sp)) {
5888 DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n",
5891 if (netif_queue_stopped(dev))
5892 netif_wake_queue(dev);
5893 } else { /* Device is down */
5894 XENA_dev_config_t __iomem *bar0 = sp->bar0;
5895 u64 val64 = new_mtu;
5897 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
5904 * s2io_tasklet - Bottom half of the ISR.
5905 * @dev_adr : address of the device structure in dma_addr_t format.
5907 * This is the tasklet or the bottom half of the ISR. This is
5908 * an extension of the ISR which is scheduled by the scheduler to be run
5909 * when the load on the CPU is low. All low priority tasks of the ISR can
5910 * be pushed into the tasklet. For now the tasklet is used only to
5911 * replenish the Rx buffers in the Rx buffer descriptors.
5916 static void s2io_tasklet(unsigned long dev_addr)
5918 struct net_device *dev = (struct net_device *) dev_addr;
5919 nic_t *sp = dev->priv;
5921 mac_info_t *mac_control;
5922 struct config_param *config;
5924 mac_control = &sp->mac_control;
5925 config = &sp->config;
5927 if (!TASKLET_IN_USE) {
5928 for (i = 0; i < config->rx_ring_num; i++) {
5929 ret = fill_rx_buffers(sp, i);
5930 if (ret == -ENOMEM) {
5931 DBG_PRINT(ERR_DBG, "%s: Out of ",
5933 DBG_PRINT(ERR_DBG, "memory in tasklet\n");
5935 } else if (ret == -EFILL) {
5937 "%s: Rx Ring %d is full\n",
5942 clear_bit(0, (&sp->tasklet_status));
5947 * s2io_set_link - Set the LInk status
5948 * @data: long pointer to device private structue
5949 * Description: Sets the link status for the adapter
5952 static void s2io_set_link(struct work_struct *work)
5954 nic_t *nic = container_of(work, nic_t, set_link_task);
5955 struct net_device *dev = nic->dev;
5956 XENA_dev_config_t __iomem *bar0 = nic->bar0;
5960 if (test_and_set_bit(0, &(nic->link_state))) {
5961 /* The card is being reset, no point doing anything */
5965 subid = nic->pdev->subsystem_device;
5966 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
5968 * Allow a small delay for the NICs self initiated
5969 * cleanup to complete.
5974 val64 = readq(&bar0->adapter_status);
5975 if (LINK_IS_UP(val64)) {
5976 if (!(readq(&bar0->adapter_control) & ADAPTER_CNTL_EN)) {
5977 if (verify_xena_quiescence(nic)) {
5978 val64 = readq(&bar0->adapter_control);
5979 val64 |= ADAPTER_CNTL_EN;
5980 writeq(val64, &bar0->adapter_control);
5981 if (CARDS_WITH_FAULTY_LINK_INDICATORS(
5982 nic->device_type, subid)) {
5983 val64 = readq(&bar0->gpio_control);
5984 val64 |= GPIO_CTRL_GPIO_0;
5985 writeq(val64, &bar0->gpio_control);
5986 val64 = readq(&bar0->gpio_control);
5988 val64 |= ADAPTER_LED_ON;
5989 writeq(val64, &bar0->adapter_control);
5991 nic->device_enabled_once = TRUE;
5993 DBG_PRINT(ERR_DBG, "%s: Error: ", dev->name);
5994 DBG_PRINT(ERR_DBG, "device is not Quiescent\n");
5995 netif_stop_queue(dev);
5998 val64 = readq(&bar0->adapter_status);
5999 if (!LINK_IS_UP(val64)) {
6000 DBG_PRINT(ERR_DBG, "%s:", dev->name);
6001 DBG_PRINT(ERR_DBG, " Link down after enabling ");
6002 DBG_PRINT(ERR_DBG, "device \n");
6004 s2io_link(nic, LINK_UP);
6006 if (CARDS_WITH_FAULTY_LINK_INDICATORS(nic->device_type,
6008 val64 = readq(&bar0->gpio_control);
6009 val64 &= ~GPIO_CTRL_GPIO_0;
6010 writeq(val64, &bar0->gpio_control);
6011 val64 = readq(&bar0->gpio_control);
6013 s2io_link(nic, LINK_DOWN);
6015 clear_bit(0, &(nic->link_state));
6018 static int set_rxd_buffer_pointer(nic_t *sp, RxD_t *rxdp, buffAdd_t *ba,
6019 struct sk_buff **skb, u64 *temp0, u64 *temp1,
6020 u64 *temp2, int size)
6022 struct net_device *dev = sp->dev;
6023 struct sk_buff *frag_list;
6025 if ((sp->rxd_mode == RXD_MODE_1) && (rxdp->Host_Control == 0)) {
6028 DBG_PRINT(INFO_DBG, "SKB is not NULL\n");
6030 * As Rx frame are not going to be processed,
6031 * using same mapped address for the Rxd
6034 ((RxD1_t*)rxdp)->Buffer0_ptr = *temp0;
6036 *skb = dev_alloc_skb(size);
6038 DBG_PRINT(ERR_DBG, "%s: Out of ", dev->name);
6039 DBG_PRINT(ERR_DBG, "memory to allocate SKBs\n");
6042 /* storing the mapped addr in a temp variable
6043 * such it will be used for next rxd whose
6044 * Host Control is NULL
6046 ((RxD1_t*)rxdp)->Buffer0_ptr = *temp0 =
6047 pci_map_single( sp->pdev, (*skb)->data,
6048 size - NET_IP_ALIGN,
6049 PCI_DMA_FROMDEVICE);
6050 rxdp->Host_Control = (unsigned long) (*skb);
6052 } else if ((sp->rxd_mode == RXD_MODE_3B) && (rxdp->Host_Control == 0)) {
6053 /* Two buffer Mode */
6055 ((RxD3_t*)rxdp)->Buffer2_ptr = *temp2;
6056 ((RxD3_t*)rxdp)->Buffer0_ptr = *temp0;
6057 ((RxD3_t*)rxdp)->Buffer1_ptr = *temp1;
6059 *skb = dev_alloc_skb(size);
6061 DBG_PRINT(ERR_DBG, "%s: dev_alloc_skb failed\n",
6065 ((RxD3_t*)rxdp)->Buffer2_ptr = *temp2 =
6066 pci_map_single(sp->pdev, (*skb)->data,
6068 PCI_DMA_FROMDEVICE);
6069 ((RxD3_t*)rxdp)->Buffer0_ptr = *temp0 =
6070 pci_map_single( sp->pdev, ba->ba_0, BUF0_LEN,
6071 PCI_DMA_FROMDEVICE);
6072 rxdp->Host_Control = (unsigned long) (*skb);
6074 /* Buffer-1 will be dummy buffer not used */
6075 ((RxD3_t*)rxdp)->Buffer1_ptr = *temp1 =
6076 pci_map_single(sp->pdev, ba->ba_1, BUF1_LEN,
6077 PCI_DMA_FROMDEVICE);
6079 } else if ((rxdp->Host_Control == 0)) {
6080 /* Three buffer mode */
6082 ((RxD3_t*)rxdp)->Buffer0_ptr = *temp0;
6083 ((RxD3_t*)rxdp)->Buffer1_ptr = *temp1;
6084 ((RxD3_t*)rxdp)->Buffer2_ptr = *temp2;
6086 *skb = dev_alloc_skb(size);
6088 DBG_PRINT(ERR_DBG, "%s: dev_alloc_skb failed\n",
6092 ((RxD3_t*)rxdp)->Buffer0_ptr = *temp0 =
6093 pci_map_single(sp->pdev, ba->ba_0, BUF0_LEN,
6094 PCI_DMA_FROMDEVICE);
6095 /* Buffer-1 receives L3/L4 headers */
6096 ((RxD3_t*)rxdp)->Buffer1_ptr = *temp1 =
6097 pci_map_single( sp->pdev, (*skb)->data,
6099 PCI_DMA_FROMDEVICE);
6101 * skb_shinfo(skb)->frag_list will have L4
6104 skb_shinfo(*skb)->frag_list = dev_alloc_skb(dev->mtu +
6106 if (skb_shinfo(*skb)->frag_list == NULL) {
6107 DBG_PRINT(ERR_DBG, "%s: dev_alloc_skb \
6108 failed\n ", dev->name);
6111 frag_list = skb_shinfo(*skb)->frag_list;
6112 frag_list->next = NULL;
6114 * Buffer-2 receives L4 data payload
6116 ((RxD3_t*)rxdp)->Buffer2_ptr = *temp2 =
6117 pci_map_single( sp->pdev, frag_list->data,
6118 dev->mtu, PCI_DMA_FROMDEVICE);
6123 static void set_rxd_buffer_size(nic_t *sp, RxD_t *rxdp, int size)
6125 struct net_device *dev = sp->dev;
6126 if (sp->rxd_mode == RXD_MODE_1) {
6127 rxdp->Control_2 = SET_BUFFER0_SIZE_1( size - NET_IP_ALIGN);
6128 } else if (sp->rxd_mode == RXD_MODE_3B) {
6129 rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
6130 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
6131 rxdp->Control_2 |= SET_BUFFER2_SIZE_3( dev->mtu + 4);
6133 rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
6134 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(l3l4hdr_size + 4);
6135 rxdp->Control_2 |= SET_BUFFER2_SIZE_3(dev->mtu);
6139 static int rxd_owner_bit_reset(nic_t *sp)
6141 int i, j, k, blk_cnt = 0, size;
6142 mac_info_t * mac_control = &sp->mac_control;
6143 struct config_param *config = &sp->config;
6144 struct net_device *dev = sp->dev;
6146 struct sk_buff *skb = NULL;
6147 buffAdd_t *ba = NULL;
6148 u64 temp0_64 = 0, temp1_64 = 0, temp2_64 = 0;
6150 /* Calculate the size based on ring mode */
6151 size = dev->mtu + HEADER_ETHERNET_II_802_3_SIZE +
6152 HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
6153 if (sp->rxd_mode == RXD_MODE_1)
6154 size += NET_IP_ALIGN;
6155 else if (sp->rxd_mode == RXD_MODE_3B)
6156 size = dev->mtu + ALIGN_SIZE + BUF0_LEN + 4;
6158 size = l3l4hdr_size + ALIGN_SIZE + BUF0_LEN + 4;
6160 for (i = 0; i < config->rx_ring_num; i++) {
6161 blk_cnt = config->rx_cfg[i].num_rxd /
6162 (rxd_count[sp->rxd_mode] +1);
6164 for (j = 0; j < blk_cnt; j++) {
6165 for (k = 0; k < rxd_count[sp->rxd_mode]; k++) {
6166 rxdp = mac_control->rings[i].
6167 rx_blocks[j].rxds[k].virt_addr;
6168 if(sp->rxd_mode >= RXD_MODE_3A)
6169 ba = &mac_control->rings[i].ba[j][k];
6170 set_rxd_buffer_pointer(sp, rxdp, ba,
6171 &skb,(u64 *)&temp0_64,
6173 (u64 *)&temp2_64, size);
6175 set_rxd_buffer_size(sp, rxdp, size);
6177 /* flip the Ownership bit to Hardware */
6178 rxdp->Control_1 |= RXD_OWN_XENA;
6186 static int s2io_add_isr(nic_t * sp)
6189 struct net_device *dev = sp->dev;
6192 if (sp->intr_type == MSI)
6193 ret = s2io_enable_msi(sp);
6194 else if (sp->intr_type == MSI_X)
6195 ret = s2io_enable_msi_x(sp);
6197 DBG_PRINT(ERR_DBG, "%s: Defaulting to INTA\n", dev->name);
6198 sp->intr_type = INTA;
6201 /* Store the values of the MSIX table in the nic_t structure */
6202 store_xmsi_data(sp);
6204 /* After proper initialization of H/W, register ISR */
6205 if (sp->intr_type == MSI) {
6206 err = request_irq((int) sp->pdev->irq, s2io_msi_handle,
6207 IRQF_SHARED, sp->name, dev);
6209 pci_disable_msi(sp->pdev);
6210 DBG_PRINT(ERR_DBG, "%s: MSI registration failed\n",
6215 if (sp->intr_type == MSI_X) {
6218 for (i=1; (sp->s2io_entries[i].in_use == MSIX_FLG); i++) {
6219 if (sp->s2io_entries[i].type == MSIX_FIFO_TYPE) {
6220 sprintf(sp->desc[i], "%s:MSI-X-%d-TX",
6222 err = request_irq(sp->entries[i].vector,
6223 s2io_msix_fifo_handle, 0, sp->desc[i],
6224 sp->s2io_entries[i].arg);
6225 DBG_PRINT(ERR_DBG, "%s @ 0x%llx\n", sp->desc[i],
6226 (unsigned long long)sp->msix_info[i].addr);
6228 sprintf(sp->desc[i], "%s:MSI-X-%d-RX",
6230 err = request_irq(sp->entries[i].vector,
6231 s2io_msix_ring_handle, 0, sp->desc[i],
6232 sp->s2io_entries[i].arg);
6233 DBG_PRINT(ERR_DBG, "%s @ 0x%llx\n", sp->desc[i],
6234 (unsigned long long)sp->msix_info[i].addr);
6237 DBG_PRINT(ERR_DBG,"%s:MSI-X-%d registration "
6238 "failed\n", dev->name, i);
6239 DBG_PRINT(ERR_DBG, "Returned: %d\n", err);
6242 sp->s2io_entries[i].in_use = MSIX_REGISTERED_SUCCESS;
6245 if (sp->intr_type == INTA) {
6246 err = request_irq((int) sp->pdev->irq, s2io_isr, IRQF_SHARED,
6249 DBG_PRINT(ERR_DBG, "%s: ISR registration failed\n",
6256 static void s2io_rem_isr(nic_t * sp)
6259 struct net_device *dev = sp->dev;
6261 if (sp->intr_type == MSI_X) {
6265 for (i=1; (sp->s2io_entries[i].in_use ==
6266 MSIX_REGISTERED_SUCCESS); i++) {
6267 int vector = sp->entries[i].vector;
6268 void *arg = sp->s2io_entries[i].arg;
6270 free_irq(vector, arg);
6272 pci_read_config_word(sp->pdev, 0x42, &msi_control);
6273 msi_control &= 0xFFFE; /* Disable MSI */
6274 pci_write_config_word(sp->pdev, 0x42, msi_control);
6276 pci_disable_msix(sp->pdev);
6278 free_irq(sp->pdev->irq, dev);
6279 if (sp->intr_type == MSI) {
6282 pci_disable_msi(sp->pdev);
6283 pci_read_config_word(sp->pdev, 0x4c, &val);
6285 pci_write_config_word(sp->pdev, 0x4c, val);
6288 /* Waiting till all Interrupt handlers are complete */
6292 if (!atomic_read(&sp->isr_cnt))
6298 static void s2io_card_down(nic_t * sp)
6301 XENA_dev_config_t __iomem *bar0 = sp->bar0;
6302 unsigned long flags;
6303 register u64 val64 = 0;
6305 del_timer_sync(&sp->alarm_timer);
6306 /* If s2io_set_link task is executing, wait till it completes. */
6307 while (test_and_set_bit(0, &(sp->link_state))) {
6310 atomic_set(&sp->card_state, CARD_DOWN);
6312 /* disable Tx and Rx traffic on the NIC */
6318 tasklet_kill(&sp->task);
6320 /* Check if the device is Quiescent and then Reset the NIC */
6322 /* As per the HW requirement we need to replenish the
6323 * receive buffer to avoid the ring bump. Since there is
6324 * no intention of processing the Rx frame at this pointwe are
6325 * just settting the ownership bit of rxd in Each Rx
6326 * ring to HW and set the appropriate buffer size
6327 * based on the ring mode
6329 rxd_owner_bit_reset(sp);
6331 val64 = readq(&bar0->adapter_status);
6332 if (verify_xena_quiescence(sp)) {
6333 if(verify_pcc_quiescent(sp, sp->device_enabled_once))
6341 "s2io_close:Device not Quiescent ");
6342 DBG_PRINT(ERR_DBG, "adaper status reads 0x%llx\n",
6343 (unsigned long long) val64);
6349 spin_lock_irqsave(&sp->tx_lock, flags);
6350 /* Free all Tx buffers */
6351 free_tx_buffers(sp);
6352 spin_unlock_irqrestore(&sp->tx_lock, flags);
6354 /* Free all Rx buffers */
6355 spin_lock_irqsave(&sp->rx_lock, flags);
6356 free_rx_buffers(sp);
6357 spin_unlock_irqrestore(&sp->rx_lock, flags);
6359 clear_bit(0, &(sp->link_state));
6362 static int s2io_card_up(nic_t * sp)
6365 mac_info_t *mac_control;
6366 struct config_param *config;
6367 struct net_device *dev = (struct net_device *) sp->dev;
6370 /* Initialize the H/W I/O registers */
6371 if (init_nic(sp) != 0) {
6372 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
6379 * Initializing the Rx buffers. For now we are considering only 1
6380 * Rx ring and initializing buffers into 30 Rx blocks
6382 mac_control = &sp->mac_control;
6383 config = &sp->config;
6385 for (i = 0; i < config->rx_ring_num; i++) {
6386 if ((ret = fill_rx_buffers(sp, i))) {
6387 DBG_PRINT(ERR_DBG, "%s: Out of memory in Open\n",
6390 free_rx_buffers(sp);
6393 DBG_PRINT(INFO_DBG, "Buf in ring:%d is %d:\n", i,
6394 atomic_read(&sp->rx_bufs_left[i]));
6396 /* Maintain the state prior to the open */
6397 if (sp->promisc_flg)
6398 sp->promisc_flg = 0;
6399 if (sp->m_cast_flg) {
6401 sp->all_multi_pos= 0;
6404 /* Setting its receive mode */
6405 s2io_set_multicast(dev);
6408 /* Initialize max aggregatable pkts per session based on MTU */
6409 sp->lro_max_aggr_per_sess = ((1<<16) - 1) / dev->mtu;
6410 /* Check if we can use(if specified) user provided value */
6411 if (lro_max_pkts < sp->lro_max_aggr_per_sess)
6412 sp->lro_max_aggr_per_sess = lro_max_pkts;
6415 /* Enable Rx Traffic and interrupts on the NIC */
6416 if (start_nic(sp)) {
6417 DBG_PRINT(ERR_DBG, "%s: Starting NIC failed\n", dev->name);
6419 free_rx_buffers(sp);
6423 /* Add interrupt service routine */
6424 if (s2io_add_isr(sp) != 0) {
6425 if (sp->intr_type == MSI_X)
6428 free_rx_buffers(sp);
6432 S2IO_TIMER_CONF(sp->alarm_timer, s2io_alarm_handle, sp, (HZ/2));
6434 /* Enable tasklet for the device */
6435 tasklet_init(&sp->task, s2io_tasklet, (unsigned long) dev);
6437 /* Enable select interrupts */
6438 if (sp->intr_type != INTA)
6439 en_dis_able_nic_intrs(sp, ENA_ALL_INTRS, DISABLE_INTRS);
6441 interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
6442 interruptible |= TX_PIC_INTR | RX_PIC_INTR;
6443 interruptible |= TX_MAC_INTR | RX_MAC_INTR;
6444 en_dis_able_nic_intrs(sp, interruptible, ENABLE_INTRS);
6448 atomic_set(&sp->card_state, CARD_UP);
6453 * s2io_restart_nic - Resets the NIC.
6454 * @data : long pointer to the device private structure
6456 * This function is scheduled to be run by the s2io_tx_watchdog
6457 * function after 0.5 secs to reset the NIC. The idea is to reduce
6458 * the run time of the watch dog routine which is run holding a
6462 static void s2io_restart_nic(struct work_struct *work)
6464 nic_t *sp = container_of(work, nic_t, rst_timer_task);
6465 struct net_device *dev = sp->dev;
6468 if (s2io_card_up(sp)) {
6469 DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n",
6472 netif_wake_queue(dev);
6473 DBG_PRINT(ERR_DBG, "%s: was reset by Tx watchdog timer\n",
6479 * s2io_tx_watchdog - Watchdog for transmit side.
6480 * @dev : Pointer to net device structure
6482 * This function is triggered if the Tx Queue is stopped
6483 * for a pre-defined amount of time when the Interface is still up.
6484 * If the Interface is jammed in such a situation, the hardware is
6485 * reset (by s2io_close) and restarted again (by s2io_open) to
6486 * overcome any problem that might have been caused in the hardware.
6491 static void s2io_tx_watchdog(struct net_device *dev)
6493 nic_t *sp = dev->priv;
6495 if (netif_carrier_ok(dev)) {
6496 schedule_work(&sp->rst_timer_task);
6497 sp->mac_control.stats_info->sw_stat.soft_reset_cnt++;
6502 * rx_osm_handler - To perform some OS related operations on SKB.
6503 * @sp: private member of the device structure,pointer to s2io_nic structure.
6504 * @skb : the socket buffer pointer.
6505 * @len : length of the packet
6506 * @cksum : FCS checksum of the frame.
6507 * @ring_no : the ring from which this RxD was extracted.
6509 * This function is called by the Rx interrupt serivce routine to perform
6510 * some OS related operations on the SKB before passing it to the upper
6511 * layers. It mainly checks if the checksum is OK, if so adds it to the
6512 * SKBs cksum variable, increments the Rx packet count and passes the SKB
6513 * to the upper layer. If the checksum is wrong, it increments the Rx
6514 * packet error count, frees the SKB and returns error.
6516 * SUCCESS on success and -1 on failure.
6518 static int rx_osm_handler(ring_info_t *ring_data, RxD_t * rxdp)
6520 nic_t *sp = ring_data->nic;
6521 struct net_device *dev = (struct net_device *) sp->dev;
6522 struct sk_buff *skb = (struct sk_buff *)
6523 ((unsigned long) rxdp->Host_Control);
6524 int ring_no = ring_data->ring_no;
6525 u16 l3_csum, l4_csum;
6526 unsigned long long err = rxdp->Control_1 & RXD_T_CODE;
6532 /* Check for parity error */
6534 sp->mac_control.stats_info->sw_stat.parity_err_cnt++;
6538 * Drop the packet if bad transfer code. Exception being
6539 * 0x5, which could be due to unsupported IPv6 extension header.
6540 * In this case, we let stack handle the packet.
6541 * Note that in this case, since checksum will be incorrect,
6542 * stack will validate the same.
6544 if (err && ((err >> 48) != 0x5)) {
6545 DBG_PRINT(ERR_DBG, "%s: Rx error Value: 0x%llx\n",
6547 sp->stats.rx_crc_errors++;
6549 atomic_dec(&sp->rx_bufs_left[ring_no]);
6550 rxdp->Host_Control = 0;
6555 /* Updating statistics */
6556 rxdp->Host_Control = 0;
6558 sp->stats.rx_packets++;
6559 if (sp->rxd_mode == RXD_MODE_1) {
6560 int len = RXD_GET_BUFFER0_SIZE_1(rxdp->Control_2);
6562 sp->stats.rx_bytes += len;
6565 } else if (sp->rxd_mode >= RXD_MODE_3A) {
6566 int get_block = ring_data->rx_curr_get_info.block_index;
6567 int get_off = ring_data->rx_curr_get_info.offset;
6568 int buf0_len = RXD_GET_BUFFER0_SIZE_3(rxdp->Control_2);
6569 int buf2_len = RXD_GET_BUFFER2_SIZE_3(rxdp->Control_2);
6570 unsigned char *buff = skb_push(skb, buf0_len);
6572 buffAdd_t *ba = &ring_data->ba[get_block][get_off];
6573 sp->stats.rx_bytes += buf0_len + buf2_len;
6574 memcpy(buff, ba->ba_0, buf0_len);
6576 if (sp->rxd_mode == RXD_MODE_3A) {
6577 int buf1_len = RXD_GET_BUFFER1_SIZE_3(rxdp->Control_2);
6579 skb_put(skb, buf1_len);
6580 skb->len += buf2_len;
6581 skb->data_len += buf2_len;
6582 skb_put(skb_shinfo(skb)->frag_list, buf2_len);
6583 sp->stats.rx_bytes += buf1_len;
6586 skb_put(skb, buf2_len);
6589 if ((rxdp->Control_1 & TCP_OR_UDP_FRAME) && ((!sp->lro) ||
6590 (sp->lro && (!(rxdp->Control_1 & RXD_FRAME_IP_FRAG)))) &&
6592 l3_csum = RXD_GET_L3_CKSUM(rxdp->Control_1);
6593 l4_csum = RXD_GET_L4_CKSUM(rxdp->Control_1);
6594 if ((l3_csum == L3_CKSUM_OK) && (l4_csum == L4_CKSUM_OK)) {
6596 * NIC verifies if the Checksum of the received
6597 * frame is Ok or not and accordingly returns
6598 * a flag in the RxD.
6600 skb->ip_summed = CHECKSUM_UNNECESSARY;
6606 ret = s2io_club_tcp_session(skb->data, &tcp,
6607 &tcp_len, &lro, rxdp, sp);
6609 case 3: /* Begin anew */
6612 case 1: /* Aggregate */
6614 lro_append_pkt(sp, lro,
6618 case 4: /* Flush session */
6620 lro_append_pkt(sp, lro,
6622 queue_rx_frame(lro->parent);
6623 clear_lro_session(lro);
6624 sp->mac_control.stats_info->
6625 sw_stat.flush_max_pkts++;
6628 case 2: /* Flush both */
6629 lro->parent->data_len =
6631 sp->mac_control.stats_info->
6632 sw_stat.sending_both++;
6633 queue_rx_frame(lro->parent);
6634 clear_lro_session(lro);
6636 case 0: /* sessions exceeded */
6637 case -1: /* non-TCP or not
6641 * First pkt in session not
6642 * L3/L4 aggregatable
6647 "%s: Samadhana!!\n",
6654 * Packet with erroneous checksum, let the
6655 * upper layers deal with it.
6657 skb->ip_summed = CHECKSUM_NONE;
6660 skb->ip_summed = CHECKSUM_NONE;
6664 skb->protocol = eth_type_trans(skb, dev);
6665 if (sp->vlgrp && RXD_GET_VLAN_TAG(rxdp->Control_2)) {
6666 /* Queueing the vlan frame to the upper layer */
6668 vlan_hwaccel_receive_skb(skb, sp->vlgrp,
6669 RXD_GET_VLAN_TAG(rxdp->Control_2));
6671 vlan_hwaccel_rx(skb, sp->vlgrp,
6672 RXD_GET_VLAN_TAG(rxdp->Control_2));
6675 netif_receive_skb(skb);
6681 queue_rx_frame(skb);
6683 dev->last_rx = jiffies;
6685 atomic_dec(&sp->rx_bufs_left[ring_no]);
6690 * s2io_link - stops/starts the Tx queue.
6691 * @sp : private member of the device structure, which is a pointer to the
6692 * s2io_nic structure.
6693 * @link : inidicates whether link is UP/DOWN.
6695 * This function stops/starts the Tx queue depending on whether the link
6696 * status of the NIC is is down or up. This is called by the Alarm
6697 * interrupt handler whenever a link change interrupt comes up.
6702 static void s2io_link(nic_t * sp, int link)
6704 struct net_device *dev = (struct net_device *) sp->dev;
6706 if (link != sp->last_link_state) {
6707 if (link == LINK_DOWN) {
6708 DBG_PRINT(ERR_DBG, "%s: Link down\n", dev->name);
6709 netif_carrier_off(dev);
6711 DBG_PRINT(ERR_DBG, "%s: Link Up\n", dev->name);
6712 netif_carrier_on(dev);
6715 sp->last_link_state = link;
6719 * get_xena_rev_id - to identify revision ID of xena.
6720 * @pdev : PCI Dev structure
6722 * Function to identify the Revision ID of xena.
6724 * returns the revision ID of the device.
6727 static int get_xena_rev_id(struct pci_dev *pdev)
6731 ret = pci_read_config_byte(pdev, PCI_REVISION_ID, (u8 *) & id);
6736 * s2io_init_pci -Initialization of PCI and PCI-X configuration registers .
6737 * @sp : private member of the device structure, which is a pointer to the
6738 * s2io_nic structure.
6740 * This function initializes a few of the PCI and PCI-X configuration registers
6741 * with recommended values.
6746 static void s2io_init_pci(nic_t * sp)
6748 u16 pci_cmd = 0, pcix_cmd = 0;
6750 /* Enable Data Parity Error Recovery in PCI-X command register. */
6751 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
6753 pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
6755 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
6758 /* Set the PErr Response bit in PCI command register. */
6759 pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
6760 pci_write_config_word(sp->pdev, PCI_COMMAND,
6761 (pci_cmd | PCI_COMMAND_PARITY));
6762 pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
6765 static int s2io_verify_parm(struct pci_dev *pdev, u8 *dev_intr_type)
6767 if ( tx_fifo_num > 8) {
6768 DBG_PRINT(ERR_DBG, "s2io: Requested number of Tx fifos not "
6770 DBG_PRINT(ERR_DBG, "s2io: Default to 8 Tx fifos\n");
6773 if ( rx_ring_num > 8) {
6774 DBG_PRINT(ERR_DBG, "s2io: Requested number of Rx rings not "
6776 DBG_PRINT(ERR_DBG, "s2io: Default to 8 Rx rings\n");
6779 if (*dev_intr_type != INTA)
6782 #ifndef CONFIG_PCI_MSI
6783 if (*dev_intr_type != INTA) {
6784 DBG_PRINT(ERR_DBG, "s2io: This kernel does not support"
6785 "MSI/MSI-X. Defaulting to INTA\n");
6786 *dev_intr_type = INTA;
6789 if (*dev_intr_type > MSI_X) {
6790 DBG_PRINT(ERR_DBG, "s2io: Wrong intr_type requested. "
6791 "Defaulting to INTA\n");
6792 *dev_intr_type = INTA;
6795 if ((*dev_intr_type == MSI_X) &&
6796 ((pdev->device != PCI_DEVICE_ID_HERC_WIN) &&
6797 (pdev->device != PCI_DEVICE_ID_HERC_UNI))) {
6798 DBG_PRINT(ERR_DBG, "s2io: Xframe I does not support MSI_X. "
6799 "Defaulting to INTA\n");
6800 *dev_intr_type = INTA;
6802 if ( (rx_ring_num > 1) && (*dev_intr_type != INTA) )
6804 if (rx_ring_mode > 3) {
6805 DBG_PRINT(ERR_DBG, "s2io: Requested ring mode not supported\n");
6806 DBG_PRINT(ERR_DBG, "s2io: Defaulting to 3-buffer mode\n");
6813 * s2io_init_nic - Initialization of the adapter .
6814 * @pdev : structure containing the PCI related information of the device.
6815 * @pre: List of PCI devices supported by the driver listed in s2io_tbl.
6817 * The function initializes an adapter identified by the pci_dec structure.
6818 * All OS related initialization including memory and device structure and
6819 * initlaization of the device private variable is done. Also the swapper
6820 * control register is initialized to enable read and write into the I/O
6821 * registers of the device.
6823 * returns 0 on success and negative on failure.
6826 static int __devinit
6827 s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
6830 struct net_device *dev;
6832 int dma_flag = FALSE;
6833 u32 mac_up, mac_down;
6834 u64 val64 = 0, tmp64 = 0;
6835 XENA_dev_config_t __iomem *bar0 = NULL;
6837 mac_info_t *mac_control;
6838 struct config_param *config;
6840 u8 dev_intr_type = intr_type;
6842 if ((ret = s2io_verify_parm(pdev, &dev_intr_type)))
6845 if ((ret = pci_enable_device(pdev))) {
6847 "s2io_init_nic: pci_enable_device failed\n");
6851 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
6852 DBG_PRINT(INIT_DBG, "s2io_init_nic: Using 64bit DMA\n");
6854 if (pci_set_consistent_dma_mask
6855 (pdev, DMA_64BIT_MASK)) {
6857 "Unable to obtain 64bit DMA for \
6858 consistent allocations\n");
6859 pci_disable_device(pdev);
6862 } else if (!pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
6863 DBG_PRINT(INIT_DBG, "s2io_init_nic: Using 32bit DMA\n");
6865 pci_disable_device(pdev);
6868 if (dev_intr_type != MSI_X) {
6869 if (pci_request_regions(pdev, s2io_driver_name)) {
6870 DBG_PRINT(ERR_DBG, "Request Regions failed\n");
6871 pci_disable_device(pdev);
6876 if (!(request_mem_region(pci_resource_start(pdev, 0),
6877 pci_resource_len(pdev, 0), s2io_driver_name))) {
6878 DBG_PRINT(ERR_DBG, "bar0 Request Regions failed\n");
6879 pci_disable_device(pdev);
6882 if (!(request_mem_region(pci_resource_start(pdev, 2),
6883 pci_resource_len(pdev, 2), s2io_driver_name))) {
6884 DBG_PRINT(ERR_DBG, "bar1 Request Regions failed\n");
6885 release_mem_region(pci_resource_start(pdev, 0),
6886 pci_resource_len(pdev, 0));
6887 pci_disable_device(pdev);
6892 dev = alloc_etherdev(sizeof(nic_t));
6894 DBG_PRINT(ERR_DBG, "Device allocation failed\n");
6895 pci_disable_device(pdev);
6896 pci_release_regions(pdev);
6900 pci_set_master(pdev);
6901 pci_set_drvdata(pdev, dev);
6902 SET_MODULE_OWNER(dev);
6903 SET_NETDEV_DEV(dev, &pdev->dev);
6905 /* Private member variable initialized to s2io NIC structure */
6907 memset(sp, 0, sizeof(nic_t));
6910 sp->high_dma_flag = dma_flag;
6911 sp->device_enabled_once = FALSE;
6912 if (rx_ring_mode == 1)
6913 sp->rxd_mode = RXD_MODE_1;
6914 if (rx_ring_mode == 2)
6915 sp->rxd_mode = RXD_MODE_3B;
6916 if (rx_ring_mode == 3)
6917 sp->rxd_mode = RXD_MODE_3A;
6919 sp->intr_type = dev_intr_type;
6921 if ((pdev->device == PCI_DEVICE_ID_HERC_WIN) ||
6922 (pdev->device == PCI_DEVICE_ID_HERC_UNI))
6923 sp->device_type = XFRAME_II_DEVICE;
6925 sp->device_type = XFRAME_I_DEVICE;
6929 /* Initialize some PCI/PCI-X fields of the NIC. */
6933 * Setting the device configuration parameters.
6934 * Most of these parameters can be specified by the user during
6935 * module insertion as they are module loadable parameters. If
6936 * these parameters are not not specified during load time, they
6937 * are initialized with default values.
6939 mac_control = &sp->mac_control;
6940 config = &sp->config;
6942 /* Tx side parameters. */
6943 config->tx_fifo_num = tx_fifo_num;
6944 for (i = 0; i < MAX_TX_FIFOS; i++) {
6945 config->tx_cfg[i].fifo_len = tx_fifo_len[i];
6946 config->tx_cfg[i].fifo_priority = i;
6949 /* mapping the QoS priority to the configured fifos */
6950 for (i = 0; i < MAX_TX_FIFOS; i++)
6951 config->fifo_mapping[i] = fifo_map[config->tx_fifo_num][i];
6953 config->tx_intr_type = TXD_INT_TYPE_UTILZ;
6954 for (i = 0; i < config->tx_fifo_num; i++) {
6955 config->tx_cfg[i].f_no_snoop =
6956 (NO_SNOOP_TXD | NO_SNOOP_TXD_BUFFER);
6957 if (config->tx_cfg[i].fifo_len < 65) {
6958 config->tx_intr_type = TXD_INT_TYPE_PER_LIST;
6962 /* + 2 because one Txd for skb->data and one Txd for UFO */
6963 config->max_txds = MAX_SKB_FRAGS + 2;
6965 /* Rx side parameters. */
6966 config->rx_ring_num = rx_ring_num;
6967 for (i = 0; i < MAX_RX_RINGS; i++) {
6968 config->rx_cfg[i].num_rxd = rx_ring_sz[i] *
6969 (rxd_count[sp->rxd_mode] + 1);
6970 config->rx_cfg[i].ring_priority = i;
6973 for (i = 0; i < rx_ring_num; i++) {
6974 config->rx_cfg[i].ring_org = RING_ORG_BUFF1;
6975 config->rx_cfg[i].f_no_snoop =
6976 (NO_SNOOP_RXD | NO_SNOOP_RXD_BUFFER);
6979 /* Setting Mac Control parameters */
6980 mac_control->rmac_pause_time = rmac_pause_time;
6981 mac_control->mc_pause_threshold_q0q3 = mc_pause_threshold_q0q3;
6982 mac_control->mc_pause_threshold_q4q7 = mc_pause_threshold_q4q7;
6985 /* Initialize Ring buffer parameters. */
6986 for (i = 0; i < config->rx_ring_num; i++)
6987 atomic_set(&sp->rx_bufs_left[i], 0);
6989 /* Initialize the number of ISRs currently running */
6990 atomic_set(&sp->isr_cnt, 0);
6992 /* initialize the shared memory used by the NIC and the host */
6993 if (init_shared_mem(sp)) {
6994 DBG_PRINT(ERR_DBG, "%s: Memory allocation failed\n",
6997 goto mem_alloc_failed;
7000 sp->bar0 = ioremap(pci_resource_start(pdev, 0),
7001 pci_resource_len(pdev, 0));
7003 DBG_PRINT(ERR_DBG, "%s: Neterion: cannot remap io mem1\n",
7006 goto bar0_remap_failed;
7009 sp->bar1 = ioremap(pci_resource_start(pdev, 2),
7010 pci_resource_len(pdev, 2));
7012 DBG_PRINT(ERR_DBG, "%s: Neterion: cannot remap io mem2\n",
7015 goto bar1_remap_failed;
7018 dev->irq = pdev->irq;
7019 dev->base_addr = (unsigned long) sp->bar0;
7021 /* Initializing the BAR1 address as the start of the FIFO pointer. */
7022 for (j = 0; j < MAX_TX_FIFOS; j++) {
7023 mac_control->tx_FIFO_start[j] = (TxFIFO_element_t __iomem *)
7024 (sp->bar1 + (j * 0x00020000));
7027 /* Driver entry points */
7028 dev->open = &s2io_open;
7029 dev->stop = &s2io_close;
7030 dev->hard_start_xmit = &s2io_xmit;
7031 dev->get_stats = &s2io_get_stats;
7032 dev->set_multicast_list = &s2io_set_multicast;
7033 dev->do_ioctl = &s2io_ioctl;
7034 dev->change_mtu = &s2io_change_mtu;
7035 SET_ETHTOOL_OPS(dev, &netdev_ethtool_ops);
7036 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
7037 dev->vlan_rx_register = s2io_vlan_rx_register;
7038 dev->vlan_rx_kill_vid = (void *)s2io_vlan_rx_kill_vid;
7041 * will use eth_mac_addr() for dev->set_mac_address
7042 * mac address will be set every time dev->open() is called
7044 dev->poll = s2io_poll;
7047 #ifdef CONFIG_NET_POLL_CONTROLLER
7048 dev->poll_controller = s2io_netpoll;
7051 dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM;
7052 if (sp->high_dma_flag == TRUE)
7053 dev->features |= NETIF_F_HIGHDMA;
7054 dev->features |= NETIF_F_TSO;
7055 dev->features |= NETIF_F_TSO6;
7056 if ((sp->device_type & XFRAME_II_DEVICE) && (ufo)) {
7057 dev->features |= NETIF_F_UFO;
7058 dev->features |= NETIF_F_HW_CSUM;
7061 dev->tx_timeout = &s2io_tx_watchdog;
7062 dev->watchdog_timeo = WATCH_DOG_TIMEOUT;
7063 INIT_WORK(&sp->rst_timer_task, s2io_restart_nic);
7064 INIT_WORK(&sp->set_link_task, s2io_set_link);
7066 pci_save_state(sp->pdev);
7068 /* Setting swapper control on the NIC, for proper reset operation */
7069 if (s2io_set_swapper(sp)) {
7070 DBG_PRINT(ERR_DBG, "%s:swapper settings are wrong\n",
7073 goto set_swap_failed;
7076 /* Verify if the Herc works on the slot its placed into */
7077 if (sp->device_type & XFRAME_II_DEVICE) {
7078 mode = s2io_verify_pci_mode(sp);
7080 DBG_PRINT(ERR_DBG, "%s: ", __FUNCTION__);
7081 DBG_PRINT(ERR_DBG, " Unsupported PCI bus mode\n");
7083 goto set_swap_failed;
7087 /* Not needed for Herc */
7088 if (sp->device_type & XFRAME_I_DEVICE) {
7090 * Fix for all "FFs" MAC address problems observed on
7093 fix_mac_address(sp);
7098 * MAC address initialization.
7099 * For now only one mac address will be read and used.
7102 val64 = RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
7103 RMAC_ADDR_CMD_MEM_OFFSET(0 + MAC_MAC_ADDR_START_OFFSET);
7104 writeq(val64, &bar0->rmac_addr_cmd_mem);
7105 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
7106 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING);
7107 tmp64 = readq(&bar0->rmac_addr_data0_mem);
7108 mac_down = (u32) tmp64;
7109 mac_up = (u32) (tmp64 >> 32);
7111 memset(sp->def_mac_addr[0].mac_addr, 0, sizeof(ETH_ALEN));
7113 sp->def_mac_addr[0].mac_addr[3] = (u8) (mac_up);
7114 sp->def_mac_addr[0].mac_addr[2] = (u8) (mac_up >> 8);
7115 sp->def_mac_addr[0].mac_addr[1] = (u8) (mac_up >> 16);
7116 sp->def_mac_addr[0].mac_addr[0] = (u8) (mac_up >> 24);
7117 sp->def_mac_addr[0].mac_addr[5] = (u8) (mac_down >> 16);
7118 sp->def_mac_addr[0].mac_addr[4] = (u8) (mac_down >> 24);
7120 /* Set the factory defined MAC address initially */
7121 dev->addr_len = ETH_ALEN;
7122 memcpy(dev->dev_addr, sp->def_mac_addr, ETH_ALEN);
7124 /* reset Nic and bring it to known state */
7128 * Initialize the tasklet status and link state flags
7129 * and the card state parameter
7131 atomic_set(&(sp->card_state), 0);
7132 sp->tasklet_status = 0;
7135 /* Initialize spinlocks */
7136 spin_lock_init(&sp->tx_lock);
7139 spin_lock_init(&sp->put_lock);
7140 spin_lock_init(&sp->rx_lock);
7143 * SXE-002: Configure link and activity LED to init state
7146 subid = sp->pdev->subsystem_device;
7147 if ((subid & 0xFF) >= 0x07) {
7148 val64 = readq(&bar0->gpio_control);
7149 val64 |= 0x0000800000000000ULL;
7150 writeq(val64, &bar0->gpio_control);
7151 val64 = 0x0411040400000000ULL;
7152 writeq(val64, (void __iomem *) bar0 + 0x2700);
7153 val64 = readq(&bar0->gpio_control);
7156 sp->rx_csum = 1; /* Rx chksum verify enabled by default */
7158 if (register_netdev(dev)) {
7159 DBG_PRINT(ERR_DBG, "Device registration failed\n");
7161 goto register_failed;
7164 DBG_PRINT(ERR_DBG, "Copyright(c) 2002-2005 Neterion Inc.\n");
7165 DBG_PRINT(ERR_DBG, "%s: Neterion %s (rev %d)\n",dev->name,
7166 sp->product_name, get_xena_rev_id(sp->pdev));
7167 DBG_PRINT(ERR_DBG, "%s: Driver version %s\n", dev->name,
7168 s2io_driver_version);
7169 DBG_PRINT(ERR_DBG, "%s: MAC ADDR: "
7170 "%02x:%02x:%02x:%02x:%02x:%02x", dev->name,
7171 sp->def_mac_addr[0].mac_addr[0],
7172 sp->def_mac_addr[0].mac_addr[1],
7173 sp->def_mac_addr[0].mac_addr[2],
7174 sp->def_mac_addr[0].mac_addr[3],
7175 sp->def_mac_addr[0].mac_addr[4],
7176 sp->def_mac_addr[0].mac_addr[5]);
7177 DBG_PRINT(ERR_DBG, "SERIAL NUMBER: %s\n", sp->serial_num);
7178 if (sp->device_type & XFRAME_II_DEVICE) {
7179 mode = s2io_print_pci_mode(sp);
7181 DBG_PRINT(ERR_DBG, " Unsupported PCI bus mode\n");
7183 unregister_netdev(dev);
7184 goto set_swap_failed;
7187 switch(sp->rxd_mode) {
7189 DBG_PRINT(ERR_DBG, "%s: 1-Buffer receive mode enabled\n",
7193 DBG_PRINT(ERR_DBG, "%s: 2-Buffer receive mode enabled\n",
7197 DBG_PRINT(ERR_DBG, "%s: 3-Buffer receive mode enabled\n",
7203 DBG_PRINT(ERR_DBG, "%s: NAPI enabled\n", dev->name);
7204 switch(sp->intr_type) {
7206 DBG_PRINT(ERR_DBG, "%s: Interrupt type INTA\n", dev->name);
7209 DBG_PRINT(ERR_DBG, "%s: Interrupt type MSI\n", dev->name);
7212 DBG_PRINT(ERR_DBG, "%s: Interrupt type MSI-X\n", dev->name);
7216 DBG_PRINT(ERR_DBG, "%s: Large receive offload enabled\n",
7219 DBG_PRINT(ERR_DBG, "%s: UDP Fragmentation Offload(UFO)"
7220 " enabled\n", dev->name);
7221 /* Initialize device name */
7222 sprintf(sp->name, "%s Neterion %s", dev->name, sp->product_name);
7224 /* Initialize bimodal Interrupts */
7225 sp->config.bimodal = bimodal;
7226 if (!(sp->device_type & XFRAME_II_DEVICE) && bimodal) {
7227 sp->config.bimodal = 0;
7228 DBG_PRINT(ERR_DBG,"%s:Bimodal intr not supported by Xframe I\n",
7233 * Make Link state as off at this point, when the Link change
7234 * interrupt comes the state will be automatically changed to
7237 netif_carrier_off(dev);
7248 free_shared_mem(sp);
7249 pci_disable_device(pdev);
7250 if (dev_intr_type != MSI_X)
7251 pci_release_regions(pdev);
7253 release_mem_region(pci_resource_start(pdev, 0),
7254 pci_resource_len(pdev, 0));
7255 release_mem_region(pci_resource_start(pdev, 2),
7256 pci_resource_len(pdev, 2));
7258 pci_set_drvdata(pdev, NULL);
7265 * s2io_rem_nic - Free the PCI device
7266 * @pdev: structure containing the PCI related information of the device.
7267 * Description: This function is called by the Pci subsystem to release a
7268 * PCI device and free up all resource held up by the device. This could
7269 * be in response to a Hot plug event or when the driver is to be removed
7273 static void __devexit s2io_rem_nic(struct pci_dev *pdev)
7275 struct net_device *dev =
7276 (struct net_device *) pci_get_drvdata(pdev);
7280 DBG_PRINT(ERR_DBG, "Driver Data is NULL!!\n");
7285 unregister_netdev(dev);
7287 free_shared_mem(sp);
7290 if (sp->intr_type != MSI_X)
7291 pci_release_regions(pdev);
7293 release_mem_region(pci_resource_start(pdev, 0),
7294 pci_resource_len(pdev, 0));
7295 release_mem_region(pci_resource_start(pdev, 2),
7296 pci_resource_len(pdev, 2));
7298 pci_set_drvdata(pdev, NULL);
7300 pci_disable_device(pdev);
7304 * s2io_starter - Entry point for the driver
7305 * Description: This function is the entry point for the driver. It verifies
7306 * the module loadable parameters and initializes PCI configuration space.
7309 int __init s2io_starter(void)
7311 return pci_register_driver(&s2io_driver);
7315 * s2io_closer - Cleanup routine for the driver
7316 * Description: This function is the cleanup routine for the driver. It unregist * ers the driver.
7319 static __exit void s2io_closer(void)
7321 pci_unregister_driver(&s2io_driver);
7322 DBG_PRINT(INIT_DBG, "cleanup done\n");
7325 module_init(s2io_starter);
7326 module_exit(s2io_closer);
7328 static int check_L2_lro_capable(u8 *buffer, struct iphdr **ip,
7329 struct tcphdr **tcp, RxD_t *rxdp)
7332 u8 l2_type = (u8)((rxdp->Control_1 >> 37) & 0x7), ip_len;
7334 if (!(rxdp->Control_1 & RXD_FRAME_PROTO_TCP)) {
7335 DBG_PRINT(INIT_DBG,"%s: Non-TCP frames not supported for LRO\n",
7341 * By default the VLAN field in the MAC is stripped by the card, if this
7342 * feature is turned off in rx_pa_cfg register, then the ip_off field
7343 * has to be shifted by a further 2 bytes
7346 case 0: /* DIX type */
7347 case 4: /* DIX type with VLAN */
7348 ip_off = HEADER_ETHERNET_II_802_3_SIZE;
7350 /* LLC, SNAP etc are considered non-mergeable */
7355 *ip = (struct iphdr *)((u8 *)buffer + ip_off);
7356 ip_len = (u8)((*ip)->ihl);
7358 *tcp = (struct tcphdr *)((unsigned long)*ip + ip_len);
7363 static int check_for_socket_match(lro_t *lro, struct iphdr *ip,
7366 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
7367 if ((lro->iph->saddr != ip->saddr) || (lro->iph->daddr != ip->daddr) ||
7368 (lro->tcph->source != tcp->source) || (lro->tcph->dest != tcp->dest))
7373 static inline int get_l4_pyld_length(struct iphdr *ip, struct tcphdr *tcp)
7375 return(ntohs(ip->tot_len) - (ip->ihl << 2) - (tcp->doff << 2));
7378 static void initiate_new_session(lro_t *lro, u8 *l2h,
7379 struct iphdr *ip, struct tcphdr *tcp, u32 tcp_pyld_len)
7381 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
7385 lro->tcp_next_seq = tcp_pyld_len + ntohl(tcp->seq);
7386 lro->tcp_ack = ntohl(tcp->ack_seq);
7388 lro->total_len = ntohs(ip->tot_len);
7391 * check if we saw TCP timestamp. Other consistency checks have
7392 * already been done.
7394 if (tcp->doff == 8) {
7396 ptr = (u32 *)(tcp+1);
7398 lro->cur_tsval = *(ptr+1);
7399 lro->cur_tsecr = *(ptr+2);
7404 static void update_L3L4_header(nic_t *sp, lro_t *lro)
7406 struct iphdr *ip = lro->iph;
7407 struct tcphdr *tcp = lro->tcph;
7409 StatInfo_t *statinfo = sp->mac_control.stats_info;
7410 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
7412 /* Update L3 header */
7413 ip->tot_len = htons(lro->total_len);
7415 nchk = ip_fast_csum((u8 *)lro->iph, ip->ihl);
7418 /* Update L4 header */
7419 tcp->ack_seq = lro->tcp_ack;
7420 tcp->window = lro->window;
7422 /* Update tsecr field if this session has timestamps enabled */
7424 u32 *ptr = (u32 *)(tcp + 1);
7425 *(ptr+2) = lro->cur_tsecr;
7428 /* Update counters required for calculation of
7429 * average no. of packets aggregated.
7431 statinfo->sw_stat.sum_avg_pkts_aggregated += lro->sg_num;
7432 statinfo->sw_stat.num_aggregations++;
7435 static void aggregate_new_rx(lro_t *lro, struct iphdr *ip,
7436 struct tcphdr *tcp, u32 l4_pyld)
7438 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
7439 lro->total_len += l4_pyld;
7440 lro->frags_len += l4_pyld;
7441 lro->tcp_next_seq += l4_pyld;
7444 /* Update ack seq no. and window ad(from this pkt) in LRO object */
7445 lro->tcp_ack = tcp->ack_seq;
7446 lro->window = tcp->window;
7450 /* Update tsecr and tsval from this packet */
7451 ptr = (u32 *) (tcp + 1);
7452 lro->cur_tsval = *(ptr + 1);
7453 lro->cur_tsecr = *(ptr + 2);
7457 static int verify_l3_l4_lro_capable(lro_t *l_lro, struct iphdr *ip,
7458 struct tcphdr *tcp, u32 tcp_pyld_len)
7462 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
7464 if (!tcp_pyld_len) {
7465 /* Runt frame or a pure ack */
7469 if (ip->ihl != 5) /* IP has options */
7472 /* If we see CE codepoint in IP header, packet is not mergeable */
7473 if (INET_ECN_is_ce(ipv4_get_dsfield(ip)))
7476 /* If we see ECE or CWR flags in TCP header, packet is not mergeable */
7477 if (tcp->urg || tcp->psh || tcp->rst || tcp->syn || tcp->fin ||
7478 tcp->ece || tcp->cwr || !tcp->ack) {
7480 * Currently recognize only the ack control word and
7481 * any other control field being set would result in
7482 * flushing the LRO session
7488 * Allow only one TCP timestamp option. Don't aggregate if
7489 * any other options are detected.
7491 if (tcp->doff != 5 && tcp->doff != 8)
7494 if (tcp->doff == 8) {
7495 ptr = (u8 *)(tcp + 1);
7496 while (*ptr == TCPOPT_NOP)
7498 if (*ptr != TCPOPT_TIMESTAMP || *(ptr+1) != TCPOLEN_TIMESTAMP)
7501 /* Ensure timestamp value increases monotonically */
7503 if (l_lro->cur_tsval > *((u32 *)(ptr+2)))
7506 /* timestamp echo reply should be non-zero */
7507 if (*((u32 *)(ptr+6)) == 0)
7515 s2io_club_tcp_session(u8 *buffer, u8 **tcp, u32 *tcp_len, lro_t **lro,
7516 RxD_t *rxdp, nic_t *sp)
7519 struct tcphdr *tcph;
7522 if (!(ret = check_L2_lro_capable(buffer, &ip, (struct tcphdr **)tcp,
7524 DBG_PRINT(INFO_DBG,"IP Saddr: %x Daddr: %x\n",
7525 ip->saddr, ip->daddr);
7530 tcph = (struct tcphdr *)*tcp;
7531 *tcp_len = get_l4_pyld_length(ip, tcph);
7532 for (i=0; i<MAX_LRO_SESSIONS; i++) {
7533 lro_t *l_lro = &sp->lro0_n[i];
7534 if (l_lro->in_use) {
7535 if (check_for_socket_match(l_lro, ip, tcph))
7537 /* Sock pair matched */
7540 if ((*lro)->tcp_next_seq != ntohl(tcph->seq)) {
7541 DBG_PRINT(INFO_DBG, "%s:Out of order. expected "
7542 "0x%x, actual 0x%x\n", __FUNCTION__,
7543 (*lro)->tcp_next_seq,
7546 sp->mac_control.stats_info->
7547 sw_stat.outof_sequence_pkts++;
7552 if (!verify_l3_l4_lro_capable(l_lro, ip, tcph,*tcp_len))
7553 ret = 1; /* Aggregate */
7555 ret = 2; /* Flush both */
7561 /* Before searching for available LRO objects,
7562 * check if the pkt is L3/L4 aggregatable. If not
7563 * don't create new LRO session. Just send this
7566 if (verify_l3_l4_lro_capable(NULL, ip, tcph, *tcp_len)) {
7570 for (i=0; i<MAX_LRO_SESSIONS; i++) {
7571 lro_t *l_lro = &sp->lro0_n[i];
7572 if (!(l_lro->in_use)) {
7574 ret = 3; /* Begin anew */
7580 if (ret == 0) { /* sessions exceeded */
7581 DBG_PRINT(INFO_DBG,"%s:All LRO sessions already in use\n",
7589 initiate_new_session(*lro, buffer, ip, tcph, *tcp_len);
7592 update_L3L4_header(sp, *lro);
7595 aggregate_new_rx(*lro, ip, tcph, *tcp_len);
7596 if ((*lro)->sg_num == sp->lro_max_aggr_per_sess) {
7597 update_L3L4_header(sp, *lro);
7598 ret = 4; /* Flush the LRO */
7602 DBG_PRINT(ERR_DBG,"%s:Dont know, can't say!!\n",
7610 static void clear_lro_session(lro_t *lro)
7612 static u16 lro_struct_size = sizeof(lro_t);
7614 memset(lro, 0, lro_struct_size);
7617 static void queue_rx_frame(struct sk_buff *skb)
7619 struct net_device *dev = skb->dev;
7621 skb->protocol = eth_type_trans(skb, dev);
7623 netif_receive_skb(skb);
7628 static void lro_append_pkt(nic_t *sp, lro_t *lro, struct sk_buff *skb,
7631 struct sk_buff *first = lro->parent;
7633 first->len += tcp_len;
7634 first->data_len = lro->frags_len;
7635 skb_pull(skb, (skb->len - tcp_len));
7636 if (skb_shinfo(first)->frag_list)
7637 lro->last_frag->next = skb;
7639 skb_shinfo(first)->frag_list = skb;
7640 first->truesize += skb->truesize;
7641 lro->last_frag = skb;
7642 sp->mac_control.stats_info->sw_stat.clubbed_frms_cnt++;