drivers/net/sfc/falcon.c

   1 /****************************************************************************
   2  * Driver for Solarflare Solarstorm network controllers and boards
   3  * Copyright 2005-2006 Fen Systems Ltd.
   4  * Copyright 2006-2008 Solarflare Communications Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 as published
   8  * by the Free Software Foundation, incorporated herein by reference.
   9  */
  10
  11 #include <linux/bitops.h>
  12 #include <linux/delay.h>
  13 #include <linux/pci.h>
  14 #include <linux/module.h>
  15 #include <linux/seq_file.h>
  16 #include <linux/i2c.h>
  17 #include <linux/mii.h>
  18 #include "net_driver.h"
  19 #include "bitfield.h"
  20 #include "efx.h"
  21 #include "mac.h"
  22 #include "spi.h"
  23 #include "falcon.h"
  24 #include "regs.h"
  25 #include "io.h"
  26 #include "mdio_10g.h"
  27 #include "phy.h"
  28 #include "workarounds.h"
  29
  30 /* Hardware control for SFC4000 (aka Falcon). */
  31
  32 /**************************************************************************
  33  *
  34  * Configurable values
  35  *
  36  **************************************************************************
  37  */
  38
  39 /* This is set to 16 for a good reason.  In summary, if larger than
  40  * 16, the descriptor cache holds more than a default socket
  41  * buffer's worth of packets (for UDP we can only have at most one
  42  * socket buffer's worth outstanding).  This combined with the fact
  43  * that we only get 1 TX event per descriptor cache means the NIC
  44  * goes idle.
  45  */
  46 #define TX_DC_ENTRIES 16
  47 #define TX_DC_ENTRIES_ORDER 1
  48
  49 #define RX_DC_ENTRIES 64
  50 #define RX_DC_ENTRIES_ORDER 3
  51
  52 static const unsigned int
  53 /* "Large" EEPROM device: Atmel AT25640 or similar
  54  * 8 KB, 16-bit address, 32 B write block */
  55 large_eeprom_type = ((13 << SPI_DEV_TYPE_SIZE_LBN)
  56                      | (2 << SPI_DEV_TYPE_ADDR_LEN_LBN)
  57                      | (5 << SPI_DEV_TYPE_BLOCK_SIZE_LBN)),
  58 /* Default flash device: Atmel AT25F1024
  59  * 128 KB, 24-bit address, 32 KB erase block, 256 B write block */
  60 default_flash_type = ((17 << SPI_DEV_TYPE_SIZE_LBN)
  61                       | (3 << SPI_DEV_TYPE_ADDR_LEN_LBN)
  62                       | (0x52 << SPI_DEV_TYPE_ERASE_CMD_LBN)
  63                       | (15 << SPI_DEV_TYPE_ERASE_SIZE_LBN)
  64                       | (8 << SPI_DEV_TYPE_BLOCK_SIZE_LBN));
  65
  66 /* RX FIFO XOFF watermark
  67  *
  68  * When the amount of the RX FIFO increases used increases past this
  69  * watermark send XOFF. Only used if RX flow control is enabled (ethtool -A)
  70  * This also has an effect on RX/TX arbitration
  71  */
  72 static int rx_xoff_thresh_bytes = -1;
  73 module_param(rx_xoff_thresh_bytes, int, 0644);
  74 MODULE_PARM_DESC(rx_xoff_thresh_bytes, "RX fifo XOFF threshold");
  75
  76 /* RX FIFO XON watermark
  77  *
  78  * When the amount of the RX FIFO used decreases below this
  79  * watermark send XON. Only used if TX flow control is enabled (ethtool -A)
  80  * This also has an effect on RX/TX arbitration
  81  */
  82 static int rx_xon_thresh_bytes = -1;
  83 module_param(rx_xon_thresh_bytes, int, 0644);
  84 MODULE_PARM_DESC(rx_xon_thresh_bytes, "RX fifo XON threshold");
  85
  86 /* If FALCON_MAX_INT_ERRORS internal errors occur within
  87  * FALCON_INT_ERROR_EXPIRE seconds, we consider the NIC broken and
  88  * disable it.
  89  */
  90 #define FALCON_INT_ERROR_EXPIRE 3600
  91 #define FALCON_MAX_INT_ERRORS 5
  92
  93 /* We poll for events every FLUSH_INTERVAL ms, and check FLUSH_POLL_COUNT times
  94  */
  95 #define FALCON_FLUSH_INTERVAL 10
  96 #define FALCON_FLUSH_POLL_COUNT 100
  97
  98 /**************************************************************************
  99  *
 100  * Falcon constants
 101  *
 102  **************************************************************************
 103  */
 104
 105 /* Size and alignment of special buffers (4KB) */
 106 #define FALCON_BUF_SIZE 4096
 107
 108 /* Depth of RX flush request fifo */
 109 #define FALCON_RX_FLUSH_COUNT 4
 110
 111 #define FALCON_IS_DUAL_FUNC(efx)                \
 112         (efx_nic_rev(efx) < EFX_REV_FALCON_B0)
 113
 114 /**************************************************************************
 115  *
 116  * Falcon hardware access
 117  *
 118  **************************************************************************/
 119
 120 static inline void falcon_write_buf_tbl(struct efx_nic *efx, efx_qword_t *value,
 121                                         unsigned int index)
 122 {
 123         efx_sram_writeq(efx, efx->membase + efx->type->buf_tbl_base,
 124                         value, index);
 125 }
 126
 127 /* Read the current event from the event queue */
 128 static inline efx_qword_t *falcon_event(struct efx_channel *channel,
 129                                         unsigned int index)
 130 {
 131         return (((efx_qword_t *) (channel->eventq.addr)) + index);
 132 }
 133
 134 /* See if an event is present
 135  *
 136  * We check both the high and low dword of the event for all ones.  We
 137  * wrote all ones when we cleared the event, and no valid event can
 138  * have all ones in either its high or low dwords.  This approach is
 139  * robust against reordering.
 140  *
 141  * Note that using a single 64-bit comparison is incorrect; even
 142  * though the CPU read will be atomic, the DMA write may not be.
 143  */
 144 static inline int falcon_event_present(efx_qword_t *event)
 145 {
 146         return (!(EFX_DWORD_IS_ALL_ONES(event->dword[0]) |
 147                   EFX_DWORD_IS_ALL_ONES(event->dword[1])));
 148 }
 149
 150 /**************************************************************************
 151  *
 152  * I2C bus - this is a bit-bashing interface using GPIO pins
 153  * Note that it uses the output enables to tristate the outputs
 154  * SDA is the data pin and SCL is the clock
 155  *
 156  **************************************************************************
 157  */
 158 static void falcon_setsda(void *data, int state)
 159 {
 160         struct efx_nic *efx = (struct efx_nic *)data;
 161         efx_oword_t reg;
 162
 163         efx_reado(efx, &reg, FR_AB_GPIO_CTL);
 164         EFX_SET_OWORD_FIELD(reg, FRF_AB_GPIO3_OEN, !state);
 165         efx_writeo(efx, &reg, FR_AB_GPIO_CTL);
 166 }
 167
 168 static void falcon_setscl(void *data, int state)
 169 {
 170         struct efx_nic *efx = (struct efx_nic *)data;
 171         efx_oword_t reg;
 172
 173         efx_reado(efx, &reg, FR_AB_GPIO_CTL);
 174         EFX_SET_OWORD_FIELD(reg, FRF_AB_GPIO0_OEN, !state);
 175         efx_writeo(efx, &reg, FR_AB_GPIO_CTL);
 176 }
 177
 178 static int falcon_getsda(void *data)
 179 {
 180         struct efx_nic *efx = (struct efx_nic *)data;
 181         efx_oword_t reg;
 182
 183         efx_reado(efx, &reg, FR_AB_GPIO_CTL);
 184         return EFX_OWORD_FIELD(reg, FRF_AB_GPIO3_IN);
 185 }
 186
 187 static int falcon_getscl(void *data)
 188 {
 189         struct efx_nic *efx = (struct efx_nic *)data;
 190         efx_oword_t reg;
 191
 192         efx_reado(efx, &reg, FR_AB_GPIO_CTL);
 193         return EFX_OWORD_FIELD(reg, FRF_AB_GPIO0_IN);
 194 }
 195
 196 static struct i2c_algo_bit_data falcon_i2c_bit_operations = {
 197         .setsda         = falcon_setsda,
 198         .setscl         = falcon_setscl,
 199         .getsda         = falcon_getsda,
 200         .getscl         = falcon_getscl,
 201         .udelay         = 5,
 202         /* Wait up to 50 ms for slave to let us pull SCL high */
 203         .timeout        = DIV_ROUND_UP(HZ, 20),
 204 };
 205
 206 /**************************************************************************
 207  *
 208  * Falcon special buffer handling
 209  * Special buffers are used for event queues and the TX and RX
 210  * descriptor rings.
 211  *
 212  *************************************************************************/
 213
 214 /*
 215  * Initialise a Falcon special buffer
 216  *
 217  * This will define a buffer (previously allocated via
 218  * falcon_alloc_special_buffer()) in Falcon's buffer table, allowing
 219  * it to be used for event queues, descriptor rings etc.
 220  */
 221 static void
 222 falcon_init_special_buffer(struct efx_nic *efx,
 223                            struct efx_special_buffer *buffer)
 224 {
 225         efx_qword_t buf_desc;
 226         int index;
 227         dma_addr_t dma_addr;
 228         int i;
 229
 230         EFX_BUG_ON_PARANOID(!buffer->addr);
 231
 232         /* Write buffer descriptors to NIC */
 233         for (i = 0; i < buffer->entries; i++) {
 234                 index = buffer->index + i;
 235                 dma_addr = buffer->dma_addr + (i * 4096);
 236                 EFX_LOG(efx, "mapping special buffer %d at %llx\n",
 237                         index, (unsigned long long)dma_addr);
 238                 EFX_POPULATE_QWORD_3(buf_desc,
 239                                      FRF_AZ_BUF_ADR_REGION, 0,
 240                                      FRF_AZ_BUF_ADR_FBUF, dma_addr >> 12,
 241                                      FRF_AZ_BUF_OWNER_ID_FBUF, 0);
 242                 falcon_write_buf_tbl(efx, &buf_desc, index);
 243         }
 244 }
 245
 246 /* Unmaps a buffer from Falcon and clears the buffer table entries */
 247 static void
 248 falcon_fini_special_buffer(struct efx_nic *efx,
 249                            struct efx_special_buffer *buffer)
 250 {
 251         efx_oword_t buf_tbl_upd;
 252         unsigned int start = buffer->index;
 253         unsigned int end = (buffer->index + buffer->entries - 1);
 254
 255         if (!buffer->entries)
 256                 return;
 257
 258         EFX_LOG(efx, "unmapping special buffers %d-%d\n",
 259                 buffer->index, buffer->index + buffer->entries - 1);
 260
 261         EFX_POPULATE_OWORD_4(buf_tbl_upd,
 262                              FRF_AZ_BUF_UPD_CMD, 0,
 263                              FRF_AZ_BUF_CLR_CMD, 1,
 264                              FRF_AZ_BUF_CLR_END_ID, end,
 265                              FRF_AZ_BUF_CLR_START_ID, start);
 266         efx_writeo(efx, &buf_tbl_upd, FR_AZ_BUF_TBL_UPD);
 267 }
 268
 269 /*
 270  * Allocate a new Falcon special buffer
 271  *
 272  * This allocates memory for a new buffer, clears it and allocates a
 273  * new buffer ID range.  It does not write into Falcon's buffer table.
 274  *
 275  * This call will allocate 4KB buffers, since Falcon can't use 8KB
 276  * buffers for event queues and descriptor rings.
 277  */
 278 static int falcon_alloc_special_buffer(struct efx_nic *efx,
 279                                        struct efx_special_buffer *buffer,
 280                                        unsigned int len)
 281 {
 282         len = ALIGN(len, FALCON_BUF_SIZE);
 283
 284         buffer->addr = pci_alloc_consistent(efx->pci_dev, len,
 285                                             &buffer->dma_addr);
 286         if (!buffer->addr)
 287                 return -ENOMEM;
 288         buffer->len = len;
 289         buffer->entries = len / FALCON_BUF_SIZE;
 290         BUG_ON(buffer->dma_addr & (FALCON_BUF_SIZE - 1));
 291
 292         /* All zeros is a potentially valid event so memset to 0xff */
 293         memset(buffer->addr, 0xff, len);
 294
 295         /* Select new buffer ID */
 296         buffer->index = efx->next_buffer_table;
 297         efx->next_buffer_table += buffer->entries;
 298
 299         EFX_LOG(efx, "allocating special buffers %d-%d at %llx+%x "
 300                 "(virt %p phys %llx)\n", buffer->index,
 301                 buffer->index + buffer->entries - 1,
 302                 (u64)buffer->dma_addr, len,
 303                 buffer->addr, (u64)virt_to_phys(buffer->addr));
 304
 305         return 0;
 306 }
 307
 308 static void falcon_free_special_buffer(struct efx_nic *efx,
 309                                        struct efx_special_buffer *buffer)
 310 {
 311         if (!buffer->addr)
 312                 return;
 313
 314         EFX_LOG(efx, "deallocating special buffers %d-%d at %llx+%x "
 315                 "(virt %p phys %llx)\n", buffer->index,
 316                 buffer->index + buffer->entries - 1,
 317                 (u64)buffer->dma_addr, buffer->len,
 318                 buffer->addr, (u64)virt_to_phys(buffer->addr));
 319
 320         pci_free_consistent(efx->pci_dev, buffer->len, buffer->addr,
 321                             buffer->dma_addr);
 322         buffer->addr = NULL;
 323         buffer->entries = 0;
 324 }
 325
 326 /**************************************************************************
 327  *
 328  * Falcon generic buffer handling
 329  * These buffers are used for interrupt status and MAC stats
 330  *
 331  **************************************************************************/
 332
 333 static int falcon_alloc_buffer(struct efx_nic *efx,
 334                                struct efx_buffer *buffer, unsigned int len)
 335 {
 336         buffer->addr = pci_alloc_consistent(efx->pci_dev, len,
 337                                             &buffer->dma_addr);
 338         if (!buffer->addr)
 339                 return -ENOMEM;
 340         buffer->len = len;
 341         memset(buffer->addr, 0, len);
 342         return 0;
 343 }
 344
 345 static void falcon_free_buffer(struct efx_nic *efx, struct efx_buffer *buffer)
 346 {
 347         if (buffer->addr) {
 348                 pci_free_consistent(efx->pci_dev, buffer->len,
 349                                     buffer->addr, buffer->dma_addr);
 350                 buffer->addr = NULL;
 351         }
 352 }
 353
 354 /**************************************************************************
 355  *
 356  * Falcon TX path
 357  *
 358  **************************************************************************/
 359
 360 /* Returns a pointer to the specified transmit descriptor in the TX
 361  * descriptor queue belonging to the specified channel.
 362  */
 363 static inline efx_qword_t *falcon_tx_desc(struct efx_tx_queue *tx_queue,
 364                                                unsigned int index)
 365 {
 366         return (((efx_qword_t *) (tx_queue->txd.addr)) + index);
 367 }
 368
 369 /* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */
 370 static inline void falcon_notify_tx_desc(struct efx_tx_queue *tx_queue)
 371 {
 372         unsigned write_ptr;
 373         efx_dword_t reg;
 374
 375         write_ptr = tx_queue->write_count & EFX_TXQ_MASK;
 376         EFX_POPULATE_DWORD_1(reg, FRF_AZ_TX_DESC_WPTR_DWORD, write_ptr);
 377         efx_writed_page(tx_queue->efx, &reg,
 378                         FR_AZ_TX_DESC_UPD_DWORD_P0, tx_queue->queue);
 379 }
 380
 381
 382 /* For each entry inserted into the software descriptor ring, create a
 383  * descriptor in the hardware TX descriptor ring (in host memory), and
 384  * write a doorbell.
 385  */
 386 void falcon_push_buffers(struct efx_tx_queue *tx_queue)
 387 {
 388
 389         struct efx_tx_buffer *buffer;
 390         efx_qword_t *txd;
 391         unsigned write_ptr;
 392
 393         BUG_ON(tx_queue->write_count == tx_queue->insert_count);
 394
 395         do {
 396                 write_ptr = tx_queue->write_count & EFX_TXQ_MASK;
 397                 buffer = &tx_queue->buffer[write_ptr];
 398                 txd = falcon_tx_desc(tx_queue, write_ptr);
 399                 ++tx_queue->write_count;
 400
 401                 /* Create TX descriptor ring entry */
 402                 EFX_POPULATE_QWORD_4(*txd,
 403                                      FSF_AZ_TX_KER_CONT, buffer->continuation,
 404                                      FSF_AZ_TX_KER_BYTE_COUNT, buffer->len,
 405                                      FSF_AZ_TX_KER_BUF_REGION, 0,
 406                                      FSF_AZ_TX_KER_BUF_ADDR, buffer->dma_addr);
 407         } while (tx_queue->write_count != tx_queue->insert_count);
 408
 409         wmb(); /* Ensure descriptors are written before they are fetched */
 410         falcon_notify_tx_desc(tx_queue);
 411 }
 412
 413 /* Allocate hardware resources for a TX queue */
 414 int falcon_probe_tx(struct efx_tx_queue *tx_queue)
 415 {
 416         struct efx_nic *efx = tx_queue->efx;
 417         BUILD_BUG_ON(EFX_TXQ_SIZE < 512 || EFX_TXQ_SIZE > 4096 ||
 418                      EFX_TXQ_SIZE & EFX_TXQ_MASK);
 419         return falcon_alloc_special_buffer(efx, &tx_queue->txd,
 420                                            EFX_TXQ_SIZE * sizeof(efx_qword_t));
 421 }
 422
 423 void falcon_init_tx(struct efx_tx_queue *tx_queue)
 424 {
 425         efx_oword_t tx_desc_ptr;
 426         struct efx_nic *efx = tx_queue->efx;
 427
 428         tx_queue->flushed = FLUSH_NONE;
 429
 430         /* Pin TX descriptor ring */
 431         falcon_init_special_buffer(efx, &tx_queue->txd);
 432
 433         /* Push TX descriptor ring to card */
 434         EFX_POPULATE_OWORD_10(tx_desc_ptr,
 435                               FRF_AZ_TX_DESCQ_EN, 1,
 436                               FRF_AZ_TX_ISCSI_DDIG_EN, 0,
 437                               FRF_AZ_TX_ISCSI_HDIG_EN, 0,
 438                               FRF_AZ_TX_DESCQ_BUF_BASE_ID, tx_queue->txd.index,
 439                               FRF_AZ_TX_DESCQ_EVQ_ID,
 440                               tx_queue->channel->channel,
 441                               FRF_AZ_TX_DESCQ_OWNER_ID, 0,
 442                               FRF_AZ_TX_DESCQ_LABEL, tx_queue->queue,
 443                               FRF_AZ_TX_DESCQ_SIZE,
 444                               __ffs(tx_queue->txd.entries),
 445                               FRF_AZ_TX_DESCQ_TYPE, 0,
 446                               FRF_BZ_TX_NON_IP_DROP_DIS, 1);
 447
 448         if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) {
 449                 int csum = tx_queue->queue == EFX_TX_QUEUE_OFFLOAD_CSUM;
 450                 EFX_SET_OWORD_FIELD(tx_desc_ptr, FRF_BZ_TX_IP_CHKSM_DIS, !csum);
 451                 EFX_SET_OWORD_FIELD(tx_desc_ptr, FRF_BZ_TX_TCP_CHKSM_DIS,
 452                                     !csum);
 453         }
 454
 455         efx_writeo_table(efx, &tx_desc_ptr, efx->type->txd_ptr_tbl_base,
 456                          tx_queue->queue);
 457
 458         if (efx_nic_rev(efx) < EFX_REV_FALCON_B0) {
 459                 efx_oword_t reg;
 460
 461                 /* Only 128 bits in this register */
 462                 BUILD_BUG_ON(EFX_TX_QUEUE_COUNT >= 128);
 463
 464                 efx_reado(efx, &reg, FR_AA_TX_CHKSM_CFG);
 465                 if (tx_queue->queue == EFX_TX_QUEUE_OFFLOAD_CSUM)
 466                         clear_bit_le(tx_queue->queue, (void *)&reg);
 467                 else
 468                         set_bit_le(tx_queue->queue, (void *)&reg);
 469                 efx_writeo(efx, &reg, FR_AA_TX_CHKSM_CFG);
 470         }
 471 }
 472
 473 static void falcon_flush_tx_queue(struct efx_tx_queue *tx_queue)
 474 {
 475         struct efx_nic *efx = tx_queue->efx;
 476         efx_oword_t tx_flush_descq;
 477
 478         tx_queue->flushed = FLUSH_PENDING;
 479
 480         /* Post a flush command */
 481         EFX_POPULATE_OWORD_2(tx_flush_descq,
 482                              FRF_AZ_TX_FLUSH_DESCQ_CMD, 1,
 483                              FRF_AZ_TX_FLUSH_DESCQ, tx_queue->queue);
 484         efx_writeo(efx, &tx_flush_descq, FR_AZ_TX_FLUSH_DESCQ);
 485 }
 486
 487 void falcon_fini_tx(struct efx_tx_queue *tx_queue)
 488 {
 489         struct efx_nic *efx = tx_queue->efx;
 490         efx_oword_t tx_desc_ptr;
 491
 492         /* The queue should have been flushed */
 493         WARN_ON(tx_queue->flushed != FLUSH_DONE);
 494
 495         /* Remove TX descriptor ring from card */
 496         EFX_ZERO_OWORD(tx_desc_ptr);
 497         efx_writeo_table(efx, &tx_desc_ptr, efx->type->txd_ptr_tbl_base,
 498                          tx_queue->queue);
 499
 500         /* Unpin TX descriptor ring */
 501         falcon_fini_special_buffer(efx, &tx_queue->txd);
 502 }
 503
 504 /* Free buffers backing TX queue */
 505 void falcon_remove_tx(struct efx_tx_queue *tx_queue)
 506 {
 507         falcon_free_special_buffer(tx_queue->efx, &tx_queue->txd);
 508 }
 509
 510 /**************************************************************************
 511  *
 512  * Falcon RX path
 513  *
 514  **************************************************************************/
 515
 516 /* Returns a pointer to the specified descriptor in the RX descriptor queue */
 517 static inline efx_qword_t *falcon_rx_desc(struct efx_rx_queue *rx_queue,
 518                                                unsigned int index)
 519 {
 520         return (((efx_qword_t *) (rx_queue->rxd.addr)) + index);
 521 }
 522
 523 /* This creates an entry in the RX descriptor queue */
 524 static inline void falcon_build_rx_desc(struct efx_rx_queue *rx_queue,
 525                                         unsigned index)
 526 {
 527         struct efx_rx_buffer *rx_buf;
 528         efx_qword_t *rxd;
 529
 530         rxd = falcon_rx_desc(rx_queue, index);
 531         rx_buf = efx_rx_buffer(rx_queue, index);
 532         EFX_POPULATE_QWORD_3(*rxd,
 533                              FSF_AZ_RX_KER_BUF_SIZE,
 534                              rx_buf->len -
 535                              rx_queue->efx->type->rx_buffer_padding,
 536                              FSF_AZ_RX_KER_BUF_REGION, 0,
 537                              FSF_AZ_RX_KER_BUF_ADDR, rx_buf->dma_addr);
 538 }
 539
 540 /* This writes to the RX_DESC_WPTR register for the specified receive
 541  * descriptor ring.
 542  */
 543 void falcon_notify_rx_desc(struct efx_rx_queue *rx_queue)
 544 {
 545         efx_dword_t reg;
 546         unsigned write_ptr;
 547
 548         while (rx_queue->notified_count != rx_queue->added_count) {
 549                 falcon_build_rx_desc(rx_queue,
 550                                      rx_queue->notified_count &
 551                                      EFX_RXQ_MASK);
 552                 ++rx_queue->notified_count;
 553         }
 554
 555         wmb();
 556         write_ptr = rx_queue->added_count & EFX_RXQ_MASK;
 557         EFX_POPULATE_DWORD_1(reg, FRF_AZ_RX_DESC_WPTR_DWORD, write_ptr);
 558         efx_writed_page(rx_queue->efx, &reg,
 559                         FR_AZ_RX_DESC_UPD_DWORD_P0, rx_queue->queue);
 560 }
 561
 562 int falcon_probe_rx(struct efx_rx_queue *rx_queue)
 563 {
 564         struct efx_nic *efx = rx_queue->efx;
 565         BUILD_BUG_ON(EFX_RXQ_SIZE < 512 || EFX_RXQ_SIZE > 4096 ||
 566                      EFX_RXQ_SIZE & EFX_RXQ_MASK);
 567         return falcon_alloc_special_buffer(efx, &rx_queue->rxd,
 568                                            EFX_RXQ_SIZE * sizeof(efx_qword_t));
 569 }
 570
 571 void falcon_init_rx(struct efx_rx_queue *rx_queue)
 572 {
 573         efx_oword_t rx_desc_ptr;
 574         struct efx_nic *efx = rx_queue->efx;
 575         bool is_b0 = efx_nic_rev(efx) >= EFX_REV_FALCON_B0;
 576         bool iscsi_digest_en = is_b0;
 577
 578         EFX_LOG(efx, "RX queue %d ring in special buffers %d-%d\n",
 579                 rx_queue->queue, rx_queue->rxd.index,
 580                 rx_queue->rxd.index + rx_queue->rxd.entries - 1);
 581
 582         rx_queue->flushed = FLUSH_NONE;
 583
 584         /* Pin RX descriptor ring */
 585         falcon_init_special_buffer(efx, &rx_queue->rxd);
 586
 587         /* Push RX descriptor ring to card */
 588         EFX_POPULATE_OWORD_10(rx_desc_ptr,
 589                               FRF_AZ_RX_ISCSI_DDIG_EN, iscsi_digest_en,
 590                               FRF_AZ_RX_ISCSI_HDIG_EN, iscsi_digest_en,
 591                               FRF_AZ_RX_DESCQ_BUF_BASE_ID, rx_queue->rxd.index,
 592                               FRF_AZ_RX_DESCQ_EVQ_ID,
 593                               rx_queue->channel->channel,
 594                               FRF_AZ_RX_DESCQ_OWNER_ID, 0,
 595                               FRF_AZ_RX_DESCQ_LABEL, rx_queue->queue,
 596                               FRF_AZ_RX_DESCQ_SIZE,
 597                               __ffs(rx_queue->rxd.entries),
 598                               FRF_AZ_RX_DESCQ_TYPE, 0 /* kernel queue */ ,
 599                               /* For >=B0 this is scatter so disable */
 600                               FRF_AZ_RX_DESCQ_JUMBO, !is_b0,
 601                               FRF_AZ_RX_DESCQ_EN, 1);
 602         efx_writeo_table(efx, &rx_desc_ptr, efx->type->rxd_ptr_tbl_base,
 603                          rx_queue->queue);
 604 }
 605
 606 static void falcon_flush_rx_queue(struct efx_rx_queue *rx_queue)
 607 {
 608         struct efx_nic *efx = rx_queue->efx;
 609         efx_oword_t rx_flush_descq;
 610
 611         rx_queue->flushed = FLUSH_PENDING;
 612
 613         /* Post a flush command */
 614         EFX_POPULATE_OWORD_2(rx_flush_descq,
 615                              FRF_AZ_RX_FLUSH_DESCQ_CMD, 1,
 616                              FRF_AZ_RX_FLUSH_DESCQ, rx_queue->queue);
 617         efx_writeo(efx, &rx_flush_descq, FR_AZ_RX_FLUSH_DESCQ);
 618 }
 619
 620 void falcon_fini_rx(struct efx_rx_queue *rx_queue)
 621 {
 622         efx_oword_t rx_desc_ptr;
 623         struct efx_nic *efx = rx_queue->efx;
 624
 625         /* The queue should already have been flushed */
 626         WARN_ON(rx_queue->flushed != FLUSH_DONE);
 627
 628         /* Remove RX descriptor ring from card */
 629         EFX_ZERO_OWORD(rx_desc_ptr);
 630         efx_writeo_table(efx, &rx_desc_ptr, efx->type->rxd_ptr_tbl_base,
 631                          rx_queue->queue);
 632
 633         /* Unpin RX descriptor ring */
 634         falcon_fini_special_buffer(efx, &rx_queue->rxd);
 635 }
 636
 637 /* Free buffers backing RX queue */
 638 void falcon_remove_rx(struct efx_rx_queue *rx_queue)
 639 {
 640         falcon_free_special_buffer(rx_queue->efx, &rx_queue->rxd);
 641 }
 642
 643 /**************************************************************************
 644  *
 645  * Falcon event queue processing
 646  * Event queues are processed by per-channel tasklets.
 647  *
 648  **************************************************************************/
 649
 650 /* Update a channel's event queue's read pointer (RPTR) register
 651  *
 652  * This writes the EVQ_RPTR_REG register for the specified channel's
 653  * event queue.
 654  *
 655  * Note that EVQ_RPTR_REG contains the index of the "last read" event,
 656  * whereas channel->eventq_read_ptr contains the index of the "next to
 657  * read" event.
 658  */
 659 void falcon_eventq_read_ack(struct efx_channel *channel)
 660 {
 661         efx_dword_t reg;
 662         struct efx_nic *efx = channel->efx;
 663
 664         EFX_POPULATE_DWORD_1(reg, FRF_AZ_EVQ_RPTR, channel->eventq_read_ptr);
 665         efx_writed_table(efx, &reg, efx->type->evq_rptr_tbl_base,
 666                             channel->channel);
 667 }
 668
 669 /* Use HW to insert a SW defined event */
 670 void falcon_generate_event(struct efx_channel *channel, efx_qword_t *event)
 671 {
 672         efx_oword_t drv_ev_reg;
 673
 674         BUILD_BUG_ON(FRF_AZ_DRV_EV_DATA_LBN != 0 ||
 675                      FRF_AZ_DRV_EV_DATA_WIDTH != 64);
 676         drv_ev_reg.u32[0] = event->u32[0];
 677         drv_ev_reg.u32[1] = event->u32[1];
 678         drv_ev_reg.u32[2] = 0;
 679         drv_ev_reg.u32[3] = 0;
 680         EFX_SET_OWORD_FIELD(drv_ev_reg, FRF_AZ_DRV_EV_QID, channel->channel);
 681         efx_writeo(channel->efx, &drv_ev_reg, FR_AZ_DRV_EV);
 682 }
 683
 684 /* Handle a transmit completion event
 685  *
 686  * Falcon batches TX completion events; the message we receive is of
 687  * the form "complete all TX events up to this index".
 688  */
 689 static void falcon_handle_tx_event(struct efx_channel *channel,
 690                                    efx_qword_t *event)
 691 {
 692         unsigned int tx_ev_desc_ptr;
 693         unsigned int tx_ev_q_label;
 694         struct efx_tx_queue *tx_queue;
 695         struct efx_nic *efx = channel->efx;
 696
 697         if (likely(EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_COMP))) {
 698                 /* Transmit completion */
 699                 tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_DESC_PTR);
 700                 tx_ev_q_label = EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_Q_LABEL);
 701                 tx_queue = &efx->tx_queue[tx_ev_q_label];
 702                 channel->irq_mod_score +=
 703                         (tx_ev_desc_ptr - tx_queue->read_count) &
 704                         EFX_TXQ_MASK;
 705                 efx_xmit_done(tx_queue, tx_ev_desc_ptr);
 706         } else if (EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_WQ_FF_FULL)) {
 707                 /* Rewrite the FIFO write pointer */
 708                 tx_ev_q_label = EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_Q_LABEL);
 709                 tx_queue = &efx->tx_queue[tx_ev_q_label];
 710
 711                 if (efx_dev_registered(efx))
 712                         netif_tx_lock(efx->net_dev);
 713                 falcon_notify_tx_desc(tx_queue);
 714                 if (efx_dev_registered(efx))
 715                         netif_tx_unlock(efx->net_dev);
 716         } else if (EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_PKT_ERR) &&
 717                    EFX_WORKAROUND_10727(efx)) {
 718                 efx_schedule_reset(efx, RESET_TYPE_TX_DESC_FETCH);
 719         } else {
 720                 EFX_ERR(efx, "channel %d unexpected TX event "
 721                         EFX_QWORD_FMT"\n", channel->channel,
 722                         EFX_QWORD_VAL(*event));
 723         }
 724 }
 725
 726 /* Detect errors included in the rx_evt_pkt_ok bit. */
 727 static void falcon_handle_rx_not_ok(struct efx_rx_queue *rx_queue,
 728                                     const efx_qword_t *event,
 729                                     bool *rx_ev_pkt_ok,
 730                                     bool *discard)
 731 {
 732         struct efx_nic *efx = rx_queue->efx;
 733         bool rx_ev_buf_owner_id_err, rx_ev_ip_hdr_chksum_err;
 734         bool rx_ev_tcp_udp_chksum_err, rx_ev_eth_crc_err;
 735         bool rx_ev_frm_trunc, rx_ev_drib_nib, rx_ev_tobe_disc;
 736         bool rx_ev_other_err, rx_ev_pause_frm;
 737         bool rx_ev_hdr_type, rx_ev_mcast_pkt;
 738         unsigned rx_ev_pkt_type;
 739
 740         rx_ev_hdr_type = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_HDR_TYPE);
 741         rx_ev_mcast_pkt = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_MCAST_PKT);
 742         rx_ev_tobe_disc = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_TOBE_DISC);
 743         rx_ev_pkt_type = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_PKT_TYPE);
 744         rx_ev_buf_owner_id_err = EFX_QWORD_FIELD(*event,
 745                                                  FSF_AZ_RX_EV_BUF_OWNER_ID_ERR);
 746         rx_ev_ip_hdr_chksum_err = EFX_QWORD_FIELD(*event,
 747                                                   FSF_AZ_RX_EV_IP_HDR_CHKSUM_ERR);
 748         rx_ev_tcp_udp_chksum_err = EFX_QWORD_FIELD(*event,
 749                                                    FSF_AZ_RX_EV_TCP_UDP_CHKSUM_ERR);
 750         rx_ev_eth_crc_err = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_ETH_CRC_ERR);
 751         rx_ev_frm_trunc = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_FRM_TRUNC);
 752         rx_ev_drib_nib = ((efx_nic_rev(efx) >= EFX_REV_FALCON_B0) ?
 753                           0 : EFX_QWORD_FIELD(*event, FSF_AA_RX_EV_DRIB_NIB));
 754         rx_ev_pause_frm = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_PAUSE_FRM_ERR);
 755
 756         /* Every error apart from tobe_disc and pause_frm */
 757         rx_ev_other_err = (rx_ev_drib_nib | rx_ev_tcp_udp_chksum_err |
 758                            rx_ev_buf_owner_id_err | rx_ev_eth_crc_err |
 759                            rx_ev_frm_trunc | rx_ev_ip_hdr_chksum_err);
 760
 761         /* Count errors that are not in MAC stats.  Ignore expected
 762          * checksum errors during self-test. */
 763         if (rx_ev_frm_trunc)
 764                 ++rx_queue->channel->n_rx_frm_trunc;
 765         else if (rx_ev_tobe_disc)
 766                 ++rx_queue->channel->n_rx_tobe_disc;
 767         else if (!efx->loopback_selftest) {
 768                 if (rx_ev_ip_hdr_chksum_err)
 769                         ++rx_queue->channel->n_rx_ip_hdr_chksum_err;
 770                 else if (rx_ev_tcp_udp_chksum_err)
 771                         ++rx_queue->channel->n_rx_tcp_udp_chksum_err;
 772         }
 773
 774         /* The frame must be discarded if any of these are true. */
 775         *discard = (rx_ev_eth_crc_err | rx_ev_frm_trunc | rx_ev_drib_nib |
 776                     rx_ev_tobe_disc | rx_ev_pause_frm);
 777
 778         /* TOBE_DISC is expected on unicast mismatches; don't print out an
 779          * error message.  FRM_TRUNC indicates RXDP dropped the packet due
 780          * to a FIFO overflow.
 781          */
 782 #ifdef EFX_ENABLE_DEBUG
 783         if (rx_ev_other_err) {
 784                 EFX_INFO_RL(efx, " RX queue %d unexpected RX event "
 785                             EFX_QWORD_FMT "%s%s%s%s%s%s%s%s\n",
 786                             rx_queue->queue, EFX_QWORD_VAL(*event),
 787                             rx_ev_buf_owner_id_err ? " [OWNER_ID_ERR]" : "",
 788                             rx_ev_ip_hdr_chksum_err ?
 789                             " [IP_HDR_CHKSUM_ERR]" : "",
 790                             rx_ev_tcp_udp_chksum_err ?
 791                             " [TCP_UDP_CHKSUM_ERR]" : "",
 792                             rx_ev_eth_crc_err ? " [ETH_CRC_ERR]" : "",
 793                             rx_ev_frm_trunc ? " [FRM_TRUNC]" : "",
 794                             rx_ev_drib_nib ? " [DRIB_NIB]" : "",
 795                             rx_ev_tobe_disc ? " [TOBE_DISC]" : "",
 796                             rx_ev_pause_frm ? " [PAUSE]" : "");
 797         }
 798 #endif
 799 }
 800
 801 /* Handle receive events that are not in-order. */
 802 static void falcon_handle_rx_bad_index(struct efx_rx_queue *rx_queue,
 803                                        unsigned index)
 804 {
 805         struct efx_nic *efx = rx_queue->efx;
 806         unsigned expected, dropped;
 807
 808         expected = rx_queue->removed_count & EFX_RXQ_MASK;
 809         dropped = (index - expected) & EFX_RXQ_MASK;
 810         EFX_INFO(efx, "dropped %d events (index=%d expected=%d)\n",
 811                 dropped, index, expected);
 812
 813         efx_schedule_reset(efx, EFX_WORKAROUND_5676(efx) ?
 814                            RESET_TYPE_RX_RECOVERY : RESET_TYPE_DISABLE);
 815 }
 816
 817 /* Handle a packet received event
 818  *
 819  * Falcon silicon gives a "discard" flag if it's a unicast packet with the
 820  * wrong destination address
 821  * Also "is multicast" and "matches multicast filter" flags can be used to
 822  * discard non-matching multicast packets.
 823  */
 824 static void falcon_handle_rx_event(struct efx_channel *channel,
 825                                    const efx_qword_t *event)
 826 {
 827         unsigned int rx_ev_desc_ptr, rx_ev_byte_cnt;
 828         unsigned int rx_ev_hdr_type, rx_ev_mcast_pkt;
 829         unsigned expected_ptr;
 830         bool rx_ev_pkt_ok, discard = false, checksummed;
 831         struct efx_rx_queue *rx_queue;
 832         struct efx_nic *efx = channel->efx;
 833
 834         /* Basic packet information */
 835         rx_ev_byte_cnt = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_BYTE_CNT);
 836         rx_ev_pkt_ok = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_PKT_OK);
 837         rx_ev_hdr_type = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_HDR_TYPE);
 838         WARN_ON(EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_JUMBO_CONT));
 839         WARN_ON(EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_SOP) != 1);
 840         WARN_ON(EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_Q_LABEL) !=
 841                 channel->channel);
 842
 843         rx_queue = &efx->rx_queue[channel->channel];
 844
 845         rx_ev_desc_ptr = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_DESC_PTR);
 846         expected_ptr = rx_queue->removed_count & EFX_RXQ_MASK;
 847         if (unlikely(rx_ev_desc_ptr != expected_ptr))
 848                 falcon_handle_rx_bad_index(rx_queue, rx_ev_desc_ptr);
 849
 850         if (likely(rx_ev_pkt_ok)) {
 851                 /* If packet is marked as OK and packet type is TCP/IPv4 or
 852                  * UDP/IPv4, then we can rely on the hardware checksum.
 853                  */
 854                 checksummed =
 855                         likely(efx->rx_checksum_enabled) &&
 856                         (rx_ev_hdr_type == FSE_AB_RX_EV_HDR_TYPE_IPV4_TCP ||
 857                          rx_ev_hdr_type == FSE_AB_RX_EV_HDR_TYPE_IPV4_UDP);
 858         } else {
 859                 falcon_handle_rx_not_ok(rx_queue, event, &rx_ev_pkt_ok,
 860                                         &discard);
 861                 checksummed = false;
 862         }
 863
 864         /* Detect multicast packets that didn't match the filter */
 865         rx_ev_mcast_pkt = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_MCAST_PKT);
 866         if (rx_ev_mcast_pkt) {
 867                 unsigned int rx_ev_mcast_hash_match =
 868                         EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_MCAST_HASH_MATCH);
 869
 870                 if (unlikely(!rx_ev_mcast_hash_match)) {
 871                         ++channel->n_rx_mcast_mismatch;
 872                         discard = true;
 873                 }
 874         }
 875
 876         channel->irq_mod_score += 2;
 877
 878         /* Handle received packet */
 879         efx_rx_packet(rx_queue, rx_ev_desc_ptr, rx_ev_byte_cnt,
 880                       checksummed, discard);
 881 }
 882
 883 /* Global events are basically PHY events */
 884 static void falcon_handle_global_event(struct efx_channel *channel,
 885                                        efx_qword_t *event)
 886 {
 887         struct efx_nic *efx = channel->efx;
 888         bool handled = false;
 889
 890         if (EFX_QWORD_FIELD(*event, FSF_AB_GLB_EV_G_PHY0_INTR) ||
 891             EFX_QWORD_FIELD(*event, FSF_AB_GLB_EV_XG_PHY0_INTR) ||
 892             EFX_QWORD_FIELD(*event, FSF_AB_GLB_EV_XFP_PHY0_INTR)) {
 893                 /* Ignored */
 894                 handled = true;
 895         }
 896
 897         if ((efx_nic_rev(efx) >= EFX_REV_FALCON_B0) &&
 898             EFX_QWORD_FIELD(*event, FSF_BB_GLB_EV_XG_MGT_INTR)) {
 899                 efx->xmac_poll_required = true;
 900                 handled = true;
 901         }
 902
 903         if (efx_nic_rev(efx) <= EFX_REV_FALCON_A1 ?
 904             EFX_QWORD_FIELD(*event, FSF_AA_GLB_EV_RX_RECOVERY) :
 905             EFX_QWORD_FIELD(*event, FSF_BB_GLB_EV_RX_RECOVERY)) {
 906                 EFX_ERR(efx, "channel %d seen global RX_RESET "
 907                         "event. Resetting.\n", channel->channel);
 908
 909                 atomic_inc(&efx->rx_reset);
 910                 efx_schedule_reset(efx, EFX_WORKAROUND_6555(efx) ?
 911                                    RESET_TYPE_RX_RECOVERY : RESET_TYPE_DISABLE);
 912                 handled = true;
 913         }
 914
 915         if (!handled)
 916                 EFX_ERR(efx, "channel %d unknown global event "
 917                         EFX_QWORD_FMT "\n", channel->channel,
 918                         EFX_QWORD_VAL(*event));
 919 }
 920
 921 static void falcon_handle_driver_event(struct efx_channel *channel,
 922                                        efx_qword_t *event)
 923 {
 924         struct efx_nic *efx = channel->efx;
 925         unsigned int ev_sub_code;
 926         unsigned int ev_sub_data;
 927
 928         ev_sub_code = EFX_QWORD_FIELD(*event, FSF_AZ_DRIVER_EV_SUBCODE);
 929         ev_sub_data = EFX_QWORD_FIELD(*event, FSF_AZ_DRIVER_EV_SUBDATA);
 930
 931         switch (ev_sub_code) {
 932         case FSE_AZ_TX_DESCQ_FLS_DONE_EV:
 933                 EFX_TRACE(efx, "channel %d TXQ %d flushed\n",
 934                           channel->channel, ev_sub_data);
 935                 break;
 936         case FSE_AZ_RX_DESCQ_FLS_DONE_EV:
 937                 EFX_TRACE(efx, "channel %d RXQ %d flushed\n",
 938                           channel->channel, ev_sub_data);
 939                 break;
 940         case FSE_AZ_EVQ_INIT_DONE_EV:
 941                 EFX_LOG(efx, "channel %d EVQ %d initialised\n",
 942                         channel->channel, ev_sub_data);
 943                 break;
 944         case FSE_AZ_SRM_UPD_DONE_EV:
 945                 EFX_TRACE(efx, "channel %d SRAM update done\n",
 946                           channel->channel);
 947                 break;
 948         case FSE_AZ_WAKE_UP_EV:
 949                 EFX_TRACE(efx, "channel %d RXQ %d wakeup event\n",
 950                           channel->channel, ev_sub_data);
 951                 break;
 952         case FSE_AZ_TIMER_EV:
 953                 EFX_TRACE(efx, "channel %d RX queue %d timer expired\n",
 954                           channel->channel, ev_sub_data);
 955                 break;
 956         case FSE_AA_RX_RECOVER_EV:
 957                 EFX_ERR(efx, "channel %d seen DRIVER RX_RESET event. "
 958                         "Resetting.\n", channel->channel);
 959                 atomic_inc(&efx->rx_reset);
 960                 efx_schedule_reset(efx,
 961                                    EFX_WORKAROUND_6555(efx) ?
 962                                    RESET_TYPE_RX_RECOVERY :
 963                                    RESET_TYPE_DISABLE);
 964                 break;
 965         case FSE_BZ_RX_DSC_ERROR_EV:
 966                 EFX_ERR(efx, "RX DMA Q %d reports descriptor fetch error."
 967                         " RX Q %d is disabled.\n", ev_sub_data, ev_sub_data);
 968                 efx_schedule_reset(efx, RESET_TYPE_RX_DESC_FETCH);
 969                 break;
 970         case FSE_BZ_TX_DSC_ERROR_EV:
 971                 EFX_ERR(efx, "TX DMA Q %d reports descriptor fetch error."
 972                         " TX Q %d is disabled.\n", ev_sub_data, ev_sub_data);
 973                 efx_schedule_reset(efx, RESET_TYPE_TX_DESC_FETCH);
 974                 break;
 975         default:
 976                 EFX_TRACE(efx, "channel %d unknown driver event code %d "
 977                           "data %04x\n", channel->channel, ev_sub_code,
 978                           ev_sub_data);
 979                 break;
 980         }
 981 }
 982
 983 int falcon_process_eventq(struct efx_channel *channel, int rx_quota)
 984 {
 985         unsigned int read_ptr;
 986         efx_qword_t event, *p_event;
 987         int ev_code;
 988         int rx_packets = 0;
 989
 990         read_ptr = channel->eventq_read_ptr;
 991
 992         do {
 993                 p_event = falcon_event(channel, read_ptr);
 994                 event = *p_event;
 995
 996                 if (!falcon_event_present(&event))
 997                         /* End of events */
 998                         break;
 999
1000                 EFX_TRACE(channel->efx, "channel %d event is "EFX_QWORD_FMT"\n",
1001                           channel->channel, EFX_QWORD_VAL(event));
1002
1003                 /* Clear this event by marking it all ones */
1004                 EFX_SET_QWORD(*p_event);
1005
1006                 ev_code = EFX_QWORD_FIELD(event, FSF_AZ_EV_CODE);
1007
1008                 switch (ev_code) {
1009                 case FSE_AZ_EV_CODE_RX_EV:
1010                         falcon_handle_rx_event(channel, &event);
1011                         ++rx_packets;
1012                         break;
1013                 case FSE_AZ_EV_CODE_TX_EV:
1014                         falcon_handle_tx_event(channel, &event);
1015                         break;
1016                 case FSE_AZ_EV_CODE_DRV_GEN_EV:
1017                         channel->eventq_magic = EFX_QWORD_FIELD(
1018                                 event, FSF_AZ_DRV_GEN_EV_MAGIC);
1019                         EFX_LOG(channel->efx, "channel %d received generated "
1020                                 "event "EFX_QWORD_FMT"\n", channel->channel,
1021                                 EFX_QWORD_VAL(event));
1022                         break;
1023                 case FSE_AZ_EV_CODE_GLOBAL_EV:
1024                         falcon_handle_global_event(channel, &event);
1025                         break;
1026                 case FSE_AZ_EV_CODE_DRIVER_EV:
1027                         falcon_handle_driver_event(channel, &event);
1028                         break;
1029                 default:
1030                         EFX_ERR(channel->efx, "channel %d unknown event type %d"
1031                                 " (data " EFX_QWORD_FMT ")\n", channel->channel,
1032                                 ev_code, EFX_QWORD_VAL(event));
1033                 }
1034
1035                 /* Increment read pointer */
1036                 read_ptr = (read_ptr + 1) & EFX_EVQ_MASK;
1037
1038         } while (rx_packets < rx_quota);
1039
1040         channel->eventq_read_ptr = read_ptr;
1041         return rx_packets;
1042 }
1043
1044 static void falcon_push_irq_moderation(struct efx_channel *channel)
1045 {
1046         efx_dword_t timer_cmd;
1047         struct efx_nic *efx = channel->efx;
1048
1049         /* Set timer register */
1050         if (channel->irq_moderation) {
1051                 EFX_POPULATE_DWORD_2(timer_cmd,
1052                                      FRF_AB_TC_TIMER_MODE,
1053                                      FFE_BB_TIMER_MODE_INT_HLDOFF,
1054                                      FRF_AB_TC_TIMER_VAL,
1055                                      channel->irq_moderation - 1);
1056         } else {
1057                 EFX_POPULATE_DWORD_2(timer_cmd,
1058                                      FRF_AB_TC_TIMER_MODE,
1059                                      FFE_BB_TIMER_MODE_DIS,
1060                                      FRF_AB_TC_TIMER_VAL, 0);
1061         }
1062         BUILD_BUG_ON(FR_AA_TIMER_COMMAND_KER != FR_BZ_TIMER_COMMAND_P0);
1063         efx_writed_page_locked(efx, &timer_cmd, FR_BZ_TIMER_COMMAND_P0,
1064                                channel->channel);
1065
1066 }
1067
1068 /* Allocate buffer table entries for event queue */
1069 int falcon_probe_eventq(struct efx_channel *channel)
1070 {
1071         struct efx_nic *efx = channel->efx;
1072         BUILD_BUG_ON(EFX_EVQ_SIZE < 512 || EFX_EVQ_SIZE > 32768 ||
1073                      EFX_EVQ_SIZE & EFX_EVQ_MASK);
1074         return falcon_alloc_special_buffer(efx, &channel->eventq,
1075                                            EFX_EVQ_SIZE * sizeof(efx_qword_t));
1076 }
1077
1078 void falcon_init_eventq(struct efx_channel *channel)
1079 {
1080         efx_oword_t evq_ptr;
1081         struct efx_nic *efx = channel->efx;
1082
1083         EFX_LOG(efx, "channel %d event queue in special buffers %d-%d\n",
1084                 channel->channel, channel->eventq.index,
1085                 channel->eventq.index + channel->eventq.entries - 1);
1086
1087         /* Pin event queue buffer */
1088         falcon_init_special_buffer(efx, &channel->eventq);
1089
1090         /* Fill event queue with all ones (i.e. empty events) */
1091         memset(channel->eventq.addr, 0xff, channel->eventq.len);
1092
1093         /* Push event queue to card */
1094         EFX_POPULATE_OWORD_3(evq_ptr,
1095                              FRF_AZ_EVQ_EN, 1,
1096                              FRF_AZ_EVQ_SIZE, __ffs(channel->eventq.entries),
1097                              FRF_AZ_EVQ_BUF_BASE_ID, channel->eventq.index);
1098         efx_writeo_table(efx, &evq_ptr, efx->type->evq_ptr_tbl_base,
1099                          channel->channel);
1100
1101         falcon_push_irq_moderation(channel);
1102 }
1103
1104 void falcon_fini_eventq(struct efx_channel *channel)
1105 {
1106         efx_oword_t eventq_ptr;
1107         struct efx_nic *efx = channel->efx;
1108
1109         /* Remove event queue from card */
1110         EFX_ZERO_OWORD(eventq_ptr);
1111         efx_writeo_table(efx, &eventq_ptr, efx->type->evq_ptr_tbl_base,
1112                          channel->channel);
1113
1114         /* Unpin event queue */
1115         falcon_fini_special_buffer(efx, &channel->eventq);
1116 }
1117
1118 /* Free buffers backing event queue */
1119 void falcon_remove_eventq(struct efx_channel *channel)
1120 {
1121         falcon_free_special_buffer(channel->efx, &channel->eventq);
1122 }
1123
1124
1125 /* Generates a test event on the event queue.  A subsequent call to
1126  * process_eventq() should pick up the event and place the value of
1127  * "magic" into channel->eventq_magic;
1128  */
1129 void falcon_generate_test_event(struct efx_channel *channel, unsigned int magic)
1130 {
1131         efx_qword_t test_event;
1132
1133         EFX_POPULATE_QWORD_2(test_event, FSF_AZ_EV_CODE,
1134                              FSE_AZ_EV_CODE_DRV_GEN_EV,
1135                              FSF_AZ_DRV_GEN_EV_MAGIC, magic);
1136         falcon_generate_event(channel, &test_event);
1137 }
1138
1139 /**************************************************************************
1140  *
1141  * Flush handling
1142  *
1143  **************************************************************************/
1144
1145
1146 static void falcon_poll_flush_events(struct efx_nic *efx)
1147 {
1148         struct efx_channel *channel = &efx->channel[0];
1149         struct efx_tx_queue *tx_queue;
1150         struct efx_rx_queue *rx_queue;
1151         unsigned int read_ptr = channel->eventq_read_ptr;
1152         unsigned int end_ptr = (read_ptr - 1) & EFX_EVQ_MASK;
1153
1154         do {
1155                 efx_qword_t *event = falcon_event(channel, read_ptr);
1156                 int ev_code, ev_sub_code, ev_queue;
1157                 bool ev_failed;
1158
1159                 if (!falcon_event_present(event))
1160                         break;
1161
1162                 ev_code = EFX_QWORD_FIELD(*event, FSF_AZ_EV_CODE);
1163                 ev_sub_code = EFX_QWORD_FIELD(*event,
1164                                               FSF_AZ_DRIVER_EV_SUBCODE);
1165                 if (ev_code == FSE_AZ_EV_CODE_DRIVER_EV &&
1166                     ev_sub_code == FSE_AZ_TX_DESCQ_FLS_DONE_EV) {
1167                         ev_queue = EFX_QWORD_FIELD(*event,
1168                                                    FSF_AZ_DRIVER_EV_SUBDATA);
1169                         if (ev_queue < EFX_TX_QUEUE_COUNT) {
1170                                 tx_queue = efx->tx_queue + ev_queue;
1171                                 tx_queue->flushed = FLUSH_DONE;
1172                         }
1173                 } else if (ev_code == FSE_AZ_EV_CODE_DRIVER_EV &&
1174                            ev_sub_code == FSE_AZ_RX_DESCQ_FLS_DONE_EV) {
1175                         ev_queue = EFX_QWORD_FIELD(
1176                                 *event, FSF_AZ_DRIVER_EV_RX_DESCQ_ID);
1177                         ev_failed = EFX_QWORD_FIELD(
1178                                 *event, FSF_AZ_DRIVER_EV_RX_FLUSH_FAIL);
1179                         if (ev_queue < efx->n_rx_queues) {
1180                                 rx_queue = efx->rx_queue + ev_queue;
1181                                 rx_queue->flushed =
1182                                         ev_failed ? FLUSH_FAILED : FLUSH_DONE;
1183                         }
1184                 }
1185
1186                 /* We're about to destroy the queue anyway, so
1187                  * it's ok to throw away every non-flush event */
1188                 EFX_SET_QWORD(*event);
1189
1190                 read_ptr = (read_ptr + 1) & EFX_EVQ_MASK;
1191         } while (read_ptr != end_ptr);
1192
1193         channel->eventq_read_ptr = read_ptr;
1194 }
1195
1196 static void falcon_deconfigure_mac_wrapper(struct efx_nic *efx);
1197
1198 static void falcon_prepare_flush(struct efx_nic *efx)
1199 {
1200         falcon_deconfigure_mac_wrapper(efx);
1201
1202         /* Wait for the tx and rx fifo's to get to the next packet boundary
1203          * (~1ms without back-pressure), then to drain the remainder of the
1204          * fifo's at data path speeds (negligible), with a healthy margin. */
1205         msleep(10);
1206 }
1207
1208 /* Handle tx and rx flushes at the same time, since they run in
1209  * parallel in the hardware and there's no reason for us to
1210  * serialise them */
1211 int falcon_flush_queues(struct efx_nic *efx)
1212 {
1213         struct efx_rx_queue *rx_queue;
1214         struct efx_tx_queue *tx_queue;
1215         int i, tx_pending, rx_pending;
1216
1217         /* If necessary prepare the hardware for flushing */
1218         efx->type->prepare_flush(efx);
1219
1220         /* Flush all tx queues in parallel */
1221         efx_for_each_tx_queue(tx_queue, efx)
1222                 falcon_flush_tx_queue(tx_queue);
1223
1224         /* The hardware supports four concurrent rx flushes, each of which may
1225          * need to be retried if there is an outstanding descriptor fetch */
1226         for (i = 0; i < FALCON_FLUSH_POLL_COUNT; ++i) {
1227                 rx_pending = tx_pending = 0;
1228                 efx_for_each_rx_queue(rx_queue, efx) {
1229                         if (rx_queue->flushed == FLUSH_PENDING)
1230                                 ++rx_pending;
1231                 }
1232                 efx_for_each_rx_queue(rx_queue, efx) {
1233                         if (rx_pending == FALCON_RX_FLUSH_COUNT)
1234                                 break;
1235                         if (rx_queue->flushed == FLUSH_FAILED ||
1236                             rx_queue->flushed == FLUSH_NONE) {
1237                                 falcon_flush_rx_queue(rx_queue);
1238                                 ++rx_pending;
1239                         }
1240                 }
1241                 efx_for_each_tx_queue(tx_queue, efx) {
1242                         if (tx_queue->flushed != FLUSH_DONE)
1243                                 ++tx_pending;
1244                 }
1245
1246                 if (rx_pending == 0 && tx_pending == 0)
1247                         return 0;
1248
1249                 msleep(FALCON_FLUSH_INTERVAL);
1250                 falcon_poll_flush_events(efx);
1251         }
1252
1253         /* Mark the queues as all flushed. We're going to return failure
1254          * leading to a reset, or fake up success anyway */
1255         efx_for_each_tx_queue(tx_queue, efx) {
1256                 if (tx_queue->flushed != FLUSH_DONE)
1257                         EFX_ERR(efx, "tx queue %d flush command timed out\n",
1258                                 tx_queue->queue);
1259                 tx_queue->flushed = FLUSH_DONE;
1260         }
1261         efx_for_each_rx_queue(rx_queue, efx) {
1262                 if (rx_queue->flushed != FLUSH_DONE)
1263                         EFX_ERR(efx, "rx queue %d flush command timed out\n",
1264                                 rx_queue->queue);
1265                 rx_queue->flushed = FLUSH_DONE;
1266         }
1267
1268         if (EFX_WORKAROUND_7803(efx))
1269                 return 0;
1270
1271         return -ETIMEDOUT;
1272 }
1273
1274 /**************************************************************************
1275  *
1276  * Falcon hardware interrupts
1277  * The hardware interrupt handler does very little work; all the event
1278  * queue processing is carried out by per-channel tasklets.
1279  *
1280  **************************************************************************/
1281
1282 /* Enable/disable/generate Falcon interrupts */
1283 static inline void falcon_interrupts(struct efx_nic *efx, int enabled,
1284                                      int force)
1285 {
1286         efx_oword_t int_en_reg_ker;
1287
1288         EFX_POPULATE_OWORD_2(int_en_reg_ker,
1289                              FRF_AZ_KER_INT_KER, force,
1290                              FRF_AZ_DRV_INT_EN_KER, enabled);
1291         efx_writeo(efx, &int_en_reg_ker, FR_AZ_INT_EN_KER);
1292 }
1293
1294 void falcon_enable_interrupts(struct efx_nic *efx)
1295 {
1296         struct efx_channel *channel;
1297
1298         EFX_ZERO_OWORD(*((efx_oword_t *) efx->irq_status.addr));
1299         wmb(); /* Ensure interrupt vector is clear before interrupts enabled */
1300
1301         /* Enable interrupts */
1302         falcon_interrupts(efx, 1, 0);
1303
1304         /* Force processing of all the channels to get the EVQ RPTRs up to
1305            date */
1306         efx_for_each_channel(channel, efx)
1307                 efx_schedule_channel(channel);
1308 }
1309
1310 void falcon_disable_interrupts(struct efx_nic *efx)
1311 {
1312         /* Disable interrupts */
1313         falcon_interrupts(efx, 0, 0);
1314 }
1315
1316 /* Generate a Falcon test interrupt
1317  * Interrupt must already have been enabled, otherwise nasty things
1318  * may happen.
1319  */
1320 void falcon_generate_interrupt(struct efx_nic *efx)
1321 {
1322         falcon_interrupts(efx, 1, 1);
1323 }
1324
1325 /* Acknowledge a legacy interrupt from Falcon
1326  *
1327  * This acknowledges a legacy (not MSI) interrupt via INT_ACK_KER_REG.
1328  *
1329  * Due to SFC bug 3706 (silicon revision <=A1) reads can be duplicated in the
1330  * BIU. Interrupt acknowledge is read sensitive so must write instead
1331  * (then read to ensure the BIU collector is flushed)
1332  *
1333  * NB most hardware supports MSI interrupts
1334  */
1335 static inline void falcon_irq_ack_a1(struct efx_nic *efx)
1336 {
1337         efx_dword_t reg;
1338
1339         EFX_POPULATE_DWORD_1(reg, FRF_AA_INT_ACK_KER_FIELD, 0xb7eb7e);
1340         efx_writed(efx, &reg, FR_AA_INT_ACK_KER);
1341         efx_readd(efx, &reg, FR_AA_WORK_AROUND_BROKEN_PCI_READS);
1342 }
1343
1344 /* Process a fatal interrupt
1345  * Disable bus mastering ASAP and schedule a reset
1346  */
1347 static irqreturn_t falcon_fatal_interrupt(struct efx_nic *efx)
1348 {
1349         struct falcon_nic_data *nic_data = efx->nic_data;
1350         efx_oword_t *int_ker = efx->irq_status.addr;
1351         efx_oword_t fatal_intr;
1352         int error, mem_perr;
1353
1354         efx_reado(efx, &fatal_intr, FR_AZ_FATAL_INTR_KER);
1355         error = EFX_OWORD_FIELD(fatal_intr, FRF_AZ_FATAL_INTR);
1356
1357         EFX_ERR(efx, "SYSTEM ERROR " EFX_OWORD_FMT " status "
1358                 EFX_OWORD_FMT ": %s\n", EFX_OWORD_VAL(*int_ker),
1359                 EFX_OWORD_VAL(fatal_intr),
1360                 error ? "disabling bus mastering" : "no recognised error");
1361         if (error == 0)
1362                 goto out;
1363
1364         /* If this is a memory parity error dump which blocks are offending */
1365         mem_perr = EFX_OWORD_FIELD(fatal_intr, FRF_AZ_MEM_PERR_INT_KER);
1366         if (mem_perr) {
1367                 efx_oword_t reg;
1368                 efx_reado(efx, &reg, FR_AZ_MEM_STAT);
1369                 EFX_ERR(efx, "SYSTEM ERROR: memory parity error "
1370                         EFX_OWORD_FMT "\n", EFX_OWORD_VAL(reg));
1371         }
1372
1373         /* Disable both devices */
1374         pci_clear_master(efx->pci_dev);
1375         if (FALCON_IS_DUAL_FUNC(efx))
1376                 pci_clear_master(nic_data->pci_dev2);
1377         falcon_disable_interrupts(efx);
1378
1379         /* Count errors and reset or disable the NIC accordingly */
1380         if (efx->int_error_count == 0 ||
1381             time_after(jiffies, efx->int_error_expire)) {
1382                 efx->int_error_count = 0;
1383                 efx->int_error_expire =
1384                         jiffies + FALCON_INT_ERROR_EXPIRE * HZ;
1385         }
1386         if (++efx->int_error_count < FALCON_MAX_INT_ERRORS) {
1387                 EFX_ERR(efx, "SYSTEM ERROR - reset scheduled\n");
1388                 efx_schedule_reset(efx, RESET_TYPE_INT_ERROR);
1389         } else {
1390                 EFX_ERR(efx, "SYSTEM ERROR - max number of errors seen."
1391                         "NIC will be disabled\n");
1392                 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
1393         }
1394 out:
1395         return IRQ_HANDLED;
1396 }
1397
1398 /* Handle a legacy interrupt from Falcon
1399  * Acknowledges the interrupt and schedule event queue processing.
1400  */
1401 static irqreturn_t falcon_legacy_interrupt_b0(int irq, void *dev_id)
1402 {
1403         struct efx_nic *efx = dev_id;
1404         efx_oword_t *int_ker = efx->irq_status.addr;
1405         irqreturn_t result = IRQ_NONE;
1406         struct efx_channel *channel;
1407         efx_dword_t reg;
1408         u32 queues;
1409         int syserr;
1410
1411         /* Read the ISR which also ACKs the interrupts */
1412         efx_readd(efx, &reg, FR_BZ_INT_ISR0);
1413         queues = EFX_EXTRACT_DWORD(reg, 0, 31);
1414
1415         /* Check to see if we have a serious error condition */
1416         syserr = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_FATAL_INT);
1417         if (unlikely(syserr))
1418                 return falcon_fatal_interrupt(efx);
1419
1420         /* Schedule processing of any interrupting queues */
1421         efx_for_each_channel(channel, efx) {
1422                 if ((queues & 1) ||
1423                     falcon_event_present(
1424                             falcon_event(channel, channel->eventq_read_ptr))) {
1425                         efx_schedule_channel(channel);
1426                         result = IRQ_HANDLED;
1427                 }
1428                 queues >>= 1;
1429         }
1430
1431         if (result == IRQ_HANDLED) {
1432                 efx->last_irq_cpu = raw_smp_processor_id();
1433                 EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n",
1434                           irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg));
1435         }
1436
1437         return result;
1438 }
1439
1440
1441 static irqreturn_t falcon_legacy_interrupt_a1(int irq, void *dev_id)
1442 {
1443         struct efx_nic *efx = dev_id;
1444         efx_oword_t *int_ker = efx->irq_status.addr;
1445         struct efx_channel *channel;
1446         int syserr;
1447         int queues;
1448
1449         /* Check to see if this is our interrupt.  If it isn't, we
1450          * exit without having touched the hardware.
1451          */
1452         if (unlikely(EFX_OWORD_IS_ZERO(*int_ker))) {
1453                 EFX_TRACE(efx, "IRQ %d on CPU %d not for me\n", irq,
1454                           raw_smp_processor_id());
1455                 return IRQ_NONE;
1456         }
1457         efx->last_irq_cpu = raw_smp_processor_id();
1458         EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_OWORD_FMT "\n",
1459                   irq, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker));
1460
1461         /* Check to see if we have a serious error condition */
1462         syserr = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_FATAL_INT);
1463         if (unlikely(syserr))
1464                 return falcon_fatal_interrupt(efx);
1465
1466         /* Determine interrupting queues, clear interrupt status
1467          * register and acknowledge the device interrupt.
1468          */
1469         BUILD_BUG_ON(FSF_AZ_NET_IVEC_INT_Q_WIDTH > EFX_MAX_CHANNELS);
1470         queues = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_INT_Q);
1471         EFX_ZERO_OWORD(*int_ker);
1472         wmb(); /* Ensure the vector is cleared before interrupt ack */
1473         falcon_irq_ack_a1(efx);
1474
1475         /* Schedule processing of any interrupting queues */
1476         channel = &efx->channel[0];
1477         while (queues) {
1478                 if (queues & 0x01)
1479                         efx_schedule_channel(channel);
1480                 channel++;
1481                 queues >>= 1;
1482         }
1483
1484         return IRQ_HANDLED;
1485 }
1486
1487 /* Handle an MSI interrupt from Falcon
1488  *
1489  * Handle an MSI hardware interrupt.  This routine schedules event
1490  * queue processing.  No interrupt acknowledgement cycle is necessary.
1491  * Also, we never need to check that the interrupt is for us, since
1492  * MSI interrupts cannot be shared.
1493  */
1494 static irqreturn_t falcon_msi_interrupt(int irq, void *dev_id)
1495 {
1496         struct efx_channel *channel = dev_id;
1497         struct efx_nic *efx = channel->efx;
1498         efx_oword_t *int_ker = efx->irq_status.addr;
1499         int syserr;
1500
1501         efx->last_irq_cpu = raw_smp_processor_id();
1502         EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_OWORD_FMT "\n",
1503                   irq, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker));
1504
1505         /* Check to see if we have a serious error condition */
1506         syserr = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_FATAL_INT);
1507         if (unlikely(syserr))
1508                 return falcon_fatal_interrupt(efx);
1509
1510         /* Schedule processing of the channel */
1511         efx_schedule_channel(channel);
1512
1513         return IRQ_HANDLED;
1514 }
1515
1516
1517 /* Setup RSS indirection table.
1518  * This maps from the hash value of the packet to RXQ
1519  */
1520 static void falcon_setup_rss_indir_table(struct efx_nic *efx)
1521 {
1522         int i = 0;
1523         unsigned long offset;
1524         efx_dword_t dword;
1525
1526         if (efx_nic_rev(efx) < EFX_REV_FALCON_B0)
1527                 return;
1528
1529         for (offset = FR_BZ_RX_INDIRECTION_TBL;
1530              offset < FR_BZ_RX_INDIRECTION_TBL + 0x800;
1531              offset += 0x10) {
1532                 EFX_POPULATE_DWORD_1(dword, FRF_BZ_IT_QUEUE,
1533                                      i % efx->n_rx_queues);
1534                 efx_writed(efx, &dword, offset);
1535                 i++;
1536         }
1537 }
1538
1539 /* Hook interrupt handler(s)
1540  * Try MSI and then legacy interrupts.
1541  */
1542 int falcon_init_interrupt(struct efx_nic *efx)
1543 {
1544         struct efx_channel *channel;
1545         int rc;
1546
1547         if (!EFX_INT_MODE_USE_MSI(efx)) {
1548                 irq_handler_t handler;
1549                 if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0)
1550                         handler = falcon_legacy_interrupt_b0;
1551                 else
1552                         handler = falcon_legacy_interrupt_a1;
1553
1554                 rc = request_irq(efx->legacy_irq, handler, IRQF_SHARED,
1555                                  efx->name, efx);
1556                 if (rc) {
1557                         EFX_ERR(efx, "failed to hook legacy IRQ %d\n",
1558                                 efx->pci_dev->irq);
1559                         goto fail1;
1560                 }
1561                 return 0;
1562         }
1563
1564         /* Hook MSI or MSI-X interrupt */
1565         efx_for_each_channel(channel, efx) {
1566                 rc = request_irq(channel->irq, falcon_msi_interrupt,
1567                                  IRQF_PROBE_SHARED, /* Not shared */
1568                                  channel->name, channel);
1569                 if (rc) {
1570                         EFX_ERR(efx, "failed to hook IRQ %d\n", channel->irq);
1571                         goto fail2;
1572                 }
1573         }
1574
1575         return 0;
1576
1577  fail2:
1578         efx_for_each_channel(channel, efx)
1579                 free_irq(channel->irq, channel);
1580  fail1:
1581         return rc;
1582 }
1583
1584 void falcon_fini_interrupt(struct efx_nic *efx)
1585 {
1586         struct efx_channel *channel;
1587         efx_oword_t reg;
1588
1589         /* Disable MSI/MSI-X interrupts */
1590         efx_for_each_channel(channel, efx) {
1591                 if (channel->irq)
1592                         free_irq(channel->irq, channel);
1593         }
1594
1595         /* ACK legacy interrupt */
1596         if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0)
1597                 efx_reado(efx, &reg, FR_BZ_INT_ISR0);
1598         else
1599                 falcon_irq_ack_a1(efx);
1600
1601         /* Disable legacy interrupt */
1602         if (efx->legacy_irq)
1603                 free_irq(efx->legacy_irq, efx);
1604 }
1605
1606 /**************************************************************************
1607  *
1608  * EEPROM/flash
1609  *
1610  **************************************************************************
1611  */
1612
1613 #define FALCON_SPI_MAX_LEN sizeof(efx_oword_t)
1614
1615 static int falcon_spi_poll(struct efx_nic *efx)
1616 {
1617         efx_oword_t reg;
1618         efx_reado(efx, &reg, FR_AB_EE_SPI_HCMD);
1619         return EFX_OWORD_FIELD(reg, FRF_AB_EE_SPI_HCMD_CMD_EN) ? -EBUSY : 0;
1620 }
1621
1622 /* Wait for SPI command completion */
1623 static int falcon_spi_wait(struct efx_nic *efx)
1624 {
1625         /* Most commands will finish quickly, so we start polling at
1626          * very short intervals.  Sometimes the command may have to
1627          * wait for VPD or expansion ROM access outside of our
1628          * control, so we allow up to 100 ms. */
1629         unsigned long timeout = jiffies + 1 + DIV_ROUND_UP(HZ, 10);
1630         int i;
1631
1632         for (i = 0; i < 10; i++) {
1633                 if (!falcon_spi_poll(efx))
1634                         return 0;
1635                 udelay(10);
1636         }
1637
1638         for (;;) {
1639                 if (!falcon_spi_poll(efx))
1640                         return 0;
1641                 if (time_after_eq(jiffies, timeout)) {
1642                         EFX_ERR(efx, "timed out waiting for SPI\n");
1643                         return -ETIMEDOUT;
1644                 }
1645                 schedule_timeout_uninterruptible(1);
1646         }
1647 }
1648
1649 int falcon_spi_cmd(const struct efx_spi_device *spi,
1650                    unsigned int command, int address,
1651                    const void *in, void *out, size_t len)
1652 {
1653         struct efx_nic *efx = spi->efx;
1654         bool addressed = (address >= 0);
1655         bool reading = (out != NULL);
1656         efx_oword_t reg;
1657         int rc;
1658
1659         /* Input validation */
1660         if (len > FALCON_SPI_MAX_LEN)
1661                 return -EINVAL;
1662         BUG_ON(!mutex_is_locked(&efx->spi_lock));
1663
1664         /* Check that previous command is not still running */
1665         rc = falcon_spi_poll(efx);
1666         if (rc)
1667                 return rc;
1668
1669         /* Program address register, if we have an address */
1670         if (addressed) {
1671                 EFX_POPULATE_OWORD_1(reg, FRF_AB_EE_SPI_HADR_ADR, address);
1672                 efx_writeo(efx, &reg, FR_AB_EE_SPI_HADR);
1673         }
1674
1675         /* Program data register, if we have data */
1676         if (in != NULL) {
1677                 memcpy(&reg, in, len);
1678                 efx_writeo(efx, &reg, FR_AB_EE_SPI_HDATA);
1679         }
1680
1681         /* Issue read/write command */
1682         EFX_POPULATE_OWORD_7(reg,
1683                              FRF_AB_EE_SPI_HCMD_CMD_EN, 1,
1684                              FRF_AB_EE_SPI_HCMD_SF_SEL, spi->device_id,
1685                              FRF_AB_EE_SPI_HCMD_DABCNT, len,
1686                              FRF_AB_EE_SPI_HCMD_READ, reading,
1687                              FRF_AB_EE_SPI_HCMD_DUBCNT, 0,
1688                              FRF_AB_EE_SPI_HCMD_ADBCNT,
1689                              (addressed ? spi->addr_len : 0),
1690                              FRF_AB_EE_SPI_HCMD_ENC, command);
1691         efx_writeo(efx, &reg, FR_AB_EE_SPI_HCMD);
1692
1693         /* Wait for read/write to complete */
1694         rc = falcon_spi_wait(efx);
1695         if (rc)
1696                 return rc;
1697
1698         /* Read data */
1699         if (out != NULL) {
1700                 efx_reado(efx, &reg, FR_AB_EE_SPI_HDATA);
1701                 memcpy(out, &reg, len);
1702         }
1703
1704         return 0;
1705 }
1706
1707 static size_t
1708 falcon_spi_write_limit(const struct efx_spi_device *spi, size_t start)
1709 {
1710         return min(FALCON_SPI_MAX_LEN,
1711                    (spi->block_size - (start & (spi->block_size - 1))));
1712 }
1713
1714 static inline u8
1715 efx_spi_munge_command(const struct efx_spi_device *spi,
1716                       const u8 command, const unsigned int address)
1717 {
1718         return command | (((address >> 8) & spi->munge_address) << 3);
1719 }
1720
1721 /* Wait up to 10 ms for buffered write completion */
1722 int falcon_spi_wait_write(const struct efx_spi_device *spi)
1723 {
1724         struct efx_nic *efx = spi->efx;
1725         unsigned long timeout = jiffies + 1 + DIV_ROUND_UP(HZ, 100);
1726         u8 status;
1727         int rc;
1728
1729         for (;;) {
1730                 rc = falcon_spi_cmd(spi, SPI_RDSR, -1, NULL,
1731                                     &status, sizeof(status));
1732                 if (rc)
1733                         return rc;
1734                 if (!(status & SPI_STATUS_NRDY))
1735                         return 0;
1736                 if (time_after_eq(jiffies, timeout)) {
1737                         EFX_ERR(efx, "SPI write timeout on device %d"
1738                                 " last status=0x%02x\n",
1739                                 spi->device_id, status);
1740                         return -ETIMEDOUT;
1741                 }
1742                 schedule_timeout_uninterruptible(1);
1743         }
1744 }
1745
1746 int falcon_spi_read(const struct efx_spi_device *spi, loff_t start,
1747                     size_t len, size_t *retlen, u8 *buffer)
1748 {
1749         size_t block_len, pos = 0;
1750         unsigned int command;
1751         int rc = 0;
1752
1753         while (pos < len) {
1754                 block_len = min(len - pos, FALCON_SPI_MAX_LEN);
1755
1756                 command = efx_spi_munge_command(spi, SPI_READ, start + pos);
1757                 rc = falcon_spi_cmd(spi, command, start + pos, NULL,
1758                                     buffer + pos, block_len);
1759                 if (rc)
1760                         break;
1761                 pos += block_len;
1762
1763                 /* Avoid locking up the system */
1764                 cond_resched();
1765                 if (signal_pending(current)) {
1766                         rc = -EINTR;
1767                         break;
1768                 }
1769         }
1770
1771         if (retlen)
1772                 *retlen = pos;
1773         return rc;
1774 }
1775
1776 int falcon_spi_write(const struct efx_spi_device *spi, loff_t start,
1777                      size_t len, size_t *retlen, const u8 *buffer)
1778 {
1779         u8 verify_buffer[FALCON_SPI_MAX_LEN];
1780         size_t block_len, pos = 0;
1781         unsigned int command;
1782         int rc = 0;
1783
1784         while (pos < len) {
1785                 rc = falcon_spi_cmd(spi, SPI_WREN, -1, NULL, NULL, 0);
1786                 if (rc)
1787                         break;
1788
1789                 block_len = min(len - pos,
1790                                 falcon_spi_write_limit(spi, start + pos));
1791                 command = efx_spi_munge_command(spi, SPI_WRITE, start + pos);
1792                 rc = falcon_spi_cmd(spi, command, start + pos,
1793                                     buffer + pos, NULL, block_len);
1794                 if (rc)
1795                         break;
1796
1797                 rc = falcon_spi_wait_write(spi);
1798                 if (rc)
1799                         break;
1800
1801                 command = efx_spi_munge_command(spi, SPI_READ, start + pos);
1802                 rc = falcon_spi_cmd(spi, command, start + pos,
1803                                     NULL, verify_buffer, block_len);
1804                 if (memcmp(verify_buffer, buffer + pos, block_len)) {
1805                         rc = -EIO;
1806                         break;
1807                 }
1808
1809                 pos += block_len;
1810
1811                 /* Avoid locking up the system */
1812                 cond_resched();
1813                 if (signal_pending(current)) {
1814                         rc = -EINTR;
1815                         break;
1816                 }
1817         }
1818
1819         if (retlen)
1820                 *retlen = pos;
1821         return rc;
1822 }
1823
1824 /**************************************************************************
1825  *
1826  * MAC wrapper
1827  *
1828  **************************************************************************
1829  */
1830
1831 static void falcon_push_multicast_hash(struct efx_nic *efx)
1832 {
1833         union efx_multicast_hash *mc_hash = &efx->multicast_hash;
1834
1835         WARN_ON(!mutex_is_locked(&efx->mac_lock));
1836
1837         efx_writeo(efx, &mc_hash->oword[0], FR_AB_MAC_MC_HASH_REG0);
1838         efx_writeo(efx, &mc_hash->oword[1], FR_AB_MAC_MC_HASH_REG1);
1839 }
1840
1841 static void falcon_reset_macs(struct efx_nic *efx)
1842 {
1843         struct falcon_nic_data *nic_data = efx->nic_data;
1844         efx_oword_t reg, mac_ctrl;
1845         int count;
1846
1847         if (efx_nic_rev(efx) < EFX_REV_FALCON_B0) {
1848                 /* It's not safe to use GLB_CTL_REG to reset the
1849                  * macs, so instead use the internal MAC resets
1850                  */
1851                 if (!EFX_IS10G(efx)) {
1852                         EFX_POPULATE_OWORD_1(reg, FRF_AB_GM_SW_RST, 1);
1853                         efx_writeo(efx, &reg, FR_AB_GM_CFG1);
1854                         udelay(1000);
1855
1856                         EFX_POPULATE_OWORD_1(reg, FRF_AB_GM_SW_RST, 0);
1857                         efx_writeo(efx, &reg, FR_AB_GM_CFG1);
1858                         udelay(1000);
1859                         return;
1860                 } else {
1861                         EFX_POPULATE_OWORD_1(reg, FRF_AB_XM_CORE_RST, 1);
1862                         efx_writeo(efx, &reg, FR_AB_XM_GLB_CFG);
1863
1864                         for (count = 0; count < 10000; count++) {
1865                                 efx_reado(efx, &reg, FR_AB_XM_GLB_CFG);
1866                                 if (EFX_OWORD_FIELD(reg, FRF_AB_XM_CORE_RST) ==
1867                                     0)
1868                                         return;
1869                                 udelay(10);
1870                         }
1871
1872                         EFX_ERR(efx, "timed out waiting for XMAC core reset\n");
1873                 }
1874         }
1875
1876         /* Mac stats will fail whist the TX fifo is draining */
1877         WARN_ON(nic_data->stats_disable_count == 0);
1878
1879         efx_reado(efx, &mac_ctrl, FR_AB_MAC_CTRL);
1880         EFX_SET_OWORD_FIELD(mac_ctrl, FRF_BB_TXFIFO_DRAIN_EN, 1);
1881         efx_writeo(efx, &mac_ctrl, FR_AB_MAC_CTRL);
1882
1883         efx_reado(efx, &reg, FR_AB_GLB_CTL);
1884         EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_XGTX, 1);
1885         EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_XGRX, 1);
1886         EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_EM, 1);
1887         efx_writeo(efx, &reg, FR_AB_GLB_CTL);
1888
1889         count = 0;
1890         while (1) {
1891                 efx_reado(efx, &reg, FR_AB_GLB_CTL);
1892                 if (!EFX_OWORD_FIELD(reg, FRF_AB_RST_XGTX) &&
1893                     !EFX_OWORD_FIELD(reg, FRF_AB_RST_XGRX) &&
1894                     !EFX_OWORD_FIELD(reg, FRF_AB_RST_EM)) {
1895                         EFX_LOG(efx, "Completed MAC reset after %d loops\n",
1896                                 count);
1897                         break;
1898                 }
1899                 if (count > 20) {
1900                         EFX_ERR(efx, "MAC reset failed\n");
1901                         break;
1902                 }
1903                 count++;
1904                 udelay(10);
1905         }
1906
1907         /* Ensure the correct MAC is selected before statistics
1908          * are re-enabled by the caller */
1909         efx_writeo(efx, &mac_ctrl, FR_AB_MAC_CTRL);
1910 }
1911
1912 void falcon_drain_tx_fifo(struct efx_nic *efx)
1913 {
1914         efx_oword_t reg;
1915
1916         if ((efx_nic_rev(efx) < EFX_REV_FALCON_B0) ||
1917             (efx->loopback_mode != LOOPBACK_NONE))
1918                 return;
1919
1920         efx_reado(efx, &reg, FR_AB_MAC_CTRL);
1921         /* There is no point in draining more than once */
1922         if (EFX_OWORD_FIELD(reg, FRF_BB_TXFIFO_DRAIN_EN))
1923                 return;
1924
1925         falcon_reset_macs(efx);
1926 }
1927
1928 static void falcon_deconfigure_mac_wrapper(struct efx_nic *efx)
1929 {
1930         efx_oword_t reg;
1931
1932         if (efx_nic_rev(efx) < EFX_REV_FALCON_B0)
1933                 return;
1934
1935         /* Isolate the MAC -> RX */
1936         efx_reado(efx, &reg, FR_AZ_RX_CFG);
1937         EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 0);
1938         efx_writeo(efx, &reg, FR_AZ_RX_CFG);
1939
1940         /* Isolate TX -> MAC */
1941         falcon_drain_tx_fifo(efx);
1942 }
1943
1944 void falcon_reconfigure_mac_wrapper(struct efx_nic *efx)
1945 {
1946         struct efx_link_state *link_state = &efx->link_state;
1947         efx_oword_t reg;
1948         int link_speed;
1949
1950         switch (link_state->speed) {
1951         case 10000: link_speed = 3; break;
1952         case 1000:  link_speed = 2; break;
1953         case 100:   link_speed = 1; break;
1954         default:    link_speed = 0; break;
1955         }
1956         /* MAC_LINK_STATUS controls MAC backpressure but doesn't work
1957          * as advertised.  Disable to ensure packets are not
1958          * indefinitely held and TX queue can be flushed at any point
1959          * while the link is down. */
1960         EFX_POPULATE_OWORD_5(reg,
1961                              FRF_AB_MAC_XOFF_VAL, 0xffff /* max pause time */,
1962                              FRF_AB_MAC_BCAD_ACPT, 1,
1963                              FRF_AB_MAC_UC_PROM, efx->promiscuous,
1964                              FRF_AB_MAC_LINK_STATUS, 1, /* always set */
1965                              FRF_AB_MAC_SPEED, link_speed);
1966         /* On B0, MAC backpressure can be disabled and packets get
1967          * discarded. */
1968         if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) {
1969                 EFX_SET_OWORD_FIELD(reg, FRF_BB_TXFIFO_DRAIN_EN,
1970                                     !link_state->up);
1971         }
1972
1973         efx_writeo(efx, &reg, FR_AB_MAC_CTRL);
1974
1975         /* Restore the multicast hash registers. */
1976         falcon_push_multicast_hash(efx);
1977
1978         efx_reado(efx, &reg, FR_AZ_RX_CFG);
1979         /* Enable XOFF signal from RX FIFO (we enabled it during NIC
1980          * initialisation but it may read back as 0) */
1981         EFX_SET_OWORD_FIELD(reg, FRF_AZ_RX_XOFF_MAC_EN, 1);
1982         /* Unisolate the MAC -> RX */
1983         if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0)
1984                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 1);
1985         efx_writeo(efx, &reg, FR_AZ_RX_CFG);
1986 }
1987
1988 static void falcon_stats_request(struct efx_nic *efx)
1989 {
1990         struct falcon_nic_data *nic_data = efx->nic_data;
1991         efx_oword_t reg;
1992
1993         WARN_ON(nic_data->stats_pending);
1994         WARN_ON(nic_data->stats_disable_count);
1995
1996         if (nic_data->stats_dma_done == NULL)
1997                 return; /* no mac selected */
1998
1999         *nic_data->stats_dma_done = FALCON_STATS_NOT_DONE;
2000         nic_data->stats_pending = true;
2001         wmb(); /* ensure done flag is clear */
2002
2003         /* Initiate DMA transfer of stats */
2004         EFX_POPULATE_OWORD_2(reg,
2005                              FRF_AB_MAC_STAT_DMA_CMD, 1,
2006                              FRF_AB_MAC_STAT_DMA_ADR,
2007                              efx->stats_buffer.dma_addr);
2008         efx_writeo(efx, &reg, FR_AB_MAC_STAT_DMA);
2009
2010         mod_timer(&nic_data->stats_timer, round_jiffies_up(jiffies + HZ / 2));
2011 }
2012
2013 static void falcon_stats_complete(struct efx_nic *efx)
2014 {
2015         struct falcon_nic_data *nic_data = efx->nic_data;
2016
2017         if (!nic_data->stats_pending)
2018                 return;
2019
2020         nic_data->stats_pending = 0;
2021         if (*nic_data->stats_dma_done == FALCON_STATS_DONE) {
2022                 rmb(); /* read the done flag before the stats */
2023                 efx->mac_op->update_stats(efx);
2024         } else {
2025                 EFX_ERR(efx, "timed out waiting for statistics\n");
2026         }
2027 }
2028
2029 static void falcon_stats_timer_func(unsigned long context)
2030 {
2031         struct efx_nic *efx = (struct efx_nic *)context;
2032         struct falcon_nic_data *nic_data = efx->nic_data;
2033
2034         spin_lock(&efx->stats_lock);
2035
2036         falcon_stats_complete(efx);
2037         if (nic_data->stats_disable_count == 0)
2038                 falcon_stats_request(efx);
2039
2040         spin_unlock(&efx->stats_lock);
2041 }
2042
2043 static void falcon_switch_mac(struct efx_nic *efx);
2044
2045 static bool falcon_loopback_link_poll(struct efx_nic *efx)
2046 {
2047         struct efx_link_state old_state = efx->link_state;
2048
2049         WARN_ON(!mutex_is_locked(&efx->mac_lock));
2050         WARN_ON(!LOOPBACK_INTERNAL(efx));
2051
2052         efx->link_state.fd = true;
2053         efx->link_state.fc = efx->wanted_fc;
2054         efx->link_state.up = true;
2055
2056         if (efx->loopback_mode == LOOPBACK_GMAC)
2057                 efx->link_state.speed = 1000;
2058         else
2059                 efx->link_state.speed = 10000;
2060
2061         return !efx_link_state_equal(&efx->link_state, &old_state);
2062 }
2063
2064 static int falcon_reconfigure_port(struct efx_nic *efx)
2065 {
2066         int rc;
2067
2068         WARN_ON(efx_nic_rev(efx) > EFX_REV_FALCON_B0);
2069
2070         /* Poll the PHY link state *before* reconfiguring it. This means we
2071          * will pick up the correct speed (in loopback) to select the correct
2072          * MAC.
2073          */
2074         if (LOOPBACK_INTERNAL(efx))
2075                 falcon_loopback_link_poll(efx);
2076         else
2077                 efx->phy_op->poll(efx);
2078
2079         falcon_stop_nic_stats(efx);
2080         falcon_deconfigure_mac_wrapper(efx);
2081
2082         falcon_switch_mac(efx);
2083
2084         efx->phy_op->reconfigure(efx);
2085         rc = efx->mac_op->reconfigure(efx);
2086         BUG_ON(rc);
2087
2088         falcon_start_nic_stats(efx);
2089
2090         /* Synchronise efx->link_state with the kernel */
2091         efx_link_status_changed(efx);
2092
2093         return 0;
2094 }
2095
2096 /**************************************************************************
2097  *
2098  * PHY access via GMII
2099  *
2100  **************************************************************************
2101  */
2102
2103 /* Wait for GMII access to complete */
2104 static int falcon_gmii_wait(struct efx_nic *efx)
2105 {
2106         efx_oword_t md_stat;
2107         int count;
2108
2109         /* wait upto 50ms - taken max from datasheet */
2110         for (count = 0; count < 5000; count++) {
2111                 efx_reado(efx, &md_stat, FR_AB_MD_STAT);
2112                 if (EFX_OWORD_FIELD(md_stat, FRF_AB_MD_BSY) == 0) {
2113                         if (EFX_OWORD_FIELD(md_stat, FRF_AB_MD_LNFL) != 0 ||
2114                             EFX_OWORD_FIELD(md_stat, FRF_AB_MD_BSERR) != 0) {
2115                                 EFX_ERR(efx, "error from GMII access "
2116                                         EFX_OWORD_FMT"\n",
2117                                         EFX_OWORD_VAL(md_stat));
2118                                 return -EIO;
2119                         }
2120                         return 0;
2121                 }
2122                 udelay(10);
2123         }
2124         EFX_ERR(efx, "timed out waiting for GMII\n");
2125         return -ETIMEDOUT;
2126 }
2127
2128 /* Write an MDIO register of a PHY connected to Falcon. */
2129 static int falcon_mdio_write(struct net_device *net_dev,
2130                              int prtad, int devad, u16 addr, u16 value)
2131 {
2132         struct efx_nic *efx = netdev_priv(net_dev);
2133         efx_oword_t reg;
2134         int rc;
2135
2136         EFX_REGDUMP(efx, "writing MDIO %d register %d.%d with 0x%04x\n",
2137                     prtad, devad, addr, value);
2138
2139         mutex_lock(&efx->mdio_lock);
2140
2141         /* Check MDIO not currently being accessed */
2142         rc = falcon_gmii_wait(efx);
2143         if (rc)
2144                 goto out;
2145
2146         /* Write the address/ID register */
2147         EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_PHY_ADR, addr);
2148         efx_writeo(efx, &reg, FR_AB_MD_PHY_ADR);
2149
2150         EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_PRT_ADR, prtad,
2151                              FRF_AB_MD_DEV_ADR, devad);
2152         efx_writeo(efx, &reg, FR_AB_MD_ID);
2153
2154         /* Write data */
2155         EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_TXD, value);
2156         efx_writeo(efx, &reg, FR_AB_MD_TXD);
2157
2158         EFX_POPULATE_OWORD_2(reg,
2159                              FRF_AB_MD_WRC, 1,
2160                              FRF_AB_MD_GC, 0);
2161         efx_writeo(efx, &reg, FR_AB_MD_CS);
2162
2163         /* Wait for data to be written */
2164         rc = falcon_gmii_wait(efx);
2165         if (rc) {
2166                 /* Abort the write operation */
2167                 EFX_POPULATE_OWORD_2(reg,
2168                                      FRF_AB_MD_WRC, 0,
2169                                      FRF_AB_MD_GC, 1);
2170                 efx_writeo(efx, &reg, FR_AB_MD_CS);
2171                 udelay(10);
2172         }
2173
2174 out:
2175         mutex_unlock(&efx->mdio_lock);
2176         return rc;
2177 }
2178
2179 /* Read an MDIO register of a PHY connected to Falcon. */
2180 static int falcon_mdio_read(struct net_device *net_dev,
2181                             int prtad, int devad, u16 addr)
2182 {
2183         struct efx_nic *efx = netdev_priv(net_dev);
2184         efx_oword_t reg;
2185         int rc;
2186
2187         mutex_lock(&efx->mdio_lock);
2188
2189         /* Check MDIO not currently being accessed */
2190         rc = falcon_gmii_wait(efx);
2191         if (rc)
2192                 goto out;
2193
2194         EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_PHY_ADR, addr);
2195         efx_writeo(efx, &reg, FR_AB_MD_PHY_ADR);
2196
2197         EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_PRT_ADR, prtad,
2198                              FRF_AB_MD_DEV_ADR, devad);
2199         efx_writeo(efx, &reg, FR_AB_MD_ID);
2200
2201         /* Request data to be read */
2202         EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_RDC, 1, FRF_AB_MD_GC, 0);
2203         efx_writeo(efx, &reg, FR_AB_MD_CS);
2204
2205         /* Wait for data to become available */
2206         rc = falcon_gmii_wait(efx);
2207         if (rc == 0) {
2208                 efx_reado(efx, &reg, FR_AB_MD_RXD);
2209                 rc = EFX_OWORD_FIELD(reg, FRF_AB_MD_RXD);
2210                 EFX_REGDUMP(efx, "read from MDIO %d register %d.%d, got %04x\n",
2211                             prtad, devad, addr, rc);
2212         } else {
2213                 /* Abort the read operation */
2214                 EFX_POPULATE_OWORD_2(reg,
2215                                      FRF_AB_MD_RIC, 0,
2216                                      FRF_AB_MD_GC, 1);
2217                 efx_writeo(efx, &reg, FR_AB_MD_CS);
2218
2219                 EFX_LOG(efx, "read from MDIO %d register %d.%d, got error %d\n",
2220                         prtad, devad, addr, rc);
2221         }
2222
2223 out:
2224         mutex_unlock(&efx->mdio_lock);
2225         return rc;
2226 }
2227
2228 static void falcon_clock_mac(struct efx_nic *efx)
2229 {
2230         unsigned strap_val;
2231         efx_oword_t nic_stat;
2232
2233         /* Configure the NIC generated MAC clock correctly */
2234         efx_reado(efx, &nic_stat, FR_AB_NIC_STAT);
2235         strap_val = EFX_IS10G(efx) ? 5 : 3;
2236         if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) {
2237                 EFX_SET_OWORD_FIELD(nic_stat, FRF_BB_EE_STRAP_EN, 1);
2238                 EFX_SET_OWORD_FIELD(nic_stat, FRF_BB_EE_STRAP, strap_val);
2239                 efx_writeo(efx, &nic_stat, FR_AB_NIC_STAT);
2240         } else {
2241                 /* Falcon A1 does not support 1G/10G speed switching
2242                  * and must not be used with a PHY that does. */
2243                 BUG_ON(EFX_OWORD_FIELD(nic_stat, FRF_AB_STRAP_PINS) !=
2244                        strap_val);
2245         }
2246 }
2247
2248 static void falcon_switch_mac(struct efx_nic *efx)
2249 {
2250         struct efx_mac_operations *old_mac_op = efx->mac_op;
2251         struct falcon_nic_data *nic_data = efx->nic_data;
2252         unsigned int stats_done_offset;
2253
2254         WARN_ON(!mutex_is_locked(&efx->mac_lock));
2255         WARN_ON(nic_data->stats_disable_count == 0);
2256
2257         efx->mac_op = (EFX_IS10G(efx) ?
2258                        &falcon_xmac_operations : &falcon_gmac_operations);
2259
2260         if (EFX_IS10G(efx))
2261                 stats_done_offset = XgDmaDone_offset;
2262         else
2263                 stats_done_offset = GDmaDone_offset;
2264         nic_data->stats_dma_done = efx->stats_buffer.addr + stats_done_offset;
2265
2266         if (old_mac_op == efx->mac_op)
2267                 return;
2268
2269         falcon_clock_mac(efx);
2270
2271         EFX_LOG(efx, "selected %cMAC\n", EFX_IS10G(efx) ? 'X' : 'G');
2272         /* Not all macs support a mac-level link state */
2273         efx->xmac_poll_required = false;
2274         falcon_reset_macs(efx);
2275 }
2276
2277 /* This call is responsible for hooking in the MAC and PHY operations */
2278 static int falcon_probe_port(struct efx_nic *efx)
2279 {
2280         int rc;
2281
2282         switch (efx->phy_type) {
2283         case PHY_TYPE_SFX7101:
2284                 efx->phy_op = &falcon_sfx7101_phy_ops;
2285                 break;
2286         case PHY_TYPE_SFT9001A:
2287         case PHY_TYPE_SFT9001B:
2288                 efx->phy_op = &falcon_sft9001_phy_ops;
2289                 break;
2290         case PHY_TYPE_QT2022C2:
2291         case PHY_TYPE_QT2025C:
2292                 efx->phy_op = &falcon_qt202x_phy_ops;
2293                 break;
2294         default:
2295                 EFX_ERR(efx, "Unknown PHY type %d\n",
2296                         efx->phy_type);
2297                 return -ENODEV;
2298         }
2299
2300         if (efx->phy_op->macs & EFX_XMAC)
2301                 efx->loopback_modes |= ((1 << LOOPBACK_XGMII) |
2302                                         (1 << LOOPBACK_XGXS) |
2303                                         (1 << LOOPBACK_XAUI));
2304         if (efx->phy_op->macs & EFX_GMAC)
2305                 efx->loopback_modes |= (1 << LOOPBACK_GMAC);
2306         efx->loopback_modes |= efx->phy_op->loopbacks;
2307
2308         /* Set up MDIO structure for PHY */
2309         efx->mdio.mmds = efx->phy_op->mmds;
2310         efx->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
2311         efx->mdio.mdio_read = falcon_mdio_read;
2312         efx->mdio.mdio_write = falcon_mdio_write;
2313
2314         /* Initial assumption */
2315         efx->link_state.speed = 10000;
2316         efx->link_state.fd = true;
2317
2318         /* Hardware flow ctrl. FalconA RX FIFO too small for pause generation */
2319         if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0)
2320                 efx->wanted_fc = EFX_FC_RX | EFX_FC_TX;
2321         else
2322                 efx->wanted_fc = EFX_FC_RX;
2323
2324         /* Allocate buffer for stats */
2325         rc = falcon_alloc_buffer(efx, &efx->stats_buffer,
2326                                  FALCON_MAC_STATS_SIZE);
2327         if (rc)
2328                 return rc;
2329         EFX_LOG(efx, "stats buffer at %llx (virt %p phys %llx)\n",
2330                 (u64)efx->stats_buffer.dma_addr,
2331                 efx->stats_buffer.addr,
2332                 (u64)virt_to_phys(efx->stats_buffer.addr));
2333
2334         return 0;
2335 }
2336
2337 static void falcon_remove_port(struct efx_nic *efx)
2338 {
2339         falcon_free_buffer(efx, &efx->stats_buffer);
2340 }
2341
2342 /**************************************************************************
2343  *
2344  * Falcon test code
2345  *
2346  **************************************************************************/
2347
2348 int falcon_read_nvram(struct efx_nic *efx, struct falcon_nvconfig *nvconfig_out)
2349 {
2350         struct falcon_nvconfig *nvconfig;
2351         struct efx_spi_device *spi;
2352         void *region;
2353         int rc, magic_num, struct_ver;
2354         __le16 *word, *limit;
2355         u32 csum;
2356
2357         spi = efx->spi_flash ? efx->spi_flash : efx->spi_eeprom;
2358         if (!spi)
2359                 return -EINVAL;
2360
2361         region = kmalloc(FALCON_NVCONFIG_END, GFP_KERNEL);
2362         if (!region)
2363                 return -ENOMEM;
2364         nvconfig = region + FALCON_NVCONFIG_OFFSET;
2365
2366         mutex_lock(&efx->spi_lock);
2367         rc = falcon_spi_read(spi, 0, FALCON_NVCONFIG_END, NULL, region);
2368         mutex_unlock(&efx->spi_lock);
2369         if (rc) {
2370                 EFX_ERR(efx, "Failed to read %s\n",
2371                         efx->spi_flash ? "flash" : "EEPROM");
2372                 rc = -EIO;
2373                 goto out;
2374         }
2375
2376         magic_num = le16_to_cpu(nvconfig->board_magic_num);
2377         struct_ver = le16_to_cpu(nvconfig->board_struct_ver);
2378
2379         rc = -EINVAL;
2380         if (magic_num != FALCON_NVCONFIG_BOARD_MAGIC_NUM) {
2381                 EFX_ERR(efx, "NVRAM bad magic 0x%x\n", magic_num);
2382                 goto out;
2383         }
2384         if (struct_ver < 2) {
2385                 EFX_ERR(efx, "NVRAM has ancient version 0x%x\n", struct_ver);
2386                 goto out;
2387         } else if (struct_ver < 4) {
2388                 word = &nvconfig->board_magic_num;
2389                 limit = (__le16 *) (nvconfig + 1);
2390         } else {
2391                 word = region;
2392                 limit = region + FALCON_NVCONFIG_END;
2393         }
2394         for (csum = 0; word < limit; ++word)
2395                 csum += le16_to_cpu(*word);
2396
2397         if (~csum & 0xffff) {
2398                 EFX_ERR(efx, "NVRAM has incorrect checksum\n");
2399                 goto out;
2400         }
2401
2402         rc = 0;
2403         if (nvconfig_out)
2404                 memcpy(nvconfig_out, nvconfig, sizeof(*nvconfig));
2405
2406  out:
2407         kfree(region);
2408         return rc;
2409 }
2410
2411 /* Registers tested in the falcon register test */
2412 static struct {
2413         unsigned address;
2414         efx_oword_t mask;
2415 } efx_test_registers[] = {
2416         { FR_AZ_ADR_REGION,
2417           EFX_OWORD32(0x0001FFFF, 0x0001FFFF, 0x0001FFFF, 0x0001FFFF) },
2418         { FR_AZ_RX_CFG,
2419           EFX_OWORD32(0xFFFFFFFE, 0x00017FFF, 0x00000000, 0x00000000) },
2420         { FR_AZ_TX_CFG,
2421           EFX_OWORD32(0x7FFF0037, 0x00000000, 0x00000000, 0x00000000) },
2422         { FR_AZ_TX_RESERVED,
2423           EFX_OWORD32(0xFFFEFE80, 0x1FFFFFFF, 0x020000FE, 0x007FFFFF) },
2424         { FR_AB_MAC_CTRL,
2425           EFX_OWORD32(0xFFFF0000, 0x00000000, 0x00000000, 0x00000000) },
2426         { FR_AZ_SRM_TX_DC_CFG,
2427           EFX_OWORD32(0x001FFFFF, 0x00000000, 0x00000000, 0x00000000) },
2428         { FR_AZ_RX_DC_CFG,
2429           EFX_OWORD32(0x0000000F, 0x00000000, 0x00000000, 0x00000000) },
2430         { FR_AZ_RX_DC_PF_WM,
2431           EFX_OWORD32(0x000003FF, 0x00000000, 0x00000000, 0x00000000) },
2432         { FR_BZ_DP_CTRL,
2433           EFX_OWORD32(0x00000FFF, 0x00000000, 0x00000000, 0x00000000) },
2434         { FR_AB_GM_CFG2,
2435           EFX_OWORD32(0x00007337, 0x00000000, 0x00000000, 0x00000000) },
2436         { FR_AB_GMF_CFG0,
2437           EFX_OWORD32(0x00001F1F, 0x00000000, 0x00000000, 0x00000000) },
2438         { FR_AB_XM_GLB_CFG,
2439           EFX_OWORD32(0x00000C68, 0x00000000, 0x00000000, 0x00000000) },
2440         { FR_AB_XM_TX_CFG,
2441           EFX_OWORD32(0x00080164, 0x00000000, 0x00000000, 0x00000000) },
2442         { FR_AB_XM_RX_CFG,
2443           EFX_OWORD32(0x07100A0C, 0x00000000, 0x00000000, 0x00000000) },
2444         { FR_AB_XM_RX_PARAM,
2445           EFX_OWORD32(0x00001FF8, 0x00000000, 0x00000000, 0x00000000) },
2446         { FR_AB_XM_FC,
2447           EFX_OWORD32(0xFFFF0001, 0x00000000, 0x00000000, 0x00000000) },
2448         { FR_AB_XM_ADR_LO,
2449           EFX_OWORD32(0xFFFFFFFF, 0x00000000, 0x00000000, 0x00000000) },
2450         { FR_AB_XX_SD_CTL,
2451           EFX_OWORD32(0x0003FF0F, 0x00000000, 0x00000000, 0x00000000) },
2452 };
2453
2454 static bool efx_masked_compare_oword(const efx_oword_t *a, const efx_oword_t *b,
2455                                      const efx_oword_t *mask)
2456 {
2457         return ((a->u64[0] ^ b->u64[0]) & mask->u64[0]) ||
2458                 ((a->u64[1] ^ b->u64[1]) & mask->u64[1]);
2459 }
2460
2461 int falcon_test_registers(struct efx_nic *efx)
2462 {
2463         unsigned address = 0, i, j;
2464         efx_oword_t mask, imask, original, reg, buf;
2465
2466         /* Falcon should be in loopback to isolate the XMAC from the PHY */
2467         WARN_ON(!LOOPBACK_INTERNAL(efx));
2468
2469         for (i = 0; i < ARRAY_SIZE(efx_test_registers); ++i) {
2470                 address = efx_test_registers[i].address;
2471                 mask = imask = efx_test_registers[i].mask;
2472                 EFX_INVERT_OWORD(imask);
2473
2474                 efx_reado(efx, &original, address);
2475
2476                 /* bit sweep on and off */
2477                 for (j = 0; j < 128; j++) {
2478                         if (!EFX_EXTRACT_OWORD32(mask, j, j))
2479                                 continue;
2480
2481                         /* Test this testable bit can be set in isolation */
2482                         EFX_AND_OWORD(reg, original, mask);
2483                         EFX_SET_OWORD32(reg, j, j, 1);
2484
2485                         efx_writeo(efx, &reg, address);
2486                         efx_reado(efx, &buf, address);
2487
2488                         if (efx_masked_compare_oword(&reg, &buf, &mask))
2489                                 goto fail;
2490
2491                         /* Test this testable bit can be cleared in isolation */
2492                         EFX_OR_OWORD(reg, original, mask);
2493                         EFX_SET_OWORD32(reg, j, j, 0);
2494
2495                         efx_writeo(efx, &reg, address);
2496                         efx_reado(efx, &buf, address);
2497
2498                         if (efx_masked_compare_oword(&reg, &buf, &mask))
2499                                 goto fail;
2500                 }
2501
2502                 efx_writeo(efx, &original, address);
2503         }
2504
2505         return 0;
2506
2507 fail:
2508         EFX_ERR(efx, "wrote "EFX_OWORD_FMT" read "EFX_OWORD_FMT
2509                 " at address 0x%x mask "EFX_OWORD_FMT"\n", EFX_OWORD_VAL(reg),
2510                 EFX_OWORD_VAL(buf), address, EFX_OWORD_VAL(mask));
2511         return -EIO;
2512 }
2513
2514 /**************************************************************************
2515  *
2516  * Device reset
2517  *
2518  **************************************************************************
2519  */
2520
2521 /* Resets NIC to known state.  This routine must be called in process
2522  * context and is allowed to sleep. */
2523 static int falcon_reset_hw(struct efx_nic *efx, enum reset_type method)
2524 {
2525         struct falcon_nic_data *nic_data = efx->nic_data;
2526         efx_oword_t glb_ctl_reg_ker;
2527         int rc;
2528
2529         EFX_LOG(efx, "performing %s hardware reset\n", RESET_TYPE(method));
2530
2531         /* Initiate device reset */
2532         if (method == RESET_TYPE_WORLD) {
2533                 rc = pci_save_state(efx->pci_dev);
2534                 if (rc) {
2535                         EFX_ERR(efx, "failed to backup PCI state of primary "
2536                                 "function prior to hardware reset\n");
2537                         goto fail1;
2538                 }
2539                 if (FALCON_IS_DUAL_FUNC(efx)) {
2540                         rc = pci_save_state(nic_data->pci_dev2);
2541                         if (rc) {
2542                                 EFX_ERR(efx, "failed to backup PCI state of "
2543                                         "secondary function prior to "
2544                                         "hardware reset\n");
2545                                 goto fail2;
2546                         }
2547                 }
2548
2549                 EFX_POPULATE_OWORD_2(glb_ctl_reg_ker,
2550                                      FRF_AB_EXT_PHY_RST_DUR,
2551                                      FFE_AB_EXT_PHY_RST_DUR_10240US,
2552                                      FRF_AB_SWRST, 1);
2553         } else {
2554                 EFX_POPULATE_OWORD_7(glb_ctl_reg_ker,
2555                                      /* exclude PHY from "invisible" reset */
2556                                      FRF_AB_EXT_PHY_RST_CTL,
2557                                      method == RESET_TYPE_INVISIBLE,
2558                                      /* exclude EEPROM/flash and PCIe */
2559                                      FRF_AB_PCIE_CORE_RST_CTL, 1,
2560                                      FRF_AB_PCIE_NSTKY_RST_CTL, 1,
2561                                      FRF_AB_PCIE_SD_RST_CTL, 1,
2562                                      FRF_AB_EE_RST_CTL, 1,
2563                                      FRF_AB_EXT_PHY_RST_DUR,
2564                                      FFE_AB_EXT_PHY_RST_DUR_10240US,
2565                                      FRF_AB_SWRST, 1);
2566         }
2567         efx_writeo(efx, &glb_ctl_reg_ker, FR_AB_GLB_CTL);
2568
2569         EFX_LOG(efx, "waiting for hardware reset\n");
2570         schedule_timeout_uninterruptible(HZ / 20);
2571
2572         /* Restore PCI configuration if needed */
2573         if (method == RESET_TYPE_WORLD) {
2574                 if (FALCON_IS_DUAL_FUNC(efx)) {
2575                         rc = pci_restore_state(nic_data->pci_dev2);
2576                         if (rc) {
2577                                 EFX_ERR(efx, "failed to restore PCI config for "
2578                                         "the secondary function\n");
2579                                 goto fail3;
2580                         }
2581                 }
2582                 rc = pci_restore_state(efx->pci_dev);
2583                 if (rc) {
2584                         EFX_ERR(efx, "failed to restore PCI config for the "
2585                                 "primary function\n");
2586                         goto fail4;
2587                 }
2588                 EFX_LOG(efx, "successfully restored PCI config\n");
2589         }
2590
2591         /* Assert that reset complete */
2592         efx_reado(efx, &glb_ctl_reg_ker, FR_AB_GLB_CTL);
2593         if (EFX_OWORD_FIELD(glb_ctl_reg_ker, FRF_AB_SWRST) != 0) {
2594                 rc = -ETIMEDOUT;
2595                 EFX_ERR(efx, "timed out waiting for hardware reset\n");
2596                 goto fail5;
2597         }
2598         EFX_LOG(efx, "hardware reset complete\n");
2599
2600         return 0;
2601
2602         /* pci_save_state() and pci_restore_state() MUST be called in pairs */
2603 fail2:
2604 fail3:
2605         pci_restore_state(efx->pci_dev);
2606 fail1:
2607 fail4:
2608 fail5:
2609         return rc;
2610 }
2611
2612 static void falcon_monitor(struct efx_nic *efx)
2613 {
2614         bool link_changed;
2615         int rc;
2616
2617         BUG_ON(!mutex_is_locked(&efx->mac_lock));
2618
2619         rc = falcon_board(efx)->type->monitor(efx);
2620         if (rc) {
2621                 EFX_ERR(efx, "Board sensor %s; shutting down PHY\n",
2622                         (rc == -ERANGE) ? "reported fault" : "failed");
2623                 efx->phy_mode |= PHY_MODE_LOW_POWER;
2624                 rc = __efx_reconfigure_port(efx);
2625                 WARN_ON(rc);
2626         }
2627
2628         if (LOOPBACK_INTERNAL(efx))
2629                 link_changed = falcon_loopback_link_poll(efx);
2630         else
2631                 link_changed = efx->phy_op->poll(efx);
2632
2633         if (link_changed) {
2634                 falcon_stop_nic_stats(efx);
2635                 falcon_deconfigure_mac_wrapper(efx);
2636
2637                 falcon_switch_mac(efx);
2638                 rc = efx->mac_op->reconfigure(efx);
2639                 BUG_ON(rc);
2640
2641                 falcon_start_nic_stats(efx);
2642
2643                 efx_link_status_changed(efx);
2644         }
2645
2646         if (EFX_IS10G(efx))
2647                 falcon_poll_xmac(efx);
2648 }
2649
2650 /* Zeroes out the SRAM contents.  This routine must be called in
2651  * process context and is allowed to sleep.
2652  */
2653 static int falcon_reset_sram(struct efx_nic *efx)
2654 {
2655         efx_oword_t srm_cfg_reg_ker, gpio_cfg_reg_ker;
2656         int count;
2657
2658         /* Set the SRAM wake/sleep GPIO appropriately. */
2659         efx_reado(efx, &gpio_cfg_reg_ker, FR_AB_GPIO_CTL);
2660         EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, FRF_AB_GPIO1_OEN, 1);
2661         EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, FRF_AB_GPIO1_OUT, 1);
2662         efx_writeo(efx, &gpio_cfg_reg_ker, FR_AB_GPIO_CTL);
2663
2664         /* Initiate SRAM reset */
2665         EFX_POPULATE_OWORD_2(srm_cfg_reg_ker,
2666                              FRF_AZ_SRM_INIT_EN, 1,
2667                              FRF_AZ_SRM_NB_SZ, 0);
2668         efx_writeo(efx, &srm_cfg_reg_ker, FR_AZ_SRM_CFG);
2669
2670         /* Wait for SRAM reset to complete */
2671         count = 0;
2672         do {
2673                 EFX_LOG(efx, "waiting for SRAM reset (attempt %d)...\n", count);
2674
2675                 /* SRAM reset is slow; expect around 16ms */
2676                 schedule_timeout_uninterruptible(HZ / 50);
2677
2678                 /* Check for reset complete */
2679                 efx_reado(efx, &srm_cfg_reg_ker, FR_AZ_SRM_CFG);
2680                 if (!EFX_OWORD_FIELD(srm_cfg_reg_ker, FRF_AZ_SRM_INIT_EN)) {
2681                         EFX_LOG(efx, "SRAM reset complete\n");
2682
2683                         return 0;
2684                 }
2685         } while (++count < 20); /* wait upto 0.4 sec */
2686
2687         EFX_ERR(efx, "timed out waiting for SRAM reset\n");
2688         return -ETIMEDOUT;
2689 }
2690
2691 static int falcon_spi_device_init(struct efx_nic *efx,
2692                                   struct efx_spi_device **spi_device_ret,
2693                                   unsigned int device_id, u32 device_type)
2694 {
2695         struct efx_spi_device *spi_device;
2696
2697         if (device_type != 0) {
2698                 spi_device = kzalloc(sizeof(*spi_device), GFP_KERNEL);
2699                 if (!spi_device)
2700                         return -ENOMEM;
2701                 spi_device->device_id = device_id;
2702                 spi_device->size =
2703                         1 << SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_SIZE);
2704                 spi_device->addr_len =
2705                         SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_ADDR_LEN);
2706                 spi_device->munge_address = (spi_device->size == 1 << 9 &&
2707                                              spi_device->addr_len == 1);
2708                 spi_device->erase_command =
2709                         SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_ERASE_CMD);
2710                 spi_device->erase_size =
2711                         1 << SPI_DEV_TYPE_FIELD(device_type,
2712                                                 SPI_DEV_TYPE_ERASE_SIZE);
2713                 spi_device->block_size =
2714                         1 << SPI_DEV_TYPE_FIELD(device_type,
2715                                                 SPI_DEV_TYPE_BLOCK_SIZE);
2716
2717                 spi_device->efx = efx;
2718         } else {
2719                 spi_device = NULL;
2720         }
2721
2722         kfree(*spi_device_ret);
2723         *spi_device_ret = spi_device;
2724         return 0;
2725 }
2726
2727
2728 static void falcon_remove_spi_devices(struct efx_nic *efx)
2729 {
2730         kfree(efx->spi_eeprom);
2731         efx->spi_eeprom = NULL;
2732         kfree(efx->spi_flash);
2733         efx->spi_flash = NULL;
2734 }
2735
2736 /* Extract non-volatile configuration */
2737 static int falcon_probe_nvconfig(struct efx_nic *efx)
2738 {
2739         struct falcon_nvconfig *nvconfig;
2740         int board_rev;
2741         int rc;
2742
2743         nvconfig = kmalloc(sizeof(*nvconfig), GFP_KERNEL);
2744         if (!nvconfig)
2745                 return -ENOMEM;
2746
2747         rc = falcon_read_nvram(efx, nvconfig);
2748         if (rc == -EINVAL) {
2749                 EFX_ERR(efx, "NVRAM is invalid therefore using defaults\n");
2750                 efx->phy_type = PHY_TYPE_NONE;
2751                 efx->mdio.prtad = MDIO_PRTAD_NONE;
2752                 board_rev = 0;
2753                 rc = 0;
2754         } else if (rc) {
2755                 goto fail1;
2756         } else {
2757                 struct falcon_nvconfig_board_v2 *v2 = &nvconfig->board_v2;
2758                 struct falcon_nvconfig_board_v3 *v3 = &nvconfig->board_v3;
2759
2760                 efx->phy_type = v2->port0_phy_type;
2761                 efx->mdio.prtad = v2->port0_phy_addr;
2762                 board_rev = le16_to_cpu(v2->board_revision);
2763
2764                 if (le16_to_cpu(nvconfig->board_struct_ver) >= 3) {
2765                         rc = falcon_spi_device_init(
2766                                 efx, &efx->spi_flash, FFE_AB_SPI_DEVICE_FLASH,
2767                                 le32_to_cpu(v3->spi_device_type
2768                                             [FFE_AB_SPI_DEVICE_FLASH]));
2769                         if (rc)
2770                                 goto fail2;
2771                         rc = falcon_spi_device_init(
2772                                 efx, &efx->spi_eeprom, FFE_AB_SPI_DEVICE_EEPROM,
2773                                 le32_to_cpu(v3->spi_device_type
2774                                             [FFE_AB_SPI_DEVICE_EEPROM]));
2775                         if (rc)
2776                                 goto fail2;
2777                 }
2778         }
2779
2780         /* Read the MAC addresses */
2781         memcpy(efx->mac_address, nvconfig->mac_address[0], ETH_ALEN);
2782
2783         EFX_LOG(efx, "PHY is %d phy_id %d\n", efx->phy_type, efx->mdio.prtad);
2784
2785         falcon_probe_board(efx, board_rev);
2786
2787         kfree(nvconfig);
2788         return 0;
2789
2790  fail2:
2791         falcon_remove_spi_devices(efx);
2792  fail1:
2793         kfree(nvconfig);
2794         return rc;
2795 }
2796
2797 /* Probe the NIC variant (revision, ASIC vs FPGA, function count, port
2798  * count, port speed).  Set workaround and feature flags accordingly.
2799  */
2800 static int falcon_probe_nic_variant(struct efx_nic *efx)
2801 {
2802         efx_oword_t altera_build;
2803         efx_oword_t nic_stat;
2804
2805         efx_reado(efx, &altera_build, FR_AZ_ALTERA_BUILD);
2806         if (EFX_OWORD_FIELD(altera_build, FRF_AZ_ALTERA_BUILD_VER)) {
2807                 EFX_ERR(efx, "Falcon FPGA not supported\n");
2808                 return -ENODEV;
2809         }
2810
2811         efx_reado(efx, &nic_stat, FR_AB_NIC_STAT);
2812
2813         if (efx_nic_rev(efx) <= EFX_REV_FALCON_A1) {
2814                 u8 pci_rev = efx->pci_dev->revision;
2815
2816                 if ((pci_rev == 0xff) || (pci_rev == 0)) {
2817                         EFX_ERR(efx, "Falcon rev A0 not supported\n");
2818                         return -ENODEV;
2819                 }
2820                 if (EFX_OWORD_FIELD(nic_stat, FRF_AB_STRAP_10G) == 0) {
2821                         EFX_ERR(efx, "Falcon rev A1 1G not supported\n");
2822                         return -ENODEV;
2823                 }
2824                 if (EFX_OWORD_FIELD(nic_stat, FRF_AA_STRAP_PCIE) == 0) {
2825                         EFX_ERR(efx, "Falcon rev A1 PCI-X not supported\n");
2826                         return -ENODEV;
2827                 }
2828         }
2829
2830         return 0;
2831 }
2832
2833 /* Probe all SPI devices on the NIC */
2834 static void falcon_probe_spi_devices(struct efx_nic *efx)
2835 {
2836         efx_oword_t nic_stat, gpio_ctl, ee_vpd_cfg;
2837         int boot_dev;
2838
2839         efx_reado(efx, &gpio_ctl, FR_AB_GPIO_CTL);
2840         efx_reado(efx, &nic_stat, FR_AB_NIC_STAT);
2841         efx_reado(efx, &ee_vpd_cfg, FR_AB_EE_VPD_CFG0);
2842
2843         if (EFX_OWORD_FIELD(gpio_ctl, FRF_AB_GPIO3_PWRUP_VALUE)) {
2844                 boot_dev = (EFX_OWORD_FIELD(nic_stat, FRF_AB_SF_PRST) ?
2845                             FFE_AB_SPI_DEVICE_FLASH : FFE_AB_SPI_DEVICE_EEPROM);
2846                 EFX_LOG(efx, "Booted from %s\n",
2847                         boot_dev == FFE_AB_SPI_DEVICE_FLASH ? "flash" : "EEPROM");
2848         } else {
2849                 /* Disable VPD and set clock dividers to safe
2850                  * values for initial programming. */
2851                 boot_dev = -1;
2852                 EFX_LOG(efx, "Booted from internal ASIC settings;"
2853                         " setting SPI config\n");
2854                 EFX_POPULATE_OWORD_3(ee_vpd_cfg, FRF_AB_EE_VPD_EN, 0,
2855                                      /* 125 MHz / 7 ~= 20 MHz */
2856                                      FRF_AB_EE_SF_CLOCK_DIV, 7,
2857                                      /* 125 MHz / 63 ~= 2 MHz */
2858                                      FRF_AB_EE_EE_CLOCK_DIV, 63);
2859                 efx_writeo(efx, &ee_vpd_cfg, FR_AB_EE_VPD_CFG0);
2860         }
2861
2862         if (boot_dev == FFE_AB_SPI_DEVICE_FLASH)
2863                 falcon_spi_device_init(efx, &efx->spi_flash,
2864                                        FFE_AB_SPI_DEVICE_FLASH,
2865                                        default_flash_type);
2866         if (boot_dev == FFE_AB_SPI_DEVICE_EEPROM)
2867                 falcon_spi_device_init(efx, &efx->spi_eeprom,
2868                                        FFE_AB_SPI_DEVICE_EEPROM,
2869                                        large_eeprom_type);
2870 }
2871
2872 static int falcon_probe_nic(struct efx_nic *efx)
2873 {
2874         struct falcon_nic_data *nic_data;
2875         struct falcon_board *board;
2876         int rc;
2877
2878         /* Allocate storage for hardware specific data */
2879         nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL);
2880         if (!nic_data)
2881                 return -ENOMEM;
2882         efx->nic_data = nic_data;
2883
2884         /* Determine number of ports etc. */
2885         rc = falcon_probe_nic_variant(efx);
2886         if (rc)
2887                 goto fail1;
2888
2889         /* Probe secondary function if expected */
2890         if (FALCON_IS_DUAL_FUNC(efx)) {
2891                 struct pci_dev *dev = pci_dev_get(efx->pci_dev);
2892
2893                 while ((dev = pci_get_device(EFX_VENDID_SFC, FALCON_A_S_DEVID,
2894                                              dev))) {
2895                         if (dev->bus == efx->pci_dev->bus &&
2896                             dev->devfn == efx->pci_dev->devfn + 1) {
2897                                 nic_data->pci_dev2 = dev;
2898                                 break;
2899                         }
2900                 }
2901                 if (!nic_data->pci_dev2) {
2902                         EFX_ERR(efx, "failed to find secondary function\n");
2903                         rc = -ENODEV;
2904                         goto fail2;
2905                 }
2906         }
2907
2908         /* Now we can reset the NIC */
2909         rc = falcon_reset_hw(efx, RESET_TYPE_ALL);
2910         if (rc) {
2911                 EFX_ERR(efx, "failed to reset NIC\n");
2912                 goto fail3;
2913         }
2914
2915         /* Allocate memory for INT_KER */
2916         rc = falcon_alloc_buffer(efx, &efx->irq_status, sizeof(efx_oword_t));
2917         if (rc)
2918                 goto fail4;
2919         BUG_ON(efx->irq_status.dma_addr & 0x0f);
2920
2921         EFX_LOG(efx, "INT_KER at %llx (virt %p phys %llx)\n",
2922                 (u64)efx->irq_status.dma_addr,
2923                 efx->irq_status.addr, (u64)virt_to_phys(efx->irq_status.addr));
2924
2925         falcon_probe_spi_devices(efx);
2926
2927         /* Read in the non-volatile configuration */
2928         rc = falcon_probe_nvconfig(efx);
2929         if (rc)
2930                 goto fail5;
2931
2932         /* Initialise I2C adapter */
2933         board = falcon_board(efx);
2934         board->i2c_adap.owner = THIS_MODULE;
2935         board->i2c_data = falcon_i2c_bit_operations;
2936         board->i2c_data.data = efx;
2937         board->i2c_adap.algo_data = &board->i2c_data;
2938         board->i2c_adap.dev.parent = &efx->pci_dev->dev;
2939         strlcpy(board->i2c_adap.name, "SFC4000 GPIO",
2940                 sizeof(board->i2c_adap.name));
2941         rc = i2c_bit_add_bus(&board->i2c_adap);
2942         if (rc)
2943                 goto fail5;
2944
2945         rc = falcon_board(efx)->type->init(efx);
2946         if (rc) {
2947                 EFX_ERR(efx, "failed to initialise board\n");
2948                 goto fail6;
2949         }
2950
2951         nic_data->stats_disable_count = 1;
2952         setup_timer(&nic_data->stats_timer, &falcon_stats_timer_func,
2953                     (unsigned long)efx);
2954
2955         return 0;
2956
2957  fail6:
2958         BUG_ON(i2c_del_adapter(&board->i2c_adap));
2959         memset(&board->i2c_adap, 0, sizeof(board->i2c_adap));
2960  fail5:
2961         falcon_remove_spi_devices(efx);
2962         falcon_free_buffer(efx, &efx->irq_status);
2963  fail4:
2964  fail3:
2965         if (nic_data->pci_dev2) {
2966                 pci_dev_put(nic_data->pci_dev2);
2967                 nic_data->pci_dev2 = NULL;
2968         }
2969  fail2:
2970  fail1:
2971         kfree(efx->nic_data);
2972         return rc;
2973 }
2974
2975 static void falcon_init_rx_cfg(struct efx_nic *efx)
2976 {
2977         /* Prior to Siena the RX DMA engine will split each frame at
2978          * intervals of RX_USR_BUF_SIZE (32-byte units). We set it to
2979          * be so large that that never happens. */
2980         const unsigned huge_buf_size = (3 * 4096) >> 5;
2981         /* RX control FIFO thresholds (32 entries) */
2982         const unsigned ctrl_xon_thr = 20;
2983         const unsigned ctrl_xoff_thr = 25;
2984         /* RX data FIFO thresholds (256-byte units; size varies) */
2985         int data_xon_thr = rx_xon_thresh_bytes >> 8;
2986         int data_xoff_thr = rx_xoff_thresh_bytes >> 8;
2987         efx_oword_t reg;
2988
2989         efx_reado(efx, &reg, FR_AZ_RX_CFG);
2990         if (efx_nic_rev(efx) <= EFX_REV_FALCON_A1) {
2991                 /* Data FIFO size is 5.5K */
2992                 if (data_xon_thr < 0)
2993                         data_xon_thr = 512 >> 8;
2994                 if (data_xoff_thr < 0)
2995                         data_xoff_thr = 2048 >> 8;
2996                 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_DESC_PUSH_EN, 0);
2997                 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_USR_BUF_SIZE,
2998                                     huge_buf_size);
2999                 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XON_MAC_TH, data_xon_thr);
3000                 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XOFF_MAC_TH, data_xoff_thr);
3001                 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XON_TX_TH, ctrl_xon_thr);
3002                 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XOFF_TX_TH, ctrl_xoff_thr);
3003         } else {
3004                 /* Data FIFO size is 80K; register fields moved */
3005                 if (data_xon_thr < 0)
3006                         data_xon_thr = 27648 >> 8; /* ~3*max MTU */
3007                 if (data_xoff_thr < 0)
3008                         data_xoff_thr = 54272 >> 8; /* ~80Kb - 3*max MTU */
3009                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_DESC_PUSH_EN, 0);
3010                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_USR_BUF_SIZE,
3011                                     huge_buf_size);
3012                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XON_MAC_TH, data_xon_thr);
3013                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XOFF_MAC_TH, data_xoff_thr);
3014                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XON_TX_TH, ctrl_xon_thr);
3015                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XOFF_TX_TH, ctrl_xoff_thr);
3016                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 1);
3017         }
3018         /* Always enable XOFF signal from RX FIFO.  We enable
3019          * or disable transmission of pause frames at the MAC. */
3020         EFX_SET_OWORD_FIELD(reg, FRF_AZ_RX_XOFF_MAC_EN, 1);
3021         efx_writeo(efx, &reg, FR_AZ_RX_CFG);
3022 }
3023
3024 /* This call performs hardware-specific global initialisation, such as
3025  * defining the descriptor cache sizes and number of RSS channels.
3026  * It does not set up any buffers, descriptor rings or event queues.
3027  */
3028 static int falcon_init_nic(struct efx_nic *efx)
3029 {
3030         efx_oword_t temp;
3031         int rc;
3032
3033         /* Use on-chip SRAM */
3034         efx_reado(efx, &temp, FR_AB_NIC_STAT);
3035         EFX_SET_OWORD_FIELD(temp, FRF_AB_ONCHIP_SRAM, 1);
3036         efx_writeo(efx, &temp, FR_AB_NIC_STAT);
3037
3038         /* Set the source of the GMAC clock */
3039         if (efx_nic_rev(efx) == EFX_REV_FALCON_B0) {
3040                 efx_reado(efx, &temp, FR_AB_GPIO_CTL);
3041                 EFX_SET_OWORD_FIELD(temp, FRF_AB_USE_NIC_CLK, true);
3042                 efx_writeo(efx, &temp, FR_AB_GPIO_CTL);
3043         }
3044
3045         /* Select the correct MAC */
3046         falcon_clock_mac(efx);
3047
3048         rc = falcon_reset_sram(efx);
3049         if (rc)
3050                 return rc;
3051
3052         /* Set positions of descriptor caches in SRAM. */
3053         EFX_POPULATE_OWORD_1(temp, FRF_AZ_SRM_TX_DC_BASE_ADR,
3054                              efx->type->tx_dc_base / 8);
3055         efx_writeo(efx, &temp, FR_AZ_SRM_TX_DC_CFG);
3056         EFX_POPULATE_OWORD_1(temp, FRF_AZ_SRM_RX_DC_BASE_ADR,
3057                              efx->type->rx_dc_base / 8);
3058         efx_writeo(efx, &temp, FR_AZ_SRM_RX_DC_CFG);
3059
3060         /* Set TX descriptor cache size. */
3061         BUILD_BUG_ON(TX_DC_ENTRIES != (8 << TX_DC_ENTRIES_ORDER));
3062         EFX_POPULATE_OWORD_1(temp, FRF_AZ_TX_DC_SIZE, TX_DC_ENTRIES_ORDER);
3063         efx_writeo(efx, &temp, FR_AZ_TX_DC_CFG);
3064
3065         /* Set RX descriptor cache size.  Set low watermark to size-8, as
3066          * this allows most efficient prefetching.
3067          */
3068         BUILD_BUG_ON(RX_DC_ENTRIES != (8 << RX_DC_ENTRIES_ORDER));
3069         EFX_POPULATE_OWORD_1(temp, FRF_AZ_RX_DC_SIZE, RX_DC_ENTRIES_ORDER);
3070         efx_writeo(efx, &temp, FR_AZ_RX_DC_CFG);
3071         EFX_POPULATE_OWORD_1(temp, FRF_AZ_RX_DC_PF_LWM, RX_DC_ENTRIES - 8);
3072         efx_writeo(efx, &temp, FR_AZ_RX_DC_PF_WM);
3073
3074         /* Program INT_KER address */
3075         EFX_POPULATE_OWORD_2(temp,
3076                              FRF_AZ_NORM_INT_VEC_DIS_KER,
3077                              EFX_INT_MODE_USE_MSI(efx),
3078                              FRF_AZ_INT_ADR_KER, efx->irq_status.dma_addr);
3079         efx_writeo(efx, &temp, FR_AZ_INT_ADR_KER);
3080
3081         /* Clear the parity enables on the TX data fifos as
3082          * they produce false parity errors because of timing issues
3083          */
3084         if (EFX_WORKAROUND_5129(efx)) {
3085                 efx_reado(efx, &temp, FR_AZ_CSR_SPARE);
3086                 EFX_SET_OWORD_FIELD(temp, FRF_AB_MEM_PERR_EN_TX_DATA, 0);
3087                 efx_writeo(efx, &temp, FR_AZ_CSR_SPARE);
3088         }
3089
3090         /* Enable all the genuinely fatal interrupts.  (They are still
3091          * masked by the overall interrupt mask, controlled by
3092          * falcon_interrupts()).
3093          *
3094          * Note: All other fatal interrupts are enabled
3095          */
3096         EFX_POPULATE_OWORD_3(temp,
3097                              FRF_AZ_ILL_ADR_INT_KER_EN, 1,
3098                              FRF_AZ_RBUF_OWN_INT_KER_EN, 1,
3099                              FRF_AZ_TBUF_OWN_INT_KER_EN, 1);
3100         EFX_INVERT_OWORD(temp);
3101         efx_writeo(efx, &temp, FR_AZ_FATAL_INTR_KER);
3102
3103         if (EFX_WORKAROUND_7244(efx)) {
3104                 efx_reado(efx, &temp, FR_BZ_RX_FILTER_CTL);
3105                 EFX_SET_OWORD_FIELD(temp, FRF_BZ_UDP_FULL_SRCH_LIMIT, 8);
3106                 EFX_SET_OWORD_FIELD(temp, FRF_BZ_UDP_WILD_SRCH_LIMIT, 8);
3107                 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TCP_FULL_SRCH_LIMIT, 8);
3108                 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TCP_WILD_SRCH_LIMIT, 8);
3109                 efx_writeo(efx, &temp, FR_BZ_RX_FILTER_CTL);
3110         }
3111
3112         falcon_setup_rss_indir_table(efx);
3113
3114         /* XXX This is documented only for Falcon A0/A1 */
3115         /* Setup RX.  Wait for descriptor is broken and must
3116          * be disabled.  RXDP recovery shouldn't be needed, but is.
3117          */
3118         efx_reado(efx, &temp, FR_AA_RX_SELF_RST);
3119         EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_NODESC_WAIT_DIS, 1);
3120         EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_SELF_RST_EN, 1);
3121         if (EFX_WORKAROUND_5583(efx))
3122                 EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_ISCSI_DIS, 1);
3123         efx_writeo(efx, &temp, FR_AA_RX_SELF_RST);
3124
3125         /* Disable the ugly timer-based TX DMA backoff and allow TX DMA to be
3126          * controlled by the RX FIFO fill level. Set arbitration to one pkt/Q.
3127          */
3128         efx_reado(efx, &temp, FR_AZ_TX_RESERVED);
3129         EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_RX_SPACER, 0xfe);
3130         EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_RX_SPACER_EN, 1);
3131         EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_ONE_PKT_PER_Q, 1);
3132         EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_PUSH_EN, 0);
3133         EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_DIS_NON_IP_EV, 1);
3134         /* Enable SW_EV to inherit in char driver - assume harmless here */
3135         EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_SOFT_EVT_EN, 1);
3136         /* Prefetch threshold 2 => fetch when descriptor cache half empty */
3137         EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_PREF_THRESHOLD, 2);
3138         /* Squash TX of packets of 16 bytes or less */
3139         if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0)
3140                 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TX_FLUSH_MIN_LEN_EN, 1);
3141         efx_writeo(efx, &temp, FR_AZ_TX_RESERVED);
3142
3143         /* Do not enable TX_NO_EOP_DISC_EN, since it limits packets to 16
3144          * descriptors (which is bad).
3145          */
3146         efx_reado(efx, &temp, FR_AZ_TX_CFG);
3147         EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_NO_EOP_DISC_EN, 0);
3148         efx_writeo(efx, &temp, FR_AZ_TX_CFG);
3149
3150         falcon_init_rx_cfg(efx);
3151
3152         /* Set destination of both TX and RX Flush events */
3153         if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) {
3154                 EFX_POPULATE_OWORD_1(temp, FRF_BZ_FLS_EVQ_ID, 0);
3155                 efx_writeo(efx, &temp, FR_BZ_DP_CTRL);
3156         }
3157
3158         return 0;
3159 }
3160
3161 static void falcon_remove_nic(struct efx_nic *efx)
3162 {
3163         struct falcon_nic_data *nic_data = efx->nic_data;
3164         struct falcon_board *board = falcon_board(efx);
3165         int rc;
3166
3167         board->type->fini(efx);
3168
3169         /* Remove I2C adapter and clear it in preparation for a retry */
3170         rc = i2c_del_adapter(&board->i2c_adap);
3171         BUG_ON(rc);
3172         memset(&board->i2c_adap, 0, sizeof(board->i2c_adap));
3173
3174         falcon_remove_spi_devices(efx);
3175         falcon_free_buffer(efx, &efx->irq_status);
3176
3177         falcon_reset_hw(efx, RESET_TYPE_ALL);
3178
3179         /* Release the second function after the reset */
3180         if (nic_data->pci_dev2) {
3181                 pci_dev_put(nic_data->pci_dev2);
3182                 nic_data->pci_dev2 = NULL;
3183         }
3184
3185         /* Tear down the private nic state */
3186         kfree(efx->nic_data);
3187         efx->nic_data = NULL;
3188 }
3189
3190 static void falcon_update_nic_stats(struct efx_nic *efx)
3191 {
3192         struct falcon_nic_data *nic_data = efx->nic_data;
3193         efx_oword_t cnt;
3194
3195         if (nic_data->stats_disable_count)
3196                 return;
3197
3198         efx_reado(efx, &cnt, FR_AZ_RX_NODESC_DROP);
3199         efx->n_rx_nodesc_drop_cnt +=
3200                 EFX_OWORD_FIELD(cnt, FRF_AB_RX_NODESC_DROP_CNT);
3201
3202         if (nic_data->stats_pending &&
3203             *nic_data->stats_dma_done == FALCON_STATS_DONE) {
3204                 nic_data->stats_pending = false;
3205                 rmb(); /* read the done flag before the stats */
3206                 efx->mac_op->update_stats(efx);
3207         }
3208 }
3209
3210 void falcon_start_nic_stats(struct efx_nic *efx)
3211 {
3212         struct falcon_nic_data *nic_data = efx->nic_data;
3213
3214         spin_lock_bh(&efx->stats_lock);
3215         if (--nic_data->stats_disable_count == 0)
3216                 falcon_stats_request(efx);
3217         spin_unlock_bh(&efx->stats_lock);
3218 }
3219
3220 void falcon_stop_nic_stats(struct efx_nic *efx)
3221 {
3222         struct falcon_nic_data *nic_data = efx->nic_data;
3223         int i;
3224
3225         might_sleep();
3226
3227         spin_lock_bh(&efx->stats_lock);
3228         ++nic_data->stats_disable_count;
3229         spin_unlock_bh(&efx->stats_lock);
3230
3231         del_timer_sync(&nic_data->stats_timer);
3232
3233         /* Wait enough time for the most recent transfer to
3234          * complete. */
3235         for (i = 0; i < 4 && nic_data->stats_pending; i++) {
3236                 if (*nic_data->stats_dma_done == FALCON_STATS_DONE)
3237                         break;
3238                 msleep(1);
3239         }
3240
3241         spin_lock_bh(&efx->stats_lock);
3242         falcon_stats_complete(efx);
3243         spin_unlock_bh(&efx->stats_lock);
3244 }
3245
3246 /**************************************************************************
3247  *
3248  * Revision-dependent attributes used by efx.c
3249  *
3250  **************************************************************************
3251  */
3252
3253 struct efx_nic_type falcon_a1_nic_type = {
3254         .probe = falcon_probe_nic,
3255         .remove = falcon_remove_nic,
3256         .init = falcon_init_nic,
3257         .fini = efx_port_dummy_op_void,
3258         .monitor = falcon_monitor,
3259         .reset = falcon_reset_hw,
3260         .probe_port = falcon_probe_port,
3261         .remove_port = falcon_remove_port,
3262         .prepare_flush = falcon_prepare_flush,
3263         .update_stats = falcon_update_nic_stats,
3264         .start_stats = falcon_start_nic_stats,
3265         .stop_stats = falcon_stop_nic_stats,
3266         .push_irq_moderation = falcon_push_irq_moderation,
3267         .push_multicast_hash = falcon_push_multicast_hash,
3268         .reconfigure_port = falcon_reconfigure_port,
3269         .default_mac_ops = &falcon_xmac_operations,
3270
3271         .revision = EFX_REV_FALCON_A1,
3272         .mem_map_size = 0x20000,
3273         .txd_ptr_tbl_base = FR_AA_TX_DESC_PTR_TBL_KER,
3274         .rxd_ptr_tbl_base = FR_AA_RX_DESC_PTR_TBL_KER,
3275         .buf_tbl_base = FR_AA_BUF_FULL_TBL_KER,
3276         .evq_ptr_tbl_base = FR_AA_EVQ_PTR_TBL_KER,
3277         .evq_rptr_tbl_base = FR_AA_EVQ_RPTR_KER,
3278         .max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH),
3279         .rx_buffer_padding = 0x24,
3280         .max_interrupt_mode = EFX_INT_MODE_MSI,
3281         .phys_addr_channels = 4,
3282         .tx_dc_base = 0x130000,
3283         .rx_dc_base = 0x100000,
3284 };
3285
3286 struct efx_nic_type falcon_b0_nic_type = {
3287         .probe = falcon_probe_nic,
3288         .remove = falcon_remove_nic,
3289         .init = falcon_init_nic,
3290         .fini = efx_port_dummy_op_void,
3291         .monitor = falcon_monitor,
3292         .reset = falcon_reset_hw,
3293         .probe_port = falcon_probe_port,
3294         .remove_port = falcon_remove_port,
3295         .prepare_flush = falcon_prepare_flush,
3296         .update_stats = falcon_update_nic_stats,
3297         .start_stats = falcon_start_nic_stats,
3298         .stop_stats = falcon_stop_nic_stats,
3299         .push_irq_moderation = falcon_push_irq_moderation,
3300         .push_multicast_hash = falcon_push_multicast_hash,
3301         .reconfigure_port = falcon_reconfigure_port,
3302         .default_mac_ops = &falcon_xmac_operations,
3303
3304         .revision = EFX_REV_FALCON_B0,
3305         /* Map everything up to and including the RSS indirection
3306          * table.  Don't map MSI-X table, MSI-X PBA since Linux
3307          * requires that they not be mapped.  */
3308         .mem_map_size = (FR_BZ_RX_INDIRECTION_TBL +
3309                          FR_BZ_RX_INDIRECTION_TBL_STEP *
3310                          FR_BZ_RX_INDIRECTION_TBL_ROWS),
3311         .txd_ptr_tbl_base = FR_BZ_TX_DESC_PTR_TBL,
3312         .rxd_ptr_tbl_base = FR_BZ_RX_DESC_PTR_TBL,
3313         .buf_tbl_base = FR_BZ_BUF_FULL_TBL,
3314         .evq_ptr_tbl_base = FR_BZ_EVQ_PTR_TBL,
3315         .evq_rptr_tbl_base = FR_BZ_EVQ_RPTR,
3316         .max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH),
3317         .rx_buffer_padding = 0,
3318         .max_interrupt_mode = EFX_INT_MODE_MSIX,
3319         .phys_addr_channels = 32, /* Hardware limit is 64, but the legacy
3320                                    * interrupt handler only supports 32
3321                                    * channels */
3322         .tx_dc_base = 0x130000,
3323         .rx_dc_base = 0x100000,
3324 };
3325