1 /****************************************************************************
2 * Driver for Solarflare Solarstorm network controllers and boards
3 * Copyright 2005-2006 Fen Systems Ltd.
4 * Copyright 2006-2008 Solarflare Communications Inc.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
11 #include <linux/bitops.h>
12 #include <linux/delay.h>
13 #include <linux/pci.h>
14 #include <linux/module.h>
15 #include <linux/seq_file.h>
16 #include <linux/i2c.h>
17 #include <linux/i2c-algo-bit.h>
18 #include <linux/mii.h>
19 #include "net_driver.h"
29 #include "workarounds.h"
31 /* Falcon hardware control.
32 * Falcon is the internal codename for the SFC4000 controller that is
33 * present in SFE400X evaluation boards
37 * struct falcon_nic_data - Falcon NIC state
38 * @pci_dev2: The secondary PCI device if present
39 * @i2c_data: Operations and state for I2C bit-bashing algorithm
41 struct falcon_nic_data {
42 struct pci_dev *pci_dev2;
43 struct i2c_algo_bit_data i2c_data;
46 /**************************************************************************
50 **************************************************************************
53 static int disable_dma_stats;
55 /* This is set to 16 for a good reason. In summary, if larger than
56 * 16, the descriptor cache holds more than a default socket
57 * buffer's worth of packets (for UDP we can only have at most one
58 * socket buffer's worth outstanding). This combined with the fact
59 * that we only get 1 TX event per descriptor cache means the NIC
62 #define TX_DC_ENTRIES 16
63 #define TX_DC_ENTRIES_ORDER 0
64 #define TX_DC_BASE 0x130000
66 #define RX_DC_ENTRIES 64
67 #define RX_DC_ENTRIES_ORDER 2
68 #define RX_DC_BASE 0x100000
70 static const unsigned int
71 /* "Large" EEPROM device: Atmel AT25640 or similar
72 * 8 KB, 16-bit address, 32 B write block */
73 large_eeprom_type = ((13 << SPI_DEV_TYPE_SIZE_LBN)
74 | (2 << SPI_DEV_TYPE_ADDR_LEN_LBN)
75 | (5 << SPI_DEV_TYPE_BLOCK_SIZE_LBN)),
76 /* Default flash device: Atmel AT25F1024
77 * 128 KB, 24-bit address, 32 KB erase block, 256 B write block */
78 default_flash_type = ((17 << SPI_DEV_TYPE_SIZE_LBN)
79 | (3 << SPI_DEV_TYPE_ADDR_LEN_LBN)
80 | (0x52 << SPI_DEV_TYPE_ERASE_CMD_LBN)
81 | (15 << SPI_DEV_TYPE_ERASE_SIZE_LBN)
82 | (8 << SPI_DEV_TYPE_BLOCK_SIZE_LBN));
84 /* RX FIFO XOFF watermark
86 * When the amount of the RX FIFO increases used increases past this
87 * watermark send XOFF. Only used if RX flow control is enabled (ethtool -A)
88 * This also has an effect on RX/TX arbitration
90 static int rx_xoff_thresh_bytes = -1;
91 module_param(rx_xoff_thresh_bytes, int, 0644);
92 MODULE_PARM_DESC(rx_xoff_thresh_bytes, "RX fifo XOFF threshold");
94 /* RX FIFO XON watermark
96 * When the amount of the RX FIFO used decreases below this
97 * watermark send XON. Only used if TX flow control is enabled (ethtool -A)
98 * This also has an effect on RX/TX arbitration
100 static int rx_xon_thresh_bytes = -1;
101 module_param(rx_xon_thresh_bytes, int, 0644);
102 MODULE_PARM_DESC(rx_xon_thresh_bytes, "RX fifo XON threshold");
104 /* If FALCON_MAX_INT_ERRORS internal errors occur within
105 * FALCON_INT_ERROR_EXPIRE seconds, we consider the NIC broken and
108 #define FALCON_INT_ERROR_EXPIRE 3600
109 #define FALCON_MAX_INT_ERRORS 5
111 /* We poll for events every FLUSH_INTERVAL ms, and check FLUSH_POLL_COUNT times
113 #define FALCON_FLUSH_INTERVAL 10
114 #define FALCON_FLUSH_POLL_COUNT 100
116 /**************************************************************************
120 **************************************************************************
123 /* Size and alignment of special buffers (4KB) */
124 #define FALCON_BUF_SIZE 4096
126 /* Dummy SRAM size code */
127 #define SRM_NB_BSZ_ONCHIP_ONLY (-1)
129 #define FALCON_IS_DUAL_FUNC(efx) \
130 (falcon_rev(efx) < FALCON_REV_B0)
132 /**************************************************************************
134 * Falcon hardware access
136 **************************************************************************/
138 static inline void falcon_write_buf_tbl(struct efx_nic *efx, efx_qword_t *value,
141 efx_sram_writeq(efx, efx->membase + efx->type->buf_tbl_base,
145 /* Read the current event from the event queue */
146 static inline efx_qword_t *falcon_event(struct efx_channel *channel,
149 return (((efx_qword_t *) (channel->eventq.addr)) + index);
152 /* See if an event is present
154 * We check both the high and low dword of the event for all ones. We
155 * wrote all ones when we cleared the event, and no valid event can
156 * have all ones in either its high or low dwords. This approach is
157 * robust against reordering.
159 * Note that using a single 64-bit comparison is incorrect; even
160 * though the CPU read will be atomic, the DMA write may not be.
162 static inline int falcon_event_present(efx_qword_t *event)
164 return (!(EFX_DWORD_IS_ALL_ONES(event->dword[0]) |
165 EFX_DWORD_IS_ALL_ONES(event->dword[1])));
168 /**************************************************************************
170 * I2C bus - this is a bit-bashing interface using GPIO pins
171 * Note that it uses the output enables to tristate the outputs
172 * SDA is the data pin and SCL is the clock
174 **************************************************************************
176 static void falcon_setsda(void *data, int state)
178 struct efx_nic *efx = (struct efx_nic *)data;
181 efx_reado(efx, ®, FR_AB_GPIO_CTL);
182 EFX_SET_OWORD_FIELD(reg, FRF_AB_GPIO3_OEN, !state);
183 efx_writeo(efx, ®, FR_AB_GPIO_CTL);
186 static void falcon_setscl(void *data, int state)
188 struct efx_nic *efx = (struct efx_nic *)data;
191 efx_reado(efx, ®, FR_AB_GPIO_CTL);
192 EFX_SET_OWORD_FIELD(reg, FRF_AB_GPIO0_OEN, !state);
193 efx_writeo(efx, ®, FR_AB_GPIO_CTL);
196 static int falcon_getsda(void *data)
198 struct efx_nic *efx = (struct efx_nic *)data;
201 efx_reado(efx, ®, FR_AB_GPIO_CTL);
202 return EFX_OWORD_FIELD(reg, FRF_AB_GPIO3_IN);
205 static int falcon_getscl(void *data)
207 struct efx_nic *efx = (struct efx_nic *)data;
210 efx_reado(efx, ®, FR_AB_GPIO_CTL);
211 return EFX_OWORD_FIELD(reg, FRF_AB_GPIO0_IN);
214 static struct i2c_algo_bit_data falcon_i2c_bit_operations = {
215 .setsda = falcon_setsda,
216 .setscl = falcon_setscl,
217 .getsda = falcon_getsda,
218 .getscl = falcon_getscl,
220 /* Wait up to 50 ms for slave to let us pull SCL high */
221 .timeout = DIV_ROUND_UP(HZ, 20),
224 /**************************************************************************
226 * Falcon special buffer handling
227 * Special buffers are used for event queues and the TX and RX
230 *************************************************************************/
233 * Initialise a Falcon special buffer
235 * This will define a buffer (previously allocated via
236 * falcon_alloc_special_buffer()) in Falcon's buffer table, allowing
237 * it to be used for event queues, descriptor rings etc.
240 falcon_init_special_buffer(struct efx_nic *efx,
241 struct efx_special_buffer *buffer)
243 efx_qword_t buf_desc;
248 EFX_BUG_ON_PARANOID(!buffer->addr);
250 /* Write buffer descriptors to NIC */
251 for (i = 0; i < buffer->entries; i++) {
252 index = buffer->index + i;
253 dma_addr = buffer->dma_addr + (i * 4096);
254 EFX_LOG(efx, "mapping special buffer %d at %llx\n",
255 index, (unsigned long long)dma_addr);
256 EFX_POPULATE_QWORD_3(buf_desc,
257 FRF_AZ_BUF_ADR_REGION, 0,
258 FRF_AZ_BUF_ADR_FBUF, dma_addr >> 12,
259 FRF_AZ_BUF_OWNER_ID_FBUF, 0);
260 falcon_write_buf_tbl(efx, &buf_desc, index);
264 /* Unmaps a buffer from Falcon and clears the buffer table entries */
266 falcon_fini_special_buffer(struct efx_nic *efx,
267 struct efx_special_buffer *buffer)
269 efx_oword_t buf_tbl_upd;
270 unsigned int start = buffer->index;
271 unsigned int end = (buffer->index + buffer->entries - 1);
273 if (!buffer->entries)
276 EFX_LOG(efx, "unmapping special buffers %d-%d\n",
277 buffer->index, buffer->index + buffer->entries - 1);
279 EFX_POPULATE_OWORD_4(buf_tbl_upd,
280 FRF_AZ_BUF_UPD_CMD, 0,
281 FRF_AZ_BUF_CLR_CMD, 1,
282 FRF_AZ_BUF_CLR_END_ID, end,
283 FRF_AZ_BUF_CLR_START_ID, start);
284 efx_writeo(efx, &buf_tbl_upd, FR_AZ_BUF_TBL_UPD);
288 * Allocate a new Falcon special buffer
290 * This allocates memory for a new buffer, clears it and allocates a
291 * new buffer ID range. It does not write into Falcon's buffer table.
293 * This call will allocate 4KB buffers, since Falcon can't use 8KB
294 * buffers for event queues and descriptor rings.
296 static int falcon_alloc_special_buffer(struct efx_nic *efx,
297 struct efx_special_buffer *buffer,
300 len = ALIGN(len, FALCON_BUF_SIZE);
302 buffer->addr = pci_alloc_consistent(efx->pci_dev, len,
307 buffer->entries = len / FALCON_BUF_SIZE;
308 BUG_ON(buffer->dma_addr & (FALCON_BUF_SIZE - 1));
310 /* All zeros is a potentially valid event so memset to 0xff */
311 memset(buffer->addr, 0xff, len);
313 /* Select new buffer ID */
314 buffer->index = efx->next_buffer_table;
315 efx->next_buffer_table += buffer->entries;
317 EFX_LOG(efx, "allocating special buffers %d-%d at %llx+%x "
318 "(virt %p phys %llx)\n", buffer->index,
319 buffer->index + buffer->entries - 1,
320 (u64)buffer->dma_addr, len,
321 buffer->addr, (u64)virt_to_phys(buffer->addr));
326 static void falcon_free_special_buffer(struct efx_nic *efx,
327 struct efx_special_buffer *buffer)
332 EFX_LOG(efx, "deallocating special buffers %d-%d at %llx+%x "
333 "(virt %p phys %llx)\n", buffer->index,
334 buffer->index + buffer->entries - 1,
335 (u64)buffer->dma_addr, buffer->len,
336 buffer->addr, (u64)virt_to_phys(buffer->addr));
338 pci_free_consistent(efx->pci_dev, buffer->len, buffer->addr,
344 /**************************************************************************
346 * Falcon generic buffer handling
347 * These buffers are used for interrupt status and MAC stats
349 **************************************************************************/
351 static int falcon_alloc_buffer(struct efx_nic *efx,
352 struct efx_buffer *buffer, unsigned int len)
354 buffer->addr = pci_alloc_consistent(efx->pci_dev, len,
359 memset(buffer->addr, 0, len);
363 static void falcon_free_buffer(struct efx_nic *efx, struct efx_buffer *buffer)
366 pci_free_consistent(efx->pci_dev, buffer->len,
367 buffer->addr, buffer->dma_addr);
372 /**************************************************************************
376 **************************************************************************/
378 /* Returns a pointer to the specified transmit descriptor in the TX
379 * descriptor queue belonging to the specified channel.
381 static inline efx_qword_t *falcon_tx_desc(struct efx_tx_queue *tx_queue,
384 return (((efx_qword_t *) (tx_queue->txd.addr)) + index);
387 /* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */
388 static inline void falcon_notify_tx_desc(struct efx_tx_queue *tx_queue)
393 write_ptr = tx_queue->write_count & EFX_TXQ_MASK;
394 EFX_POPULATE_DWORD_1(reg, FRF_AZ_TX_DESC_WPTR_DWORD, write_ptr);
395 efx_writed_page(tx_queue->efx, ®,
396 FR_AZ_TX_DESC_UPD_DWORD_P0, tx_queue->queue);
400 /* For each entry inserted into the software descriptor ring, create a
401 * descriptor in the hardware TX descriptor ring (in host memory), and
404 void falcon_push_buffers(struct efx_tx_queue *tx_queue)
407 struct efx_tx_buffer *buffer;
411 BUG_ON(tx_queue->write_count == tx_queue->insert_count);
414 write_ptr = tx_queue->write_count & EFX_TXQ_MASK;
415 buffer = &tx_queue->buffer[write_ptr];
416 txd = falcon_tx_desc(tx_queue, write_ptr);
417 ++tx_queue->write_count;
419 /* Create TX descriptor ring entry */
420 EFX_POPULATE_QWORD_4(*txd,
421 FSF_AZ_TX_KER_CONT, buffer->continuation,
422 FSF_AZ_TX_KER_BYTE_COUNT, buffer->len,
423 FSF_AZ_TX_KER_BUF_REGION, 0,
424 FSF_AZ_TX_KER_BUF_ADDR, buffer->dma_addr);
425 } while (tx_queue->write_count != tx_queue->insert_count);
427 wmb(); /* Ensure descriptors are written before they are fetched */
428 falcon_notify_tx_desc(tx_queue);
431 /* Allocate hardware resources for a TX queue */
432 int falcon_probe_tx(struct efx_tx_queue *tx_queue)
434 struct efx_nic *efx = tx_queue->efx;
435 BUILD_BUG_ON(EFX_TXQ_SIZE < 512 || EFX_TXQ_SIZE > 4096 ||
436 EFX_TXQ_SIZE & EFX_TXQ_MASK);
437 return falcon_alloc_special_buffer(efx, &tx_queue->txd,
438 EFX_TXQ_SIZE * sizeof(efx_qword_t));
441 void falcon_init_tx(struct efx_tx_queue *tx_queue)
443 efx_oword_t tx_desc_ptr;
444 struct efx_nic *efx = tx_queue->efx;
446 tx_queue->flushed = false;
448 /* Pin TX descriptor ring */
449 falcon_init_special_buffer(efx, &tx_queue->txd);
451 /* Push TX descriptor ring to card */
452 EFX_POPULATE_OWORD_10(tx_desc_ptr,
453 FRF_AZ_TX_DESCQ_EN, 1,
454 FRF_AZ_TX_ISCSI_DDIG_EN, 0,
455 FRF_AZ_TX_ISCSI_HDIG_EN, 0,
456 FRF_AZ_TX_DESCQ_BUF_BASE_ID, tx_queue->txd.index,
457 FRF_AZ_TX_DESCQ_EVQ_ID,
458 tx_queue->channel->channel,
459 FRF_AZ_TX_DESCQ_OWNER_ID, 0,
460 FRF_AZ_TX_DESCQ_LABEL, tx_queue->queue,
461 FRF_AZ_TX_DESCQ_SIZE,
462 __ffs(tx_queue->txd.entries),
463 FRF_AZ_TX_DESCQ_TYPE, 0,
464 FRF_BZ_TX_NON_IP_DROP_DIS, 1);
466 if (falcon_rev(efx) >= FALCON_REV_B0) {
467 int csum = tx_queue->queue == EFX_TX_QUEUE_OFFLOAD_CSUM;
468 EFX_SET_OWORD_FIELD(tx_desc_ptr, FRF_BZ_TX_IP_CHKSM_DIS, !csum);
469 EFX_SET_OWORD_FIELD(tx_desc_ptr, FRF_BZ_TX_TCP_CHKSM_DIS,
473 efx_writeo_table(efx, &tx_desc_ptr, efx->type->txd_ptr_tbl_base,
476 if (falcon_rev(efx) < FALCON_REV_B0) {
479 /* Only 128 bits in this register */
480 BUILD_BUG_ON(EFX_TX_QUEUE_COUNT >= 128);
482 efx_reado(efx, ®, FR_AA_TX_CHKSM_CFG);
483 if (tx_queue->queue == EFX_TX_QUEUE_OFFLOAD_CSUM)
484 clear_bit_le(tx_queue->queue, (void *)®);
486 set_bit_le(tx_queue->queue, (void *)®);
487 efx_writeo(efx, ®, FR_AA_TX_CHKSM_CFG);
491 static void falcon_flush_tx_queue(struct efx_tx_queue *tx_queue)
493 struct efx_nic *efx = tx_queue->efx;
494 efx_oword_t tx_flush_descq;
496 /* Post a flush command */
497 EFX_POPULATE_OWORD_2(tx_flush_descq,
498 FRF_AZ_TX_FLUSH_DESCQ_CMD, 1,
499 FRF_AZ_TX_FLUSH_DESCQ, tx_queue->queue);
500 efx_writeo(efx, &tx_flush_descq, FR_AZ_TX_FLUSH_DESCQ);
503 void falcon_fini_tx(struct efx_tx_queue *tx_queue)
505 struct efx_nic *efx = tx_queue->efx;
506 efx_oword_t tx_desc_ptr;
508 /* The queue should have been flushed */
509 WARN_ON(!tx_queue->flushed);
511 /* Remove TX descriptor ring from card */
512 EFX_ZERO_OWORD(tx_desc_ptr);
513 efx_writeo_table(efx, &tx_desc_ptr, efx->type->txd_ptr_tbl_base,
516 /* Unpin TX descriptor ring */
517 falcon_fini_special_buffer(efx, &tx_queue->txd);
520 /* Free buffers backing TX queue */
521 void falcon_remove_tx(struct efx_tx_queue *tx_queue)
523 falcon_free_special_buffer(tx_queue->efx, &tx_queue->txd);
526 /**************************************************************************
530 **************************************************************************/
532 /* Returns a pointer to the specified descriptor in the RX descriptor queue */
533 static inline efx_qword_t *falcon_rx_desc(struct efx_rx_queue *rx_queue,
536 return (((efx_qword_t *) (rx_queue->rxd.addr)) + index);
539 /* This creates an entry in the RX descriptor queue */
540 static inline void falcon_build_rx_desc(struct efx_rx_queue *rx_queue,
543 struct efx_rx_buffer *rx_buf;
546 rxd = falcon_rx_desc(rx_queue, index);
547 rx_buf = efx_rx_buffer(rx_queue, index);
548 EFX_POPULATE_QWORD_3(*rxd,
549 FSF_AZ_RX_KER_BUF_SIZE,
551 rx_queue->efx->type->rx_buffer_padding,
552 FSF_AZ_RX_KER_BUF_REGION, 0,
553 FSF_AZ_RX_KER_BUF_ADDR, rx_buf->dma_addr);
556 /* This writes to the RX_DESC_WPTR register for the specified receive
559 void falcon_notify_rx_desc(struct efx_rx_queue *rx_queue)
564 while (rx_queue->notified_count != rx_queue->added_count) {
565 falcon_build_rx_desc(rx_queue,
566 rx_queue->notified_count &
568 ++rx_queue->notified_count;
572 write_ptr = rx_queue->added_count & EFX_RXQ_MASK;
573 EFX_POPULATE_DWORD_1(reg, FRF_AZ_RX_DESC_WPTR_DWORD, write_ptr);
574 efx_writed_page(rx_queue->efx, ®,
575 FR_AZ_RX_DESC_UPD_DWORD_P0, rx_queue->queue);
578 int falcon_probe_rx(struct efx_rx_queue *rx_queue)
580 struct efx_nic *efx = rx_queue->efx;
581 BUILD_BUG_ON(EFX_RXQ_SIZE < 512 || EFX_RXQ_SIZE > 4096 ||
582 EFX_RXQ_SIZE & EFX_RXQ_MASK);
583 return falcon_alloc_special_buffer(efx, &rx_queue->rxd,
584 EFX_RXQ_SIZE * sizeof(efx_qword_t));
587 void falcon_init_rx(struct efx_rx_queue *rx_queue)
589 efx_oword_t rx_desc_ptr;
590 struct efx_nic *efx = rx_queue->efx;
591 bool is_b0 = falcon_rev(efx) >= FALCON_REV_B0;
592 bool iscsi_digest_en = is_b0;
594 EFX_LOG(efx, "RX queue %d ring in special buffers %d-%d\n",
595 rx_queue->queue, rx_queue->rxd.index,
596 rx_queue->rxd.index + rx_queue->rxd.entries - 1);
598 rx_queue->flushed = false;
600 /* Pin RX descriptor ring */
601 falcon_init_special_buffer(efx, &rx_queue->rxd);
603 /* Push RX descriptor ring to card */
604 EFX_POPULATE_OWORD_10(rx_desc_ptr,
605 FRF_AZ_RX_ISCSI_DDIG_EN, iscsi_digest_en,
606 FRF_AZ_RX_ISCSI_HDIG_EN, iscsi_digest_en,
607 FRF_AZ_RX_DESCQ_BUF_BASE_ID, rx_queue->rxd.index,
608 FRF_AZ_RX_DESCQ_EVQ_ID,
609 rx_queue->channel->channel,
610 FRF_AZ_RX_DESCQ_OWNER_ID, 0,
611 FRF_AZ_RX_DESCQ_LABEL, rx_queue->queue,
612 FRF_AZ_RX_DESCQ_SIZE,
613 __ffs(rx_queue->rxd.entries),
614 FRF_AZ_RX_DESCQ_TYPE, 0 /* kernel queue */ ,
615 /* For >=B0 this is scatter so disable */
616 FRF_AZ_RX_DESCQ_JUMBO, !is_b0,
617 FRF_AZ_RX_DESCQ_EN, 1);
618 efx_writeo_table(efx, &rx_desc_ptr, efx->type->rxd_ptr_tbl_base,
622 static void falcon_flush_rx_queue(struct efx_rx_queue *rx_queue)
624 struct efx_nic *efx = rx_queue->efx;
625 efx_oword_t rx_flush_descq;
627 /* Post a flush command */
628 EFX_POPULATE_OWORD_2(rx_flush_descq,
629 FRF_AZ_RX_FLUSH_DESCQ_CMD, 1,
630 FRF_AZ_RX_FLUSH_DESCQ, rx_queue->queue);
631 efx_writeo(efx, &rx_flush_descq, FR_AZ_RX_FLUSH_DESCQ);
634 void falcon_fini_rx(struct efx_rx_queue *rx_queue)
636 efx_oword_t rx_desc_ptr;
637 struct efx_nic *efx = rx_queue->efx;
639 /* The queue should already have been flushed */
640 WARN_ON(!rx_queue->flushed);
642 /* Remove RX descriptor ring from card */
643 EFX_ZERO_OWORD(rx_desc_ptr);
644 efx_writeo_table(efx, &rx_desc_ptr, efx->type->rxd_ptr_tbl_base,
647 /* Unpin RX descriptor ring */
648 falcon_fini_special_buffer(efx, &rx_queue->rxd);
651 /* Free buffers backing RX queue */
652 void falcon_remove_rx(struct efx_rx_queue *rx_queue)
654 falcon_free_special_buffer(rx_queue->efx, &rx_queue->rxd);
657 /**************************************************************************
659 * Falcon event queue processing
660 * Event queues are processed by per-channel tasklets.
662 **************************************************************************/
664 /* Update a channel's event queue's read pointer (RPTR) register
666 * This writes the EVQ_RPTR_REG register for the specified channel's
669 * Note that EVQ_RPTR_REG contains the index of the "last read" event,
670 * whereas channel->eventq_read_ptr contains the index of the "next to
673 void falcon_eventq_read_ack(struct efx_channel *channel)
676 struct efx_nic *efx = channel->efx;
678 EFX_POPULATE_DWORD_1(reg, FRF_AZ_EVQ_RPTR, channel->eventq_read_ptr);
679 efx_writed_table(efx, ®, efx->type->evq_rptr_tbl_base,
683 /* Use HW to insert a SW defined event */
684 void falcon_generate_event(struct efx_channel *channel, efx_qword_t *event)
686 efx_oword_t drv_ev_reg;
688 BUILD_BUG_ON(FRF_AZ_DRV_EV_DATA_LBN != 0 ||
689 FRF_AZ_DRV_EV_DATA_WIDTH != 64);
690 drv_ev_reg.u32[0] = event->u32[0];
691 drv_ev_reg.u32[1] = event->u32[1];
692 drv_ev_reg.u32[2] = 0;
693 drv_ev_reg.u32[3] = 0;
694 EFX_SET_OWORD_FIELD(drv_ev_reg, FRF_AZ_DRV_EV_QID, channel->channel);
695 efx_writeo(channel->efx, &drv_ev_reg, FR_AZ_DRV_EV);
698 /* Handle a transmit completion event
700 * Falcon batches TX completion events; the message we receive is of
701 * the form "complete all TX events up to this index".
703 static void falcon_handle_tx_event(struct efx_channel *channel,
706 unsigned int tx_ev_desc_ptr;
707 unsigned int tx_ev_q_label;
708 struct efx_tx_queue *tx_queue;
709 struct efx_nic *efx = channel->efx;
711 if (likely(EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_COMP))) {
712 /* Transmit completion */
713 tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_DESC_PTR);
714 tx_ev_q_label = EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_Q_LABEL);
715 tx_queue = &efx->tx_queue[tx_ev_q_label];
716 channel->irq_mod_score +=
717 (tx_ev_desc_ptr - tx_queue->read_count) &
719 efx_xmit_done(tx_queue, tx_ev_desc_ptr);
720 } else if (EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_WQ_FF_FULL)) {
721 /* Rewrite the FIFO write pointer */
722 tx_ev_q_label = EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_Q_LABEL);
723 tx_queue = &efx->tx_queue[tx_ev_q_label];
725 if (efx_dev_registered(efx))
726 netif_tx_lock(efx->net_dev);
727 falcon_notify_tx_desc(tx_queue);
728 if (efx_dev_registered(efx))
729 netif_tx_unlock(efx->net_dev);
730 } else if (EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_PKT_ERR) &&
731 EFX_WORKAROUND_10727(efx)) {
732 efx_schedule_reset(efx, RESET_TYPE_TX_DESC_FETCH);
734 EFX_ERR(efx, "channel %d unexpected TX event "
735 EFX_QWORD_FMT"\n", channel->channel,
736 EFX_QWORD_VAL(*event));
740 /* Detect errors included in the rx_evt_pkt_ok bit. */
741 static void falcon_handle_rx_not_ok(struct efx_rx_queue *rx_queue,
742 const efx_qword_t *event,
746 struct efx_nic *efx = rx_queue->efx;
747 bool rx_ev_buf_owner_id_err, rx_ev_ip_hdr_chksum_err;
748 bool rx_ev_tcp_udp_chksum_err, rx_ev_eth_crc_err;
749 bool rx_ev_frm_trunc, rx_ev_drib_nib, rx_ev_tobe_disc;
750 bool rx_ev_other_err, rx_ev_pause_frm;
751 bool rx_ev_ip_frag_err, rx_ev_hdr_type, rx_ev_mcast_pkt;
752 unsigned rx_ev_pkt_type;
754 rx_ev_hdr_type = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_HDR_TYPE);
755 rx_ev_mcast_pkt = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_MCAST_PKT);
756 rx_ev_tobe_disc = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_TOBE_DISC);
757 rx_ev_pkt_type = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_PKT_TYPE);
758 rx_ev_buf_owner_id_err = EFX_QWORD_FIELD(*event,
759 FSF_AZ_RX_EV_BUF_OWNER_ID_ERR);
760 rx_ev_ip_frag_err = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_IP_FRAG_ERR);
761 rx_ev_ip_hdr_chksum_err = EFX_QWORD_FIELD(*event,
762 FSF_AZ_RX_EV_IP_HDR_CHKSUM_ERR);
763 rx_ev_tcp_udp_chksum_err = EFX_QWORD_FIELD(*event,
764 FSF_AZ_RX_EV_TCP_UDP_CHKSUM_ERR);
765 rx_ev_eth_crc_err = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_ETH_CRC_ERR);
766 rx_ev_frm_trunc = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_FRM_TRUNC);
767 rx_ev_drib_nib = ((falcon_rev(efx) >= FALCON_REV_B0) ?
768 0 : EFX_QWORD_FIELD(*event, FSF_AA_RX_EV_DRIB_NIB));
769 rx_ev_pause_frm = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_PAUSE_FRM_ERR);
771 /* Every error apart from tobe_disc and pause_frm */
772 rx_ev_other_err = (rx_ev_drib_nib | rx_ev_tcp_udp_chksum_err |
773 rx_ev_buf_owner_id_err | rx_ev_eth_crc_err |
774 rx_ev_frm_trunc | rx_ev_ip_hdr_chksum_err);
776 /* Count errors that are not in MAC stats. Ignore expected
777 * checksum errors during self-test. */
779 ++rx_queue->channel->n_rx_frm_trunc;
780 else if (rx_ev_tobe_disc)
781 ++rx_queue->channel->n_rx_tobe_disc;
782 else if (!efx->loopback_selftest) {
783 if (rx_ev_ip_hdr_chksum_err)
784 ++rx_queue->channel->n_rx_ip_hdr_chksum_err;
785 else if (rx_ev_tcp_udp_chksum_err)
786 ++rx_queue->channel->n_rx_tcp_udp_chksum_err;
788 if (rx_ev_ip_frag_err)
789 ++rx_queue->channel->n_rx_ip_frag_err;
791 /* The frame must be discarded if any of these are true. */
792 *discard = (rx_ev_eth_crc_err | rx_ev_frm_trunc | rx_ev_drib_nib |
793 rx_ev_tobe_disc | rx_ev_pause_frm);
795 /* TOBE_DISC is expected on unicast mismatches; don't print out an
796 * error message. FRM_TRUNC indicates RXDP dropped the packet due
797 * to a FIFO overflow.
799 #ifdef EFX_ENABLE_DEBUG
800 if (rx_ev_other_err) {
801 EFX_INFO_RL(efx, " RX queue %d unexpected RX event "
802 EFX_QWORD_FMT "%s%s%s%s%s%s%s%s\n",
803 rx_queue->queue, EFX_QWORD_VAL(*event),
804 rx_ev_buf_owner_id_err ? " [OWNER_ID_ERR]" : "",
805 rx_ev_ip_hdr_chksum_err ?
806 " [IP_HDR_CHKSUM_ERR]" : "",
807 rx_ev_tcp_udp_chksum_err ?
808 " [TCP_UDP_CHKSUM_ERR]" : "",
809 rx_ev_eth_crc_err ? " [ETH_CRC_ERR]" : "",
810 rx_ev_frm_trunc ? " [FRM_TRUNC]" : "",
811 rx_ev_drib_nib ? " [DRIB_NIB]" : "",
812 rx_ev_tobe_disc ? " [TOBE_DISC]" : "",
813 rx_ev_pause_frm ? " [PAUSE]" : "");
818 /* Handle receive events that are not in-order. */
819 static void falcon_handle_rx_bad_index(struct efx_rx_queue *rx_queue,
822 struct efx_nic *efx = rx_queue->efx;
823 unsigned expected, dropped;
825 expected = rx_queue->removed_count & EFX_RXQ_MASK;
826 dropped = (index - expected) & EFX_RXQ_MASK;
827 EFX_INFO(efx, "dropped %d events (index=%d expected=%d)\n",
828 dropped, index, expected);
830 efx_schedule_reset(efx, EFX_WORKAROUND_5676(efx) ?
831 RESET_TYPE_RX_RECOVERY : RESET_TYPE_DISABLE);
834 /* Handle a packet received event
836 * Falcon silicon gives a "discard" flag if it's a unicast packet with the
837 * wrong destination address
838 * Also "is multicast" and "matches multicast filter" flags can be used to
839 * discard non-matching multicast packets.
841 static void falcon_handle_rx_event(struct efx_channel *channel,
842 const efx_qword_t *event)
844 unsigned int rx_ev_desc_ptr, rx_ev_byte_cnt;
845 unsigned int rx_ev_hdr_type, rx_ev_mcast_pkt;
846 unsigned expected_ptr;
847 bool rx_ev_pkt_ok, discard = false, checksummed;
848 struct efx_rx_queue *rx_queue;
849 struct efx_nic *efx = channel->efx;
851 /* Basic packet information */
852 rx_ev_byte_cnt = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_BYTE_CNT);
853 rx_ev_pkt_ok = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_PKT_OK);
854 rx_ev_hdr_type = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_HDR_TYPE);
855 WARN_ON(EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_JUMBO_CONT));
856 WARN_ON(EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_SOP) != 1);
857 WARN_ON(EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_Q_LABEL) !=
860 rx_queue = &efx->rx_queue[channel->channel];
862 rx_ev_desc_ptr = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_DESC_PTR);
863 expected_ptr = rx_queue->removed_count & EFX_RXQ_MASK;
864 if (unlikely(rx_ev_desc_ptr != expected_ptr))
865 falcon_handle_rx_bad_index(rx_queue, rx_ev_desc_ptr);
867 if (likely(rx_ev_pkt_ok)) {
868 /* If packet is marked as OK and packet type is TCP/IPv4 or
869 * UDP/IPv4, then we can rely on the hardware checksum.
872 efx->rx_checksum_enabled &&
873 (rx_ev_hdr_type == FSE_AB_RX_EV_HDR_TYPE_IPV4_TCP ||
874 rx_ev_hdr_type == FSE_AB_RX_EV_HDR_TYPE_IPV4_UDP);
876 falcon_handle_rx_not_ok(rx_queue, event, &rx_ev_pkt_ok,
881 /* Detect multicast packets that didn't match the filter */
882 rx_ev_mcast_pkt = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_MCAST_PKT);
883 if (rx_ev_mcast_pkt) {
884 unsigned int rx_ev_mcast_hash_match =
885 EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_MCAST_HASH_MATCH);
887 if (unlikely(!rx_ev_mcast_hash_match))
891 channel->irq_mod_score += 2;
893 /* Handle received packet */
894 efx_rx_packet(rx_queue, rx_ev_desc_ptr, rx_ev_byte_cnt,
895 checksummed, discard);
898 /* Global events are basically PHY events */
899 static void falcon_handle_global_event(struct efx_channel *channel,
902 struct efx_nic *efx = channel->efx;
903 bool handled = false;
905 if (EFX_QWORD_FIELD(*event, FSF_AB_GLB_EV_G_PHY0_INTR) ||
906 EFX_QWORD_FIELD(*event, FSF_AB_GLB_EV_XG_PHY0_INTR) ||
907 EFX_QWORD_FIELD(*event, FSF_AB_GLB_EV_XFP_PHY0_INTR)) {
908 efx->phy_op->clear_interrupt(efx);
909 queue_work(efx->workqueue, &efx->phy_work);
913 if ((falcon_rev(efx) >= FALCON_REV_B0) &&
914 EFX_QWORD_FIELD(*event, FSF_BB_GLB_EV_XG_MGT_INTR)) {
915 queue_work(efx->workqueue, &efx->mac_work);
919 if (falcon_rev(efx) <= FALCON_REV_A1 ?
920 EFX_QWORD_FIELD(*event, FSF_AA_GLB_EV_RX_RECOVERY) :
921 EFX_QWORD_FIELD(*event, FSF_BB_GLB_EV_RX_RECOVERY)) {
922 EFX_ERR(efx, "channel %d seen global RX_RESET "
923 "event. Resetting.\n", channel->channel);
925 atomic_inc(&efx->rx_reset);
926 efx_schedule_reset(efx, EFX_WORKAROUND_6555(efx) ?
927 RESET_TYPE_RX_RECOVERY : RESET_TYPE_DISABLE);
932 EFX_ERR(efx, "channel %d unknown global event "
933 EFX_QWORD_FMT "\n", channel->channel,
934 EFX_QWORD_VAL(*event));
937 static void falcon_handle_driver_event(struct efx_channel *channel,
940 struct efx_nic *efx = channel->efx;
941 unsigned int ev_sub_code;
942 unsigned int ev_sub_data;
944 ev_sub_code = EFX_QWORD_FIELD(*event, FSF_AZ_DRIVER_EV_SUBCODE);
945 ev_sub_data = EFX_QWORD_FIELD(*event, FSF_AZ_DRIVER_EV_SUBDATA);
947 switch (ev_sub_code) {
948 case FSE_AZ_TX_DESCQ_FLS_DONE_EV:
949 EFX_TRACE(efx, "channel %d TXQ %d flushed\n",
950 channel->channel, ev_sub_data);
952 case FSE_AZ_RX_DESCQ_FLS_DONE_EV:
953 EFX_TRACE(efx, "channel %d RXQ %d flushed\n",
954 channel->channel, ev_sub_data);
956 case FSE_AZ_EVQ_INIT_DONE_EV:
957 EFX_LOG(efx, "channel %d EVQ %d initialised\n",
958 channel->channel, ev_sub_data);
960 case FSE_AZ_SRM_UPD_DONE_EV:
961 EFX_TRACE(efx, "channel %d SRAM update done\n",
964 case FSE_AZ_WAKE_UP_EV:
965 EFX_TRACE(efx, "channel %d RXQ %d wakeup event\n",
966 channel->channel, ev_sub_data);
968 case FSE_AZ_TIMER_EV:
969 EFX_TRACE(efx, "channel %d RX queue %d timer expired\n",
970 channel->channel, ev_sub_data);
972 case FSE_AA_RX_RECOVER_EV:
973 EFX_ERR(efx, "channel %d seen DRIVER RX_RESET event. "
974 "Resetting.\n", channel->channel);
975 atomic_inc(&efx->rx_reset);
976 efx_schedule_reset(efx,
977 EFX_WORKAROUND_6555(efx) ?
978 RESET_TYPE_RX_RECOVERY :
981 case FSE_BZ_RX_DSC_ERROR_EV:
982 EFX_ERR(efx, "RX DMA Q %d reports descriptor fetch error."
983 " RX Q %d is disabled.\n", ev_sub_data, ev_sub_data);
984 efx_schedule_reset(efx, RESET_TYPE_RX_DESC_FETCH);
986 case FSE_BZ_TX_DSC_ERROR_EV:
987 EFX_ERR(efx, "TX DMA Q %d reports descriptor fetch error."
988 " TX Q %d is disabled.\n", ev_sub_data, ev_sub_data);
989 efx_schedule_reset(efx, RESET_TYPE_TX_DESC_FETCH);
992 EFX_TRACE(efx, "channel %d unknown driver event code %d "
993 "data %04x\n", channel->channel, ev_sub_code,
999 int falcon_process_eventq(struct efx_channel *channel, int rx_quota)
1001 unsigned int read_ptr;
1002 efx_qword_t event, *p_event;
1006 read_ptr = channel->eventq_read_ptr;
1009 p_event = falcon_event(channel, read_ptr);
1012 if (!falcon_event_present(&event))
1016 EFX_TRACE(channel->efx, "channel %d event is "EFX_QWORD_FMT"\n",
1017 channel->channel, EFX_QWORD_VAL(event));
1019 /* Clear this event by marking it all ones */
1020 EFX_SET_QWORD(*p_event);
1022 ev_code = EFX_QWORD_FIELD(event, FSF_AZ_EV_CODE);
1025 case FSE_AZ_EV_CODE_RX_EV:
1026 falcon_handle_rx_event(channel, &event);
1029 case FSE_AZ_EV_CODE_TX_EV:
1030 falcon_handle_tx_event(channel, &event);
1032 case FSE_AZ_EV_CODE_DRV_GEN_EV:
1033 channel->eventq_magic = EFX_QWORD_FIELD(
1034 event, FSF_AZ_DRV_GEN_EV_MAGIC);
1035 EFX_LOG(channel->efx, "channel %d received generated "
1036 "event "EFX_QWORD_FMT"\n", channel->channel,
1037 EFX_QWORD_VAL(event));
1039 case FSE_AZ_EV_CODE_GLOBAL_EV:
1040 falcon_handle_global_event(channel, &event);
1042 case FSE_AZ_EV_CODE_DRIVER_EV:
1043 falcon_handle_driver_event(channel, &event);
1046 EFX_ERR(channel->efx, "channel %d unknown event type %d"
1047 " (data " EFX_QWORD_FMT ")\n", channel->channel,
1048 ev_code, EFX_QWORD_VAL(event));
1051 /* Increment read pointer */
1052 read_ptr = (read_ptr + 1) & EFX_EVQ_MASK;
1054 } while (rx_packets < rx_quota);
1056 channel->eventq_read_ptr = read_ptr;
1060 void falcon_set_int_moderation(struct efx_channel *channel)
1062 efx_dword_t timer_cmd;
1063 struct efx_nic *efx = channel->efx;
1065 /* Set timer register */
1066 if (channel->irq_moderation) {
1067 EFX_POPULATE_DWORD_2(timer_cmd,
1068 FRF_AB_TC_TIMER_MODE,
1069 FFE_BB_TIMER_MODE_INT_HLDOFF,
1070 FRF_AB_TC_TIMER_VAL,
1071 channel->irq_moderation - 1);
1073 EFX_POPULATE_DWORD_2(timer_cmd,
1074 FRF_AB_TC_TIMER_MODE,
1075 FFE_BB_TIMER_MODE_DIS,
1076 FRF_AB_TC_TIMER_VAL, 0);
1078 BUILD_BUG_ON(FR_AA_TIMER_COMMAND_KER != FR_BZ_TIMER_COMMAND_P0);
1079 efx_writed_page_locked(efx, &timer_cmd, FR_BZ_TIMER_COMMAND_P0,
1084 /* Allocate buffer table entries for event queue */
1085 int falcon_probe_eventq(struct efx_channel *channel)
1087 struct efx_nic *efx = channel->efx;
1088 BUILD_BUG_ON(EFX_EVQ_SIZE < 512 || EFX_EVQ_SIZE > 32768 ||
1089 EFX_EVQ_SIZE & EFX_EVQ_MASK);
1090 return falcon_alloc_special_buffer(efx, &channel->eventq,
1091 EFX_EVQ_SIZE * sizeof(efx_qword_t));
1094 void falcon_init_eventq(struct efx_channel *channel)
1096 efx_oword_t evq_ptr;
1097 struct efx_nic *efx = channel->efx;
1099 EFX_LOG(efx, "channel %d event queue in special buffers %d-%d\n",
1100 channel->channel, channel->eventq.index,
1101 channel->eventq.index + channel->eventq.entries - 1);
1103 /* Pin event queue buffer */
1104 falcon_init_special_buffer(efx, &channel->eventq);
1106 /* Fill event queue with all ones (i.e. empty events) */
1107 memset(channel->eventq.addr, 0xff, channel->eventq.len);
1109 /* Push event queue to card */
1110 EFX_POPULATE_OWORD_3(evq_ptr,
1112 FRF_AZ_EVQ_SIZE, __ffs(channel->eventq.entries),
1113 FRF_AZ_EVQ_BUF_BASE_ID, channel->eventq.index);
1114 efx_writeo_table(efx, &evq_ptr, efx->type->evq_ptr_tbl_base,
1117 falcon_set_int_moderation(channel);
1120 void falcon_fini_eventq(struct efx_channel *channel)
1122 efx_oword_t eventq_ptr;
1123 struct efx_nic *efx = channel->efx;
1125 /* Remove event queue from card */
1126 EFX_ZERO_OWORD(eventq_ptr);
1127 efx_writeo_table(efx, &eventq_ptr, efx->type->evq_ptr_tbl_base,
1130 /* Unpin event queue */
1131 falcon_fini_special_buffer(efx, &channel->eventq);
1134 /* Free buffers backing event queue */
1135 void falcon_remove_eventq(struct efx_channel *channel)
1137 falcon_free_special_buffer(channel->efx, &channel->eventq);
1141 /* Generates a test event on the event queue. A subsequent call to
1142 * process_eventq() should pick up the event and place the value of
1143 * "magic" into channel->eventq_magic;
1145 void falcon_generate_test_event(struct efx_channel *channel, unsigned int magic)
1147 efx_qword_t test_event;
1149 EFX_POPULATE_QWORD_2(test_event, FSF_AZ_EV_CODE,
1150 FSE_AZ_EV_CODE_DRV_GEN_EV,
1151 FSF_AZ_DRV_GEN_EV_MAGIC, magic);
1152 falcon_generate_event(channel, &test_event);
1155 void falcon_sim_phy_event(struct efx_nic *efx)
1157 efx_qword_t phy_event;
1159 EFX_POPULATE_QWORD_1(phy_event, FSF_AZ_EV_CODE,
1160 FSE_AZ_EV_CODE_GLOBAL_EV);
1162 EFX_SET_QWORD_FIELD(phy_event, FSF_AB_GLB_EV_XG_PHY0_INTR, 1);
1164 EFX_SET_QWORD_FIELD(phy_event, FSF_AB_GLB_EV_G_PHY0_INTR, 1);
1166 falcon_generate_event(&efx->channel[0], &phy_event);
1169 /**************************************************************************
1173 **************************************************************************/
1176 static void falcon_poll_flush_events(struct efx_nic *efx)
1178 struct efx_channel *channel = &efx->channel[0];
1179 struct efx_tx_queue *tx_queue;
1180 struct efx_rx_queue *rx_queue;
1181 unsigned int read_ptr = channel->eventq_read_ptr;
1182 unsigned int end_ptr = (read_ptr - 1) & EFX_EVQ_MASK;
1185 efx_qword_t *event = falcon_event(channel, read_ptr);
1186 int ev_code, ev_sub_code, ev_queue;
1189 if (!falcon_event_present(event))
1192 ev_code = EFX_QWORD_FIELD(*event, FSF_AZ_EV_CODE);
1193 ev_sub_code = EFX_QWORD_FIELD(*event,
1194 FSF_AZ_DRIVER_EV_SUBCODE);
1195 if (ev_code == FSE_AZ_EV_CODE_DRIVER_EV &&
1196 ev_sub_code == FSE_AZ_TX_DESCQ_FLS_DONE_EV) {
1197 ev_queue = EFX_QWORD_FIELD(*event,
1198 FSF_AZ_DRIVER_EV_SUBDATA);
1199 if (ev_queue < EFX_TX_QUEUE_COUNT) {
1200 tx_queue = efx->tx_queue + ev_queue;
1201 tx_queue->flushed = true;
1203 } else if (ev_code == FSE_AZ_EV_CODE_DRIVER_EV &&
1204 ev_sub_code == FSE_AZ_RX_DESCQ_FLS_DONE_EV) {
1205 ev_queue = EFX_QWORD_FIELD(
1206 *event, FSF_AZ_DRIVER_EV_RX_DESCQ_ID);
1207 ev_failed = EFX_QWORD_FIELD(
1208 *event, FSF_AZ_DRIVER_EV_RX_FLUSH_FAIL);
1209 if (ev_queue < efx->n_rx_queues) {
1210 rx_queue = efx->rx_queue + ev_queue;
1212 /* retry the rx flush */
1214 falcon_flush_rx_queue(rx_queue);
1216 rx_queue->flushed = true;
1220 read_ptr = (read_ptr + 1) & EFX_EVQ_MASK;
1221 } while (read_ptr != end_ptr);
1224 /* Handle tx and rx flushes at the same time, since they run in
1225 * parallel in the hardware and there's no reason for us to
1227 int falcon_flush_queues(struct efx_nic *efx)
1229 struct efx_rx_queue *rx_queue;
1230 struct efx_tx_queue *tx_queue;
1234 /* Issue flush requests */
1235 efx_for_each_tx_queue(tx_queue, efx) {
1236 tx_queue->flushed = false;
1237 falcon_flush_tx_queue(tx_queue);
1239 efx_for_each_rx_queue(rx_queue, efx) {
1240 rx_queue->flushed = false;
1241 falcon_flush_rx_queue(rx_queue);
1244 /* Poll the evq looking for flush completions. Since we're not pushing
1245 * any more rx or tx descriptors at this point, we're in no danger of
1246 * overflowing the evq whilst we wait */
1247 for (i = 0; i < FALCON_FLUSH_POLL_COUNT; ++i) {
1248 msleep(FALCON_FLUSH_INTERVAL);
1249 falcon_poll_flush_events(efx);
1251 /* Check if every queue has been succesfully flushed */
1252 outstanding = false;
1253 efx_for_each_tx_queue(tx_queue, efx)
1254 outstanding |= !tx_queue->flushed;
1255 efx_for_each_rx_queue(rx_queue, efx)
1256 outstanding |= !rx_queue->flushed;
1261 /* Mark the queues as all flushed. We're going to return failure
1262 * leading to a reset, or fake up success anyway. "flushed" now
1263 * indicates that we tried to flush. */
1264 efx_for_each_tx_queue(tx_queue, efx) {
1265 if (!tx_queue->flushed)
1266 EFX_ERR(efx, "tx queue %d flush command timed out\n",
1268 tx_queue->flushed = true;
1270 efx_for_each_rx_queue(rx_queue, efx) {
1271 if (!rx_queue->flushed)
1272 EFX_ERR(efx, "rx queue %d flush command timed out\n",
1274 rx_queue->flushed = true;
1277 if (EFX_WORKAROUND_7803(efx))
1283 /**************************************************************************
1285 * Falcon hardware interrupts
1286 * The hardware interrupt handler does very little work; all the event
1287 * queue processing is carried out by per-channel tasklets.
1289 **************************************************************************/
1291 /* Enable/disable/generate Falcon interrupts */
1292 static inline void falcon_interrupts(struct efx_nic *efx, int enabled,
1295 efx_oword_t int_en_reg_ker;
1297 EFX_POPULATE_OWORD_2(int_en_reg_ker,
1298 FRF_AZ_KER_INT_KER, force,
1299 FRF_AZ_DRV_INT_EN_KER, enabled);
1300 efx_writeo(efx, &int_en_reg_ker, FR_AZ_INT_EN_KER);
1303 void falcon_enable_interrupts(struct efx_nic *efx)
1305 efx_oword_t int_adr_reg_ker;
1306 struct efx_channel *channel;
1308 EFX_ZERO_OWORD(*((efx_oword_t *) efx->irq_status.addr));
1309 wmb(); /* Ensure interrupt vector is clear before interrupts enabled */
1311 /* Program address */
1312 EFX_POPULATE_OWORD_2(int_adr_reg_ker,
1313 FRF_AZ_NORM_INT_VEC_DIS_KER,
1314 EFX_INT_MODE_USE_MSI(efx),
1315 FRF_AZ_INT_ADR_KER, efx->irq_status.dma_addr);
1316 efx_writeo(efx, &int_adr_reg_ker, FR_AZ_INT_ADR_KER);
1318 /* Enable interrupts */
1319 falcon_interrupts(efx, 1, 0);
1321 /* Force processing of all the channels to get the EVQ RPTRs up to
1323 efx_for_each_channel(channel, efx)
1324 efx_schedule_channel(channel);
1327 void falcon_disable_interrupts(struct efx_nic *efx)
1329 /* Disable interrupts */
1330 falcon_interrupts(efx, 0, 0);
1333 /* Generate a Falcon test interrupt
1334 * Interrupt must already have been enabled, otherwise nasty things
1337 void falcon_generate_interrupt(struct efx_nic *efx)
1339 falcon_interrupts(efx, 1, 1);
1342 /* Acknowledge a legacy interrupt from Falcon
1344 * This acknowledges a legacy (not MSI) interrupt via INT_ACK_KER_REG.
1346 * Due to SFC bug 3706 (silicon revision <=A1) reads can be duplicated in the
1347 * BIU. Interrupt acknowledge is read sensitive so must write instead
1348 * (then read to ensure the BIU collector is flushed)
1350 * NB most hardware supports MSI interrupts
1352 static inline void falcon_irq_ack_a1(struct efx_nic *efx)
1356 EFX_POPULATE_DWORD_1(reg, FRF_AA_INT_ACK_KER_FIELD, 0xb7eb7e);
1357 efx_writed(efx, ®, FR_AA_INT_ACK_KER);
1358 efx_readd(efx, ®, FR_AA_WORK_AROUND_BROKEN_PCI_READS);
1361 /* Process a fatal interrupt
1362 * Disable bus mastering ASAP and schedule a reset
1364 static irqreturn_t falcon_fatal_interrupt(struct efx_nic *efx)
1366 struct falcon_nic_data *nic_data = efx->nic_data;
1367 efx_oword_t *int_ker = efx->irq_status.addr;
1368 efx_oword_t fatal_intr;
1369 int error, mem_perr;
1371 efx_reado(efx, &fatal_intr, FR_AZ_FATAL_INTR_KER);
1372 error = EFX_OWORD_FIELD(fatal_intr, FRF_AZ_FATAL_INTR);
1374 EFX_ERR(efx, "SYSTEM ERROR " EFX_OWORD_FMT " status "
1375 EFX_OWORD_FMT ": %s\n", EFX_OWORD_VAL(*int_ker),
1376 EFX_OWORD_VAL(fatal_intr),
1377 error ? "disabling bus mastering" : "no recognised error");
1381 /* If this is a memory parity error dump which blocks are offending */
1382 mem_perr = EFX_OWORD_FIELD(fatal_intr, FRF_AZ_MEM_PERR_INT_KER);
1385 efx_reado(efx, ®, FR_AZ_MEM_STAT);
1386 EFX_ERR(efx, "SYSTEM ERROR: memory parity error "
1387 EFX_OWORD_FMT "\n", EFX_OWORD_VAL(reg));
1390 /* Disable both devices */
1391 pci_clear_master(efx->pci_dev);
1392 if (FALCON_IS_DUAL_FUNC(efx))
1393 pci_clear_master(nic_data->pci_dev2);
1394 falcon_disable_interrupts(efx);
1396 /* Count errors and reset or disable the NIC accordingly */
1397 if (efx->int_error_count == 0 ||
1398 time_after(jiffies, efx->int_error_expire)) {
1399 efx->int_error_count = 0;
1400 efx->int_error_expire =
1401 jiffies + FALCON_INT_ERROR_EXPIRE * HZ;
1403 if (++efx->int_error_count < FALCON_MAX_INT_ERRORS) {
1404 EFX_ERR(efx, "SYSTEM ERROR - reset scheduled\n");
1405 efx_schedule_reset(efx, RESET_TYPE_INT_ERROR);
1407 EFX_ERR(efx, "SYSTEM ERROR - max number of errors seen."
1408 "NIC will be disabled\n");
1409 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
1415 /* Handle a legacy interrupt from Falcon
1416 * Acknowledges the interrupt and schedule event queue processing.
1418 static irqreturn_t falcon_legacy_interrupt_b0(int irq, void *dev_id)
1420 struct efx_nic *efx = dev_id;
1421 efx_oword_t *int_ker = efx->irq_status.addr;
1422 irqreturn_t result = IRQ_NONE;
1423 struct efx_channel *channel;
1428 /* Read the ISR which also ACKs the interrupts */
1429 efx_readd(efx, ®, FR_BZ_INT_ISR0);
1430 queues = EFX_EXTRACT_DWORD(reg, 0, 31);
1432 /* Check to see if we have a serious error condition */
1433 syserr = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_FATAL_INT);
1434 if (unlikely(syserr))
1435 return falcon_fatal_interrupt(efx);
1437 /* Schedule processing of any interrupting queues */
1438 efx_for_each_channel(channel, efx) {
1440 falcon_event_present(
1441 falcon_event(channel, channel->eventq_read_ptr))) {
1442 efx_schedule_channel(channel);
1443 result = IRQ_HANDLED;
1448 if (result == IRQ_HANDLED) {
1449 efx->last_irq_cpu = raw_smp_processor_id();
1450 EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n",
1451 irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg));
1458 static irqreturn_t falcon_legacy_interrupt_a1(int irq, void *dev_id)
1460 struct efx_nic *efx = dev_id;
1461 efx_oword_t *int_ker = efx->irq_status.addr;
1462 struct efx_channel *channel;
1466 /* Check to see if this is our interrupt. If it isn't, we
1467 * exit without having touched the hardware.
1469 if (unlikely(EFX_OWORD_IS_ZERO(*int_ker))) {
1470 EFX_TRACE(efx, "IRQ %d on CPU %d not for me\n", irq,
1471 raw_smp_processor_id());
1474 efx->last_irq_cpu = raw_smp_processor_id();
1475 EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_OWORD_FMT "\n",
1476 irq, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker));
1478 /* Check to see if we have a serious error condition */
1479 syserr = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_FATAL_INT);
1480 if (unlikely(syserr))
1481 return falcon_fatal_interrupt(efx);
1483 /* Determine interrupting queues, clear interrupt status
1484 * register and acknowledge the device interrupt.
1486 BUILD_BUG_ON(INT_EVQS_WIDTH > EFX_MAX_CHANNELS);
1487 queues = EFX_OWORD_FIELD(*int_ker, INT_EVQS);
1488 EFX_ZERO_OWORD(*int_ker);
1489 wmb(); /* Ensure the vector is cleared before interrupt ack */
1490 falcon_irq_ack_a1(efx);
1492 /* Schedule processing of any interrupting queues */
1493 channel = &efx->channel[0];
1496 efx_schedule_channel(channel);
1504 /* Handle an MSI interrupt from Falcon
1506 * Handle an MSI hardware interrupt. This routine schedules event
1507 * queue processing. No interrupt acknowledgement cycle is necessary.
1508 * Also, we never need to check that the interrupt is for us, since
1509 * MSI interrupts cannot be shared.
1511 static irqreturn_t falcon_msi_interrupt(int irq, void *dev_id)
1513 struct efx_channel *channel = dev_id;
1514 struct efx_nic *efx = channel->efx;
1515 efx_oword_t *int_ker = efx->irq_status.addr;
1518 efx->last_irq_cpu = raw_smp_processor_id();
1519 EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_OWORD_FMT "\n",
1520 irq, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker));
1522 /* Check to see if we have a serious error condition */
1523 syserr = EFX_OWORD_FIELD(*int_ker, FATAL_INT);
1524 if (unlikely(syserr))
1525 return falcon_fatal_interrupt(efx);
1527 /* Schedule processing of the channel */
1528 efx_schedule_channel(channel);
1534 /* Setup RSS indirection table.
1535 * This maps from the hash value of the packet to RXQ
1537 static void falcon_setup_rss_indir_table(struct efx_nic *efx)
1540 unsigned long offset;
1543 if (falcon_rev(efx) < FALCON_REV_B0)
1546 for (offset = FR_BZ_RX_INDIRECTION_TBL;
1547 offset < FR_BZ_RX_INDIRECTION_TBL + 0x800;
1549 EFX_POPULATE_DWORD_1(dword, FRF_BZ_IT_QUEUE,
1550 i % efx->n_rx_queues);
1551 efx_writed(efx, &dword, offset);
1556 /* Hook interrupt handler(s)
1557 * Try MSI and then legacy interrupts.
1559 int falcon_init_interrupt(struct efx_nic *efx)
1561 struct efx_channel *channel;
1564 if (!EFX_INT_MODE_USE_MSI(efx)) {
1565 irq_handler_t handler;
1566 if (falcon_rev(efx) >= FALCON_REV_B0)
1567 handler = falcon_legacy_interrupt_b0;
1569 handler = falcon_legacy_interrupt_a1;
1571 rc = request_irq(efx->legacy_irq, handler, IRQF_SHARED,
1574 EFX_ERR(efx, "failed to hook legacy IRQ %d\n",
1581 /* Hook MSI or MSI-X interrupt */
1582 efx_for_each_channel(channel, efx) {
1583 rc = request_irq(channel->irq, falcon_msi_interrupt,
1584 IRQF_PROBE_SHARED, /* Not shared */
1585 channel->name, channel);
1587 EFX_ERR(efx, "failed to hook IRQ %d\n", channel->irq);
1595 efx_for_each_channel(channel, efx)
1596 free_irq(channel->irq, channel);
1601 void falcon_fini_interrupt(struct efx_nic *efx)
1603 struct efx_channel *channel;
1606 /* Disable MSI/MSI-X interrupts */
1607 efx_for_each_channel(channel, efx) {
1609 free_irq(channel->irq, channel);
1612 /* ACK legacy interrupt */
1613 if (falcon_rev(efx) >= FALCON_REV_B0)
1614 efx_reado(efx, ®, FR_BZ_INT_ISR0);
1616 falcon_irq_ack_a1(efx);
1618 /* Disable legacy interrupt */
1619 if (efx->legacy_irq)
1620 free_irq(efx->legacy_irq, efx);
1623 /**************************************************************************
1627 **************************************************************************
1630 #define FALCON_SPI_MAX_LEN sizeof(efx_oword_t)
1632 static int falcon_spi_poll(struct efx_nic *efx)
1635 efx_reado(efx, ®, FR_AB_EE_SPI_HCMD);
1636 return EFX_OWORD_FIELD(reg, FRF_AB_EE_SPI_HCMD_CMD_EN) ? -EBUSY : 0;
1639 /* Wait for SPI command completion */
1640 static int falcon_spi_wait(struct efx_nic *efx)
1642 /* Most commands will finish quickly, so we start polling at
1643 * very short intervals. Sometimes the command may have to
1644 * wait for VPD or expansion ROM access outside of our
1645 * control, so we allow up to 100 ms. */
1646 unsigned long timeout = jiffies + 1 + DIV_ROUND_UP(HZ, 10);
1649 for (i = 0; i < 10; i++) {
1650 if (!falcon_spi_poll(efx))
1656 if (!falcon_spi_poll(efx))
1658 if (time_after_eq(jiffies, timeout)) {
1659 EFX_ERR(efx, "timed out waiting for SPI\n");
1662 schedule_timeout_uninterruptible(1);
1666 int falcon_spi_cmd(const struct efx_spi_device *spi,
1667 unsigned int command, int address,
1668 const void *in, void *out, size_t len)
1670 struct efx_nic *efx = spi->efx;
1671 bool addressed = (address >= 0);
1672 bool reading = (out != NULL);
1676 /* Input validation */
1677 if (len > FALCON_SPI_MAX_LEN)
1679 BUG_ON(!mutex_is_locked(&efx->spi_lock));
1681 /* Check that previous command is not still running */
1682 rc = falcon_spi_poll(efx);
1686 /* Program address register, if we have an address */
1688 EFX_POPULATE_OWORD_1(reg, FRF_AB_EE_SPI_HADR_ADR, address);
1689 efx_writeo(efx, ®, FR_AB_EE_SPI_HADR);
1692 /* Program data register, if we have data */
1694 memcpy(®, in, len);
1695 efx_writeo(efx, ®, FR_AB_EE_SPI_HDATA);
1698 /* Issue read/write command */
1699 EFX_POPULATE_OWORD_7(reg,
1700 FRF_AB_EE_SPI_HCMD_CMD_EN, 1,
1701 FRF_AB_EE_SPI_HCMD_SF_SEL, spi->device_id,
1702 FRF_AB_EE_SPI_HCMD_DABCNT, len,
1703 FRF_AB_EE_SPI_HCMD_READ, reading,
1704 FRF_AB_EE_SPI_HCMD_DUBCNT, 0,
1705 FRF_AB_EE_SPI_HCMD_ADBCNT,
1706 (addressed ? spi->addr_len : 0),
1707 FRF_AB_EE_SPI_HCMD_ENC, command);
1708 efx_writeo(efx, ®, FR_AB_EE_SPI_HCMD);
1710 /* Wait for read/write to complete */
1711 rc = falcon_spi_wait(efx);
1717 efx_reado(efx, ®, FR_AB_EE_SPI_HDATA);
1718 memcpy(out, ®, len);
1725 falcon_spi_write_limit(const struct efx_spi_device *spi, size_t start)
1727 return min(FALCON_SPI_MAX_LEN,
1728 (spi->block_size - (start & (spi->block_size - 1))));
1732 efx_spi_munge_command(const struct efx_spi_device *spi,
1733 const u8 command, const unsigned int address)
1735 return command | (((address >> 8) & spi->munge_address) << 3);
1738 /* Wait up to 10 ms for buffered write completion */
1739 int falcon_spi_wait_write(const struct efx_spi_device *spi)
1741 struct efx_nic *efx = spi->efx;
1742 unsigned long timeout = jiffies + 1 + DIV_ROUND_UP(HZ, 100);
1747 rc = falcon_spi_cmd(spi, SPI_RDSR, -1, NULL,
1748 &status, sizeof(status));
1751 if (!(status & SPI_STATUS_NRDY))
1753 if (time_after_eq(jiffies, timeout)) {
1754 EFX_ERR(efx, "SPI write timeout on device %d"
1755 " last status=0x%02x\n",
1756 spi->device_id, status);
1759 schedule_timeout_uninterruptible(1);
1763 int falcon_spi_read(const struct efx_spi_device *spi, loff_t start,
1764 size_t len, size_t *retlen, u8 *buffer)
1766 size_t block_len, pos = 0;
1767 unsigned int command;
1771 block_len = min(len - pos, FALCON_SPI_MAX_LEN);
1773 command = efx_spi_munge_command(spi, SPI_READ, start + pos);
1774 rc = falcon_spi_cmd(spi, command, start + pos, NULL,
1775 buffer + pos, block_len);
1780 /* Avoid locking up the system */
1782 if (signal_pending(current)) {
1793 int falcon_spi_write(const struct efx_spi_device *spi, loff_t start,
1794 size_t len, size_t *retlen, const u8 *buffer)
1796 u8 verify_buffer[FALCON_SPI_MAX_LEN];
1797 size_t block_len, pos = 0;
1798 unsigned int command;
1802 rc = falcon_spi_cmd(spi, SPI_WREN, -1, NULL, NULL, 0);
1806 block_len = min(len - pos,
1807 falcon_spi_write_limit(spi, start + pos));
1808 command = efx_spi_munge_command(spi, SPI_WRITE, start + pos);
1809 rc = falcon_spi_cmd(spi, command, start + pos,
1810 buffer + pos, NULL, block_len);
1814 rc = falcon_spi_wait_write(spi);
1818 command = efx_spi_munge_command(spi, SPI_READ, start + pos);
1819 rc = falcon_spi_cmd(spi, command, start + pos,
1820 NULL, verify_buffer, block_len);
1821 if (memcmp(verify_buffer, buffer + pos, block_len)) {
1828 /* Avoid locking up the system */
1830 if (signal_pending(current)) {
1841 /**************************************************************************
1845 **************************************************************************
1848 static int falcon_reset_macs(struct efx_nic *efx)
1853 if (falcon_rev(efx) < FALCON_REV_B0) {
1854 /* It's not safe to use GLB_CTL_REG to reset the
1855 * macs, so instead use the internal MAC resets
1857 if (!EFX_IS10G(efx)) {
1858 EFX_POPULATE_OWORD_1(reg, FRF_AB_GM_SW_RST, 1);
1859 efx_writeo(efx, ®, FR_AB_GM_CFG1);
1862 EFX_POPULATE_OWORD_1(reg, FRF_AB_GM_SW_RST, 0);
1863 efx_writeo(efx, ®, FR_AB_GM_CFG1);
1867 EFX_POPULATE_OWORD_1(reg, FRF_AB_XM_CORE_RST, 1);
1868 efx_writeo(efx, ®, FR_AB_XM_GLB_CFG);
1870 for (count = 0; count < 10000; count++) {
1871 efx_reado(efx, ®, FR_AB_XM_GLB_CFG);
1872 if (EFX_OWORD_FIELD(reg, FRF_AB_XM_CORE_RST) ==
1878 EFX_ERR(efx, "timed out waiting for XMAC core reset\n");
1883 /* MAC stats will fail whilst the TX fifo is draining. Serialise
1884 * the drain sequence with the statistics fetch */
1885 efx_stats_disable(efx);
1887 efx_reado(efx, ®, FR_AB_MAC_CTRL);
1888 EFX_SET_OWORD_FIELD(reg, FRF_BB_TXFIFO_DRAIN_EN, 1);
1889 efx_writeo(efx, ®, FR_AB_MAC_CTRL);
1891 efx_reado(efx, ®, FR_AB_GLB_CTL);
1892 EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_XGTX, 1);
1893 EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_XGRX, 1);
1894 EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_EM, 1);
1895 efx_writeo(efx, ®, FR_AB_GLB_CTL);
1899 efx_reado(efx, ®, FR_AB_GLB_CTL);
1900 if (!EFX_OWORD_FIELD(reg, FRF_AB_RST_XGTX) &&
1901 !EFX_OWORD_FIELD(reg, FRF_AB_RST_XGRX) &&
1902 !EFX_OWORD_FIELD(reg, FRF_AB_RST_EM)) {
1903 EFX_LOG(efx, "Completed MAC reset after %d loops\n",
1908 EFX_ERR(efx, "MAC reset failed\n");
1915 efx_stats_enable(efx);
1917 /* If we've reset the EM block and the link is up, then
1918 * we'll have to kick the XAUI link so the PHY can recover */
1919 if (efx->link_up && EFX_IS10G(efx) && EFX_WORKAROUND_5147(efx))
1920 falcon_reset_xaui(efx);
1925 void falcon_drain_tx_fifo(struct efx_nic *efx)
1929 if ((falcon_rev(efx) < FALCON_REV_B0) ||
1930 (efx->loopback_mode != LOOPBACK_NONE))
1933 efx_reado(efx, ®, FR_AB_MAC_CTRL);
1934 /* There is no point in draining more than once */
1935 if (EFX_OWORD_FIELD(reg, FRF_BB_TXFIFO_DRAIN_EN))
1938 falcon_reset_macs(efx);
1941 void falcon_deconfigure_mac_wrapper(struct efx_nic *efx)
1945 if (falcon_rev(efx) < FALCON_REV_B0)
1948 /* Isolate the MAC -> RX */
1949 efx_reado(efx, ®, FR_AZ_RX_CFG);
1950 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 0);
1951 efx_writeo(efx, ®, FR_AZ_RX_CFG);
1954 falcon_drain_tx_fifo(efx);
1957 void falcon_reconfigure_mac_wrapper(struct efx_nic *efx)
1963 switch (efx->link_speed) {
1964 case 10000: link_speed = 3; break;
1965 case 1000: link_speed = 2; break;
1966 case 100: link_speed = 1; break;
1967 default: link_speed = 0; break;
1969 /* MAC_LINK_STATUS controls MAC backpressure but doesn't work
1970 * as advertised. Disable to ensure packets are not
1971 * indefinitely held and TX queue can be flushed at any point
1972 * while the link is down. */
1973 EFX_POPULATE_OWORD_5(reg,
1974 FRF_AB_MAC_XOFF_VAL, 0xffff /* max pause time */,
1975 FRF_AB_MAC_BCAD_ACPT, 1,
1976 FRF_AB_MAC_UC_PROM, efx->promiscuous,
1977 FRF_AB_MAC_LINK_STATUS, 1, /* always set */
1978 FRF_AB_MAC_SPEED, link_speed);
1979 /* On B0, MAC backpressure can be disabled and packets get
1981 if (falcon_rev(efx) >= FALCON_REV_B0) {
1982 EFX_SET_OWORD_FIELD(reg, FRF_BB_TXFIFO_DRAIN_EN,
1986 efx_writeo(efx, ®, FR_AB_MAC_CTRL);
1988 /* Restore the multicast hash registers. */
1989 falcon_set_multicast_hash(efx);
1991 /* Transmission of pause frames when RX crosses the threshold is
1992 * covered by RX_XOFF_MAC_EN and XM_TX_CFG_REG:XM_FCNTL.
1993 * Action on receipt of pause frames is controller by XM_DIS_FCNTL */
1994 tx_fc = !!(efx->link_fc & EFX_FC_TX);
1995 efx_reado(efx, ®, FR_AZ_RX_CFG);
1996 EFX_SET_OWORD_FIELD(reg, FRF_AZ_RX_XOFF_MAC_EN, tx_fc);
1998 /* Unisolate the MAC -> RX */
1999 if (falcon_rev(efx) >= FALCON_REV_B0)
2000 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 1);
2001 efx_writeo(efx, ®, FR_AZ_RX_CFG);
2004 int falcon_dma_stats(struct efx_nic *efx, unsigned int done_offset)
2010 if (disable_dma_stats)
2013 /* Statistics fetch will fail if the MAC is in TX drain */
2014 if (falcon_rev(efx) >= FALCON_REV_B0) {
2016 efx_reado(efx, &temp, FR_AB_MAC_CTRL);
2017 if (EFX_OWORD_FIELD(temp, FRF_BB_TXFIFO_DRAIN_EN))
2021 dma_done = (efx->stats_buffer.addr + done_offset);
2022 *dma_done = FALCON_STATS_NOT_DONE;
2023 wmb(); /* ensure done flag is clear */
2025 /* Initiate DMA transfer of stats */
2026 EFX_POPULATE_OWORD_2(reg,
2027 FRF_AB_MAC_STAT_DMA_CMD, 1,
2028 FRF_AB_MAC_STAT_DMA_ADR,
2029 efx->stats_buffer.dma_addr);
2030 efx_writeo(efx, ®, FR_AB_MAC_STAT_DMA);
2032 /* Wait for transfer to complete */
2033 for (i = 0; i < 400; i++) {
2034 if (*(volatile u32 *)dma_done == FALCON_STATS_DONE) {
2035 rmb(); /* Ensure the stats are valid. */
2041 EFX_ERR(efx, "timed out waiting for statistics\n");
2045 /**************************************************************************
2047 * PHY access via GMII
2049 **************************************************************************
2052 /* Wait for GMII access to complete */
2053 static int falcon_gmii_wait(struct efx_nic *efx)
2055 efx_dword_t md_stat;
2058 /* wait upto 50ms - taken max from datasheet */
2059 for (count = 0; count < 5000; count++) {
2060 efx_readd(efx, &md_stat, FR_AB_MD_STAT);
2061 if (EFX_DWORD_FIELD(md_stat, FRF_AB_MD_BSY) == 0) {
2062 if (EFX_DWORD_FIELD(md_stat, FRF_AB_MD_LNFL) != 0 ||
2063 EFX_DWORD_FIELD(md_stat, FRF_AB_MD_BSERR) != 0) {
2064 EFX_ERR(efx, "error from GMII access "
2066 EFX_DWORD_VAL(md_stat));
2073 EFX_ERR(efx, "timed out waiting for GMII\n");
2077 /* Write an MDIO register of a PHY connected to Falcon. */
2078 static int falcon_mdio_write(struct net_device *net_dev,
2079 int prtad, int devad, u16 addr, u16 value)
2081 struct efx_nic *efx = netdev_priv(net_dev);
2085 EFX_REGDUMP(efx, "writing MDIO %d register %d.%d with 0x%04x\n",
2086 prtad, devad, addr, value);
2088 spin_lock_bh(&efx->phy_lock);
2090 /* Check MDIO not currently being accessed */
2091 rc = falcon_gmii_wait(efx);
2095 /* Write the address/ID register */
2096 EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_PHY_ADR, addr);
2097 efx_writeo(efx, ®, FR_AB_MD_PHY_ADR);
2099 EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_PRT_ADR, prtad,
2100 FRF_AB_MD_DEV_ADR, devad);
2101 efx_writeo(efx, ®, FR_AB_MD_ID);
2104 EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_TXD, value);
2105 efx_writeo(efx, ®, FR_AB_MD_TXD);
2107 EFX_POPULATE_OWORD_2(reg,
2110 efx_writeo(efx, ®, FR_AB_MD_CS);
2112 /* Wait for data to be written */
2113 rc = falcon_gmii_wait(efx);
2115 /* Abort the write operation */
2116 EFX_POPULATE_OWORD_2(reg,
2119 efx_writeo(efx, ®, FR_AB_MD_CS);
2124 spin_unlock_bh(&efx->phy_lock);
2128 /* Read an MDIO register of a PHY connected to Falcon. */
2129 static int falcon_mdio_read(struct net_device *net_dev,
2130 int prtad, int devad, u16 addr)
2132 struct efx_nic *efx = netdev_priv(net_dev);
2136 spin_lock_bh(&efx->phy_lock);
2138 /* Check MDIO not currently being accessed */
2139 rc = falcon_gmii_wait(efx);
2143 EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_PHY_ADR, addr);
2144 efx_writeo(efx, ®, FR_AB_MD_PHY_ADR);
2146 EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_PRT_ADR, prtad,
2147 FRF_AB_MD_DEV_ADR, devad);
2148 efx_writeo(efx, ®, FR_AB_MD_ID);
2150 /* Request data to be read */
2151 EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_RDC, 1, FRF_AB_MD_GC, 0);
2152 efx_writeo(efx, ®, FR_AB_MD_CS);
2154 /* Wait for data to become available */
2155 rc = falcon_gmii_wait(efx);
2157 efx_reado(efx, ®, FR_AB_MD_RXD);
2158 rc = EFX_OWORD_FIELD(reg, FRF_AB_MD_RXD);
2159 EFX_REGDUMP(efx, "read from MDIO %d register %d.%d, got %04x\n",
2160 prtad, devad, addr, rc);
2162 /* Abort the read operation */
2163 EFX_POPULATE_OWORD_2(reg,
2166 efx_writeo(efx, ®, FR_AB_MD_CS);
2168 EFX_LOG(efx, "read from MDIO %d register %d.%d, got error %d\n",
2169 prtad, devad, addr, rc);
2173 spin_unlock_bh(&efx->phy_lock);
2177 int falcon_switch_mac(struct efx_nic *efx)
2179 struct efx_mac_operations *old_mac_op = efx->mac_op;
2180 efx_oword_t nic_stat;
2184 /* Don't try to fetch MAC stats while we're switching MACs */
2185 efx_stats_disable(efx);
2187 /* Internal loopbacks override the phy speed setting */
2188 if (efx->loopback_mode == LOOPBACK_GMAC) {
2189 efx->link_speed = 1000;
2190 efx->link_fd = true;
2191 } else if (LOOPBACK_INTERNAL(efx)) {
2192 efx->link_speed = 10000;
2193 efx->link_fd = true;
2196 WARN_ON(!mutex_is_locked(&efx->mac_lock));
2197 efx->mac_op = (EFX_IS10G(efx) ?
2198 &falcon_xmac_operations : &falcon_gmac_operations);
2200 /* Always push the NIC_STAT_REG setting even if the mac hasn't
2201 * changed, because this function is run post online reset */
2202 efx_reado(efx, &nic_stat, FR_AB_NIC_STAT);
2203 strap_val = EFX_IS10G(efx) ? 5 : 3;
2204 if (falcon_rev(efx) >= FALCON_REV_B0) {
2205 EFX_SET_OWORD_FIELD(nic_stat, FRF_BB_EE_STRAP_EN, 1);
2206 EFX_SET_OWORD_FIELD(nic_stat, FRF_BB_EE_STRAP, strap_val);
2207 efx_writeo(efx, &nic_stat, FR_AB_NIC_STAT);
2209 /* Falcon A1 does not support 1G/10G speed switching
2210 * and must not be used with a PHY that does. */
2211 BUG_ON(EFX_OWORD_FIELD(nic_stat, FRF_AB_STRAP_PINS) !=
2215 if (old_mac_op == efx->mac_op)
2218 EFX_LOG(efx, "selected %cMAC\n", EFX_IS10G(efx) ? 'X' : 'G');
2219 /* Not all macs support a mac-level link state */
2222 rc = falcon_reset_macs(efx);
2224 efx_stats_enable(efx);
2228 /* This call is responsible for hooking in the MAC and PHY operations */
2229 int falcon_probe_port(struct efx_nic *efx)
2233 switch (efx->phy_type) {
2234 case PHY_TYPE_SFX7101:
2235 efx->phy_op = &falcon_sfx7101_phy_ops;
2237 case PHY_TYPE_SFT9001A:
2238 case PHY_TYPE_SFT9001B:
2239 efx->phy_op = &falcon_sft9001_phy_ops;
2241 case PHY_TYPE_QT2022C2:
2242 case PHY_TYPE_QT2025C:
2243 efx->phy_op = &falcon_qt202x_phy_ops;
2246 EFX_ERR(efx, "Unknown PHY type %d\n",
2251 if (efx->phy_op->macs & EFX_XMAC)
2252 efx->loopback_modes |= ((1 << LOOPBACK_XGMII) |
2253 (1 << LOOPBACK_XGXS) |
2254 (1 << LOOPBACK_XAUI));
2255 if (efx->phy_op->macs & EFX_GMAC)
2256 efx->loopback_modes |= (1 << LOOPBACK_GMAC);
2257 efx->loopback_modes |= efx->phy_op->loopbacks;
2259 /* Set up MDIO structure for PHY */
2260 efx->mdio.mmds = efx->phy_op->mmds;
2261 efx->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
2262 efx->mdio.mdio_read = falcon_mdio_read;
2263 efx->mdio.mdio_write = falcon_mdio_write;
2265 /* Hardware flow ctrl. FalconA RX FIFO too small for pause generation */
2266 if (falcon_rev(efx) >= FALCON_REV_B0)
2267 efx->wanted_fc = EFX_FC_RX | EFX_FC_TX;
2269 efx->wanted_fc = EFX_FC_RX;
2271 /* Allocate buffer for stats */
2272 rc = falcon_alloc_buffer(efx, &efx->stats_buffer,
2273 FALCON_MAC_STATS_SIZE);
2276 EFX_LOG(efx, "stats buffer at %llx (virt %p phys %llx)\n",
2277 (u64)efx->stats_buffer.dma_addr,
2278 efx->stats_buffer.addr,
2279 (u64)virt_to_phys(efx->stats_buffer.addr));
2284 void falcon_remove_port(struct efx_nic *efx)
2286 falcon_free_buffer(efx, &efx->stats_buffer);
2289 /**************************************************************************
2291 * Multicast filtering
2293 **************************************************************************
2296 void falcon_set_multicast_hash(struct efx_nic *efx)
2298 union efx_multicast_hash *mc_hash = &efx->multicast_hash;
2300 /* Broadcast packets go through the multicast hash filter.
2301 * ether_crc_le() of the broadcast address is 0xbe2612ff
2302 * so we always add bit 0xff to the mask.
2304 set_bit_le(0xff, mc_hash->byte);
2306 efx_writeo(efx, &mc_hash->oword[0], FR_AB_MAC_MC_HASH_REG0);
2307 efx_writeo(efx, &mc_hash->oword[1], FR_AB_MAC_MC_HASH_REG1);
2311 /**************************************************************************
2315 **************************************************************************/
2317 int falcon_read_nvram(struct efx_nic *efx, struct falcon_nvconfig *nvconfig_out)
2319 struct falcon_nvconfig *nvconfig;
2320 struct efx_spi_device *spi;
2322 int rc, magic_num, struct_ver;
2323 __le16 *word, *limit;
2326 spi = efx->spi_flash ? efx->spi_flash : efx->spi_eeprom;
2330 region = kmalloc(FALCON_NVCONFIG_END, GFP_KERNEL);
2333 nvconfig = region + FALCON_NVCONFIG_OFFSET;
2335 mutex_lock(&efx->spi_lock);
2336 rc = falcon_spi_read(spi, 0, FALCON_NVCONFIG_END, NULL, region);
2337 mutex_unlock(&efx->spi_lock);
2339 EFX_ERR(efx, "Failed to read %s\n",
2340 efx->spi_flash ? "flash" : "EEPROM");
2345 magic_num = le16_to_cpu(nvconfig->board_magic_num);
2346 struct_ver = le16_to_cpu(nvconfig->board_struct_ver);
2349 if (magic_num != FALCON_NVCONFIG_BOARD_MAGIC_NUM) {
2350 EFX_ERR(efx, "NVRAM bad magic 0x%x\n", magic_num);
2353 if (struct_ver < 2) {
2354 EFX_ERR(efx, "NVRAM has ancient version 0x%x\n", struct_ver);
2356 } else if (struct_ver < 4) {
2357 word = &nvconfig->board_magic_num;
2358 limit = (__le16 *) (nvconfig + 1);
2361 limit = region + FALCON_NVCONFIG_END;
2363 for (csum = 0; word < limit; ++word)
2364 csum += le16_to_cpu(*word);
2366 if (~csum & 0xffff) {
2367 EFX_ERR(efx, "NVRAM has incorrect checksum\n");
2373 memcpy(nvconfig_out, nvconfig, sizeof(*nvconfig));
2380 /* Registers tested in the falcon register test */
2384 } efx_test_registers[] = {
2386 EFX_OWORD32(0x0001FFFF, 0x0001FFFF, 0x0001FFFF, 0x0001FFFF) },
2388 EFX_OWORD32(0xFFFFFFFE, 0x00017FFF, 0x00000000, 0x00000000) },
2390 EFX_OWORD32(0x7FFF0037, 0x00000000, 0x00000000, 0x00000000) },
2391 { FR_AZ_TX_RESERVED,
2392 EFX_OWORD32(0xFFFEFE80, 0x1FFFFFFF, 0x020000FE, 0x007FFFFF) },
2394 EFX_OWORD32(0xFFFF0000, 0x00000000, 0x00000000, 0x00000000) },
2395 { FR_AZ_SRM_TX_DC_CFG,
2396 EFX_OWORD32(0x001FFFFF, 0x00000000, 0x00000000, 0x00000000) },
2398 EFX_OWORD32(0x0000000F, 0x00000000, 0x00000000, 0x00000000) },
2399 { FR_AZ_RX_DC_PF_WM,
2400 EFX_OWORD32(0x000003FF, 0x00000000, 0x00000000, 0x00000000) },
2402 EFX_OWORD32(0x00000FFF, 0x00000000, 0x00000000, 0x00000000) },
2404 EFX_OWORD32(0x00007337, 0x00000000, 0x00000000, 0x00000000) },
2406 EFX_OWORD32(0x00001F1F, 0x00000000, 0x00000000, 0x00000000) },
2408 EFX_OWORD32(0x00000C68, 0x00000000, 0x00000000, 0x00000000) },
2410 EFX_OWORD32(0x00080164, 0x00000000, 0x00000000, 0x00000000) },
2412 EFX_OWORD32(0x07100A0C, 0x00000000, 0x00000000, 0x00000000) },
2413 { FR_AB_XM_RX_PARAM,
2414 EFX_OWORD32(0x00001FF8, 0x00000000, 0x00000000, 0x00000000) },
2416 EFX_OWORD32(0xFFFF0001, 0x00000000, 0x00000000, 0x00000000) },
2418 EFX_OWORD32(0xFFFFFFFF, 0x00000000, 0x00000000, 0x00000000) },
2420 EFX_OWORD32(0x0003FF0F, 0x00000000, 0x00000000, 0x00000000) },
2423 static bool efx_masked_compare_oword(const efx_oword_t *a, const efx_oword_t *b,
2424 const efx_oword_t *mask)
2426 return ((a->u64[0] ^ b->u64[0]) & mask->u64[0]) ||
2427 ((a->u64[1] ^ b->u64[1]) & mask->u64[1]);
2430 int falcon_test_registers(struct efx_nic *efx)
2432 unsigned address = 0, i, j;
2433 efx_oword_t mask, imask, original, reg, buf;
2435 /* Falcon should be in loopback to isolate the XMAC from the PHY */
2436 WARN_ON(!LOOPBACK_INTERNAL(efx));
2438 for (i = 0; i < ARRAY_SIZE(efx_test_registers); ++i) {
2439 address = efx_test_registers[i].address;
2440 mask = imask = efx_test_registers[i].mask;
2441 EFX_INVERT_OWORD(imask);
2443 efx_reado(efx, &original, address);
2445 /* bit sweep on and off */
2446 for (j = 0; j < 128; j++) {
2447 if (!EFX_EXTRACT_OWORD32(mask, j, j))
2450 /* Test this testable bit can be set in isolation */
2451 EFX_AND_OWORD(reg, original, mask);
2452 EFX_SET_OWORD32(reg, j, j, 1);
2454 efx_writeo(efx, ®, address);
2455 efx_reado(efx, &buf, address);
2457 if (efx_masked_compare_oword(®, &buf, &mask))
2460 /* Test this testable bit can be cleared in isolation */
2461 EFX_OR_OWORD(reg, original, mask);
2462 EFX_SET_OWORD32(reg, j, j, 0);
2464 efx_writeo(efx, ®, address);
2465 efx_reado(efx, &buf, address);
2467 if (efx_masked_compare_oword(®, &buf, &mask))
2471 efx_writeo(efx, &original, address);
2477 EFX_ERR(efx, "wrote "EFX_OWORD_FMT" read "EFX_OWORD_FMT
2478 " at address 0x%x mask "EFX_OWORD_FMT"\n", EFX_OWORD_VAL(reg),
2479 EFX_OWORD_VAL(buf), address, EFX_OWORD_VAL(mask));
2483 /**************************************************************************
2487 **************************************************************************
2490 /* Resets NIC to known state. This routine must be called in process
2491 * context and is allowed to sleep. */
2492 int falcon_reset_hw(struct efx_nic *efx, enum reset_type method)
2494 struct falcon_nic_data *nic_data = efx->nic_data;
2495 efx_oword_t glb_ctl_reg_ker;
2498 EFX_LOG(efx, "performing hardware reset (%d)\n", method);
2500 /* Initiate device reset */
2501 if (method == RESET_TYPE_WORLD) {
2502 rc = pci_save_state(efx->pci_dev);
2504 EFX_ERR(efx, "failed to backup PCI state of primary "
2505 "function prior to hardware reset\n");
2508 if (FALCON_IS_DUAL_FUNC(efx)) {
2509 rc = pci_save_state(nic_data->pci_dev2);
2511 EFX_ERR(efx, "failed to backup PCI state of "
2512 "secondary function prior to "
2513 "hardware reset\n");
2518 EFX_POPULATE_OWORD_2(glb_ctl_reg_ker,
2519 FRF_AB_EXT_PHY_RST_DUR,
2520 FFE_AB_EXT_PHY_RST_DUR_10240US,
2523 EFX_POPULATE_OWORD_7(glb_ctl_reg_ker,
2524 /* exclude PHY from "invisible" reset */
2525 FRF_AB_EXT_PHY_RST_CTL,
2526 method == RESET_TYPE_INVISIBLE,
2527 /* exclude EEPROM/flash and PCIe */
2528 FRF_AB_PCIE_CORE_RST_CTL, 1,
2529 FRF_AB_PCIE_NSTKY_RST_CTL, 1,
2530 FRF_AB_PCIE_SD_RST_CTL, 1,
2531 FRF_AB_EE_RST_CTL, 1,
2532 FRF_AB_EXT_PHY_RST_DUR,
2533 FFE_AB_EXT_PHY_RST_DUR_10240US,
2536 efx_writeo(efx, &glb_ctl_reg_ker, FR_AB_GLB_CTL);
2538 EFX_LOG(efx, "waiting for hardware reset\n");
2539 schedule_timeout_uninterruptible(HZ / 20);
2541 /* Restore PCI configuration if needed */
2542 if (method == RESET_TYPE_WORLD) {
2543 if (FALCON_IS_DUAL_FUNC(efx)) {
2544 rc = pci_restore_state(nic_data->pci_dev2);
2546 EFX_ERR(efx, "failed to restore PCI config for "
2547 "the secondary function\n");
2551 rc = pci_restore_state(efx->pci_dev);
2553 EFX_ERR(efx, "failed to restore PCI config for the "
2554 "primary function\n");
2557 EFX_LOG(efx, "successfully restored PCI config\n");
2560 /* Assert that reset complete */
2561 efx_reado(efx, &glb_ctl_reg_ker, FR_AB_GLB_CTL);
2562 if (EFX_OWORD_FIELD(glb_ctl_reg_ker, FRF_AB_SWRST) != 0) {
2564 EFX_ERR(efx, "timed out waiting for hardware reset\n");
2567 EFX_LOG(efx, "hardware reset complete\n");
2571 /* pci_save_state() and pci_restore_state() MUST be called in pairs */
2574 pci_restore_state(efx->pci_dev);
2581 /* Zeroes out the SRAM contents. This routine must be called in
2582 * process context and is allowed to sleep.
2584 static int falcon_reset_sram(struct efx_nic *efx)
2586 efx_oword_t srm_cfg_reg_ker, gpio_cfg_reg_ker;
2589 /* Set the SRAM wake/sleep GPIO appropriately. */
2590 efx_reado(efx, &gpio_cfg_reg_ker, FR_AB_GPIO_CTL);
2591 EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, FRF_AB_GPIO1_OEN, 1);
2592 EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, FRF_AB_GPIO1_OUT, 1);
2593 efx_writeo(efx, &gpio_cfg_reg_ker, FR_AB_GPIO_CTL);
2595 /* Initiate SRAM reset */
2596 EFX_POPULATE_OWORD_2(srm_cfg_reg_ker,
2597 FRF_AZ_SRM_INIT_EN, 1,
2598 FRF_AZ_SRM_NB_SZ, 0);
2599 efx_writeo(efx, &srm_cfg_reg_ker, FR_AZ_SRM_CFG);
2601 /* Wait for SRAM reset to complete */
2604 EFX_LOG(efx, "waiting for SRAM reset (attempt %d)...\n", count);
2606 /* SRAM reset is slow; expect around 16ms */
2607 schedule_timeout_uninterruptible(HZ / 50);
2609 /* Check for reset complete */
2610 efx_reado(efx, &srm_cfg_reg_ker, FR_AZ_SRM_CFG);
2611 if (!EFX_OWORD_FIELD(srm_cfg_reg_ker, FRF_AZ_SRM_INIT_EN)) {
2612 EFX_LOG(efx, "SRAM reset complete\n");
2616 } while (++count < 20); /* wait upto 0.4 sec */
2618 EFX_ERR(efx, "timed out waiting for SRAM reset\n");
2622 static int falcon_spi_device_init(struct efx_nic *efx,
2623 struct efx_spi_device **spi_device_ret,
2624 unsigned int device_id, u32 device_type)
2626 struct efx_spi_device *spi_device;
2628 if (device_type != 0) {
2629 spi_device = kzalloc(sizeof(*spi_device), GFP_KERNEL);
2632 spi_device->device_id = device_id;
2634 1 << SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_SIZE);
2635 spi_device->addr_len =
2636 SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_ADDR_LEN);
2637 spi_device->munge_address = (spi_device->size == 1 << 9 &&
2638 spi_device->addr_len == 1);
2639 spi_device->erase_command =
2640 SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_ERASE_CMD);
2641 spi_device->erase_size =
2642 1 << SPI_DEV_TYPE_FIELD(device_type,
2643 SPI_DEV_TYPE_ERASE_SIZE);
2644 spi_device->block_size =
2645 1 << SPI_DEV_TYPE_FIELD(device_type,
2646 SPI_DEV_TYPE_BLOCK_SIZE);
2648 spi_device->efx = efx;
2653 kfree(*spi_device_ret);
2654 *spi_device_ret = spi_device;
2659 static void falcon_remove_spi_devices(struct efx_nic *efx)
2661 kfree(efx->spi_eeprom);
2662 efx->spi_eeprom = NULL;
2663 kfree(efx->spi_flash);
2664 efx->spi_flash = NULL;
2667 /* Extract non-volatile configuration */
2668 static int falcon_probe_nvconfig(struct efx_nic *efx)
2670 struct falcon_nvconfig *nvconfig;
2674 nvconfig = kmalloc(sizeof(*nvconfig), GFP_KERNEL);
2678 rc = falcon_read_nvram(efx, nvconfig);
2679 if (rc == -EINVAL) {
2680 EFX_ERR(efx, "NVRAM is invalid therefore using defaults\n");
2681 efx->phy_type = PHY_TYPE_NONE;
2682 efx->mdio.prtad = MDIO_PRTAD_NONE;
2688 struct falcon_nvconfig_board_v2 *v2 = &nvconfig->board_v2;
2689 struct falcon_nvconfig_board_v3 *v3 = &nvconfig->board_v3;
2691 efx->phy_type = v2->port0_phy_type;
2692 efx->mdio.prtad = v2->port0_phy_addr;
2693 board_rev = le16_to_cpu(v2->board_revision);
2695 if (le16_to_cpu(nvconfig->board_struct_ver) >= 3) {
2696 rc = falcon_spi_device_init(
2697 efx, &efx->spi_flash, FFE_AB_SPI_DEVICE_FLASH,
2698 le32_to_cpu(v3->spi_device_type
2699 [FFE_AB_SPI_DEVICE_FLASH]));
2702 rc = falcon_spi_device_init(
2703 efx, &efx->spi_eeprom, FFE_AB_SPI_DEVICE_EEPROM,
2704 le32_to_cpu(v3->spi_device_type
2705 [FFE_AB_SPI_DEVICE_EEPROM]));
2711 /* Read the MAC addresses */
2712 memcpy(efx->mac_address, nvconfig->mac_address[0], ETH_ALEN);
2714 EFX_LOG(efx, "PHY is %d phy_id %d\n", efx->phy_type, efx->mdio.prtad);
2716 falcon_probe_board(efx, board_rev);
2722 falcon_remove_spi_devices(efx);
2728 /* Probe the NIC variant (revision, ASIC vs FPGA, function count, port
2729 * count, port speed). Set workaround and feature flags accordingly.
2731 static int falcon_probe_nic_variant(struct efx_nic *efx)
2733 efx_oword_t altera_build;
2734 efx_oword_t nic_stat;
2736 efx_reado(efx, &altera_build, FR_AZ_ALTERA_BUILD);
2737 if (EFX_OWORD_FIELD(altera_build, FRF_AZ_ALTERA_BUILD_VER)) {
2738 EFX_ERR(efx, "Falcon FPGA not supported\n");
2742 efx_reado(efx, &nic_stat, FR_AB_NIC_STAT);
2744 switch (falcon_rev(efx)) {
2747 EFX_ERR(efx, "Falcon rev A0 not supported\n");
2751 if (EFX_OWORD_FIELD(nic_stat, FRF_AA_STRAP_PCIE) == 0) {
2752 EFX_ERR(efx, "Falcon rev A1 PCI-X not supported\n");
2761 EFX_ERR(efx, "Unknown Falcon rev %d\n", falcon_rev(efx));
2765 /* Initial assumed speed */
2766 efx->link_speed = EFX_OWORD_FIELD(nic_stat, FRF_AB_STRAP_10G) ? 10000 : 1000;
2771 /* Probe all SPI devices on the NIC */
2772 static void falcon_probe_spi_devices(struct efx_nic *efx)
2774 efx_oword_t nic_stat, gpio_ctl, ee_vpd_cfg;
2777 efx_reado(efx, &gpio_ctl, FR_AB_GPIO_CTL);
2778 efx_reado(efx, &nic_stat, FR_AB_NIC_STAT);
2779 efx_reado(efx, &ee_vpd_cfg, FR_AB_EE_VPD_CFG0);
2781 if (EFX_OWORD_FIELD(gpio_ctl, FRF_AB_GPIO3_PWRUP_VALUE)) {
2782 boot_dev = (EFX_OWORD_FIELD(nic_stat, FRF_AB_SF_PRST) ?
2783 FFE_AB_SPI_DEVICE_FLASH : FFE_AB_SPI_DEVICE_EEPROM);
2784 EFX_LOG(efx, "Booted from %s\n",
2785 boot_dev == FFE_AB_SPI_DEVICE_FLASH ? "flash" : "EEPROM");
2787 /* Disable VPD and set clock dividers to safe
2788 * values for initial programming. */
2790 EFX_LOG(efx, "Booted from internal ASIC settings;"
2791 " setting SPI config\n");
2792 EFX_POPULATE_OWORD_3(ee_vpd_cfg, FRF_AB_EE_VPD_EN, 0,
2793 /* 125 MHz / 7 ~= 20 MHz */
2794 FRF_AB_EE_SF_CLOCK_DIV, 7,
2795 /* 125 MHz / 63 ~= 2 MHz */
2796 FRF_AB_EE_EE_CLOCK_DIV, 63);
2797 efx_writeo(efx, &ee_vpd_cfg, FR_AB_EE_VPD_CFG0);
2800 if (boot_dev == FFE_AB_SPI_DEVICE_FLASH)
2801 falcon_spi_device_init(efx, &efx->spi_flash,
2802 FFE_AB_SPI_DEVICE_FLASH,
2803 default_flash_type);
2804 if (boot_dev == FFE_AB_SPI_DEVICE_EEPROM)
2805 falcon_spi_device_init(efx, &efx->spi_eeprom,
2806 FFE_AB_SPI_DEVICE_EEPROM,
2810 int falcon_probe_nic(struct efx_nic *efx)
2812 struct falcon_nic_data *nic_data;
2815 /* Allocate storage for hardware specific data */
2816 nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL);
2819 efx->nic_data = nic_data;
2821 /* Determine number of ports etc. */
2822 rc = falcon_probe_nic_variant(efx);
2826 /* Probe secondary function if expected */
2827 if (FALCON_IS_DUAL_FUNC(efx)) {
2828 struct pci_dev *dev = pci_dev_get(efx->pci_dev);
2830 while ((dev = pci_get_device(EFX_VENDID_SFC, FALCON_A_S_DEVID,
2832 if (dev->bus == efx->pci_dev->bus &&
2833 dev->devfn == efx->pci_dev->devfn + 1) {
2834 nic_data->pci_dev2 = dev;
2838 if (!nic_data->pci_dev2) {
2839 EFX_ERR(efx, "failed to find secondary function\n");
2845 /* Now we can reset the NIC */
2846 rc = falcon_reset_hw(efx, RESET_TYPE_ALL);
2848 EFX_ERR(efx, "failed to reset NIC\n");
2852 /* Allocate memory for INT_KER */
2853 rc = falcon_alloc_buffer(efx, &efx->irq_status, sizeof(efx_oword_t));
2856 BUG_ON(efx->irq_status.dma_addr & 0x0f);
2858 EFX_LOG(efx, "INT_KER at %llx (virt %p phys %llx)\n",
2859 (u64)efx->irq_status.dma_addr,
2860 efx->irq_status.addr, (u64)virt_to_phys(efx->irq_status.addr));
2862 falcon_probe_spi_devices(efx);
2864 /* Read in the non-volatile configuration */
2865 rc = falcon_probe_nvconfig(efx);
2869 /* Initialise I2C adapter */
2870 efx->i2c_adap.owner = THIS_MODULE;
2871 nic_data->i2c_data = falcon_i2c_bit_operations;
2872 nic_data->i2c_data.data = efx;
2873 efx->i2c_adap.algo_data = &nic_data->i2c_data;
2874 efx->i2c_adap.dev.parent = &efx->pci_dev->dev;
2875 strlcpy(efx->i2c_adap.name, "SFC4000 GPIO", sizeof(efx->i2c_adap.name));
2876 rc = i2c_bit_add_bus(&efx->i2c_adap);
2883 falcon_remove_spi_devices(efx);
2884 falcon_free_buffer(efx, &efx->irq_status);
2887 if (nic_data->pci_dev2) {
2888 pci_dev_put(nic_data->pci_dev2);
2889 nic_data->pci_dev2 = NULL;
2893 kfree(efx->nic_data);
2897 static void falcon_init_rx_cfg(struct efx_nic *efx)
2899 /* Prior to Siena the RX DMA engine will split each frame at
2900 * intervals of RX_USR_BUF_SIZE (32-byte units). We set it to
2901 * be so large that that never happens. */
2902 const unsigned huge_buf_size = (3 * 4096) >> 5;
2903 /* RX control FIFO thresholds (32 entries) */
2904 const unsigned ctrl_xon_thr = 20;
2905 const unsigned ctrl_xoff_thr = 25;
2906 /* RX data FIFO thresholds (256-byte units; size varies) */
2907 int data_xon_thr = rx_xon_thresh_bytes >> 8;
2908 int data_xoff_thr = rx_xoff_thresh_bytes >> 8;
2911 efx_reado(efx, ®, FR_AZ_RX_CFG);
2912 if (falcon_rev(efx) <= FALCON_REV_A1) {
2913 /* Data FIFO size is 5.5K */
2914 if (data_xon_thr < 0)
2915 data_xon_thr = 512 >> 8;
2916 if (data_xoff_thr < 0)
2917 data_xoff_thr = 2048 >> 8;
2918 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_DESC_PUSH_EN, 0);
2919 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_USR_BUF_SIZE,
2921 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XON_MAC_TH, data_xon_thr);
2922 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XOFF_MAC_TH, data_xoff_thr);
2923 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XON_TX_TH, ctrl_xon_thr);
2924 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XOFF_TX_TH, ctrl_xoff_thr);
2926 /* Data FIFO size is 80K; register fields moved */
2927 if (data_xon_thr < 0)
2928 data_xon_thr = 27648 >> 8; /* ~3*max MTU */
2929 if (data_xoff_thr < 0)
2930 data_xoff_thr = 54272 >> 8; /* ~80Kb - 3*max MTU */
2931 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_DESC_PUSH_EN, 0);
2932 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_USR_BUF_SIZE,
2934 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XON_MAC_TH, data_xon_thr);
2935 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XOFF_MAC_TH, data_xoff_thr);
2936 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XON_TX_TH, ctrl_xon_thr);
2937 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XOFF_TX_TH, ctrl_xoff_thr);
2938 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 1);
2940 efx_writeo(efx, ®, FR_AZ_RX_CFG);
2943 /* This call performs hardware-specific global initialisation, such as
2944 * defining the descriptor cache sizes and number of RSS channels.
2945 * It does not set up any buffers, descriptor rings or event queues.
2947 int falcon_init_nic(struct efx_nic *efx)
2952 /* Use on-chip SRAM */
2953 efx_reado(efx, &temp, FR_AB_NIC_STAT);
2954 EFX_SET_OWORD_FIELD(temp, FRF_AB_ONCHIP_SRAM, 1);
2955 efx_writeo(efx, &temp, FR_AB_NIC_STAT);
2957 /* Set the source of the GMAC clock */
2958 if (falcon_rev(efx) == FALCON_REV_B0) {
2959 efx_reado(efx, &temp, FR_AB_GPIO_CTL);
2960 EFX_SET_OWORD_FIELD(temp, FRF_AB_USE_NIC_CLK, true);
2961 efx_writeo(efx, &temp, FR_AB_GPIO_CTL);
2964 rc = falcon_reset_sram(efx);
2968 /* Set positions of descriptor caches in SRAM. */
2969 EFX_POPULATE_OWORD_1(temp, FRF_AZ_SRM_TX_DC_BASE_ADR, TX_DC_BASE / 8);
2970 efx_writeo(efx, &temp, FR_AZ_SRM_TX_DC_CFG);
2971 EFX_POPULATE_OWORD_1(temp, FRF_AZ_SRM_RX_DC_BASE_ADR, RX_DC_BASE / 8);
2972 efx_writeo(efx, &temp, FR_AZ_SRM_RX_DC_CFG);
2974 /* Set TX descriptor cache size. */
2975 BUILD_BUG_ON(TX_DC_ENTRIES != (16 << TX_DC_ENTRIES_ORDER));
2976 EFX_POPULATE_OWORD_1(temp, FRF_AZ_TX_DC_SIZE, TX_DC_ENTRIES_ORDER);
2977 efx_writeo(efx, &temp, FR_AZ_TX_DC_CFG);
2979 /* Set RX descriptor cache size. Set low watermark to size-8, as
2980 * this allows most efficient prefetching.
2982 BUILD_BUG_ON(RX_DC_ENTRIES != (16 << RX_DC_ENTRIES_ORDER));
2983 EFX_POPULATE_OWORD_1(temp, FRF_AZ_RX_DC_SIZE, RX_DC_ENTRIES_ORDER);
2984 efx_writeo(efx, &temp, FR_AZ_RX_DC_CFG);
2985 EFX_POPULATE_OWORD_1(temp, FRF_AZ_RX_DC_PF_LWM, RX_DC_ENTRIES - 8);
2986 efx_writeo(efx, &temp, FR_AZ_RX_DC_PF_WM);
2988 /* Clear the parity enables on the TX data fifos as
2989 * they produce false parity errors because of timing issues
2991 if (EFX_WORKAROUND_5129(efx)) {
2992 efx_reado(efx, &temp, FR_AZ_CSR_SPARE);
2993 EFX_SET_OWORD_FIELD(temp, FRF_AB_MEM_PERR_EN_TX_DATA, 0);
2994 efx_writeo(efx, &temp, FR_AZ_CSR_SPARE);
2997 /* Enable all the genuinely fatal interrupts. (They are still
2998 * masked by the overall interrupt mask, controlled by
2999 * falcon_interrupts()).
3001 * Note: All other fatal interrupts are enabled
3003 EFX_POPULATE_OWORD_3(temp,
3004 FRF_AZ_ILL_ADR_INT_KER_EN, 1,
3005 FRF_AZ_RBUF_OWN_INT_KER_EN, 1,
3006 FRF_AZ_TBUF_OWN_INT_KER_EN, 1);
3007 EFX_INVERT_OWORD(temp);
3008 efx_writeo(efx, &temp, FR_AZ_FATAL_INTR_KER);
3010 if (EFX_WORKAROUND_7244(efx)) {
3011 efx_reado(efx, &temp, FR_BZ_RX_FILTER_CTL);
3012 EFX_SET_OWORD_FIELD(temp, FRF_BZ_UDP_FULL_SRCH_LIMIT, 8);
3013 EFX_SET_OWORD_FIELD(temp, FRF_BZ_UDP_WILD_SRCH_LIMIT, 8);
3014 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TCP_FULL_SRCH_LIMIT, 8);
3015 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TCP_WILD_SRCH_LIMIT, 8);
3016 efx_writeo(efx, &temp, FR_BZ_RX_FILTER_CTL);
3019 falcon_setup_rss_indir_table(efx);
3021 /* XXX This is documented only for Falcon A0/A1 */
3022 /* Setup RX. Wait for descriptor is broken and must
3023 * be disabled. RXDP recovery shouldn't be needed, but is.
3025 efx_reado(efx, &temp, FR_AA_RX_SELF_RST);
3026 EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_NODESC_WAIT_DIS, 1);
3027 EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_SELF_RST_EN, 1);
3028 if (EFX_WORKAROUND_5583(efx))
3029 EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_ISCSI_DIS, 1);
3030 efx_writeo(efx, &temp, FR_AA_RX_SELF_RST);
3032 /* Disable the ugly timer-based TX DMA backoff and allow TX DMA to be
3033 * controlled by the RX FIFO fill level. Set arbitration to one pkt/Q.
3035 efx_reado(efx, &temp, FR_AZ_TX_RESERVED);
3036 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_RX_SPACER, 0xfe);
3037 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_RX_SPACER_EN, 1);
3038 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_ONE_PKT_PER_Q, 1);
3039 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_PUSH_EN, 0);
3040 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_DIS_NON_IP_EV, 1);
3041 /* Enable SW_EV to inherit in char driver - assume harmless here */
3042 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_SOFT_EVT_EN, 1);
3043 /* Prefetch threshold 2 => fetch when descriptor cache half empty */
3044 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_PREF_THRESHOLD, 2);
3045 /* Squash TX of packets of 16 bytes or less */
3046 if (falcon_rev(efx) >= FALCON_REV_B0 && EFX_WORKAROUND_9141(efx))
3047 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TX_FLUSH_MIN_LEN_EN, 1);
3048 efx_writeo(efx, &temp, FR_AZ_TX_RESERVED);
3050 /* Do not enable TX_NO_EOP_DISC_EN, since it limits packets to 16
3051 * descriptors (which is bad).
3053 efx_reado(efx, &temp, FR_AZ_TX_CFG);
3054 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_NO_EOP_DISC_EN, 0);
3055 efx_writeo(efx, &temp, FR_AZ_TX_CFG);
3057 falcon_init_rx_cfg(efx);
3059 /* Set destination of both TX and RX Flush events */
3060 if (falcon_rev(efx) >= FALCON_REV_B0) {
3061 EFX_POPULATE_OWORD_1(temp, FRF_BZ_FLS_EVQ_ID, 0);
3062 efx_writeo(efx, &temp, FR_BZ_DP_CTRL);
3068 void falcon_remove_nic(struct efx_nic *efx)
3070 struct falcon_nic_data *nic_data = efx->nic_data;
3073 /* Remove I2C adapter and clear it in preparation for a retry */
3074 rc = i2c_del_adapter(&efx->i2c_adap);
3076 memset(&efx->i2c_adap, 0, sizeof(efx->i2c_adap));
3078 falcon_remove_spi_devices(efx);
3079 falcon_free_buffer(efx, &efx->irq_status);
3081 falcon_reset_hw(efx, RESET_TYPE_ALL);
3083 /* Release the second function after the reset */
3084 if (nic_data->pci_dev2) {
3085 pci_dev_put(nic_data->pci_dev2);
3086 nic_data->pci_dev2 = NULL;
3089 /* Tear down the private nic state */
3090 kfree(efx->nic_data);
3091 efx->nic_data = NULL;
3094 void falcon_update_nic_stats(struct efx_nic *efx)
3098 efx_reado(efx, &cnt, FR_AZ_RX_NODESC_DROP);
3099 efx->n_rx_nodesc_drop_cnt +=
3100 EFX_OWORD_FIELD(cnt, FRF_AB_RX_NODESC_DROP_CNT);
3103 /**************************************************************************
3105 * Revision-dependent attributes used by efx.c
3107 **************************************************************************
3110 struct efx_nic_type falcon_a_nic_type = {
3111 .mem_map_size = 0x20000,
3112 .txd_ptr_tbl_base = FR_AA_TX_DESC_PTR_TBL_KER,
3113 .rxd_ptr_tbl_base = FR_AA_RX_DESC_PTR_TBL_KER,
3114 .buf_tbl_base = FR_AA_BUF_FULL_TBL_KER,
3115 .evq_ptr_tbl_base = FR_AA_EVQ_PTR_TBL_KER,
3116 .evq_rptr_tbl_base = FR_AA_EVQ_RPTR_KER,
3117 .max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH),
3118 .rx_buffer_padding = 0x24,
3119 .max_interrupt_mode = EFX_INT_MODE_MSI,
3120 .phys_addr_channels = 4,
3123 struct efx_nic_type falcon_b_nic_type = {
3124 /* Map everything up to and including the RSS indirection
3125 * table. Don't map MSI-X table, MSI-X PBA since Linux
3126 * requires that they not be mapped. */
3127 .mem_map_size = (FR_BZ_RX_INDIRECTION_TBL +
3128 FR_BZ_RX_INDIRECTION_TBL_STEP *
3129 FR_BZ_RX_INDIRECTION_TBL_ROWS),
3130 .txd_ptr_tbl_base = FR_BZ_TX_DESC_PTR_TBL,
3131 .rxd_ptr_tbl_base = FR_BZ_RX_DESC_PTR_TBL,
3132 .buf_tbl_base = FR_BZ_BUF_FULL_TBL,
3133 .evq_ptr_tbl_base = FR_BZ_EVQ_PTR_TBL,
3134 .evq_rptr_tbl_base = FR_BZ_EVQ_RPTR,
3135 .max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH),
3136 .rx_buffer_padding = 0,
3137 .max_interrupt_mode = EFX_INT_MODE_MSIX,
3138 .phys_addr_channels = 32, /* Hardware limit is 64, but the legacy
3139 * interrupt handler only supports 32