drivers/net/sfc/falcon.c

   1 /****************************************************************************
   2  * Driver for Solarflare Solarstorm network controllers and boards
   3  * Copyright 2005-2006 Fen Systems Ltd.
   4  * Copyright 2006-2008 Solarflare Communications Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 as published
   8  * by the Free Software Foundation, incorporated herein by reference.
   9  */
  10
  11 #include <linux/bitops.h>
  12 #include <linux/delay.h>
  13 #include <linux/pci.h>
  14 #include <linux/module.h>
  15 #include <linux/seq_file.h>
  16 #include <linux/i2c.h>
  17 #include <linux/mii.h>
  18 #include "net_driver.h"
  19 #include "bitfield.h"
  20 #include "efx.h"
  21 #include "mac.h"
  22 #include "spi.h"
  23 #include "falcon.h"
  24 #include "regs.h"
  25 #include "io.h"
  26 #include "mdio_10g.h"
  27 #include "phy.h"
  28 #include "workarounds.h"
  29
  30 /* Hardware control for SFC4000 (aka Falcon). */
  31
  32 /**************************************************************************
  33  *
  34  * Configurable values
  35  *
  36  **************************************************************************
  37  */
  38
  39 static int disable_dma_stats;
  40
  41 /* This is set to 16 for a good reason.  In summary, if larger than
  42  * 16, the descriptor cache holds more than a default socket
  43  * buffer's worth of packets (for UDP we can only have at most one
  44  * socket buffer's worth outstanding).  This combined with the fact
  45  * that we only get 1 TX event per descriptor cache means the NIC
  46  * goes idle.
  47  */
  48 #define TX_DC_ENTRIES 16
  49 #define TX_DC_ENTRIES_ORDER 1
  50 #define TX_DC_BASE 0x130000
  51
  52 #define RX_DC_ENTRIES 64
  53 #define RX_DC_ENTRIES_ORDER 3
  54 #define RX_DC_BASE 0x100000
  55
  56 static const unsigned int
  57 /* "Large" EEPROM device: Atmel AT25640 or similar
  58  * 8 KB, 16-bit address, 32 B write block */
  59 large_eeprom_type = ((13 << SPI_DEV_TYPE_SIZE_LBN)
  60                      | (2 << SPI_DEV_TYPE_ADDR_LEN_LBN)
  61                      | (5 << SPI_DEV_TYPE_BLOCK_SIZE_LBN)),
  62 /* Default flash device: Atmel AT25F1024
  63  * 128 KB, 24-bit address, 32 KB erase block, 256 B write block */
  64 default_flash_type = ((17 << SPI_DEV_TYPE_SIZE_LBN)
  65                       | (3 << SPI_DEV_TYPE_ADDR_LEN_LBN)
  66                       | (0x52 << SPI_DEV_TYPE_ERASE_CMD_LBN)
  67                       | (15 << SPI_DEV_TYPE_ERASE_SIZE_LBN)
  68                       | (8 << SPI_DEV_TYPE_BLOCK_SIZE_LBN));
  69
  70 /* RX FIFO XOFF watermark
  71  *
  72  * When the amount of the RX FIFO increases used increases past this
  73  * watermark send XOFF. Only used if RX flow control is enabled (ethtool -A)
  74  * This also has an effect on RX/TX arbitration
  75  */
  76 static int rx_xoff_thresh_bytes = -1;
  77 module_param(rx_xoff_thresh_bytes, int, 0644);
  78 MODULE_PARM_DESC(rx_xoff_thresh_bytes, "RX fifo XOFF threshold");
  79
  80 /* RX FIFO XON watermark
  81  *
  82  * When the amount of the RX FIFO used decreases below this
  83  * watermark send XON. Only used if TX flow control is enabled (ethtool -A)
  84  * This also has an effect on RX/TX arbitration
  85  */
  86 static int rx_xon_thresh_bytes = -1;
  87 module_param(rx_xon_thresh_bytes, int, 0644);
  88 MODULE_PARM_DESC(rx_xon_thresh_bytes, "RX fifo XON threshold");
  89
  90 /* If FALCON_MAX_INT_ERRORS internal errors occur within
  91  * FALCON_INT_ERROR_EXPIRE seconds, we consider the NIC broken and
  92  * disable it.
  93  */
  94 #define FALCON_INT_ERROR_EXPIRE 3600
  95 #define FALCON_MAX_INT_ERRORS 5
  96
  97 /* We poll for events every FLUSH_INTERVAL ms, and check FLUSH_POLL_COUNT times
  98  */
  99 #define FALCON_FLUSH_INTERVAL 10
 100 #define FALCON_FLUSH_POLL_COUNT 100
 101
 102 /**************************************************************************
 103  *
 104  * Falcon constants
 105  *
 106  **************************************************************************
 107  */
 108
 109 /* Size and alignment of special buffers (4KB) */
 110 #define FALCON_BUF_SIZE 4096
 111
 112 /* Depth of RX flush request fifo */
 113 #define FALCON_RX_FLUSH_COUNT 4
 114
 115 #define FALCON_IS_DUAL_FUNC(efx)                \
 116         (falcon_rev(efx) < FALCON_REV_B0)
 117
 118 /**************************************************************************
 119  *
 120  * Falcon hardware access
 121  *
 122  **************************************************************************/
 123
 124 static inline void falcon_write_buf_tbl(struct efx_nic *efx, efx_qword_t *value,
 125                                         unsigned int index)
 126 {
 127         efx_sram_writeq(efx, efx->membase + efx->type->buf_tbl_base,
 128                         value, index);
 129 }
 130
 131 /* Read the current event from the event queue */
 132 static inline efx_qword_t *falcon_event(struct efx_channel *channel,
 133                                         unsigned int index)
 134 {
 135         return (((efx_qword_t *) (channel->eventq.addr)) + index);
 136 }
 137
 138 /* See if an event is present
 139  *
 140  * We check both the high and low dword of the event for all ones.  We
 141  * wrote all ones when we cleared the event, and no valid event can
 142  * have all ones in either its high or low dwords.  This approach is
 143  * robust against reordering.
 144  *
 145  * Note that using a single 64-bit comparison is incorrect; even
 146  * though the CPU read will be atomic, the DMA write may not be.
 147  */
 148 static inline int falcon_event_present(efx_qword_t *event)
 149 {
 150         return (!(EFX_DWORD_IS_ALL_ONES(event->dword[0]) |
 151                   EFX_DWORD_IS_ALL_ONES(event->dword[1])));
 152 }
 153
 154 /**************************************************************************
 155  *
 156  * I2C bus - this is a bit-bashing interface using GPIO pins
 157  * Note that it uses the output enables to tristate the outputs
 158  * SDA is the data pin and SCL is the clock
 159  *
 160  **************************************************************************
 161  */
 162 static void falcon_setsda(void *data, int state)
 163 {
 164         struct efx_nic *efx = (struct efx_nic *)data;
 165         efx_oword_t reg;
 166
 167         efx_reado(efx, &reg, FR_AB_GPIO_CTL);
 168         EFX_SET_OWORD_FIELD(reg, FRF_AB_GPIO3_OEN, !state);
 169         efx_writeo(efx, &reg, FR_AB_GPIO_CTL);
 170 }
 171
 172 static void falcon_setscl(void *data, int state)
 173 {
 174         struct efx_nic *efx = (struct efx_nic *)data;
 175         efx_oword_t reg;
 176
 177         efx_reado(efx, &reg, FR_AB_GPIO_CTL);
 178         EFX_SET_OWORD_FIELD(reg, FRF_AB_GPIO0_OEN, !state);
 179         efx_writeo(efx, &reg, FR_AB_GPIO_CTL);
 180 }
 181
 182 static int falcon_getsda(void *data)
 183 {
 184         struct efx_nic *efx = (struct efx_nic *)data;
 185         efx_oword_t reg;
 186
 187         efx_reado(efx, &reg, FR_AB_GPIO_CTL);
 188         return EFX_OWORD_FIELD(reg, FRF_AB_GPIO3_IN);
 189 }
 190
 191 static int falcon_getscl(void *data)
 192 {
 193         struct efx_nic *efx = (struct efx_nic *)data;
 194         efx_oword_t reg;
 195
 196         efx_reado(efx, &reg, FR_AB_GPIO_CTL);
 197         return EFX_OWORD_FIELD(reg, FRF_AB_GPIO0_IN);
 198 }
 199
 200 static struct i2c_algo_bit_data falcon_i2c_bit_operations = {
 201         .setsda         = falcon_setsda,
 202         .setscl         = falcon_setscl,
 203         .getsda         = falcon_getsda,
 204         .getscl         = falcon_getscl,
 205         .udelay         = 5,
 206         /* Wait up to 50 ms for slave to let us pull SCL high */
 207         .timeout        = DIV_ROUND_UP(HZ, 20),
 208 };
 209
 210 /**************************************************************************
 211  *
 212  * Falcon special buffer handling
 213  * Special buffers are used for event queues and the TX and RX
 214  * descriptor rings.
 215  *
 216  *************************************************************************/
 217
 218 /*
 219  * Initialise a Falcon special buffer
 220  *
 221  * This will define a buffer (previously allocated via
 222  * falcon_alloc_special_buffer()) in Falcon's buffer table, allowing
 223  * it to be used for event queues, descriptor rings etc.
 224  */
 225 static void
 226 falcon_init_special_buffer(struct efx_nic *efx,
 227                            struct efx_special_buffer *buffer)
 228 {
 229         efx_qword_t buf_desc;
 230         int index;
 231         dma_addr_t dma_addr;
 232         int i;
 233
 234         EFX_BUG_ON_PARANOID(!buffer->addr);
 235
 236         /* Write buffer descriptors to NIC */
 237         for (i = 0; i < buffer->entries; i++) {
 238                 index = buffer->index + i;
 239                 dma_addr = buffer->dma_addr + (i * 4096);
 240                 EFX_LOG(efx, "mapping special buffer %d at %llx\n",
 241                         index, (unsigned long long)dma_addr);
 242                 EFX_POPULATE_QWORD_3(buf_desc,
 243                                      FRF_AZ_BUF_ADR_REGION, 0,
 244                                      FRF_AZ_BUF_ADR_FBUF, dma_addr >> 12,
 245                                      FRF_AZ_BUF_OWNER_ID_FBUF, 0);
 246                 falcon_write_buf_tbl(efx, &buf_desc, index);
 247         }
 248 }
 249
 250 /* Unmaps a buffer from Falcon and clears the buffer table entries */
 251 static void
 252 falcon_fini_special_buffer(struct efx_nic *efx,
 253                            struct efx_special_buffer *buffer)
 254 {
 255         efx_oword_t buf_tbl_upd;
 256         unsigned int start = buffer->index;
 257         unsigned int end = (buffer->index + buffer->entries - 1);
 258
 259         if (!buffer->entries)
 260                 return;
 261
 262         EFX_LOG(efx, "unmapping special buffers %d-%d\n",
 263                 buffer->index, buffer->index + buffer->entries - 1);
 264
 265         EFX_POPULATE_OWORD_4(buf_tbl_upd,
 266                              FRF_AZ_BUF_UPD_CMD, 0,
 267                              FRF_AZ_BUF_CLR_CMD, 1,
 268                              FRF_AZ_BUF_CLR_END_ID, end,
 269                              FRF_AZ_BUF_CLR_START_ID, start);
 270         efx_writeo(efx, &buf_tbl_upd, FR_AZ_BUF_TBL_UPD);
 271 }
 272
 273 /*
 274  * Allocate a new Falcon special buffer
 275  *
 276  * This allocates memory for a new buffer, clears it and allocates a
 277  * new buffer ID range.  It does not write into Falcon's buffer table.
 278  *
 279  * This call will allocate 4KB buffers, since Falcon can't use 8KB
 280  * buffers for event queues and descriptor rings.
 281  */
 282 static int falcon_alloc_special_buffer(struct efx_nic *efx,
 283                                        struct efx_special_buffer *buffer,
 284                                        unsigned int len)
 285 {
 286         len = ALIGN(len, FALCON_BUF_SIZE);
 287
 288         buffer->addr = pci_alloc_consistent(efx->pci_dev, len,
 289                                             &buffer->dma_addr);
 290         if (!buffer->addr)
 291                 return -ENOMEM;
 292         buffer->len = len;
 293         buffer->entries = len / FALCON_BUF_SIZE;
 294         BUG_ON(buffer->dma_addr & (FALCON_BUF_SIZE - 1));
 295
 296         /* All zeros is a potentially valid event so memset to 0xff */
 297         memset(buffer->addr, 0xff, len);
 298
 299         /* Select new buffer ID */
 300         buffer->index = efx->next_buffer_table;
 301         efx->next_buffer_table += buffer->entries;
 302
 303         EFX_LOG(efx, "allocating special buffers %d-%d at %llx+%x "
 304                 "(virt %p phys %llx)\n", buffer->index,
 305                 buffer->index + buffer->entries - 1,
 306                 (u64)buffer->dma_addr, len,
 307                 buffer->addr, (u64)virt_to_phys(buffer->addr));
 308
 309         return 0;
 310 }
 311
 312 static void falcon_free_special_buffer(struct efx_nic *efx,
 313                                        struct efx_special_buffer *buffer)
 314 {
 315         if (!buffer->addr)
 316                 return;
 317
 318         EFX_LOG(efx, "deallocating special buffers %d-%d at %llx+%x "
 319                 "(virt %p phys %llx)\n", buffer->index,
 320                 buffer->index + buffer->entries - 1,
 321                 (u64)buffer->dma_addr, buffer->len,
 322                 buffer->addr, (u64)virt_to_phys(buffer->addr));
 323
 324         pci_free_consistent(efx->pci_dev, buffer->len, buffer->addr,
 325                             buffer->dma_addr);
 326         buffer->addr = NULL;
 327         buffer->entries = 0;
 328 }
 329
 330 /**************************************************************************
 331  *
 332  * Falcon generic buffer handling
 333  * These buffers are used for interrupt status and MAC stats
 334  *
 335  **************************************************************************/
 336
 337 static int falcon_alloc_buffer(struct efx_nic *efx,
 338                                struct efx_buffer *buffer, unsigned int len)
 339 {
 340         buffer->addr = pci_alloc_consistent(efx->pci_dev, len,
 341                                             &buffer->dma_addr);
 342         if (!buffer->addr)
 343                 return -ENOMEM;
 344         buffer->len = len;
 345         memset(buffer->addr, 0, len);
 346         return 0;
 347 }
 348
 349 static void falcon_free_buffer(struct efx_nic *efx, struct efx_buffer *buffer)
 350 {
 351         if (buffer->addr) {
 352                 pci_free_consistent(efx->pci_dev, buffer->len,
 353                                     buffer->addr, buffer->dma_addr);
 354                 buffer->addr = NULL;
 355         }
 356 }
 357
 358 /**************************************************************************
 359  *
 360  * Falcon TX path
 361  *
 362  **************************************************************************/
 363
 364 /* Returns a pointer to the specified transmit descriptor in the TX
 365  * descriptor queue belonging to the specified channel.
 366  */
 367 static inline efx_qword_t *falcon_tx_desc(struct efx_tx_queue *tx_queue,
 368                                                unsigned int index)
 369 {
 370         return (((efx_qword_t *) (tx_queue->txd.addr)) + index);
 371 }
 372
 373 /* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */
 374 static inline void falcon_notify_tx_desc(struct efx_tx_queue *tx_queue)
 375 {
 376         unsigned write_ptr;
 377         efx_dword_t reg;
 378
 379         write_ptr = tx_queue->write_count & EFX_TXQ_MASK;
 380         EFX_POPULATE_DWORD_1(reg, FRF_AZ_TX_DESC_WPTR_DWORD, write_ptr);
 381         efx_writed_page(tx_queue->efx, &reg,
 382                         FR_AZ_TX_DESC_UPD_DWORD_P0, tx_queue->queue);
 383 }
 384
 385
 386 /* For each entry inserted into the software descriptor ring, create a
 387  * descriptor in the hardware TX descriptor ring (in host memory), and
 388  * write a doorbell.
 389  */
 390 void falcon_push_buffers(struct efx_tx_queue *tx_queue)
 391 {
 392
 393         struct efx_tx_buffer *buffer;
 394         efx_qword_t *txd;
 395         unsigned write_ptr;
 396
 397         BUG_ON(tx_queue->write_count == tx_queue->insert_count);
 398
 399         do {
 400                 write_ptr = tx_queue->write_count & EFX_TXQ_MASK;
 401                 buffer = &tx_queue->buffer[write_ptr];
 402                 txd = falcon_tx_desc(tx_queue, write_ptr);
 403                 ++tx_queue->write_count;
 404
 405                 /* Create TX descriptor ring entry */
 406                 EFX_POPULATE_QWORD_4(*txd,
 407                                      FSF_AZ_TX_KER_CONT, buffer->continuation,
 408                                      FSF_AZ_TX_KER_BYTE_COUNT, buffer->len,
 409                                      FSF_AZ_TX_KER_BUF_REGION, 0,
 410                                      FSF_AZ_TX_KER_BUF_ADDR, buffer->dma_addr);
 411         } while (tx_queue->write_count != tx_queue->insert_count);
 412
 413         wmb(); /* Ensure descriptors are written before they are fetched */
 414         falcon_notify_tx_desc(tx_queue);
 415 }
 416
 417 /* Allocate hardware resources for a TX queue */
 418 int falcon_probe_tx(struct efx_tx_queue *tx_queue)
 419 {
 420         struct efx_nic *efx = tx_queue->efx;
 421         BUILD_BUG_ON(EFX_TXQ_SIZE < 512 || EFX_TXQ_SIZE > 4096 ||
 422                      EFX_TXQ_SIZE & EFX_TXQ_MASK);
 423         return falcon_alloc_special_buffer(efx, &tx_queue->txd,
 424                                            EFX_TXQ_SIZE * sizeof(efx_qword_t));
 425 }
 426
 427 void falcon_init_tx(struct efx_tx_queue *tx_queue)
 428 {
 429         efx_oword_t tx_desc_ptr;
 430         struct efx_nic *efx = tx_queue->efx;
 431
 432         tx_queue->flushed = FLUSH_NONE;
 433
 434         /* Pin TX descriptor ring */
 435         falcon_init_special_buffer(efx, &tx_queue->txd);
 436
 437         /* Push TX descriptor ring to card */
 438         EFX_POPULATE_OWORD_10(tx_desc_ptr,
 439                               FRF_AZ_TX_DESCQ_EN, 1,
 440                               FRF_AZ_TX_ISCSI_DDIG_EN, 0,
 441                               FRF_AZ_TX_ISCSI_HDIG_EN, 0,
 442                               FRF_AZ_TX_DESCQ_BUF_BASE_ID, tx_queue->txd.index,
 443                               FRF_AZ_TX_DESCQ_EVQ_ID,
 444                               tx_queue->channel->channel,
 445                               FRF_AZ_TX_DESCQ_OWNER_ID, 0,
 446                               FRF_AZ_TX_DESCQ_LABEL, tx_queue->queue,
 447                               FRF_AZ_TX_DESCQ_SIZE,
 448                               __ffs(tx_queue->txd.entries),
 449                               FRF_AZ_TX_DESCQ_TYPE, 0,
 450                               FRF_BZ_TX_NON_IP_DROP_DIS, 1);
 451
 452         if (falcon_rev(efx) >= FALCON_REV_B0) {
 453                 int csum = tx_queue->queue == EFX_TX_QUEUE_OFFLOAD_CSUM;
 454                 EFX_SET_OWORD_FIELD(tx_desc_ptr, FRF_BZ_TX_IP_CHKSM_DIS, !csum);
 455                 EFX_SET_OWORD_FIELD(tx_desc_ptr, FRF_BZ_TX_TCP_CHKSM_DIS,
 456                                     !csum);
 457         }
 458
 459         efx_writeo_table(efx, &tx_desc_ptr, efx->type->txd_ptr_tbl_base,
 460                          tx_queue->queue);
 461
 462         if (falcon_rev(efx) < FALCON_REV_B0) {
 463                 efx_oword_t reg;
 464
 465                 /* Only 128 bits in this register */
 466                 BUILD_BUG_ON(EFX_TX_QUEUE_COUNT >= 128);
 467
 468                 efx_reado(efx, &reg, FR_AA_TX_CHKSM_CFG);
 469                 if (tx_queue->queue == EFX_TX_QUEUE_OFFLOAD_CSUM)
 470                         clear_bit_le(tx_queue->queue, (void *)&reg);
 471                 else
 472                         set_bit_le(tx_queue->queue, (void *)&reg);
 473                 efx_writeo(efx, &reg, FR_AA_TX_CHKSM_CFG);
 474         }
 475 }
 476
 477 static void falcon_flush_tx_queue(struct efx_tx_queue *tx_queue)
 478 {
 479         struct efx_nic *efx = tx_queue->efx;
 480         efx_oword_t tx_flush_descq;
 481
 482         tx_queue->flushed = FLUSH_PENDING;
 483
 484         /* Post a flush command */
 485         EFX_POPULATE_OWORD_2(tx_flush_descq,
 486                              FRF_AZ_TX_FLUSH_DESCQ_CMD, 1,
 487                              FRF_AZ_TX_FLUSH_DESCQ, tx_queue->queue);
 488         efx_writeo(efx, &tx_flush_descq, FR_AZ_TX_FLUSH_DESCQ);
 489 }
 490
 491 void falcon_fini_tx(struct efx_tx_queue *tx_queue)
 492 {
 493         struct efx_nic *efx = tx_queue->efx;
 494         efx_oword_t tx_desc_ptr;
 495
 496         /* The queue should have been flushed */
 497         WARN_ON(tx_queue->flushed != FLUSH_DONE);
 498
 499         /* Remove TX descriptor ring from card */
 500         EFX_ZERO_OWORD(tx_desc_ptr);
 501         efx_writeo_table(efx, &tx_desc_ptr, efx->type->txd_ptr_tbl_base,
 502                          tx_queue->queue);
 503
 504         /* Unpin TX descriptor ring */
 505         falcon_fini_special_buffer(efx, &tx_queue->txd);
 506 }
 507
 508 /* Free buffers backing TX queue */
 509 void falcon_remove_tx(struct efx_tx_queue *tx_queue)
 510 {
 511         falcon_free_special_buffer(tx_queue->efx, &tx_queue->txd);
 512 }
 513
 514 /**************************************************************************
 515  *
 516  * Falcon RX path
 517  *
 518  **************************************************************************/
 519
 520 /* Returns a pointer to the specified descriptor in the RX descriptor queue */
 521 static inline efx_qword_t *falcon_rx_desc(struct efx_rx_queue *rx_queue,
 522                                                unsigned int index)
 523 {
 524         return (((efx_qword_t *) (rx_queue->rxd.addr)) + index);
 525 }
 526
 527 /* This creates an entry in the RX descriptor queue */
 528 static inline void falcon_build_rx_desc(struct efx_rx_queue *rx_queue,
 529                                         unsigned index)
 530 {
 531         struct efx_rx_buffer *rx_buf;
 532         efx_qword_t *rxd;
 533
 534         rxd = falcon_rx_desc(rx_queue, index);
 535         rx_buf = efx_rx_buffer(rx_queue, index);
 536         EFX_POPULATE_QWORD_3(*rxd,
 537                              FSF_AZ_RX_KER_BUF_SIZE,
 538                              rx_buf->len -
 539                              rx_queue->efx->type->rx_buffer_padding,
 540                              FSF_AZ_RX_KER_BUF_REGION, 0,
 541                              FSF_AZ_RX_KER_BUF_ADDR, rx_buf->dma_addr);
 542 }
 543
 544 /* This writes to the RX_DESC_WPTR register for the specified receive
 545  * descriptor ring.
 546  */
 547 void falcon_notify_rx_desc(struct efx_rx_queue *rx_queue)
 548 {
 549         efx_dword_t reg;
 550         unsigned write_ptr;
 551
 552         while (rx_queue->notified_count != rx_queue->added_count) {
 553                 falcon_build_rx_desc(rx_queue,
 554                                      rx_queue->notified_count &
 555                                      EFX_RXQ_MASK);
 556                 ++rx_queue->notified_count;
 557         }
 558
 559         wmb();
 560         write_ptr = rx_queue->added_count & EFX_RXQ_MASK;
 561         EFX_POPULATE_DWORD_1(reg, FRF_AZ_RX_DESC_WPTR_DWORD, write_ptr);
 562         efx_writed_page(rx_queue->efx, &reg,
 563                         FR_AZ_RX_DESC_UPD_DWORD_P0, rx_queue->queue);
 564 }
 565
 566 int falcon_probe_rx(struct efx_rx_queue *rx_queue)
 567 {
 568         struct efx_nic *efx = rx_queue->efx;
 569         BUILD_BUG_ON(EFX_RXQ_SIZE < 512 || EFX_RXQ_SIZE > 4096 ||
 570                      EFX_RXQ_SIZE & EFX_RXQ_MASK);
 571         return falcon_alloc_special_buffer(efx, &rx_queue->rxd,
 572                                            EFX_RXQ_SIZE * sizeof(efx_qword_t));
 573 }
 574
 575 void falcon_init_rx(struct efx_rx_queue *rx_queue)
 576 {
 577         efx_oword_t rx_desc_ptr;
 578         struct efx_nic *efx = rx_queue->efx;
 579         bool is_b0 = falcon_rev(efx) >= FALCON_REV_B0;
 580         bool iscsi_digest_en = is_b0;
 581
 582         EFX_LOG(efx, "RX queue %d ring in special buffers %d-%d\n",
 583                 rx_queue->queue, rx_queue->rxd.index,
 584                 rx_queue->rxd.index + rx_queue->rxd.entries - 1);
 585
 586         rx_queue->flushed = FLUSH_NONE;
 587
 588         /* Pin RX descriptor ring */
 589         falcon_init_special_buffer(efx, &rx_queue->rxd);
 590
 591         /* Push RX descriptor ring to card */
 592         EFX_POPULATE_OWORD_10(rx_desc_ptr,
 593                               FRF_AZ_RX_ISCSI_DDIG_EN, iscsi_digest_en,
 594                               FRF_AZ_RX_ISCSI_HDIG_EN, iscsi_digest_en,
 595                               FRF_AZ_RX_DESCQ_BUF_BASE_ID, rx_queue->rxd.index,
 596                               FRF_AZ_RX_DESCQ_EVQ_ID,
 597                               rx_queue->channel->channel,
 598                               FRF_AZ_RX_DESCQ_OWNER_ID, 0,
 599                               FRF_AZ_RX_DESCQ_LABEL, rx_queue->queue,
 600                               FRF_AZ_RX_DESCQ_SIZE,
 601                               __ffs(rx_queue->rxd.entries),
 602                               FRF_AZ_RX_DESCQ_TYPE, 0 /* kernel queue */ ,
 603                               /* For >=B0 this is scatter so disable */
 604                               FRF_AZ_RX_DESCQ_JUMBO, !is_b0,
 605                               FRF_AZ_RX_DESCQ_EN, 1);
 606         efx_writeo_table(efx, &rx_desc_ptr, efx->type->rxd_ptr_tbl_base,
 607                          rx_queue->queue);
 608 }
 609
 610 static void falcon_flush_rx_queue(struct efx_rx_queue *rx_queue)
 611 {
 612         struct efx_nic *efx = rx_queue->efx;
 613         efx_oword_t rx_flush_descq;
 614
 615         rx_queue->flushed = FLUSH_PENDING;
 616
 617         /* Post a flush command */
 618         EFX_POPULATE_OWORD_2(rx_flush_descq,
 619                              FRF_AZ_RX_FLUSH_DESCQ_CMD, 1,
 620                              FRF_AZ_RX_FLUSH_DESCQ, rx_queue->queue);
 621         efx_writeo(efx, &rx_flush_descq, FR_AZ_RX_FLUSH_DESCQ);
 622 }
 623
 624 void falcon_fini_rx(struct efx_rx_queue *rx_queue)
 625 {
 626         efx_oword_t rx_desc_ptr;
 627         struct efx_nic *efx = rx_queue->efx;
 628
 629         /* The queue should already have been flushed */
 630         WARN_ON(rx_queue->flushed != FLUSH_DONE);
 631
 632         /* Remove RX descriptor ring from card */
 633         EFX_ZERO_OWORD(rx_desc_ptr);
 634         efx_writeo_table(efx, &rx_desc_ptr, efx->type->rxd_ptr_tbl_base,
 635                          rx_queue->queue);
 636
 637         /* Unpin RX descriptor ring */
 638         falcon_fini_special_buffer(efx, &rx_queue->rxd);
 639 }
 640
 641 /* Free buffers backing RX queue */
 642 void falcon_remove_rx(struct efx_rx_queue *rx_queue)
 643 {
 644         falcon_free_special_buffer(rx_queue->efx, &rx_queue->rxd);
 645 }
 646
 647 /**************************************************************************
 648  *
 649  * Falcon event queue processing
 650  * Event queues are processed by per-channel tasklets.
 651  *
 652  **************************************************************************/
 653
 654 /* Update a channel's event queue's read pointer (RPTR) register
 655  *
 656  * This writes the EVQ_RPTR_REG register for the specified channel's
 657  * event queue.
 658  *
 659  * Note that EVQ_RPTR_REG contains the index of the "last read" event,
 660  * whereas channel->eventq_read_ptr contains the index of the "next to
 661  * read" event.
 662  */
 663 void falcon_eventq_read_ack(struct efx_channel *channel)
 664 {
 665         efx_dword_t reg;
 666         struct efx_nic *efx = channel->efx;
 667
 668         EFX_POPULATE_DWORD_1(reg, FRF_AZ_EVQ_RPTR, channel->eventq_read_ptr);
 669         efx_writed_table(efx, &reg, efx->type->evq_rptr_tbl_base,
 670                             channel->channel);
 671 }
 672
 673 /* Use HW to insert a SW defined event */
 674 void falcon_generate_event(struct efx_channel *channel, efx_qword_t *event)
 675 {
 676         efx_oword_t drv_ev_reg;
 677
 678         BUILD_BUG_ON(FRF_AZ_DRV_EV_DATA_LBN != 0 ||
 679                      FRF_AZ_DRV_EV_DATA_WIDTH != 64);
 680         drv_ev_reg.u32[0] = event->u32[0];
 681         drv_ev_reg.u32[1] = event->u32[1];
 682         drv_ev_reg.u32[2] = 0;
 683         drv_ev_reg.u32[3] = 0;
 684         EFX_SET_OWORD_FIELD(drv_ev_reg, FRF_AZ_DRV_EV_QID, channel->channel);
 685         efx_writeo(channel->efx, &drv_ev_reg, FR_AZ_DRV_EV);
 686 }
 687
 688 /* Handle a transmit completion event
 689  *
 690  * Falcon batches TX completion events; the message we receive is of
 691  * the form "complete all TX events up to this index".
 692  */
 693 static void falcon_handle_tx_event(struct efx_channel *channel,
 694                                    efx_qword_t *event)
 695 {
 696         unsigned int tx_ev_desc_ptr;
 697         unsigned int tx_ev_q_label;
 698         struct efx_tx_queue *tx_queue;
 699         struct efx_nic *efx = channel->efx;
 700
 701         if (likely(EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_COMP))) {
 702                 /* Transmit completion */
 703                 tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_DESC_PTR);
 704                 tx_ev_q_label = EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_Q_LABEL);
 705                 tx_queue = &efx->tx_queue[tx_ev_q_label];
 706                 channel->irq_mod_score +=
 707                         (tx_ev_desc_ptr - tx_queue->read_count) &
 708                         EFX_TXQ_MASK;
 709                 efx_xmit_done(tx_queue, tx_ev_desc_ptr);
 710         } else if (EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_WQ_FF_FULL)) {
 711                 /* Rewrite the FIFO write pointer */
 712                 tx_ev_q_label = EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_Q_LABEL);
 713                 tx_queue = &efx->tx_queue[tx_ev_q_label];
 714
 715                 if (efx_dev_registered(efx))
 716                         netif_tx_lock(efx->net_dev);
 717                 falcon_notify_tx_desc(tx_queue);
 718                 if (efx_dev_registered(efx))
 719                         netif_tx_unlock(efx->net_dev);
 720         } else if (EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_PKT_ERR) &&
 721                    EFX_WORKAROUND_10727(efx)) {
 722                 efx_schedule_reset(efx, RESET_TYPE_TX_DESC_FETCH);
 723         } else {
 724                 EFX_ERR(efx, "channel %d unexpected TX event "
 725                         EFX_QWORD_FMT"\n", channel->channel,
 726                         EFX_QWORD_VAL(*event));
 727         }
 728 }
 729
 730 /* Detect errors included in the rx_evt_pkt_ok bit. */
 731 static void falcon_handle_rx_not_ok(struct efx_rx_queue *rx_queue,
 732                                     const efx_qword_t *event,
 733                                     bool *rx_ev_pkt_ok,
 734                                     bool *discard)
 735 {
 736         struct efx_nic *efx = rx_queue->efx;
 737         bool rx_ev_buf_owner_id_err, rx_ev_ip_hdr_chksum_err;
 738         bool rx_ev_tcp_udp_chksum_err, rx_ev_eth_crc_err;
 739         bool rx_ev_frm_trunc, rx_ev_drib_nib, rx_ev_tobe_disc;
 740         bool rx_ev_other_err, rx_ev_pause_frm;
 741         bool rx_ev_ip_frag_err, rx_ev_hdr_type, rx_ev_mcast_pkt;
 742         unsigned rx_ev_pkt_type;
 743
 744         rx_ev_hdr_type = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_HDR_TYPE);
 745         rx_ev_mcast_pkt = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_MCAST_PKT);
 746         rx_ev_tobe_disc = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_TOBE_DISC);
 747         rx_ev_pkt_type = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_PKT_TYPE);
 748         rx_ev_buf_owner_id_err = EFX_QWORD_FIELD(*event,
 749                                                  FSF_AZ_RX_EV_BUF_OWNER_ID_ERR);
 750         rx_ev_ip_frag_err = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_IP_FRAG_ERR);
 751         rx_ev_ip_hdr_chksum_err = EFX_QWORD_FIELD(*event,
 752                                                   FSF_AZ_RX_EV_IP_HDR_CHKSUM_ERR);
 753         rx_ev_tcp_udp_chksum_err = EFX_QWORD_FIELD(*event,
 754                                                    FSF_AZ_RX_EV_TCP_UDP_CHKSUM_ERR);
 755         rx_ev_eth_crc_err = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_ETH_CRC_ERR);
 756         rx_ev_frm_trunc = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_FRM_TRUNC);
 757         rx_ev_drib_nib = ((falcon_rev(efx) >= FALCON_REV_B0) ?
 758                           0 : EFX_QWORD_FIELD(*event, FSF_AA_RX_EV_DRIB_NIB));
 759         rx_ev_pause_frm = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_PAUSE_FRM_ERR);
 760
 761         /* Every error apart from tobe_disc and pause_frm */
 762         rx_ev_other_err = (rx_ev_drib_nib | rx_ev_tcp_udp_chksum_err |
 763                            rx_ev_buf_owner_id_err | rx_ev_eth_crc_err |
 764                            rx_ev_frm_trunc | rx_ev_ip_hdr_chksum_err);
 765
 766         /* Count errors that are not in MAC stats.  Ignore expected
 767          * checksum errors during self-test. */
 768         if (rx_ev_frm_trunc)
 769                 ++rx_queue->channel->n_rx_frm_trunc;
 770         else if (rx_ev_tobe_disc)
 771                 ++rx_queue->channel->n_rx_tobe_disc;
 772         else if (!efx->loopback_selftest) {
 773                 if (rx_ev_ip_hdr_chksum_err)
 774                         ++rx_queue->channel->n_rx_ip_hdr_chksum_err;
 775                 else if (rx_ev_tcp_udp_chksum_err)
 776                         ++rx_queue->channel->n_rx_tcp_udp_chksum_err;
 777         }
 778         if (rx_ev_ip_frag_err)
 779                 ++rx_queue->channel->n_rx_ip_frag_err;
 780
 781         /* The frame must be discarded if any of these are true. */
 782         *discard = (rx_ev_eth_crc_err | rx_ev_frm_trunc | rx_ev_drib_nib |
 783                     rx_ev_tobe_disc | rx_ev_pause_frm);
 784
 785         /* TOBE_DISC is expected on unicast mismatches; don't print out an
 786          * error message.  FRM_TRUNC indicates RXDP dropped the packet due
 787          * to a FIFO overflow.
 788          */
 789 #ifdef EFX_ENABLE_DEBUG
 790         if (rx_ev_other_err) {
 791                 EFX_INFO_RL(efx, " RX queue %d unexpected RX event "
 792                             EFX_QWORD_FMT "%s%s%s%s%s%s%s%s\n",
 793                             rx_queue->queue, EFX_QWORD_VAL(*event),
 794                             rx_ev_buf_owner_id_err ? " [OWNER_ID_ERR]" : "",
 795                             rx_ev_ip_hdr_chksum_err ?
 796                             " [IP_HDR_CHKSUM_ERR]" : "",
 797                             rx_ev_tcp_udp_chksum_err ?
 798                             " [TCP_UDP_CHKSUM_ERR]" : "",
 799                             rx_ev_eth_crc_err ? " [ETH_CRC_ERR]" : "",
 800                             rx_ev_frm_trunc ? " [FRM_TRUNC]" : "",
 801                             rx_ev_drib_nib ? " [DRIB_NIB]" : "",
 802                             rx_ev_tobe_disc ? " [TOBE_DISC]" : "",
 803                             rx_ev_pause_frm ? " [PAUSE]" : "");
 804         }
 805 #endif
 806 }
 807
 808 /* Handle receive events that are not in-order. */
 809 static void falcon_handle_rx_bad_index(struct efx_rx_queue *rx_queue,
 810                                        unsigned index)
 811 {
 812         struct efx_nic *efx = rx_queue->efx;
 813         unsigned expected, dropped;
 814
 815         expected = rx_queue->removed_count & EFX_RXQ_MASK;
 816         dropped = (index - expected) & EFX_RXQ_MASK;
 817         EFX_INFO(efx, "dropped %d events (index=%d expected=%d)\n",
 818                 dropped, index, expected);
 819
 820         efx_schedule_reset(efx, EFX_WORKAROUND_5676(efx) ?
 821                            RESET_TYPE_RX_RECOVERY : RESET_TYPE_DISABLE);
 822 }
 823
 824 /* Handle a packet received event
 825  *
 826  * Falcon silicon gives a "discard" flag if it's a unicast packet with the
 827  * wrong destination address
 828  * Also "is multicast" and "matches multicast filter" flags can be used to
 829  * discard non-matching multicast packets.
 830  */
 831 static void falcon_handle_rx_event(struct efx_channel *channel,
 832                                    const efx_qword_t *event)
 833 {
 834         unsigned int rx_ev_desc_ptr, rx_ev_byte_cnt;
 835         unsigned int rx_ev_hdr_type, rx_ev_mcast_pkt;
 836         unsigned expected_ptr;
 837         bool rx_ev_pkt_ok, discard = false, checksummed;
 838         struct efx_rx_queue *rx_queue;
 839         struct efx_nic *efx = channel->efx;
 840
 841         /* Basic packet information */
 842         rx_ev_byte_cnt = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_BYTE_CNT);
 843         rx_ev_pkt_ok = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_PKT_OK);
 844         rx_ev_hdr_type = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_HDR_TYPE);
 845         WARN_ON(EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_JUMBO_CONT));
 846         WARN_ON(EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_SOP) != 1);
 847         WARN_ON(EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_Q_LABEL) !=
 848                 channel->channel);
 849
 850         rx_queue = &efx->rx_queue[channel->channel];
 851
 852         rx_ev_desc_ptr = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_DESC_PTR);
 853         expected_ptr = rx_queue->removed_count & EFX_RXQ_MASK;
 854         if (unlikely(rx_ev_desc_ptr != expected_ptr))
 855                 falcon_handle_rx_bad_index(rx_queue, rx_ev_desc_ptr);
 856
 857         if (likely(rx_ev_pkt_ok)) {
 858                 /* If packet is marked as OK and packet type is TCP/IPv4 or
 859                  * UDP/IPv4, then we can rely on the hardware checksum.
 860                  */
 861                 checksummed =
 862                         efx->rx_checksum_enabled &&
 863                         (rx_ev_hdr_type == FSE_AB_RX_EV_HDR_TYPE_IPV4_TCP ||
 864                          rx_ev_hdr_type == FSE_AB_RX_EV_HDR_TYPE_IPV4_UDP);
 865         } else {
 866                 falcon_handle_rx_not_ok(rx_queue, event, &rx_ev_pkt_ok,
 867                                         &discard);
 868                 checksummed = false;
 869         }
 870
 871         /* Detect multicast packets that didn't match the filter */
 872         rx_ev_mcast_pkt = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_MCAST_PKT);
 873         if (rx_ev_mcast_pkt) {
 874                 unsigned int rx_ev_mcast_hash_match =
 875                         EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_MCAST_HASH_MATCH);
 876
 877                 if (unlikely(!rx_ev_mcast_hash_match))
 878                         discard = true;
 879         }
 880
 881         channel->irq_mod_score += 2;
 882
 883         /* Handle received packet */
 884         efx_rx_packet(rx_queue, rx_ev_desc_ptr, rx_ev_byte_cnt,
 885                       checksummed, discard);
 886 }
 887
 888 /* Global events are basically PHY events */
 889 static void falcon_handle_global_event(struct efx_channel *channel,
 890                                        efx_qword_t *event)
 891 {
 892         struct efx_nic *efx = channel->efx;
 893         bool handled = false;
 894
 895         if (EFX_QWORD_FIELD(*event, FSF_AB_GLB_EV_G_PHY0_INTR) ||
 896             EFX_QWORD_FIELD(*event, FSF_AB_GLB_EV_XG_PHY0_INTR) ||
 897             EFX_QWORD_FIELD(*event, FSF_AB_GLB_EV_XFP_PHY0_INTR)) {
 898                 efx->phy_op->clear_interrupt(efx);
 899                 queue_work(efx->workqueue, &efx->phy_work);
 900                 handled = true;
 901         }
 902
 903         if ((falcon_rev(efx) >= FALCON_REV_B0) &&
 904             EFX_QWORD_FIELD(*event, FSF_BB_GLB_EV_XG_MGT_INTR)) {
 905                 queue_work(efx->workqueue, &efx->mac_work);
 906                 handled = true;
 907         }
 908
 909         if (falcon_rev(efx) <= FALCON_REV_A1 ?
 910             EFX_QWORD_FIELD(*event, FSF_AA_GLB_EV_RX_RECOVERY) :
 911             EFX_QWORD_FIELD(*event, FSF_BB_GLB_EV_RX_RECOVERY)) {
 912                 EFX_ERR(efx, "channel %d seen global RX_RESET "
 913                         "event. Resetting.\n", channel->channel);
 914
 915                 atomic_inc(&efx->rx_reset);
 916                 efx_schedule_reset(efx, EFX_WORKAROUND_6555(efx) ?
 917                                    RESET_TYPE_RX_RECOVERY : RESET_TYPE_DISABLE);
 918                 handled = true;
 919         }
 920
 921         if (!handled)
 922                 EFX_ERR(efx, "channel %d unknown global event "
 923                         EFX_QWORD_FMT "\n", channel->channel,
 924                         EFX_QWORD_VAL(*event));
 925 }
 926
 927 static void falcon_handle_driver_event(struct efx_channel *channel,
 928                                        efx_qword_t *event)
 929 {
 930         struct efx_nic *efx = channel->efx;
 931         unsigned int ev_sub_code;
 932         unsigned int ev_sub_data;
 933
 934         ev_sub_code = EFX_QWORD_FIELD(*event, FSF_AZ_DRIVER_EV_SUBCODE);
 935         ev_sub_data = EFX_QWORD_FIELD(*event, FSF_AZ_DRIVER_EV_SUBDATA);
 936
 937         switch (ev_sub_code) {
 938         case FSE_AZ_TX_DESCQ_FLS_DONE_EV:
 939                 EFX_TRACE(efx, "channel %d TXQ %d flushed\n",
 940                           channel->channel, ev_sub_data);
 941                 break;
 942         case FSE_AZ_RX_DESCQ_FLS_DONE_EV:
 943                 EFX_TRACE(efx, "channel %d RXQ %d flushed\n",
 944                           channel->channel, ev_sub_data);
 945                 break;
 946         case FSE_AZ_EVQ_INIT_DONE_EV:
 947                 EFX_LOG(efx, "channel %d EVQ %d initialised\n",
 948                         channel->channel, ev_sub_data);
 949                 break;
 950         case FSE_AZ_SRM_UPD_DONE_EV:
 951                 EFX_TRACE(efx, "channel %d SRAM update done\n",
 952                           channel->channel);
 953                 break;
 954         case FSE_AZ_WAKE_UP_EV:
 955                 EFX_TRACE(efx, "channel %d RXQ %d wakeup event\n",
 956                           channel->channel, ev_sub_data);
 957                 break;
 958         case FSE_AZ_TIMER_EV:
 959                 EFX_TRACE(efx, "channel %d RX queue %d timer expired\n",
 960                           channel->channel, ev_sub_data);
 961                 break;
 962         case FSE_AA_RX_RECOVER_EV:
 963                 EFX_ERR(efx, "channel %d seen DRIVER RX_RESET event. "
 964                         "Resetting.\n", channel->channel);
 965                 atomic_inc(&efx->rx_reset);
 966                 efx_schedule_reset(efx,
 967                                    EFX_WORKAROUND_6555(efx) ?
 968                                    RESET_TYPE_RX_RECOVERY :
 969                                    RESET_TYPE_DISABLE);
 970                 break;
 971         case FSE_BZ_RX_DSC_ERROR_EV:
 972                 EFX_ERR(efx, "RX DMA Q %d reports descriptor fetch error."
 973                         " RX Q %d is disabled.\n", ev_sub_data, ev_sub_data);
 974                 efx_schedule_reset(efx, RESET_TYPE_RX_DESC_FETCH);
 975                 break;
 976         case FSE_BZ_TX_DSC_ERROR_EV:
 977                 EFX_ERR(efx, "TX DMA Q %d reports descriptor fetch error."
 978                         " TX Q %d is disabled.\n", ev_sub_data, ev_sub_data);
 979                 efx_schedule_reset(efx, RESET_TYPE_TX_DESC_FETCH);
 980                 break;
 981         default:
 982                 EFX_TRACE(efx, "channel %d unknown driver event code %d "
 983                           "data %04x\n", channel->channel, ev_sub_code,
 984                           ev_sub_data);
 985                 break;
 986         }
 987 }
 988
 989 int falcon_process_eventq(struct efx_channel *channel, int rx_quota)
 990 {
 991         unsigned int read_ptr;
 992         efx_qword_t event, *p_event;
 993         int ev_code;
 994         int rx_packets = 0;
 995
 996         read_ptr = channel->eventq_read_ptr;
 997
 998         do {
 999                 p_event = falcon_event(channel, read_ptr);
1000                 event = *p_event;
1001
1002                 if (!falcon_event_present(&event))
1003                         /* End of events */
1004                         break;
1005
1006                 EFX_TRACE(channel->efx, "channel %d event is "EFX_QWORD_FMT"\n",
1007                           channel->channel, EFX_QWORD_VAL(event));
1008
1009                 /* Clear this event by marking it all ones */
1010                 EFX_SET_QWORD(*p_event);
1011
1012                 ev_code = EFX_QWORD_FIELD(event, FSF_AZ_EV_CODE);
1013
1014                 switch (ev_code) {
1015                 case FSE_AZ_EV_CODE_RX_EV:
1016                         falcon_handle_rx_event(channel, &event);
1017                         ++rx_packets;
1018                         break;
1019                 case FSE_AZ_EV_CODE_TX_EV:
1020                         falcon_handle_tx_event(channel, &event);
1021                         break;
1022                 case FSE_AZ_EV_CODE_DRV_GEN_EV:
1023                         channel->eventq_magic = EFX_QWORD_FIELD(
1024                                 event, FSF_AZ_DRV_GEN_EV_MAGIC);
1025                         EFX_LOG(channel->efx, "channel %d received generated "
1026                                 "event "EFX_QWORD_FMT"\n", channel->channel,
1027                                 EFX_QWORD_VAL(event));
1028                         break;
1029                 case FSE_AZ_EV_CODE_GLOBAL_EV:
1030                         falcon_handle_global_event(channel, &event);
1031                         break;
1032                 case FSE_AZ_EV_CODE_DRIVER_EV:
1033                         falcon_handle_driver_event(channel, &event);
1034                         break;
1035                 default:
1036                         EFX_ERR(channel->efx, "channel %d unknown event type %d"
1037                                 " (data " EFX_QWORD_FMT ")\n", channel->channel,
1038                                 ev_code, EFX_QWORD_VAL(event));
1039                 }
1040
1041                 /* Increment read pointer */
1042                 read_ptr = (read_ptr + 1) & EFX_EVQ_MASK;
1043
1044         } while (rx_packets < rx_quota);
1045
1046         channel->eventq_read_ptr = read_ptr;
1047         return rx_packets;
1048 }
1049
1050 void falcon_set_int_moderation(struct efx_channel *channel)
1051 {
1052         efx_dword_t timer_cmd;
1053         struct efx_nic *efx = channel->efx;
1054
1055         /* Set timer register */
1056         if (channel->irq_moderation) {
1057                 EFX_POPULATE_DWORD_2(timer_cmd,
1058                                      FRF_AB_TC_TIMER_MODE,
1059                                      FFE_BB_TIMER_MODE_INT_HLDOFF,
1060                                      FRF_AB_TC_TIMER_VAL,
1061                                      channel->irq_moderation - 1);
1062         } else {
1063                 EFX_POPULATE_DWORD_2(timer_cmd,
1064                                      FRF_AB_TC_TIMER_MODE,
1065                                      FFE_BB_TIMER_MODE_DIS,
1066                                      FRF_AB_TC_TIMER_VAL, 0);
1067         }
1068         BUILD_BUG_ON(FR_AA_TIMER_COMMAND_KER != FR_BZ_TIMER_COMMAND_P0);
1069         efx_writed_page_locked(efx, &timer_cmd, FR_BZ_TIMER_COMMAND_P0,
1070                                channel->channel);
1071
1072 }
1073
1074 /* Allocate buffer table entries for event queue */
1075 int falcon_probe_eventq(struct efx_channel *channel)
1076 {
1077         struct efx_nic *efx = channel->efx;
1078         BUILD_BUG_ON(EFX_EVQ_SIZE < 512 || EFX_EVQ_SIZE > 32768 ||
1079                      EFX_EVQ_SIZE & EFX_EVQ_MASK);
1080         return falcon_alloc_special_buffer(efx, &channel->eventq,
1081                                            EFX_EVQ_SIZE * sizeof(efx_qword_t));
1082 }
1083
1084 void falcon_init_eventq(struct efx_channel *channel)
1085 {
1086         efx_oword_t evq_ptr;
1087         struct efx_nic *efx = channel->efx;
1088
1089         EFX_LOG(efx, "channel %d event queue in special buffers %d-%d\n",
1090                 channel->channel, channel->eventq.index,
1091                 channel->eventq.index + channel->eventq.entries - 1);
1092
1093         /* Pin event queue buffer */
1094         falcon_init_special_buffer(efx, &channel->eventq);
1095
1096         /* Fill event queue with all ones (i.e. empty events) */
1097         memset(channel->eventq.addr, 0xff, channel->eventq.len);
1098
1099         /* Push event queue to card */
1100         EFX_POPULATE_OWORD_3(evq_ptr,
1101                              FRF_AZ_EVQ_EN, 1,
1102                              FRF_AZ_EVQ_SIZE, __ffs(channel->eventq.entries),
1103                              FRF_AZ_EVQ_BUF_BASE_ID, channel->eventq.index);
1104         efx_writeo_table(efx, &evq_ptr, efx->type->evq_ptr_tbl_base,
1105                          channel->channel);
1106
1107         falcon_set_int_moderation(channel);
1108 }
1109
1110 void falcon_fini_eventq(struct efx_channel *channel)
1111 {
1112         efx_oword_t eventq_ptr;
1113         struct efx_nic *efx = channel->efx;
1114
1115         /* Remove event queue from card */
1116         EFX_ZERO_OWORD(eventq_ptr);
1117         efx_writeo_table(efx, &eventq_ptr, efx->type->evq_ptr_tbl_base,
1118                          channel->channel);
1119
1120         /* Unpin event queue */
1121         falcon_fini_special_buffer(efx, &channel->eventq);
1122 }
1123
1124 /* Free buffers backing event queue */
1125 void falcon_remove_eventq(struct efx_channel *channel)
1126 {
1127         falcon_free_special_buffer(channel->efx, &channel->eventq);
1128 }
1129
1130
1131 /* Generates a test event on the event queue.  A subsequent call to
1132  * process_eventq() should pick up the event and place the value of
1133  * "magic" into channel->eventq_magic;
1134  */
1135 void falcon_generate_test_event(struct efx_channel *channel, unsigned int magic)
1136 {
1137         efx_qword_t test_event;
1138
1139         EFX_POPULATE_QWORD_2(test_event, FSF_AZ_EV_CODE,
1140                              FSE_AZ_EV_CODE_DRV_GEN_EV,
1141                              FSF_AZ_DRV_GEN_EV_MAGIC, magic);
1142         falcon_generate_event(channel, &test_event);
1143 }
1144
1145 void falcon_sim_phy_event(struct efx_nic *efx)
1146 {
1147         efx_qword_t phy_event;
1148
1149         EFX_POPULATE_QWORD_1(phy_event, FSF_AZ_EV_CODE,
1150                              FSE_AZ_EV_CODE_GLOBAL_EV);
1151         if (EFX_IS10G(efx))
1152                 EFX_SET_QWORD_FIELD(phy_event, FSF_AB_GLB_EV_XG_PHY0_INTR, 1);
1153         else
1154                 EFX_SET_QWORD_FIELD(phy_event, FSF_AB_GLB_EV_G_PHY0_INTR, 1);
1155
1156         falcon_generate_event(&efx->channel[0], &phy_event);
1157 }
1158
1159 /**************************************************************************
1160  *
1161  * Flush handling
1162  *
1163  **************************************************************************/
1164
1165
1166 static void falcon_poll_flush_events(struct efx_nic *efx)
1167 {
1168         struct efx_channel *channel = &efx->channel[0];
1169         struct efx_tx_queue *tx_queue;
1170         struct efx_rx_queue *rx_queue;
1171         unsigned int read_ptr = channel->eventq_read_ptr;
1172         unsigned int end_ptr = (read_ptr - 1) & EFX_EVQ_MASK;
1173
1174         do {
1175                 efx_qword_t *event = falcon_event(channel, read_ptr);
1176                 int ev_code, ev_sub_code, ev_queue;
1177                 bool ev_failed;
1178
1179                 if (!falcon_event_present(event))
1180                         break;
1181
1182                 ev_code = EFX_QWORD_FIELD(*event, FSF_AZ_EV_CODE);
1183                 ev_sub_code = EFX_QWORD_FIELD(*event,
1184                                               FSF_AZ_DRIVER_EV_SUBCODE);
1185                 if (ev_code == FSE_AZ_EV_CODE_DRIVER_EV &&
1186                     ev_sub_code == FSE_AZ_TX_DESCQ_FLS_DONE_EV) {
1187                         ev_queue = EFX_QWORD_FIELD(*event,
1188                                                    FSF_AZ_DRIVER_EV_SUBDATA);
1189                         if (ev_queue < EFX_TX_QUEUE_COUNT) {
1190                                 tx_queue = efx->tx_queue + ev_queue;
1191                                 tx_queue->flushed = FLUSH_DONE;
1192                         }
1193                 } else if (ev_code == FSE_AZ_EV_CODE_DRIVER_EV &&
1194                            ev_sub_code == FSE_AZ_RX_DESCQ_FLS_DONE_EV) {
1195                         ev_queue = EFX_QWORD_FIELD(
1196                                 *event, FSF_AZ_DRIVER_EV_RX_DESCQ_ID);
1197                         ev_failed = EFX_QWORD_FIELD(
1198                                 *event, FSF_AZ_DRIVER_EV_RX_FLUSH_FAIL);
1199                         if (ev_queue < efx->n_rx_queues) {
1200                                 rx_queue = efx->rx_queue + ev_queue;
1201                                 rx_queue->flushed =
1202                                         ev_failed ? FLUSH_FAILED : FLUSH_DONE;
1203                         }
1204                 }
1205
1206                 /* We're about to destroy the queue anyway, so
1207                  * it's ok to throw away every non-flush event */
1208                 EFX_SET_QWORD(*event);
1209
1210                 read_ptr = (read_ptr + 1) & EFX_EVQ_MASK;
1211         } while (read_ptr != end_ptr);
1212
1213         channel->eventq_read_ptr = read_ptr;
1214 }
1215
1216 static void falcon_prepare_flush(struct efx_nic *efx)
1217 {
1218         falcon_deconfigure_mac_wrapper(efx);
1219
1220         /* Wait for the tx and rx fifo's to get to the next packet boundary
1221          * (~1ms without back-pressure), then to drain the remainder of the
1222          * fifo's at data path speeds (negligible), with a healthy margin. */
1223         msleep(10);
1224 }
1225
1226 /* Handle tx and rx flushes at the same time, since they run in
1227  * parallel in the hardware and there's no reason for us to
1228  * serialise them */
1229 int falcon_flush_queues(struct efx_nic *efx)
1230 {
1231         struct efx_rx_queue *rx_queue;
1232         struct efx_tx_queue *tx_queue;
1233         int i, tx_pending, rx_pending;
1234
1235         falcon_prepare_flush(efx);
1236
1237         /* Flush all tx queues in parallel */
1238         efx_for_each_tx_queue(tx_queue, efx)
1239                 falcon_flush_tx_queue(tx_queue);
1240
1241         /* The hardware supports four concurrent rx flushes, each of which may
1242          * need to be retried if there is an outstanding descriptor fetch */
1243         for (i = 0; i < FALCON_FLUSH_POLL_COUNT; ++i) {
1244                 rx_pending = tx_pending = 0;
1245                 efx_for_each_rx_queue(rx_queue, efx) {
1246                         if (rx_queue->flushed == FLUSH_PENDING)
1247                                 ++rx_pending;
1248                 }
1249                 efx_for_each_rx_queue(rx_queue, efx) {
1250                         if (rx_pending == FALCON_RX_FLUSH_COUNT)
1251                                 break;
1252                         if (rx_queue->flushed == FLUSH_FAILED ||
1253                             rx_queue->flushed == FLUSH_NONE) {
1254                                 falcon_flush_rx_queue(rx_queue);
1255                                 ++rx_pending;
1256                         }
1257                 }
1258                 efx_for_each_tx_queue(tx_queue, efx) {
1259                         if (tx_queue->flushed != FLUSH_DONE)
1260                                 ++tx_pending;
1261                 }
1262
1263                 if (rx_pending == 0 && tx_pending == 0)
1264                         return 0;
1265
1266                 msleep(FALCON_FLUSH_INTERVAL);
1267                 falcon_poll_flush_events(efx);
1268         }
1269
1270         /* Mark the queues as all flushed. We're going to return failure
1271          * leading to a reset, or fake up success anyway */
1272         efx_for_each_tx_queue(tx_queue, efx) {
1273                 if (tx_queue->flushed != FLUSH_DONE)
1274                         EFX_ERR(efx, "tx queue %d flush command timed out\n",
1275                                 tx_queue->queue);
1276                 tx_queue->flushed = FLUSH_DONE;
1277         }
1278         efx_for_each_rx_queue(rx_queue, efx) {
1279                 if (rx_queue->flushed != FLUSH_DONE)
1280                         EFX_ERR(efx, "rx queue %d flush command timed out\n",
1281                                 rx_queue->queue);
1282                 rx_queue->flushed = FLUSH_DONE;
1283         }
1284
1285         if (EFX_WORKAROUND_7803(efx))
1286                 return 0;
1287
1288         return -ETIMEDOUT;
1289 }
1290
1291 /**************************************************************************
1292  *
1293  * Falcon hardware interrupts
1294  * The hardware interrupt handler does very little work; all the event
1295  * queue processing is carried out by per-channel tasklets.
1296  *
1297  **************************************************************************/
1298
1299 /* Enable/disable/generate Falcon interrupts */
1300 static inline void falcon_interrupts(struct efx_nic *efx, int enabled,
1301                                      int force)
1302 {
1303         efx_oword_t int_en_reg_ker;
1304
1305         EFX_POPULATE_OWORD_2(int_en_reg_ker,
1306                              FRF_AZ_KER_INT_KER, force,
1307                              FRF_AZ_DRV_INT_EN_KER, enabled);
1308         efx_writeo(efx, &int_en_reg_ker, FR_AZ_INT_EN_KER);
1309 }
1310
1311 void falcon_enable_interrupts(struct efx_nic *efx)
1312 {
1313         efx_oword_t int_adr_reg_ker;
1314         struct efx_channel *channel;
1315
1316         EFX_ZERO_OWORD(*((efx_oword_t *) efx->irq_status.addr));
1317         wmb(); /* Ensure interrupt vector is clear before interrupts enabled */
1318
1319         /* Program address */
1320         EFX_POPULATE_OWORD_2(int_adr_reg_ker,
1321                              FRF_AZ_NORM_INT_VEC_DIS_KER,
1322                              EFX_INT_MODE_USE_MSI(efx),
1323                              FRF_AZ_INT_ADR_KER, efx->irq_status.dma_addr);
1324         efx_writeo(efx, &int_adr_reg_ker, FR_AZ_INT_ADR_KER);
1325
1326         /* Enable interrupts */
1327         falcon_interrupts(efx, 1, 0);
1328
1329         /* Force processing of all the channels to get the EVQ RPTRs up to
1330            date */
1331         efx_for_each_channel(channel, efx)
1332                 efx_schedule_channel(channel);
1333 }
1334
1335 void falcon_disable_interrupts(struct efx_nic *efx)
1336 {
1337         /* Disable interrupts */
1338         falcon_interrupts(efx, 0, 0);
1339 }
1340
1341 /* Generate a Falcon test interrupt
1342  * Interrupt must already have been enabled, otherwise nasty things
1343  * may happen.
1344  */
1345 void falcon_generate_interrupt(struct efx_nic *efx)
1346 {
1347         falcon_interrupts(efx, 1, 1);
1348 }
1349
1350 /* Acknowledge a legacy interrupt from Falcon
1351  *
1352  * This acknowledges a legacy (not MSI) interrupt via INT_ACK_KER_REG.
1353  *
1354  * Due to SFC bug 3706 (silicon revision <=A1) reads can be duplicated in the
1355  * BIU. Interrupt acknowledge is read sensitive so must write instead
1356  * (then read to ensure the BIU collector is flushed)
1357  *
1358  * NB most hardware supports MSI interrupts
1359  */
1360 static inline void falcon_irq_ack_a1(struct efx_nic *efx)
1361 {
1362         efx_dword_t reg;
1363
1364         EFX_POPULATE_DWORD_1(reg, FRF_AA_INT_ACK_KER_FIELD, 0xb7eb7e);
1365         efx_writed(efx, &reg, FR_AA_INT_ACK_KER);
1366         efx_readd(efx, &reg, FR_AA_WORK_AROUND_BROKEN_PCI_READS);
1367 }
1368
1369 /* Process a fatal interrupt
1370  * Disable bus mastering ASAP and schedule a reset
1371  */
1372 static irqreturn_t falcon_fatal_interrupt(struct efx_nic *efx)
1373 {
1374         struct falcon_nic_data *nic_data = efx->nic_data;
1375         efx_oword_t *int_ker = efx->irq_status.addr;
1376         efx_oword_t fatal_intr;
1377         int error, mem_perr;
1378
1379         efx_reado(efx, &fatal_intr, FR_AZ_FATAL_INTR_KER);
1380         error = EFX_OWORD_FIELD(fatal_intr, FRF_AZ_FATAL_INTR);
1381
1382         EFX_ERR(efx, "SYSTEM ERROR " EFX_OWORD_FMT " status "
1383                 EFX_OWORD_FMT ": %s\n", EFX_OWORD_VAL(*int_ker),
1384                 EFX_OWORD_VAL(fatal_intr),
1385                 error ? "disabling bus mastering" : "no recognised error");
1386         if (error == 0)
1387                 goto out;
1388
1389         /* If this is a memory parity error dump which blocks are offending */
1390         mem_perr = EFX_OWORD_FIELD(fatal_intr, FRF_AZ_MEM_PERR_INT_KER);
1391         if (mem_perr) {
1392                 efx_oword_t reg;
1393                 efx_reado(efx, &reg, FR_AZ_MEM_STAT);
1394                 EFX_ERR(efx, "SYSTEM ERROR: memory parity error "
1395                         EFX_OWORD_FMT "\n", EFX_OWORD_VAL(reg));
1396         }
1397
1398         /* Disable both devices */
1399         pci_clear_master(efx->pci_dev);
1400         if (FALCON_IS_DUAL_FUNC(efx))
1401                 pci_clear_master(nic_data->pci_dev2);
1402         falcon_disable_interrupts(efx);
1403
1404         /* Count errors and reset or disable the NIC accordingly */
1405         if (efx->int_error_count == 0 ||
1406             time_after(jiffies, efx->int_error_expire)) {
1407                 efx->int_error_count = 0;
1408                 efx->int_error_expire =
1409                         jiffies + FALCON_INT_ERROR_EXPIRE * HZ;
1410         }
1411         if (++efx->int_error_count < FALCON_MAX_INT_ERRORS) {
1412                 EFX_ERR(efx, "SYSTEM ERROR - reset scheduled\n");
1413                 efx_schedule_reset(efx, RESET_TYPE_INT_ERROR);
1414         } else {
1415                 EFX_ERR(efx, "SYSTEM ERROR - max number of errors seen."
1416                         "NIC will be disabled\n");
1417                 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
1418         }
1419 out:
1420         return IRQ_HANDLED;
1421 }
1422
1423 /* Handle a legacy interrupt from Falcon
1424  * Acknowledges the interrupt and schedule event queue processing.
1425  */
1426 static irqreturn_t falcon_legacy_interrupt_b0(int irq, void *dev_id)
1427 {
1428         struct efx_nic *efx = dev_id;
1429         efx_oword_t *int_ker = efx->irq_status.addr;
1430         irqreturn_t result = IRQ_NONE;
1431         struct efx_channel *channel;
1432         efx_dword_t reg;
1433         u32 queues;
1434         int syserr;
1435
1436         /* Read the ISR which also ACKs the interrupts */
1437         efx_readd(efx, &reg, FR_BZ_INT_ISR0);
1438         queues = EFX_EXTRACT_DWORD(reg, 0, 31);
1439
1440         /* Check to see if we have a serious error condition */
1441         syserr = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_FATAL_INT);
1442         if (unlikely(syserr))
1443                 return falcon_fatal_interrupt(efx);
1444
1445         /* Schedule processing of any interrupting queues */
1446         efx_for_each_channel(channel, efx) {
1447                 if ((queues & 1) ||
1448                     falcon_event_present(
1449                             falcon_event(channel, channel->eventq_read_ptr))) {
1450                         efx_schedule_channel(channel);
1451                         result = IRQ_HANDLED;
1452                 }
1453                 queues >>= 1;
1454         }
1455
1456         if (result == IRQ_HANDLED) {
1457                 efx->last_irq_cpu = raw_smp_processor_id();
1458                 EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n",
1459                           irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg));
1460         }
1461
1462         return result;
1463 }
1464
1465
1466 static irqreturn_t falcon_legacy_interrupt_a1(int irq, void *dev_id)
1467 {
1468         struct efx_nic *efx = dev_id;
1469         efx_oword_t *int_ker = efx->irq_status.addr;
1470         struct efx_channel *channel;
1471         int syserr;
1472         int queues;
1473
1474         /* Check to see if this is our interrupt.  If it isn't, we
1475          * exit without having touched the hardware.
1476          */
1477         if (unlikely(EFX_OWORD_IS_ZERO(*int_ker))) {
1478                 EFX_TRACE(efx, "IRQ %d on CPU %d not for me\n", irq,
1479                           raw_smp_processor_id());
1480                 return IRQ_NONE;
1481         }
1482         efx->last_irq_cpu = raw_smp_processor_id();
1483         EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_OWORD_FMT "\n",
1484                   irq, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker));
1485
1486         /* Check to see if we have a serious error condition */
1487         syserr = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_FATAL_INT);
1488         if (unlikely(syserr))
1489                 return falcon_fatal_interrupt(efx);
1490
1491         /* Determine interrupting queues, clear interrupt status
1492          * register and acknowledge the device interrupt.
1493          */
1494         BUILD_BUG_ON(INT_EVQS_WIDTH > EFX_MAX_CHANNELS);
1495         queues = EFX_OWORD_FIELD(*int_ker, INT_EVQS);
1496         EFX_ZERO_OWORD(*int_ker);
1497         wmb(); /* Ensure the vector is cleared before interrupt ack */
1498         falcon_irq_ack_a1(efx);
1499
1500         /* Schedule processing of any interrupting queues */
1501         channel = &efx->channel[0];
1502         while (queues) {
1503                 if (queues & 0x01)
1504                         efx_schedule_channel(channel);
1505                 channel++;
1506                 queues >>= 1;
1507         }
1508
1509         return IRQ_HANDLED;
1510 }
1511
1512 /* Handle an MSI interrupt from Falcon
1513  *
1514  * Handle an MSI hardware interrupt.  This routine schedules event
1515  * queue processing.  No interrupt acknowledgement cycle is necessary.
1516  * Also, we never need to check that the interrupt is for us, since
1517  * MSI interrupts cannot be shared.
1518  */
1519 static irqreturn_t falcon_msi_interrupt(int irq, void *dev_id)
1520 {
1521         struct efx_channel *channel = dev_id;
1522         struct efx_nic *efx = channel->efx;
1523         efx_oword_t *int_ker = efx->irq_status.addr;
1524         int syserr;
1525
1526         efx->last_irq_cpu = raw_smp_processor_id();
1527         EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_OWORD_FMT "\n",
1528                   irq, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker));
1529
1530         /* Check to see if we have a serious error condition */
1531         syserr = EFX_OWORD_FIELD(*int_ker, FATAL_INT);
1532         if (unlikely(syserr))
1533                 return falcon_fatal_interrupt(efx);
1534
1535         /* Schedule processing of the channel */
1536         efx_schedule_channel(channel);
1537
1538         return IRQ_HANDLED;
1539 }
1540
1541
1542 /* Setup RSS indirection table.
1543  * This maps from the hash value of the packet to RXQ
1544  */
1545 static void falcon_setup_rss_indir_table(struct efx_nic *efx)
1546 {
1547         int i = 0;
1548         unsigned long offset;
1549         efx_dword_t dword;
1550
1551         if (falcon_rev(efx) < FALCON_REV_B0)
1552                 return;
1553
1554         for (offset = FR_BZ_RX_INDIRECTION_TBL;
1555              offset < FR_BZ_RX_INDIRECTION_TBL + 0x800;
1556              offset += 0x10) {
1557                 EFX_POPULATE_DWORD_1(dword, FRF_BZ_IT_QUEUE,
1558                                      i % efx->n_rx_queues);
1559                 efx_writed(efx, &dword, offset);
1560                 i++;
1561         }
1562 }
1563
1564 /* Hook interrupt handler(s)
1565  * Try MSI and then legacy interrupts.
1566  */
1567 int falcon_init_interrupt(struct efx_nic *efx)
1568 {
1569         struct efx_channel *channel;
1570         int rc;
1571
1572         if (!EFX_INT_MODE_USE_MSI(efx)) {
1573                 irq_handler_t handler;
1574                 if (falcon_rev(efx) >= FALCON_REV_B0)
1575                         handler = falcon_legacy_interrupt_b0;
1576                 else
1577                         handler = falcon_legacy_interrupt_a1;
1578
1579                 rc = request_irq(efx->legacy_irq, handler, IRQF_SHARED,
1580                                  efx->name, efx);
1581                 if (rc) {
1582                         EFX_ERR(efx, "failed to hook legacy IRQ %d\n",
1583                                 efx->pci_dev->irq);
1584                         goto fail1;
1585                 }
1586                 return 0;
1587         }
1588
1589         /* Hook MSI or MSI-X interrupt */
1590         efx_for_each_channel(channel, efx) {
1591                 rc = request_irq(channel->irq, falcon_msi_interrupt,
1592                                  IRQF_PROBE_SHARED, /* Not shared */
1593                                  channel->name, channel);
1594                 if (rc) {
1595                         EFX_ERR(efx, "failed to hook IRQ %d\n", channel->irq);
1596                         goto fail2;
1597                 }
1598         }
1599
1600         return 0;
1601
1602  fail2:
1603         efx_for_each_channel(channel, efx)
1604                 free_irq(channel->irq, channel);
1605  fail1:
1606         return rc;
1607 }
1608
1609 void falcon_fini_interrupt(struct efx_nic *efx)
1610 {
1611         struct efx_channel *channel;
1612         efx_oword_t reg;
1613
1614         /* Disable MSI/MSI-X interrupts */
1615         efx_for_each_channel(channel, efx) {
1616                 if (channel->irq)
1617                         free_irq(channel->irq, channel);
1618         }
1619
1620         /* ACK legacy interrupt */
1621         if (falcon_rev(efx) >= FALCON_REV_B0)
1622                 efx_reado(efx, &reg, FR_BZ_INT_ISR0);
1623         else
1624                 falcon_irq_ack_a1(efx);
1625
1626         /* Disable legacy interrupt */
1627         if (efx->legacy_irq)
1628                 free_irq(efx->legacy_irq, efx);
1629 }
1630
1631 /**************************************************************************
1632  *
1633  * EEPROM/flash
1634  *
1635  **************************************************************************
1636  */
1637
1638 #define FALCON_SPI_MAX_LEN sizeof(efx_oword_t)
1639
1640 static int falcon_spi_poll(struct efx_nic *efx)
1641 {
1642         efx_oword_t reg;
1643         efx_reado(efx, &reg, FR_AB_EE_SPI_HCMD);
1644         return EFX_OWORD_FIELD(reg, FRF_AB_EE_SPI_HCMD_CMD_EN) ? -EBUSY : 0;
1645 }
1646
1647 /* Wait for SPI command completion */
1648 static int falcon_spi_wait(struct efx_nic *efx)
1649 {
1650         /* Most commands will finish quickly, so we start polling at
1651          * very short intervals.  Sometimes the command may have to
1652          * wait for VPD or expansion ROM access outside of our
1653          * control, so we allow up to 100 ms. */
1654         unsigned long timeout = jiffies + 1 + DIV_ROUND_UP(HZ, 10);
1655         int i;
1656
1657         for (i = 0; i < 10; i++) {
1658                 if (!falcon_spi_poll(efx))
1659                         return 0;
1660                 udelay(10);
1661         }
1662
1663         for (;;) {
1664                 if (!falcon_spi_poll(efx))
1665                         return 0;
1666                 if (time_after_eq(jiffies, timeout)) {
1667                         EFX_ERR(efx, "timed out waiting for SPI\n");
1668                         return -ETIMEDOUT;
1669                 }
1670                 schedule_timeout_uninterruptible(1);
1671         }
1672 }
1673
1674 int falcon_spi_cmd(const struct efx_spi_device *spi,
1675                    unsigned int command, int address,
1676                    const void *in, void *out, size_t len)
1677 {
1678         struct efx_nic *efx = spi->efx;
1679         bool addressed = (address >= 0);
1680         bool reading = (out != NULL);
1681         efx_oword_t reg;
1682         int rc;
1683
1684         /* Input validation */
1685         if (len > FALCON_SPI_MAX_LEN)
1686                 return -EINVAL;
1687         BUG_ON(!mutex_is_locked(&efx->spi_lock));
1688
1689         /* Check that previous command is not still running */
1690         rc = falcon_spi_poll(efx);
1691         if (rc)
1692                 return rc;
1693
1694         /* Program address register, if we have an address */
1695         if (addressed) {
1696                 EFX_POPULATE_OWORD_1(reg, FRF_AB_EE_SPI_HADR_ADR, address);
1697                 efx_writeo(efx, &reg, FR_AB_EE_SPI_HADR);
1698         }
1699
1700         /* Program data register, if we have data */
1701         if (in != NULL) {
1702                 memcpy(&reg, in, len);
1703                 efx_writeo(efx, &reg, FR_AB_EE_SPI_HDATA);
1704         }
1705
1706         /* Issue read/write command */
1707         EFX_POPULATE_OWORD_7(reg,
1708                              FRF_AB_EE_SPI_HCMD_CMD_EN, 1,
1709                              FRF_AB_EE_SPI_HCMD_SF_SEL, spi->device_id,
1710                              FRF_AB_EE_SPI_HCMD_DABCNT, len,
1711                              FRF_AB_EE_SPI_HCMD_READ, reading,
1712                              FRF_AB_EE_SPI_HCMD_DUBCNT, 0,
1713                              FRF_AB_EE_SPI_HCMD_ADBCNT,
1714                              (addressed ? spi->addr_len : 0),
1715                              FRF_AB_EE_SPI_HCMD_ENC, command);
1716         efx_writeo(efx, &reg, FR_AB_EE_SPI_HCMD);
1717
1718         /* Wait for read/write to complete */
1719         rc = falcon_spi_wait(efx);
1720         if (rc)
1721                 return rc;
1722
1723         /* Read data */
1724         if (out != NULL) {
1725                 efx_reado(efx, &reg, FR_AB_EE_SPI_HDATA);
1726                 memcpy(out, &reg, len);
1727         }
1728
1729         return 0;
1730 }
1731
1732 static size_t
1733 falcon_spi_write_limit(const struct efx_spi_device *spi, size_t start)
1734 {
1735         return min(FALCON_SPI_MAX_LEN,
1736                    (spi->block_size - (start & (spi->block_size - 1))));
1737 }
1738
1739 static inline u8
1740 efx_spi_munge_command(const struct efx_spi_device *spi,
1741                       const u8 command, const unsigned int address)
1742 {
1743         return command | (((address >> 8) & spi->munge_address) << 3);
1744 }
1745
1746 /* Wait up to 10 ms for buffered write completion */
1747 int falcon_spi_wait_write(const struct efx_spi_device *spi)
1748 {
1749         struct efx_nic *efx = spi->efx;
1750         unsigned long timeout = jiffies + 1 + DIV_ROUND_UP(HZ, 100);
1751         u8 status;
1752         int rc;
1753
1754         for (;;) {
1755                 rc = falcon_spi_cmd(spi, SPI_RDSR, -1, NULL,
1756                                     &status, sizeof(status));
1757                 if (rc)
1758                         return rc;
1759                 if (!(status & SPI_STATUS_NRDY))
1760                         return 0;
1761                 if (time_after_eq(jiffies, timeout)) {
1762                         EFX_ERR(efx, "SPI write timeout on device %d"
1763                                 " last status=0x%02x\n",
1764                                 spi->device_id, status);
1765                         return -ETIMEDOUT;
1766                 }
1767                 schedule_timeout_uninterruptible(1);
1768         }
1769 }
1770
1771 int falcon_spi_read(const struct efx_spi_device *spi, loff_t start,
1772                     size_t len, size_t *retlen, u8 *buffer)
1773 {
1774         size_t block_len, pos = 0;
1775         unsigned int command;
1776         int rc = 0;
1777
1778         while (pos < len) {
1779                 block_len = min(len - pos, FALCON_SPI_MAX_LEN);
1780
1781                 command = efx_spi_munge_command(spi, SPI_READ, start + pos);
1782                 rc = falcon_spi_cmd(spi, command, start + pos, NULL,
1783                                     buffer + pos, block_len);
1784                 if (rc)
1785                         break;
1786                 pos += block_len;
1787
1788                 /* Avoid locking up the system */
1789                 cond_resched();
1790                 if (signal_pending(current)) {
1791                         rc = -EINTR;
1792                         break;
1793                 }
1794         }
1795
1796         if (retlen)
1797                 *retlen = pos;
1798         return rc;
1799 }
1800
1801 int falcon_spi_write(const struct efx_spi_device *spi, loff_t start,
1802                      size_t len, size_t *retlen, const u8 *buffer)
1803 {
1804         u8 verify_buffer[FALCON_SPI_MAX_LEN];
1805         size_t block_len, pos = 0;
1806         unsigned int command;
1807         int rc = 0;
1808
1809         while (pos < len) {
1810                 rc = falcon_spi_cmd(spi, SPI_WREN, -1, NULL, NULL, 0);
1811                 if (rc)
1812                         break;
1813
1814                 block_len = min(len - pos,
1815                                 falcon_spi_write_limit(spi, start + pos));
1816                 command = efx_spi_munge_command(spi, SPI_WRITE, start + pos);
1817                 rc = falcon_spi_cmd(spi, command, start + pos,
1818                                     buffer + pos, NULL, block_len);
1819                 if (rc)
1820                         break;
1821
1822                 rc = falcon_spi_wait_write(spi);
1823                 if (rc)
1824                         break;
1825
1826                 command = efx_spi_munge_command(spi, SPI_READ, start + pos);
1827                 rc = falcon_spi_cmd(spi, command, start + pos,
1828                                     NULL, verify_buffer, block_len);
1829                 if (memcmp(verify_buffer, buffer + pos, block_len)) {
1830                         rc = -EIO;
1831                         break;
1832                 }
1833
1834                 pos += block_len;
1835
1836                 /* Avoid locking up the system */
1837                 cond_resched();
1838                 if (signal_pending(current)) {
1839                         rc = -EINTR;
1840                         break;
1841                 }
1842         }
1843
1844         if (retlen)
1845                 *retlen = pos;
1846         return rc;
1847 }
1848
1849 /**************************************************************************
1850  *
1851  * MAC wrapper
1852  *
1853  **************************************************************************
1854  */
1855
1856 static int falcon_reset_macs(struct efx_nic *efx)
1857 {
1858         efx_oword_t reg;
1859         int count;
1860
1861         if (falcon_rev(efx) < FALCON_REV_B0) {
1862                 /* It's not safe to use GLB_CTL_REG to reset the
1863                  * macs, so instead use the internal MAC resets
1864                  */
1865                 if (!EFX_IS10G(efx)) {
1866                         EFX_POPULATE_OWORD_1(reg, FRF_AB_GM_SW_RST, 1);
1867                         efx_writeo(efx, &reg, FR_AB_GM_CFG1);
1868                         udelay(1000);
1869
1870                         EFX_POPULATE_OWORD_1(reg, FRF_AB_GM_SW_RST, 0);
1871                         efx_writeo(efx, &reg, FR_AB_GM_CFG1);
1872                         udelay(1000);
1873                         return 0;
1874                 } else {
1875                         EFX_POPULATE_OWORD_1(reg, FRF_AB_XM_CORE_RST, 1);
1876                         efx_writeo(efx, &reg, FR_AB_XM_GLB_CFG);
1877
1878                         for (count = 0; count < 10000; count++) {
1879                                 efx_reado(efx, &reg, FR_AB_XM_GLB_CFG);
1880                                 if (EFX_OWORD_FIELD(reg, FRF_AB_XM_CORE_RST) ==
1881                                     0)
1882                                         return 0;
1883                                 udelay(10);
1884                         }
1885
1886                         EFX_ERR(efx, "timed out waiting for XMAC core reset\n");
1887                         return -ETIMEDOUT;
1888                 }
1889         }
1890
1891         /* MAC stats will fail whilst the TX fifo is draining. Serialise
1892          * the drain sequence with the statistics fetch */
1893         efx_stats_disable(efx);
1894
1895         efx_reado(efx, &reg, FR_AB_MAC_CTRL);
1896         EFX_SET_OWORD_FIELD(reg, FRF_BB_TXFIFO_DRAIN_EN, 1);
1897         efx_writeo(efx, &reg, FR_AB_MAC_CTRL);
1898
1899         efx_reado(efx, &reg, FR_AB_GLB_CTL);
1900         EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_XGTX, 1);
1901         EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_XGRX, 1);
1902         EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_EM, 1);
1903         efx_writeo(efx, &reg, FR_AB_GLB_CTL);
1904
1905         count = 0;
1906         while (1) {
1907                 efx_reado(efx, &reg, FR_AB_GLB_CTL);
1908                 if (!EFX_OWORD_FIELD(reg, FRF_AB_RST_XGTX) &&
1909                     !EFX_OWORD_FIELD(reg, FRF_AB_RST_XGRX) &&
1910                     !EFX_OWORD_FIELD(reg, FRF_AB_RST_EM)) {
1911                         EFX_LOG(efx, "Completed MAC reset after %d loops\n",
1912                                 count);
1913                         break;
1914                 }
1915                 if (count > 20) {
1916                         EFX_ERR(efx, "MAC reset failed\n");
1917                         break;
1918                 }
1919                 count++;
1920                 udelay(10);
1921         }
1922
1923         efx_stats_enable(efx);
1924
1925         /* If we've reset the EM block and the link is up, then
1926          * we'll have to kick the XAUI link so the PHY can recover */
1927         if (efx->link_state.up && EFX_IS10G(efx) && EFX_WORKAROUND_5147(efx))
1928                 falcon_reset_xaui(efx);
1929
1930         return 0;
1931 }
1932
1933 void falcon_drain_tx_fifo(struct efx_nic *efx)
1934 {
1935         efx_oword_t reg;
1936
1937         if ((falcon_rev(efx) < FALCON_REV_B0) ||
1938             (efx->loopback_mode != LOOPBACK_NONE))
1939                 return;
1940
1941         efx_reado(efx, &reg, FR_AB_MAC_CTRL);
1942         /* There is no point in draining more than once */
1943         if (EFX_OWORD_FIELD(reg, FRF_BB_TXFIFO_DRAIN_EN))
1944                 return;
1945
1946         falcon_reset_macs(efx);
1947 }
1948
1949 void falcon_deconfigure_mac_wrapper(struct efx_nic *efx)
1950 {
1951         efx_oword_t reg;
1952
1953         if (falcon_rev(efx) < FALCON_REV_B0)
1954                 return;
1955
1956         /* Isolate the MAC -> RX */
1957         efx_reado(efx, &reg, FR_AZ_RX_CFG);
1958         EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 0);
1959         efx_writeo(efx, &reg, FR_AZ_RX_CFG);
1960
1961         if (!efx->link_state.up)
1962                 falcon_drain_tx_fifo(efx);
1963 }
1964
1965 void falcon_reconfigure_mac_wrapper(struct efx_nic *efx)
1966 {
1967         struct efx_link_state *link_state = &efx->link_state;
1968         efx_oword_t reg;
1969         int link_speed;
1970         bool tx_fc;
1971
1972         switch (link_state->speed) {
1973         case 10000: link_speed = 3; break;
1974         case 1000:  link_speed = 2; break;
1975         case 100:   link_speed = 1; break;
1976         default:    link_speed = 0; break;
1977         }
1978         /* MAC_LINK_STATUS controls MAC backpressure but doesn't work
1979          * as advertised.  Disable to ensure packets are not
1980          * indefinitely held and TX queue can be flushed at any point
1981          * while the link is down. */
1982         EFX_POPULATE_OWORD_5(reg,
1983                              FRF_AB_MAC_XOFF_VAL, 0xffff /* max pause time */,
1984                              FRF_AB_MAC_BCAD_ACPT, 1,
1985                              FRF_AB_MAC_UC_PROM, efx->promiscuous,
1986                              FRF_AB_MAC_LINK_STATUS, 1, /* always set */
1987                              FRF_AB_MAC_SPEED, link_speed);
1988         /* On B0, MAC backpressure can be disabled and packets get
1989          * discarded. */
1990         if (falcon_rev(efx) >= FALCON_REV_B0) {
1991                 EFX_SET_OWORD_FIELD(reg, FRF_BB_TXFIFO_DRAIN_EN,
1992                                     !link_state->up);
1993         }
1994
1995         efx_writeo(efx, &reg, FR_AB_MAC_CTRL);
1996
1997         /* Restore the multicast hash registers. */
1998         falcon_set_multicast_hash(efx);
1999
2000         /* Transmission of pause frames when RX crosses the threshold is
2001          * covered by RX_XOFF_MAC_EN and XM_TX_CFG_REG:XM_FCNTL.
2002          * Action on receipt of pause frames is controller by XM_DIS_FCNTL */
2003         tx_fc = !!(efx->link_state.fc & EFX_FC_TX);
2004         efx_reado(efx, &reg, FR_AZ_RX_CFG);
2005         EFX_SET_OWORD_FIELD(reg, FRF_AZ_RX_XOFF_MAC_EN, tx_fc);
2006
2007         /* Unisolate the MAC -> RX */
2008         if (falcon_rev(efx) >= FALCON_REV_B0)
2009                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 1);
2010         efx_writeo(efx, &reg, FR_AZ_RX_CFG);
2011 }
2012
2013 int falcon_dma_stats(struct efx_nic *efx, unsigned int done_offset)
2014 {
2015         efx_oword_t reg;
2016         u32 *dma_done;
2017         int i;
2018
2019         if (disable_dma_stats)
2020                 return 0;
2021
2022         /* Statistics fetch will fail if the MAC is in TX drain */
2023         if (falcon_rev(efx) >= FALCON_REV_B0) {
2024                 efx_oword_t temp;
2025                 efx_reado(efx, &temp, FR_AB_MAC_CTRL);
2026                 if (EFX_OWORD_FIELD(temp, FRF_BB_TXFIFO_DRAIN_EN))
2027                         return 0;
2028         }
2029
2030         dma_done = (efx->stats_buffer.addr + done_offset);
2031         *dma_done = FALCON_STATS_NOT_DONE;
2032         wmb(); /* ensure done flag is clear */
2033
2034         /* Initiate DMA transfer of stats */
2035         EFX_POPULATE_OWORD_2(reg,
2036                              FRF_AB_MAC_STAT_DMA_CMD, 1,
2037                              FRF_AB_MAC_STAT_DMA_ADR,
2038                              efx->stats_buffer.dma_addr);
2039         efx_writeo(efx, &reg, FR_AB_MAC_STAT_DMA);
2040
2041         /* Wait for transfer to complete */
2042         for (i = 0; i < 400; i++) {
2043                 if (*(volatile u32 *)dma_done == FALCON_STATS_DONE) {
2044                         rmb(); /* Ensure the stats are valid. */
2045                         return 0;
2046                 }
2047                 udelay(10);
2048         }
2049
2050         EFX_ERR(efx, "timed out waiting for statistics\n");
2051         return -ETIMEDOUT;
2052 }
2053
2054 /**************************************************************************
2055  *
2056  * PHY access via GMII
2057  *
2058  **************************************************************************
2059  */
2060
2061 /* Wait for GMII access to complete */
2062 static int falcon_gmii_wait(struct efx_nic *efx)
2063 {
2064         efx_oword_t md_stat;
2065         int count;
2066
2067         /* wait upto 50ms - taken max from datasheet */
2068         for (count = 0; count < 5000; count++) {
2069                 efx_reado(efx, &md_stat, FR_AB_MD_STAT);
2070                 if (EFX_OWORD_FIELD(md_stat, FRF_AB_MD_BSY) == 0) {
2071                         if (EFX_OWORD_FIELD(md_stat, FRF_AB_MD_LNFL) != 0 ||
2072                             EFX_OWORD_FIELD(md_stat, FRF_AB_MD_BSERR) != 0) {
2073                                 EFX_ERR(efx, "error from GMII access "
2074                                         EFX_OWORD_FMT"\n",
2075                                         EFX_OWORD_VAL(md_stat));
2076                                 return -EIO;
2077                         }
2078                         return 0;
2079                 }
2080                 udelay(10);
2081         }
2082         EFX_ERR(efx, "timed out waiting for GMII\n");
2083         return -ETIMEDOUT;
2084 }
2085
2086 /* Write an MDIO register of a PHY connected to Falcon. */
2087 static int falcon_mdio_write(struct net_device *net_dev,
2088                              int prtad, int devad, u16 addr, u16 value)
2089 {
2090         struct efx_nic *efx = netdev_priv(net_dev);
2091         efx_oword_t reg;
2092         int rc;
2093
2094         EFX_REGDUMP(efx, "writing MDIO %d register %d.%d with 0x%04x\n",
2095                     prtad, devad, addr, value);
2096
2097         spin_lock_bh(&efx->phy_lock);
2098
2099         /* Check MDIO not currently being accessed */
2100         rc = falcon_gmii_wait(efx);
2101         if (rc)
2102                 goto out;
2103
2104         /* Write the address/ID register */
2105         EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_PHY_ADR, addr);
2106         efx_writeo(efx, &reg, FR_AB_MD_PHY_ADR);
2107
2108         EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_PRT_ADR, prtad,
2109                              FRF_AB_MD_DEV_ADR, devad);
2110         efx_writeo(efx, &reg, FR_AB_MD_ID);
2111
2112         /* Write data */
2113         EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_TXD, value);
2114         efx_writeo(efx, &reg, FR_AB_MD_TXD);
2115
2116         EFX_POPULATE_OWORD_2(reg,
2117                              FRF_AB_MD_WRC, 1,
2118                              FRF_AB_MD_GC, 0);
2119         efx_writeo(efx, &reg, FR_AB_MD_CS);
2120
2121         /* Wait for data to be written */
2122         rc = falcon_gmii_wait(efx);
2123         if (rc) {
2124                 /* Abort the write operation */
2125                 EFX_POPULATE_OWORD_2(reg,
2126                                      FRF_AB_MD_WRC, 0,
2127                                      FRF_AB_MD_GC, 1);
2128                 efx_writeo(efx, &reg, FR_AB_MD_CS);
2129                 udelay(10);
2130         }
2131
2132  out:
2133         spin_unlock_bh(&efx->phy_lock);
2134         return rc;
2135 }
2136
2137 /* Read an MDIO register of a PHY connected to Falcon. */
2138 static int falcon_mdio_read(struct net_device *net_dev,
2139                             int prtad, int devad, u16 addr)
2140 {
2141         struct efx_nic *efx = netdev_priv(net_dev);
2142         efx_oword_t reg;
2143         int rc;
2144
2145         spin_lock_bh(&efx->phy_lock);
2146
2147         /* Check MDIO not currently being accessed */
2148         rc = falcon_gmii_wait(efx);
2149         if (rc)
2150                 goto out;
2151
2152         EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_PHY_ADR, addr);
2153         efx_writeo(efx, &reg, FR_AB_MD_PHY_ADR);
2154
2155         EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_PRT_ADR, prtad,
2156                              FRF_AB_MD_DEV_ADR, devad);
2157         efx_writeo(efx, &reg, FR_AB_MD_ID);
2158
2159         /* Request data to be read */
2160         EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_RDC, 1, FRF_AB_MD_GC, 0);
2161         efx_writeo(efx, &reg, FR_AB_MD_CS);
2162
2163         /* Wait for data to become available */
2164         rc = falcon_gmii_wait(efx);
2165         if (rc == 0) {
2166                 efx_reado(efx, &reg, FR_AB_MD_RXD);
2167                 rc = EFX_OWORD_FIELD(reg, FRF_AB_MD_RXD);
2168                 EFX_REGDUMP(efx, "read from MDIO %d register %d.%d, got %04x\n",
2169                             prtad, devad, addr, rc);
2170         } else {
2171                 /* Abort the read operation */
2172                 EFX_POPULATE_OWORD_2(reg,
2173                                      FRF_AB_MD_RIC, 0,
2174                                      FRF_AB_MD_GC, 1);
2175                 efx_writeo(efx, &reg, FR_AB_MD_CS);
2176
2177                 EFX_LOG(efx, "read from MDIO %d register %d.%d, got error %d\n",
2178                         prtad, devad, addr, rc);
2179         }
2180
2181  out:
2182         spin_unlock_bh(&efx->phy_lock);
2183         return rc;
2184 }
2185
2186 static void falcon_clock_mac(struct efx_nic *efx)
2187 {
2188         unsigned strap_val;
2189         efx_oword_t nic_stat;
2190
2191         /* Configure the NIC generated MAC clock correctly */
2192         efx_reado(efx, &nic_stat, FR_AB_NIC_STAT);
2193         strap_val = EFX_IS10G(efx) ? 5 : 3;
2194         if (falcon_rev(efx) >= FALCON_REV_B0) {
2195                 EFX_SET_OWORD_FIELD(nic_stat, FRF_BB_EE_STRAP_EN, 1);
2196                 EFX_SET_OWORD_FIELD(nic_stat, FRF_BB_EE_STRAP, strap_val);
2197                 efx_writeo(efx, &nic_stat, FR_AB_NIC_STAT);
2198         } else {
2199                 /* Falcon A1 does not support 1G/10G speed switching
2200                  * and must not be used with a PHY that does. */
2201                 BUG_ON(EFX_OWORD_FIELD(nic_stat, FRF_AB_STRAP_PINS) !=
2202                        strap_val);
2203         }
2204 }
2205
2206 int falcon_switch_mac(struct efx_nic *efx)
2207 {
2208         struct efx_mac_operations *old_mac_op = efx->mac_op;
2209         int rc = 0;
2210
2211         /* Don't try to fetch MAC stats while we're switching MACs */
2212         efx_stats_disable(efx);
2213
2214         /* Internal loopbacks override the phy speed setting */
2215         if (efx->loopback_mode == LOOPBACK_GMAC) {
2216                 efx->link_state.speed = 1000;
2217                 efx->link_state.fd = true;
2218         } else if (LOOPBACK_INTERNAL(efx)) {
2219                 efx->link_state.speed = 10000;
2220                 efx->link_state.fd = true;
2221         }
2222
2223         WARN_ON(!mutex_is_locked(&efx->mac_lock));
2224         efx->mac_op = (EFX_IS10G(efx) ?
2225                        &falcon_xmac_operations : &falcon_gmac_operations);
2226
2227         if (old_mac_op == efx->mac_op)
2228                 goto out;
2229
2230         falcon_clock_mac(efx);
2231
2232         EFX_LOG(efx, "selected %cMAC\n", EFX_IS10G(efx) ? 'X' : 'G');
2233         /* Not all macs support a mac-level link state */
2234         efx->mac_up = true;
2235
2236         rc = falcon_reset_macs(efx);
2237 out:
2238         efx_stats_enable(efx);
2239         return rc;
2240 }
2241
2242 /* This call is responsible for hooking in the MAC and PHY operations */
2243 int falcon_probe_port(struct efx_nic *efx)
2244 {
2245         int rc;
2246
2247         switch (efx->phy_type) {
2248         case PHY_TYPE_SFX7101:
2249                 efx->phy_op = &falcon_sfx7101_phy_ops;
2250                 break;
2251         case PHY_TYPE_SFT9001A:
2252         case PHY_TYPE_SFT9001B:
2253                 efx->phy_op = &falcon_sft9001_phy_ops;
2254                 break;
2255         case PHY_TYPE_QT2022C2:
2256         case PHY_TYPE_QT2025C:
2257                 efx->phy_op = &falcon_qt202x_phy_ops;
2258                 break;
2259         default:
2260                 EFX_ERR(efx, "Unknown PHY type %d\n",
2261                         efx->phy_type);
2262                 return -ENODEV;
2263         }
2264
2265         if (efx->phy_op->macs & EFX_XMAC)
2266                 efx->loopback_modes |= ((1 << LOOPBACK_XGMII) |
2267                                         (1 << LOOPBACK_XGXS) |
2268                                         (1 << LOOPBACK_XAUI));
2269         if (efx->phy_op->macs & EFX_GMAC)
2270                 efx->loopback_modes |= (1 << LOOPBACK_GMAC);
2271         efx->loopback_modes |= efx->phy_op->loopbacks;
2272
2273         /* Set up MDIO structure for PHY */
2274         efx->mdio.mmds = efx->phy_op->mmds;
2275         efx->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
2276         efx->mdio.mdio_read = falcon_mdio_read;
2277         efx->mdio.mdio_write = falcon_mdio_write;
2278
2279         /* Hardware flow ctrl. FalconA RX FIFO too small for pause generation */
2280         if (falcon_rev(efx) >= FALCON_REV_B0)
2281                 efx->wanted_fc = EFX_FC_RX | EFX_FC_TX;
2282         else
2283                 efx->wanted_fc = EFX_FC_RX;
2284
2285         /* Allocate buffer for stats */
2286         rc = falcon_alloc_buffer(efx, &efx->stats_buffer,
2287                                  FALCON_MAC_STATS_SIZE);
2288         if (rc)
2289                 return rc;
2290         EFX_LOG(efx, "stats buffer at %llx (virt %p phys %llx)\n",
2291                 (u64)efx->stats_buffer.dma_addr,
2292                 efx->stats_buffer.addr,
2293                 (u64)virt_to_phys(efx->stats_buffer.addr));
2294
2295         return 0;
2296 }
2297
2298 void falcon_remove_port(struct efx_nic *efx)
2299 {
2300         falcon_free_buffer(efx, &efx->stats_buffer);
2301 }
2302
2303 /**************************************************************************
2304  *
2305  * Multicast filtering
2306  *
2307  **************************************************************************
2308  */
2309
2310 void falcon_set_multicast_hash(struct efx_nic *efx)
2311 {
2312         union efx_multicast_hash *mc_hash = &efx->multicast_hash;
2313
2314         /* Broadcast packets go through the multicast hash filter.
2315          * ether_crc_le() of the broadcast address is 0xbe2612ff
2316          * so we always add bit 0xff to the mask.
2317          */
2318         set_bit_le(0xff, mc_hash->byte);
2319
2320         efx_writeo(efx, &mc_hash->oword[0], FR_AB_MAC_MC_HASH_REG0);
2321         efx_writeo(efx, &mc_hash->oword[1], FR_AB_MAC_MC_HASH_REG1);
2322 }
2323
2324
2325 /**************************************************************************
2326  *
2327  * Falcon test code
2328  *
2329  **************************************************************************/
2330
2331 int falcon_read_nvram(struct efx_nic *efx, struct falcon_nvconfig *nvconfig_out)
2332 {
2333         struct falcon_nvconfig *nvconfig;
2334         struct efx_spi_device *spi;
2335         void *region;
2336         int rc, magic_num, struct_ver;
2337         __le16 *word, *limit;
2338         u32 csum;
2339
2340         spi = efx->spi_flash ? efx->spi_flash : efx->spi_eeprom;
2341         if (!spi)
2342                 return -EINVAL;
2343
2344         region = kmalloc(FALCON_NVCONFIG_END, GFP_KERNEL);
2345         if (!region)
2346                 return -ENOMEM;
2347         nvconfig = region + FALCON_NVCONFIG_OFFSET;
2348
2349         mutex_lock(&efx->spi_lock);
2350         rc = falcon_spi_read(spi, 0, FALCON_NVCONFIG_END, NULL, region);
2351         mutex_unlock(&efx->spi_lock);
2352         if (rc) {
2353                 EFX_ERR(efx, "Failed to read %s\n",
2354                         efx->spi_flash ? "flash" : "EEPROM");
2355                 rc = -EIO;
2356                 goto out;
2357         }
2358
2359         magic_num = le16_to_cpu(nvconfig->board_magic_num);
2360         struct_ver = le16_to_cpu(nvconfig->board_struct_ver);
2361
2362         rc = -EINVAL;
2363         if (magic_num != FALCON_NVCONFIG_BOARD_MAGIC_NUM) {
2364                 EFX_ERR(efx, "NVRAM bad magic 0x%x\n", magic_num);
2365                 goto out;
2366         }
2367         if (struct_ver < 2) {
2368                 EFX_ERR(efx, "NVRAM has ancient version 0x%x\n", struct_ver);
2369                 goto out;
2370         } else if (struct_ver < 4) {
2371                 word = &nvconfig->board_magic_num;
2372                 limit = (__le16 *) (nvconfig + 1);
2373         } else {
2374                 word = region;
2375                 limit = region + FALCON_NVCONFIG_END;
2376         }
2377         for (csum = 0; word < limit; ++word)
2378                 csum += le16_to_cpu(*word);
2379
2380         if (~csum & 0xffff) {
2381                 EFX_ERR(efx, "NVRAM has incorrect checksum\n");
2382                 goto out;
2383         }
2384
2385         rc = 0;
2386         if (nvconfig_out)
2387                 memcpy(nvconfig_out, nvconfig, sizeof(*nvconfig));
2388
2389  out:
2390         kfree(region);
2391         return rc;
2392 }
2393
2394 /* Registers tested in the falcon register test */
2395 static struct {
2396         unsigned address;
2397         efx_oword_t mask;
2398 } efx_test_registers[] = {
2399         { FR_AZ_ADR_REGION,
2400           EFX_OWORD32(0x0001FFFF, 0x0001FFFF, 0x0001FFFF, 0x0001FFFF) },
2401         { FR_AZ_RX_CFG,
2402           EFX_OWORD32(0xFFFFFFFE, 0x00017FFF, 0x00000000, 0x00000000) },
2403         { FR_AZ_TX_CFG,
2404           EFX_OWORD32(0x7FFF0037, 0x00000000, 0x00000000, 0x00000000) },
2405         { FR_AZ_TX_RESERVED,
2406           EFX_OWORD32(0xFFFEFE80, 0x1FFFFFFF, 0x020000FE, 0x007FFFFF) },
2407         { FR_AB_MAC_CTRL,
2408           EFX_OWORD32(0xFFFF0000, 0x00000000, 0x00000000, 0x00000000) },
2409         { FR_AZ_SRM_TX_DC_CFG,
2410           EFX_OWORD32(0x001FFFFF, 0x00000000, 0x00000000, 0x00000000) },
2411         { FR_AZ_RX_DC_CFG,
2412           EFX_OWORD32(0x0000000F, 0x00000000, 0x00000000, 0x00000000) },
2413         { FR_AZ_RX_DC_PF_WM,
2414           EFX_OWORD32(0x000003FF, 0x00000000, 0x00000000, 0x00000000) },
2415         { FR_BZ_DP_CTRL,
2416           EFX_OWORD32(0x00000FFF, 0x00000000, 0x00000000, 0x00000000) },
2417         { FR_AB_GM_CFG2,
2418           EFX_OWORD32(0x00007337, 0x00000000, 0x00000000, 0x00000000) },
2419         { FR_AB_GMF_CFG0,
2420           EFX_OWORD32(0x00001F1F, 0x00000000, 0x00000000, 0x00000000) },
2421         { FR_AB_XM_GLB_CFG,
2422           EFX_OWORD32(0x00000C68, 0x00000000, 0x00000000, 0x00000000) },
2423         { FR_AB_XM_TX_CFG,
2424           EFX_OWORD32(0x00080164, 0x00000000, 0x00000000, 0x00000000) },
2425         { FR_AB_XM_RX_CFG,
2426           EFX_OWORD32(0x07100A0C, 0x00000000, 0x00000000, 0x00000000) },
2427         { FR_AB_XM_RX_PARAM,
2428           EFX_OWORD32(0x00001FF8, 0x00000000, 0x00000000, 0x00000000) },
2429         { FR_AB_XM_FC,
2430           EFX_OWORD32(0xFFFF0001, 0x00000000, 0x00000000, 0x00000000) },
2431         { FR_AB_XM_ADR_LO,
2432           EFX_OWORD32(0xFFFFFFFF, 0x00000000, 0x00000000, 0x00000000) },
2433         { FR_AB_XX_SD_CTL,
2434           EFX_OWORD32(0x0003FF0F, 0x00000000, 0x00000000, 0x00000000) },
2435 };
2436
2437 static bool efx_masked_compare_oword(const efx_oword_t *a, const efx_oword_t *b,
2438                                      const efx_oword_t *mask)
2439 {
2440         return ((a->u64[0] ^ b->u64[0]) & mask->u64[0]) ||
2441                 ((a->u64[1] ^ b->u64[1]) & mask->u64[1]);
2442 }
2443
2444 int falcon_test_registers(struct efx_nic *efx)
2445 {
2446         unsigned address = 0, i, j;
2447         efx_oword_t mask, imask, original, reg, buf;
2448
2449         /* Falcon should be in loopback to isolate the XMAC from the PHY */
2450         WARN_ON(!LOOPBACK_INTERNAL(efx));
2451
2452         for (i = 0; i < ARRAY_SIZE(efx_test_registers); ++i) {
2453                 address = efx_test_registers[i].address;
2454                 mask = imask = efx_test_registers[i].mask;
2455                 EFX_INVERT_OWORD(imask);
2456
2457                 efx_reado(efx, &original, address);
2458
2459                 /* bit sweep on and off */
2460                 for (j = 0; j < 128; j++) {
2461                         if (!EFX_EXTRACT_OWORD32(mask, j, j))
2462                                 continue;
2463
2464                         /* Test this testable bit can be set in isolation */
2465                         EFX_AND_OWORD(reg, original, mask);
2466                         EFX_SET_OWORD32(reg, j, j, 1);
2467
2468                         efx_writeo(efx, &reg, address);
2469                         efx_reado(efx, &buf, address);
2470
2471                         if (efx_masked_compare_oword(&reg, &buf, &mask))
2472                                 goto fail;
2473
2474                         /* Test this testable bit can be cleared in isolation */
2475                         EFX_OR_OWORD(reg, original, mask);
2476                         EFX_SET_OWORD32(reg, j, j, 0);
2477
2478                         efx_writeo(efx, &reg, address);
2479                         efx_reado(efx, &buf, address);
2480
2481                         if (efx_masked_compare_oword(&reg, &buf, &mask))
2482                                 goto fail;
2483                 }
2484
2485                 efx_writeo(efx, &original, address);
2486         }
2487
2488         return 0;
2489
2490 fail:
2491         EFX_ERR(efx, "wrote "EFX_OWORD_FMT" read "EFX_OWORD_FMT
2492                 " at address 0x%x mask "EFX_OWORD_FMT"\n", EFX_OWORD_VAL(reg),
2493                 EFX_OWORD_VAL(buf), address, EFX_OWORD_VAL(mask));
2494         return -EIO;
2495 }
2496
2497 /**************************************************************************
2498  *
2499  * Device reset
2500  *
2501  **************************************************************************
2502  */
2503
2504 /* Resets NIC to known state.  This routine must be called in process
2505  * context and is allowed to sleep. */
2506 int falcon_reset_hw(struct efx_nic *efx, enum reset_type method)
2507 {
2508         struct falcon_nic_data *nic_data = efx->nic_data;
2509         efx_oword_t glb_ctl_reg_ker;
2510         int rc;
2511
2512         EFX_LOG(efx, "performing %s hardware reset\n", RESET_TYPE(method));
2513
2514         /* Initiate device reset */
2515         if (method == RESET_TYPE_WORLD) {
2516                 rc = pci_save_state(efx->pci_dev);
2517                 if (rc) {
2518                         EFX_ERR(efx, "failed to backup PCI state of primary "
2519                                 "function prior to hardware reset\n");
2520                         goto fail1;
2521                 }
2522                 if (FALCON_IS_DUAL_FUNC(efx)) {
2523                         rc = pci_save_state(nic_data->pci_dev2);
2524                         if (rc) {
2525                                 EFX_ERR(efx, "failed to backup PCI state of "
2526                                         "secondary function prior to "
2527                                         "hardware reset\n");
2528                                 goto fail2;
2529                         }
2530                 }
2531
2532                 EFX_POPULATE_OWORD_2(glb_ctl_reg_ker,
2533                                      FRF_AB_EXT_PHY_RST_DUR,
2534                                      FFE_AB_EXT_PHY_RST_DUR_10240US,
2535                                      FRF_AB_SWRST, 1);
2536         } else {
2537                 EFX_POPULATE_OWORD_7(glb_ctl_reg_ker,
2538                                      /* exclude PHY from "invisible" reset */
2539                                      FRF_AB_EXT_PHY_RST_CTL,
2540                                      method == RESET_TYPE_INVISIBLE,
2541                                      /* exclude EEPROM/flash and PCIe */
2542                                      FRF_AB_PCIE_CORE_RST_CTL, 1,
2543                                      FRF_AB_PCIE_NSTKY_RST_CTL, 1,
2544                                      FRF_AB_PCIE_SD_RST_CTL, 1,
2545                                      FRF_AB_EE_RST_CTL, 1,
2546                                      FRF_AB_EXT_PHY_RST_DUR,
2547                                      FFE_AB_EXT_PHY_RST_DUR_10240US,
2548                                      FRF_AB_SWRST, 1);
2549         }
2550         efx_writeo(efx, &glb_ctl_reg_ker, FR_AB_GLB_CTL);
2551
2552         EFX_LOG(efx, "waiting for hardware reset\n");
2553         schedule_timeout_uninterruptible(HZ / 20);
2554
2555         /* Restore PCI configuration if needed */
2556         if (method == RESET_TYPE_WORLD) {
2557                 if (FALCON_IS_DUAL_FUNC(efx)) {
2558                         rc = pci_restore_state(nic_data->pci_dev2);
2559                         if (rc) {
2560                                 EFX_ERR(efx, "failed to restore PCI config for "
2561                                         "the secondary function\n");
2562                                 goto fail3;
2563                         }
2564                 }
2565                 rc = pci_restore_state(efx->pci_dev);
2566                 if (rc) {
2567                         EFX_ERR(efx, "failed to restore PCI config for the "
2568                                 "primary function\n");
2569                         goto fail4;
2570                 }
2571                 EFX_LOG(efx, "successfully restored PCI config\n");
2572         }
2573
2574         /* Assert that reset complete */
2575         efx_reado(efx, &glb_ctl_reg_ker, FR_AB_GLB_CTL);
2576         if (EFX_OWORD_FIELD(glb_ctl_reg_ker, FRF_AB_SWRST) != 0) {
2577                 rc = -ETIMEDOUT;
2578                 EFX_ERR(efx, "timed out waiting for hardware reset\n");
2579                 goto fail5;
2580         }
2581         EFX_LOG(efx, "hardware reset complete\n");
2582
2583         return 0;
2584
2585         /* pci_save_state() and pci_restore_state() MUST be called in pairs */
2586 fail2:
2587 fail3:
2588         pci_restore_state(efx->pci_dev);
2589 fail1:
2590 fail4:
2591 fail5:
2592         return rc;
2593 }
2594
2595 /* Zeroes out the SRAM contents.  This routine must be called in
2596  * process context and is allowed to sleep.
2597  */
2598 static int falcon_reset_sram(struct efx_nic *efx)
2599 {
2600         efx_oword_t srm_cfg_reg_ker, gpio_cfg_reg_ker;
2601         int count;
2602
2603         /* Set the SRAM wake/sleep GPIO appropriately. */
2604         efx_reado(efx, &gpio_cfg_reg_ker, FR_AB_GPIO_CTL);
2605         EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, FRF_AB_GPIO1_OEN, 1);
2606         EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, FRF_AB_GPIO1_OUT, 1);
2607         efx_writeo(efx, &gpio_cfg_reg_ker, FR_AB_GPIO_CTL);
2608
2609         /* Initiate SRAM reset */
2610         EFX_POPULATE_OWORD_2(srm_cfg_reg_ker,
2611                              FRF_AZ_SRM_INIT_EN, 1,
2612                              FRF_AZ_SRM_NB_SZ, 0);
2613         efx_writeo(efx, &srm_cfg_reg_ker, FR_AZ_SRM_CFG);
2614
2615         /* Wait for SRAM reset to complete */
2616         count = 0;
2617         do {
2618                 EFX_LOG(efx, "waiting for SRAM reset (attempt %d)...\n", count);
2619
2620                 /* SRAM reset is slow; expect around 16ms */
2621                 schedule_timeout_uninterruptible(HZ / 50);
2622
2623                 /* Check for reset complete */
2624                 efx_reado(efx, &srm_cfg_reg_ker, FR_AZ_SRM_CFG);
2625                 if (!EFX_OWORD_FIELD(srm_cfg_reg_ker, FRF_AZ_SRM_INIT_EN)) {
2626                         EFX_LOG(efx, "SRAM reset complete\n");
2627
2628                         return 0;
2629                 }
2630         } while (++count < 20); /* wait upto 0.4 sec */
2631
2632         EFX_ERR(efx, "timed out waiting for SRAM reset\n");
2633         return -ETIMEDOUT;
2634 }
2635
2636 static int falcon_spi_device_init(struct efx_nic *efx,
2637                                   struct efx_spi_device **spi_device_ret,
2638                                   unsigned int device_id, u32 device_type)
2639 {
2640         struct efx_spi_device *spi_device;
2641
2642         if (device_type != 0) {
2643                 spi_device = kzalloc(sizeof(*spi_device), GFP_KERNEL);
2644                 if (!spi_device)
2645                         return -ENOMEM;
2646                 spi_device->device_id = device_id;
2647                 spi_device->size =
2648                         1 << SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_SIZE);
2649                 spi_device->addr_len =
2650                         SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_ADDR_LEN);
2651                 spi_device->munge_address = (spi_device->size == 1 << 9 &&
2652                                              spi_device->addr_len == 1);
2653                 spi_device->erase_command =
2654                         SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_ERASE_CMD);
2655                 spi_device->erase_size =
2656                         1 << SPI_DEV_TYPE_FIELD(device_type,
2657                                                 SPI_DEV_TYPE_ERASE_SIZE);
2658                 spi_device->block_size =
2659                         1 << SPI_DEV_TYPE_FIELD(device_type,
2660                                                 SPI_DEV_TYPE_BLOCK_SIZE);
2661
2662                 spi_device->efx = efx;
2663         } else {
2664                 spi_device = NULL;
2665         }
2666
2667         kfree(*spi_device_ret);
2668         *spi_device_ret = spi_device;
2669         return 0;
2670 }
2671
2672
2673 static void falcon_remove_spi_devices(struct efx_nic *efx)
2674 {
2675         kfree(efx->spi_eeprom);
2676         efx->spi_eeprom = NULL;
2677         kfree(efx->spi_flash);
2678         efx->spi_flash = NULL;
2679 }
2680
2681 /* Extract non-volatile configuration */
2682 static int falcon_probe_nvconfig(struct efx_nic *efx)
2683 {
2684         struct falcon_nvconfig *nvconfig;
2685         int board_rev;
2686         int rc;
2687
2688         nvconfig = kmalloc(sizeof(*nvconfig), GFP_KERNEL);
2689         if (!nvconfig)
2690                 return -ENOMEM;
2691
2692         rc = falcon_read_nvram(efx, nvconfig);
2693         if (rc == -EINVAL) {
2694                 EFX_ERR(efx, "NVRAM is invalid therefore using defaults\n");
2695                 efx->phy_type = PHY_TYPE_NONE;
2696                 efx->mdio.prtad = MDIO_PRTAD_NONE;
2697                 board_rev = 0;
2698                 rc = 0;
2699         } else if (rc) {
2700                 goto fail1;
2701         } else {
2702                 struct falcon_nvconfig_board_v2 *v2 = &nvconfig->board_v2;
2703                 struct falcon_nvconfig_board_v3 *v3 = &nvconfig->board_v3;
2704
2705                 efx->phy_type = v2->port0_phy_type;
2706                 efx->mdio.prtad = v2->port0_phy_addr;
2707                 board_rev = le16_to_cpu(v2->board_revision);
2708
2709                 if (le16_to_cpu(nvconfig->board_struct_ver) >= 3) {
2710                         rc = falcon_spi_device_init(
2711                                 efx, &efx->spi_flash, FFE_AB_SPI_DEVICE_FLASH,
2712                                 le32_to_cpu(v3->spi_device_type
2713                                             [FFE_AB_SPI_DEVICE_FLASH]));
2714                         if (rc)
2715                                 goto fail2;
2716                         rc = falcon_spi_device_init(
2717                                 efx, &efx->spi_eeprom, FFE_AB_SPI_DEVICE_EEPROM,
2718                                 le32_to_cpu(v3->spi_device_type
2719                                             [FFE_AB_SPI_DEVICE_EEPROM]));
2720                         if (rc)
2721                                 goto fail2;
2722                 }
2723         }
2724
2725         /* Read the MAC addresses */
2726         memcpy(efx->mac_address, nvconfig->mac_address[0], ETH_ALEN);
2727
2728         EFX_LOG(efx, "PHY is %d phy_id %d\n", efx->phy_type, efx->mdio.prtad);
2729
2730         falcon_probe_board(efx, board_rev);
2731
2732         kfree(nvconfig);
2733         return 0;
2734
2735  fail2:
2736         falcon_remove_spi_devices(efx);
2737  fail1:
2738         kfree(nvconfig);
2739         return rc;
2740 }
2741
2742 /* Probe the NIC variant (revision, ASIC vs FPGA, function count, port
2743  * count, port speed).  Set workaround and feature flags accordingly.
2744  */
2745 static int falcon_probe_nic_variant(struct efx_nic *efx)
2746 {
2747         efx_oword_t altera_build;
2748         efx_oword_t nic_stat;
2749
2750         efx_reado(efx, &altera_build, FR_AZ_ALTERA_BUILD);
2751         if (EFX_OWORD_FIELD(altera_build, FRF_AZ_ALTERA_BUILD_VER)) {
2752                 EFX_ERR(efx, "Falcon FPGA not supported\n");
2753                 return -ENODEV;
2754         }
2755
2756         efx_reado(efx, &nic_stat, FR_AB_NIC_STAT);
2757
2758         switch (falcon_rev(efx)) {
2759         case FALCON_REV_A0:
2760         case 0xff:
2761                 EFX_ERR(efx, "Falcon rev A0 not supported\n");
2762                 return -ENODEV;
2763
2764         case FALCON_REV_A1:
2765                 if (EFX_OWORD_FIELD(nic_stat, FRF_AA_STRAP_PCIE) == 0) {
2766                         EFX_ERR(efx, "Falcon rev A1 PCI-X not supported\n");
2767                         return -ENODEV;
2768                 }
2769                 break;
2770
2771         case FALCON_REV_B0:
2772                 break;
2773
2774         default:
2775                 EFX_ERR(efx, "Unknown Falcon rev %d\n", falcon_rev(efx));
2776                 return -ENODEV;
2777         }
2778
2779         /* Initial assumed speed */
2780         efx->link_state.speed = EFX_OWORD_FIELD(nic_stat, FRF_AB_STRAP_10G) ? 10000 : 1000;
2781
2782         return 0;
2783 }
2784
2785 /* Probe all SPI devices on the NIC */
2786 static void falcon_probe_spi_devices(struct efx_nic *efx)
2787 {
2788         efx_oword_t nic_stat, gpio_ctl, ee_vpd_cfg;
2789         int boot_dev;
2790
2791         efx_reado(efx, &gpio_ctl, FR_AB_GPIO_CTL);
2792         efx_reado(efx, &nic_stat, FR_AB_NIC_STAT);
2793         efx_reado(efx, &ee_vpd_cfg, FR_AB_EE_VPD_CFG0);
2794
2795         if (EFX_OWORD_FIELD(gpio_ctl, FRF_AB_GPIO3_PWRUP_VALUE)) {
2796                 boot_dev = (EFX_OWORD_FIELD(nic_stat, FRF_AB_SF_PRST) ?
2797                             FFE_AB_SPI_DEVICE_FLASH : FFE_AB_SPI_DEVICE_EEPROM);
2798                 EFX_LOG(efx, "Booted from %s\n",
2799                         boot_dev == FFE_AB_SPI_DEVICE_FLASH ? "flash" : "EEPROM");
2800         } else {
2801                 /* Disable VPD and set clock dividers to safe
2802                  * values for initial programming. */
2803                 boot_dev = -1;
2804                 EFX_LOG(efx, "Booted from internal ASIC settings;"
2805                         " setting SPI config\n");
2806                 EFX_POPULATE_OWORD_3(ee_vpd_cfg, FRF_AB_EE_VPD_EN, 0,
2807                                      /* 125 MHz / 7 ~= 20 MHz */
2808                                      FRF_AB_EE_SF_CLOCK_DIV, 7,
2809                                      /* 125 MHz / 63 ~= 2 MHz */
2810                                      FRF_AB_EE_EE_CLOCK_DIV, 63);
2811                 efx_writeo(efx, &ee_vpd_cfg, FR_AB_EE_VPD_CFG0);
2812         }
2813
2814         if (boot_dev == FFE_AB_SPI_DEVICE_FLASH)
2815                 falcon_spi_device_init(efx, &efx->spi_flash,
2816                                        FFE_AB_SPI_DEVICE_FLASH,
2817                                        default_flash_type);
2818         if (boot_dev == FFE_AB_SPI_DEVICE_EEPROM)
2819                 falcon_spi_device_init(efx, &efx->spi_eeprom,
2820                                        FFE_AB_SPI_DEVICE_EEPROM,
2821                                        large_eeprom_type);
2822 }
2823
2824 int falcon_probe_nic(struct efx_nic *efx)
2825 {
2826         struct falcon_nic_data *nic_data;
2827         struct falcon_board *board;
2828         int rc;
2829
2830         /* Allocate storage for hardware specific data */
2831         nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL);
2832         if (!nic_data)
2833                 return -ENOMEM;
2834         efx->nic_data = nic_data;
2835
2836         /* Determine number of ports etc. */
2837         rc = falcon_probe_nic_variant(efx);
2838         if (rc)
2839                 goto fail1;
2840
2841         /* Probe secondary function if expected */
2842         if (FALCON_IS_DUAL_FUNC(efx)) {
2843                 struct pci_dev *dev = pci_dev_get(efx->pci_dev);
2844
2845                 while ((dev = pci_get_device(EFX_VENDID_SFC, FALCON_A_S_DEVID,
2846                                              dev))) {
2847                         if (dev->bus == efx->pci_dev->bus &&
2848                             dev->devfn == efx->pci_dev->devfn + 1) {
2849                                 nic_data->pci_dev2 = dev;
2850                                 break;
2851                         }
2852                 }
2853                 if (!nic_data->pci_dev2) {
2854                         EFX_ERR(efx, "failed to find secondary function\n");
2855                         rc = -ENODEV;
2856                         goto fail2;
2857                 }
2858         }
2859
2860         /* Now we can reset the NIC */
2861         rc = falcon_reset_hw(efx, RESET_TYPE_ALL);
2862         if (rc) {
2863                 EFX_ERR(efx, "failed to reset NIC\n");
2864                 goto fail3;
2865         }
2866
2867         /* Allocate memory for INT_KER */
2868         rc = falcon_alloc_buffer(efx, &efx->irq_status, sizeof(efx_oword_t));
2869         if (rc)
2870                 goto fail4;
2871         BUG_ON(efx->irq_status.dma_addr & 0x0f);
2872
2873         EFX_LOG(efx, "INT_KER at %llx (virt %p phys %llx)\n",
2874                 (u64)efx->irq_status.dma_addr,
2875                 efx->irq_status.addr, (u64)virt_to_phys(efx->irq_status.addr));
2876
2877         falcon_probe_spi_devices(efx);
2878
2879         /* Read in the non-volatile configuration */
2880         rc = falcon_probe_nvconfig(efx);
2881         if (rc)
2882                 goto fail5;
2883
2884         /* Initialise I2C adapter */
2885         board = falcon_board(efx);
2886         board->i2c_adap.owner = THIS_MODULE;
2887         board->i2c_data = falcon_i2c_bit_operations;
2888         board->i2c_data.data = efx;
2889         board->i2c_adap.algo_data = &board->i2c_data;
2890         board->i2c_adap.dev.parent = &efx->pci_dev->dev;
2891         strlcpy(board->i2c_adap.name, "SFC4000 GPIO",
2892                 sizeof(board->i2c_adap.name));
2893         rc = i2c_bit_add_bus(&board->i2c_adap);
2894         if (rc)
2895                 goto fail5;
2896
2897         rc = falcon_board(efx)->type->init(efx);
2898         if (rc) {
2899                 EFX_ERR(efx, "failed to initialise board\n");
2900                 goto fail6;
2901         }
2902
2903         return 0;
2904
2905  fail6:
2906         BUG_ON(i2c_del_adapter(&board->i2c_adap));
2907         memset(&board->i2c_adap, 0, sizeof(board->i2c_adap));
2908  fail5:
2909         falcon_remove_spi_devices(efx);
2910         falcon_free_buffer(efx, &efx->irq_status);
2911  fail4:
2912  fail3:
2913         if (nic_data->pci_dev2) {
2914                 pci_dev_put(nic_data->pci_dev2);
2915                 nic_data->pci_dev2 = NULL;
2916         }
2917  fail2:
2918  fail1:
2919         kfree(efx->nic_data);
2920         return rc;
2921 }
2922
2923 static void falcon_init_rx_cfg(struct efx_nic *efx)
2924 {
2925         /* Prior to Siena the RX DMA engine will split each frame at
2926          * intervals of RX_USR_BUF_SIZE (32-byte units). We set it to
2927          * be so large that that never happens. */
2928         const unsigned huge_buf_size = (3 * 4096) >> 5;
2929         /* RX control FIFO thresholds (32 entries) */
2930         const unsigned ctrl_xon_thr = 20;
2931         const unsigned ctrl_xoff_thr = 25;
2932         /* RX data FIFO thresholds (256-byte units; size varies) */
2933         int data_xon_thr = rx_xon_thresh_bytes >> 8;
2934         int data_xoff_thr = rx_xoff_thresh_bytes >> 8;
2935         efx_oword_t reg;
2936
2937         efx_reado(efx, &reg, FR_AZ_RX_CFG);
2938         if (falcon_rev(efx) <= FALCON_REV_A1) {
2939                 /* Data FIFO size is 5.5K */
2940                 if (data_xon_thr < 0)
2941                         data_xon_thr = 512 >> 8;
2942                 if (data_xoff_thr < 0)
2943                         data_xoff_thr = 2048 >> 8;
2944                 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_DESC_PUSH_EN, 0);
2945                 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_USR_BUF_SIZE,
2946                                     huge_buf_size);
2947                 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XON_MAC_TH, data_xon_thr);
2948                 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XOFF_MAC_TH, data_xoff_thr);
2949                 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XON_TX_TH, ctrl_xon_thr);
2950                 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XOFF_TX_TH, ctrl_xoff_thr);
2951         } else {
2952                 /* Data FIFO size is 80K; register fields moved */
2953                 if (data_xon_thr < 0)
2954                         data_xon_thr = 27648 >> 8; /* ~3*max MTU */
2955                 if (data_xoff_thr < 0)
2956                         data_xoff_thr = 54272 >> 8; /* ~80Kb - 3*max MTU */
2957                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_DESC_PUSH_EN, 0);
2958                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_USR_BUF_SIZE,
2959                                     huge_buf_size);
2960                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XON_MAC_TH, data_xon_thr);
2961                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XOFF_MAC_TH, data_xoff_thr);
2962                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XON_TX_TH, ctrl_xon_thr);
2963                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XOFF_TX_TH, ctrl_xoff_thr);
2964                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 1);
2965         }
2966         efx_writeo(efx, &reg, FR_AZ_RX_CFG);
2967 }
2968
2969 /* This call performs hardware-specific global initialisation, such as
2970  * defining the descriptor cache sizes and number of RSS channels.
2971  * It does not set up any buffers, descriptor rings or event queues.
2972  */
2973 int falcon_init_nic(struct efx_nic *efx)
2974 {
2975         efx_oword_t temp;
2976         int rc;
2977
2978         /* Use on-chip SRAM */
2979         efx_reado(efx, &temp, FR_AB_NIC_STAT);
2980         EFX_SET_OWORD_FIELD(temp, FRF_AB_ONCHIP_SRAM, 1);
2981         efx_writeo(efx, &temp, FR_AB_NIC_STAT);
2982
2983         /* Set the source of the GMAC clock */
2984         if (falcon_rev(efx) == FALCON_REV_B0) {
2985                 efx_reado(efx, &temp, FR_AB_GPIO_CTL);
2986                 EFX_SET_OWORD_FIELD(temp, FRF_AB_USE_NIC_CLK, true);
2987                 efx_writeo(efx, &temp, FR_AB_GPIO_CTL);
2988         }
2989
2990         /* Select the correct MAC */
2991         falcon_clock_mac(efx);
2992
2993         rc = falcon_reset_sram(efx);
2994         if (rc)
2995                 return rc;
2996
2997         /* Set positions of descriptor caches in SRAM. */
2998         EFX_POPULATE_OWORD_1(temp, FRF_AZ_SRM_TX_DC_BASE_ADR, TX_DC_BASE / 8);
2999         efx_writeo(efx, &temp, FR_AZ_SRM_TX_DC_CFG);
3000         EFX_POPULATE_OWORD_1(temp, FRF_AZ_SRM_RX_DC_BASE_ADR, RX_DC_BASE / 8);
3001         efx_writeo(efx, &temp, FR_AZ_SRM_RX_DC_CFG);
3002
3003         /* Set TX descriptor cache size. */
3004         BUILD_BUG_ON(TX_DC_ENTRIES != (8 << TX_DC_ENTRIES_ORDER));
3005         EFX_POPULATE_OWORD_1(temp, FRF_AZ_TX_DC_SIZE, TX_DC_ENTRIES_ORDER);
3006         efx_writeo(efx, &temp, FR_AZ_TX_DC_CFG);
3007
3008         /* Set RX descriptor cache size.  Set low watermark to size-8, as
3009          * this allows most efficient prefetching.
3010          */
3011         BUILD_BUG_ON(RX_DC_ENTRIES != (8 << RX_DC_ENTRIES_ORDER));
3012         EFX_POPULATE_OWORD_1(temp, FRF_AZ_RX_DC_SIZE, RX_DC_ENTRIES_ORDER);
3013         efx_writeo(efx, &temp, FR_AZ_RX_DC_CFG);
3014         EFX_POPULATE_OWORD_1(temp, FRF_AZ_RX_DC_PF_LWM, RX_DC_ENTRIES - 8);
3015         efx_writeo(efx, &temp, FR_AZ_RX_DC_PF_WM);
3016
3017         /* Clear the parity enables on the TX data fifos as
3018          * they produce false parity errors because of timing issues
3019          */
3020         if (EFX_WORKAROUND_5129(efx)) {
3021                 efx_reado(efx, &temp, FR_AZ_CSR_SPARE);
3022                 EFX_SET_OWORD_FIELD(temp, FRF_AB_MEM_PERR_EN_TX_DATA, 0);
3023                 efx_writeo(efx, &temp, FR_AZ_CSR_SPARE);
3024         }
3025
3026         /* Enable all the genuinely fatal interrupts.  (They are still
3027          * masked by the overall interrupt mask, controlled by
3028          * falcon_interrupts()).
3029          *
3030          * Note: All other fatal interrupts are enabled
3031          */
3032         EFX_POPULATE_OWORD_3(temp,
3033                              FRF_AZ_ILL_ADR_INT_KER_EN, 1,
3034                              FRF_AZ_RBUF_OWN_INT_KER_EN, 1,
3035                              FRF_AZ_TBUF_OWN_INT_KER_EN, 1);
3036         EFX_INVERT_OWORD(temp);
3037         efx_writeo(efx, &temp, FR_AZ_FATAL_INTR_KER);
3038
3039         if (EFX_WORKAROUND_7244(efx)) {
3040                 efx_reado(efx, &temp, FR_BZ_RX_FILTER_CTL);
3041                 EFX_SET_OWORD_FIELD(temp, FRF_BZ_UDP_FULL_SRCH_LIMIT, 8);
3042                 EFX_SET_OWORD_FIELD(temp, FRF_BZ_UDP_WILD_SRCH_LIMIT, 8);
3043                 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TCP_FULL_SRCH_LIMIT, 8);
3044                 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TCP_WILD_SRCH_LIMIT, 8);
3045                 efx_writeo(efx, &temp, FR_BZ_RX_FILTER_CTL);
3046         }
3047
3048         falcon_setup_rss_indir_table(efx);
3049
3050         /* XXX This is documented only for Falcon A0/A1 */
3051         /* Setup RX.  Wait for descriptor is broken and must
3052          * be disabled.  RXDP recovery shouldn't be needed, but is.
3053          */
3054         efx_reado(efx, &temp, FR_AA_RX_SELF_RST);
3055         EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_NODESC_WAIT_DIS, 1);
3056         EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_SELF_RST_EN, 1);
3057         if (EFX_WORKAROUND_5583(efx))
3058                 EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_ISCSI_DIS, 1);
3059         efx_writeo(efx, &temp, FR_AA_RX_SELF_RST);
3060
3061         /* Disable the ugly timer-based TX DMA backoff and allow TX DMA to be
3062          * controlled by the RX FIFO fill level. Set arbitration to one pkt/Q.
3063          */
3064         efx_reado(efx, &temp, FR_AZ_TX_RESERVED);
3065         EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_RX_SPACER, 0xfe);
3066         EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_RX_SPACER_EN, 1);
3067         EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_ONE_PKT_PER_Q, 1);
3068         EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_PUSH_EN, 0);
3069         EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_DIS_NON_IP_EV, 1);
3070         /* Enable SW_EV to inherit in char driver - assume harmless here */
3071         EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_SOFT_EVT_EN, 1);
3072         /* Prefetch threshold 2 => fetch when descriptor cache half empty */
3073         EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_PREF_THRESHOLD, 2);
3074         /* Squash TX of packets of 16 bytes or less */
3075         if (falcon_rev(efx) >= FALCON_REV_B0 && EFX_WORKAROUND_9141(efx))
3076                 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TX_FLUSH_MIN_LEN_EN, 1);
3077         efx_writeo(efx, &temp, FR_AZ_TX_RESERVED);
3078
3079         /* Do not enable TX_NO_EOP_DISC_EN, since it limits packets to 16
3080          * descriptors (which is bad).
3081          */
3082         efx_reado(efx, &temp, FR_AZ_TX_CFG);
3083         EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_NO_EOP_DISC_EN, 0);
3084         efx_writeo(efx, &temp, FR_AZ_TX_CFG);
3085
3086         falcon_init_rx_cfg(efx);
3087
3088         /* Set destination of both TX and RX Flush events */
3089         if (falcon_rev(efx) >= FALCON_REV_B0) {
3090                 EFX_POPULATE_OWORD_1(temp, FRF_BZ_FLS_EVQ_ID, 0);
3091                 efx_writeo(efx, &temp, FR_BZ_DP_CTRL);
3092         }
3093
3094         return 0;
3095 }
3096
3097 void falcon_remove_nic(struct efx_nic *efx)
3098 {
3099         struct falcon_nic_data *nic_data = efx->nic_data;
3100         struct falcon_board *board = falcon_board(efx);
3101         int rc;
3102
3103         board->type->fini(efx);
3104
3105         /* Remove I2C adapter and clear it in preparation for a retry */
3106         rc = i2c_del_adapter(&board->i2c_adap);
3107         BUG_ON(rc);
3108         memset(&board->i2c_adap, 0, sizeof(board->i2c_adap));
3109
3110         falcon_remove_spi_devices(efx);
3111         falcon_free_buffer(efx, &efx->irq_status);
3112
3113         falcon_reset_hw(efx, RESET_TYPE_ALL);
3114
3115         /* Release the second function after the reset */
3116         if (nic_data->pci_dev2) {
3117                 pci_dev_put(nic_data->pci_dev2);
3118                 nic_data->pci_dev2 = NULL;
3119         }
3120
3121         /* Tear down the private nic state */
3122         kfree(efx->nic_data);
3123         efx->nic_data = NULL;
3124 }
3125
3126 void falcon_update_nic_stats(struct efx_nic *efx)
3127 {
3128         efx_oword_t cnt;
3129
3130         efx_reado(efx, &cnt, FR_AZ_RX_NODESC_DROP);
3131         efx->n_rx_nodesc_drop_cnt +=
3132                 EFX_OWORD_FIELD(cnt, FRF_AB_RX_NODESC_DROP_CNT);
3133 }
3134
3135 /**************************************************************************
3136  *
3137  * Revision-dependent attributes used by efx.c
3138  *
3139  **************************************************************************
3140  */
3141
3142 struct efx_nic_type falcon_a_nic_type = {
3143         .mem_map_size = 0x20000,
3144         .txd_ptr_tbl_base = FR_AA_TX_DESC_PTR_TBL_KER,
3145         .rxd_ptr_tbl_base = FR_AA_RX_DESC_PTR_TBL_KER,
3146         .buf_tbl_base = FR_AA_BUF_FULL_TBL_KER,
3147         .evq_ptr_tbl_base = FR_AA_EVQ_PTR_TBL_KER,
3148         .evq_rptr_tbl_base = FR_AA_EVQ_RPTR_KER,
3149         .max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH),
3150         .rx_buffer_padding = 0x24,
3151         .max_interrupt_mode = EFX_INT_MODE_MSI,
3152         .phys_addr_channels = 4,
3153 };
3154
3155 struct efx_nic_type falcon_b_nic_type = {
3156         /* Map everything up to and including the RSS indirection
3157          * table.  Don't map MSI-X table, MSI-X PBA since Linux
3158          * requires that they not be mapped.  */
3159         .mem_map_size = (FR_BZ_RX_INDIRECTION_TBL +
3160                          FR_BZ_RX_INDIRECTION_TBL_STEP *
3161                          FR_BZ_RX_INDIRECTION_TBL_ROWS),
3162         .txd_ptr_tbl_base = FR_BZ_TX_DESC_PTR_TBL,
3163         .rxd_ptr_tbl_base = FR_BZ_RX_DESC_PTR_TBL,
3164         .buf_tbl_base = FR_BZ_BUF_FULL_TBL,
3165         .evq_ptr_tbl_base = FR_BZ_EVQ_PTR_TBL,
3166         .evq_rptr_tbl_base = FR_BZ_EVQ_RPTR,
3167         .max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH),
3168         .rx_buffer_padding = 0,
3169         .max_interrupt_mode = EFX_INT_MODE_MSIX,
3170         .phys_addr_channels = 32, /* Hardware limit is 64, but the legacy
3171                                    * interrupt handler only supports 32
3172                                    * channels */
3173 };
3174