1 /****************************************************************************
2 * Driver for Solarflare Solarstorm network controllers and boards
3 * Copyright 2005-2006 Fen Systems Ltd.
4 * Copyright 2006-2009 Solarflare Communications Inc.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
11 #include <linux/bitops.h>
12 #include <linux/delay.h>
13 #include <linux/pci.h>
14 #include <linux/module.h>
15 #include <linux/seq_file.h>
16 #include <linux/i2c.h>
17 #include <linux/mii.h>
18 #include <linux/slab.h>
19 #include "net_driver.h"
29 #include "workarounds.h"
31 /* Hardware control for SFC4000 (aka Falcon). */
33 static const unsigned int
34 /* "Large" EEPROM device: Atmel AT25640 or similar
35 * 8 KB, 16-bit address, 32 B write block */
36 large_eeprom_type = ((13 << SPI_DEV_TYPE_SIZE_LBN)
37 | (2 << SPI_DEV_TYPE_ADDR_LEN_LBN)
38 | (5 << SPI_DEV_TYPE_BLOCK_SIZE_LBN)),
39 /* Default flash device: Atmel AT25F1024
40 * 128 KB, 24-bit address, 32 KB erase block, 256 B write block */
41 default_flash_type = ((17 << SPI_DEV_TYPE_SIZE_LBN)
42 | (3 << SPI_DEV_TYPE_ADDR_LEN_LBN)
43 | (0x52 << SPI_DEV_TYPE_ERASE_CMD_LBN)
44 | (15 << SPI_DEV_TYPE_ERASE_SIZE_LBN)
45 | (8 << SPI_DEV_TYPE_BLOCK_SIZE_LBN));
47 /**************************************************************************
49 * I2C bus - this is a bit-bashing interface using GPIO pins
50 * Note that it uses the output enables to tristate the outputs
51 * SDA is the data pin and SCL is the clock
53 **************************************************************************
55 static void falcon_setsda(void *data, int state)
57 struct efx_nic *efx = (struct efx_nic *)data;
60 efx_reado(efx, ®, FR_AB_GPIO_CTL);
61 EFX_SET_OWORD_FIELD(reg, FRF_AB_GPIO3_OEN, !state);
62 efx_writeo(efx, ®, FR_AB_GPIO_CTL);
65 static void falcon_setscl(void *data, int state)
67 struct efx_nic *efx = (struct efx_nic *)data;
70 efx_reado(efx, ®, FR_AB_GPIO_CTL);
71 EFX_SET_OWORD_FIELD(reg, FRF_AB_GPIO0_OEN, !state);
72 efx_writeo(efx, ®, FR_AB_GPIO_CTL);
75 static int falcon_getsda(void *data)
77 struct efx_nic *efx = (struct efx_nic *)data;
80 efx_reado(efx, ®, FR_AB_GPIO_CTL);
81 return EFX_OWORD_FIELD(reg, FRF_AB_GPIO3_IN);
84 static int falcon_getscl(void *data)
86 struct efx_nic *efx = (struct efx_nic *)data;
89 efx_reado(efx, ®, FR_AB_GPIO_CTL);
90 return EFX_OWORD_FIELD(reg, FRF_AB_GPIO0_IN);
93 static struct i2c_algo_bit_data falcon_i2c_bit_operations = {
94 .setsda = falcon_setsda,
95 .setscl = falcon_setscl,
96 .getsda = falcon_getsda,
97 .getscl = falcon_getscl,
99 /* Wait up to 50 ms for slave to let us pull SCL high */
100 .timeout = DIV_ROUND_UP(HZ, 20),
103 static void falcon_push_irq_moderation(struct efx_channel *channel)
105 efx_dword_t timer_cmd;
106 struct efx_nic *efx = channel->efx;
108 /* Set timer register */
109 if (channel->irq_moderation) {
110 EFX_POPULATE_DWORD_2(timer_cmd,
111 FRF_AB_TC_TIMER_MODE,
112 FFE_BB_TIMER_MODE_INT_HLDOFF,
114 channel->irq_moderation - 1);
116 EFX_POPULATE_DWORD_2(timer_cmd,
117 FRF_AB_TC_TIMER_MODE,
118 FFE_BB_TIMER_MODE_DIS,
119 FRF_AB_TC_TIMER_VAL, 0);
121 BUILD_BUG_ON(FR_AA_TIMER_COMMAND_KER != FR_BZ_TIMER_COMMAND_P0);
122 efx_writed_page_locked(efx, &timer_cmd, FR_BZ_TIMER_COMMAND_P0,
126 static void falcon_deconfigure_mac_wrapper(struct efx_nic *efx);
128 static void falcon_prepare_flush(struct efx_nic *efx)
130 falcon_deconfigure_mac_wrapper(efx);
132 /* Wait for the tx and rx fifo's to get to the next packet boundary
133 * (~1ms without back-pressure), then to drain the remainder of the
134 * fifo's at data path speeds (negligible), with a healthy margin. */
138 /* Acknowledge a legacy interrupt from Falcon
140 * This acknowledges a legacy (not MSI) interrupt via INT_ACK_KER_REG.
142 * Due to SFC bug 3706 (silicon revision <=A1) reads can be duplicated in the
143 * BIU. Interrupt acknowledge is read sensitive so must write instead
144 * (then read to ensure the BIU collector is flushed)
146 * NB most hardware supports MSI interrupts
148 inline void falcon_irq_ack_a1(struct efx_nic *efx)
152 EFX_POPULATE_DWORD_1(reg, FRF_AA_INT_ACK_KER_FIELD, 0xb7eb7e);
153 efx_writed(efx, ®, FR_AA_INT_ACK_KER);
154 efx_readd(efx, ®, FR_AA_WORK_AROUND_BROKEN_PCI_READS);
158 irqreturn_t falcon_legacy_interrupt_a1(int irq, void *dev_id)
160 struct efx_nic *efx = dev_id;
161 efx_oword_t *int_ker = efx->irq_status.addr;
165 /* Check to see if this is our interrupt. If it isn't, we
166 * exit without having touched the hardware.
168 if (unlikely(EFX_OWORD_IS_ZERO(*int_ker))) {
169 netif_vdbg(efx, intr, efx->net_dev,
170 "IRQ %d on CPU %d not for me\n", irq,
171 raw_smp_processor_id());
174 efx->last_irq_cpu = raw_smp_processor_id();
175 netif_vdbg(efx, intr, efx->net_dev,
176 "IRQ %d on CPU %d status " EFX_OWORD_FMT "\n",
177 irq, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker));
179 /* Determine interrupting queues, clear interrupt status
180 * register and acknowledge the device interrupt.
182 BUILD_BUG_ON(FSF_AZ_NET_IVEC_INT_Q_WIDTH > EFX_MAX_CHANNELS);
183 queues = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_INT_Q);
185 /* Check to see if we have a serious error condition */
186 if (queues & (1U << efx->fatal_irq_level)) {
187 syserr = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_FATAL_INT);
188 if (unlikely(syserr))
189 return efx_nic_fatal_interrupt(efx);
192 EFX_ZERO_OWORD(*int_ker);
193 wmb(); /* Ensure the vector is cleared before interrupt ack */
194 falcon_irq_ack_a1(efx);
197 efx_schedule_channel(efx_get_channel(efx, 0));
199 efx_schedule_channel(efx_get_channel(efx, 1));
202 /**************************************************************************
206 **************************************************************************
209 #define FALCON_SPI_MAX_LEN sizeof(efx_oword_t)
211 static int falcon_spi_poll(struct efx_nic *efx)
214 efx_reado(efx, ®, FR_AB_EE_SPI_HCMD);
215 return EFX_OWORD_FIELD(reg, FRF_AB_EE_SPI_HCMD_CMD_EN) ? -EBUSY : 0;
218 /* Wait for SPI command completion */
219 static int falcon_spi_wait(struct efx_nic *efx)
221 /* Most commands will finish quickly, so we start polling at
222 * very short intervals. Sometimes the command may have to
223 * wait for VPD or expansion ROM access outside of our
224 * control, so we allow up to 100 ms. */
225 unsigned long timeout = jiffies + 1 + DIV_ROUND_UP(HZ, 10);
228 for (i = 0; i < 10; i++) {
229 if (!falcon_spi_poll(efx))
235 if (!falcon_spi_poll(efx))
237 if (time_after_eq(jiffies, timeout)) {
238 netif_err(efx, hw, efx->net_dev,
239 "timed out waiting for SPI\n");
242 schedule_timeout_uninterruptible(1);
246 int falcon_spi_cmd(struct efx_nic *efx, const struct efx_spi_device *spi,
247 unsigned int command, int address,
248 const void *in, void *out, size_t len)
250 bool addressed = (address >= 0);
251 bool reading = (out != NULL);
255 /* Input validation */
256 if (len > FALCON_SPI_MAX_LEN)
258 BUG_ON(!mutex_is_locked(&efx->spi_lock));
260 /* Check that previous command is not still running */
261 rc = falcon_spi_poll(efx);
265 /* Program address register, if we have an address */
267 EFX_POPULATE_OWORD_1(reg, FRF_AB_EE_SPI_HADR_ADR, address);
268 efx_writeo(efx, ®, FR_AB_EE_SPI_HADR);
271 /* Program data register, if we have data */
273 memcpy(®, in, len);
274 efx_writeo(efx, ®, FR_AB_EE_SPI_HDATA);
277 /* Issue read/write command */
278 EFX_POPULATE_OWORD_7(reg,
279 FRF_AB_EE_SPI_HCMD_CMD_EN, 1,
280 FRF_AB_EE_SPI_HCMD_SF_SEL, spi->device_id,
281 FRF_AB_EE_SPI_HCMD_DABCNT, len,
282 FRF_AB_EE_SPI_HCMD_READ, reading,
283 FRF_AB_EE_SPI_HCMD_DUBCNT, 0,
284 FRF_AB_EE_SPI_HCMD_ADBCNT,
285 (addressed ? spi->addr_len : 0),
286 FRF_AB_EE_SPI_HCMD_ENC, command);
287 efx_writeo(efx, ®, FR_AB_EE_SPI_HCMD);
289 /* Wait for read/write to complete */
290 rc = falcon_spi_wait(efx);
296 efx_reado(efx, ®, FR_AB_EE_SPI_HDATA);
297 memcpy(out, ®, len);
304 falcon_spi_write_limit(const struct efx_spi_device *spi, size_t start)
306 return min(FALCON_SPI_MAX_LEN,
307 (spi->block_size - (start & (spi->block_size - 1))));
311 efx_spi_munge_command(const struct efx_spi_device *spi,
312 const u8 command, const unsigned int address)
314 return command | (((address >> 8) & spi->munge_address) << 3);
317 /* Wait up to 10 ms for buffered write completion */
319 falcon_spi_wait_write(struct efx_nic *efx, const struct efx_spi_device *spi)
321 unsigned long timeout = jiffies + 1 + DIV_ROUND_UP(HZ, 100);
326 rc = falcon_spi_cmd(efx, spi, SPI_RDSR, -1, NULL,
327 &status, sizeof(status));
330 if (!(status & SPI_STATUS_NRDY))
332 if (time_after_eq(jiffies, timeout)) {
333 netif_err(efx, hw, efx->net_dev,
334 "SPI write timeout on device %d"
335 " last status=0x%02x\n",
336 spi->device_id, status);
339 schedule_timeout_uninterruptible(1);
343 int falcon_spi_read(struct efx_nic *efx, const struct efx_spi_device *spi,
344 loff_t start, size_t len, size_t *retlen, u8 *buffer)
346 size_t block_len, pos = 0;
347 unsigned int command;
351 block_len = min(len - pos, FALCON_SPI_MAX_LEN);
353 command = efx_spi_munge_command(spi, SPI_READ, start + pos);
354 rc = falcon_spi_cmd(efx, spi, command, start + pos, NULL,
355 buffer + pos, block_len);
360 /* Avoid locking up the system */
362 if (signal_pending(current)) {
374 falcon_spi_write(struct efx_nic *efx, const struct efx_spi_device *spi,
375 loff_t start, size_t len, size_t *retlen, const u8 *buffer)
377 u8 verify_buffer[FALCON_SPI_MAX_LEN];
378 size_t block_len, pos = 0;
379 unsigned int command;
383 rc = falcon_spi_cmd(efx, spi, SPI_WREN, -1, NULL, NULL, 0);
387 block_len = min(len - pos,
388 falcon_spi_write_limit(spi, start + pos));
389 command = efx_spi_munge_command(spi, SPI_WRITE, start + pos);
390 rc = falcon_spi_cmd(efx, spi, command, start + pos,
391 buffer + pos, NULL, block_len);
395 rc = falcon_spi_wait_write(efx, spi);
399 command = efx_spi_munge_command(spi, SPI_READ, start + pos);
400 rc = falcon_spi_cmd(efx, spi, command, start + pos,
401 NULL, verify_buffer, block_len);
402 if (memcmp(verify_buffer, buffer + pos, block_len)) {
409 /* Avoid locking up the system */
411 if (signal_pending(current)) {
422 /**************************************************************************
426 **************************************************************************
429 static void falcon_push_multicast_hash(struct efx_nic *efx)
431 union efx_multicast_hash *mc_hash = &efx->multicast_hash;
433 WARN_ON(!mutex_is_locked(&efx->mac_lock));
435 efx_writeo(efx, &mc_hash->oword[0], FR_AB_MAC_MC_HASH_REG0);
436 efx_writeo(efx, &mc_hash->oword[1], FR_AB_MAC_MC_HASH_REG1);
439 static void falcon_reset_macs(struct efx_nic *efx)
441 struct falcon_nic_data *nic_data = efx->nic_data;
442 efx_oword_t reg, mac_ctrl;
445 if (efx_nic_rev(efx) < EFX_REV_FALCON_B0) {
446 /* It's not safe to use GLB_CTL_REG to reset the
447 * macs, so instead use the internal MAC resets
449 if (!EFX_IS10G(efx)) {
450 EFX_POPULATE_OWORD_1(reg, FRF_AB_GM_SW_RST, 1);
451 efx_writeo(efx, ®, FR_AB_GM_CFG1);
454 EFX_POPULATE_OWORD_1(reg, FRF_AB_GM_SW_RST, 0);
455 efx_writeo(efx, ®, FR_AB_GM_CFG1);
459 EFX_POPULATE_OWORD_1(reg, FRF_AB_XM_CORE_RST, 1);
460 efx_writeo(efx, ®, FR_AB_XM_GLB_CFG);
462 for (count = 0; count < 10000; count++) {
463 efx_reado(efx, ®, FR_AB_XM_GLB_CFG);
464 if (EFX_OWORD_FIELD(reg, FRF_AB_XM_CORE_RST) ==
470 netif_err(efx, hw, efx->net_dev,
471 "timed out waiting for XMAC core reset\n");
475 /* Mac stats will fail whist the TX fifo is draining */
476 WARN_ON(nic_data->stats_disable_count == 0);
478 efx_reado(efx, &mac_ctrl, FR_AB_MAC_CTRL);
479 EFX_SET_OWORD_FIELD(mac_ctrl, FRF_BB_TXFIFO_DRAIN_EN, 1);
480 efx_writeo(efx, &mac_ctrl, FR_AB_MAC_CTRL);
482 efx_reado(efx, ®, FR_AB_GLB_CTL);
483 EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_XGTX, 1);
484 EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_XGRX, 1);
485 EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_EM, 1);
486 efx_writeo(efx, ®, FR_AB_GLB_CTL);
490 efx_reado(efx, ®, FR_AB_GLB_CTL);
491 if (!EFX_OWORD_FIELD(reg, FRF_AB_RST_XGTX) &&
492 !EFX_OWORD_FIELD(reg, FRF_AB_RST_XGRX) &&
493 !EFX_OWORD_FIELD(reg, FRF_AB_RST_EM)) {
494 netif_dbg(efx, hw, efx->net_dev,
495 "Completed MAC reset after %d loops\n",
500 netif_err(efx, hw, efx->net_dev, "MAC reset failed\n");
507 /* Ensure the correct MAC is selected before statistics
508 * are re-enabled by the caller */
509 efx_writeo(efx, &mac_ctrl, FR_AB_MAC_CTRL);
511 /* This can run even when the GMAC is selected */
512 falcon_setup_xaui(efx);
515 void falcon_drain_tx_fifo(struct efx_nic *efx)
519 if ((efx_nic_rev(efx) < EFX_REV_FALCON_B0) ||
520 (efx->loopback_mode != LOOPBACK_NONE))
523 efx_reado(efx, ®, FR_AB_MAC_CTRL);
524 /* There is no point in draining more than once */
525 if (EFX_OWORD_FIELD(reg, FRF_BB_TXFIFO_DRAIN_EN))
528 falcon_reset_macs(efx);
531 static void falcon_deconfigure_mac_wrapper(struct efx_nic *efx)
535 if (efx_nic_rev(efx) < EFX_REV_FALCON_B0)
538 /* Isolate the MAC -> RX */
539 efx_reado(efx, ®, FR_AZ_RX_CFG);
540 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 0);
541 efx_writeo(efx, ®, FR_AZ_RX_CFG);
543 /* Isolate TX -> MAC */
544 falcon_drain_tx_fifo(efx);
547 void falcon_reconfigure_mac_wrapper(struct efx_nic *efx)
549 struct efx_link_state *link_state = &efx->link_state;
551 int link_speed, isolate;
553 isolate = (efx->reset_pending != RESET_TYPE_NONE);
555 switch (link_state->speed) {
556 case 10000: link_speed = 3; break;
557 case 1000: link_speed = 2; break;
558 case 100: link_speed = 1; break;
559 default: link_speed = 0; break;
561 /* MAC_LINK_STATUS controls MAC backpressure but doesn't work
562 * as advertised. Disable to ensure packets are not
563 * indefinitely held and TX queue can be flushed at any point
564 * while the link is down. */
565 EFX_POPULATE_OWORD_5(reg,
566 FRF_AB_MAC_XOFF_VAL, 0xffff /* max pause time */,
567 FRF_AB_MAC_BCAD_ACPT, 1,
568 FRF_AB_MAC_UC_PROM, efx->promiscuous,
569 FRF_AB_MAC_LINK_STATUS, 1, /* always set */
570 FRF_AB_MAC_SPEED, link_speed);
571 /* On B0, MAC backpressure can be disabled and packets get
573 if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) {
574 EFX_SET_OWORD_FIELD(reg, FRF_BB_TXFIFO_DRAIN_EN,
575 !link_state->up || isolate);
578 efx_writeo(efx, ®, FR_AB_MAC_CTRL);
580 /* Restore the multicast hash registers. */
581 falcon_push_multicast_hash(efx);
583 efx_reado(efx, ®, FR_AZ_RX_CFG);
584 /* Enable XOFF signal from RX FIFO (we enabled it during NIC
585 * initialisation but it may read back as 0) */
586 EFX_SET_OWORD_FIELD(reg, FRF_AZ_RX_XOFF_MAC_EN, 1);
587 /* Unisolate the MAC -> RX */
588 if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0)
589 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, !isolate);
590 efx_writeo(efx, ®, FR_AZ_RX_CFG);
593 static void falcon_stats_request(struct efx_nic *efx)
595 struct falcon_nic_data *nic_data = efx->nic_data;
598 WARN_ON(nic_data->stats_pending);
599 WARN_ON(nic_data->stats_disable_count);
601 if (nic_data->stats_dma_done == NULL)
602 return; /* no mac selected */
604 *nic_data->stats_dma_done = FALCON_STATS_NOT_DONE;
605 nic_data->stats_pending = true;
606 wmb(); /* ensure done flag is clear */
608 /* Initiate DMA transfer of stats */
609 EFX_POPULATE_OWORD_2(reg,
610 FRF_AB_MAC_STAT_DMA_CMD, 1,
611 FRF_AB_MAC_STAT_DMA_ADR,
612 efx->stats_buffer.dma_addr);
613 efx_writeo(efx, ®, FR_AB_MAC_STAT_DMA);
615 mod_timer(&nic_data->stats_timer, round_jiffies_up(jiffies + HZ / 2));
618 static void falcon_stats_complete(struct efx_nic *efx)
620 struct falcon_nic_data *nic_data = efx->nic_data;
622 if (!nic_data->stats_pending)
625 nic_data->stats_pending = 0;
626 if (*nic_data->stats_dma_done == FALCON_STATS_DONE) {
627 rmb(); /* read the done flag before the stats */
628 efx->mac_op->update_stats(efx);
630 netif_err(efx, hw, efx->net_dev,
631 "timed out waiting for statistics\n");
635 static void falcon_stats_timer_func(unsigned long context)
637 struct efx_nic *efx = (struct efx_nic *)context;
638 struct falcon_nic_data *nic_data = efx->nic_data;
640 spin_lock(&efx->stats_lock);
642 falcon_stats_complete(efx);
643 if (nic_data->stats_disable_count == 0)
644 falcon_stats_request(efx);
646 spin_unlock(&efx->stats_lock);
649 static void falcon_switch_mac(struct efx_nic *efx);
651 static bool falcon_loopback_link_poll(struct efx_nic *efx)
653 struct efx_link_state old_state = efx->link_state;
655 WARN_ON(!mutex_is_locked(&efx->mac_lock));
656 WARN_ON(!LOOPBACK_INTERNAL(efx));
658 efx->link_state.fd = true;
659 efx->link_state.fc = efx->wanted_fc;
660 efx->link_state.up = true;
662 if (efx->loopback_mode == LOOPBACK_GMAC)
663 efx->link_state.speed = 1000;
665 efx->link_state.speed = 10000;
667 return !efx_link_state_equal(&efx->link_state, &old_state);
670 static int falcon_reconfigure_port(struct efx_nic *efx)
674 WARN_ON(efx_nic_rev(efx) > EFX_REV_FALCON_B0);
676 /* Poll the PHY link state *before* reconfiguring it. This means we
677 * will pick up the correct speed (in loopback) to select the correct
680 if (LOOPBACK_INTERNAL(efx))
681 falcon_loopback_link_poll(efx);
683 efx->phy_op->poll(efx);
685 falcon_stop_nic_stats(efx);
686 falcon_deconfigure_mac_wrapper(efx);
688 falcon_switch_mac(efx);
690 efx->phy_op->reconfigure(efx);
691 rc = efx->mac_op->reconfigure(efx);
694 falcon_start_nic_stats(efx);
696 /* Synchronise efx->link_state with the kernel */
697 efx_link_status_changed(efx);
702 /**************************************************************************
704 * PHY access via GMII
706 **************************************************************************
709 /* Wait for GMII access to complete */
710 static int falcon_gmii_wait(struct efx_nic *efx)
715 /* wait upto 50ms - taken max from datasheet */
716 for (count = 0; count < 5000; count++) {
717 efx_reado(efx, &md_stat, FR_AB_MD_STAT);
718 if (EFX_OWORD_FIELD(md_stat, FRF_AB_MD_BSY) == 0) {
719 if (EFX_OWORD_FIELD(md_stat, FRF_AB_MD_LNFL) != 0 ||
720 EFX_OWORD_FIELD(md_stat, FRF_AB_MD_BSERR) != 0) {
721 netif_err(efx, hw, efx->net_dev,
722 "error from GMII access "
724 EFX_OWORD_VAL(md_stat));
731 netif_err(efx, hw, efx->net_dev, "timed out waiting for GMII\n");
735 /* Write an MDIO register of a PHY connected to Falcon. */
736 static int falcon_mdio_write(struct net_device *net_dev,
737 int prtad, int devad, u16 addr, u16 value)
739 struct efx_nic *efx = netdev_priv(net_dev);
743 netif_vdbg(efx, hw, efx->net_dev,
744 "writing MDIO %d register %d.%d with 0x%04x\n",
745 prtad, devad, addr, value);
747 mutex_lock(&efx->mdio_lock);
749 /* Check MDIO not currently being accessed */
750 rc = falcon_gmii_wait(efx);
754 /* Write the address/ID register */
755 EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_PHY_ADR, addr);
756 efx_writeo(efx, ®, FR_AB_MD_PHY_ADR);
758 EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_PRT_ADR, prtad,
759 FRF_AB_MD_DEV_ADR, devad);
760 efx_writeo(efx, ®, FR_AB_MD_ID);
763 EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_TXD, value);
764 efx_writeo(efx, ®, FR_AB_MD_TXD);
766 EFX_POPULATE_OWORD_2(reg,
769 efx_writeo(efx, ®, FR_AB_MD_CS);
771 /* Wait for data to be written */
772 rc = falcon_gmii_wait(efx);
774 /* Abort the write operation */
775 EFX_POPULATE_OWORD_2(reg,
778 efx_writeo(efx, ®, FR_AB_MD_CS);
783 mutex_unlock(&efx->mdio_lock);
787 /* Read an MDIO register of a PHY connected to Falcon. */
788 static int falcon_mdio_read(struct net_device *net_dev,
789 int prtad, int devad, u16 addr)
791 struct efx_nic *efx = netdev_priv(net_dev);
795 mutex_lock(&efx->mdio_lock);
797 /* Check MDIO not currently being accessed */
798 rc = falcon_gmii_wait(efx);
802 EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_PHY_ADR, addr);
803 efx_writeo(efx, ®, FR_AB_MD_PHY_ADR);
805 EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_PRT_ADR, prtad,
806 FRF_AB_MD_DEV_ADR, devad);
807 efx_writeo(efx, ®, FR_AB_MD_ID);
809 /* Request data to be read */
810 EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_RDC, 1, FRF_AB_MD_GC, 0);
811 efx_writeo(efx, ®, FR_AB_MD_CS);
813 /* Wait for data to become available */
814 rc = falcon_gmii_wait(efx);
816 efx_reado(efx, ®, FR_AB_MD_RXD);
817 rc = EFX_OWORD_FIELD(reg, FRF_AB_MD_RXD);
818 netif_vdbg(efx, hw, efx->net_dev,
819 "read from MDIO %d register %d.%d, got %04x\n",
820 prtad, devad, addr, rc);
822 /* Abort the read operation */
823 EFX_POPULATE_OWORD_2(reg,
826 efx_writeo(efx, ®, FR_AB_MD_CS);
828 netif_dbg(efx, hw, efx->net_dev,
829 "read from MDIO %d register %d.%d, got error %d\n",
830 prtad, devad, addr, rc);
834 mutex_unlock(&efx->mdio_lock);
838 static void falcon_clock_mac(struct efx_nic *efx)
841 efx_oword_t nic_stat;
843 /* Configure the NIC generated MAC clock correctly */
844 efx_reado(efx, &nic_stat, FR_AB_NIC_STAT);
845 strap_val = EFX_IS10G(efx) ? 5 : 3;
846 if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) {
847 EFX_SET_OWORD_FIELD(nic_stat, FRF_BB_EE_STRAP_EN, 1);
848 EFX_SET_OWORD_FIELD(nic_stat, FRF_BB_EE_STRAP, strap_val);
849 efx_writeo(efx, &nic_stat, FR_AB_NIC_STAT);
851 /* Falcon A1 does not support 1G/10G speed switching
852 * and must not be used with a PHY that does. */
853 BUG_ON(EFX_OWORD_FIELD(nic_stat, FRF_AB_STRAP_PINS) !=
858 static void falcon_switch_mac(struct efx_nic *efx)
860 struct efx_mac_operations *old_mac_op = efx->mac_op;
861 struct falcon_nic_data *nic_data = efx->nic_data;
862 unsigned int stats_done_offset;
864 WARN_ON(!mutex_is_locked(&efx->mac_lock));
865 WARN_ON(nic_data->stats_disable_count == 0);
867 efx->mac_op = (EFX_IS10G(efx) ?
868 &falcon_xmac_operations : &falcon_gmac_operations);
871 stats_done_offset = XgDmaDone_offset;
873 stats_done_offset = GDmaDone_offset;
874 nic_data->stats_dma_done = efx->stats_buffer.addr + stats_done_offset;
876 if (old_mac_op == efx->mac_op)
879 falcon_clock_mac(efx);
881 netif_dbg(efx, hw, efx->net_dev, "selected %cMAC\n",
882 EFX_IS10G(efx) ? 'X' : 'G');
883 /* Not all macs support a mac-level link state */
884 efx->xmac_poll_required = false;
885 falcon_reset_macs(efx);
888 /* This call is responsible for hooking in the MAC and PHY operations */
889 static int falcon_probe_port(struct efx_nic *efx)
893 switch (efx->phy_type) {
894 case PHY_TYPE_SFX7101:
895 efx->phy_op = &falcon_sfx7101_phy_ops;
897 case PHY_TYPE_SFT9001A:
898 case PHY_TYPE_SFT9001B:
899 efx->phy_op = &falcon_sft9001_phy_ops;
901 case PHY_TYPE_QT2022C2:
902 case PHY_TYPE_QT2025C:
903 efx->phy_op = &falcon_qt202x_phy_ops;
906 netif_err(efx, probe, efx->net_dev, "Unknown PHY type %d\n",
911 /* Fill out MDIO structure and loopback modes */
912 efx->mdio.mdio_read = falcon_mdio_read;
913 efx->mdio.mdio_write = falcon_mdio_write;
914 rc = efx->phy_op->probe(efx);
918 /* Initial assumption */
919 efx->link_state.speed = 10000;
920 efx->link_state.fd = true;
922 /* Hardware flow ctrl. FalconA RX FIFO too small for pause generation */
923 if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0)
924 efx->wanted_fc = EFX_FC_RX | EFX_FC_TX;
926 efx->wanted_fc = EFX_FC_RX;
927 if (efx->mdio.mmds & MDIO_DEVS_AN)
928 efx->wanted_fc |= EFX_FC_AUTO;
930 /* Allocate buffer for stats */
931 rc = efx_nic_alloc_buffer(efx, &efx->stats_buffer,
932 FALCON_MAC_STATS_SIZE);
935 netif_dbg(efx, probe, efx->net_dev,
936 "stats buffer at %llx (virt %p phys %llx)\n",
937 (u64)efx->stats_buffer.dma_addr,
938 efx->stats_buffer.addr,
939 (u64)virt_to_phys(efx->stats_buffer.addr));
944 static void falcon_remove_port(struct efx_nic *efx)
946 efx->phy_op->remove(efx);
947 efx_nic_free_buffer(efx, &efx->stats_buffer);
950 /**************************************************************************
954 **************************************************************************/
957 falcon_read_nvram(struct efx_nic *efx, struct falcon_nvconfig *nvconfig_out)
959 struct falcon_nvconfig *nvconfig;
960 struct efx_spi_device *spi;
962 int rc, magic_num, struct_ver;
963 __le16 *word, *limit;
966 spi = efx->spi_flash ? efx->spi_flash : efx->spi_eeprom;
970 region = kmalloc(FALCON_NVCONFIG_END, GFP_KERNEL);
973 nvconfig = region + FALCON_NVCONFIG_OFFSET;
975 mutex_lock(&efx->spi_lock);
976 rc = falcon_spi_read(efx, spi, 0, FALCON_NVCONFIG_END, NULL, region);
977 mutex_unlock(&efx->spi_lock);
979 netif_err(efx, hw, efx->net_dev, "Failed to read %s\n",
980 efx->spi_flash ? "flash" : "EEPROM");
985 magic_num = le16_to_cpu(nvconfig->board_magic_num);
986 struct_ver = le16_to_cpu(nvconfig->board_struct_ver);
989 if (magic_num != FALCON_NVCONFIG_BOARD_MAGIC_NUM) {
990 netif_err(efx, hw, efx->net_dev,
991 "NVRAM bad magic 0x%x\n", magic_num);
994 if (struct_ver < 2) {
995 netif_err(efx, hw, efx->net_dev,
996 "NVRAM has ancient version 0x%x\n", struct_ver);
998 } else if (struct_ver < 4) {
999 word = &nvconfig->board_magic_num;
1000 limit = (__le16 *) (nvconfig + 1);
1003 limit = region + FALCON_NVCONFIG_END;
1005 for (csum = 0; word < limit; ++word)
1006 csum += le16_to_cpu(*word);
1008 if (~csum & 0xffff) {
1009 netif_err(efx, hw, efx->net_dev,
1010 "NVRAM has incorrect checksum\n");
1016 memcpy(nvconfig_out, nvconfig, sizeof(*nvconfig));
1023 static int falcon_test_nvram(struct efx_nic *efx)
1025 return falcon_read_nvram(efx, NULL);
1028 static const struct efx_nic_register_test falcon_b0_register_tests[] = {
1030 EFX_OWORD32(0x0003FFFF, 0x0003FFFF, 0x0003FFFF, 0x0003FFFF) },
1032 EFX_OWORD32(0xFFFFFFFE, 0x00017FFF, 0x00000000, 0x00000000) },
1034 EFX_OWORD32(0x7FFF0037, 0x00000000, 0x00000000, 0x00000000) },
1035 { FR_AZ_TX_RESERVED,
1036 EFX_OWORD32(0xFFFEFE80, 0x1FFFFFFF, 0x020000FE, 0x007FFFFF) },
1038 EFX_OWORD32(0xFFFF0000, 0x00000000, 0x00000000, 0x00000000) },
1039 { FR_AZ_SRM_TX_DC_CFG,
1040 EFX_OWORD32(0x001FFFFF, 0x00000000, 0x00000000, 0x00000000) },
1042 EFX_OWORD32(0x0000000F, 0x00000000, 0x00000000, 0x00000000) },
1043 { FR_AZ_RX_DC_PF_WM,
1044 EFX_OWORD32(0x000003FF, 0x00000000, 0x00000000, 0x00000000) },
1046 EFX_OWORD32(0x00000FFF, 0x00000000, 0x00000000, 0x00000000) },
1048 EFX_OWORD32(0x00007337, 0x00000000, 0x00000000, 0x00000000) },
1050 EFX_OWORD32(0x00001F1F, 0x00000000, 0x00000000, 0x00000000) },
1052 EFX_OWORD32(0x00000C68, 0x00000000, 0x00000000, 0x00000000) },
1054 EFX_OWORD32(0x00080164, 0x00000000, 0x00000000, 0x00000000) },
1056 EFX_OWORD32(0x07100A0C, 0x00000000, 0x00000000, 0x00000000) },
1057 { FR_AB_XM_RX_PARAM,
1058 EFX_OWORD32(0x00001FF8, 0x00000000, 0x00000000, 0x00000000) },
1060 EFX_OWORD32(0xFFFF0001, 0x00000000, 0x00000000, 0x00000000) },
1062 EFX_OWORD32(0xFFFFFFFF, 0x00000000, 0x00000000, 0x00000000) },
1064 EFX_OWORD32(0x0003FF0F, 0x00000000, 0x00000000, 0x00000000) },
1067 static int falcon_b0_test_registers(struct efx_nic *efx)
1069 return efx_nic_test_registers(efx, falcon_b0_register_tests,
1070 ARRAY_SIZE(falcon_b0_register_tests));
1073 /**************************************************************************
1077 **************************************************************************
1080 /* Resets NIC to known state. This routine must be called in process
1081 * context and is allowed to sleep. */
1082 static int falcon_reset_hw(struct efx_nic *efx, enum reset_type method)
1084 struct falcon_nic_data *nic_data = efx->nic_data;
1085 efx_oword_t glb_ctl_reg_ker;
1088 netif_dbg(efx, hw, efx->net_dev, "performing %s hardware reset\n",
1089 RESET_TYPE(method));
1091 /* Initiate device reset */
1092 if (method == RESET_TYPE_WORLD) {
1093 rc = pci_save_state(efx->pci_dev);
1095 netif_err(efx, drv, efx->net_dev,
1096 "failed to backup PCI state of primary "
1097 "function prior to hardware reset\n");
1100 if (efx_nic_is_dual_func(efx)) {
1101 rc = pci_save_state(nic_data->pci_dev2);
1103 netif_err(efx, drv, efx->net_dev,
1104 "failed to backup PCI state of "
1105 "secondary function prior to "
1106 "hardware reset\n");
1111 EFX_POPULATE_OWORD_2(glb_ctl_reg_ker,
1112 FRF_AB_EXT_PHY_RST_DUR,
1113 FFE_AB_EXT_PHY_RST_DUR_10240US,
1116 EFX_POPULATE_OWORD_7(glb_ctl_reg_ker,
1117 /* exclude PHY from "invisible" reset */
1118 FRF_AB_EXT_PHY_RST_CTL,
1119 method == RESET_TYPE_INVISIBLE,
1120 /* exclude EEPROM/flash and PCIe */
1121 FRF_AB_PCIE_CORE_RST_CTL, 1,
1122 FRF_AB_PCIE_NSTKY_RST_CTL, 1,
1123 FRF_AB_PCIE_SD_RST_CTL, 1,
1124 FRF_AB_EE_RST_CTL, 1,
1125 FRF_AB_EXT_PHY_RST_DUR,
1126 FFE_AB_EXT_PHY_RST_DUR_10240US,
1129 efx_writeo(efx, &glb_ctl_reg_ker, FR_AB_GLB_CTL);
1131 netif_dbg(efx, hw, efx->net_dev, "waiting for hardware reset\n");
1132 schedule_timeout_uninterruptible(HZ / 20);
1134 /* Restore PCI configuration if needed */
1135 if (method == RESET_TYPE_WORLD) {
1136 if (efx_nic_is_dual_func(efx)) {
1137 rc = pci_restore_state(nic_data->pci_dev2);
1139 netif_err(efx, drv, efx->net_dev,
1140 "failed to restore PCI config for "
1141 "the secondary function\n");
1145 rc = pci_restore_state(efx->pci_dev);
1147 netif_err(efx, drv, efx->net_dev,
1148 "failed to restore PCI config for the "
1149 "primary function\n");
1152 netif_dbg(efx, drv, efx->net_dev,
1153 "successfully restored PCI config\n");
1156 /* Assert that reset complete */
1157 efx_reado(efx, &glb_ctl_reg_ker, FR_AB_GLB_CTL);
1158 if (EFX_OWORD_FIELD(glb_ctl_reg_ker, FRF_AB_SWRST) != 0) {
1160 netif_err(efx, hw, efx->net_dev,
1161 "timed out waiting for hardware reset\n");
1164 netif_dbg(efx, hw, efx->net_dev, "hardware reset complete\n");
1168 /* pci_save_state() and pci_restore_state() MUST be called in pairs */
1171 pci_restore_state(efx->pci_dev);
1178 static void falcon_monitor(struct efx_nic *efx)
1183 BUG_ON(!mutex_is_locked(&efx->mac_lock));
1185 rc = falcon_board(efx)->type->monitor(efx);
1187 netif_err(efx, hw, efx->net_dev,
1188 "Board sensor %s; shutting down PHY\n",
1189 (rc == -ERANGE) ? "reported fault" : "failed");
1190 efx->phy_mode |= PHY_MODE_LOW_POWER;
1191 rc = __efx_reconfigure_port(efx);
1195 if (LOOPBACK_INTERNAL(efx))
1196 link_changed = falcon_loopback_link_poll(efx);
1198 link_changed = efx->phy_op->poll(efx);
1201 falcon_stop_nic_stats(efx);
1202 falcon_deconfigure_mac_wrapper(efx);
1204 falcon_switch_mac(efx);
1205 rc = efx->mac_op->reconfigure(efx);
1208 falcon_start_nic_stats(efx);
1210 efx_link_status_changed(efx);
1214 falcon_poll_xmac(efx);
1217 /* Zeroes out the SRAM contents. This routine must be called in
1218 * process context and is allowed to sleep.
1220 static int falcon_reset_sram(struct efx_nic *efx)
1222 efx_oword_t srm_cfg_reg_ker, gpio_cfg_reg_ker;
1225 /* Set the SRAM wake/sleep GPIO appropriately. */
1226 efx_reado(efx, &gpio_cfg_reg_ker, FR_AB_GPIO_CTL);
1227 EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, FRF_AB_GPIO1_OEN, 1);
1228 EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, FRF_AB_GPIO1_OUT, 1);
1229 efx_writeo(efx, &gpio_cfg_reg_ker, FR_AB_GPIO_CTL);
1231 /* Initiate SRAM reset */
1232 EFX_POPULATE_OWORD_2(srm_cfg_reg_ker,
1233 FRF_AZ_SRM_INIT_EN, 1,
1234 FRF_AZ_SRM_NB_SZ, 0);
1235 efx_writeo(efx, &srm_cfg_reg_ker, FR_AZ_SRM_CFG);
1237 /* Wait for SRAM reset to complete */
1240 netif_dbg(efx, hw, efx->net_dev,
1241 "waiting for SRAM reset (attempt %d)...\n", count);
1243 /* SRAM reset is slow; expect around 16ms */
1244 schedule_timeout_uninterruptible(HZ / 50);
1246 /* Check for reset complete */
1247 efx_reado(efx, &srm_cfg_reg_ker, FR_AZ_SRM_CFG);
1248 if (!EFX_OWORD_FIELD(srm_cfg_reg_ker, FRF_AZ_SRM_INIT_EN)) {
1249 netif_dbg(efx, hw, efx->net_dev,
1250 "SRAM reset complete\n");
1254 } while (++count < 20); /* wait upto 0.4 sec */
1256 netif_err(efx, hw, efx->net_dev, "timed out waiting for SRAM reset\n");
1260 static int falcon_spi_device_init(struct efx_nic *efx,
1261 struct efx_spi_device **spi_device_ret,
1262 unsigned int device_id, u32 device_type)
1264 struct efx_spi_device *spi_device;
1266 if (device_type != 0) {
1267 spi_device = kzalloc(sizeof(*spi_device), GFP_KERNEL);
1270 spi_device->device_id = device_id;
1272 1 << SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_SIZE);
1273 spi_device->addr_len =
1274 SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_ADDR_LEN);
1275 spi_device->munge_address = (spi_device->size == 1 << 9 &&
1276 spi_device->addr_len == 1);
1277 spi_device->erase_command =
1278 SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_ERASE_CMD);
1279 spi_device->erase_size =
1280 1 << SPI_DEV_TYPE_FIELD(device_type,
1281 SPI_DEV_TYPE_ERASE_SIZE);
1282 spi_device->block_size =
1283 1 << SPI_DEV_TYPE_FIELD(device_type,
1284 SPI_DEV_TYPE_BLOCK_SIZE);
1289 kfree(*spi_device_ret);
1290 *spi_device_ret = spi_device;
1294 static void falcon_remove_spi_devices(struct efx_nic *efx)
1296 kfree(efx->spi_eeprom);
1297 efx->spi_eeprom = NULL;
1298 kfree(efx->spi_flash);
1299 efx->spi_flash = NULL;
1302 /* Extract non-volatile configuration */
1303 static int falcon_probe_nvconfig(struct efx_nic *efx)
1305 struct falcon_nvconfig *nvconfig;
1309 nvconfig = kmalloc(sizeof(*nvconfig), GFP_KERNEL);
1313 rc = falcon_read_nvram(efx, nvconfig);
1314 if (rc == -EINVAL) {
1315 netif_err(efx, probe, efx->net_dev,
1316 "NVRAM is invalid therefore using defaults\n");
1317 efx->phy_type = PHY_TYPE_NONE;
1318 efx->mdio.prtad = MDIO_PRTAD_NONE;
1324 struct falcon_nvconfig_board_v2 *v2 = &nvconfig->board_v2;
1325 struct falcon_nvconfig_board_v3 *v3 = &nvconfig->board_v3;
1327 efx->phy_type = v2->port0_phy_type;
1328 efx->mdio.prtad = v2->port0_phy_addr;
1329 board_rev = le16_to_cpu(v2->board_revision);
1331 if (le16_to_cpu(nvconfig->board_struct_ver) >= 3) {
1332 rc = falcon_spi_device_init(
1333 efx, &efx->spi_flash, FFE_AB_SPI_DEVICE_FLASH,
1334 le32_to_cpu(v3->spi_device_type
1335 [FFE_AB_SPI_DEVICE_FLASH]));
1338 rc = falcon_spi_device_init(
1339 efx, &efx->spi_eeprom, FFE_AB_SPI_DEVICE_EEPROM,
1340 le32_to_cpu(v3->spi_device_type
1341 [FFE_AB_SPI_DEVICE_EEPROM]));
1347 /* Read the MAC addresses */
1348 memcpy(efx->mac_address, nvconfig->mac_address[0], ETH_ALEN);
1350 netif_dbg(efx, probe, efx->net_dev, "PHY is %d phy_id %d\n",
1351 efx->phy_type, efx->mdio.prtad);
1353 rc = falcon_probe_board(efx, board_rev);
1361 falcon_remove_spi_devices(efx);
1367 /* Probe all SPI devices on the NIC */
1368 static void falcon_probe_spi_devices(struct efx_nic *efx)
1370 efx_oword_t nic_stat, gpio_ctl, ee_vpd_cfg;
1373 efx_reado(efx, &gpio_ctl, FR_AB_GPIO_CTL);
1374 efx_reado(efx, &nic_stat, FR_AB_NIC_STAT);
1375 efx_reado(efx, &ee_vpd_cfg, FR_AB_EE_VPD_CFG0);
1377 if (EFX_OWORD_FIELD(gpio_ctl, FRF_AB_GPIO3_PWRUP_VALUE)) {
1378 boot_dev = (EFX_OWORD_FIELD(nic_stat, FRF_AB_SF_PRST) ?
1379 FFE_AB_SPI_DEVICE_FLASH : FFE_AB_SPI_DEVICE_EEPROM);
1380 netif_dbg(efx, probe, efx->net_dev, "Booted from %s\n",
1381 boot_dev == FFE_AB_SPI_DEVICE_FLASH ?
1382 "flash" : "EEPROM");
1384 /* Disable VPD and set clock dividers to safe
1385 * values for initial programming. */
1387 netif_dbg(efx, probe, efx->net_dev,
1388 "Booted from internal ASIC settings;"
1389 " setting SPI config\n");
1390 EFX_POPULATE_OWORD_3(ee_vpd_cfg, FRF_AB_EE_VPD_EN, 0,
1391 /* 125 MHz / 7 ~= 20 MHz */
1392 FRF_AB_EE_SF_CLOCK_DIV, 7,
1393 /* 125 MHz / 63 ~= 2 MHz */
1394 FRF_AB_EE_EE_CLOCK_DIV, 63);
1395 efx_writeo(efx, &ee_vpd_cfg, FR_AB_EE_VPD_CFG0);
1398 if (boot_dev == FFE_AB_SPI_DEVICE_FLASH)
1399 falcon_spi_device_init(efx, &efx->spi_flash,
1400 FFE_AB_SPI_DEVICE_FLASH,
1401 default_flash_type);
1402 if (boot_dev == FFE_AB_SPI_DEVICE_EEPROM)
1403 falcon_spi_device_init(efx, &efx->spi_eeprom,
1404 FFE_AB_SPI_DEVICE_EEPROM,
1408 static int falcon_probe_nic(struct efx_nic *efx)
1410 struct falcon_nic_data *nic_data;
1411 struct falcon_board *board;
1414 /* Allocate storage for hardware specific data */
1415 nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL);
1418 efx->nic_data = nic_data;
1422 if (efx_nic_fpga_ver(efx) != 0) {
1423 netif_err(efx, probe, efx->net_dev,
1424 "Falcon FPGA not supported\n");
1428 if (efx_nic_rev(efx) <= EFX_REV_FALCON_A1) {
1429 efx_oword_t nic_stat;
1430 struct pci_dev *dev;
1431 u8 pci_rev = efx->pci_dev->revision;
1433 if ((pci_rev == 0xff) || (pci_rev == 0)) {
1434 netif_err(efx, probe, efx->net_dev,
1435 "Falcon rev A0 not supported\n");
1438 efx_reado(efx, &nic_stat, FR_AB_NIC_STAT);
1439 if (EFX_OWORD_FIELD(nic_stat, FRF_AB_STRAP_10G) == 0) {
1440 netif_err(efx, probe, efx->net_dev,
1441 "Falcon rev A1 1G not supported\n");
1444 if (EFX_OWORD_FIELD(nic_stat, FRF_AA_STRAP_PCIE) == 0) {
1445 netif_err(efx, probe, efx->net_dev,
1446 "Falcon rev A1 PCI-X not supported\n");
1450 dev = pci_dev_get(efx->pci_dev);
1451 while ((dev = pci_get_device(EFX_VENDID_SFC, FALCON_A_S_DEVID,
1453 if (dev->bus == efx->pci_dev->bus &&
1454 dev->devfn == efx->pci_dev->devfn + 1) {
1455 nic_data->pci_dev2 = dev;
1459 if (!nic_data->pci_dev2) {
1460 netif_err(efx, probe, efx->net_dev,
1461 "failed to find secondary function\n");
1467 /* Now we can reset the NIC */
1468 rc = falcon_reset_hw(efx, RESET_TYPE_ALL);
1470 netif_err(efx, probe, efx->net_dev, "failed to reset NIC\n");
1474 /* Allocate memory for INT_KER */
1475 rc = efx_nic_alloc_buffer(efx, &efx->irq_status, sizeof(efx_oword_t));
1478 BUG_ON(efx->irq_status.dma_addr & 0x0f);
1480 netif_dbg(efx, probe, efx->net_dev,
1481 "INT_KER at %llx (virt %p phys %llx)\n",
1482 (u64)efx->irq_status.dma_addr,
1483 efx->irq_status.addr,
1484 (u64)virt_to_phys(efx->irq_status.addr));
1486 falcon_probe_spi_devices(efx);
1488 /* Read in the non-volatile configuration */
1489 rc = falcon_probe_nvconfig(efx);
1493 /* Initialise I2C adapter */
1494 board = falcon_board(efx);
1495 board->i2c_adap.owner = THIS_MODULE;
1496 board->i2c_data = falcon_i2c_bit_operations;
1497 board->i2c_data.data = efx;
1498 board->i2c_adap.algo_data = &board->i2c_data;
1499 board->i2c_adap.dev.parent = &efx->pci_dev->dev;
1500 strlcpy(board->i2c_adap.name, "SFC4000 GPIO",
1501 sizeof(board->i2c_adap.name));
1502 rc = i2c_bit_add_bus(&board->i2c_adap);
1506 rc = falcon_board(efx)->type->init(efx);
1508 netif_err(efx, probe, efx->net_dev,
1509 "failed to initialise board\n");
1513 nic_data->stats_disable_count = 1;
1514 setup_timer(&nic_data->stats_timer, &falcon_stats_timer_func,
1515 (unsigned long)efx);
1520 BUG_ON(i2c_del_adapter(&board->i2c_adap));
1521 memset(&board->i2c_adap, 0, sizeof(board->i2c_adap));
1523 falcon_remove_spi_devices(efx);
1524 efx_nic_free_buffer(efx, &efx->irq_status);
1527 if (nic_data->pci_dev2) {
1528 pci_dev_put(nic_data->pci_dev2);
1529 nic_data->pci_dev2 = NULL;
1533 kfree(efx->nic_data);
1537 static void falcon_init_rx_cfg(struct efx_nic *efx)
1539 /* Prior to Siena the RX DMA engine will split each frame at
1540 * intervals of RX_USR_BUF_SIZE (32-byte units). We set it to
1541 * be so large that that never happens. */
1542 const unsigned huge_buf_size = (3 * 4096) >> 5;
1543 /* RX control FIFO thresholds (32 entries) */
1544 const unsigned ctrl_xon_thr = 20;
1545 const unsigned ctrl_xoff_thr = 25;
1546 /* RX data FIFO thresholds (256-byte units; size varies) */
1547 int data_xon_thr = efx_nic_rx_xon_thresh >> 8;
1548 int data_xoff_thr = efx_nic_rx_xoff_thresh >> 8;
1551 efx_reado(efx, ®, FR_AZ_RX_CFG);
1552 if (efx_nic_rev(efx) <= EFX_REV_FALCON_A1) {
1553 /* Data FIFO size is 5.5K */
1554 if (data_xon_thr < 0)
1555 data_xon_thr = 512 >> 8;
1556 if (data_xoff_thr < 0)
1557 data_xoff_thr = 2048 >> 8;
1558 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_DESC_PUSH_EN, 0);
1559 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_USR_BUF_SIZE,
1561 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XON_MAC_TH, data_xon_thr);
1562 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XOFF_MAC_TH, data_xoff_thr);
1563 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XON_TX_TH, ctrl_xon_thr);
1564 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XOFF_TX_TH, ctrl_xoff_thr);
1566 /* Data FIFO size is 80K; register fields moved */
1567 if (data_xon_thr < 0)
1568 data_xon_thr = 27648 >> 8; /* ~3*max MTU */
1569 if (data_xoff_thr < 0)
1570 data_xoff_thr = 54272 >> 8; /* ~80Kb - 3*max MTU */
1571 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_DESC_PUSH_EN, 0);
1572 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_USR_BUF_SIZE,
1574 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XON_MAC_TH, data_xon_thr);
1575 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XOFF_MAC_TH, data_xoff_thr);
1576 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XON_TX_TH, ctrl_xon_thr);
1577 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XOFF_TX_TH, ctrl_xoff_thr);
1578 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 1);
1580 /* Enable hash insertion. This is broken for the
1581 * 'Falcon' hash so also select Toeplitz TCP/IPv4 and
1583 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_HASH_INSRT_HDR, 1);
1584 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_HASH_ALG, 1);
1585 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_IP_HASH, 1);
1587 /* Always enable XOFF signal from RX FIFO. We enable
1588 * or disable transmission of pause frames at the MAC. */
1589 EFX_SET_OWORD_FIELD(reg, FRF_AZ_RX_XOFF_MAC_EN, 1);
1590 efx_writeo(efx, ®, FR_AZ_RX_CFG);
1593 /* This call performs hardware-specific global initialisation, such as
1594 * defining the descriptor cache sizes and number of RSS channels.
1595 * It does not set up any buffers, descriptor rings or event queues.
1597 static int falcon_init_nic(struct efx_nic *efx)
1602 /* Use on-chip SRAM */
1603 efx_reado(efx, &temp, FR_AB_NIC_STAT);
1604 EFX_SET_OWORD_FIELD(temp, FRF_AB_ONCHIP_SRAM, 1);
1605 efx_writeo(efx, &temp, FR_AB_NIC_STAT);
1607 /* Set the source of the GMAC clock */
1608 if (efx_nic_rev(efx) == EFX_REV_FALCON_B0) {
1609 efx_reado(efx, &temp, FR_AB_GPIO_CTL);
1610 EFX_SET_OWORD_FIELD(temp, FRF_AB_USE_NIC_CLK, true);
1611 efx_writeo(efx, &temp, FR_AB_GPIO_CTL);
1614 /* Select the correct MAC */
1615 falcon_clock_mac(efx);
1617 rc = falcon_reset_sram(efx);
1621 /* Clear the parity enables on the TX data fifos as
1622 * they produce false parity errors because of timing issues
1624 if (EFX_WORKAROUND_5129(efx)) {
1625 efx_reado(efx, &temp, FR_AZ_CSR_SPARE);
1626 EFX_SET_OWORD_FIELD(temp, FRF_AB_MEM_PERR_EN_TX_DATA, 0);
1627 efx_writeo(efx, &temp, FR_AZ_CSR_SPARE);
1630 if (EFX_WORKAROUND_7244(efx)) {
1631 efx_reado(efx, &temp, FR_BZ_RX_FILTER_CTL);
1632 EFX_SET_OWORD_FIELD(temp, FRF_BZ_UDP_FULL_SRCH_LIMIT, 8);
1633 EFX_SET_OWORD_FIELD(temp, FRF_BZ_UDP_WILD_SRCH_LIMIT, 8);
1634 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TCP_FULL_SRCH_LIMIT, 8);
1635 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TCP_WILD_SRCH_LIMIT, 8);
1636 efx_writeo(efx, &temp, FR_BZ_RX_FILTER_CTL);
1639 /* XXX This is documented only for Falcon A0/A1 */
1640 /* Setup RX. Wait for descriptor is broken and must
1641 * be disabled. RXDP recovery shouldn't be needed, but is.
1643 efx_reado(efx, &temp, FR_AA_RX_SELF_RST);
1644 EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_NODESC_WAIT_DIS, 1);
1645 EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_SELF_RST_EN, 1);
1646 if (EFX_WORKAROUND_5583(efx))
1647 EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_ISCSI_DIS, 1);
1648 efx_writeo(efx, &temp, FR_AA_RX_SELF_RST);
1650 /* Do not enable TX_NO_EOP_DISC_EN, since it limits packets to 16
1651 * descriptors (which is bad).
1653 efx_reado(efx, &temp, FR_AZ_TX_CFG);
1654 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_NO_EOP_DISC_EN, 0);
1655 efx_writeo(efx, &temp, FR_AZ_TX_CFG);
1657 falcon_init_rx_cfg(efx);
1659 if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) {
1660 /* Set hash key for IPv4 */
1661 memcpy(&temp, efx->rx_hash_key, sizeof(temp));
1662 efx_writeo(efx, &temp, FR_BZ_RX_RSS_TKEY);
1664 /* Set destination of both TX and RX Flush events */
1665 EFX_POPULATE_OWORD_1(temp, FRF_BZ_FLS_EVQ_ID, 0);
1666 efx_writeo(efx, &temp, FR_BZ_DP_CTRL);
1669 efx_nic_init_common(efx);
1674 static void falcon_remove_nic(struct efx_nic *efx)
1676 struct falcon_nic_data *nic_data = efx->nic_data;
1677 struct falcon_board *board = falcon_board(efx);
1680 board->type->fini(efx);
1682 /* Remove I2C adapter and clear it in preparation for a retry */
1683 rc = i2c_del_adapter(&board->i2c_adap);
1685 memset(&board->i2c_adap, 0, sizeof(board->i2c_adap));
1687 falcon_remove_spi_devices(efx);
1688 efx_nic_free_buffer(efx, &efx->irq_status);
1690 falcon_reset_hw(efx, RESET_TYPE_ALL);
1692 /* Release the second function after the reset */
1693 if (nic_data->pci_dev2) {
1694 pci_dev_put(nic_data->pci_dev2);
1695 nic_data->pci_dev2 = NULL;
1698 /* Tear down the private nic state */
1699 kfree(efx->nic_data);
1700 efx->nic_data = NULL;
1703 static void falcon_update_nic_stats(struct efx_nic *efx)
1705 struct falcon_nic_data *nic_data = efx->nic_data;
1708 if (nic_data->stats_disable_count)
1711 efx_reado(efx, &cnt, FR_AZ_RX_NODESC_DROP);
1712 efx->n_rx_nodesc_drop_cnt +=
1713 EFX_OWORD_FIELD(cnt, FRF_AB_RX_NODESC_DROP_CNT);
1715 if (nic_data->stats_pending &&
1716 *nic_data->stats_dma_done == FALCON_STATS_DONE) {
1717 nic_data->stats_pending = false;
1718 rmb(); /* read the done flag before the stats */
1719 efx->mac_op->update_stats(efx);
1723 void falcon_start_nic_stats(struct efx_nic *efx)
1725 struct falcon_nic_data *nic_data = efx->nic_data;
1727 spin_lock_bh(&efx->stats_lock);
1728 if (--nic_data->stats_disable_count == 0)
1729 falcon_stats_request(efx);
1730 spin_unlock_bh(&efx->stats_lock);
1733 void falcon_stop_nic_stats(struct efx_nic *efx)
1735 struct falcon_nic_data *nic_data = efx->nic_data;
1740 spin_lock_bh(&efx->stats_lock);
1741 ++nic_data->stats_disable_count;
1742 spin_unlock_bh(&efx->stats_lock);
1744 del_timer_sync(&nic_data->stats_timer);
1746 /* Wait enough time for the most recent transfer to
1748 for (i = 0; i < 4 && nic_data->stats_pending; i++) {
1749 if (*nic_data->stats_dma_done == FALCON_STATS_DONE)
1754 spin_lock_bh(&efx->stats_lock);
1755 falcon_stats_complete(efx);
1756 spin_unlock_bh(&efx->stats_lock);
1759 static void falcon_set_id_led(struct efx_nic *efx, enum efx_led_mode mode)
1761 falcon_board(efx)->type->set_id_led(efx, mode);
1764 /**************************************************************************
1768 **************************************************************************
1771 static void falcon_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol)
1775 memset(&wol->sopass, 0, sizeof(wol->sopass));
1778 static int falcon_set_wol(struct efx_nic *efx, u32 type)
1785 /**************************************************************************
1787 * Revision-dependent attributes used by efx.c and nic.c
1789 **************************************************************************
1792 struct efx_nic_type falcon_a1_nic_type = {
1793 .probe = falcon_probe_nic,
1794 .remove = falcon_remove_nic,
1795 .init = falcon_init_nic,
1796 .fini = efx_port_dummy_op_void,
1797 .monitor = falcon_monitor,
1798 .reset = falcon_reset_hw,
1799 .probe_port = falcon_probe_port,
1800 .remove_port = falcon_remove_port,
1801 .prepare_flush = falcon_prepare_flush,
1802 .update_stats = falcon_update_nic_stats,
1803 .start_stats = falcon_start_nic_stats,
1804 .stop_stats = falcon_stop_nic_stats,
1805 .set_id_led = falcon_set_id_led,
1806 .push_irq_moderation = falcon_push_irq_moderation,
1807 .push_multicast_hash = falcon_push_multicast_hash,
1808 .reconfigure_port = falcon_reconfigure_port,
1809 .get_wol = falcon_get_wol,
1810 .set_wol = falcon_set_wol,
1811 .resume_wol = efx_port_dummy_op_void,
1812 .test_nvram = falcon_test_nvram,
1813 .default_mac_ops = &falcon_xmac_operations,
1815 .revision = EFX_REV_FALCON_A1,
1816 .mem_map_size = 0x20000,
1817 .txd_ptr_tbl_base = FR_AA_TX_DESC_PTR_TBL_KER,
1818 .rxd_ptr_tbl_base = FR_AA_RX_DESC_PTR_TBL_KER,
1819 .buf_tbl_base = FR_AA_BUF_FULL_TBL_KER,
1820 .evq_ptr_tbl_base = FR_AA_EVQ_PTR_TBL_KER,
1821 .evq_rptr_tbl_base = FR_AA_EVQ_RPTR_KER,
1822 .max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH),
1823 .rx_buffer_padding = 0x24,
1824 .max_interrupt_mode = EFX_INT_MODE_MSI,
1825 .phys_addr_channels = 4,
1826 .tx_dc_base = 0x130000,
1827 .rx_dc_base = 0x100000,
1828 .offload_features = NETIF_F_IP_CSUM,
1829 .reset_world_flags = ETH_RESET_IRQ,
1832 struct efx_nic_type falcon_b0_nic_type = {
1833 .probe = falcon_probe_nic,
1834 .remove = falcon_remove_nic,
1835 .init = falcon_init_nic,
1836 .fini = efx_port_dummy_op_void,
1837 .monitor = falcon_monitor,
1838 .reset = falcon_reset_hw,
1839 .probe_port = falcon_probe_port,
1840 .remove_port = falcon_remove_port,
1841 .prepare_flush = falcon_prepare_flush,
1842 .update_stats = falcon_update_nic_stats,
1843 .start_stats = falcon_start_nic_stats,
1844 .stop_stats = falcon_stop_nic_stats,
1845 .set_id_led = falcon_set_id_led,
1846 .push_irq_moderation = falcon_push_irq_moderation,
1847 .push_multicast_hash = falcon_push_multicast_hash,
1848 .reconfigure_port = falcon_reconfigure_port,
1849 .get_wol = falcon_get_wol,
1850 .set_wol = falcon_set_wol,
1851 .resume_wol = efx_port_dummy_op_void,
1852 .test_registers = falcon_b0_test_registers,
1853 .test_nvram = falcon_test_nvram,
1854 .default_mac_ops = &falcon_xmac_operations,
1856 .revision = EFX_REV_FALCON_B0,
1857 /* Map everything up to and including the RSS indirection
1858 * table. Don't map MSI-X table, MSI-X PBA since Linux
1859 * requires that they not be mapped. */
1860 .mem_map_size = (FR_BZ_RX_INDIRECTION_TBL +
1861 FR_BZ_RX_INDIRECTION_TBL_STEP *
1862 FR_BZ_RX_INDIRECTION_TBL_ROWS),
1863 .txd_ptr_tbl_base = FR_BZ_TX_DESC_PTR_TBL,
1864 .rxd_ptr_tbl_base = FR_BZ_RX_DESC_PTR_TBL,
1865 .buf_tbl_base = FR_BZ_BUF_FULL_TBL,
1866 .evq_ptr_tbl_base = FR_BZ_EVQ_PTR_TBL,
1867 .evq_rptr_tbl_base = FR_BZ_EVQ_RPTR,
1868 .max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH),
1869 .rx_buffer_hash_size = 0x10,
1870 .rx_buffer_padding = 0,
1871 .max_interrupt_mode = EFX_INT_MODE_MSIX,
1872 .phys_addr_channels = 32, /* Hardware limit is 64, but the legacy
1873 * interrupt handler only supports 32
1875 .tx_dc_base = 0x130000,
1876 .rx_dc_base = 0x100000,
1877 .offload_features = NETIF_F_IP_CSUM | NETIF_F_RXHASH,
1878 .reset_world_flags = ETH_RESET_IRQ,