1 /****************************************************************************
2 * Driver for Solarflare Solarstorm network controllers and boards
3 * Copyright 2006-2008 Solarflare Communications Inc.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published
7 * by the Free Software Foundation, incorporated herein by reference.
10 * Useful functions for working with MDIO clause 45 PHYs
12 #include <linux/types.h>
13 #include <linux/ethtool.h>
14 #include <linux/delay.h>
15 #include "net_driver.h"
19 int mdio_clause45_reset_mmd(struct efx_nic *port, int mmd,
20 int spins, int spintime)
23 int phy_id = port->mii.phy_id;
25 /* Catch callers passing values in the wrong units (or just silly) */
26 EFX_BUG_ON_PARANOID(spins * spintime >= 5000);
28 mdio_clause45_write(port, phy_id, mmd, MDIO_MMDREG_CTRL1,
29 (1 << MDIO_MMDREG_CTRL1_RESET_LBN));
30 /* Wait for the reset bit to clear. */
33 ctrl = mdio_clause45_read(port, phy_id, mmd, MDIO_MMDREG_CTRL1);
36 } while (spins && (ctrl & (1 << MDIO_MMDREG_CTRL1_RESET_LBN)));
38 return spins ? spins : -ETIMEDOUT;
41 static int mdio_clause45_check_mmd(struct efx_nic *efx, int mmd,
45 int phy_id = efx->mii.phy_id;
47 if (LOOPBACK_INTERNAL(efx))
50 if (mmd != MDIO_MMD_AN) {
51 /* Read MMD STATUS2 to check it is responding. */
52 status = mdio_clause45_read(efx, phy_id, mmd,
54 if (((status >> MDIO_MMDREG_STAT2_PRESENT_LBN) &
55 ((1 << MDIO_MMDREG_STAT2_PRESENT_WIDTH) - 1)) !=
56 MDIO_MMDREG_STAT2_PRESENT_VAL) {
57 EFX_ERR(efx, "PHY MMD %d not responding.\n", mmd);
62 /* Read MMD STATUS 1 to check for fault. */
63 status = mdio_clause45_read(efx, phy_id, mmd, MDIO_MMDREG_STAT1);
64 if ((status & (1 << MDIO_MMDREG_STAT1_FAULT_LBN)) != 0) {
66 EFX_ERR(efx, "PHY MMD %d reporting fatal"
67 " fault: status %x\n", mmd, status);
70 EFX_LOG(efx, "PHY MMD %d reporting status"
71 " %x (expected)\n", mmd, status);
77 /* This ought to be ridiculous overkill. We expect it to fail rarely */
78 #define MDIO45_RESET_TIME 1000 /* ms */
79 #define MDIO45_RESET_ITERS 100
81 int mdio_clause45_wait_reset_mmds(struct efx_nic *efx,
82 unsigned int mmd_mask)
84 const int spintime = MDIO45_RESET_TIME / MDIO45_RESET_ITERS;
85 int tries = MDIO45_RESET_ITERS;
96 stat = mdio_clause45_read(efx,
101 EFX_ERR(efx, "failed to read status of"
105 if (stat & (1 << MDIO_MMDREG_CTRL1_RESET_LBN))
106 in_reset |= (1 << mmd);
117 EFX_ERR(efx, "not all MMDs came out of reset in time."
118 " MMDs still in reset: %x\n", in_reset);
124 int mdio_clause45_check_mmds(struct efx_nic *efx,
125 unsigned int mmd_mask, unsigned int fatal_mask)
128 int mmd = 0, probe_mmd;
130 /* Historically we have probed the PHYXS to find out what devices are
131 * present,but that doesn't work so well if the PHYXS isn't expected
132 * to exist, if so just find the first item in the list supplied. */
133 probe_mmd = (mmd_mask & MDIO_MMDREG_DEVS_PHYXS) ? MDIO_MMD_PHYXS :
135 devices = (mdio_clause45_read(efx, efx->mii.phy_id,
136 probe_mmd, MDIO_MMDREG_DEVS0) |
137 mdio_clause45_read(efx, efx->mii.phy_id,
138 probe_mmd, MDIO_MMDREG_DEVS1) << 16);
140 /* Check all the expected MMDs are present */
142 EFX_ERR(efx, "failed to read devices present\n");
145 if ((devices & mmd_mask) != mmd_mask) {
146 EFX_ERR(efx, "required MMDs not present: got %x, "
147 "wanted %x\n", devices, mmd_mask);
150 EFX_TRACE(efx, "Devices present: %x\n", devices);
152 /* Check all required MMDs are responding and happy. */
155 int fault_fatal = fatal_mask & 1;
156 if (mdio_clause45_check_mmd(efx, mmd, fault_fatal))
159 mmd_mask = mmd_mask >> 1;
160 fatal_mask = fatal_mask >> 1;
167 bool mdio_clause45_links_ok(struct efx_nic *efx, unsigned int mmd_mask)
169 int phy_id = efx->mii.phy_id;
174 /* If the port is in loopback, then we should only consider a subset
176 if (LOOPBACK_INTERNAL(efx))
178 else if (efx->loopback_mode == LOOPBACK_NETWORK)
180 else if (efx_phy_mode_disabled(efx->phy_mode))
182 else if (efx->loopback_mode == LOOPBACK_PHYXS)
183 mmd_mask &= ~(MDIO_MMDREG_DEVS_PHYXS |
184 MDIO_MMDREG_DEVS_PCS |
185 MDIO_MMDREG_DEVS_PMAPMD |
186 MDIO_MMDREG_DEVS_AN);
187 else if (efx->loopback_mode == LOOPBACK_PCS)
188 mmd_mask &= ~(MDIO_MMDREG_DEVS_PCS |
189 MDIO_MMDREG_DEVS_PMAPMD |
190 MDIO_MMDREG_DEVS_AN);
191 else if (efx->loopback_mode == LOOPBACK_PMAPMD)
192 mmd_mask &= ~(MDIO_MMDREG_DEVS_PMAPMD |
193 MDIO_MMDREG_DEVS_AN);
197 /* Double reads because link state is latched, and a
198 * read moves the current state into the register */
199 status = mdio_clause45_read(efx, phy_id,
200 mmd, MDIO_MMDREG_STAT1);
201 status = mdio_clause45_read(efx, phy_id,
202 mmd, MDIO_MMDREG_STAT1);
204 ok = ok && (status & (1 << MDIO_MMDREG_STAT1_LINK_LBN));
206 mmd_mask = (mmd_mask >> 1);
212 void mdio_clause45_transmit_disable(struct efx_nic *efx)
214 mdio_clause45_set_flag(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD,
215 MDIO_MMDREG_TXDIS, MDIO_MMDREG_TXDIS_GLOBAL_LBN,
216 efx->phy_mode & PHY_MODE_TX_DISABLED);
219 void mdio_clause45_phy_reconfigure(struct efx_nic *efx)
221 int phy_id = efx->mii.phy_id;
223 mdio_clause45_set_flag(efx, phy_id, MDIO_MMD_PMAPMD,
224 MDIO_MMDREG_CTRL1, MDIO_PMAPMD_CTRL1_LBACK_LBN,
225 efx->loopback_mode == LOOPBACK_PMAPMD);
226 mdio_clause45_set_flag(efx, phy_id, MDIO_MMD_PCS,
227 MDIO_MMDREG_CTRL1, MDIO_MMDREG_CTRL1_LBACK_LBN,
228 efx->loopback_mode == LOOPBACK_PCS);
229 mdio_clause45_set_flag(efx, phy_id, MDIO_MMD_PHYXS,
230 MDIO_MMDREG_CTRL1, MDIO_MMDREG_CTRL1_LBACK_LBN,
231 efx->loopback_mode == LOOPBACK_NETWORK);
234 static void mdio_clause45_set_mmd_lpower(struct efx_nic *efx,
237 int phy = efx->mii.phy_id;
238 int stat = mdio_clause45_read(efx, phy, mmd, MDIO_MMDREG_STAT1);
240 EFX_TRACE(efx, "Setting low power mode for MMD %d to %d\n",
243 if (stat & (1 << MDIO_MMDREG_STAT1_LPABLE_LBN)) {
244 mdio_clause45_set_flag(efx, phy, mmd, MDIO_MMDREG_CTRL1,
245 MDIO_MMDREG_CTRL1_LPOWER_LBN, lpower);
249 void mdio_clause45_set_mmds_lpower(struct efx_nic *efx,
250 int low_power, unsigned int mmd_mask)
253 mmd_mask &= ~MDIO_MMDREG_DEVS_AN;
256 mdio_clause45_set_mmd_lpower(efx, low_power, mmd);
257 mmd_mask = (mmd_mask >> 1);
262 static u32 mdio_clause45_get_an(struct efx_nic *efx, u16 addr, u32 xnp)
264 int phy_id = efx->mii.phy_id;
268 reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_AN, addr);
269 if (reg & ADVERTISE_10HALF)
270 result |= ADVERTISED_10baseT_Half;
271 if (reg & ADVERTISE_10FULL)
272 result |= ADVERTISED_10baseT_Full;
273 if (reg & ADVERTISE_100HALF)
274 result |= ADVERTISED_100baseT_Half;
275 if (reg & ADVERTISE_100FULL)
276 result |= ADVERTISED_100baseT_Full;
284 * mdio_clause45_get_settings - Read (some of) the PHY settings over MDIO.
286 * @ecmd: Buffer for settings
288 * On return the 'port', 'speed', 'supported' and 'advertising' fields of
289 * ecmd have been filled out.
291 void mdio_clause45_get_settings(struct efx_nic *efx,
292 struct ethtool_cmd *ecmd)
294 mdio_clause45_get_settings_ext(efx, ecmd, 0, 0);
298 * mdio_clause45_get_settings_ext - Read (some of) the PHY settings over MDIO.
300 * @ecmd: Buffer for settings
301 * @xnp: Advertised Extended Next Page state
302 * @xnp_lpa: Link Partner's advertised XNP state
304 * On return the 'port', 'speed', 'supported' and 'advertising' fields of
305 * ecmd have been filled out.
307 void mdio_clause45_get_settings_ext(struct efx_nic *efx,
308 struct ethtool_cmd *ecmd,
309 u32 xnp, u32 xnp_lpa)
311 int phy_id = efx->mii.phy_id;
314 ecmd->transceiver = XCVR_INTERNAL;
315 ecmd->phy_address = phy_id;
317 reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_PMAPMD,
319 switch (reg & MDIO_PMAPMD_CTRL2_TYPE_MASK) {
320 case MDIO_PMAPMD_CTRL2_10G_BT:
321 case MDIO_PMAPMD_CTRL2_1G_BT:
322 case MDIO_PMAPMD_CTRL2_100_BT:
323 case MDIO_PMAPMD_CTRL2_10_BT:
324 ecmd->port = PORT_TP;
325 ecmd->supported = SUPPORTED_TP;
326 reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_PMAPMD,
328 if (reg & (1 << MDIO_MMDREG_SPEED_10G_LBN))
329 ecmd->supported |= SUPPORTED_10000baseT_Full;
330 if (reg & (1 << MDIO_MMDREG_SPEED_1000M_LBN))
331 ecmd->supported |= (SUPPORTED_1000baseT_Full |
332 SUPPORTED_1000baseT_Half);
333 if (reg & (1 << MDIO_MMDREG_SPEED_100M_LBN))
334 ecmd->supported |= (SUPPORTED_100baseT_Full |
335 SUPPORTED_100baseT_Half);
336 if (reg & (1 << MDIO_MMDREG_SPEED_10M_LBN))
337 ecmd->supported |= (SUPPORTED_10baseT_Full |
338 SUPPORTED_10baseT_Half);
339 ecmd->advertising = ADVERTISED_TP;
342 /* We represent CX4 as fibre in the absence of anything better */
343 case MDIO_PMAPMD_CTRL2_10G_CX4:
344 /* All the other defined modes are flavours of optical */
346 ecmd->port = PORT_FIBRE;
347 ecmd->supported = SUPPORTED_FIBRE;
348 ecmd->advertising = ADVERTISED_FIBRE;
352 if (efx->phy_op->mmds & DEV_PRESENT_BIT(MDIO_MMD_AN)) {
353 ecmd->supported |= SUPPORTED_Autoneg;
354 reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_AN,
356 if (reg & BMCR_ANENABLE) {
357 ecmd->autoneg = AUTONEG_ENABLE;
360 mdio_clause45_get_an(efx,
361 MDIO_AN_ADVERTISE, xnp);
363 ecmd->autoneg = AUTONEG_DISABLE;
365 ecmd->autoneg = AUTONEG_DISABLE;
367 /* If AN is enabled and complete, report best common mode */
369 (mdio_clause45_read(efx, phy_id, MDIO_MMD_AN, MDIO_MMDREG_STAT1) &
370 (1 << MDIO_AN_STATUS_AN_DONE_LBN))) {
372 lpa = mdio_clause45_get_an(efx, MDIO_AN_LPA, xnp_lpa);
373 common = ecmd->advertising & lpa;
374 if (common & ADVERTISED_10000baseT_Full) {
375 ecmd->speed = SPEED_10000;
376 ecmd->duplex = DUPLEX_FULL;
377 } else if (common & (ADVERTISED_1000baseT_Full |
378 ADVERTISED_1000baseT_Half)) {
379 ecmd->speed = SPEED_1000;
380 ecmd->duplex = !!(common & ADVERTISED_1000baseT_Full);
381 } else if (common & (ADVERTISED_100baseT_Full |
382 ADVERTISED_100baseT_Half)) {
383 ecmd->speed = SPEED_100;
384 ecmd->duplex = !!(common & ADVERTISED_100baseT_Full);
386 ecmd->speed = SPEED_10;
387 ecmd->duplex = !!(common & ADVERTISED_10baseT_Full);
390 /* Report forced settings */
391 reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_PMAPMD,
393 ecmd->speed = (((reg & BMCR_SPEED1000) ? 100 : 1) *
394 ((reg & BMCR_SPEED100) ? 100 : 10));
395 ecmd->duplex = (reg & BMCR_FULLDPLX ||
396 ecmd->speed == SPEED_10000);
401 * mdio_clause45_set_settings - Set (some of) the PHY settings over MDIO.
403 * @ecmd: New settings
405 int mdio_clause45_set_settings(struct efx_nic *efx,
406 struct ethtool_cmd *ecmd)
408 int phy_id = efx->mii.phy_id;
409 struct ethtool_cmd prev;
413 efx->phy_op->get_settings(efx, &prev);
415 if (ecmd->advertising == prev.advertising &&
416 ecmd->speed == prev.speed &&
417 ecmd->duplex == prev.duplex &&
418 ecmd->port == prev.port &&
419 ecmd->autoneg == prev.autoneg)
422 /* We can only change these settings for -T PHYs */
423 if (prev.port != PORT_TP || ecmd->port != PORT_TP)
426 /* Check that PHY supports these settings and work out the
427 * basic control bits */
429 switch (ecmd->speed) {
431 ctrl1_bits = BMCR_FULLDPLX;
432 required = SUPPORTED_10baseT_Full;
435 ctrl1_bits = BMCR_SPEED100 | BMCR_FULLDPLX;
436 required = SUPPORTED_100baseT_Full;
439 ctrl1_bits = BMCR_SPEED1000 | BMCR_FULLDPLX;
440 required = SUPPORTED_1000baseT_Full;
443 ctrl1_bits = (BMCR_SPEED1000 | BMCR_SPEED100 |
445 required = SUPPORTED_10000baseT_Full;
451 switch (ecmd->speed) {
454 required = SUPPORTED_10baseT_Half;
457 ctrl1_bits = BMCR_SPEED100;
458 required = SUPPORTED_100baseT_Half;
461 ctrl1_bits = BMCR_SPEED1000;
462 required = SUPPORTED_1000baseT_Half;
469 required |= SUPPORTED_Autoneg;
470 required |= ecmd->advertising;
471 if (required & ~prev.supported)
474 /* Set the basic control bits */
475 reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_PMAPMD,
477 reg &= ~(BMCR_SPEED1000 | BMCR_SPEED100 | BMCR_FULLDPLX | 0x003c);
479 mdio_clause45_write(efx, phy_id, MDIO_MMD_PMAPMD, MDIO_MMDREG_CTRL1,
482 /* Set the AN registers */
483 if (ecmd->autoneg != prev.autoneg ||
484 ecmd->advertising != prev.advertising) {
487 if (efx->phy_op->set_xnp_advertise)
488 xnp = efx->phy_op->set_xnp_advertise(efx,
493 if (ecmd->advertising & ADVERTISED_10baseT_Half)
494 reg |= ADVERTISE_10HALF;
495 if (ecmd->advertising & ADVERTISED_10baseT_Full)
496 reg |= ADVERTISE_10FULL;
497 if (ecmd->advertising & ADVERTISED_100baseT_Half)
498 reg |= ADVERTISE_100HALF;
499 if (ecmd->advertising & ADVERTISED_100baseT_Full)
500 reg |= ADVERTISE_100FULL;
502 reg |= ADVERTISE_RESV;
503 mdio_clause45_write(efx, phy_id, MDIO_MMD_AN,
504 MDIO_AN_ADVERTISE, reg);
507 reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_AN,
510 reg |= BMCR_ANENABLE | BMCR_ANRESTART;
512 reg &= ~BMCR_ANENABLE;
514 reg |= 1 << MDIO_AN_CTRL_XNP_LBN;
516 reg &= ~(1 << MDIO_AN_CTRL_XNP_LBN);
517 mdio_clause45_write(efx, phy_id, MDIO_MMD_AN,
518 MDIO_MMDREG_CTRL1, reg);
524 void mdio_clause45_set_pause(struct efx_nic *efx)
526 int phy_id = efx->mii.phy_id;
529 if (efx->phy_op->mmds & DEV_PRESENT_BIT(MDIO_MMD_AN)) {
530 /* Set pause capability advertising */
531 reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_AN,
533 reg &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
534 reg |= efx_fc_advertise(efx->wanted_fc);
535 mdio_clause45_write(efx, phy_id, MDIO_MMD_AN,
536 MDIO_AN_ADVERTISE, reg);
538 /* Restart auto-negotiation */
539 reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_AN,
541 if (reg & BMCR_ANENABLE) {
542 reg |= BMCR_ANRESTART;
543 mdio_clause45_write(efx, phy_id, MDIO_MMD_AN,
544 MDIO_MMDREG_CTRL1, reg);
549 enum efx_fc_type mdio_clause45_get_pause(struct efx_nic *efx)
551 int phy_id = efx->mii.phy_id;
554 if (!(efx->phy_op->mmds & DEV_PRESENT_BIT(MDIO_MMD_AN)))
555 return efx->wanted_fc;
556 lpa = mdio_clause45_read(efx, phy_id, MDIO_MMD_AN, MDIO_AN_LPA);
557 return efx_fc_resolve(efx->wanted_fc, lpa);
560 void mdio_clause45_set_flag(struct efx_nic *efx, u8 prt, u8 dev,
561 u16 addr, int bit, bool sense)
563 int old_val = mdio_clause45_read(efx, prt, dev, addr);
567 new_val = old_val | (1 << bit);
569 new_val = old_val & ~(1 << bit);
570 if (old_val != new_val)
571 mdio_clause45_write(efx, prt, dev, addr, new_val);