1 /****************************************************************************
2 * Driver for Solarflare Solarstorm network controllers and boards
3 * Copyright 2006-2008 Solarflare Communications Inc.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published
7 * by the Free Software Foundation, incorporated herein by reference.
10 * Driver for AMCC QT202x SFP+ and XFP adapters; see www.amcc.com for details
13 #include <linux/timer.h>
14 #include <linux/delay.h>
20 #define QT202X_REQUIRED_DEVS (MDIO_DEVS_PCS | \
24 #define QT202X_LOOPBACKS ((1 << LOOPBACK_PCS) | \
25 (1 << LOOPBACK_PMAPMD) | \
26 (1 << LOOPBACK_NETWORK))
28 /****************************************************************************/
29 /* Quake-specific MDIO registers */
30 #define MDIO_QUAKE_LED0_REG (0xD006)
33 #define PCS_FW_HEARTBEAT_REG 0xd7ee
34 #define PCS_FW_HEARTB_LBN 0
35 #define PCS_FW_HEARTB_WIDTH 8
36 #define PCS_UC8051_STATUS_REG 0xd7fd
37 #define PCS_UC_STATUS_LBN 0
38 #define PCS_UC_STATUS_WIDTH 8
39 #define PCS_UC_STATUS_FW_SAVE 0x20
40 #define PMA_PMD_FTX_CTRL2_REG 0xc309
41 #define PMA_PMD_FTX_STATIC_LBN 13
42 #define PMA_PMD_VEND1_REG 0xc001
43 #define PMA_PMD_VEND1_LBTXD_LBN 15
44 #define PCS_VEND1_REG 0xc000
45 #define PCS_VEND1_LBTXD_LBN 5
47 void falcon_qt202x_set_led(struct efx_nic *p, int led, int mode)
49 int addr = MDIO_QUAKE_LED0_REG + led;
50 efx_mdio_write(p, MDIO_MMD_PMAPMD, addr, mode);
53 struct qt202x_phy_data {
54 enum efx_phy_mode phy_mode;
57 #define QT2022C2_MAX_RESET_TIME 500
58 #define QT2022C2_RESET_WAIT 10
60 static int qt2025c_wait_reset(struct efx_nic *efx)
62 unsigned long timeout = jiffies + 10 * HZ;
63 int reg, old_counter = 0;
65 /* Wait for firmware heartbeat to start */
68 reg = efx_mdio_read(efx, MDIO_MMD_PCS, PCS_FW_HEARTBEAT_REG);
71 counter = ((reg >> PCS_FW_HEARTB_LBN) &
72 ((1 << PCS_FW_HEARTB_WIDTH) - 1));
74 old_counter = counter;
75 else if (counter != old_counter)
77 if (time_after(jiffies, timeout))
82 /* Wait for firmware status to look good */
84 reg = efx_mdio_read(efx, MDIO_MMD_PCS, PCS_UC8051_STATUS_REG);
88 ((1 << PCS_UC_STATUS_WIDTH) - 1) << PCS_UC_STATUS_LBN) >=
89 PCS_UC_STATUS_FW_SAVE)
91 if (time_after(jiffies, timeout))
99 static int qt202x_reset_phy(struct efx_nic *efx)
103 if (efx->phy_type == PHY_TYPE_QT2025C) {
104 /* Wait for the reset triggered by falcon_reset_hw()
106 rc = qt2025c_wait_reset(efx);
110 /* Reset the PHYXS MMD. This is documented as doing
111 * a complete soft reset. */
112 rc = efx_mdio_reset_mmd(efx, MDIO_MMD_PHYXS,
113 QT2022C2_MAX_RESET_TIME /
115 QT2022C2_RESET_WAIT);
120 /* Wait 250ms for the PHY to complete bootup */
123 /* Check that all the MMDs we expect are present and responding. We
124 * expect faults on some if the link is down, but not on the PHY XS */
125 rc = efx_mdio_check_mmds(efx, QT202X_REQUIRED_DEVS, MDIO_DEVS_PHYXS);
129 efx->board_info.init_phy(efx);
134 EFX_ERR(efx, "PHY reset timed out\n");
138 static int qt202x_phy_init(struct efx_nic *efx)
140 struct qt202x_phy_data *phy_data;
141 u32 devid = efx_mdio_read_id(efx, MDIO_MMD_PHYXS);
144 phy_data = kzalloc(sizeof(struct qt202x_phy_data), GFP_KERNEL);
147 efx->phy_data = phy_data;
149 EFX_INFO(efx, "PHY ID reg %x (OUI %06x model %02x revision %x)\n",
150 devid, efx_mdio_id_oui(devid), efx_mdio_id_model(devid),
151 efx_mdio_id_rev(devid));
153 phy_data->phy_mode = efx->phy_mode;
155 rc = qt202x_reset_phy(efx);
157 EFX_INFO(efx, "PHY init %s.\n",
158 rc ? "failed" : "successful");
165 kfree(efx->phy_data);
166 efx->phy_data = NULL;
170 static void qt202x_phy_clear_interrupt(struct efx_nic *efx)
172 /* Read to clear link status alarm */
173 efx_mdio_read(efx, MDIO_MMD_PMAPMD, MDIO_PMA_LASI_STAT);
176 static int qt202x_link_ok(struct efx_nic *efx)
178 return efx_mdio_links_ok(efx, QT202X_REQUIRED_DEVS);
181 static void qt202x_phy_poll(struct efx_nic *efx)
183 int link_up = qt202x_link_ok(efx);
184 /* Simulate a PHY event if link state has changed */
185 if (link_up != efx->link_up)
186 falcon_sim_phy_event(efx);
189 static void qt202x_phy_reconfigure(struct efx_nic *efx)
191 struct qt202x_phy_data *phy_data = efx->phy_data;
193 if (efx->phy_type == PHY_TYPE_QT2025C) {
194 /* There are several different register bits which can
195 * disable TX (and save power) on direct-attach cables
196 * or optical transceivers, varying somewhat between
197 * firmware versions. Only 'static mode' appears to
198 * cover everything. */
200 &efx->mdio, efx->mdio.prtad, MDIO_MMD_PMAPMD,
201 PMA_PMD_FTX_CTRL2_REG, 1 << PMA_PMD_FTX_STATIC_LBN,
202 efx->phy_mode & PHY_MODE_TX_DISABLED ||
203 efx->phy_mode & PHY_MODE_LOW_POWER ||
204 efx->loopback_mode == LOOPBACK_PCS ||
205 efx->loopback_mode == LOOPBACK_PMAPMD);
207 /* Reset the PHY when moving from tx off to tx on */
208 if (!(efx->phy_mode & PHY_MODE_TX_DISABLED) &&
209 (phy_data->phy_mode & PHY_MODE_TX_DISABLED))
210 qt202x_reset_phy(efx);
212 efx_mdio_transmit_disable(efx);
215 efx_mdio_phy_reconfigure(efx);
217 phy_data->phy_mode = efx->phy_mode;
218 efx->link_up = qt202x_link_ok(efx);
219 efx->link_speed = 10000;
221 efx->link_fc = efx->wanted_fc;
224 static void qt202x_phy_get_settings(struct efx_nic *efx, struct ethtool_cmd *ecmd)
226 mdio45_ethtool_gset(&efx->mdio, ecmd);
229 static void qt202x_phy_fini(struct efx_nic *efx)
231 /* Free the context block */
232 kfree(efx->phy_data);
233 efx->phy_data = NULL;
236 struct efx_phy_operations falcon_qt202x_phy_ops = {
238 .init = qt202x_phy_init,
239 .reconfigure = qt202x_phy_reconfigure,
240 .poll = qt202x_phy_poll,
241 .fini = qt202x_phy_fini,
242 .clear_interrupt = qt202x_phy_clear_interrupt,
243 .get_settings = qt202x_phy_get_settings,
244 .set_settings = efx_mdio_set_settings,
245 .mmds = QT202X_REQUIRED_DEVS,
246 .loopbacks = QT202X_LOOPBACKS,