1 /****************************************************************************
2 * Driver for Solarflare Solarstorm network controllers and boards
3 * Copyright 2005-2006 Fen Systems Ltd.
4 * Copyright 2006-2009 Solarflare Communications Inc.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
11 #include <linux/bitops.h>
12 #include <linux/delay.h>
13 #include <linux/pci.h>
14 #include <linux/module.h>
15 #include <linux/slab.h>
16 #include <linux/random.h>
17 #include "net_driver.h"
26 #include "workarounds.h"
28 #include "mcdi_pcol.h"
30 /* Hardware control for SFC9000 family including SFL9021 (aka Siena). */
32 static void siena_init_wol(struct efx_nic *efx);
35 static void siena_push_irq_moderation(struct efx_channel *channel)
37 efx_dword_t timer_cmd;
39 if (channel->irq_moderation)
40 EFX_POPULATE_DWORD_2(timer_cmd,
42 FFE_CZ_TIMER_MODE_INT_HLDOFF,
44 channel->irq_moderation - 1);
46 EFX_POPULATE_DWORD_2(timer_cmd,
48 FFE_CZ_TIMER_MODE_DIS,
49 FRF_CZ_TC_TIMER_VAL, 0);
50 efx_writed_page_locked(channel->efx, &timer_cmd, FR_BZ_TIMER_COMMAND_P0,
54 static void siena_push_multicast_hash(struct efx_nic *efx)
56 WARN_ON(!mutex_is_locked(&efx->mac_lock));
58 efx_mcdi_rpc(efx, MC_CMD_SET_MCAST_HASH,
59 efx->multicast_hash.byte, sizeof(efx->multicast_hash),
63 static int siena_mdio_write(struct net_device *net_dev,
64 int prtad, int devad, u16 addr, u16 value)
66 struct efx_nic *efx = netdev_priv(net_dev);
70 rc = efx_mcdi_mdio_write(efx, efx->mdio_bus, prtad, devad,
71 addr, value, &status);
74 if (status != MC_CMD_MDIO_STATUS_GOOD)
80 static int siena_mdio_read(struct net_device *net_dev,
81 int prtad, int devad, u16 addr)
83 struct efx_nic *efx = netdev_priv(net_dev);
88 rc = efx_mcdi_mdio_read(efx, efx->mdio_bus, prtad, devad,
89 addr, &value, &status);
92 if (status != MC_CMD_MDIO_STATUS_GOOD)
98 /* This call is responsible for hooking in the MAC and PHY operations */
99 static int siena_probe_port(struct efx_nic *efx)
103 /* Hook in PHY operations table */
104 efx->phy_op = &efx_mcdi_phy_ops;
106 /* Set up MDIO structure for PHY */
107 efx->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
108 efx->mdio.mdio_read = siena_mdio_read;
109 efx->mdio.mdio_write = siena_mdio_write;
111 /* Fill out MDIO structure, loopback modes, and initial link state */
112 rc = efx->phy_op->probe(efx);
116 /* Allocate buffer for stats */
117 rc = efx_nic_alloc_buffer(efx, &efx->stats_buffer,
118 MC_CMD_MAC_NSTATS * sizeof(u64));
121 EFX_LOG(efx, "stats buffer at %llx (virt %p phys %llx)\n",
122 (u64)efx->stats_buffer.dma_addr,
123 efx->stats_buffer.addr,
124 (u64)virt_to_phys(efx->stats_buffer.addr));
126 efx_mcdi_mac_stats(efx, efx->stats_buffer.dma_addr, 0, 0, 1);
131 void siena_remove_port(struct efx_nic *efx)
133 efx->phy_op->remove(efx);
134 efx_nic_free_buffer(efx, &efx->stats_buffer);
137 static const struct efx_nic_register_test siena_register_tests[] = {
139 EFX_OWORD32(0x0003FFFF, 0x0003FFFF, 0x0003FFFF, 0x0003FFFF) },
141 EFX_OWORD32(0x000103FF, 0x00000000, 0x00000000, 0x00000000) },
143 EFX_OWORD32(0xFFFFFFFE, 0xFFFFFFFF, 0x0003FFFF, 0x00000000) },
145 EFX_OWORD32(0x7FFF0037, 0xFFFF8000, 0xFFFFFFFF, 0x03FFFFFF) },
147 EFX_OWORD32(0xFFFEFE80, 0x1FFFFFFF, 0x020000FE, 0x007FFFFF) },
148 { FR_AZ_SRM_TX_DC_CFG,
149 EFX_OWORD32(0x001FFFFF, 0x00000000, 0x00000000, 0x00000000) },
151 EFX_OWORD32(0x00000003, 0x00000000, 0x00000000, 0x00000000) },
153 EFX_OWORD32(0x000003FF, 0x00000000, 0x00000000, 0x00000000) },
155 EFX_OWORD32(0x00000FFF, 0x00000000, 0x00000000, 0x00000000) },
157 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) },
158 { FR_CZ_RX_RSS_IPV6_REG1,
159 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) },
160 { FR_CZ_RX_RSS_IPV6_REG2,
161 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) },
162 { FR_CZ_RX_RSS_IPV6_REG3,
163 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0x00000007, 0x00000000) },
166 static int siena_test_registers(struct efx_nic *efx)
168 return efx_nic_test_registers(efx, siena_register_tests,
169 ARRAY_SIZE(siena_register_tests));
172 /**************************************************************************
176 **************************************************************************
179 static int siena_reset_hw(struct efx_nic *efx, enum reset_type method)
183 /* Recover from a failed assertion pre-reset */
184 rc = efx_mcdi_handle_assertion(efx);
188 if (method == RESET_TYPE_WORLD)
189 return efx_mcdi_reset_mc(efx);
191 return efx_mcdi_reset_port(efx);
194 static int siena_probe_nvconfig(struct efx_nic *efx)
198 rc = efx_mcdi_get_board_cfg(efx, efx->mac_address, NULL);
205 static int siena_probe_nic(struct efx_nic *efx)
207 struct siena_nic_data *nic_data;
208 bool already_attached = 0;
211 /* Allocate storage for hardware specific data */
212 nic_data = kzalloc(sizeof(struct siena_nic_data), GFP_KERNEL);
215 efx->nic_data = nic_data;
217 if (efx_nic_fpga_ver(efx) != 0) {
218 EFX_ERR(efx, "Siena FPGA not supported\n");
225 /* Recover from a failed assertion before probing */
226 rc = efx_mcdi_handle_assertion(efx);
230 rc = efx_mcdi_fwver(efx, &nic_data->fw_version, &nic_data->fw_build);
232 EFX_ERR(efx, "Failed to read MCPU firmware version - "
234 goto fail1; /* MCPU absent? */
237 /* Let the BMC know that the driver is now in charge of link and
238 * filter settings. We must do this before we reset the NIC */
239 rc = efx_mcdi_drv_attach(efx, true, &already_attached);
241 EFX_ERR(efx, "Unable to register driver with MCPU\n");
244 if (already_attached)
245 /* Not a fatal error */
246 EFX_ERR(efx, "Host already registered with MCPU\n");
248 /* Now we can reset the NIC */
249 rc = siena_reset_hw(efx, RESET_TYPE_ALL);
251 EFX_ERR(efx, "failed to reset NIC\n");
257 /* Allocate memory for INT_KER */
258 rc = efx_nic_alloc_buffer(efx, &efx->irq_status, sizeof(efx_oword_t));
261 BUG_ON(efx->irq_status.dma_addr & 0x0f);
263 EFX_LOG(efx, "INT_KER at %llx (virt %p phys %llx)\n",
264 (unsigned long long)efx->irq_status.dma_addr,
265 efx->irq_status.addr,
266 (unsigned long long)virt_to_phys(efx->irq_status.addr));
268 /* Read in the non-volatile configuration */
269 rc = siena_probe_nvconfig(efx);
271 EFX_ERR(efx, "NVRAM is invalid therefore using defaults\n");
272 efx->phy_type = PHY_TYPE_NONE;
273 efx->mdio.prtad = MDIO_PRTAD_NONE;
278 get_random_bytes(&nic_data->ipv6_rss_key,
279 sizeof(nic_data->ipv6_rss_key));
284 efx_nic_free_buffer(efx, &efx->irq_status);
287 efx_mcdi_drv_attach(efx, false, NULL);
290 kfree(efx->nic_data);
294 /* This call performs hardware-specific global initialisation, such as
295 * defining the descriptor cache sizes and number of RSS channels.
296 * It does not set up any buffers, descriptor rings or event queues.
298 static int siena_init_nic(struct efx_nic *efx)
300 struct siena_nic_data *nic_data = efx->nic_data;
304 /* Recover from a failed assertion post-reset */
305 rc = efx_mcdi_handle_assertion(efx);
309 /* Squash TX of packets of 16 bytes or less */
310 efx_reado(efx, &temp, FR_AZ_TX_RESERVED);
311 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TX_FLUSH_MIN_LEN_EN, 1);
312 efx_writeo(efx, &temp, FR_AZ_TX_RESERVED);
314 /* Do not enable TX_NO_EOP_DISC_EN, since it limits packets to 16
315 * descriptors (which is bad).
317 efx_reado(efx, &temp, FR_AZ_TX_CFG);
318 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_NO_EOP_DISC_EN, 0);
319 EFX_SET_OWORD_FIELD(temp, FRF_CZ_TX_FILTER_EN_BIT, 1);
320 efx_writeo(efx, &temp, FR_AZ_TX_CFG);
322 efx_reado(efx, &temp, FR_AZ_RX_CFG);
323 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_DESC_PUSH_EN, 0);
324 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_INGR_EN, 1);
325 efx_writeo(efx, &temp, FR_AZ_RX_CFG);
327 /* Enable IPv6 RSS */
328 BUILD_BUG_ON(sizeof(nic_data->ipv6_rss_key) !=
329 2 * sizeof(temp) + FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH / 8 ||
330 FRF_CZ_RX_RSS_IPV6_TKEY_HI_LBN != 0);
331 memcpy(&temp, nic_data->ipv6_rss_key, sizeof(temp));
332 efx_writeo(efx, &temp, FR_CZ_RX_RSS_IPV6_REG1);
333 memcpy(&temp, nic_data->ipv6_rss_key + sizeof(temp), sizeof(temp));
334 efx_writeo(efx, &temp, FR_CZ_RX_RSS_IPV6_REG2);
335 EFX_POPULATE_OWORD_2(temp, FRF_CZ_RX_RSS_IPV6_THASH_ENABLE, 1,
336 FRF_CZ_RX_RSS_IPV6_IP_THASH_ENABLE, 1);
337 memcpy(&temp, nic_data->ipv6_rss_key + 2 * sizeof(temp),
338 FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH / 8);
339 efx_writeo(efx, &temp, FR_CZ_RX_RSS_IPV6_REG3);
341 if (efx_nic_rx_xoff_thresh >= 0 || efx_nic_rx_xon_thresh >= 0)
342 /* No MCDI operation has been defined to set thresholds */
343 EFX_ERR(efx, "ignoring RX flow control thresholds\n");
345 /* Enable event logging */
346 rc = efx_mcdi_log_ctrl(efx, true, false, 0);
350 /* Set destination of both TX and RX Flush events */
351 EFX_POPULATE_OWORD_1(temp, FRF_BZ_FLS_EVQ_ID, 0);
352 efx_writeo(efx, &temp, FR_BZ_DP_CTRL);
354 EFX_POPULATE_OWORD_1(temp, FRF_CZ_USREV_DIS, 1);
355 efx_writeo(efx, &temp, FR_CZ_USR_EV_CFG);
357 efx_nic_init_common(efx);
361 static void siena_remove_nic(struct efx_nic *efx)
363 efx_nic_free_buffer(efx, &efx->irq_status);
365 siena_reset_hw(efx, RESET_TYPE_ALL);
367 /* Relinquish the device back to the BMC */
368 if (efx_nic_has_mc(efx))
369 efx_mcdi_drv_attach(efx, false, NULL);
371 /* Tear down the private nic state */
372 kfree(efx->nic_data);
373 efx->nic_data = NULL;
376 #define STATS_GENERATION_INVALID ((u64)(-1))
378 static int siena_try_update_nic_stats(struct efx_nic *efx)
381 struct efx_mac_stats *mac_stats;
382 u64 generation_start;
385 mac_stats = &efx->mac_stats;
386 dma_stats = (u64 *)efx->stats_buffer.addr;
388 generation_end = dma_stats[MC_CMD_MAC_GENERATION_END];
389 if (generation_end == STATS_GENERATION_INVALID)
393 #define MAC_STAT(M, D) \
394 mac_stats->M = dma_stats[MC_CMD_MAC_ ## D]
396 MAC_STAT(tx_bytes, TX_BYTES);
397 MAC_STAT(tx_bad_bytes, TX_BAD_BYTES);
398 mac_stats->tx_good_bytes = (mac_stats->tx_bytes -
399 mac_stats->tx_bad_bytes);
400 MAC_STAT(tx_packets, TX_PKTS);
401 MAC_STAT(tx_bad, TX_BAD_FCS_PKTS);
402 MAC_STAT(tx_pause, TX_PAUSE_PKTS);
403 MAC_STAT(tx_control, TX_CONTROL_PKTS);
404 MAC_STAT(tx_unicast, TX_UNICAST_PKTS);
405 MAC_STAT(tx_multicast, TX_MULTICAST_PKTS);
406 MAC_STAT(tx_broadcast, TX_BROADCAST_PKTS);
407 MAC_STAT(tx_lt64, TX_LT64_PKTS);
408 MAC_STAT(tx_64, TX_64_PKTS);
409 MAC_STAT(tx_65_to_127, TX_65_TO_127_PKTS);
410 MAC_STAT(tx_128_to_255, TX_128_TO_255_PKTS);
411 MAC_STAT(tx_256_to_511, TX_256_TO_511_PKTS);
412 MAC_STAT(tx_512_to_1023, TX_512_TO_1023_PKTS);
413 MAC_STAT(tx_1024_to_15xx, TX_1024_TO_15XX_PKTS);
414 MAC_STAT(tx_15xx_to_jumbo, TX_15XX_TO_JUMBO_PKTS);
415 MAC_STAT(tx_gtjumbo, TX_GTJUMBO_PKTS);
416 mac_stats->tx_collision = 0;
417 MAC_STAT(tx_single_collision, TX_SINGLE_COLLISION_PKTS);
418 MAC_STAT(tx_multiple_collision, TX_MULTIPLE_COLLISION_PKTS);
419 MAC_STAT(tx_excessive_collision, TX_EXCESSIVE_COLLISION_PKTS);
420 MAC_STAT(tx_deferred, TX_DEFERRED_PKTS);
421 MAC_STAT(tx_late_collision, TX_LATE_COLLISION_PKTS);
422 mac_stats->tx_collision = (mac_stats->tx_single_collision +
423 mac_stats->tx_multiple_collision +
424 mac_stats->tx_excessive_collision +
425 mac_stats->tx_late_collision);
426 MAC_STAT(tx_excessive_deferred, TX_EXCESSIVE_DEFERRED_PKTS);
427 MAC_STAT(tx_non_tcpudp, TX_NON_TCPUDP_PKTS);
428 MAC_STAT(tx_mac_src_error, TX_MAC_SRC_ERR_PKTS);
429 MAC_STAT(tx_ip_src_error, TX_IP_SRC_ERR_PKTS);
430 MAC_STAT(rx_bytes, RX_BYTES);
431 MAC_STAT(rx_bad_bytes, RX_BAD_BYTES);
432 mac_stats->rx_good_bytes = (mac_stats->rx_bytes -
433 mac_stats->rx_bad_bytes);
434 MAC_STAT(rx_packets, RX_PKTS);
435 MAC_STAT(rx_good, RX_GOOD_PKTS);
436 mac_stats->rx_bad = mac_stats->rx_packets - mac_stats->rx_good;
437 MAC_STAT(rx_pause, RX_PAUSE_PKTS);
438 MAC_STAT(rx_control, RX_CONTROL_PKTS);
439 MAC_STAT(rx_unicast, RX_UNICAST_PKTS);
440 MAC_STAT(rx_multicast, RX_MULTICAST_PKTS);
441 MAC_STAT(rx_broadcast, RX_BROADCAST_PKTS);
442 MAC_STAT(rx_lt64, RX_UNDERSIZE_PKTS);
443 MAC_STAT(rx_64, RX_64_PKTS);
444 MAC_STAT(rx_65_to_127, RX_65_TO_127_PKTS);
445 MAC_STAT(rx_128_to_255, RX_128_TO_255_PKTS);
446 MAC_STAT(rx_256_to_511, RX_256_TO_511_PKTS);
447 MAC_STAT(rx_512_to_1023, RX_512_TO_1023_PKTS);
448 MAC_STAT(rx_1024_to_15xx, RX_1024_TO_15XX_PKTS);
449 MAC_STAT(rx_15xx_to_jumbo, RX_15XX_TO_JUMBO_PKTS);
450 MAC_STAT(rx_gtjumbo, RX_GTJUMBO_PKTS);
451 mac_stats->rx_bad_lt64 = 0;
452 mac_stats->rx_bad_64_to_15xx = 0;
453 mac_stats->rx_bad_15xx_to_jumbo = 0;
454 MAC_STAT(rx_bad_gtjumbo, RX_JABBER_PKTS);
455 MAC_STAT(rx_overflow, RX_OVERFLOW_PKTS);
456 mac_stats->rx_missed = 0;
457 MAC_STAT(rx_false_carrier, RX_FALSE_CARRIER_PKTS);
458 MAC_STAT(rx_symbol_error, RX_SYMBOL_ERROR_PKTS);
459 MAC_STAT(rx_align_error, RX_ALIGN_ERROR_PKTS);
460 MAC_STAT(rx_length_error, RX_LENGTH_ERROR_PKTS);
461 MAC_STAT(rx_internal_error, RX_INTERNAL_ERROR_PKTS);
462 mac_stats->rx_good_lt64 = 0;
464 efx->n_rx_nodesc_drop_cnt = dma_stats[MC_CMD_MAC_RX_NODESC_DROPS];
469 generation_start = dma_stats[MC_CMD_MAC_GENERATION_START];
470 if (generation_end != generation_start)
476 static void siena_update_nic_stats(struct efx_nic *efx)
480 /* If we're unlucky enough to read statistics wduring the DMA, wait
481 * up to 10ms for it to finish (typically takes <500us) */
482 for (retry = 0; retry < 100; ++retry) {
483 if (siena_try_update_nic_stats(efx) == 0)
488 /* Use the old values instead */
491 static void siena_start_nic_stats(struct efx_nic *efx)
493 u64 *dma_stats = (u64 *)efx->stats_buffer.addr;
495 dma_stats[MC_CMD_MAC_GENERATION_END] = STATS_GENERATION_INVALID;
497 efx_mcdi_mac_stats(efx, efx->stats_buffer.dma_addr,
498 MC_CMD_MAC_NSTATS * sizeof(u64), 1, 0);
501 static void siena_stop_nic_stats(struct efx_nic *efx)
503 efx_mcdi_mac_stats(efx, efx->stats_buffer.dma_addr, 0, 0, 0);
506 void siena_print_fwver(struct efx_nic *efx, char *buf, size_t len)
508 struct siena_nic_data *nic_data = efx->nic_data;
509 snprintf(buf, len, "%u.%u.%u.%u",
510 (unsigned int)(nic_data->fw_version >> 48),
511 (unsigned int)(nic_data->fw_version >> 32 & 0xffff),
512 (unsigned int)(nic_data->fw_version >> 16 & 0xffff),
513 (unsigned int)(nic_data->fw_version & 0xffff));
516 /**************************************************************************
520 **************************************************************************
523 static void siena_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol)
525 struct siena_nic_data *nic_data = efx->nic_data;
527 wol->supported = WAKE_MAGIC;
528 if (nic_data->wol_filter_id != -1)
529 wol->wolopts = WAKE_MAGIC;
532 memset(&wol->sopass, 0, sizeof(wol->sopass));
536 static int siena_set_wol(struct efx_nic *efx, u32 type)
538 struct siena_nic_data *nic_data = efx->nic_data;
541 if (type & ~WAKE_MAGIC)
544 if (type & WAKE_MAGIC) {
545 if (nic_data->wol_filter_id != -1)
546 efx_mcdi_wol_filter_remove(efx,
547 nic_data->wol_filter_id);
548 rc = efx_mcdi_wol_filter_set_magic(efx, efx->mac_address,
549 &nic_data->wol_filter_id);
553 pci_wake_from_d3(efx->pci_dev, true);
555 rc = efx_mcdi_wol_filter_reset(efx);
556 nic_data->wol_filter_id = -1;
557 pci_wake_from_d3(efx->pci_dev, false);
564 EFX_ERR(efx, "%s failed: type=%d rc=%d\n", __func__, type, rc);
569 static void siena_init_wol(struct efx_nic *efx)
571 struct siena_nic_data *nic_data = efx->nic_data;
574 rc = efx_mcdi_wol_filter_get_magic(efx, &nic_data->wol_filter_id);
577 /* If it failed, attempt to get into a synchronised
578 * state with MC by resetting any set WoL filters */
579 efx_mcdi_wol_filter_reset(efx);
580 nic_data->wol_filter_id = -1;
581 } else if (nic_data->wol_filter_id != -1) {
582 pci_wake_from_d3(efx->pci_dev, true);
587 /**************************************************************************
589 * Revision-dependent attributes used by efx.c and nic.c
591 **************************************************************************
594 struct efx_nic_type siena_a0_nic_type = {
595 .probe = siena_probe_nic,
596 .remove = siena_remove_nic,
597 .init = siena_init_nic,
598 .fini = efx_port_dummy_op_void,
600 .reset = siena_reset_hw,
601 .probe_port = siena_probe_port,
602 .remove_port = siena_remove_port,
603 .prepare_flush = efx_port_dummy_op_void,
604 .update_stats = siena_update_nic_stats,
605 .start_stats = siena_start_nic_stats,
606 .stop_stats = siena_stop_nic_stats,
607 .set_id_led = efx_mcdi_set_id_led,
608 .push_irq_moderation = siena_push_irq_moderation,
609 .push_multicast_hash = siena_push_multicast_hash,
610 .reconfigure_port = efx_mcdi_phy_reconfigure,
611 .get_wol = siena_get_wol,
612 .set_wol = siena_set_wol,
613 .resume_wol = siena_init_wol,
614 .test_registers = siena_test_registers,
615 .test_nvram = efx_mcdi_nvram_test_all,
616 .default_mac_ops = &efx_mcdi_mac_operations,
618 .revision = EFX_REV_SIENA_A0,
619 .mem_map_size = (FR_CZ_MC_TREG_SMEM +
620 FR_CZ_MC_TREG_SMEM_STEP * FR_CZ_MC_TREG_SMEM_ROWS),
621 .txd_ptr_tbl_base = FR_BZ_TX_DESC_PTR_TBL,
622 .rxd_ptr_tbl_base = FR_BZ_RX_DESC_PTR_TBL,
623 .buf_tbl_base = FR_BZ_BUF_FULL_TBL,
624 .evq_ptr_tbl_base = FR_BZ_EVQ_PTR_TBL,
625 .evq_rptr_tbl_base = FR_BZ_EVQ_RPTR,
626 .max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH),
627 .rx_buffer_padding = 0,
628 .max_interrupt_mode = EFX_INT_MODE_MSIX,
629 .phys_addr_channels = 32, /* Hardware limit is 64, but the legacy
630 * interrupt handler only supports 32
632 .tx_dc_base = 0x88000,
633 .rx_dc_base = 0x68000,
634 .offload_features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM,
635 .reset_world_flags = ETH_RESET_MGMT << ETH_RESET_SHARED_SHIFT,