2 * SuperH Ethernet device driver
4 * Copyright (C) 2006-2008 Nobuhiro Iwamatsu
5 * Copyright (C) 2008-2009 Renesas Solutions Corp.
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
16 * this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 * The full GNU General Public License is included in this distribution in
20 * the file called "COPYING".
23 #include <linux/init.h>
24 #include <linux/interrupt.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/etherdevice.h>
27 #include <linux/delay.h>
28 #include <linux/platform_device.h>
29 #include <linux/mdio-bitbang.h>
30 #include <linux/netdevice.h>
31 #include <linux/phy.h>
32 #include <linux/cache.h>
34 #include <linux/interrupt.h>
35 #include <linux/pm_runtime.h>
36 #include <linux/slab.h>
37 #include <linux/ethtool.h>
41 #define SH_ETH_DEF_MSG_ENABLE \
47 /* There is CPU dependent code */
48 #if defined(CONFIG_CPU_SUBTYPE_SH7724)
49 #define SH_ETH_RESET_DEFAULT 1
50 static void sh_eth_set_duplex(struct net_device *ndev)
52 struct sh_eth_private *mdp = netdev_priv(ndev);
54 if (mdp->duplex) /* Full */
55 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
57 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
60 static void sh_eth_set_rate(struct net_device *ndev)
62 struct sh_eth_private *mdp = netdev_priv(ndev);
66 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_RTM, ECMR);
68 case 100:/* 100BASE */
69 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_RTM, ECMR);
77 static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
78 .set_duplex = sh_eth_set_duplex,
79 .set_rate = sh_eth_set_rate,
81 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
82 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
83 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x01ff009f,
85 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
86 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE |
87 EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI,
88 .tx_error_check = EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE,
95 .rpadir_value = 0x00020000, /* NET_IP_ALIGN assumed to be 2 */
97 #elif defined(CONFIG_CPU_SUBTYPE_SH7757)
98 #define SH_ETH_HAS_BOTH_MODULES 1
99 #define SH_ETH_HAS_TSU 1
100 static void sh_eth_set_duplex(struct net_device *ndev)
102 struct sh_eth_private *mdp = netdev_priv(ndev);
104 if (mdp->duplex) /* Full */
105 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
107 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
110 static void sh_eth_set_rate(struct net_device *ndev)
112 struct sh_eth_private *mdp = netdev_priv(ndev);
114 switch (mdp->speed) {
115 case 10: /* 10BASE */
116 sh_eth_write(ndev, 0, RTRATE);
118 case 100:/* 100BASE */
119 sh_eth_write(ndev, 1, RTRATE);
127 static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
128 .set_duplex = sh_eth_set_duplex,
129 .set_rate = sh_eth_set_rate,
131 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
132 .rmcr_value = 0x00000001,
134 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
135 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE |
136 EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI,
137 .tx_error_check = EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE,
145 .rpadir_value = 2 << 16,
148 #define SH_GIGA_ETH_BASE 0xfee00000
149 #define GIGA_MALR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8)
150 #define GIGA_MAHR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0)
151 static void sh_eth_chip_reset_giga(struct net_device *ndev)
154 unsigned long mahr[2], malr[2];
156 /* save MAHR and MALR */
157 for (i = 0; i < 2; i++) {
158 malr[i] = readl(GIGA_MALR(i));
159 mahr[i] = readl(GIGA_MAHR(i));
163 writel(ARSTR_ARSTR, SH_GIGA_ETH_BASE + 0x1800);
166 /* restore MAHR and MALR */
167 for (i = 0; i < 2; i++) {
168 writel(malr[i], GIGA_MALR(i));
169 writel(mahr[i], GIGA_MAHR(i));
173 static int sh_eth_is_gether(struct sh_eth_private *mdp);
174 static void sh_eth_reset(struct net_device *ndev)
176 struct sh_eth_private *mdp = netdev_priv(ndev);
179 if (sh_eth_is_gether(mdp)) {
180 sh_eth_write(ndev, 0x03, EDSR);
181 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER,
184 if (!(sh_eth_read(ndev, EDMR) & 0x3))
190 printk(KERN_ERR "Device reset fail\n");
193 sh_eth_write(ndev, 0x0, TDLAR);
194 sh_eth_write(ndev, 0x0, TDFAR);
195 sh_eth_write(ndev, 0x0, TDFXR);
196 sh_eth_write(ndev, 0x0, TDFFR);
197 sh_eth_write(ndev, 0x0, RDLAR);
198 sh_eth_write(ndev, 0x0, RDFAR);
199 sh_eth_write(ndev, 0x0, RDFXR);
200 sh_eth_write(ndev, 0x0, RDFFR);
202 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_ETHER,
205 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) & ~EDMR_SRST_ETHER,
210 static void sh_eth_set_duplex_giga(struct net_device *ndev)
212 struct sh_eth_private *mdp = netdev_priv(ndev);
214 if (mdp->duplex) /* Full */
215 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
217 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
220 static void sh_eth_set_rate_giga(struct net_device *ndev)
222 struct sh_eth_private *mdp = netdev_priv(ndev);
224 switch (mdp->speed) {
225 case 10: /* 10BASE */
226 sh_eth_write(ndev, 0x00000000, GECMR);
228 case 100:/* 100BASE */
229 sh_eth_write(ndev, 0x00000010, GECMR);
231 case 1000: /* 1000BASE */
232 sh_eth_write(ndev, 0x00000020, GECMR);
239 /* SH7757(GETHERC) */
240 static struct sh_eth_cpu_data sh_eth_my_cpu_data_giga = {
241 .chip_reset = sh_eth_chip_reset_giga,
242 .set_duplex = sh_eth_set_duplex_giga,
243 .set_rate = sh_eth_set_rate_giga,
245 .ecsr_value = ECSR_ICD | ECSR_MPD,
246 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
247 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
249 .tx_check = EESR_TC1 | EESR_FTC,
250 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | \
251 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | \
253 .tx_error_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_TDE | \
255 .fdr_value = 0x0000072f,
256 .rmcr_value = 0x00000001,
264 .rpadir_value = 2 << 16,
269 static struct sh_eth_cpu_data *sh_eth_get_cpu_data(struct sh_eth_private *mdp)
271 if (sh_eth_is_gether(mdp))
272 return &sh_eth_my_cpu_data_giga;
274 return &sh_eth_my_cpu_data;
277 #elif defined(CONFIG_CPU_SUBTYPE_SH7763)
278 #define SH_ETH_HAS_TSU 1
279 static void sh_eth_chip_reset(struct net_device *ndev)
281 struct sh_eth_private *mdp = netdev_priv(ndev);
284 sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
288 static void sh_eth_reset(struct net_device *ndev)
292 sh_eth_write(ndev, EDSR_ENALL, EDSR);
293 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER, EDMR);
295 if (!(sh_eth_read(ndev, EDMR) & 0x3))
301 printk(KERN_ERR "Device reset fail\n");
304 sh_eth_write(ndev, 0x0, TDLAR);
305 sh_eth_write(ndev, 0x0, TDFAR);
306 sh_eth_write(ndev, 0x0, TDFXR);
307 sh_eth_write(ndev, 0x0, TDFFR);
308 sh_eth_write(ndev, 0x0, RDLAR);
309 sh_eth_write(ndev, 0x0, RDFAR);
310 sh_eth_write(ndev, 0x0, RDFXR);
311 sh_eth_write(ndev, 0x0, RDFFR);
314 static void sh_eth_set_duplex(struct net_device *ndev)
316 struct sh_eth_private *mdp = netdev_priv(ndev);
318 if (mdp->duplex) /* Full */
319 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
321 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
324 static void sh_eth_set_rate(struct net_device *ndev)
326 struct sh_eth_private *mdp = netdev_priv(ndev);
328 switch (mdp->speed) {
329 case 10: /* 10BASE */
330 sh_eth_write(ndev, GECMR_10, GECMR);
332 case 100:/* 100BASE */
333 sh_eth_write(ndev, GECMR_100, GECMR);
335 case 1000: /* 1000BASE */
336 sh_eth_write(ndev, GECMR_1000, GECMR);
344 static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
345 .chip_reset = sh_eth_chip_reset,
346 .set_duplex = sh_eth_set_duplex,
347 .set_rate = sh_eth_set_rate,
349 .ecsr_value = ECSR_ICD | ECSR_MPD,
350 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
351 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
353 .tx_check = EESR_TC1 | EESR_FTC,
354 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | \
355 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | \
357 .tx_error_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_TDE | \
370 #elif defined(CONFIG_CPU_SUBTYPE_SH7619)
371 #define SH_ETH_RESET_DEFAULT 1
372 static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
373 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
380 #elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
381 #define SH_ETH_RESET_DEFAULT 1
382 #define SH_ETH_HAS_TSU 1
383 static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
384 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
389 static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd)
392 cd->ecsr_value = DEFAULT_ECSR_INIT;
394 if (!cd->ecsipr_value)
395 cd->ecsipr_value = DEFAULT_ECSIPR_INIT;
397 if (!cd->fcftr_value)
398 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF | \
399 DEFAULT_FIFO_F_D_RFD;
402 cd->fdr_value = DEFAULT_FDR_INIT;
405 cd->rmcr_value = DEFAULT_RMCR_VALUE;
408 cd->tx_check = DEFAULT_TX_CHECK;
410 if (!cd->eesr_err_check)
411 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK;
413 if (!cd->tx_error_check)
414 cd->tx_error_check = DEFAULT_TX_ERROR_CHECK;
417 #if defined(SH_ETH_RESET_DEFAULT)
419 static void sh_eth_reset(struct net_device *ndev)
421 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_ETHER, EDMR);
423 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) & ~EDMR_SRST_ETHER, EDMR);
427 #if defined(CONFIG_CPU_SH4)
428 static void sh_eth_set_receive_align(struct sk_buff *skb)
432 reserve = SH4_SKB_RX_ALIGN - ((u32)skb->data & (SH4_SKB_RX_ALIGN - 1));
434 skb_reserve(skb, reserve);
437 static void sh_eth_set_receive_align(struct sk_buff *skb)
439 skb_reserve(skb, SH2_SH3_SKB_RX_ALIGN);
444 /* CPU <-> EDMAC endian convert */
445 static inline __u32 cpu_to_edmac(struct sh_eth_private *mdp, u32 x)
447 switch (mdp->edmac_endian) {
448 case EDMAC_LITTLE_ENDIAN:
449 return cpu_to_le32(x);
450 case EDMAC_BIG_ENDIAN:
451 return cpu_to_be32(x);
456 static inline __u32 edmac_to_cpu(struct sh_eth_private *mdp, u32 x)
458 switch (mdp->edmac_endian) {
459 case EDMAC_LITTLE_ENDIAN:
460 return le32_to_cpu(x);
461 case EDMAC_BIG_ENDIAN:
462 return be32_to_cpu(x);
468 * Program the hardware MAC address from dev->dev_addr.
470 static void update_mac_address(struct net_device *ndev)
473 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
474 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
476 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
480 * Get MAC address from SuperH MAC address register
482 * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
483 * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
484 * When you want use this device, you must set MAC address in bootloader.
487 static void read_mac_address(struct net_device *ndev, unsigned char *mac)
489 if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) {
490 memcpy(ndev->dev_addr, mac, 6);
492 ndev->dev_addr[0] = (sh_eth_read(ndev, MAHR) >> 24);
493 ndev->dev_addr[1] = (sh_eth_read(ndev, MAHR) >> 16) & 0xFF;
494 ndev->dev_addr[2] = (sh_eth_read(ndev, MAHR) >> 8) & 0xFF;
495 ndev->dev_addr[3] = (sh_eth_read(ndev, MAHR) & 0xFF);
496 ndev->dev_addr[4] = (sh_eth_read(ndev, MALR) >> 8) & 0xFF;
497 ndev->dev_addr[5] = (sh_eth_read(ndev, MALR) & 0xFF);
501 static int sh_eth_is_gether(struct sh_eth_private *mdp)
503 if (mdp->reg_offset == sh_eth_offset_gigabit)
509 static unsigned long sh_eth_get_edtrr_trns(struct sh_eth_private *mdp)
511 if (sh_eth_is_gether(mdp))
512 return EDTRR_TRNS_GETHER;
514 return EDTRR_TRNS_ETHER;
518 void (*set_gate)(unsigned long addr);
519 struct mdiobb_ctrl ctrl;
521 u32 mmd_msk;/* MMD */
528 static void bb_set(u32 addr, u32 msk)
530 writel(readl(addr) | msk, addr);
534 static void bb_clr(u32 addr, u32 msk)
536 writel((readl(addr) & ~msk), addr);
540 static int bb_read(u32 addr, u32 msk)
542 return (readl(addr) & msk) != 0;
545 /* Data I/O pin control */
546 static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit)
548 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
550 if (bitbang->set_gate)
551 bitbang->set_gate(bitbang->addr);
554 bb_set(bitbang->addr, bitbang->mmd_msk);
556 bb_clr(bitbang->addr, bitbang->mmd_msk);
560 static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit)
562 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
564 if (bitbang->set_gate)
565 bitbang->set_gate(bitbang->addr);
568 bb_set(bitbang->addr, bitbang->mdo_msk);
570 bb_clr(bitbang->addr, bitbang->mdo_msk);
574 static int sh_get_mdio(struct mdiobb_ctrl *ctrl)
576 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
578 if (bitbang->set_gate)
579 bitbang->set_gate(bitbang->addr);
581 return bb_read(bitbang->addr, bitbang->mdi_msk);
584 /* MDC pin control */
585 static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit)
587 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
589 if (bitbang->set_gate)
590 bitbang->set_gate(bitbang->addr);
593 bb_set(bitbang->addr, bitbang->mdc_msk);
595 bb_clr(bitbang->addr, bitbang->mdc_msk);
598 /* mdio bus control struct */
599 static struct mdiobb_ops bb_ops = {
600 .owner = THIS_MODULE,
601 .set_mdc = sh_mdc_ctrl,
602 .set_mdio_dir = sh_mmd_ctrl,
603 .set_mdio_data = sh_set_mdio,
604 .get_mdio_data = sh_get_mdio,
607 /* free skb and descriptor buffer */
608 static void sh_eth_ring_free(struct net_device *ndev)
610 struct sh_eth_private *mdp = netdev_priv(ndev);
613 /* Free Rx skb ringbuffer */
614 if (mdp->rx_skbuff) {
615 for (i = 0; i < RX_RING_SIZE; i++) {
616 if (mdp->rx_skbuff[i])
617 dev_kfree_skb(mdp->rx_skbuff[i]);
620 kfree(mdp->rx_skbuff);
622 /* Free Tx skb ringbuffer */
623 if (mdp->tx_skbuff) {
624 for (i = 0; i < TX_RING_SIZE; i++) {
625 if (mdp->tx_skbuff[i])
626 dev_kfree_skb(mdp->tx_skbuff[i]);
629 kfree(mdp->tx_skbuff);
632 /* format skb and descriptor buffer */
633 static void sh_eth_ring_format(struct net_device *ndev)
635 struct sh_eth_private *mdp = netdev_priv(ndev);
638 struct sh_eth_rxdesc *rxdesc = NULL;
639 struct sh_eth_txdesc *txdesc = NULL;
640 int rx_ringsize = sizeof(*rxdesc) * RX_RING_SIZE;
641 int tx_ringsize = sizeof(*txdesc) * TX_RING_SIZE;
643 mdp->cur_rx = mdp->cur_tx = 0;
644 mdp->dirty_rx = mdp->dirty_tx = 0;
646 memset(mdp->rx_ring, 0, rx_ringsize);
648 /* build Rx ring buffer */
649 for (i = 0; i < RX_RING_SIZE; i++) {
651 mdp->rx_skbuff[i] = NULL;
652 skb = dev_alloc_skb(mdp->rx_buf_sz);
653 mdp->rx_skbuff[i] = skb;
656 dma_map_single(&ndev->dev, skb->tail, mdp->rx_buf_sz,
658 skb->dev = ndev; /* Mark as being used by this device. */
659 sh_eth_set_receive_align(skb);
662 rxdesc = &mdp->rx_ring[i];
663 rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4));
664 rxdesc->status = cpu_to_edmac(mdp, RD_RACT | RD_RFP);
666 /* The size of the buffer is 16 byte boundary. */
667 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16);
668 /* Rx descriptor address set */
670 sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR);
671 if (sh_eth_is_gether(mdp))
672 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR);
676 mdp->dirty_rx = (u32) (i - RX_RING_SIZE);
678 /* Mark the last entry as wrapping the ring. */
679 rxdesc->status |= cpu_to_edmac(mdp, RD_RDEL);
681 memset(mdp->tx_ring, 0, tx_ringsize);
683 /* build Tx ring buffer */
684 for (i = 0; i < TX_RING_SIZE; i++) {
685 mdp->tx_skbuff[i] = NULL;
686 txdesc = &mdp->tx_ring[i];
687 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
688 txdesc->buffer_length = 0;
690 /* Tx descriptor address set */
691 sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR);
692 if (sh_eth_is_gether(mdp))
693 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR);
697 txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
700 /* Get skb and descriptor buffer */
701 static int sh_eth_ring_init(struct net_device *ndev)
703 struct sh_eth_private *mdp = netdev_priv(ndev);
704 int rx_ringsize, tx_ringsize, ret = 0;
707 * +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
708 * card needs room to do 8 byte alignment, +2 so we can reserve
709 * the first 2 bytes, and +16 gets room for the status word from the
712 mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ :
713 (((ndev->mtu + 26 + 7) & ~7) + 2 + 16));
715 mdp->rx_buf_sz += NET_IP_ALIGN;
717 /* Allocate RX and TX skb rings */
718 mdp->rx_skbuff = kmalloc(sizeof(*mdp->rx_skbuff) * RX_RING_SIZE,
720 if (!mdp->rx_skbuff) {
721 dev_err(&ndev->dev, "Cannot allocate Rx skb\n");
726 mdp->tx_skbuff = kmalloc(sizeof(*mdp->tx_skbuff) * TX_RING_SIZE,
728 if (!mdp->tx_skbuff) {
729 dev_err(&ndev->dev, "Cannot allocate Tx skb\n");
734 /* Allocate all Rx descriptors. */
735 rx_ringsize = sizeof(struct sh_eth_rxdesc) * RX_RING_SIZE;
736 mdp->rx_ring = dma_alloc_coherent(NULL, rx_ringsize, &mdp->rx_desc_dma,
740 dev_err(&ndev->dev, "Cannot allocate Rx Ring (size %d bytes)\n",
748 /* Allocate all Tx descriptors. */
749 tx_ringsize = sizeof(struct sh_eth_txdesc) * TX_RING_SIZE;
750 mdp->tx_ring = dma_alloc_coherent(NULL, tx_ringsize, &mdp->tx_desc_dma,
753 dev_err(&ndev->dev, "Cannot allocate Tx Ring (size %d bytes)\n",
761 /* free DMA buffer */
762 dma_free_coherent(NULL, rx_ringsize, mdp->rx_ring, mdp->rx_desc_dma);
765 /* Free Rx and Tx skb ring buffer */
766 sh_eth_ring_free(ndev);
771 static int sh_eth_dev_init(struct net_device *ndev)
774 struct sh_eth_private *mdp = netdev_priv(ndev);
775 u_int32_t rx_int_var, tx_int_var;
781 /* Descriptor format */
782 sh_eth_ring_format(ndev);
784 sh_eth_write(ndev, mdp->cd->rpadir_value, RPADIR);
786 /* all sh_eth int mask */
787 sh_eth_write(ndev, 0, EESIPR);
789 #if defined(__LITTLE_ENDIAN__)
790 if (mdp->cd->hw_swap)
791 sh_eth_write(ndev, EDMR_EL, EDMR);
794 sh_eth_write(ndev, 0, EDMR);
797 sh_eth_write(ndev, mdp->cd->fdr_value, FDR);
798 sh_eth_write(ndev, 0, TFTR);
800 /* Frame recv control */
801 sh_eth_write(ndev, mdp->cd->rmcr_value, RMCR);
803 rx_int_var = mdp->rx_int_var = DESC_I_RINT8 | DESC_I_RINT5;
804 tx_int_var = mdp->tx_int_var = DESC_I_TINT2;
805 sh_eth_write(ndev, rx_int_var | tx_int_var, TRSCER);
808 sh_eth_write(ndev, 0x800, BCULR); /* Burst sycle set */
810 sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR);
812 if (!mdp->cd->no_trimd)
813 sh_eth_write(ndev, 0, TRIMD);
815 /* Recv frame limit set register */
816 sh_eth_write(ndev, RFLR_VALUE, RFLR);
818 sh_eth_write(ndev, sh_eth_read(ndev, EESR), EESR);
819 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
821 /* PAUSE Prohibition */
822 val = (sh_eth_read(ndev, ECMR) & ECMR_DM) |
823 ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) | ECMR_TE | ECMR_RE;
825 sh_eth_write(ndev, val, ECMR);
827 if (mdp->cd->set_rate)
828 mdp->cd->set_rate(ndev);
830 /* E-MAC Status Register clear */
831 sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR);
833 /* E-MAC Interrupt Enable register */
834 sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR);
836 /* Set MAC address */
837 update_mac_address(ndev);
841 sh_eth_write(ndev, APR_AP, APR);
843 sh_eth_write(ndev, MPR_MP, MPR);
844 if (mdp->cd->tpauser)
845 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER);
847 /* Setting the Rx mode will start the Rx process. */
848 sh_eth_write(ndev, EDRRR_R, EDRRR);
850 netif_start_queue(ndev);
855 /* free Tx skb function */
856 static int sh_eth_txfree(struct net_device *ndev)
858 struct sh_eth_private *mdp = netdev_priv(ndev);
859 struct sh_eth_txdesc *txdesc;
863 for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) {
864 entry = mdp->dirty_tx % TX_RING_SIZE;
865 txdesc = &mdp->tx_ring[entry];
866 if (txdesc->status & cpu_to_edmac(mdp, TD_TACT))
868 /* Free the original skb. */
869 if (mdp->tx_skbuff[entry]) {
870 dma_unmap_single(&ndev->dev, txdesc->addr,
871 txdesc->buffer_length, DMA_TO_DEVICE);
872 dev_kfree_skb_irq(mdp->tx_skbuff[entry]);
873 mdp->tx_skbuff[entry] = NULL;
876 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
877 if (entry >= TX_RING_SIZE - 1)
878 txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
880 mdp->stats.tx_packets++;
881 mdp->stats.tx_bytes += txdesc->buffer_length;
886 /* Packet receive function */
887 static int sh_eth_rx(struct net_device *ndev)
889 struct sh_eth_private *mdp = netdev_priv(ndev);
890 struct sh_eth_rxdesc *rxdesc;
892 int entry = mdp->cur_rx % RX_RING_SIZE;
893 int boguscnt = (mdp->dirty_rx + RX_RING_SIZE) - mdp->cur_rx;
898 rxdesc = &mdp->rx_ring[entry];
899 while (!(rxdesc->status & cpu_to_edmac(mdp, RD_RACT))) {
900 desc_status = edmac_to_cpu(mdp, rxdesc->status);
901 pkt_len = rxdesc->frame_length;
906 if (!(desc_status & RDFEND))
907 mdp->stats.rx_length_errors++;
909 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 |
910 RD_RFS5 | RD_RFS6 | RD_RFS10)) {
911 mdp->stats.rx_errors++;
912 if (desc_status & RD_RFS1)
913 mdp->stats.rx_crc_errors++;
914 if (desc_status & RD_RFS2)
915 mdp->stats.rx_frame_errors++;
916 if (desc_status & RD_RFS3)
917 mdp->stats.rx_length_errors++;
918 if (desc_status & RD_RFS4)
919 mdp->stats.rx_length_errors++;
920 if (desc_status & RD_RFS6)
921 mdp->stats.rx_missed_errors++;
922 if (desc_status & RD_RFS10)
923 mdp->stats.rx_over_errors++;
925 if (!mdp->cd->hw_swap)
927 phys_to_virt(ALIGN(rxdesc->addr, 4)),
929 skb = mdp->rx_skbuff[entry];
930 mdp->rx_skbuff[entry] = NULL;
932 skb_reserve(skb, NET_IP_ALIGN);
933 skb_put(skb, pkt_len);
934 skb->protocol = eth_type_trans(skb, ndev);
936 mdp->stats.rx_packets++;
937 mdp->stats.rx_bytes += pkt_len;
939 rxdesc->status |= cpu_to_edmac(mdp, RD_RACT);
940 entry = (++mdp->cur_rx) % RX_RING_SIZE;
941 rxdesc = &mdp->rx_ring[entry];
944 /* Refill the Rx ring buffers. */
945 for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) {
946 entry = mdp->dirty_rx % RX_RING_SIZE;
947 rxdesc = &mdp->rx_ring[entry];
948 /* The size of the buffer is 16 byte boundary. */
949 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16);
951 if (mdp->rx_skbuff[entry] == NULL) {
952 skb = dev_alloc_skb(mdp->rx_buf_sz);
953 mdp->rx_skbuff[entry] = skb;
955 break; /* Better luck next round. */
956 dma_map_single(&ndev->dev, skb->tail, mdp->rx_buf_sz,
959 sh_eth_set_receive_align(skb);
961 skb_checksum_none_assert(skb);
962 rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4));
964 if (entry >= RX_RING_SIZE - 1)
966 cpu_to_edmac(mdp, RD_RACT | RD_RFP | RD_RDEL);
969 cpu_to_edmac(mdp, RD_RACT | RD_RFP);
972 /* Restart Rx engine if stopped. */
973 /* If we don't need to check status, don't. -KDU */
974 if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R))
975 sh_eth_write(ndev, EDRRR_R, EDRRR);
980 static void sh_eth_rcv_snd_disable(struct net_device *ndev)
982 /* disable tx and rx */
983 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) &
984 ~(ECMR_RE | ECMR_TE), ECMR);
987 static void sh_eth_rcv_snd_enable(struct net_device *ndev)
989 /* enable tx and rx */
990 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) |
991 (ECMR_RE | ECMR_TE), ECMR);
994 /* error control function */
995 static void sh_eth_error(struct net_device *ndev, int intr_status)
997 struct sh_eth_private *mdp = netdev_priv(ndev);
1002 if (intr_status & EESR_ECI) {
1003 felic_stat = sh_eth_read(ndev, ECSR);
1004 sh_eth_write(ndev, felic_stat, ECSR); /* clear int */
1005 if (felic_stat & ECSR_ICD)
1006 mdp->stats.tx_carrier_errors++;
1007 if (felic_stat & ECSR_LCHNG) {
1009 if (mdp->cd->no_psr || mdp->no_ether_link) {
1010 if (mdp->link == PHY_DOWN)
1013 link_stat = PHY_ST_LINK;
1015 link_stat = (sh_eth_read(ndev, PSR));
1016 if (mdp->ether_link_active_low)
1017 link_stat = ~link_stat;
1019 if (!(link_stat & PHY_ST_LINK))
1020 sh_eth_rcv_snd_disable(ndev);
1023 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) &
1024 ~DMAC_M_ECI, EESIPR);
1026 sh_eth_write(ndev, sh_eth_read(ndev, ECSR),
1028 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) |
1029 DMAC_M_ECI, EESIPR);
1030 /* enable tx and rx */
1031 sh_eth_rcv_snd_enable(ndev);
1036 if (intr_status & EESR_TWB) {
1037 /* Write buck end. unused write back interrupt */
1038 if (intr_status & EESR_TABT) /* Transmit Abort int */
1039 mdp->stats.tx_aborted_errors++;
1040 if (netif_msg_tx_err(mdp))
1041 dev_err(&ndev->dev, "Transmit Abort\n");
1044 if (intr_status & EESR_RABT) {
1045 /* Receive Abort int */
1046 if (intr_status & EESR_RFRMER) {
1047 /* Receive Frame Overflow int */
1048 mdp->stats.rx_frame_errors++;
1049 if (netif_msg_rx_err(mdp))
1050 dev_err(&ndev->dev, "Receive Abort\n");
1054 if (intr_status & EESR_TDE) {
1055 /* Transmit Descriptor Empty int */
1056 mdp->stats.tx_fifo_errors++;
1057 if (netif_msg_tx_err(mdp))
1058 dev_err(&ndev->dev, "Transmit Descriptor Empty\n");
1061 if (intr_status & EESR_TFE) {
1062 /* FIFO under flow */
1063 mdp->stats.tx_fifo_errors++;
1064 if (netif_msg_tx_err(mdp))
1065 dev_err(&ndev->dev, "Transmit FIFO Under flow\n");
1068 if (intr_status & EESR_RDE) {
1069 /* Receive Descriptor Empty int */
1070 mdp->stats.rx_over_errors++;
1072 if (sh_eth_read(ndev, EDRRR) ^ EDRRR_R)
1073 sh_eth_write(ndev, EDRRR_R, EDRRR);
1074 if (netif_msg_rx_err(mdp))
1075 dev_err(&ndev->dev, "Receive Descriptor Empty\n");
1078 if (intr_status & EESR_RFE) {
1079 /* Receive FIFO Overflow int */
1080 mdp->stats.rx_fifo_errors++;
1081 if (netif_msg_rx_err(mdp))
1082 dev_err(&ndev->dev, "Receive FIFO Overflow\n");
1085 if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) {
1087 mdp->stats.tx_fifo_errors++;
1088 if (netif_msg_tx_err(mdp))
1089 dev_err(&ndev->dev, "Address Error\n");
1092 mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE;
1093 if (mdp->cd->no_ade)
1095 if (intr_status & mask) {
1097 u32 edtrr = sh_eth_read(ndev, EDTRR);
1099 dev_err(&ndev->dev, "TX error. status=%8.8x cur_tx=%8.8x ",
1100 intr_status, mdp->cur_tx);
1101 dev_err(&ndev->dev, "dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
1102 mdp->dirty_tx, (u32) ndev->state, edtrr);
1103 /* dirty buffer free */
1104 sh_eth_txfree(ndev);
1107 if (edtrr ^ sh_eth_get_edtrr_trns(mdp)) {
1109 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
1112 netif_wake_queue(ndev);
1116 static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
1118 struct net_device *ndev = netdev;
1119 struct sh_eth_private *mdp = netdev_priv(ndev);
1120 struct sh_eth_cpu_data *cd = mdp->cd;
1121 irqreturn_t ret = IRQ_NONE;
1122 u32 intr_status = 0;
1124 spin_lock(&mdp->lock);
1126 /* Get interrpt stat */
1127 intr_status = sh_eth_read(ndev, EESR);
1128 /* Clear interrupt */
1129 if (intr_status & (EESR_FRC | EESR_RMAF | EESR_RRF |
1130 EESR_RTLF | EESR_RTSF | EESR_PRE | EESR_CERF |
1131 cd->tx_check | cd->eesr_err_check)) {
1132 sh_eth_write(ndev, intr_status, EESR);
1137 if (intr_status & (EESR_FRC | /* Frame recv*/
1138 EESR_RMAF | /* Multi cast address recv*/
1139 EESR_RRF | /* Bit frame recv */
1140 EESR_RTLF | /* Long frame recv*/
1141 EESR_RTSF | /* short frame recv */
1142 EESR_PRE | /* PHY-LSI recv error */
1143 EESR_CERF)){ /* recv frame CRC error */
1148 if (intr_status & cd->tx_check) {
1149 sh_eth_txfree(ndev);
1150 netif_wake_queue(ndev);
1153 if (intr_status & cd->eesr_err_check)
1154 sh_eth_error(ndev, intr_status);
1157 spin_unlock(&mdp->lock);
1162 static void sh_eth_timer(unsigned long data)
1164 struct net_device *ndev = (struct net_device *)data;
1165 struct sh_eth_private *mdp = netdev_priv(ndev);
1167 mod_timer(&mdp->timer, jiffies + (10 * HZ));
1170 /* PHY state control function */
1171 static void sh_eth_adjust_link(struct net_device *ndev)
1173 struct sh_eth_private *mdp = netdev_priv(ndev);
1174 struct phy_device *phydev = mdp->phydev;
1177 if (phydev->link != PHY_DOWN) {
1178 if (phydev->duplex != mdp->duplex) {
1180 mdp->duplex = phydev->duplex;
1181 if (mdp->cd->set_duplex)
1182 mdp->cd->set_duplex(ndev);
1185 if (phydev->speed != mdp->speed) {
1187 mdp->speed = phydev->speed;
1188 if (mdp->cd->set_rate)
1189 mdp->cd->set_rate(ndev);
1191 if (mdp->link == PHY_DOWN) {
1193 (sh_eth_read(ndev, ECMR) & ~ECMR_TXF), ECMR);
1195 mdp->link = phydev->link;
1197 } else if (mdp->link) {
1199 mdp->link = PHY_DOWN;
1204 if (new_state && netif_msg_link(mdp))
1205 phy_print_status(phydev);
1208 /* PHY init function */
1209 static int sh_eth_phy_init(struct net_device *ndev)
1211 struct sh_eth_private *mdp = netdev_priv(ndev);
1212 char phy_id[MII_BUS_ID_SIZE + 3];
1213 struct phy_device *phydev = NULL;
1215 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
1216 mdp->mii_bus->id , mdp->phy_id);
1218 mdp->link = PHY_DOWN;
1222 /* Try connect to PHY */
1223 phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link,
1224 0, mdp->phy_interface);
1225 if (IS_ERR(phydev)) {
1226 dev_err(&ndev->dev, "phy_connect failed\n");
1227 return PTR_ERR(phydev);
1230 dev_info(&ndev->dev, "attached phy %i to driver %s\n",
1231 phydev->addr, phydev->drv->name);
1233 mdp->phydev = phydev;
1238 /* PHY control start function */
1239 static int sh_eth_phy_start(struct net_device *ndev)
1241 struct sh_eth_private *mdp = netdev_priv(ndev);
1244 ret = sh_eth_phy_init(ndev);
1248 /* reset phy - this also wakes it from PDOWN */
1249 phy_write(mdp->phydev, MII_BMCR, BMCR_RESET);
1250 phy_start(mdp->phydev);
1255 static int sh_eth_get_settings(struct net_device *ndev,
1256 struct ethtool_cmd *ecmd)
1258 struct sh_eth_private *mdp = netdev_priv(ndev);
1259 unsigned long flags;
1262 spin_lock_irqsave(&mdp->lock, flags);
1263 ret = phy_ethtool_gset(mdp->phydev, ecmd);
1264 spin_unlock_irqrestore(&mdp->lock, flags);
1269 static int sh_eth_set_settings(struct net_device *ndev,
1270 struct ethtool_cmd *ecmd)
1272 struct sh_eth_private *mdp = netdev_priv(ndev);
1273 unsigned long flags;
1276 spin_lock_irqsave(&mdp->lock, flags);
1278 /* disable tx and rx */
1279 sh_eth_rcv_snd_disable(ndev);
1281 ret = phy_ethtool_sset(mdp->phydev, ecmd);
1285 if (ecmd->duplex == DUPLEX_FULL)
1290 if (mdp->cd->set_duplex)
1291 mdp->cd->set_duplex(ndev);
1296 /* enable tx and rx */
1297 sh_eth_rcv_snd_enable(ndev);
1299 spin_unlock_irqrestore(&mdp->lock, flags);
1304 static int sh_eth_nway_reset(struct net_device *ndev)
1306 struct sh_eth_private *mdp = netdev_priv(ndev);
1307 unsigned long flags;
1310 spin_lock_irqsave(&mdp->lock, flags);
1311 ret = phy_start_aneg(mdp->phydev);
1312 spin_unlock_irqrestore(&mdp->lock, flags);
1317 static u32 sh_eth_get_msglevel(struct net_device *ndev)
1319 struct sh_eth_private *mdp = netdev_priv(ndev);
1320 return mdp->msg_enable;
1323 static void sh_eth_set_msglevel(struct net_device *ndev, u32 value)
1325 struct sh_eth_private *mdp = netdev_priv(ndev);
1326 mdp->msg_enable = value;
1329 static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = {
1330 "rx_current", "tx_current",
1331 "rx_dirty", "tx_dirty",
1333 #define SH_ETH_STATS_LEN ARRAY_SIZE(sh_eth_gstrings_stats)
1335 static int sh_eth_get_sset_count(struct net_device *netdev, int sset)
1339 return SH_ETH_STATS_LEN;
1345 static void sh_eth_get_ethtool_stats(struct net_device *ndev,
1346 struct ethtool_stats *stats, u64 *data)
1348 struct sh_eth_private *mdp = netdev_priv(ndev);
1351 /* device-specific stats */
1352 data[i++] = mdp->cur_rx;
1353 data[i++] = mdp->cur_tx;
1354 data[i++] = mdp->dirty_rx;
1355 data[i++] = mdp->dirty_tx;
1358 static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1360 switch (stringset) {
1362 memcpy(data, *sh_eth_gstrings_stats,
1363 sizeof(sh_eth_gstrings_stats));
1368 static struct ethtool_ops sh_eth_ethtool_ops = {
1369 .get_settings = sh_eth_get_settings,
1370 .set_settings = sh_eth_set_settings,
1371 .nway_reset = sh_eth_nway_reset,
1372 .get_msglevel = sh_eth_get_msglevel,
1373 .set_msglevel = sh_eth_set_msglevel,
1374 .get_link = ethtool_op_get_link,
1375 .get_strings = sh_eth_get_strings,
1376 .get_ethtool_stats = sh_eth_get_ethtool_stats,
1377 .get_sset_count = sh_eth_get_sset_count,
1380 /* network device open function */
1381 static int sh_eth_open(struct net_device *ndev)
1384 struct sh_eth_private *mdp = netdev_priv(ndev);
1386 pm_runtime_get_sync(&mdp->pdev->dev);
1388 ret = request_irq(ndev->irq, sh_eth_interrupt,
1389 #if defined(CONFIG_CPU_SUBTYPE_SH7763) || \
1390 defined(CONFIG_CPU_SUBTYPE_SH7764) || \
1391 defined(CONFIG_CPU_SUBTYPE_SH7757)
1398 dev_err(&ndev->dev, "Can not assign IRQ number\n");
1402 /* Descriptor set */
1403 ret = sh_eth_ring_init(ndev);
1408 ret = sh_eth_dev_init(ndev);
1412 /* PHY control start*/
1413 ret = sh_eth_phy_start(ndev);
1417 /* Set the timer to check for link beat. */
1418 init_timer(&mdp->timer);
1419 mdp->timer.expires = (jiffies + (24 * HZ)) / 10;/* 2.4 sec. */
1420 setup_timer(&mdp->timer, sh_eth_timer, (unsigned long)ndev);
1425 free_irq(ndev->irq, ndev);
1426 pm_runtime_put_sync(&mdp->pdev->dev);
1430 /* Timeout function */
1431 static void sh_eth_tx_timeout(struct net_device *ndev)
1433 struct sh_eth_private *mdp = netdev_priv(ndev);
1434 struct sh_eth_rxdesc *rxdesc;
1437 netif_stop_queue(ndev);
1439 if (netif_msg_timer(mdp))
1440 dev_err(&ndev->dev, "%s: transmit timed out, status %8.8x,"
1441 " resetting...\n", ndev->name, (int)sh_eth_read(ndev, EESR));
1443 /* tx_errors count up */
1444 mdp->stats.tx_errors++;
1447 del_timer_sync(&mdp->timer);
1449 /* Free all the skbuffs in the Rx queue. */
1450 for (i = 0; i < RX_RING_SIZE; i++) {
1451 rxdesc = &mdp->rx_ring[i];
1453 rxdesc->addr = 0xBADF00D0;
1454 if (mdp->rx_skbuff[i])
1455 dev_kfree_skb(mdp->rx_skbuff[i]);
1456 mdp->rx_skbuff[i] = NULL;
1458 for (i = 0; i < TX_RING_SIZE; i++) {
1459 if (mdp->tx_skbuff[i])
1460 dev_kfree_skb(mdp->tx_skbuff[i]);
1461 mdp->tx_skbuff[i] = NULL;
1465 sh_eth_dev_init(ndev);
1468 mdp->timer.expires = (jiffies + (24 * HZ)) / 10;/* 2.4 sec. */
1469 add_timer(&mdp->timer);
1472 /* Packet transmit function */
1473 static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
1475 struct sh_eth_private *mdp = netdev_priv(ndev);
1476 struct sh_eth_txdesc *txdesc;
1478 unsigned long flags;
1480 spin_lock_irqsave(&mdp->lock, flags);
1481 if ((mdp->cur_tx - mdp->dirty_tx) >= (TX_RING_SIZE - 4)) {
1482 if (!sh_eth_txfree(ndev)) {
1483 if (netif_msg_tx_queued(mdp))
1484 dev_warn(&ndev->dev, "TxFD exhausted.\n");
1485 netif_stop_queue(ndev);
1486 spin_unlock_irqrestore(&mdp->lock, flags);
1487 return NETDEV_TX_BUSY;
1490 spin_unlock_irqrestore(&mdp->lock, flags);
1492 entry = mdp->cur_tx % TX_RING_SIZE;
1493 mdp->tx_skbuff[entry] = skb;
1494 txdesc = &mdp->tx_ring[entry];
1496 if (!mdp->cd->hw_swap)
1497 sh_eth_soft_swap(phys_to_virt(ALIGN(txdesc->addr, 4)),
1499 txdesc->addr = dma_map_single(&ndev->dev, skb->data, skb->len,
1501 if (skb->len < ETHERSMALL)
1502 txdesc->buffer_length = ETHERSMALL;
1504 txdesc->buffer_length = skb->len;
1506 if (entry >= TX_RING_SIZE - 1)
1507 txdesc->status |= cpu_to_edmac(mdp, TD_TACT | TD_TDLE);
1509 txdesc->status |= cpu_to_edmac(mdp, TD_TACT);
1513 if (!(sh_eth_read(ndev, EDTRR) & sh_eth_get_edtrr_trns(mdp)))
1514 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
1516 return NETDEV_TX_OK;
1519 /* device close function */
1520 static int sh_eth_close(struct net_device *ndev)
1522 struct sh_eth_private *mdp = netdev_priv(ndev);
1525 netif_stop_queue(ndev);
1527 /* Disable interrupts by clearing the interrupt mask. */
1528 sh_eth_write(ndev, 0x0000, EESIPR);
1530 /* Stop the chip's Tx and Rx processes. */
1531 sh_eth_write(ndev, 0, EDTRR);
1532 sh_eth_write(ndev, 0, EDRRR);
1534 /* PHY Disconnect */
1536 phy_stop(mdp->phydev);
1537 phy_disconnect(mdp->phydev);
1540 free_irq(ndev->irq, ndev);
1542 del_timer_sync(&mdp->timer);
1544 /* Free all the skbuffs in the Rx queue. */
1545 sh_eth_ring_free(ndev);
1547 /* free DMA buffer */
1548 ringsize = sizeof(struct sh_eth_rxdesc) * RX_RING_SIZE;
1549 dma_free_coherent(NULL, ringsize, mdp->rx_ring, mdp->rx_desc_dma);
1551 /* free DMA buffer */
1552 ringsize = sizeof(struct sh_eth_txdesc) * TX_RING_SIZE;
1553 dma_free_coherent(NULL, ringsize, mdp->tx_ring, mdp->tx_desc_dma);
1555 pm_runtime_put_sync(&mdp->pdev->dev);
1560 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev)
1562 struct sh_eth_private *mdp = netdev_priv(ndev);
1564 pm_runtime_get_sync(&mdp->pdev->dev);
1566 mdp->stats.tx_dropped += sh_eth_read(ndev, TROCR);
1567 sh_eth_write(ndev, 0, TROCR); /* (write clear) */
1568 mdp->stats.collisions += sh_eth_read(ndev, CDCR);
1569 sh_eth_write(ndev, 0, CDCR); /* (write clear) */
1570 mdp->stats.tx_carrier_errors += sh_eth_read(ndev, LCCR);
1571 sh_eth_write(ndev, 0, LCCR); /* (write clear) */
1572 if (sh_eth_is_gether(mdp)) {
1573 mdp->stats.tx_carrier_errors += sh_eth_read(ndev, CERCR);
1574 sh_eth_write(ndev, 0, CERCR); /* (write clear) */
1575 mdp->stats.tx_carrier_errors += sh_eth_read(ndev, CEECR);
1576 sh_eth_write(ndev, 0, CEECR); /* (write clear) */
1578 mdp->stats.tx_carrier_errors += sh_eth_read(ndev, CNDCR);
1579 sh_eth_write(ndev, 0, CNDCR); /* (write clear) */
1581 pm_runtime_put_sync(&mdp->pdev->dev);
1586 /* ioctl to device funciotn*/
1587 static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq,
1590 struct sh_eth_private *mdp = netdev_priv(ndev);
1591 struct phy_device *phydev = mdp->phydev;
1593 if (!netif_running(ndev))
1599 return phy_mii_ioctl(phydev, rq, cmd);
1602 #if defined(SH_ETH_HAS_TSU)
1603 /* Multicast reception directions set */
1604 static void sh_eth_set_multicast_list(struct net_device *ndev)
1606 if (ndev->flags & IFF_PROMISC) {
1607 /* Set promiscuous. */
1608 sh_eth_write(ndev, (sh_eth_read(ndev, ECMR) & ~ECMR_MCT) |
1611 /* Normal, unicast/broadcast-only mode. */
1612 sh_eth_write(ndev, (sh_eth_read(ndev, ECMR) & ~ECMR_PRM) |
1616 #endif /* SH_ETH_HAS_TSU */
1618 /* SuperH's TSU register init function */
1619 static void sh_eth_tsu_init(struct sh_eth_private *mdp)
1621 sh_eth_tsu_write(mdp, 0, TSU_FWEN0); /* Disable forward(0->1) */
1622 sh_eth_tsu_write(mdp, 0, TSU_FWEN1); /* Disable forward(1->0) */
1623 sh_eth_tsu_write(mdp, 0, TSU_FCM); /* forward fifo 3k-3k */
1624 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0);
1625 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1);
1626 sh_eth_tsu_write(mdp, 0, TSU_PRISL0);
1627 sh_eth_tsu_write(mdp, 0, TSU_PRISL1);
1628 sh_eth_tsu_write(mdp, 0, TSU_FWSL0);
1629 sh_eth_tsu_write(mdp, 0, TSU_FWSL1);
1630 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC);
1631 if (sh_eth_is_gether(mdp)) {
1632 sh_eth_tsu_write(mdp, 0, TSU_QTAG0); /* Disable QTAG(0->1) */
1633 sh_eth_tsu_write(mdp, 0, TSU_QTAG1); /* Disable QTAG(1->0) */
1635 sh_eth_tsu_write(mdp, 0, TSU_QTAGM0); /* Disable QTAG(0->1) */
1636 sh_eth_tsu_write(mdp, 0, TSU_QTAGM1); /* Disable QTAG(1->0) */
1638 sh_eth_tsu_write(mdp, 0, TSU_FWSR); /* all interrupt status clear */
1639 sh_eth_tsu_write(mdp, 0, TSU_FWINMK); /* Disable all interrupt */
1640 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
1641 sh_eth_tsu_write(mdp, 0, TSU_POST1); /* Disable CAM entry [ 0- 7] */
1642 sh_eth_tsu_write(mdp, 0, TSU_POST2); /* Disable CAM entry [ 8-15] */
1643 sh_eth_tsu_write(mdp, 0, TSU_POST3); /* Disable CAM entry [16-23] */
1644 sh_eth_tsu_write(mdp, 0, TSU_POST4); /* Disable CAM entry [24-31] */
1647 /* MDIO bus release function */
1648 static int sh_mdio_release(struct net_device *ndev)
1650 struct mii_bus *bus = dev_get_drvdata(&ndev->dev);
1652 /* unregister mdio bus */
1653 mdiobus_unregister(bus);
1655 /* remove mdio bus info from net_device */
1656 dev_set_drvdata(&ndev->dev, NULL);
1658 /* free interrupts memory */
1661 /* free bitbang info */
1662 free_mdio_bitbang(bus);
1667 /* MDIO bus init function */
1668 static int sh_mdio_init(struct net_device *ndev, int id,
1669 struct sh_eth_plat_data *pd)
1672 struct bb_info *bitbang;
1673 struct sh_eth_private *mdp = netdev_priv(ndev);
1675 /* create bit control struct for PHY */
1676 bitbang = kzalloc(sizeof(struct bb_info), GFP_KERNEL);
1683 bitbang->addr = ndev->base_addr + mdp->reg_offset[PIR];
1684 bitbang->set_gate = pd->set_mdio_gate;
1685 bitbang->mdi_msk = 0x08;
1686 bitbang->mdo_msk = 0x04;
1687 bitbang->mmd_msk = 0x02;/* MMD */
1688 bitbang->mdc_msk = 0x01;
1689 bitbang->ctrl.ops = &bb_ops;
1691 /* MII controller setting */
1692 mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl);
1693 if (!mdp->mii_bus) {
1695 goto out_free_bitbang;
1698 /* Hook up MII support for ethtool */
1699 mdp->mii_bus->name = "sh_mii";
1700 mdp->mii_bus->parent = &ndev->dev;
1701 snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%x", id);
1704 mdp->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
1705 if (!mdp->mii_bus->irq) {
1710 for (i = 0; i < PHY_MAX_ADDR; i++)
1711 mdp->mii_bus->irq[i] = PHY_POLL;
1713 /* regist mdio bus */
1714 ret = mdiobus_register(mdp->mii_bus);
1718 dev_set_drvdata(&ndev->dev, mdp->mii_bus);
1723 kfree(mdp->mii_bus->irq);
1726 free_mdio_bitbang(mdp->mii_bus);
1735 static const u16 *sh_eth_get_register_offset(int register_type)
1737 const u16 *reg_offset = NULL;
1739 switch (register_type) {
1740 case SH_ETH_REG_GIGABIT:
1741 reg_offset = sh_eth_offset_gigabit;
1743 case SH_ETH_REG_FAST_SH4:
1744 reg_offset = sh_eth_offset_fast_sh4;
1746 case SH_ETH_REG_FAST_SH3_SH2:
1747 reg_offset = sh_eth_offset_fast_sh3_sh2;
1750 printk(KERN_ERR "Unknown register type (%d)\n", register_type);
1757 static const struct net_device_ops sh_eth_netdev_ops = {
1758 .ndo_open = sh_eth_open,
1759 .ndo_stop = sh_eth_close,
1760 .ndo_start_xmit = sh_eth_start_xmit,
1761 .ndo_get_stats = sh_eth_get_stats,
1762 #if defined(SH_ETH_HAS_TSU)
1763 .ndo_set_multicast_list = sh_eth_set_multicast_list,
1765 .ndo_tx_timeout = sh_eth_tx_timeout,
1766 .ndo_do_ioctl = sh_eth_do_ioctl,
1767 .ndo_validate_addr = eth_validate_addr,
1768 .ndo_set_mac_address = eth_mac_addr,
1769 .ndo_change_mtu = eth_change_mtu,
1772 static int sh_eth_drv_probe(struct platform_device *pdev)
1775 struct resource *res;
1776 struct net_device *ndev = NULL;
1777 struct sh_eth_private *mdp = NULL;
1778 struct sh_eth_plat_data *pd;
1781 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1782 if (unlikely(res == NULL)) {
1783 dev_err(&pdev->dev, "invalid resource\n");
1788 ndev = alloc_etherdev(sizeof(struct sh_eth_private));
1790 dev_err(&pdev->dev, "Could not allocate device.\n");
1795 /* The sh Ether-specific entries in the device structure. */
1796 ndev->base_addr = res->start;
1802 ret = platform_get_irq(pdev, 0);
1809 SET_NETDEV_DEV(ndev, &pdev->dev);
1811 /* Fill in the fields of the device structure with ethernet values. */
1814 mdp = netdev_priv(ndev);
1815 spin_lock_init(&mdp->lock);
1817 pm_runtime_enable(&pdev->dev);
1818 pm_runtime_resume(&pdev->dev);
1820 pd = (struct sh_eth_plat_data *)(pdev->dev.platform_data);
1822 mdp->phy_id = pd->phy;
1823 mdp->phy_interface = pd->phy_interface;
1825 mdp->edmac_endian = pd->edmac_endian;
1826 mdp->no_ether_link = pd->no_ether_link;
1827 mdp->ether_link_active_low = pd->ether_link_active_low;
1828 mdp->reg_offset = sh_eth_get_register_offset(pd->register_type);
1831 #if defined(SH_ETH_HAS_BOTH_MODULES)
1832 mdp->cd = sh_eth_get_cpu_data(mdp);
1834 mdp->cd = &sh_eth_my_cpu_data;
1836 sh_eth_set_default_cpu_data(mdp->cd);
1839 ndev->netdev_ops = &sh_eth_netdev_ops;
1840 SET_ETHTOOL_OPS(ndev, &sh_eth_ethtool_ops);
1841 ndev->watchdog_timeo = TX_TIMEOUT;
1843 /* debug message level */
1844 mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE;
1845 mdp->post_rx = POST_RX >> (devno << 1);
1846 mdp->post_fw = POST_FW >> (devno << 1);
1848 /* read and set MAC address */
1849 read_mac_address(ndev, pd->mac_addr);
1851 /* First device only init */
1854 struct resource *rtsu;
1855 rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1857 dev_err(&pdev->dev, "Not found TSU resource\n");
1860 mdp->tsu_addr = ioremap(rtsu->start,
1861 resource_size(rtsu));
1863 if (mdp->cd->chip_reset)
1864 mdp->cd->chip_reset(ndev);
1867 /* TSU init (Init only)*/
1868 sh_eth_tsu_init(mdp);
1872 /* network device register */
1873 ret = register_netdev(ndev);
1878 ret = sh_mdio_init(ndev, pdev->id, pd);
1880 goto out_unregister;
1882 /* print device information */
1883 pr_info("Base address at 0x%x, %pM, IRQ %d.\n",
1884 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
1886 platform_set_drvdata(pdev, ndev);
1891 unregister_netdev(ndev);
1895 if (mdp && mdp->tsu_addr)
1896 iounmap(mdp->tsu_addr);
1904 static int sh_eth_drv_remove(struct platform_device *pdev)
1906 struct net_device *ndev = platform_get_drvdata(pdev);
1907 struct sh_eth_private *mdp = netdev_priv(ndev);
1909 iounmap(mdp->tsu_addr);
1910 sh_mdio_release(ndev);
1911 unregister_netdev(ndev);
1912 pm_runtime_disable(&pdev->dev);
1914 platform_set_drvdata(pdev, NULL);
1919 static int sh_eth_runtime_nop(struct device *dev)
1922 * Runtime PM callback shared between ->runtime_suspend()
1923 * and ->runtime_resume(). Simply returns success.
1925 * This driver re-initializes all registers after
1926 * pm_runtime_get_sync() anyway so there is no need
1927 * to save and restore registers here.
1932 static struct dev_pm_ops sh_eth_dev_pm_ops = {
1933 .runtime_suspend = sh_eth_runtime_nop,
1934 .runtime_resume = sh_eth_runtime_nop,
1937 static struct platform_driver sh_eth_driver = {
1938 .probe = sh_eth_drv_probe,
1939 .remove = sh_eth_drv_remove,
1942 .pm = &sh_eth_dev_pm_ops,
1946 static int __init sh_eth_init(void)
1948 return platform_driver_register(&sh_eth_driver);
1951 static void __exit sh_eth_cleanup(void)
1953 platform_driver_unregister(&sh_eth_driver);
1956 module_init(sh_eth_init);
1957 module_exit(sh_eth_cleanup);
1959 MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
1960 MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
1961 MODULE_LICENSE("GPL v2");