2 * SuperH Ethernet device driver
4 * Copyright (C) 2006-2008 Nobuhiro Iwamatsu
5 * Copyright (C) 2008-2009 Renesas Solutions Corp.
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
16 * this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 * The full GNU General Public License is included in this distribution in
20 * the file called "COPYING".
23 #include <linux/init.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/etherdevice.h>
26 #include <linux/delay.h>
27 #include <linux/platform_device.h>
28 #include <linux/mdio-bitbang.h>
29 #include <linux/netdevice.h>
30 #include <linux/phy.h>
31 #include <linux/cache.h>
33 #include <linux/pm_runtime.h>
34 #include <linux/slab.h>
35 #include <linux/ethtool.h>
36 #include <asm/cacheflush.h>
40 #define SH_ETH_DEF_MSG_ENABLE \
46 /* There is CPU dependent code */
47 #if defined(CONFIG_CPU_SUBTYPE_SH7724)
48 #define SH_ETH_RESET_DEFAULT 1
49 static void sh_eth_set_duplex(struct net_device *ndev)
51 struct sh_eth_private *mdp = netdev_priv(ndev);
53 if (mdp->duplex) /* Full */
54 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
56 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
59 static void sh_eth_set_rate(struct net_device *ndev)
61 struct sh_eth_private *mdp = netdev_priv(ndev);
65 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_RTM, ECMR);
67 case 100:/* 100BASE */
68 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_RTM, ECMR);
76 static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
77 .set_duplex = sh_eth_set_duplex,
78 .set_rate = sh_eth_set_rate,
80 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
81 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
82 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x01ff009f,
84 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
85 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE |
86 EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI,
87 .tx_error_check = EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE,
94 .rpadir_value = 0x00020000, /* NET_IP_ALIGN assumed to be 2 */
96 #elif defined(CONFIG_CPU_SUBTYPE_SH7757)
97 #define SH_ETH_RESET_DEFAULT 1
98 static void sh_eth_set_duplex(struct net_device *ndev)
100 struct sh_eth_private *mdp = netdev_priv(ndev);
102 if (mdp->duplex) /* Full */
103 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
105 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
108 static void sh_eth_set_rate(struct net_device *ndev)
110 struct sh_eth_private *mdp = netdev_priv(ndev);
112 switch (mdp->speed) {
113 case 10: /* 10BASE */
114 sh_eth_write(ndev, 0, RTRATE);
116 case 100:/* 100BASE */
117 sh_eth_write(ndev, 1, RTRATE);
125 static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
126 .set_duplex = sh_eth_set_duplex,
127 .set_rate = sh_eth_set_rate,
129 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
130 .rmcr_value = 0x00000001,
132 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
133 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE |
134 EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI,
135 .tx_error_check = EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE,
144 #elif defined(CONFIG_CPU_SUBTYPE_SH7763)
145 #define SH_ETH_HAS_TSU 1
146 static void sh_eth_chip_reset(struct net_device *ndev)
149 writel(ARSTR_ARSTR, ARSTR);
153 static void sh_eth_reset(struct net_device *ndev)
157 sh_eth_write(ndev, EDSR_ENALL, EDSR);
158 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST, EDMR);
160 if (!(sh_eth_read(ndev, EDMR) & 0x3))
166 printk(KERN_ERR "Device reset fail\n");
169 sh_eth_write(ndev, 0x0, TDLAR);
170 sh_eth_write(ndev, 0x0, TDFAR);
171 sh_eth_write(ndev, 0x0, TDFXR);
172 sh_eth_write(ndev, 0x0, TDFFR);
173 sh_eth_write(ndev, 0x0, RDLAR);
174 sh_eth_write(ndev, 0x0, RDFAR);
175 sh_eth_write(ndev, 0x0, RDFXR);
176 sh_eth_write(ndev, 0x0, RDFFR);
179 static void sh_eth_set_duplex(struct net_device *ndev)
181 struct sh_eth_private *mdp = netdev_priv(ndev);
183 if (mdp->duplex) /* Full */
184 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
186 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
189 static void sh_eth_set_rate(struct net_device *ndev)
191 struct sh_eth_private *mdp = netdev_priv(ndev);
193 switch (mdp->speed) {
194 case 10: /* 10BASE */
195 sh_eth_write(ndev, GECMR_10, GECMR);
197 case 100:/* 100BASE */
198 sh_eth_write(ndev, GECMR_100, GECMR);
200 case 1000: /* 1000BASE */
201 sh_eth_write(ndev, GECMR_1000, GECMR);
209 static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
210 .chip_reset = sh_eth_chip_reset,
211 .set_duplex = sh_eth_set_duplex,
212 .set_rate = sh_eth_set_rate,
214 .ecsr_value = ECSR_ICD | ECSR_MPD,
215 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
216 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
218 .tx_check = EESR_TC1 | EESR_FTC,
219 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | \
220 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | \
222 .tx_error_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_TDE | \
234 #elif defined(CONFIG_CPU_SUBTYPE_SH7619)
235 #define SH_ETH_RESET_DEFAULT 1
236 static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
237 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
244 #elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
245 #define SH_ETH_RESET_DEFAULT 1
246 #define SH_ETH_HAS_TSU 1
247 static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
248 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
252 static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd)
255 cd->ecsr_value = DEFAULT_ECSR_INIT;
257 if (!cd->ecsipr_value)
258 cd->ecsipr_value = DEFAULT_ECSIPR_INIT;
260 if (!cd->fcftr_value)
261 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF | \
262 DEFAULT_FIFO_F_D_RFD;
265 cd->fdr_value = DEFAULT_FDR_INIT;
268 cd->rmcr_value = DEFAULT_RMCR_VALUE;
271 cd->tx_check = DEFAULT_TX_CHECK;
273 if (!cd->eesr_err_check)
274 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK;
276 if (!cd->tx_error_check)
277 cd->tx_error_check = DEFAULT_TX_ERROR_CHECK;
280 #if defined(SH_ETH_RESET_DEFAULT)
282 static void sh_eth_reset(struct net_device *ndev)
284 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST, EDMR);
286 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) & ~EDMR_SRST, EDMR);
290 #if defined(CONFIG_CPU_SH4)
291 static void sh_eth_set_receive_align(struct sk_buff *skb)
295 reserve = SH4_SKB_RX_ALIGN - ((u32)skb->data & (SH4_SKB_RX_ALIGN - 1));
297 skb_reserve(skb, reserve);
300 static void sh_eth_set_receive_align(struct sk_buff *skb)
302 skb_reserve(skb, SH2_SH3_SKB_RX_ALIGN);
307 /* CPU <-> EDMAC endian convert */
308 static inline __u32 cpu_to_edmac(struct sh_eth_private *mdp, u32 x)
310 switch (mdp->edmac_endian) {
311 case EDMAC_LITTLE_ENDIAN:
312 return cpu_to_le32(x);
313 case EDMAC_BIG_ENDIAN:
314 return cpu_to_be32(x);
319 static inline __u32 edmac_to_cpu(struct sh_eth_private *mdp, u32 x)
321 switch (mdp->edmac_endian) {
322 case EDMAC_LITTLE_ENDIAN:
323 return le32_to_cpu(x);
324 case EDMAC_BIG_ENDIAN:
325 return be32_to_cpu(x);
331 * Program the hardware MAC address from dev->dev_addr.
333 static void update_mac_address(struct net_device *ndev)
336 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
337 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
339 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
343 * Get MAC address from SuperH MAC address register
345 * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
346 * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
347 * When you want use this device, you must set MAC address in bootloader.
350 static void read_mac_address(struct net_device *ndev, unsigned char *mac)
352 if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) {
353 memcpy(ndev->dev_addr, mac, 6);
355 ndev->dev_addr[0] = (sh_eth_read(ndev, MAHR) >> 24);
356 ndev->dev_addr[1] = (sh_eth_read(ndev, MAHR) >> 16) & 0xFF;
357 ndev->dev_addr[2] = (sh_eth_read(ndev, MAHR) >> 8) & 0xFF;
358 ndev->dev_addr[3] = (sh_eth_read(ndev, MAHR) & 0xFF);
359 ndev->dev_addr[4] = (sh_eth_read(ndev, MALR) >> 8) & 0xFF;
360 ndev->dev_addr[5] = (sh_eth_read(ndev, MALR) & 0xFF);
365 struct mdiobb_ctrl ctrl;
367 u32 mmd_msk;/* MMD */
374 static void bb_set(u32 addr, u32 msk)
376 writel(readl(addr) | msk, addr);
380 static void bb_clr(u32 addr, u32 msk)
382 writel((readl(addr) & ~msk), addr);
386 static int bb_read(u32 addr, u32 msk)
388 return (readl(addr) & msk) != 0;
391 /* Data I/O pin control */
392 static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit)
394 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
396 bb_set(bitbang->addr, bitbang->mmd_msk);
398 bb_clr(bitbang->addr, bitbang->mmd_msk);
402 static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit)
404 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
407 bb_set(bitbang->addr, bitbang->mdo_msk);
409 bb_clr(bitbang->addr, bitbang->mdo_msk);
413 static int sh_get_mdio(struct mdiobb_ctrl *ctrl)
415 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
416 return bb_read(bitbang->addr, bitbang->mdi_msk);
419 /* MDC pin control */
420 static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit)
422 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
425 bb_set(bitbang->addr, bitbang->mdc_msk);
427 bb_clr(bitbang->addr, bitbang->mdc_msk);
430 /* mdio bus control struct */
431 static struct mdiobb_ops bb_ops = {
432 .owner = THIS_MODULE,
433 .set_mdc = sh_mdc_ctrl,
434 .set_mdio_dir = sh_mmd_ctrl,
435 .set_mdio_data = sh_set_mdio,
436 .get_mdio_data = sh_get_mdio,
439 /* free skb and descriptor buffer */
440 static void sh_eth_ring_free(struct net_device *ndev)
442 struct sh_eth_private *mdp = netdev_priv(ndev);
445 /* Free Rx skb ringbuffer */
446 if (mdp->rx_skbuff) {
447 for (i = 0; i < RX_RING_SIZE; i++) {
448 if (mdp->rx_skbuff[i])
449 dev_kfree_skb(mdp->rx_skbuff[i]);
452 kfree(mdp->rx_skbuff);
454 /* Free Tx skb ringbuffer */
455 if (mdp->tx_skbuff) {
456 for (i = 0; i < TX_RING_SIZE; i++) {
457 if (mdp->tx_skbuff[i])
458 dev_kfree_skb(mdp->tx_skbuff[i]);
461 kfree(mdp->tx_skbuff);
464 /* format skb and descriptor buffer */
465 static void sh_eth_ring_format(struct net_device *ndev)
467 struct sh_eth_private *mdp = netdev_priv(ndev);
470 struct sh_eth_rxdesc *rxdesc = NULL;
471 struct sh_eth_txdesc *txdesc = NULL;
472 int rx_ringsize = sizeof(*rxdesc) * RX_RING_SIZE;
473 int tx_ringsize = sizeof(*txdesc) * TX_RING_SIZE;
475 mdp->cur_rx = mdp->cur_tx = 0;
476 mdp->dirty_rx = mdp->dirty_tx = 0;
478 memset(mdp->rx_ring, 0, rx_ringsize);
480 /* build Rx ring buffer */
481 for (i = 0; i < RX_RING_SIZE; i++) {
483 mdp->rx_skbuff[i] = NULL;
484 skb = dev_alloc_skb(mdp->rx_buf_sz);
485 mdp->rx_skbuff[i] = skb;
488 dma_map_single(&ndev->dev, skb->tail, mdp->rx_buf_sz,
490 skb->dev = ndev; /* Mark as being used by this device. */
491 sh_eth_set_receive_align(skb);
494 rxdesc = &mdp->rx_ring[i];
495 rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4));
496 rxdesc->status = cpu_to_edmac(mdp, RD_RACT | RD_RFP);
498 /* The size of the buffer is 16 byte boundary. */
499 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16);
500 /* Rx descriptor address set */
502 sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR);
503 #if defined(CONFIG_CPU_SUBTYPE_SH7763)
504 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR);
509 mdp->dirty_rx = (u32) (i - RX_RING_SIZE);
511 /* Mark the last entry as wrapping the ring. */
512 rxdesc->status |= cpu_to_edmac(mdp, RD_RDEL);
514 memset(mdp->tx_ring, 0, tx_ringsize);
516 /* build Tx ring buffer */
517 for (i = 0; i < TX_RING_SIZE; i++) {
518 mdp->tx_skbuff[i] = NULL;
519 txdesc = &mdp->tx_ring[i];
520 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
521 txdesc->buffer_length = 0;
523 /* Tx descriptor address set */
524 sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR);
525 #if defined(CONFIG_CPU_SUBTYPE_SH7763)
526 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR);
531 txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
534 /* Get skb and descriptor buffer */
535 static int sh_eth_ring_init(struct net_device *ndev)
537 struct sh_eth_private *mdp = netdev_priv(ndev);
538 int rx_ringsize, tx_ringsize, ret = 0;
541 * +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
542 * card needs room to do 8 byte alignment, +2 so we can reserve
543 * the first 2 bytes, and +16 gets room for the status word from the
546 mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ :
547 (((ndev->mtu + 26 + 7) & ~7) + 2 + 16));
549 mdp->rx_buf_sz += NET_IP_ALIGN;
551 /* Allocate RX and TX skb rings */
552 mdp->rx_skbuff = kmalloc(sizeof(*mdp->rx_skbuff) * RX_RING_SIZE,
554 if (!mdp->rx_skbuff) {
555 dev_err(&ndev->dev, "Cannot allocate Rx skb\n");
560 mdp->tx_skbuff = kmalloc(sizeof(*mdp->tx_skbuff) * TX_RING_SIZE,
562 if (!mdp->tx_skbuff) {
563 dev_err(&ndev->dev, "Cannot allocate Tx skb\n");
568 /* Allocate all Rx descriptors. */
569 rx_ringsize = sizeof(struct sh_eth_rxdesc) * RX_RING_SIZE;
570 mdp->rx_ring = dma_alloc_coherent(NULL, rx_ringsize, &mdp->rx_desc_dma,
574 dev_err(&ndev->dev, "Cannot allocate Rx Ring (size %d bytes)\n",
582 /* Allocate all Tx descriptors. */
583 tx_ringsize = sizeof(struct sh_eth_txdesc) * TX_RING_SIZE;
584 mdp->tx_ring = dma_alloc_coherent(NULL, tx_ringsize, &mdp->tx_desc_dma,
587 dev_err(&ndev->dev, "Cannot allocate Tx Ring (size %d bytes)\n",
595 /* free DMA buffer */
596 dma_free_coherent(NULL, rx_ringsize, mdp->rx_ring, mdp->rx_desc_dma);
599 /* Free Rx and Tx skb ring buffer */
600 sh_eth_ring_free(ndev);
605 static int sh_eth_dev_init(struct net_device *ndev)
608 struct sh_eth_private *mdp = netdev_priv(ndev);
609 u_int32_t rx_int_var, tx_int_var;
615 /* Descriptor format */
616 sh_eth_ring_format(ndev);
618 sh_eth_write(ndev, mdp->cd->rpadir_value, RPADIR);
620 /* all sh_eth int mask */
621 sh_eth_write(ndev, 0, EESIPR);
623 #if defined(__LITTLE_ENDIAN__)
624 if (mdp->cd->hw_swap)
625 sh_eth_write(ndev, EDMR_EL, EDMR);
628 sh_eth_write(ndev, 0, EDMR);
631 sh_eth_write(ndev, mdp->cd->fdr_value, FDR);
632 sh_eth_write(ndev, 0, TFTR);
634 /* Frame recv control */
635 sh_eth_write(ndev, mdp->cd->rmcr_value, RMCR);
637 rx_int_var = mdp->rx_int_var = DESC_I_RINT8 | DESC_I_RINT5;
638 tx_int_var = mdp->tx_int_var = DESC_I_TINT2;
639 sh_eth_write(ndev, rx_int_var | tx_int_var, TRSCER);
642 sh_eth_write(ndev, 0x800, BCULR); /* Burst sycle set */
644 sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR);
646 if (!mdp->cd->no_trimd)
647 sh_eth_write(ndev, 0, TRIMD);
649 /* Recv frame limit set register */
650 sh_eth_write(ndev, RFLR_VALUE, RFLR);
652 sh_eth_write(ndev, sh_eth_read(ndev, EESR), EESR);
653 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
655 /* PAUSE Prohibition */
656 val = (sh_eth_read(ndev, ECMR) & ECMR_DM) |
657 ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) | ECMR_TE | ECMR_RE;
659 sh_eth_write(ndev, val, ECMR);
661 if (mdp->cd->set_rate)
662 mdp->cd->set_rate(ndev);
664 /* E-MAC Status Register clear */
665 sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR);
667 /* E-MAC Interrupt Enable register */
668 sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR);
670 /* Set MAC address */
671 update_mac_address(ndev);
675 sh_eth_write(ndev, APR_AP, APR);
677 sh_eth_write(ndev, MPR_MP, MPR);
678 if (mdp->cd->tpauser)
679 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER);
681 /* Setting the Rx mode will start the Rx process. */
682 sh_eth_write(ndev, EDRRR_R, EDRRR);
684 netif_start_queue(ndev);
689 /* free Tx skb function */
690 static int sh_eth_txfree(struct net_device *ndev)
692 struct sh_eth_private *mdp = netdev_priv(ndev);
693 struct sh_eth_txdesc *txdesc;
697 for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) {
698 entry = mdp->dirty_tx % TX_RING_SIZE;
699 txdesc = &mdp->tx_ring[entry];
700 if (txdesc->status & cpu_to_edmac(mdp, TD_TACT))
702 /* Free the original skb. */
703 if (mdp->tx_skbuff[entry]) {
704 dev_kfree_skb_irq(mdp->tx_skbuff[entry]);
705 mdp->tx_skbuff[entry] = NULL;
708 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
709 if (entry >= TX_RING_SIZE - 1)
710 txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
712 mdp->stats.tx_packets++;
713 mdp->stats.tx_bytes += txdesc->buffer_length;
718 /* Packet receive function */
719 static int sh_eth_rx(struct net_device *ndev)
721 struct sh_eth_private *mdp = netdev_priv(ndev);
722 struct sh_eth_rxdesc *rxdesc;
724 int entry = mdp->cur_rx % RX_RING_SIZE;
725 int boguscnt = (mdp->dirty_rx + RX_RING_SIZE) - mdp->cur_rx;
730 rxdesc = &mdp->rx_ring[entry];
731 while (!(rxdesc->status & cpu_to_edmac(mdp, RD_RACT))) {
732 desc_status = edmac_to_cpu(mdp, rxdesc->status);
733 pkt_len = rxdesc->frame_length;
738 if (!(desc_status & RDFEND))
739 mdp->stats.rx_length_errors++;
741 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 |
742 RD_RFS5 | RD_RFS6 | RD_RFS10)) {
743 mdp->stats.rx_errors++;
744 if (desc_status & RD_RFS1)
745 mdp->stats.rx_crc_errors++;
746 if (desc_status & RD_RFS2)
747 mdp->stats.rx_frame_errors++;
748 if (desc_status & RD_RFS3)
749 mdp->stats.rx_length_errors++;
750 if (desc_status & RD_RFS4)
751 mdp->stats.rx_length_errors++;
752 if (desc_status & RD_RFS6)
753 mdp->stats.rx_missed_errors++;
754 if (desc_status & RD_RFS10)
755 mdp->stats.rx_over_errors++;
757 if (!mdp->cd->hw_swap)
759 phys_to_virt(ALIGN(rxdesc->addr, 4)),
761 skb = mdp->rx_skbuff[entry];
762 mdp->rx_skbuff[entry] = NULL;
764 skb_reserve(skb, NET_IP_ALIGN);
765 skb_put(skb, pkt_len);
766 skb->protocol = eth_type_trans(skb, ndev);
768 mdp->stats.rx_packets++;
769 mdp->stats.rx_bytes += pkt_len;
771 rxdesc->status |= cpu_to_edmac(mdp, RD_RACT);
772 entry = (++mdp->cur_rx) % RX_RING_SIZE;
773 rxdesc = &mdp->rx_ring[entry];
776 /* Refill the Rx ring buffers. */
777 for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) {
778 entry = mdp->dirty_rx % RX_RING_SIZE;
779 rxdesc = &mdp->rx_ring[entry];
780 /* The size of the buffer is 16 byte boundary. */
781 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16);
783 if (mdp->rx_skbuff[entry] == NULL) {
784 skb = dev_alloc_skb(mdp->rx_buf_sz);
785 mdp->rx_skbuff[entry] = skb;
787 break; /* Better luck next round. */
788 dma_map_single(&ndev->dev, skb->tail, mdp->rx_buf_sz,
791 sh_eth_set_receive_align(skb);
793 skb_checksum_none_assert(skb);
794 rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4));
796 if (entry >= RX_RING_SIZE - 1)
798 cpu_to_edmac(mdp, RD_RACT | RD_RFP | RD_RDEL);
801 cpu_to_edmac(mdp, RD_RACT | RD_RFP);
804 /* Restart Rx engine if stopped. */
805 /* If we don't need to check status, don't. -KDU */
806 if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R))
807 sh_eth_write(ndev, EDRRR_R, EDRRR);
812 static void sh_eth_rcv_snd_disable(struct net_device *ndev)
814 /* disable tx and rx */
815 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) &
816 ~(ECMR_RE | ECMR_TE), ECMR);
819 static void sh_eth_rcv_snd_enable(struct net_device *ndev)
821 /* enable tx and rx */
822 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) |
823 (ECMR_RE | ECMR_TE), ECMR);
826 /* error control function */
827 static void sh_eth_error(struct net_device *ndev, int intr_status)
829 struct sh_eth_private *mdp = netdev_priv(ndev);
834 if (intr_status & EESR_ECI) {
835 felic_stat = sh_eth_read(ndev, ECSR);
836 sh_eth_write(ndev, felic_stat, ECSR); /* clear int */
837 if (felic_stat & ECSR_ICD)
838 mdp->stats.tx_carrier_errors++;
839 if (felic_stat & ECSR_LCHNG) {
841 if (mdp->cd->no_psr || mdp->no_ether_link) {
842 if (mdp->link == PHY_DOWN)
845 link_stat = PHY_ST_LINK;
847 link_stat = (sh_eth_read(ndev, PSR));
848 if (mdp->ether_link_active_low)
849 link_stat = ~link_stat;
851 if (!(link_stat & PHY_ST_LINK))
852 sh_eth_rcv_snd_disable(ndev);
855 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) &
856 ~DMAC_M_ECI, EESIPR);
858 sh_eth_write(ndev, sh_eth_read(ndev, ECSR),
860 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) |
862 /* enable tx and rx */
863 sh_eth_rcv_snd_enable(ndev);
868 if (intr_status & EESR_TWB) {
869 /* Write buck end. unused write back interrupt */
870 if (intr_status & EESR_TABT) /* Transmit Abort int */
871 mdp->stats.tx_aborted_errors++;
872 if (netif_msg_tx_err(mdp))
873 dev_err(&ndev->dev, "Transmit Abort\n");
876 if (intr_status & EESR_RABT) {
877 /* Receive Abort int */
878 if (intr_status & EESR_RFRMER) {
879 /* Receive Frame Overflow int */
880 mdp->stats.rx_frame_errors++;
881 if (netif_msg_rx_err(mdp))
882 dev_err(&ndev->dev, "Receive Abort\n");
886 if (intr_status & EESR_TDE) {
887 /* Transmit Descriptor Empty int */
888 mdp->stats.tx_fifo_errors++;
889 if (netif_msg_tx_err(mdp))
890 dev_err(&ndev->dev, "Transmit Descriptor Empty\n");
893 if (intr_status & EESR_TFE) {
894 /* FIFO under flow */
895 mdp->stats.tx_fifo_errors++;
896 if (netif_msg_tx_err(mdp))
897 dev_err(&ndev->dev, "Transmit FIFO Under flow\n");
900 if (intr_status & EESR_RDE) {
901 /* Receive Descriptor Empty int */
902 mdp->stats.rx_over_errors++;
904 if (sh_eth_read(ndev, EDRRR) ^ EDRRR_R)
905 sh_eth_write(ndev, EDRRR_R, EDRRR);
906 if (netif_msg_rx_err(mdp))
907 dev_err(&ndev->dev, "Receive Descriptor Empty\n");
910 if (intr_status & EESR_RFE) {
911 /* Receive FIFO Overflow int */
912 mdp->stats.rx_fifo_errors++;
913 if (netif_msg_rx_err(mdp))
914 dev_err(&ndev->dev, "Receive FIFO Overflow\n");
917 if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) {
919 mdp->stats.tx_fifo_errors++;
920 if (netif_msg_tx_err(mdp))
921 dev_err(&ndev->dev, "Address Error\n");
924 mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE;
927 if (intr_status & mask) {
929 u32 edtrr = sh_eth_read(ndev, EDTRR);
931 dev_err(&ndev->dev, "TX error. status=%8.8x cur_tx=%8.8x ",
932 intr_status, mdp->cur_tx);
933 dev_err(&ndev->dev, "dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
934 mdp->dirty_tx, (u32) ndev->state, edtrr);
935 /* dirty buffer free */
939 if (edtrr ^ EDTRR_TRNS) {
941 sh_eth_write(ndev, EDTRR_TRNS, EDTRR);
944 netif_wake_queue(ndev);
948 static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
950 struct net_device *ndev = netdev;
951 struct sh_eth_private *mdp = netdev_priv(ndev);
952 struct sh_eth_cpu_data *cd = mdp->cd;
953 irqreturn_t ret = IRQ_NONE;
956 spin_lock(&mdp->lock);
958 /* Get interrpt stat */
959 intr_status = sh_eth_read(ndev, EESR);
960 /* Clear interrupt */
961 if (intr_status & (EESR_FRC | EESR_RMAF | EESR_RRF |
962 EESR_RTLF | EESR_RTSF | EESR_PRE | EESR_CERF |
963 cd->tx_check | cd->eesr_err_check)) {
964 sh_eth_write(ndev, intr_status, EESR);
969 if (intr_status & (EESR_FRC | /* Frame recv*/
970 EESR_RMAF | /* Multi cast address recv*/
971 EESR_RRF | /* Bit frame recv */
972 EESR_RTLF | /* Long frame recv*/
973 EESR_RTSF | /* short frame recv */
974 EESR_PRE | /* PHY-LSI recv error */
975 EESR_CERF)){ /* recv frame CRC error */
980 if (intr_status & cd->tx_check) {
982 netif_wake_queue(ndev);
985 if (intr_status & cd->eesr_err_check)
986 sh_eth_error(ndev, intr_status);
989 spin_unlock(&mdp->lock);
994 static void sh_eth_timer(unsigned long data)
996 struct net_device *ndev = (struct net_device *)data;
997 struct sh_eth_private *mdp = netdev_priv(ndev);
999 mod_timer(&mdp->timer, jiffies + (10 * HZ));
1002 /* PHY state control function */
1003 static void sh_eth_adjust_link(struct net_device *ndev)
1005 struct sh_eth_private *mdp = netdev_priv(ndev);
1006 struct phy_device *phydev = mdp->phydev;
1009 if (phydev->link != PHY_DOWN) {
1010 if (phydev->duplex != mdp->duplex) {
1012 mdp->duplex = phydev->duplex;
1013 if (mdp->cd->set_duplex)
1014 mdp->cd->set_duplex(ndev);
1017 if (phydev->speed != mdp->speed) {
1019 mdp->speed = phydev->speed;
1020 if (mdp->cd->set_rate)
1021 mdp->cd->set_rate(ndev);
1023 if (mdp->link == PHY_DOWN) {
1024 sh_eth_write(ndev, (sh_eth_read(ndev, ECMR) & ~ECMR_TXF)
1027 mdp->link = phydev->link;
1029 } else if (mdp->link) {
1031 mdp->link = PHY_DOWN;
1036 if (new_state && netif_msg_link(mdp))
1037 phy_print_status(phydev);
1040 /* PHY init function */
1041 static int sh_eth_phy_init(struct net_device *ndev)
1043 struct sh_eth_private *mdp = netdev_priv(ndev);
1044 char phy_id[MII_BUS_ID_SIZE + 3];
1045 struct phy_device *phydev = NULL;
1047 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
1048 mdp->mii_bus->id , mdp->phy_id);
1050 mdp->link = PHY_DOWN;
1054 /* Try connect to PHY */
1055 phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link,
1056 0, PHY_INTERFACE_MODE_MII);
1057 if (IS_ERR(phydev)) {
1058 dev_err(&ndev->dev, "phy_connect failed\n");
1059 return PTR_ERR(phydev);
1062 dev_info(&ndev->dev, "attached phy %i to driver %s\n",
1063 phydev->addr, phydev->drv->name);
1065 mdp->phydev = phydev;
1070 /* PHY control start function */
1071 static int sh_eth_phy_start(struct net_device *ndev)
1073 struct sh_eth_private *mdp = netdev_priv(ndev);
1076 ret = sh_eth_phy_init(ndev);
1080 /* reset phy - this also wakes it from PDOWN */
1081 phy_write(mdp->phydev, MII_BMCR, BMCR_RESET);
1082 phy_start(mdp->phydev);
1087 static int sh_eth_get_settings(struct net_device *ndev,
1088 struct ethtool_cmd *ecmd)
1090 struct sh_eth_private *mdp = netdev_priv(ndev);
1091 unsigned long flags;
1094 spin_lock_irqsave(&mdp->lock, flags);
1095 ret = phy_ethtool_gset(mdp->phydev, ecmd);
1096 spin_unlock_irqrestore(&mdp->lock, flags);
1101 static int sh_eth_set_settings(struct net_device *ndev,
1102 struct ethtool_cmd *ecmd)
1104 struct sh_eth_private *mdp = netdev_priv(ndev);
1105 unsigned long flags;
1108 spin_lock_irqsave(&mdp->lock, flags);
1110 /* disable tx and rx */
1111 sh_eth_rcv_snd_disable(ndev);
1113 ret = phy_ethtool_sset(mdp->phydev, ecmd);
1117 if (ecmd->duplex == DUPLEX_FULL)
1122 if (mdp->cd->set_duplex)
1123 mdp->cd->set_duplex(ndev);
1128 /* enable tx and rx */
1129 sh_eth_rcv_snd_enable(ndev);
1131 spin_unlock_irqrestore(&mdp->lock, flags);
1136 static int sh_eth_nway_reset(struct net_device *ndev)
1138 struct sh_eth_private *mdp = netdev_priv(ndev);
1139 unsigned long flags;
1142 spin_lock_irqsave(&mdp->lock, flags);
1143 ret = phy_start_aneg(mdp->phydev);
1144 spin_unlock_irqrestore(&mdp->lock, flags);
1149 static u32 sh_eth_get_msglevel(struct net_device *ndev)
1151 struct sh_eth_private *mdp = netdev_priv(ndev);
1152 return mdp->msg_enable;
1155 static void sh_eth_set_msglevel(struct net_device *ndev, u32 value)
1157 struct sh_eth_private *mdp = netdev_priv(ndev);
1158 mdp->msg_enable = value;
1161 static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = {
1162 "rx_current", "tx_current",
1163 "rx_dirty", "tx_dirty",
1165 #define SH_ETH_STATS_LEN ARRAY_SIZE(sh_eth_gstrings_stats)
1167 static int sh_eth_get_sset_count(struct net_device *netdev, int sset)
1171 return SH_ETH_STATS_LEN;
1177 static void sh_eth_get_ethtool_stats(struct net_device *ndev,
1178 struct ethtool_stats *stats, u64 *data)
1180 struct sh_eth_private *mdp = netdev_priv(ndev);
1183 /* device-specific stats */
1184 data[i++] = mdp->cur_rx;
1185 data[i++] = mdp->cur_tx;
1186 data[i++] = mdp->dirty_rx;
1187 data[i++] = mdp->dirty_tx;
1190 static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1192 switch (stringset) {
1194 memcpy(data, *sh_eth_gstrings_stats,
1195 sizeof(sh_eth_gstrings_stats));
1200 static struct ethtool_ops sh_eth_ethtool_ops = {
1201 .get_settings = sh_eth_get_settings,
1202 .set_settings = sh_eth_set_settings,
1203 .nway_reset = sh_eth_nway_reset,
1204 .get_msglevel = sh_eth_get_msglevel,
1205 .set_msglevel = sh_eth_set_msglevel,
1206 .get_link = ethtool_op_get_link,
1207 .get_strings = sh_eth_get_strings,
1208 .get_ethtool_stats = sh_eth_get_ethtool_stats,
1209 .get_sset_count = sh_eth_get_sset_count,
1212 /* network device open function */
1213 static int sh_eth_open(struct net_device *ndev)
1216 struct sh_eth_private *mdp = netdev_priv(ndev);
1218 pm_runtime_get_sync(&mdp->pdev->dev);
1220 ret = request_irq(ndev->irq, sh_eth_interrupt,
1221 #if defined(CONFIG_CPU_SUBTYPE_SH7763) || \
1222 defined(CONFIG_CPU_SUBTYPE_SH7764) || \
1223 defined(CONFIG_CPU_SUBTYPE_SH7757)
1230 dev_err(&ndev->dev, "Can not assign IRQ number\n");
1234 /* Descriptor set */
1235 ret = sh_eth_ring_init(ndev);
1240 ret = sh_eth_dev_init(ndev);
1244 /* PHY control start*/
1245 ret = sh_eth_phy_start(ndev);
1249 /* Set the timer to check for link beat. */
1250 init_timer(&mdp->timer);
1251 mdp->timer.expires = (jiffies + (24 * HZ)) / 10;/* 2.4 sec. */
1252 setup_timer(&mdp->timer, sh_eth_timer, (unsigned long)ndev);
1257 free_irq(ndev->irq, ndev);
1258 pm_runtime_put_sync(&mdp->pdev->dev);
1262 /* Timeout function */
1263 static void sh_eth_tx_timeout(struct net_device *ndev)
1265 struct sh_eth_private *mdp = netdev_priv(ndev);
1266 struct sh_eth_rxdesc *rxdesc;
1269 netif_stop_queue(ndev);
1271 if (netif_msg_timer(mdp))
1272 dev_err(&ndev->dev, "%s: transmit timed out, status %8.8x,"
1273 " resetting...\n", ndev->name, (int)sh_eth_read(ndev, EESR));
1275 /* tx_errors count up */
1276 mdp->stats.tx_errors++;
1279 del_timer_sync(&mdp->timer);
1281 /* Free all the skbuffs in the Rx queue. */
1282 for (i = 0; i < RX_RING_SIZE; i++) {
1283 rxdesc = &mdp->rx_ring[i];
1285 rxdesc->addr = 0xBADF00D0;
1286 if (mdp->rx_skbuff[i])
1287 dev_kfree_skb(mdp->rx_skbuff[i]);
1288 mdp->rx_skbuff[i] = NULL;
1290 for (i = 0; i < TX_RING_SIZE; i++) {
1291 if (mdp->tx_skbuff[i])
1292 dev_kfree_skb(mdp->tx_skbuff[i]);
1293 mdp->tx_skbuff[i] = NULL;
1297 sh_eth_dev_init(ndev);
1300 mdp->timer.expires = (jiffies + (24 * HZ)) / 10;/* 2.4 sec. */
1301 add_timer(&mdp->timer);
1304 /* Packet transmit function */
1305 static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
1307 struct sh_eth_private *mdp = netdev_priv(ndev);
1308 struct sh_eth_txdesc *txdesc;
1310 unsigned long flags;
1312 spin_lock_irqsave(&mdp->lock, flags);
1313 if ((mdp->cur_tx - mdp->dirty_tx) >= (TX_RING_SIZE - 4)) {
1314 if (!sh_eth_txfree(ndev)) {
1315 if (netif_msg_tx_queued(mdp))
1316 dev_warn(&ndev->dev, "TxFD exhausted.\n");
1317 netif_stop_queue(ndev);
1318 spin_unlock_irqrestore(&mdp->lock, flags);
1319 return NETDEV_TX_BUSY;
1322 spin_unlock_irqrestore(&mdp->lock, flags);
1324 entry = mdp->cur_tx % TX_RING_SIZE;
1325 mdp->tx_skbuff[entry] = skb;
1326 txdesc = &mdp->tx_ring[entry];
1327 txdesc->addr = virt_to_phys(skb->data);
1329 if (!mdp->cd->hw_swap)
1330 sh_eth_soft_swap(phys_to_virt(ALIGN(txdesc->addr, 4)),
1333 __flush_purge_region(skb->data, skb->len);
1334 if (skb->len < ETHERSMALL)
1335 txdesc->buffer_length = ETHERSMALL;
1337 txdesc->buffer_length = skb->len;
1339 if (entry >= TX_RING_SIZE - 1)
1340 txdesc->status |= cpu_to_edmac(mdp, TD_TACT | TD_TDLE);
1342 txdesc->status |= cpu_to_edmac(mdp, TD_TACT);
1346 if (!(sh_eth_read(ndev, EDTRR) & EDTRR_TRNS))
1347 sh_eth_write(ndev, EDTRR_TRNS, EDTRR);
1349 return NETDEV_TX_OK;
1352 /* device close function */
1353 static int sh_eth_close(struct net_device *ndev)
1355 struct sh_eth_private *mdp = netdev_priv(ndev);
1358 netif_stop_queue(ndev);
1360 /* Disable interrupts by clearing the interrupt mask. */
1361 sh_eth_write(ndev, 0x0000, EESIPR);
1363 /* Stop the chip's Tx and Rx processes. */
1364 sh_eth_write(ndev, 0, EDTRR);
1365 sh_eth_write(ndev, 0, EDRRR);
1367 /* PHY Disconnect */
1369 phy_stop(mdp->phydev);
1370 phy_disconnect(mdp->phydev);
1373 free_irq(ndev->irq, ndev);
1375 del_timer_sync(&mdp->timer);
1377 /* Free all the skbuffs in the Rx queue. */
1378 sh_eth_ring_free(ndev);
1380 /* free DMA buffer */
1381 ringsize = sizeof(struct sh_eth_rxdesc) * RX_RING_SIZE;
1382 dma_free_coherent(NULL, ringsize, mdp->rx_ring, mdp->rx_desc_dma);
1384 /* free DMA buffer */
1385 ringsize = sizeof(struct sh_eth_txdesc) * TX_RING_SIZE;
1386 dma_free_coherent(NULL, ringsize, mdp->tx_ring, mdp->tx_desc_dma);
1388 pm_runtime_put_sync(&mdp->pdev->dev);
1393 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev)
1395 struct sh_eth_private *mdp = netdev_priv(ndev);
1397 pm_runtime_get_sync(&mdp->pdev->dev);
1399 mdp->stats.tx_dropped += sh_eth_read(ndev, TROCR);
1400 sh_eth_write(ndev, 0, TROCR); /* (write clear) */
1401 mdp->stats.collisions += sh_eth_read(ndev, CDCR);
1402 sh_eth_write(ndev, 0, CDCR); /* (write clear) */
1403 mdp->stats.tx_carrier_errors += sh_eth_read(ndev, LCCR);
1404 sh_eth_write(ndev, 0, LCCR); /* (write clear) */
1405 #if defined(CONFIG_CPU_SUBTYPE_SH7763)
1406 mdp->stats.tx_carrier_errors += sh_eth_read(ndev, CERCR);/* CERCR */
1407 sh_eth_write(ndev, 0, CERCR); /* (write clear) */
1408 mdp->stats.tx_carrier_errors += sh_eth_read(ndev, CEECR);/* CEECR */
1409 sh_eth_write(ndev, 0, CEECR); /* (write clear) */
1411 mdp->stats.tx_carrier_errors += sh_eth_read(ndev, CNDCR);
1412 sh_eth_write(ndev, 0, CNDCR); /* (write clear) */
1414 pm_runtime_put_sync(&mdp->pdev->dev);
1419 /* ioctl to device funciotn*/
1420 static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq,
1423 struct sh_eth_private *mdp = netdev_priv(ndev);
1424 struct phy_device *phydev = mdp->phydev;
1426 if (!netif_running(ndev))
1432 return phy_mii_ioctl(phydev, rq, cmd);
1435 #if defined(SH_ETH_HAS_TSU)
1436 /* Multicast reception directions set */
1437 static void sh_eth_set_multicast_list(struct net_device *ndev)
1439 if (ndev->flags & IFF_PROMISC) {
1440 /* Set promiscuous. */
1441 sh_eth_write(ndev, (sh_eth_read(ndev, ECMR) & ~ECMR_MCT) |
1444 /* Normal, unicast/broadcast-only mode. */
1445 sh_eth_write(ndev, (sh_eth_read(ndev, ECMR) & ~ECMR_PRM) |
1450 /* SuperH's TSU register init function */
1451 static void sh_eth_tsu_init(struct sh_eth_private *mdp)
1453 sh_eth_tsu_write(mdp, 0, TSU_FWEN0); /* Disable forward(0->1) */
1454 sh_eth_tsu_write(mdp, 0, TSU_FWEN1); /* Disable forward(1->0) */
1455 sh_eth_tsu_write(mdp, 0, TSU_FCM); /* forward fifo 3k-3k */
1456 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0);
1457 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1);
1458 sh_eth_tsu_write(mdp, 0, TSU_PRISL0);
1459 sh_eth_tsu_write(mdp, 0, TSU_PRISL1);
1460 sh_eth_tsu_write(mdp, 0, TSU_FWSL0);
1461 sh_eth_tsu_write(mdp, 0, TSU_FWSL1);
1462 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC);
1463 #if defined(CONFIG_CPU_SUBTYPE_SH7763)
1464 sh_eth_tsu_write(mdp, 0, TSU_QTAG0); /* Disable QTAG(0->1) */
1465 sh_eth_tsu_write(mdp, 0, TSU_QTAG1); /* Disable QTAG(1->0) */
1467 sh_eth_tsu_write(mdp, 0, TSU_QTAGM0); /* Disable QTAG(0->1) */
1468 sh_eth_tsu_write(mdp, 0, TSU_QTAGM1); /* Disable QTAG(1->0) */
1470 sh_eth_tsu_write(mdp, 0, TSU_FWSR); /* all interrupt status clear */
1471 sh_eth_tsu_write(mdp, 0, TSU_FWINMK); /* Disable all interrupt */
1472 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
1473 sh_eth_tsu_write(mdp, 0, TSU_POST1); /* Disable CAM entry [ 0- 7] */
1474 sh_eth_tsu_write(mdp, 0, TSU_POST2); /* Disable CAM entry [ 8-15] */
1475 sh_eth_tsu_write(mdp, 0, TSU_POST3); /* Disable CAM entry [16-23] */
1476 sh_eth_tsu_write(mdp, 0, TSU_POST4); /* Disable CAM entry [24-31] */
1478 #endif /* SH_ETH_HAS_TSU */
1480 /* MDIO bus release function */
1481 static int sh_mdio_release(struct net_device *ndev)
1483 struct mii_bus *bus = dev_get_drvdata(&ndev->dev);
1485 /* unregister mdio bus */
1486 mdiobus_unregister(bus);
1488 /* remove mdio bus info from net_device */
1489 dev_set_drvdata(&ndev->dev, NULL);
1491 /* free interrupts memory */
1494 /* free bitbang info */
1495 free_mdio_bitbang(bus);
1500 /* MDIO bus init function */
1501 static int sh_mdio_init(struct net_device *ndev, int id)
1504 struct bb_info *bitbang;
1505 struct sh_eth_private *mdp = netdev_priv(ndev);
1507 /* create bit control struct for PHY */
1508 bitbang = kzalloc(sizeof(struct bb_info), GFP_KERNEL);
1515 bitbang->addr = ndev->base_addr + mdp->reg_offset[PIR];
1516 bitbang->mdi_msk = 0x08;
1517 bitbang->mdo_msk = 0x04;
1518 bitbang->mmd_msk = 0x02;/* MMD */
1519 bitbang->mdc_msk = 0x01;
1520 bitbang->ctrl.ops = &bb_ops;
1522 /* MII controller setting */
1523 mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl);
1524 if (!mdp->mii_bus) {
1526 goto out_free_bitbang;
1529 /* Hook up MII support for ethtool */
1530 mdp->mii_bus->name = "sh_mii";
1531 mdp->mii_bus->parent = &ndev->dev;
1532 snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%x", id);
1535 mdp->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
1536 if (!mdp->mii_bus->irq) {
1541 for (i = 0; i < PHY_MAX_ADDR; i++)
1542 mdp->mii_bus->irq[i] = PHY_POLL;
1544 /* regist mdio bus */
1545 ret = mdiobus_register(mdp->mii_bus);
1549 dev_set_drvdata(&ndev->dev, mdp->mii_bus);
1554 kfree(mdp->mii_bus->irq);
1557 free_mdio_bitbang(mdp->mii_bus);
1566 static const u16 *sh_eth_get_register_offset(int register_type)
1568 const u16 *reg_offset = NULL;
1570 switch (register_type) {
1571 case SH_ETH_REG_GIGABIT:
1572 reg_offset = sh_eth_offset_gigabit;
1574 case SH_ETH_REG_FAST_SH4:
1575 reg_offset = sh_eth_offset_fast_sh4;
1577 case SH_ETH_REG_FAST_SH3_SH2:
1578 reg_offset = sh_eth_offset_fast_sh3_sh2;
1581 printk(KERN_ERR "Unknown register type (%d)\n", register_type);
1588 static const struct net_device_ops sh_eth_netdev_ops = {
1589 .ndo_open = sh_eth_open,
1590 .ndo_stop = sh_eth_close,
1591 .ndo_start_xmit = sh_eth_start_xmit,
1592 .ndo_get_stats = sh_eth_get_stats,
1593 #if defined(SH_ETH_HAS_TSU)
1594 .ndo_set_multicast_list = sh_eth_set_multicast_list,
1596 .ndo_tx_timeout = sh_eth_tx_timeout,
1597 .ndo_do_ioctl = sh_eth_do_ioctl,
1598 .ndo_validate_addr = eth_validate_addr,
1599 .ndo_set_mac_address = eth_mac_addr,
1600 .ndo_change_mtu = eth_change_mtu,
1603 static int sh_eth_drv_probe(struct platform_device *pdev)
1606 struct resource *res;
1607 struct net_device *ndev = NULL;
1608 struct sh_eth_private *mdp;
1609 struct sh_eth_plat_data *pd;
1612 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1613 if (unlikely(res == NULL)) {
1614 dev_err(&pdev->dev, "invalid resource\n");
1619 ndev = alloc_etherdev(sizeof(struct sh_eth_private));
1621 dev_err(&pdev->dev, "Could not allocate device.\n");
1626 /* The sh Ether-specific entries in the device structure. */
1627 ndev->base_addr = res->start;
1633 ret = platform_get_irq(pdev, 0);
1640 SET_NETDEV_DEV(ndev, &pdev->dev);
1642 /* Fill in the fields of the device structure with ethernet values. */
1645 mdp = netdev_priv(ndev);
1646 spin_lock_init(&mdp->lock);
1648 pm_runtime_enable(&pdev->dev);
1649 pm_runtime_resume(&pdev->dev);
1651 pd = (struct sh_eth_plat_data *)(pdev->dev.platform_data);
1653 mdp->phy_id = pd->phy;
1655 mdp->edmac_endian = pd->edmac_endian;
1656 mdp->no_ether_link = pd->no_ether_link;
1657 mdp->ether_link_active_low = pd->ether_link_active_low;
1658 mdp->reg_offset = sh_eth_get_register_offset(pd->register_type);
1661 mdp->cd = &sh_eth_my_cpu_data;
1662 sh_eth_set_default_cpu_data(mdp->cd);
1665 ndev->netdev_ops = &sh_eth_netdev_ops;
1666 SET_ETHTOOL_OPS(ndev, &sh_eth_ethtool_ops);
1667 ndev->watchdog_timeo = TX_TIMEOUT;
1669 /* debug message level */
1670 mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE;
1671 mdp->post_rx = POST_RX >> (devno << 1);
1672 mdp->post_fw = POST_FW >> (devno << 1);
1674 /* read and set MAC address */
1675 read_mac_address(ndev, pd->mac_addr);
1677 /* First device only init */
1679 if (mdp->cd->chip_reset)
1680 mdp->cd->chip_reset(ndev);
1682 #if defined(SH_ETH_HAS_TSU)
1683 /* TSU init (Init only)*/
1684 mdp->tsu_addr = SH_TSU_ADDR;
1685 sh_eth_tsu_init(mdp);
1689 /* network device register */
1690 ret = register_netdev(ndev);
1695 ret = sh_mdio_init(ndev, pdev->id);
1697 goto out_unregister;
1699 /* print device infomation */
1700 pr_info("Base address at 0x%x, %pM, IRQ %d.\n",
1701 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
1703 platform_set_drvdata(pdev, ndev);
1708 unregister_netdev(ndev);
1719 static int sh_eth_drv_remove(struct platform_device *pdev)
1721 struct net_device *ndev = platform_get_drvdata(pdev);
1723 sh_mdio_release(ndev);
1724 unregister_netdev(ndev);
1725 pm_runtime_disable(&pdev->dev);
1727 platform_set_drvdata(pdev, NULL);
1732 static int sh_eth_runtime_nop(struct device *dev)
1735 * Runtime PM callback shared between ->runtime_suspend()
1736 * and ->runtime_resume(). Simply returns success.
1738 * This driver re-initializes all registers after
1739 * pm_runtime_get_sync() anyway so there is no need
1740 * to save and restore registers here.
1745 static struct dev_pm_ops sh_eth_dev_pm_ops = {
1746 .runtime_suspend = sh_eth_runtime_nop,
1747 .runtime_resume = sh_eth_runtime_nop,
1750 static struct platform_driver sh_eth_driver = {
1751 .probe = sh_eth_drv_probe,
1752 .remove = sh_eth_drv_remove,
1755 .pm = &sh_eth_dev_pm_ops,
1759 static int __init sh_eth_init(void)
1761 return platform_driver_register(&sh_eth_driver);
1764 static void __exit sh_eth_cleanup(void)
1766 platform_driver_unregister(&sh_eth_driver);
1769 module_init(sh_eth_init);
1770 module_exit(sh_eth_cleanup);
1772 MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
1773 MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
1774 MODULE_LICENSE("GPL v2");