2 * SuperH Ethernet device driver
4 * Copyright (C) 2006-2008 Nobuhiro Iwamatsu
5 * Copyright (C) 2008 Renesas Solutions Corp.
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
16 * this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 * The full GNU General Public License is included in this distribution in
20 * the file called "COPYING".
26 #include <linux/module.h>
27 #include <linux/kernel.h>
28 #include <linux/spinlock.h>
29 #include <linux/workqueue.h>
30 #include <linux/netdevice.h>
31 #include <linux/phy.h>
33 #define CARDNAME "sh-eth"
34 #define TX_TIMEOUT (5*HZ)
36 #define TX_RING_SIZE 128 /* Tx ring size */
37 #define RX_RING_SIZE 128 /* Rx ring size */
38 #define RX_OFFSET 2 /* skb offset */
40 #define PKT_BUF_SZ 1538
42 /* Chip Base Address */
43 #define SH_ETH0_BASE 0xA7000000
44 #define SH_ETH1_BASE 0xA7000400
45 #define SH_TSU_ADDR 0xA7000804
89 #if defined(CONFIG_CPU_SUBTYPE_SH7710)
94 #endif /* CONFIG_CPU_SH7710 */
99 #define TSU_CTRST 0x004
100 #define TSU_FWEN0 0x010
101 #define TSU_FWEN1 0x014
102 #define TSU_FCM 0x018
103 #define TSU_BSYSL0 0x020
104 #define TSU_BSYSL1 0x024
105 #define TSU_PRISL0 0x028
106 #define TSU_PRISL1 0x02C
107 #define TSU_FWSL0 0x030
108 #define TSU_FWSL1 0x034
109 #define TSU_FWSLC 0x038
110 #define TSU_QTAGM0 0x040
111 #define TSU_QTAGM1 0x044
112 #define TSU_ADQT0 0x048
113 #define TSU_ADQT1 0x04C
114 #define TSU_FWSR 0x050
115 #define TSU_FWINMK 0x054
116 #define TSU_ADSBSY 0x060
117 #define TSU_TEN 0x064
118 #define TSU_POST1 0x070
119 #define TSU_POST2 0x074
120 #define TSU_POST3 0x078
121 #define TSU_POST4 0x07C
122 #define TXNLCR0 0x080
123 #define TXALCR0 0x084
124 #define RXNLCR0 0x088
125 #define RXALCR0 0x08C
126 #define FWNLCR0 0x090
127 #define FWALCR0 0x094
128 #define TXNLCR1 0x0A0
129 #define TXALCR1 0x0A4
130 #define RXNLCR1 0x0A8
131 #define RXALCR1 0x0AC
132 #define FWNLCR1 0x0B0
133 #define FWALCR1 0x0B4
135 #define TSU_ADRH0 0x0100
136 #define TSU_ADRL0 0x0104
137 #define TSU_ADRL31 0x01FC
139 /* Register's bits */
143 EDMR_DL1 = 0x20, EDMR_DL0 = 0x10, EDMR_SRST = 0x01,
158 TPAUSER_TPAUSE = 0x0000ffff,
159 TPAUSER_UNLIMITED = 0,
164 BCFR_RPAUSE = 0x0000ffff,
170 PIR_MDI = 0x08, PIR_MDO = 0x04, PIR_MMD = 0x02, PIR_MDC = 0x01,
174 enum PHY_STATUS_BIT { PHY_ST_LINK = 0x01, };
178 EESR_TWB = 0x40000000, EESR_TABT = 0x04000000,
179 EESR_RABT = 0x02000000, EESR_RFRMER = 0x01000000,
180 EESR_ADE = 0x00800000, EESR_ECI = 0x00400000,
181 EESR_FTC = 0x00200000, EESR_TDE = 0x00100000,
182 EESR_TFE = 0x00080000, EESR_FRC = 0x00040000,
183 EESR_RDE = 0x00020000, EESR_RFE = 0x00010000,
184 EESR_TINT4 = 0x00000800, EESR_TINT3 = 0x00000400,
185 EESR_TINT2 = 0x00000200, EESR_TINT1 = 0x00000100,
186 EESR_RINT8 = 0x00000080, EESR_RINT5 = 0x00000010,
187 EESR_RINT4 = 0x00000008, EESR_RINT3 = 0x00000004,
188 EESR_RINT2 = 0x00000002, EESR_RINT1 = 0x00000001,
191 #define EESR_ERR_CHECK (EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE \
192 | EESR_RFRMER | EESR_ADE | EESR_TFE | EESR_TDE | EESR_ECI)
196 DMAC_M_TWB = 0x40000000, DMAC_M_TABT = 0x04000000,
197 DMAC_M_RABT = 0x02000000,
198 DMAC_M_RFRMER = 0x01000000, DMAC_M_ADF = 0x00800000,
199 DMAC_M_ECI = 0x00400000, DMAC_M_FTC = 0x00200000,
200 DMAC_M_TDE = 0x00100000, DMAC_M_TFE = 0x00080000,
201 DMAC_M_FRC = 0x00040000, DMAC_M_RDE = 0x00020000,
202 DMAC_M_RFE = 0x00010000, DMAC_M_TINT4 = 0x00000800,
203 DMAC_M_TINT3 = 0x00000400, DMAC_M_TINT2 = 0x00000200,
204 DMAC_M_TINT1 = 0x00000100, DMAC_M_RINT8 = 0x00000080,
205 DMAC_M_RINT5 = 0x00000010, DMAC_M_RINT4 = 0x00000008,
206 DMAC_M_RINT3 = 0x00000004, DMAC_M_RINT2 = 0x00000002,
207 DMAC_M_RINT1 = 0x00000001,
210 /* Receive descriptor bit */
212 RD_RACT = 0x80000000, RC_RDEL = 0x40000000,
213 RC_RFP1 = 0x20000000, RC_RFP0 = 0x10000000,
214 RD_RFE = 0x08000000, RD_RFS10 = 0x00000200,
215 RD_RFS9 = 0x00000100, RD_RFS8 = 0x00000080,
216 RD_RFS7 = 0x00000040, RD_RFS6 = 0x00000020,
217 RD_RFS5 = 0x00000010, RD_RFS4 = 0x00000008,
218 RD_RFS3 = 0x00000004, RD_RFS2 = 0x00000002,
219 RD_RFS1 = 0x00000001,
221 #define RDF1ST RC_RFP1
222 #define RDFEND RC_RFP0
223 #define RD_RFP (RC_RFP1|RC_RFP0)
227 FCFTR_RFF2 = 0x00040000, FCFTR_RFF1 = 0x00020000,
228 FCFTR_RFF0 = 0x00010000, FCFTR_RFD2 = 0x00000004,
229 FCFTR_RFD1 = 0x00000002, FCFTR_RFD0 = 0x00000001,
231 #define FIFO_F_D_RFF (FCFTR_RFF2|FCFTR_RFF1|FCFTR_RFF0)
232 #define FIFO_F_D_RFD (FCFTR_RFD2|FCFTR_RFD1|FCFTR_RFD0)
234 /* Transfer descriptor bit */
236 TD_TACT = 0x80000000, TD_TDLE = 0x40000000, TD_TFP1 = 0x20000000,
237 TD_TFP0 = 0x10000000,
239 #define TDF1ST TD_TFP1
240 #define TDFEND TD_TFP0
241 #define TD_TFP (TD_TFP1|TD_TFP0)
244 enum RECV_RST_BIT { RMCR_RST = 0x01, };
246 enum FELIC_MODE_BIT {
247 ECMR_ZPF = 0x00080000, ECMR_PFR = 0x00040000, ECMR_RXF = 0x00020000,
248 ECMR_TXF = 0x00010000, ECMR_MCT = 0x00002000, ECMR_PRCEF = 0x00001000,
249 ECMR_PMDE = 0x00000200, ECMR_RE = 0x00000040, ECMR_TE = 0x00000020,
250 ECMR_ILB = 0x00000008, ECMR_ELB = 0x00000004, ECMR_DM = 0x00000002,
251 ECMR_PRM = 0x00000001,
255 enum ECSR_STATUS_BIT {
256 ECSR_BRCRX = 0x20, ECSR_PSRTO = 0x10, ECSR_LCHNG = 0x04,
257 ECSR_MPD = 0x02, ECSR_ICD = 0x01,
261 enum ECSIPR_STATUS_MASK_BIT {
262 ECSIPR_BRCRXIP = 0x20, ECSIPR_PSRTOIP = 0x10, ECSIPR_LCHNGIP = 0x04,
263 ECSIPR_MPDIP = 0x02, ECSIPR_ICDIP = 0x01,
278 DESC_I_TINT4 = 0x0800, DESC_I_TINT3 = 0x0400, DESC_I_TINT2 = 0x0200,
279 DESC_I_TINT1 = 0x0100, DESC_I_RINT8 = 0x0080, DESC_I_RINT5 = 0x0010,
280 DESC_I_RINT4 = 0x0008, DESC_I_RINT3 = 0x0004, DESC_I_RINT2 = 0x0002,
281 DESC_I_RINT1 = 0x0001,
286 RPADIR_PADS1 = 0x20000, RPADIR_PADS0 = 0x10000,
287 RPADIR_PADR = 0x0003f,
292 FIFO_SIZE_T = 0x00000700, FIFO_SIZE_R = 0x00000007,
295 PHY_CTRL = 0, PHY_STAT = 1, PHY_IDT1 = 2, PHY_IDT2 = 3,
296 PHY_ANA = 4, PHY_ANL = 5, PHY_ANE = 6,
302 PHY_C_RESET = 0x8000, PHY_C_LOOPBK = 0x4000, PHY_C_SPEEDSL = 0x2000,
303 PHY_C_ANEGEN = 0x1000, PHY_C_PWRDN = 0x0800, PHY_C_ISO = 0x0400,
304 PHY_C_RANEG = 0x0200, PHY_C_DUPLEX = 0x0100, PHY_C_COLT = 0x0080,
306 #define DM9161_PHY_C_ANEGEN 0 /* auto nego special */
310 PHY_S_100T4 = 0x8000, PHY_S_100X_F = 0x4000, PHY_S_100X_H = 0x2000,
311 PHY_S_10T_F = 0x1000, PHY_S_10T_H = 0x0800, PHY_S_ANEGC = 0x0020,
312 PHY_S_RFAULT = 0x0010, PHY_S_ANEGA = 0x0008, PHY_S_LINK = 0x0004,
313 PHY_S_JAB = 0x0002, PHY_S_EXTD = 0x0001,
318 PHY_A_NP = 0x8000, PHY_A_ACK = 0x4000, PHY_A_RF = 0x2000,
319 PHY_A_FCS = 0x0400, PHY_A_T4 = 0x0200, PHY_A_FDX = 0x0100,
320 PHY_A_HDX = 0x0080, PHY_A_10FDX = 0x0040, PHY_A_10HDX = 0x0020,
325 PHY_L_NP = 0x8000, PHY_L_ACK = 0x4000, PHY_L_RF = 0x2000,
326 PHY_L_FCS = 0x0400, PHY_L_T4 = 0x0200, PHY_L_FDX = 0x0100,
327 PHY_L_HDX = 0x0080, PHY_L_10FDX = 0x0040, PHY_L_10HDX = 0x0020,
333 PHY_E_PDF = 0x0010, PHY_E_LPNPA = 0x0008, PHY_E_NPA = 0x0004,
334 PHY_E_PRX = 0x0002, PHY_E_LPANEGA = 0x0001,
339 PHY_16_BP4B45 = 0x8000, PHY_16_BPSCR = 0x4000, PHY_16_BPALIGN = 0x2000,
340 PHY_16_BP_ADPOK = 0x1000, PHY_16_Repeatmode = 0x0800,
341 PHY_16_TXselect = 0x0400,
342 PHY_16_Rsvd = 0x0200, PHY_16_RMIIEnable = 0x0100,
343 PHY_16_Force100LNK = 0x0080,
344 PHY_16_APDLED_CTL = 0x0040, PHY_16_COLLED_CTL = 0x0020,
345 PHY_16_RPDCTR_EN = 0x0010,
346 PHY_16_ResetStMch = 0x0008, PHY_16_PreamSupr = 0x0004,
347 PHY_16_Sleepmode = 0x0002,
348 PHY_16_RemoteLoopOut = 0x0001,
353 #define POST0_RX (POST_RX)
354 #define POST0_FW (POST_FW)
355 #define POST1_RX (POST_RX >> 2)
356 #define POST1_FW (POST_FW >> 2)
357 #define POST_ALL (POST0_RX | POST0_FW | POST1_RX | POST1_FW)
360 enum ARSTR_BIT { ARSTR_ARSTR = 0x00000001, };
364 TSU_FWEN0_0 = 0x00000001,
368 enum TSU_ADSBSY_BIT {
369 TSU_ADSBSY_0 = 0x00000001,
374 TSU_TEN_0 = 0x80000000,
379 TSU_FWSL0_FW50 = 0x1000, TSU_FWSL0_FW40 = 0x0800,
380 TSU_FWSL0_FW30 = 0x0400, TSU_FWSL0_FW20 = 0x0200,
381 TSU_FWSL0_FW10 = 0x0100, TSU_FWSL0_RMSA0 = 0x0010,
386 TSU_FWSLC_POSTENU = 0x2000, TSU_FWSLC_POSTENL = 0x1000,
387 TSU_FWSLC_CAMSEL03 = 0x0080, TSU_FWSLC_CAMSEL02 = 0x0040,
388 TSU_FWSLC_CAMSEL01 = 0x0020, TSU_FWSLC_CAMSEL00 = 0x0010,
389 TSU_FWSLC_CAMSEL13 = 0x0008, TSU_FWSLC_CAMSEL12 = 0x0004,
390 TSU_FWSLC_CAMSEL11 = 0x0002, TSU_FWSLC_CAMSEL10 = 0x0001,
394 * The sh ether Tx buffer descriptors.
395 * This structure should be 20 bytes.
397 struct sh_eth_txdesc {
398 u32 status; /* TD0 */
399 #if defined(CONFIG_CPU_LITTLE_ENDIAN)
401 u16 buffer_length; /* TD1 */
403 u16 buffer_length; /* TD1 */
407 u32 pad1; /* padding data */
411 * The sh ether Rx buffer descriptors.
412 * This structure should be 20 bytes.
414 struct sh_eth_rxdesc {
415 u32 status; /* RD0 */
416 #if defined(CONFIG_CPU_LITTLE_ENDIAN)
417 u16 frame_length; /* RD1 */
418 u16 buffer_length; /* RD1 */
420 u16 buffer_length; /* RD1 */
421 u16 frame_length; /* RD1 */
424 u32 pad0; /* padding data */
427 struct sh_eth_private {
428 dma_addr_t rx_desc_dma;
429 dma_addr_t tx_desc_dma;
430 struct sh_eth_rxdesc *rx_ring;
431 struct sh_eth_txdesc *tx_ring;
432 struct sk_buff **rx_skbuff;
433 struct sk_buff **tx_skbuff;
434 struct net_device_stats stats;
435 struct timer_list timer;
437 u32 cur_rx, dirty_rx; /* Producer/consumer ring indices */
438 u32 cur_tx, dirty_tx;
439 u32 rx_buf_sz; /* Based on MTU+slack. */
440 /* MII transceiver section. */
441 u32 phy_id; /* PHY ID */
442 struct mii_bus *mii_bus; /* MDIO bus control */
443 struct phy_device *phydev; /* PHY device control */
448 u32 rx_int_var, tx_int_var; /* interrupt control variables */
449 char post_rx; /* POST receive */
450 char post_fw; /* POST forward */
451 struct net_device_stats tsu_stats; /* TSU forward status */
454 static void swaps(char *src, int len)
456 #ifdef __LITTLE_ENDIAN__
459 maxp = p + ((len + sizeof(u32) - 1) / sizeof(u32));
461 for (; p < maxp; p++)