drivers/net/sh_eth.h

   1 /*
   2  *  SuperH Ethernet device driver
   3  *
   4  *  Copyright (C) 2006-2008 Nobuhiro Iwamatsu
   5  *  Copyright (C) 2008-2011 Renesas Solutions Corp.
   6  *
   7  *  This program is free software; you can redistribute it and/or modify it
   8  *  under the terms and conditions of the GNU General Public License,
   9  *  version 2, as published by the Free Software Foundation.
  10  *
  11  *  This program is distributed in the hope it will be useful, but WITHOUT
  12  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14  *  more details.
  15  *  You should have received a copy of the GNU General Public License along with
  16  *  this program; if not, write to the Free Software Foundation, Inc.,
  17  *  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  *  The full GNU General Public License is included in this distribution in
  20  *  the file called "COPYING".
  21  */
  22
  23 #ifndef __SH_ETH_H__
  24 #define __SH_ETH_H__
  25
  26 #include <linux/module.h>
  27 #include <linux/kernel.h>
  28 #include <linux/spinlock.h>
  29 #include <linux/netdevice.h>
  30 #include <linux/phy.h>
  31
  32 #include <asm/sh_eth.h>
  33
  34 #define CARDNAME        "sh-eth"
  35 #define TX_TIMEOUT      (5*HZ)
  36 #define TX_RING_SIZE    64      /* Tx ring size */
  37 #define RX_RING_SIZE    64      /* Rx ring size */
  38 #define ETHERSMALL              60
  39 #define PKT_BUF_SZ              1538
  40
  41 enum {
  42         /* E-DMAC registers */
  43         EDSR = 0,
  44         EDMR,
  45         EDTRR,
  46         EDRRR,
  47         EESR,
  48         EESIPR,
  49         TDLAR,
  50         TDFAR,
  51         TDFXR,
  52         TDFFR,
  53         RDLAR,
  54         RDFAR,
  55         RDFXR,
  56         RDFFR,
  57         TRSCER,
  58         RMFCR,
  59         TFTR,
  60         FDR,
  61         RMCR,
  62         EDOCR,
  63         TFUCR,
  64         RFOCR,
  65         FCFTR,
  66         RPADIR,
  67         TRIMD,
  68         RBWAR,
  69         TBRAR,
  70
  71         /* Ether registers */
  72         ECMR,
  73         ECSR,
  74         ECSIPR,
  75         PIR,
  76         PSR,
  77         RDMLR,
  78         PIPR,
  79         RFLR,
  80         IPGR,
  81         APR,
  82         MPR,
  83         PFTCR,
  84         PFRCR,
  85         RFCR,
  86         RFCF,
  87         TPAUSER,
  88         TPAUSECR,
  89         BCFR,
  90         BCFRR,
  91         GECMR,
  92         BCULR,
  93         MAHR,
  94         MALR,
  95         TROCR,
  96         CDCR,
  97         LCCR,
  98         CNDCR,
  99         CEFCR,
 100         FRECR,
 101         TSFRCR,
 102         TLFRCR,
 103         CERCR,
 104         CEECR,
 105         MAFCR,
 106         RTRATE,
 107
 108         /* TSU Absolute address */
 109         ARSTR,
 110         TSU_CTRST,
 111         TSU_FWEN0,
 112         TSU_FWEN1,
 113         TSU_FCM,
 114         TSU_BSYSL0,
 115         TSU_BSYSL1,
 116         TSU_PRISL0,
 117         TSU_PRISL1,
 118         TSU_FWSL0,
 119         TSU_FWSL1,
 120         TSU_FWSLC,
 121         TSU_QTAG0,
 122         TSU_QTAG1,
 123         TSU_QTAGM0,
 124         TSU_QTAGM1,
 125         TSU_FWSR,
 126         TSU_FWINMK,
 127         TSU_ADQT0,
 128         TSU_ADQT1,
 129         TSU_VTAG0,
 130         TSU_VTAG1,
 131         TSU_ADSBSY,
 132         TSU_TEN,
 133         TSU_POST1,
 134         TSU_POST2,
 135         TSU_POST3,
 136         TSU_POST4,
 137         TSU_ADRH0,
 138         TSU_ADRL0,
 139         TSU_ADRH31,
 140         TSU_ADRL31,
 141
 142         TXNLCR0,
 143         TXALCR0,
 144         RXNLCR0,
 145         RXALCR0,
 146         FWNLCR0,
 147         FWALCR0,
 148         TXNLCR1,
 149         TXALCR1,
 150         RXNLCR1,
 151         RXALCR1,
 152         FWNLCR1,
 153         FWALCR1,
 154
 155         /* This value must be written at last. */
 156         SH_ETH_MAX_REGISTER_OFFSET,
 157 };
 158
 159 static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
 160         [EDSR]  = 0x0000,
 161         [EDMR]  = 0x0400,
 162         [EDTRR] = 0x0408,
 163         [EDRRR] = 0x0410,
 164         [EESR]  = 0x0428,
 165         [EESIPR]        = 0x0430,
 166         [TDLAR] = 0x0010,
 167         [TDFAR] = 0x0014,
 168         [TDFXR] = 0x0018,
 169         [TDFFR] = 0x001c,
 170         [RDLAR] = 0x0030,
 171         [RDFAR] = 0x0034,
 172         [RDFXR] = 0x0038,
 173         [RDFFR] = 0x003c,
 174         [TRSCER]        = 0x0438,
 175         [RMFCR] = 0x0440,
 176         [TFTR]  = 0x0448,
 177         [FDR]   = 0x0450,
 178         [RMCR]  = 0x0458,
 179         [RPADIR]        = 0x0460,
 180         [FCFTR] = 0x0468,
 181
 182         [ECMR]  = 0x0500,
 183         [ECSR]  = 0x0510,
 184         [ECSIPR]        = 0x0518,
 185         [PIR]   = 0x0520,
 186         [PSR]   = 0x0528,
 187         [PIPR]  = 0x052c,
 188         [RFLR]  = 0x0508,
 189         [APR]   = 0x0554,
 190         [MPR]   = 0x0558,
 191         [PFTCR] = 0x055c,
 192         [PFRCR] = 0x0560,
 193         [TPAUSER]       = 0x0564,
 194         [GECMR] = 0x05b0,
 195         [BCULR] = 0x05b4,
 196         [MAHR]  = 0x05c0,
 197         [MALR]  = 0x05c8,
 198         [TROCR] = 0x0700,
 199         [CDCR]  = 0x0708,
 200         [LCCR]  = 0x0710,
 201         [CEFCR] = 0x0740,
 202         [FRECR] = 0x0748,
 203         [TSFRCR]        = 0x0750,
 204         [TLFRCR]        = 0x0758,
 205         [RFCR]  = 0x0760,
 206         [CERCR] = 0x0768,
 207         [CEECR] = 0x0770,
 208         [MAFCR] = 0x0778,
 209
 210         [TSU_CTRST]     = 0x0004,
 211         [TSU_FWEN0]     = 0x0010,
 212         [TSU_FWEN1]     = 0x0014,
 213         [TSU_FCM]       = 0x0018,
 214         [TSU_BSYSL0]    = 0x0020,
 215         [TSU_BSYSL1]    = 0x0024,
 216         [TSU_PRISL0]    = 0x0028,
 217         [TSU_PRISL1]    = 0x002c,
 218         [TSU_FWSL0]     = 0x0030,
 219         [TSU_FWSL1]     = 0x0034,
 220         [TSU_FWSLC]     = 0x0038,
 221         [TSU_QTAG0]     = 0x0040,
 222         [TSU_QTAG1]     = 0x0044,
 223         [TSU_FWSR]      = 0x0050,
 224         [TSU_FWINMK]    = 0x0054,
 225         [TSU_ADQT0]     = 0x0048,
 226         [TSU_ADQT1]     = 0x004c,
 227         [TSU_VTAG0]     = 0x0058,
 228         [TSU_VTAG1]     = 0x005c,
 229         [TSU_ADSBSY]    = 0x0060,
 230         [TSU_TEN]       = 0x0064,
 231         [TSU_POST1]     = 0x0070,
 232         [TSU_POST2]     = 0x0074,
 233         [TSU_POST3]     = 0x0078,
 234         [TSU_POST4]     = 0x007c,
 235         [TSU_ADRH0]     = 0x0100,
 236         [TSU_ADRL0]     = 0x0104,
 237         [TSU_ADRH31]    = 0x01f8,
 238         [TSU_ADRL31]    = 0x01fc,
 239
 240         [TXNLCR0]       = 0x0080,
 241         [TXALCR0]       = 0x0084,
 242         [RXNLCR0]       = 0x0088,
 243         [RXALCR0]       = 0x008c,
 244         [FWNLCR0]       = 0x0090,
 245         [FWALCR0]       = 0x0094,
 246         [TXNLCR1]       = 0x00a0,
 247         [TXALCR1]       = 0x00a0,
 248         [RXNLCR1]       = 0x00a8,
 249         [RXALCR1]       = 0x00ac,
 250         [FWNLCR1]       = 0x00b0,
 251         [FWALCR1]       = 0x00b4,
 252 };
 253
 254 static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
 255         [ECMR]  = 0x0100,
 256         [RFLR]  = 0x0108,
 257         [ECSR]  = 0x0110,
 258         [ECSIPR]        = 0x0118,
 259         [PIR]   = 0x0120,
 260         [PSR]   = 0x0128,
 261         [RDMLR] = 0x0140,
 262         [IPGR]  = 0x0150,
 263         [APR]   = 0x0154,
 264         [MPR]   = 0x0158,
 265         [TPAUSER]       = 0x0164,
 266         [RFCF]  = 0x0160,
 267         [TPAUSECR]      = 0x0168,
 268         [BCFRR] = 0x016c,
 269         [MAHR]  = 0x01c0,
 270         [MALR]  = 0x01c8,
 271         [TROCR] = 0x01d0,
 272         [CDCR]  = 0x01d4,
 273         [LCCR]  = 0x01d8,
 274         [CNDCR] = 0x01dc,
 275         [CEFCR] = 0x01e4,
 276         [FRECR] = 0x01e8,
 277         [TSFRCR]        = 0x01ec,
 278         [TLFRCR]        = 0x01f0,
 279         [RFCR]  = 0x01f4,
 280         [MAFCR] = 0x01f8,
 281         [RTRATE]        = 0x01fc,
 282
 283         [EDMR]  = 0x0000,
 284         [EDTRR] = 0x0008,
 285         [EDRRR] = 0x0010,
 286         [TDLAR] = 0x0018,
 287         [RDLAR] = 0x0020,
 288         [EESR]  = 0x0028,
 289         [EESIPR]        = 0x0030,
 290         [TRSCER]        = 0x0038,
 291         [RMFCR] = 0x0040,
 292         [TFTR]  = 0x0048,
 293         [FDR]   = 0x0050,
 294         [RMCR]  = 0x0058,
 295         [TFUCR] = 0x0064,
 296         [RFOCR] = 0x0068,
 297         [FCFTR] = 0x0070,
 298         [RPADIR]        = 0x0078,
 299         [TRIMD] = 0x007c,
 300         [RBWAR] = 0x00c8,
 301         [RDFAR] = 0x00cc,
 302         [TBRAR] = 0x00d4,
 303         [TDFAR] = 0x00d8,
 304 };
 305
 306 static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = {
 307         [ECMR]  = 0x0160,
 308         [ECSR]  = 0x0164,
 309         [ECSIPR]        = 0x0168,
 310         [PIR]   = 0x016c,
 311         [MAHR]  = 0x0170,
 312         [MALR]  = 0x0174,
 313         [RFLR]  = 0x0178,
 314         [PSR]   = 0x017c,
 315         [TROCR] = 0x0180,
 316         [CDCR]  = 0x0184,
 317         [LCCR]  = 0x0188,
 318         [CNDCR] = 0x018c,
 319         [CEFCR] = 0x0194,
 320         [FRECR] = 0x0198,
 321         [TSFRCR]        = 0x019c,
 322         [TLFRCR]        = 0x01a0,
 323         [RFCR]  = 0x01a4,
 324         [MAFCR] = 0x01a8,
 325         [IPGR]  = 0x01b4,
 326         [APR]   = 0x01b8,
 327         [MPR]   = 0x01bc,
 328         [TPAUSER]       = 0x01c4,
 329         [BCFR]  = 0x01cc,
 330
 331         [TSU_CTRST]     = 0x0004,
 332         [TSU_FWEN0]     = 0x0010,
 333         [TSU_FWEN1]     = 0x0014,
 334         [TSU_FCM]       = 0x0018,
 335         [TSU_BSYSL0]    = 0x0020,
 336         [TSU_BSYSL1]    = 0x0024,
 337         [TSU_PRISL0]    = 0x0028,
 338         [TSU_PRISL1]    = 0x002c,
 339         [TSU_FWSL0]     = 0x0030,
 340         [TSU_FWSL1]     = 0x0034,
 341         [TSU_FWSLC]     = 0x0038,
 342         [TSU_QTAGM0]    = 0x0040,
 343         [TSU_QTAGM1]    = 0x0044,
 344         [TSU_ADQT0]     = 0x0048,
 345         [TSU_ADQT1]     = 0x004c,
 346         [TSU_FWSR]      = 0x0050,
 347         [TSU_FWINMK]    = 0x0054,
 348         [TSU_ADSBSY]    = 0x0060,
 349         [TSU_TEN]       = 0x0064,
 350         [TSU_POST1]     = 0x0070,
 351         [TSU_POST2]     = 0x0074,
 352         [TSU_POST3]     = 0x0078,
 353         [TSU_POST4]     = 0x007c,
 354
 355         [TXNLCR0]       = 0x0080,
 356         [TXALCR0]       = 0x0084,
 357         [RXNLCR0]       = 0x0088,
 358         [RXALCR0]       = 0x008c,
 359         [FWNLCR0]       = 0x0090,
 360         [FWALCR0]       = 0x0094,
 361         [TXNLCR1]       = 0x00a0,
 362         [TXALCR1]       = 0x00a0,
 363         [RXNLCR1]       = 0x00a8,
 364         [RXALCR1]       = 0x00ac,
 365         [FWNLCR1]       = 0x00b0,
 366         [FWALCR1]       = 0x00b4,
 367
 368         [TSU_ADRH0]     = 0x0100,
 369         [TSU_ADRL0]     = 0x0104,
 370         [TSU_ADRL31]    = 0x01fc,
 371
 372 };
 373
 374 #if defined(CONFIG_CPU_SUBTYPE_SH7763)
 375 /* This CPU register maps is very difference by other SH4 CPU */
 376 /* Chip Base Address */
 377 # define SH_TSU_ADDR    0xFEE01800
 378 # define ARSTR          SH_TSU_ADDR
 379 #elif defined(CONFIG_CPU_SH4)   /* #if defined(CONFIG_CPU_SUBTYPE_SH7763) */
 380 #else /* #elif defined(CONFIG_CPU_SH4) */
 381 /* This section is SH3 or SH2 */
 382 #ifndef CONFIG_CPU_SUBTYPE_SH7619
 383 /* Chip base address */
 384 # define SH_TSU_ADDR  0xA7000804
 385 # define ARSTR            0xA7000800
 386 #endif
 387 #endif /* CONFIG_CPU_SUBTYPE_SH7763 */
 388
 389 /* Driver's parameters */
 390 #if defined(CONFIG_CPU_SH4)
 391 #define SH4_SKB_RX_ALIGN        32
 392 #else
 393 #define SH2_SH3_SKB_RX_ALIGN    2
 394 #endif
 395
 396 /*
 397  * Register's bits
 398  */
 399 #ifdef CONFIG_CPU_SUBTYPE_SH7763
 400 /* EDSR */
 401 enum EDSR_BIT {
 402         EDSR_ENT = 0x01, EDSR_ENR = 0x02,
 403 };
 404 #define EDSR_ENALL (EDSR_ENT|EDSR_ENR)
 405
 406 /* GECMR */
 407 enum GECMR_BIT {
 408         GECMR_10 = 0x0, GECMR_100 = 0x04, GECMR_1000 = 0x01,
 409 };
 410 #endif
 411
 412 /* EDMR */
 413 enum DMAC_M_BIT {
 414         EDMR_EL = 0x40, /* Litte endian */
 415         EDMR_DL1 = 0x20, EDMR_DL0 = 0x10,
 416 #ifdef CONFIG_CPU_SUBTYPE_SH7763
 417         EDMR_SRST = 0x03,
 418 #else /* CONFIG_CPU_SUBTYPE_SH7763 */
 419         EDMR_SRST = 0x01,
 420 #endif
 421 };
 422
 423 /* EDTRR */
 424 enum DMAC_T_BIT {
 425 #ifdef CONFIG_CPU_SUBTYPE_SH7763
 426         EDTRR_TRNS = 0x03,
 427 #else
 428         EDTRR_TRNS = 0x01,
 429 #endif
 430 };
 431
 432 /* EDRRR*/
 433 enum EDRRR_R_BIT {
 434         EDRRR_R = 0x01,
 435 };
 436
 437 /* TPAUSER */
 438 enum TPAUSER_BIT {
 439         TPAUSER_TPAUSE = 0x0000ffff,
 440         TPAUSER_UNLIMITED = 0,
 441 };
 442
 443 /* BCFR */
 444 enum BCFR_BIT {
 445         BCFR_RPAUSE = 0x0000ffff,
 446         BCFR_UNLIMITED = 0,
 447 };
 448
 449 /* PIR */
 450 enum PIR_BIT {
 451         PIR_MDI = 0x08, PIR_MDO = 0x04, PIR_MMD = 0x02, PIR_MDC = 0x01,
 452 };
 453
 454 /* PSR */
 455 enum PHY_STATUS_BIT { PHY_ST_LINK = 0x01, };
 456
 457 /* EESR */
 458 enum EESR_BIT {
 459         EESR_TWB1       = 0x80000000,
 460         EESR_TWB        = 0x40000000,   /* same as TWB0 */
 461         EESR_TC1        = 0x20000000,
 462         EESR_TUC        = 0x10000000,
 463         EESR_ROC        = 0x08000000,
 464         EESR_TABT       = 0x04000000,
 465         EESR_RABT       = 0x02000000,
 466         EESR_RFRMER     = 0x01000000,   /* same as RFCOF */
 467         EESR_ADE        = 0x00800000,
 468         EESR_ECI        = 0x00400000,
 469         EESR_FTC        = 0x00200000,   /* same as TC or TC0 */
 470         EESR_TDE        = 0x00100000,
 471         EESR_TFE        = 0x00080000,   /* same as TFUF */
 472         EESR_FRC        = 0x00040000,   /* same as FR */
 473         EESR_RDE        = 0x00020000,
 474         EESR_RFE        = 0x00010000,
 475         EESR_CND        = 0x00000800,
 476         EESR_DLC        = 0x00000400,
 477         EESR_CD         = 0x00000200,
 478         EESR_RTO        = 0x00000100,
 479         EESR_RMAF       = 0x00000080,
 480         EESR_CEEF       = 0x00000040,
 481         EESR_CELF       = 0x00000020,
 482         EESR_RRF        = 0x00000010,
 483         EESR_RTLF       = 0x00000008,
 484         EESR_RTSF       = 0x00000004,
 485         EESR_PRE        = 0x00000002,
 486         EESR_CERF       = 0x00000001,
 487 };
 488
 489 #define DEFAULT_TX_CHECK        (EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | \
 490                                  EESR_RTO)
 491 #define DEFAULT_EESR_ERR_CHECK  (EESR_TWB | EESR_TABT | EESR_RABT | \
 492                                  EESR_RDE | EESR_RFRMER | EESR_ADE | \
 493                                  EESR_TFE | EESR_TDE | EESR_ECI)
 494 #define DEFAULT_TX_ERROR_CHECK  (EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | \
 495                                  EESR_TFE)
 496
 497 /* EESIPR */
 498 enum DMAC_IM_BIT {
 499         DMAC_M_TWB = 0x40000000, DMAC_M_TABT = 0x04000000,
 500         DMAC_M_RABT = 0x02000000,
 501         DMAC_M_RFRMER = 0x01000000, DMAC_M_ADF = 0x00800000,
 502         DMAC_M_ECI = 0x00400000, DMAC_M_FTC = 0x00200000,
 503         DMAC_M_TDE = 0x00100000, DMAC_M_TFE = 0x00080000,
 504         DMAC_M_FRC = 0x00040000, DMAC_M_RDE = 0x00020000,
 505         DMAC_M_RFE = 0x00010000, DMAC_M_TINT4 = 0x00000800,
 506         DMAC_M_TINT3 = 0x00000400, DMAC_M_TINT2 = 0x00000200,
 507         DMAC_M_TINT1 = 0x00000100, DMAC_M_RINT8 = 0x00000080,
 508         DMAC_M_RINT5 = 0x00000010, DMAC_M_RINT4 = 0x00000008,
 509         DMAC_M_RINT3 = 0x00000004, DMAC_M_RINT2 = 0x00000002,
 510         DMAC_M_RINT1 = 0x00000001,
 511 };
 512
 513 /* Receive descriptor bit */
 514 enum RD_STS_BIT {
 515         RD_RACT = 0x80000000, RD_RDEL = 0x40000000,
 516         RD_RFP1 = 0x20000000, RD_RFP0 = 0x10000000,
 517         RD_RFE = 0x08000000, RD_RFS10 = 0x00000200,
 518         RD_RFS9 = 0x00000100, RD_RFS8 = 0x00000080,
 519         RD_RFS7 = 0x00000040, RD_RFS6 = 0x00000020,
 520         RD_RFS5 = 0x00000010, RD_RFS4 = 0x00000008,
 521         RD_RFS3 = 0x00000004, RD_RFS2 = 0x00000002,
 522         RD_RFS1 = 0x00000001,
 523 };
 524 #define RDF1ST  RD_RFP1
 525 #define RDFEND  RD_RFP0
 526 #define RD_RFP  (RD_RFP1|RD_RFP0)
 527
 528 /* FCFTR */
 529 enum FCFTR_BIT {
 530         FCFTR_RFF2 = 0x00040000, FCFTR_RFF1 = 0x00020000,
 531         FCFTR_RFF0 = 0x00010000, FCFTR_RFD2 = 0x00000004,
 532         FCFTR_RFD1 = 0x00000002, FCFTR_RFD0 = 0x00000001,
 533 };
 534 #define DEFAULT_FIFO_F_D_RFF    (FCFTR_RFF2 | FCFTR_RFF1 | FCFTR_RFF0)
 535 #define DEFAULT_FIFO_F_D_RFD    (FCFTR_RFD2 | FCFTR_RFD1 | FCFTR_RFD0)
 536
 537 /* Transfer descriptor bit */
 538 enum TD_STS_BIT {
 539         TD_TACT = 0x80000000,
 540         TD_TDLE = 0x40000000, TD_TFP1 = 0x20000000,
 541         TD_TFP0 = 0x10000000,
 542 };
 543 #define TDF1ST  TD_TFP1
 544 #define TDFEND  TD_TFP0
 545 #define TD_TFP  (TD_TFP1|TD_TFP0)
 546
 547 /* RMCR */
 548 #define DEFAULT_RMCR_VALUE      0x00000000
 549
 550 /* ECMR */
 551 enum FELIC_MODE_BIT {
 552         ECMR_TRCCM = 0x04000000, ECMR_RCSC = 0x00800000,
 553         ECMR_DPAD = 0x00200000, ECMR_RZPF = 0x00100000,
 554         ECMR_ZPF = 0x00080000, ECMR_PFR = 0x00040000, ECMR_RXF = 0x00020000,
 555         ECMR_TXF = 0x00010000, ECMR_MCT = 0x00002000, ECMR_PRCEF = 0x00001000,
 556         ECMR_PMDE = 0x00000200, ECMR_RE = 0x00000040, ECMR_TE = 0x00000020,
 557         ECMR_RTM = 0x00000010, ECMR_ILB = 0x00000008, ECMR_ELB = 0x00000004,
 558         ECMR_DM = 0x00000002, ECMR_PRM = 0x00000001,
 559 };
 560
 561 /* ECSR */
 562 enum ECSR_STATUS_BIT {
 563         ECSR_BRCRX = 0x20, ECSR_PSRTO = 0x10,
 564         ECSR_LCHNG = 0x04,
 565         ECSR_MPD = 0x02, ECSR_ICD = 0x01,
 566 };
 567
 568 #define DEFAULT_ECSR_INIT       (ECSR_BRCRX | ECSR_PSRTO | ECSR_LCHNG | \
 569                                  ECSR_ICD | ECSIPR_MPDIP)
 570
 571 /* ECSIPR */
 572 enum ECSIPR_STATUS_MASK_BIT {
 573         ECSIPR_BRCRXIP = 0x20, ECSIPR_PSRTOIP = 0x10,
 574         ECSIPR_LCHNGIP = 0x04,
 575         ECSIPR_MPDIP = 0x02, ECSIPR_ICDIP = 0x01,
 576 };
 577
 578 #define DEFAULT_ECSIPR_INIT     (ECSIPR_BRCRXIP | ECSIPR_PSRTOIP | \
 579                                  ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP)
 580
 581 /* APR */
 582 enum APR_BIT {
 583         APR_AP = 0x00000001,
 584 };
 585
 586 /* MPR */
 587 enum MPR_BIT {
 588         MPR_MP = 0x00000001,
 589 };
 590
 591 /* TRSCER */
 592 enum DESC_I_BIT {
 593         DESC_I_TINT4 = 0x0800, DESC_I_TINT3 = 0x0400, DESC_I_TINT2 = 0x0200,
 594         DESC_I_TINT1 = 0x0100, DESC_I_RINT8 = 0x0080, DESC_I_RINT5 = 0x0010,
 595         DESC_I_RINT4 = 0x0008, DESC_I_RINT3 = 0x0004, DESC_I_RINT2 = 0x0002,
 596         DESC_I_RINT1 = 0x0001,
 597 };
 598
 599 /* RPADIR */
 600 enum RPADIR_BIT {
 601         RPADIR_PADS1 = 0x20000, RPADIR_PADS0 = 0x10000,
 602         RPADIR_PADR = 0x0003f,
 603 };
 604
 605 /* RFLR */
 606 #define RFLR_VALUE 0x1000
 607
 608 /* FDR */
 609 #define DEFAULT_FDR_INIT        0x00000707
 610
 611 enum phy_offsets {
 612         PHY_CTRL = 0, PHY_STAT = 1, PHY_IDT1 = 2, PHY_IDT2 = 3,
 613         PHY_ANA = 4, PHY_ANL = 5, PHY_ANE = 6,
 614         PHY_16 = 16,
 615 };
 616
 617 /* PHY_CTRL */
 618 enum PHY_CTRL_BIT {
 619         PHY_C_RESET = 0x8000, PHY_C_LOOPBK = 0x4000, PHY_C_SPEEDSL = 0x2000,
 620         PHY_C_ANEGEN = 0x1000, PHY_C_PWRDN = 0x0800, PHY_C_ISO = 0x0400,
 621         PHY_C_RANEG = 0x0200, PHY_C_DUPLEX = 0x0100, PHY_C_COLT = 0x0080,
 622 };
 623 #define DM9161_PHY_C_ANEGEN 0   /* auto nego special */
 624
 625 /* PHY_STAT */
 626 enum PHY_STAT_BIT {
 627         PHY_S_100T4 = 0x8000, PHY_S_100X_F = 0x4000, PHY_S_100X_H = 0x2000,
 628         PHY_S_10T_F = 0x1000, PHY_S_10T_H = 0x0800, PHY_S_ANEGC = 0x0020,
 629         PHY_S_RFAULT = 0x0010, PHY_S_ANEGA = 0x0008, PHY_S_LINK = 0x0004,
 630         PHY_S_JAB = 0x0002, PHY_S_EXTD = 0x0001,
 631 };
 632
 633 /* PHY_ANA */
 634 enum PHY_ANA_BIT {
 635         PHY_A_NP = 0x8000, PHY_A_ACK = 0x4000, PHY_A_RF = 0x2000,
 636         PHY_A_FCS = 0x0400, PHY_A_T4 = 0x0200, PHY_A_FDX = 0x0100,
 637         PHY_A_HDX = 0x0080, PHY_A_10FDX = 0x0040, PHY_A_10HDX = 0x0020,
 638         PHY_A_SEL = 0x001e,
 639 };
 640 /* PHY_ANL */
 641 enum PHY_ANL_BIT {
 642         PHY_L_NP = 0x8000, PHY_L_ACK = 0x4000, PHY_L_RF = 0x2000,
 643         PHY_L_FCS = 0x0400, PHY_L_T4 = 0x0200, PHY_L_FDX = 0x0100,
 644         PHY_L_HDX = 0x0080, PHY_L_10FDX = 0x0040, PHY_L_10HDX = 0x0020,
 645         PHY_L_SEL = 0x001f,
 646 };
 647
 648 /* PHY_ANE */
 649 enum PHY_ANE_BIT {
 650         PHY_E_PDF = 0x0010, PHY_E_LPNPA = 0x0008, PHY_E_NPA = 0x0004,
 651         PHY_E_PRX = 0x0002, PHY_E_LPANEGA = 0x0001,
 652 };
 653
 654 /* DM9161 */
 655 enum PHY_16_BIT {
 656         PHY_16_BP4B45 = 0x8000, PHY_16_BPSCR = 0x4000, PHY_16_BPALIGN = 0x2000,
 657         PHY_16_BP_ADPOK = 0x1000, PHY_16_Repeatmode = 0x0800,
 658         PHY_16_TXselect = 0x0400,
 659         PHY_16_Rsvd = 0x0200, PHY_16_RMIIEnable = 0x0100,
 660         PHY_16_Force100LNK = 0x0080,
 661         PHY_16_APDLED_CTL = 0x0040, PHY_16_COLLED_CTL = 0x0020,
 662         PHY_16_RPDCTR_EN = 0x0010,
 663         PHY_16_ResetStMch = 0x0008, PHY_16_PreamSupr = 0x0004,
 664         PHY_16_Sleepmode = 0x0002,
 665         PHY_16_RemoteLoopOut = 0x0001,
 666 };
 667
 668 #define POST_RX         0x08
 669 #define POST_FW         0x04
 670 #define POST0_RX        (POST_RX)
 671 #define POST0_FW        (POST_FW)
 672 #define POST1_RX        (POST_RX >> 2)
 673 #define POST1_FW        (POST_FW >> 2)
 674 #define POST_ALL        (POST0_RX | POST0_FW | POST1_RX | POST1_FW)
 675
 676 /* ARSTR */
 677 enum ARSTR_BIT { ARSTR_ARSTR = 0x00000001, };
 678
 679 /* TSU_FWEN0 */
 680 enum TSU_FWEN0_BIT {
 681         TSU_FWEN0_0 = 0x00000001,
 682 };
 683
 684 /* TSU_ADSBSY */
 685 enum TSU_ADSBSY_BIT {
 686         TSU_ADSBSY_0 = 0x00000001,
 687 };
 688
 689 /* TSU_TEN */
 690 enum TSU_TEN_BIT {
 691         TSU_TEN_0 = 0x80000000,
 692 };
 693
 694 /* TSU_FWSL0 */
 695 enum TSU_FWSL0_BIT {
 696         TSU_FWSL0_FW50 = 0x1000, TSU_FWSL0_FW40 = 0x0800,
 697         TSU_FWSL0_FW30 = 0x0400, TSU_FWSL0_FW20 = 0x0200,
 698         TSU_FWSL0_FW10 = 0x0100, TSU_FWSL0_RMSA0 = 0x0010,
 699 };
 700
 701 /* TSU_FWSLC */
 702 enum TSU_FWSLC_BIT {
 703         TSU_FWSLC_POSTENU = 0x2000, TSU_FWSLC_POSTENL = 0x1000,
 704         TSU_FWSLC_CAMSEL03 = 0x0080, TSU_FWSLC_CAMSEL02 = 0x0040,
 705         TSU_FWSLC_CAMSEL01 = 0x0020, TSU_FWSLC_CAMSEL00 = 0x0010,
 706         TSU_FWSLC_CAMSEL13 = 0x0008, TSU_FWSLC_CAMSEL12 = 0x0004,
 707         TSU_FWSLC_CAMSEL11 = 0x0002, TSU_FWSLC_CAMSEL10 = 0x0001,
 708 };
 709
 710 /*
 711  * The sh ether Tx buffer descriptors.
 712  * This structure should be 20 bytes.
 713  */
 714 struct sh_eth_txdesc {
 715         u32 status;             /* TD0 */
 716 #if defined(CONFIG_CPU_LITTLE_ENDIAN)
 717         u16 pad0;               /* TD1 */
 718         u16 buffer_length;      /* TD1 */
 719 #else
 720         u16 buffer_length;      /* TD1 */
 721         u16 pad0;               /* TD1 */
 722 #endif
 723         u32 addr;               /* TD2 */
 724         u32 pad1;               /* padding data */
 725 } __attribute__((aligned(2), packed));
 726
 727 /*
 728  * The sh ether Rx buffer descriptors.
 729  * This structure should be 20 bytes.
 730  */
 731 struct sh_eth_rxdesc {
 732         u32 status;             /* RD0 */
 733 #if defined(CONFIG_CPU_LITTLE_ENDIAN)
 734         u16 frame_length;       /* RD1 */
 735         u16 buffer_length;      /* RD1 */
 736 #else
 737         u16 buffer_length;      /* RD1 */
 738         u16 frame_length;       /* RD1 */
 739 #endif
 740         u32 addr;               /* RD2 */
 741         u32 pad0;               /* padding data */
 742 } __attribute__((aligned(2), packed));
 743
 744 /* This structure is used by each CPU dependency handling. */
 745 struct sh_eth_cpu_data {
 746         /* optional functions */
 747         void (*chip_reset)(struct net_device *ndev);
 748         void (*set_duplex)(struct net_device *ndev);
 749         void (*set_rate)(struct net_device *ndev);
 750
 751         /* mandatory initialize value */
 752         unsigned long eesipr_value;
 753
 754         /* optional initialize value */
 755         unsigned long ecsr_value;
 756         unsigned long ecsipr_value;
 757         unsigned long fdr_value;
 758         unsigned long fcftr_value;
 759         unsigned long rpadir_value;
 760         unsigned long rmcr_value;
 761
 762         /* interrupt checking mask */
 763         unsigned long tx_check;
 764         unsigned long eesr_err_check;
 765         unsigned long tx_error_check;
 766
 767         /* hardware features */
 768         unsigned no_psr:1;              /* EtherC DO NOT have PSR */
 769         unsigned apr:1;                 /* EtherC have APR */
 770         unsigned mpr:1;                 /* EtherC have MPR */
 771         unsigned tpauser:1;             /* EtherC have TPAUSER */
 772         unsigned bculr:1;               /* EtherC have BCULR */
 773         unsigned hw_swap:1;             /* E-DMAC have DE bit in EDMR */
 774         unsigned rpadir:1;              /* E-DMAC have RPADIR */
 775         unsigned no_trimd:1;            /* E-DMAC DO NOT have TRIMD */
 776         unsigned no_ade:1;      /* E-DMAC DO NOT have ADE bit in EESR */
 777 };
 778
 779 struct sh_eth_private {
 780         struct platform_device *pdev;
 781         struct sh_eth_cpu_data *cd;
 782         const u16 *reg_offset;
 783         void __iomem *tsu_addr;
 784         dma_addr_t rx_desc_dma;
 785         dma_addr_t tx_desc_dma;
 786         struct sh_eth_rxdesc *rx_ring;
 787         struct sh_eth_txdesc *tx_ring;
 788         struct sk_buff **rx_skbuff;
 789         struct sk_buff **tx_skbuff;
 790         struct net_device_stats stats;
 791         struct timer_list timer;
 792         spinlock_t lock;
 793         u32 cur_rx, dirty_rx;   /* Producer/consumer ring indices */
 794         u32 cur_tx, dirty_tx;
 795         u32 rx_buf_sz;          /* Based on MTU+slack. */
 796         int edmac_endian;
 797         /* MII transceiver section. */
 798         u32 phy_id;                                     /* PHY ID */
 799         struct mii_bus *mii_bus;        /* MDIO bus control */
 800         struct phy_device *phydev;      /* PHY device control */
 801         enum phy_state link;
 802         int msg_enable;
 803         int speed;
 804         int duplex;
 805         u32 rx_int_var, tx_int_var;     /* interrupt control variables */
 806         char post_rx;           /* POST receive */
 807         char post_fw;           /* POST forward */
 808         struct net_device_stats tsu_stats;      /* TSU forward status */
 809
 810         unsigned no_ether_link:1;
 811         unsigned ether_link_active_low:1;
 812 };
 813
 814 static inline void sh_eth_soft_swap(char *src, int len)
 815 {
 816 #ifdef __LITTLE_ENDIAN__
 817         u32 *p = (u32 *)src;
 818         u32 *maxp;
 819         maxp = p + ((len + sizeof(u32) - 1) / sizeof(u32));
 820
 821         for (; p < maxp; p++)
 822                 *p = swab32(*p);
 823 #endif
 824 }
 825
 826 static inline void sh_eth_write(struct net_device *ndev, unsigned long data,
 827                                 int enum_index)
 828 {
 829         struct sh_eth_private *mdp = netdev_priv(ndev);
 830
 831         writel(data, ndev->base_addr + mdp->reg_offset[enum_index]);
 832 }
 833
 834 static inline unsigned long sh_eth_read(struct net_device *ndev,
 835                                         int enum_index)
 836 {
 837         struct sh_eth_private *mdp = netdev_priv(ndev);
 838
 839         return readl(ndev->base_addr + mdp->reg_offset[enum_index]);
 840 }
 841
 842 static inline void sh_eth_tsu_write(struct sh_eth_private *mdp,
 843                                 unsigned long data, int enum_index)
 844 {
 845         writel(data, mdp->tsu_addr + mdp->reg_offset[enum_index]);
 846 }
 847
 848 static inline unsigned long sh_eth_tsu_read(struct sh_eth_private *mdp,
 849                                         int enum_index)
 850 {
 851         return readl(mdp->tsu_addr + mdp->reg_offset[enum_index]);
 852 }
 853
 854 #endif  /* #ifndef __SH_ETH_H__ */