2 * New driver for Marvell Yukon chipset and SysKonnect Gigabit
3 * Ethernet adapters. Based on earlier sk98lin, e100 and
4 * FreeBSD if_sk drivers.
6 * This driver intentionally does not support all the features
7 * of the original driver such as link fail-over and link management because
8 * those should be done at higher levels.
10 * Copyright (C) 2004, 2005 Stephen Hemminger <shemminger@osdl.org>
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
27 #include <linux/kernel.h>
28 #include <linux/module.h>
29 #include <linux/moduleparam.h>
30 #include <linux/netdevice.h>
31 #include <linux/etherdevice.h>
32 #include <linux/ethtool.h>
33 #include <linux/pci.h>
34 #include <linux/if_vlan.h>
36 #include <linux/delay.h>
37 #include <linux/crc32.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/debugfs.h>
40 #include <linux/sched.h>
41 #include <linux/seq_file.h>
42 #include <linux/mii.h>
47 #define DRV_NAME "skge"
48 #define DRV_VERSION "1.13"
49 #define PFX DRV_NAME " "
51 #define DEFAULT_TX_RING_SIZE 128
52 #define DEFAULT_RX_RING_SIZE 512
53 #define MAX_TX_RING_SIZE 1024
54 #define TX_LOW_WATER (MAX_SKB_FRAGS + 1)
55 #define MAX_RX_RING_SIZE 4096
56 #define RX_COPY_THRESHOLD 128
57 #define RX_BUF_SIZE 1536
58 #define PHY_RETRIES 1000
59 #define ETH_JUMBO_MTU 9000
60 #define TX_WATCHDOG (5 * HZ)
61 #define NAPI_WEIGHT 64
65 #define SKGE_EEPROM_MAGIC 0x9933aabb
68 MODULE_DESCRIPTION("SysKonnect Gigabit Ethernet driver");
69 MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
70 MODULE_LICENSE("GPL");
71 MODULE_VERSION(DRV_VERSION);
73 static const u32 default_msg
74 = NETIF_MSG_DRV| NETIF_MSG_PROBE| NETIF_MSG_LINK
75 | NETIF_MSG_IFUP| NETIF_MSG_IFDOWN;
77 static int debug = -1; /* defaults above */
78 module_param(debug, int, 0);
79 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
81 static DEFINE_PCI_DEVICE_TABLE(skge_id_table) = {
82 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940) },
83 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940B) },
84 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_GE) },
85 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_YU) },
86 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_DGE510T) },
87 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b01) }, /* DGE-530T */
88 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4320) },
89 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5005) }, /* Belkin */
90 { PCI_DEVICE(PCI_VENDOR_ID_CNET, PCI_DEVICE_ID_CNET_GIGACARD) },
91 { PCI_DEVICE(PCI_VENDOR_ID_LINKSYS, PCI_DEVICE_ID_LINKSYS_EG1064) },
92 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0015 },
95 MODULE_DEVICE_TABLE(pci, skge_id_table);
97 static int skge_up(struct net_device *dev);
98 static int skge_down(struct net_device *dev);
99 static void skge_phy_reset(struct skge_port *skge);
100 static void skge_tx_clean(struct net_device *dev);
101 static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
102 static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
103 static void genesis_get_stats(struct skge_port *skge, u64 *data);
104 static void yukon_get_stats(struct skge_port *skge, u64 *data);
105 static void yukon_init(struct skge_hw *hw, int port);
106 static void genesis_mac_init(struct skge_hw *hw, int port);
107 static void genesis_link_up(struct skge_port *skge);
108 static void skge_set_multicast(struct net_device *dev);
110 /* Avoid conditionals by using array */
111 static const int txqaddr[] = { Q_XA1, Q_XA2 };
112 static const int rxqaddr[] = { Q_R1, Q_R2 };
113 static const u32 rxirqmask[] = { IS_R1_F, IS_R2_F };
114 static const u32 txirqmask[] = { IS_XA1_F, IS_XA2_F };
115 static const u32 napimask[] = { IS_R1_F|IS_XA1_F, IS_R2_F|IS_XA2_F };
116 static const u32 portmask[] = { IS_PORT_1, IS_PORT_2 };
118 static int skge_get_regs_len(struct net_device *dev)
124 * Returns copy of whole control register region
125 * Note: skip RAM address register because accessing it will
128 static void skge_get_regs(struct net_device *dev, struct ethtool_regs *regs,
131 const struct skge_port *skge = netdev_priv(dev);
132 const void __iomem *io = skge->hw->regs;
135 memset(p, 0, regs->len);
136 memcpy_fromio(p, io, B3_RAM_ADDR);
138 memcpy_fromio(p + B3_RI_WTO_R1, io + B3_RI_WTO_R1,
139 regs->len - B3_RI_WTO_R1);
142 /* Wake on Lan only supported on Yukon chips with rev 1 or above */
143 static u32 wol_supported(const struct skge_hw *hw)
145 if (hw->chip_id == CHIP_ID_GENESIS)
148 if (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)
151 return WAKE_MAGIC | WAKE_PHY;
154 static void skge_wol_init(struct skge_port *skge)
156 struct skge_hw *hw = skge->hw;
157 int port = skge->port;
160 skge_write16(hw, B0_CTST, CS_RST_CLR);
161 skge_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
164 skge_write8(hw, B0_POWER_CTRL,
165 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_ON | PC_VCC_OFF);
167 /* WA code for COMA mode -- clear PHY reset */
168 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
169 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
170 u32 reg = skge_read32(hw, B2_GP_IO);
173 skge_write32(hw, B2_GP_IO, reg);
176 skge_write32(hw, SK_REG(port, GPHY_CTRL),
178 GPC_HWCFG_M_3 | GPC_HWCFG_M_2 | GPC_HWCFG_M_1 | GPC_HWCFG_M_0 |
179 GPC_ANEG_1 | GPC_RST_SET);
181 skge_write32(hw, SK_REG(port, GPHY_CTRL),
183 GPC_HWCFG_M_3 | GPC_HWCFG_M_2 | GPC_HWCFG_M_1 | GPC_HWCFG_M_0 |
184 GPC_ANEG_1 | GPC_RST_CLR);
186 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
188 /* Force to 10/100 skge_reset will re-enable on resume */
189 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
190 PHY_AN_100FULL | PHY_AN_100HALF |
191 PHY_AN_10FULL | PHY_AN_10HALF| PHY_AN_CSMA);
193 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, 0);
194 gm_phy_write(hw, port, PHY_MARV_CTRL,
195 PHY_CT_RESET | PHY_CT_SPS_LSB | PHY_CT_ANE |
196 PHY_CT_RE_CFG | PHY_CT_DUP_MD);
199 /* Set GMAC to no flow control and auto update for speed/duplex */
200 gma_write16(hw, port, GM_GP_CTRL,
201 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
202 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
204 /* Set WOL address */
205 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
206 skge->netdev->dev_addr, ETH_ALEN);
208 /* Turn on appropriate WOL control bits */
209 skge_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
211 if (skge->wol & WAKE_PHY)
212 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
214 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
216 if (skge->wol & WAKE_MAGIC)
217 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
219 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;
221 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
222 skge_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
225 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
228 static void skge_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
230 struct skge_port *skge = netdev_priv(dev);
232 wol->supported = wol_supported(skge->hw);
233 wol->wolopts = skge->wol;
236 static int skge_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
238 struct skge_port *skge = netdev_priv(dev);
239 struct skge_hw *hw = skge->hw;
241 if ((wol->wolopts & ~wol_supported(hw)) ||
242 !device_can_wakeup(&hw->pdev->dev))
245 skge->wol = wol->wolopts;
247 device_set_wakeup_enable(&hw->pdev->dev, skge->wol);
252 /* Determine supported/advertised modes based on hardware.
253 * Note: ethtool ADVERTISED_xxx == SUPPORTED_xxx
255 static u32 skge_supported_modes(const struct skge_hw *hw)
260 supported = SUPPORTED_10baseT_Half
261 | SUPPORTED_10baseT_Full
262 | SUPPORTED_100baseT_Half
263 | SUPPORTED_100baseT_Full
264 | SUPPORTED_1000baseT_Half
265 | SUPPORTED_1000baseT_Full
266 | SUPPORTED_Autoneg| SUPPORTED_TP;
268 if (hw->chip_id == CHIP_ID_GENESIS)
269 supported &= ~(SUPPORTED_10baseT_Half
270 | SUPPORTED_10baseT_Full
271 | SUPPORTED_100baseT_Half
272 | SUPPORTED_100baseT_Full);
274 else if (hw->chip_id == CHIP_ID_YUKON)
275 supported &= ~SUPPORTED_1000baseT_Half;
277 supported = SUPPORTED_1000baseT_Full | SUPPORTED_1000baseT_Half
278 | SUPPORTED_FIBRE | SUPPORTED_Autoneg;
283 static int skge_get_settings(struct net_device *dev,
284 struct ethtool_cmd *ecmd)
286 struct skge_port *skge = netdev_priv(dev);
287 struct skge_hw *hw = skge->hw;
289 ecmd->transceiver = XCVR_INTERNAL;
290 ecmd->supported = skge_supported_modes(hw);
293 ecmd->port = PORT_TP;
294 ecmd->phy_address = hw->phy_addr;
296 ecmd->port = PORT_FIBRE;
298 ecmd->advertising = skge->advertising;
299 ecmd->autoneg = skge->autoneg;
300 ecmd->speed = skge->speed;
301 ecmd->duplex = skge->duplex;
305 static int skge_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
307 struct skge_port *skge = netdev_priv(dev);
308 const struct skge_hw *hw = skge->hw;
309 u32 supported = skge_supported_modes(hw);
312 if (ecmd->autoneg == AUTONEG_ENABLE) {
313 ecmd->advertising = supported;
319 switch (ecmd->speed) {
321 if (ecmd->duplex == DUPLEX_FULL)
322 setting = SUPPORTED_1000baseT_Full;
323 else if (ecmd->duplex == DUPLEX_HALF)
324 setting = SUPPORTED_1000baseT_Half;
329 if (ecmd->duplex == DUPLEX_FULL)
330 setting = SUPPORTED_100baseT_Full;
331 else if (ecmd->duplex == DUPLEX_HALF)
332 setting = SUPPORTED_100baseT_Half;
338 if (ecmd->duplex == DUPLEX_FULL)
339 setting = SUPPORTED_10baseT_Full;
340 else if (ecmd->duplex == DUPLEX_HALF)
341 setting = SUPPORTED_10baseT_Half;
349 if ((setting & supported) == 0)
352 skge->speed = ecmd->speed;
353 skge->duplex = ecmd->duplex;
356 skge->autoneg = ecmd->autoneg;
357 skge->advertising = ecmd->advertising;
359 if (netif_running(dev)) {
371 static void skge_get_drvinfo(struct net_device *dev,
372 struct ethtool_drvinfo *info)
374 struct skge_port *skge = netdev_priv(dev);
376 strcpy(info->driver, DRV_NAME);
377 strcpy(info->version, DRV_VERSION);
378 strcpy(info->fw_version, "N/A");
379 strcpy(info->bus_info, pci_name(skge->hw->pdev));
382 static const struct skge_stat {
383 char name[ETH_GSTRING_LEN];
387 { "tx_bytes", XM_TXO_OK_HI, GM_TXO_OK_HI },
388 { "rx_bytes", XM_RXO_OK_HI, GM_RXO_OK_HI },
390 { "tx_broadcast", XM_TXF_BC_OK, GM_TXF_BC_OK },
391 { "rx_broadcast", XM_RXF_BC_OK, GM_RXF_BC_OK },
392 { "tx_multicast", XM_TXF_MC_OK, GM_TXF_MC_OK },
393 { "rx_multicast", XM_RXF_MC_OK, GM_RXF_MC_OK },
394 { "tx_unicast", XM_TXF_UC_OK, GM_TXF_UC_OK },
395 { "rx_unicast", XM_RXF_UC_OK, GM_RXF_UC_OK },
396 { "tx_mac_pause", XM_TXF_MPAUSE, GM_TXF_MPAUSE },
397 { "rx_mac_pause", XM_RXF_MPAUSE, GM_RXF_MPAUSE },
399 { "collisions", XM_TXF_SNG_COL, GM_TXF_SNG_COL },
400 { "multi_collisions", XM_TXF_MUL_COL, GM_TXF_MUL_COL },
401 { "aborted", XM_TXF_ABO_COL, GM_TXF_ABO_COL },
402 { "late_collision", XM_TXF_LAT_COL, GM_TXF_LAT_COL },
403 { "fifo_underrun", XM_TXE_FIFO_UR, GM_TXE_FIFO_UR },
404 { "fifo_overflow", XM_RXE_FIFO_OV, GM_RXE_FIFO_OV },
406 { "rx_toolong", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
407 { "rx_jabber", XM_RXF_JAB_PKT, GM_RXF_JAB_PKT },
408 { "rx_runt", XM_RXE_RUNT, GM_RXE_FRAG },
409 { "rx_too_long", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
410 { "rx_fcs_error", XM_RXF_FCS_ERR, GM_RXF_FCS_ERR },
413 static int skge_get_sset_count(struct net_device *dev, int sset)
417 return ARRAY_SIZE(skge_stats);
423 static void skge_get_ethtool_stats(struct net_device *dev,
424 struct ethtool_stats *stats, u64 *data)
426 struct skge_port *skge = netdev_priv(dev);
428 if (skge->hw->chip_id == CHIP_ID_GENESIS)
429 genesis_get_stats(skge, data);
431 yukon_get_stats(skge, data);
434 /* Use hardware MIB variables for critical path statistics and
435 * transmit feedback not reported at interrupt.
436 * Other errors are accounted for in interrupt handler.
438 static struct net_device_stats *skge_get_stats(struct net_device *dev)
440 struct skge_port *skge = netdev_priv(dev);
441 u64 data[ARRAY_SIZE(skge_stats)];
443 if (skge->hw->chip_id == CHIP_ID_GENESIS)
444 genesis_get_stats(skge, data);
446 yukon_get_stats(skge, data);
448 dev->stats.tx_bytes = data[0];
449 dev->stats.rx_bytes = data[1];
450 dev->stats.tx_packets = data[2] + data[4] + data[6];
451 dev->stats.rx_packets = data[3] + data[5] + data[7];
452 dev->stats.multicast = data[3] + data[5];
453 dev->stats.collisions = data[10];
454 dev->stats.tx_aborted_errors = data[12];
459 static void skge_get_strings(struct net_device *dev, u32 stringset, u8 *data)
465 for (i = 0; i < ARRAY_SIZE(skge_stats); i++)
466 memcpy(data + i * ETH_GSTRING_LEN,
467 skge_stats[i].name, ETH_GSTRING_LEN);
472 static void skge_get_ring_param(struct net_device *dev,
473 struct ethtool_ringparam *p)
475 struct skge_port *skge = netdev_priv(dev);
477 p->rx_max_pending = MAX_RX_RING_SIZE;
478 p->tx_max_pending = MAX_TX_RING_SIZE;
479 p->rx_mini_max_pending = 0;
480 p->rx_jumbo_max_pending = 0;
482 p->rx_pending = skge->rx_ring.count;
483 p->tx_pending = skge->tx_ring.count;
484 p->rx_mini_pending = 0;
485 p->rx_jumbo_pending = 0;
488 static int skge_set_ring_param(struct net_device *dev,
489 struct ethtool_ringparam *p)
491 struct skge_port *skge = netdev_priv(dev);
494 if (p->rx_pending == 0 || p->rx_pending > MAX_RX_RING_SIZE ||
495 p->tx_pending < TX_LOW_WATER || p->tx_pending > MAX_TX_RING_SIZE)
498 skge->rx_ring.count = p->rx_pending;
499 skge->tx_ring.count = p->tx_pending;
501 if (netif_running(dev)) {
511 static u32 skge_get_msglevel(struct net_device *netdev)
513 struct skge_port *skge = netdev_priv(netdev);
514 return skge->msg_enable;
517 static void skge_set_msglevel(struct net_device *netdev, u32 value)
519 struct skge_port *skge = netdev_priv(netdev);
520 skge->msg_enable = value;
523 static int skge_nway_reset(struct net_device *dev)
525 struct skge_port *skge = netdev_priv(dev);
527 if (skge->autoneg != AUTONEG_ENABLE || !netif_running(dev))
530 skge_phy_reset(skge);
534 static int skge_set_sg(struct net_device *dev, u32 data)
536 struct skge_port *skge = netdev_priv(dev);
537 struct skge_hw *hw = skge->hw;
539 if (hw->chip_id == CHIP_ID_GENESIS && data)
541 return ethtool_op_set_sg(dev, data);
544 static int skge_set_tx_csum(struct net_device *dev, u32 data)
546 struct skge_port *skge = netdev_priv(dev);
547 struct skge_hw *hw = skge->hw;
549 if (hw->chip_id == CHIP_ID_GENESIS && data)
552 return ethtool_op_set_tx_csum(dev, data);
555 static u32 skge_get_rx_csum(struct net_device *dev)
557 struct skge_port *skge = netdev_priv(dev);
559 return skge->rx_csum;
562 /* Only Yukon supports checksum offload. */
563 static int skge_set_rx_csum(struct net_device *dev, u32 data)
565 struct skge_port *skge = netdev_priv(dev);
567 if (skge->hw->chip_id == CHIP_ID_GENESIS && data)
570 skge->rx_csum = data;
574 static void skge_get_pauseparam(struct net_device *dev,
575 struct ethtool_pauseparam *ecmd)
577 struct skge_port *skge = netdev_priv(dev);
579 ecmd->rx_pause = ((skge->flow_control == FLOW_MODE_SYMMETRIC) ||
580 (skge->flow_control == FLOW_MODE_SYM_OR_REM));
581 ecmd->tx_pause = (ecmd->rx_pause ||
582 (skge->flow_control == FLOW_MODE_LOC_SEND));
584 ecmd->autoneg = ecmd->rx_pause || ecmd->tx_pause;
587 static int skge_set_pauseparam(struct net_device *dev,
588 struct ethtool_pauseparam *ecmd)
590 struct skge_port *skge = netdev_priv(dev);
591 struct ethtool_pauseparam old;
594 skge_get_pauseparam(dev, &old);
596 if (ecmd->autoneg != old.autoneg)
597 skge->flow_control = ecmd->autoneg ? FLOW_MODE_NONE : FLOW_MODE_SYMMETRIC;
599 if (ecmd->rx_pause && ecmd->tx_pause)
600 skge->flow_control = FLOW_MODE_SYMMETRIC;
601 else if (ecmd->rx_pause && !ecmd->tx_pause)
602 skge->flow_control = FLOW_MODE_SYM_OR_REM;
603 else if (!ecmd->rx_pause && ecmd->tx_pause)
604 skge->flow_control = FLOW_MODE_LOC_SEND;
606 skge->flow_control = FLOW_MODE_NONE;
609 if (netif_running(dev)) {
621 /* Chip internal frequency for clock calculations */
622 static inline u32 hwkhz(const struct skge_hw *hw)
624 return (hw->chip_id == CHIP_ID_GENESIS) ? 53125 : 78125;
627 /* Chip HZ to microseconds */
628 static inline u32 skge_clk2usec(const struct skge_hw *hw, u32 ticks)
630 return (ticks * 1000) / hwkhz(hw);
633 /* Microseconds to chip HZ */
634 static inline u32 skge_usecs2clk(const struct skge_hw *hw, u32 usec)
636 return hwkhz(hw) * usec / 1000;
639 static int skge_get_coalesce(struct net_device *dev,
640 struct ethtool_coalesce *ecmd)
642 struct skge_port *skge = netdev_priv(dev);
643 struct skge_hw *hw = skge->hw;
644 int port = skge->port;
646 ecmd->rx_coalesce_usecs = 0;
647 ecmd->tx_coalesce_usecs = 0;
649 if (skge_read32(hw, B2_IRQM_CTRL) & TIM_START) {
650 u32 delay = skge_clk2usec(hw, skge_read32(hw, B2_IRQM_INI));
651 u32 msk = skge_read32(hw, B2_IRQM_MSK);
653 if (msk & rxirqmask[port])
654 ecmd->rx_coalesce_usecs = delay;
655 if (msk & txirqmask[port])
656 ecmd->tx_coalesce_usecs = delay;
662 /* Note: interrupt timer is per board, but can turn on/off per port */
663 static int skge_set_coalesce(struct net_device *dev,
664 struct ethtool_coalesce *ecmd)
666 struct skge_port *skge = netdev_priv(dev);
667 struct skge_hw *hw = skge->hw;
668 int port = skge->port;
669 u32 msk = skge_read32(hw, B2_IRQM_MSK);
672 if (ecmd->rx_coalesce_usecs == 0)
673 msk &= ~rxirqmask[port];
674 else if (ecmd->rx_coalesce_usecs < 25 ||
675 ecmd->rx_coalesce_usecs > 33333)
678 msk |= rxirqmask[port];
679 delay = ecmd->rx_coalesce_usecs;
682 if (ecmd->tx_coalesce_usecs == 0)
683 msk &= ~txirqmask[port];
684 else if (ecmd->tx_coalesce_usecs < 25 ||
685 ecmd->tx_coalesce_usecs > 33333)
688 msk |= txirqmask[port];
689 delay = min(delay, ecmd->rx_coalesce_usecs);
692 skge_write32(hw, B2_IRQM_MSK, msk);
694 skge_write32(hw, B2_IRQM_CTRL, TIM_STOP);
696 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, delay));
697 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
702 enum led_mode { LED_MODE_OFF, LED_MODE_ON, LED_MODE_TST };
703 static void skge_led(struct skge_port *skge, enum led_mode mode)
705 struct skge_hw *hw = skge->hw;
706 int port = skge->port;
708 spin_lock_bh(&hw->phy_lock);
709 if (hw->chip_id == CHIP_ID_GENESIS) {
712 if (hw->phy_type == SK_PHY_BCOM)
713 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_OFF);
715 skge_write32(hw, SK_REG(port, TX_LED_VAL), 0);
716 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_T_OFF);
718 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
719 skge_write32(hw, SK_REG(port, RX_LED_VAL), 0);
720 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_T_OFF);
724 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON);
725 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_LINKSYNC_ON);
727 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
728 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
733 skge_write8(hw, SK_REG(port, RX_LED_TST), LED_T_ON);
734 skge_write32(hw, SK_REG(port, RX_LED_VAL), 100);
735 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
737 if (hw->phy_type == SK_PHY_BCOM)
738 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_ON);
740 skge_write8(hw, SK_REG(port, TX_LED_TST), LED_T_ON);
741 skge_write32(hw, SK_REG(port, TX_LED_VAL), 100);
742 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
749 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
750 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
751 PHY_M_LED_MO_DUP(MO_LED_OFF) |
752 PHY_M_LED_MO_10(MO_LED_OFF) |
753 PHY_M_LED_MO_100(MO_LED_OFF) |
754 PHY_M_LED_MO_1000(MO_LED_OFF) |
755 PHY_M_LED_MO_RX(MO_LED_OFF));
758 gm_phy_write(hw, port, PHY_MARV_LED_CTRL,
759 PHY_M_LED_PULS_DUR(PULS_170MS) |
760 PHY_M_LED_BLINK_RT(BLINK_84MS) |
764 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
765 PHY_M_LED_MO_RX(MO_LED_OFF) |
766 (skge->speed == SPEED_100 ?
767 PHY_M_LED_MO_100(MO_LED_ON) : 0));
770 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
771 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
772 PHY_M_LED_MO_DUP(MO_LED_ON) |
773 PHY_M_LED_MO_10(MO_LED_ON) |
774 PHY_M_LED_MO_100(MO_LED_ON) |
775 PHY_M_LED_MO_1000(MO_LED_ON) |
776 PHY_M_LED_MO_RX(MO_LED_ON));
779 spin_unlock_bh(&hw->phy_lock);
782 /* blink LED's for finding board */
783 static int skge_phys_id(struct net_device *dev, u32 data)
785 struct skge_port *skge = netdev_priv(dev);
787 enum led_mode mode = LED_MODE_TST;
789 if (!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))
790 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT / HZ) * 1000;
795 skge_led(skge, mode);
796 mode ^= LED_MODE_TST;
798 if (msleep_interruptible(BLINK_MS))
803 /* back to regular LED state */
804 skge_led(skge, netif_running(dev) ? LED_MODE_ON : LED_MODE_OFF);
809 static int skge_get_eeprom_len(struct net_device *dev)
811 struct skge_port *skge = netdev_priv(dev);
814 pci_read_config_dword(skge->hw->pdev, PCI_DEV_REG2, ®2);
815 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
818 static u32 skge_vpd_read(struct pci_dev *pdev, int cap, u16 offset)
822 pci_write_config_word(pdev, cap + PCI_VPD_ADDR, offset);
825 pci_read_config_word(pdev, cap + PCI_VPD_ADDR, &offset);
826 } while (!(offset & PCI_VPD_ADDR_F));
828 pci_read_config_dword(pdev, cap + PCI_VPD_DATA, &val);
832 static void skge_vpd_write(struct pci_dev *pdev, int cap, u16 offset, u32 val)
834 pci_write_config_dword(pdev, cap + PCI_VPD_DATA, val);
835 pci_write_config_word(pdev, cap + PCI_VPD_ADDR,
836 offset | PCI_VPD_ADDR_F);
839 pci_read_config_word(pdev, cap + PCI_VPD_ADDR, &offset);
840 } while (offset & PCI_VPD_ADDR_F);
843 static int skge_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
846 struct skge_port *skge = netdev_priv(dev);
847 struct pci_dev *pdev = skge->hw->pdev;
848 int cap = pci_find_capability(pdev, PCI_CAP_ID_VPD);
849 int length = eeprom->len;
850 u16 offset = eeprom->offset;
855 eeprom->magic = SKGE_EEPROM_MAGIC;
858 u32 val = skge_vpd_read(pdev, cap, offset);
859 int n = min_t(int, length, sizeof(val));
861 memcpy(data, &val, n);
869 static int skge_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
872 struct skge_port *skge = netdev_priv(dev);
873 struct pci_dev *pdev = skge->hw->pdev;
874 int cap = pci_find_capability(pdev, PCI_CAP_ID_VPD);
875 int length = eeprom->len;
876 u16 offset = eeprom->offset;
881 if (eeprom->magic != SKGE_EEPROM_MAGIC)
886 int n = min_t(int, length, sizeof(val));
889 val = skge_vpd_read(pdev, cap, offset);
890 memcpy(&val, data, n);
892 skge_vpd_write(pdev, cap, offset, val);
901 static const struct ethtool_ops skge_ethtool_ops = {
902 .get_settings = skge_get_settings,
903 .set_settings = skge_set_settings,
904 .get_drvinfo = skge_get_drvinfo,
905 .get_regs_len = skge_get_regs_len,
906 .get_regs = skge_get_regs,
907 .get_wol = skge_get_wol,
908 .set_wol = skge_set_wol,
909 .get_msglevel = skge_get_msglevel,
910 .set_msglevel = skge_set_msglevel,
911 .nway_reset = skge_nway_reset,
912 .get_link = ethtool_op_get_link,
913 .get_eeprom_len = skge_get_eeprom_len,
914 .get_eeprom = skge_get_eeprom,
915 .set_eeprom = skge_set_eeprom,
916 .get_ringparam = skge_get_ring_param,
917 .set_ringparam = skge_set_ring_param,
918 .get_pauseparam = skge_get_pauseparam,
919 .set_pauseparam = skge_set_pauseparam,
920 .get_coalesce = skge_get_coalesce,
921 .set_coalesce = skge_set_coalesce,
922 .set_sg = skge_set_sg,
923 .set_tx_csum = skge_set_tx_csum,
924 .get_rx_csum = skge_get_rx_csum,
925 .set_rx_csum = skge_set_rx_csum,
926 .get_strings = skge_get_strings,
927 .phys_id = skge_phys_id,
928 .get_sset_count = skge_get_sset_count,
929 .get_ethtool_stats = skge_get_ethtool_stats,
933 * Allocate ring elements and chain them together
934 * One-to-one association of board descriptors with ring elements
936 static int skge_ring_alloc(struct skge_ring *ring, void *vaddr, u32 base)
938 struct skge_tx_desc *d;
939 struct skge_element *e;
942 ring->start = kcalloc(ring->count, sizeof(*e), GFP_KERNEL);
946 for (i = 0, e = ring->start, d = vaddr; i < ring->count; i++, e++, d++) {
948 if (i == ring->count - 1) {
949 e->next = ring->start;
950 d->next_offset = base;
953 d->next_offset = base + (i+1) * sizeof(*d);
956 ring->to_use = ring->to_clean = ring->start;
961 /* Allocate and setup a new buffer for receiving */
962 static void skge_rx_setup(struct skge_port *skge, struct skge_element *e,
963 struct sk_buff *skb, unsigned int bufsize)
965 struct skge_rx_desc *rd = e->desc;
968 map = pci_map_single(skge->hw->pdev, skb->data, bufsize,
972 rd->dma_hi = map >> 32;
974 rd->csum1_start = ETH_HLEN;
975 rd->csum2_start = ETH_HLEN;
981 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | bufsize;
982 pci_unmap_addr_set(e, mapaddr, map);
983 pci_unmap_len_set(e, maplen, bufsize);
986 /* Resume receiving using existing skb,
987 * Note: DMA address is not changed by chip.
988 * MTU not changed while receiver active.
990 static inline void skge_rx_reuse(struct skge_element *e, unsigned int size)
992 struct skge_rx_desc *rd = e->desc;
995 rd->csum2_start = ETH_HLEN;
999 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | size;
1003 /* Free all buffers in receive ring, assumes receiver stopped */
1004 static void skge_rx_clean(struct skge_port *skge)
1006 struct skge_hw *hw = skge->hw;
1007 struct skge_ring *ring = &skge->rx_ring;
1008 struct skge_element *e;
1012 struct skge_rx_desc *rd = e->desc;
1015 pci_unmap_single(hw->pdev,
1016 pci_unmap_addr(e, mapaddr),
1017 pci_unmap_len(e, maplen),
1018 PCI_DMA_FROMDEVICE);
1019 dev_kfree_skb(e->skb);
1022 } while ((e = e->next) != ring->start);
1026 /* Allocate buffers for receive ring
1027 * For receive: to_clean is next received frame.
1029 static int skge_rx_fill(struct net_device *dev)
1031 struct skge_port *skge = netdev_priv(dev);
1032 struct skge_ring *ring = &skge->rx_ring;
1033 struct skge_element *e;
1037 struct sk_buff *skb;
1039 skb = __netdev_alloc_skb(dev, skge->rx_buf_size + NET_IP_ALIGN,
1044 skb_reserve(skb, NET_IP_ALIGN);
1045 skge_rx_setup(skge, e, skb, skge->rx_buf_size);
1046 } while ( (e = e->next) != ring->start);
1048 ring->to_clean = ring->start;
1052 static const char *skge_pause(enum pause_status status)
1055 case FLOW_STAT_NONE:
1057 case FLOW_STAT_REM_SEND:
1059 case FLOW_STAT_LOC_SEND:
1061 case FLOW_STAT_SYMMETRIC: /* Both station may send PAUSE */
1064 return "indeterminated";
1069 static void skge_link_up(struct skge_port *skge)
1071 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG),
1072 LED_BLK_OFF|LED_SYNC_OFF|LED_ON);
1074 netif_carrier_on(skge->netdev);
1075 netif_wake_queue(skge->netdev);
1077 netif_info(skge, link, skge->netdev,
1078 "Link is up at %d Mbps, %s duplex, flow control %s\n",
1080 skge->duplex == DUPLEX_FULL ? "full" : "half",
1081 skge_pause(skge->flow_status));
1084 static void skge_link_down(struct skge_port *skge)
1086 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
1087 netif_carrier_off(skge->netdev);
1088 netif_stop_queue(skge->netdev);
1090 netif_info(skge, link, skge->netdev, "Link is down\n");
1094 static void xm_link_down(struct skge_hw *hw, int port)
1096 struct net_device *dev = hw->dev[port];
1097 struct skge_port *skge = netdev_priv(dev);
1099 xm_write16(hw, port, XM_IMSK, XM_IMSK_DISABLE);
1101 if (netif_carrier_ok(dev))
1102 skge_link_down(skge);
1105 static int __xm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
1109 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
1110 *val = xm_read16(hw, port, XM_PHY_DATA);
1112 if (hw->phy_type == SK_PHY_XMAC)
1115 for (i = 0; i < PHY_RETRIES; i++) {
1116 if (xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_RDY)
1123 *val = xm_read16(hw, port, XM_PHY_DATA);
1128 static u16 xm_phy_read(struct skge_hw *hw, int port, u16 reg)
1131 if (__xm_phy_read(hw, port, reg, &v))
1132 printk(KERN_WARNING PFX "%s: phy read timed out\n",
1133 hw->dev[port]->name);
1137 static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
1141 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
1142 for (i = 0; i < PHY_RETRIES; i++) {
1143 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
1150 xm_write16(hw, port, XM_PHY_DATA, val);
1151 for (i = 0; i < PHY_RETRIES; i++) {
1152 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
1159 static void genesis_init(struct skge_hw *hw)
1161 /* set blink source counter */
1162 skge_write32(hw, B2_BSC_INI, (SK_BLK_DUR * SK_FACT_53) / 100);
1163 skge_write8(hw, B2_BSC_CTRL, BSC_START);
1165 /* configure mac arbiter */
1166 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
1168 /* configure mac arbiter timeout values */
1169 skge_write8(hw, B3_MA_TOINI_RX1, SK_MAC_TO_53);
1170 skge_write8(hw, B3_MA_TOINI_RX2, SK_MAC_TO_53);
1171 skge_write8(hw, B3_MA_TOINI_TX1, SK_MAC_TO_53);
1172 skge_write8(hw, B3_MA_TOINI_TX2, SK_MAC_TO_53);
1174 skge_write8(hw, B3_MA_RCINI_RX1, 0);
1175 skge_write8(hw, B3_MA_RCINI_RX2, 0);
1176 skge_write8(hw, B3_MA_RCINI_TX1, 0);
1177 skge_write8(hw, B3_MA_RCINI_TX2, 0);
1179 /* configure packet arbiter timeout */
1180 skge_write16(hw, B3_PA_CTRL, PA_RST_CLR);
1181 skge_write16(hw, B3_PA_TOINI_RX1, SK_PKT_TO_MAX);
1182 skge_write16(hw, B3_PA_TOINI_TX1, SK_PKT_TO_MAX);
1183 skge_write16(hw, B3_PA_TOINI_RX2, SK_PKT_TO_MAX);
1184 skge_write16(hw, B3_PA_TOINI_TX2, SK_PKT_TO_MAX);
1187 static void genesis_reset(struct skge_hw *hw, int port)
1189 const u8 zero[8] = { 0 };
1192 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
1194 /* reset the statistics module */
1195 xm_write32(hw, port, XM_GP_PORT, XM_GP_RES_STAT);
1196 xm_write16(hw, port, XM_IMSK, XM_IMSK_DISABLE);
1197 xm_write32(hw, port, XM_MODE, 0); /* clear Mode Reg */
1198 xm_write16(hw, port, XM_TX_CMD, 0); /* reset TX CMD Reg */
1199 xm_write16(hw, port, XM_RX_CMD, 0); /* reset RX CMD Reg */
1201 /* disable Broadcom PHY IRQ */
1202 if (hw->phy_type == SK_PHY_BCOM)
1203 xm_write16(hw, port, PHY_BCOM_INT_MASK, 0xffff);
1205 xm_outhash(hw, port, XM_HSM, zero);
1207 /* Flush TX and RX fifo */
1208 reg = xm_read32(hw, port, XM_MODE);
1209 xm_write32(hw, port, XM_MODE, reg | XM_MD_FTF);
1210 xm_write32(hw, port, XM_MODE, reg | XM_MD_FRF);
1214 /* Convert mode to MII values */
1215 static const u16 phy_pause_map[] = {
1216 [FLOW_MODE_NONE] = 0,
1217 [FLOW_MODE_LOC_SEND] = PHY_AN_PAUSE_ASYM,
1218 [FLOW_MODE_SYMMETRIC] = PHY_AN_PAUSE_CAP,
1219 [FLOW_MODE_SYM_OR_REM] = PHY_AN_PAUSE_CAP | PHY_AN_PAUSE_ASYM,
1222 /* special defines for FIBER (88E1011S only) */
1223 static const u16 fiber_pause_map[] = {
1224 [FLOW_MODE_NONE] = PHY_X_P_NO_PAUSE,
1225 [FLOW_MODE_LOC_SEND] = PHY_X_P_ASYM_MD,
1226 [FLOW_MODE_SYMMETRIC] = PHY_X_P_SYM_MD,
1227 [FLOW_MODE_SYM_OR_REM] = PHY_X_P_BOTH_MD,
1231 /* Check status of Broadcom phy link */
1232 static void bcom_check_link(struct skge_hw *hw, int port)
1234 struct net_device *dev = hw->dev[port];
1235 struct skge_port *skge = netdev_priv(dev);
1238 /* read twice because of latch */
1239 xm_phy_read(hw, port, PHY_BCOM_STAT);
1240 status = xm_phy_read(hw, port, PHY_BCOM_STAT);
1242 if ((status & PHY_ST_LSYNC) == 0) {
1243 xm_link_down(hw, port);
1247 if (skge->autoneg == AUTONEG_ENABLE) {
1250 if (!(status & PHY_ST_AN_OVER))
1253 lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP);
1254 if (lpa & PHY_B_AN_RF) {
1255 printk(KERN_NOTICE PFX "%s: remote fault\n",
1260 aux = xm_phy_read(hw, port, PHY_BCOM_AUX_STAT);
1262 /* Check Duplex mismatch */
1263 switch (aux & PHY_B_AS_AN_RES_MSK) {
1264 case PHY_B_RES_1000FD:
1265 skge->duplex = DUPLEX_FULL;
1267 case PHY_B_RES_1000HD:
1268 skge->duplex = DUPLEX_HALF;
1271 printk(KERN_NOTICE PFX "%s: duplex mismatch\n",
1276 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1277 switch (aux & PHY_B_AS_PAUSE_MSK) {
1278 case PHY_B_AS_PAUSE_MSK:
1279 skge->flow_status = FLOW_STAT_SYMMETRIC;
1282 skge->flow_status = FLOW_STAT_REM_SEND;
1285 skge->flow_status = FLOW_STAT_LOC_SEND;
1288 skge->flow_status = FLOW_STAT_NONE;
1290 skge->speed = SPEED_1000;
1293 if (!netif_carrier_ok(dev))
1294 genesis_link_up(skge);
1297 /* Broadcom 5400 only supports giagabit! SysKonnect did not put an additional
1298 * Phy on for 100 or 10Mbit operation
1300 static void bcom_phy_init(struct skge_port *skge)
1302 struct skge_hw *hw = skge->hw;
1303 int port = skge->port;
1305 u16 id1, r, ext, ctl;
1307 /* magic workaround patterns for Broadcom */
1308 static const struct {
1312 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 },
1313 { 0x17, 0x0013 }, { 0x15, 0x0404 }, { 0x17, 0x8006 },
1314 { 0x15, 0x0132 }, { 0x17, 0x8006 }, { 0x15, 0x0232 },
1315 { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
1317 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1204 },
1318 { 0x17, 0x0013 }, { 0x15, 0x0A04 }, { 0x18, 0x0420 },
1321 /* read Id from external PHY (all have the same address) */
1322 id1 = xm_phy_read(hw, port, PHY_XMAC_ID1);
1324 /* Optimize MDIO transfer by suppressing preamble. */
1325 r = xm_read16(hw, port, XM_MMU_CMD);
1327 xm_write16(hw, port, XM_MMU_CMD,r);
1330 case PHY_BCOM_ID1_C0:
1332 * Workaround BCOM Errata for the C0 type.
1333 * Write magic patterns to reserved registers.
1335 for (i = 0; i < ARRAY_SIZE(C0hack); i++)
1336 xm_phy_write(hw, port,
1337 C0hack[i].reg, C0hack[i].val);
1340 case PHY_BCOM_ID1_A1:
1342 * Workaround BCOM Errata for the A1 type.
1343 * Write magic patterns to reserved registers.
1345 for (i = 0; i < ARRAY_SIZE(A1hack); i++)
1346 xm_phy_write(hw, port,
1347 A1hack[i].reg, A1hack[i].val);
1352 * Workaround BCOM Errata (#10523) for all BCom PHYs.
1353 * Disable Power Management after reset.
1355 r = xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL);
1356 r |= PHY_B_AC_DIS_PM;
1357 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, r);
1360 xm_read16(hw, port, XM_ISRC);
1362 ext = PHY_B_PEC_EN_LTR; /* enable tx led */
1363 ctl = PHY_CT_SP1000; /* always 1000mbit */
1365 if (skge->autoneg == AUTONEG_ENABLE) {
1367 * Workaround BCOM Errata #1 for the C5 type.
1368 * 1000Base-T Link Acquisition Failure in Slave Mode
1369 * Set Repeater/DTE bit 10 of the 1000Base-T Control Register
1371 u16 adv = PHY_B_1000C_RD;
1372 if (skge->advertising & ADVERTISED_1000baseT_Half)
1373 adv |= PHY_B_1000C_AHD;
1374 if (skge->advertising & ADVERTISED_1000baseT_Full)
1375 adv |= PHY_B_1000C_AFD;
1376 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, adv);
1378 ctl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1380 if (skge->duplex == DUPLEX_FULL)
1381 ctl |= PHY_CT_DUP_MD;
1382 /* Force to slave */
1383 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, PHY_B_1000C_MSE);
1386 /* Set autonegotiation pause parameters */
1387 xm_phy_write(hw, port, PHY_BCOM_AUNE_ADV,
1388 phy_pause_map[skge->flow_control] | PHY_AN_CSMA);
1390 /* Handle Jumbo frames */
1391 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
1392 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1393 PHY_B_AC_TX_TST | PHY_B_AC_LONG_PACK);
1395 ext |= PHY_B_PEC_HIGH_LA;
1399 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ext);
1400 xm_phy_write(hw, port, PHY_BCOM_CTRL, ctl);
1402 /* Use link status change interrupt */
1403 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1406 static void xm_phy_init(struct skge_port *skge)
1408 struct skge_hw *hw = skge->hw;
1409 int port = skge->port;
1412 if (skge->autoneg == AUTONEG_ENABLE) {
1413 if (skge->advertising & ADVERTISED_1000baseT_Half)
1414 ctrl |= PHY_X_AN_HD;
1415 if (skge->advertising & ADVERTISED_1000baseT_Full)
1416 ctrl |= PHY_X_AN_FD;
1418 ctrl |= fiber_pause_map[skge->flow_control];
1420 xm_phy_write(hw, port, PHY_XMAC_AUNE_ADV, ctrl);
1422 /* Restart Auto-negotiation */
1423 ctrl = PHY_CT_ANE | PHY_CT_RE_CFG;
1425 /* Set DuplexMode in Config register */
1426 if (skge->duplex == DUPLEX_FULL)
1427 ctrl |= PHY_CT_DUP_MD;
1429 * Do NOT enable Auto-negotiation here. This would hold
1430 * the link down because no IDLEs are transmitted
1434 xm_phy_write(hw, port, PHY_XMAC_CTRL, ctrl);
1436 /* Poll PHY for status changes */
1437 mod_timer(&skge->link_timer, jiffies + LINK_HZ);
1440 static int xm_check_link(struct net_device *dev)
1442 struct skge_port *skge = netdev_priv(dev);
1443 struct skge_hw *hw = skge->hw;
1444 int port = skge->port;
1447 /* read twice because of latch */
1448 xm_phy_read(hw, port, PHY_XMAC_STAT);
1449 status = xm_phy_read(hw, port, PHY_XMAC_STAT);
1451 if ((status & PHY_ST_LSYNC) == 0) {
1452 xm_link_down(hw, port);
1456 if (skge->autoneg == AUTONEG_ENABLE) {
1459 if (!(status & PHY_ST_AN_OVER))
1462 lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP);
1463 if (lpa & PHY_B_AN_RF) {
1464 printk(KERN_NOTICE PFX "%s: remote fault\n",
1469 res = xm_phy_read(hw, port, PHY_XMAC_RES_ABI);
1471 /* Check Duplex mismatch */
1472 switch (res & (PHY_X_RS_HD | PHY_X_RS_FD)) {
1474 skge->duplex = DUPLEX_FULL;
1477 skge->duplex = DUPLEX_HALF;
1480 printk(KERN_NOTICE PFX "%s: duplex mismatch\n",
1485 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1486 if ((skge->flow_control == FLOW_MODE_SYMMETRIC ||
1487 skge->flow_control == FLOW_MODE_SYM_OR_REM) &&
1488 (lpa & PHY_X_P_SYM_MD))
1489 skge->flow_status = FLOW_STAT_SYMMETRIC;
1490 else if (skge->flow_control == FLOW_MODE_SYM_OR_REM &&
1491 (lpa & PHY_X_RS_PAUSE) == PHY_X_P_ASYM_MD)
1492 /* Enable PAUSE receive, disable PAUSE transmit */
1493 skge->flow_status = FLOW_STAT_REM_SEND;
1494 else if (skge->flow_control == FLOW_MODE_LOC_SEND &&
1495 (lpa & PHY_X_RS_PAUSE) == PHY_X_P_BOTH_MD)
1496 /* Disable PAUSE receive, enable PAUSE transmit */
1497 skge->flow_status = FLOW_STAT_LOC_SEND;
1499 skge->flow_status = FLOW_STAT_NONE;
1501 skge->speed = SPEED_1000;
1504 if (!netif_carrier_ok(dev))
1505 genesis_link_up(skge);
1509 /* Poll to check for link coming up.
1511 * Since internal PHY is wired to a level triggered pin, can't
1512 * get an interrupt when carrier is detected, need to poll for
1515 static void xm_link_timer(unsigned long arg)
1517 struct skge_port *skge = (struct skge_port *) arg;
1518 struct net_device *dev = skge->netdev;
1519 struct skge_hw *hw = skge->hw;
1520 int port = skge->port;
1522 unsigned long flags;
1524 if (!netif_running(dev))
1527 spin_lock_irqsave(&hw->phy_lock, flags);
1530 * Verify that the link by checking GPIO register three times.
1531 * This pin has the signal from the link_sync pin connected to it.
1533 for (i = 0; i < 3; i++) {
1534 if (xm_read16(hw, port, XM_GP_PORT) & XM_GP_INP_ASS)
1538 /* Re-enable interrupt to detect link down */
1539 if (xm_check_link(dev)) {
1540 u16 msk = xm_read16(hw, port, XM_IMSK);
1541 msk &= ~XM_IS_INP_ASS;
1542 xm_write16(hw, port, XM_IMSK, msk);
1543 xm_read16(hw, port, XM_ISRC);
1546 mod_timer(&skge->link_timer,
1547 round_jiffies(jiffies + LINK_HZ));
1549 spin_unlock_irqrestore(&hw->phy_lock, flags);
1552 static void genesis_mac_init(struct skge_hw *hw, int port)
1554 struct net_device *dev = hw->dev[port];
1555 struct skge_port *skge = netdev_priv(dev);
1556 int jumbo = hw->dev[port]->mtu > ETH_DATA_LEN;
1559 const u8 zero[6] = { 0 };
1561 for (i = 0; i < 10; i++) {
1562 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
1564 if (skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST)
1569 printk(KERN_WARNING PFX "%s: genesis reset failed\n", dev->name);
1572 /* Unreset the XMAC. */
1573 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
1576 * Perform additional initialization for external PHYs,
1577 * namely for the 1000baseTX cards that use the XMAC's
1580 if (hw->phy_type != SK_PHY_XMAC) {
1581 /* Take external Phy out of reset */
1582 r = skge_read32(hw, B2_GP_IO);
1584 r |= GP_DIR_0|GP_IO_0;
1586 r |= GP_DIR_2|GP_IO_2;
1588 skge_write32(hw, B2_GP_IO, r);
1590 /* Enable GMII interface */
1591 xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD);
1595 switch(hw->phy_type) {
1600 bcom_phy_init(skge);
1601 bcom_check_link(hw, port);
1604 /* Set Station Address */
1605 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
1607 /* We don't use match addresses so clear */
1608 for (i = 1; i < 16; i++)
1609 xm_outaddr(hw, port, XM_EXM(i), zero);
1611 /* Clear MIB counters */
1612 xm_write16(hw, port, XM_STAT_CMD,
1613 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1614 /* Clear two times according to Errata #3 */
1615 xm_write16(hw, port, XM_STAT_CMD,
1616 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1618 /* configure Rx High Water Mark (XM_RX_HI_WM) */
1619 xm_write16(hw, port, XM_RX_HI_WM, 1450);
1621 /* We don't need the FCS appended to the packet. */
1622 r = XM_RX_LENERR_OK | XM_RX_STRIP_FCS;
1624 r |= XM_RX_BIG_PK_OK;
1626 if (skge->duplex == DUPLEX_HALF) {
1628 * If in manual half duplex mode the other side might be in
1629 * full duplex mode, so ignore if a carrier extension is not seen
1630 * on frames received
1632 r |= XM_RX_DIS_CEXT;
1634 xm_write16(hw, port, XM_RX_CMD, r);
1636 /* We want short frames padded to 60 bytes. */
1637 xm_write16(hw, port, XM_TX_CMD, XM_TX_AUTO_PAD);
1639 /* Increase threshold for jumbo frames on dual port */
1640 if (hw->ports > 1 && jumbo)
1641 xm_write16(hw, port, XM_TX_THR, 1020);
1643 xm_write16(hw, port, XM_TX_THR, 512);
1646 * Enable the reception of all error frames. This is is
1647 * a necessary evil due to the design of the XMAC. The
1648 * XMAC's receive FIFO is only 8K in size, however jumbo
1649 * frames can be up to 9000 bytes in length. When bad
1650 * frame filtering is enabled, the XMAC's RX FIFO operates
1651 * in 'store and forward' mode. For this to work, the
1652 * entire frame has to fit into the FIFO, but that means
1653 * that jumbo frames larger than 8192 bytes will be
1654 * truncated. Disabling all bad frame filtering causes
1655 * the RX FIFO to operate in streaming mode, in which
1656 * case the XMAC will start transferring frames out of the
1657 * RX FIFO as soon as the FIFO threshold is reached.
1659 xm_write32(hw, port, XM_MODE, XM_DEF_MODE);
1663 * Initialize the Receive Counter Event Mask (XM_RX_EV_MSK)
1664 * - Enable all bits excepting 'Octets Rx OK Low CntOv'
1665 * and 'Octets Rx OK Hi Cnt Ov'.
1667 xm_write32(hw, port, XM_RX_EV_MSK, XMR_DEF_MSK);
1670 * Initialize the Transmit Counter Event Mask (XM_TX_EV_MSK)
1671 * - Enable all bits excepting 'Octets Tx OK Low CntOv'
1672 * and 'Octets Tx OK Hi Cnt Ov'.
1674 xm_write32(hw, port, XM_TX_EV_MSK, XMT_DEF_MSK);
1676 /* Configure MAC arbiter */
1677 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
1679 /* configure timeout values */
1680 skge_write8(hw, B3_MA_TOINI_RX1, 72);
1681 skge_write8(hw, B3_MA_TOINI_RX2, 72);
1682 skge_write8(hw, B3_MA_TOINI_TX1, 72);
1683 skge_write8(hw, B3_MA_TOINI_TX2, 72);
1685 skge_write8(hw, B3_MA_RCINI_RX1, 0);
1686 skge_write8(hw, B3_MA_RCINI_RX2, 0);
1687 skge_write8(hw, B3_MA_RCINI_TX1, 0);
1688 skge_write8(hw, B3_MA_RCINI_TX2, 0);
1690 /* Configure Rx MAC FIFO */
1691 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_CLR);
1692 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_TIM_PAT);
1693 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_ENA_OP_MD);
1695 /* Configure Tx MAC FIFO */
1696 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_CLR);
1697 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF);
1698 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_ENA_OP_MD);
1701 /* Enable frame flushing if jumbo frames used */
1702 skge_write16(hw, SK_REG(port,RX_MFF_CTRL1), MFF_ENA_FLUSH);
1704 /* enable timeout timers if normal frames */
1705 skge_write16(hw, B3_PA_CTRL,
1706 (port == 0) ? PA_ENA_TO_TX1 : PA_ENA_TO_TX2);
1710 static void genesis_stop(struct skge_port *skge)
1712 struct skge_hw *hw = skge->hw;
1713 int port = skge->port;
1714 unsigned retries = 1000;
1717 /* Disable Tx and Rx */
1718 cmd = xm_read16(hw, port, XM_MMU_CMD);
1719 cmd &= ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1720 xm_write16(hw, port, XM_MMU_CMD, cmd);
1722 genesis_reset(hw, port);
1724 /* Clear Tx packet arbiter timeout IRQ */
1725 skge_write16(hw, B3_PA_CTRL,
1726 port == 0 ? PA_CLR_TO_TX1 : PA_CLR_TO_TX2);
1729 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
1731 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_SET_MAC_RST);
1732 if (!(skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST))
1734 } while (--retries > 0);
1736 /* For external PHYs there must be special handling */
1737 if (hw->phy_type != SK_PHY_XMAC) {
1738 u32 reg = skge_read32(hw, B2_GP_IO);
1746 skge_write32(hw, B2_GP_IO, reg);
1747 skge_read32(hw, B2_GP_IO);
1750 xm_write16(hw, port, XM_MMU_CMD,
1751 xm_read16(hw, port, XM_MMU_CMD)
1752 & ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX));
1754 xm_read16(hw, port, XM_MMU_CMD);
1758 static void genesis_get_stats(struct skge_port *skge, u64 *data)
1760 struct skge_hw *hw = skge->hw;
1761 int port = skge->port;
1763 unsigned long timeout = jiffies + HZ;
1765 xm_write16(hw, port,
1766 XM_STAT_CMD, XM_SC_SNP_TXC | XM_SC_SNP_RXC);
1768 /* wait for update to complete */
1769 while (xm_read16(hw, port, XM_STAT_CMD)
1770 & (XM_SC_SNP_TXC | XM_SC_SNP_RXC)) {
1771 if (time_after(jiffies, timeout))
1776 /* special case for 64 bit octet counter */
1777 data[0] = (u64) xm_read32(hw, port, XM_TXO_OK_HI) << 32
1778 | xm_read32(hw, port, XM_TXO_OK_LO);
1779 data[1] = (u64) xm_read32(hw, port, XM_RXO_OK_HI) << 32
1780 | xm_read32(hw, port, XM_RXO_OK_LO);
1782 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
1783 data[i] = xm_read32(hw, port, skge_stats[i].xmac_offset);
1786 static void genesis_mac_intr(struct skge_hw *hw, int port)
1788 struct net_device *dev = hw->dev[port];
1789 struct skge_port *skge = netdev_priv(dev);
1790 u16 status = xm_read16(hw, port, XM_ISRC);
1792 netif_printk(skge, intr, KERN_DEBUG, skge->netdev,
1793 "mac interrupt status 0x%x\n", status);
1795 if (hw->phy_type == SK_PHY_XMAC && (status & XM_IS_INP_ASS)) {
1796 xm_link_down(hw, port);
1797 mod_timer(&skge->link_timer, jiffies + 1);
1800 if (status & XM_IS_TXF_UR) {
1801 xm_write32(hw, port, XM_MODE, XM_MD_FTF);
1802 ++dev->stats.tx_fifo_errors;
1806 static void genesis_link_up(struct skge_port *skge)
1808 struct skge_hw *hw = skge->hw;
1809 int port = skge->port;
1813 cmd = xm_read16(hw, port, XM_MMU_CMD);
1816 * enabling pause frame reception is required for 1000BT
1817 * because the XMAC is not reset if the link is going down
1819 if (skge->flow_status == FLOW_STAT_NONE ||
1820 skge->flow_status == FLOW_STAT_LOC_SEND)
1821 /* Disable Pause Frame Reception */
1822 cmd |= XM_MMU_IGN_PF;
1824 /* Enable Pause Frame Reception */
1825 cmd &= ~XM_MMU_IGN_PF;
1827 xm_write16(hw, port, XM_MMU_CMD, cmd);
1829 mode = xm_read32(hw, port, XM_MODE);
1830 if (skge->flow_status== FLOW_STAT_SYMMETRIC ||
1831 skge->flow_status == FLOW_STAT_LOC_SEND) {
1833 * Configure Pause Frame Generation
1834 * Use internal and external Pause Frame Generation.
1835 * Sending pause frames is edge triggered.
1836 * Send a Pause frame with the maximum pause time if
1837 * internal oder external FIFO full condition occurs.
1838 * Send a zero pause time frame to re-start transmission.
1840 /* XM_PAUSE_DA = '010000C28001' (default) */
1841 /* XM_MAC_PTIME = 0xffff (maximum) */
1842 /* remember this value is defined in big endian (!) */
1843 xm_write16(hw, port, XM_MAC_PTIME, 0xffff);
1845 mode |= XM_PAUSE_MODE;
1846 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_PAUSE);
1849 * disable pause frame generation is required for 1000BT
1850 * because the XMAC is not reset if the link is going down
1852 /* Disable Pause Mode in Mode Register */
1853 mode &= ~XM_PAUSE_MODE;
1855 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_DIS_PAUSE);
1858 xm_write32(hw, port, XM_MODE, mode);
1860 /* Turn on detection of Tx underrun */
1861 msk = xm_read16(hw, port, XM_IMSK);
1862 msk &= ~XM_IS_TXF_UR;
1863 xm_write16(hw, port, XM_IMSK, msk);
1865 xm_read16(hw, port, XM_ISRC);
1867 /* get MMU Command Reg. */
1868 cmd = xm_read16(hw, port, XM_MMU_CMD);
1869 if (hw->phy_type != SK_PHY_XMAC && skge->duplex == DUPLEX_FULL)
1870 cmd |= XM_MMU_GMII_FD;
1873 * Workaround BCOM Errata (#10523) for all BCom Phys
1874 * Enable Power Management after link up
1876 if (hw->phy_type == SK_PHY_BCOM) {
1877 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1878 xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL)
1879 & ~PHY_B_AC_DIS_PM);
1880 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1884 xm_write16(hw, port, XM_MMU_CMD,
1885 cmd | XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1890 static inline void bcom_phy_intr(struct skge_port *skge)
1892 struct skge_hw *hw = skge->hw;
1893 int port = skge->port;
1896 isrc = xm_phy_read(hw, port, PHY_BCOM_INT_STAT);
1897 netif_printk(skge, intr, KERN_DEBUG, skge->netdev,
1898 "phy interrupt status 0x%x\n", isrc);
1900 if (isrc & PHY_B_IS_PSE)
1901 printk(KERN_ERR PFX "%s: uncorrectable pair swap error\n",
1902 hw->dev[port]->name);
1904 /* Workaround BCom Errata:
1905 * enable and disable loopback mode if "NO HCD" occurs.
1907 if (isrc & PHY_B_IS_NO_HDCL) {
1908 u16 ctrl = xm_phy_read(hw, port, PHY_BCOM_CTRL);
1909 xm_phy_write(hw, port, PHY_BCOM_CTRL,
1910 ctrl | PHY_CT_LOOP);
1911 xm_phy_write(hw, port, PHY_BCOM_CTRL,
1912 ctrl & ~PHY_CT_LOOP);
1915 if (isrc & (PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE))
1916 bcom_check_link(hw, port);
1920 static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
1924 gma_write16(hw, port, GM_SMI_DATA, val);
1925 gma_write16(hw, port, GM_SMI_CTRL,
1926 GM_SMI_CT_PHY_AD(hw->phy_addr) | GM_SMI_CT_REG_AD(reg));
1927 for (i = 0; i < PHY_RETRIES; i++) {
1930 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
1934 printk(KERN_WARNING PFX "%s: phy write timeout\n",
1935 hw->dev[port]->name);
1939 static int __gm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
1943 gma_write16(hw, port, GM_SMI_CTRL,
1944 GM_SMI_CT_PHY_AD(hw->phy_addr)
1945 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
1947 for (i = 0; i < PHY_RETRIES; i++) {
1949 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL)
1955 *val = gma_read16(hw, port, GM_SMI_DATA);
1959 static u16 gm_phy_read(struct skge_hw *hw, int port, u16 reg)
1962 if (__gm_phy_read(hw, port, reg, &v))
1963 printk(KERN_WARNING PFX "%s: phy read timeout\n",
1964 hw->dev[port]->name);
1968 /* Marvell Phy Initialization */
1969 static void yukon_init(struct skge_hw *hw, int port)
1971 struct skge_port *skge = netdev_priv(hw->dev[port]);
1972 u16 ctrl, ct1000, adv;
1974 if (skge->autoneg == AUTONEG_ENABLE) {
1975 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
1977 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
1978 PHY_M_EC_MAC_S_MSK);
1979 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
1981 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
1983 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
1986 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
1987 if (skge->autoneg == AUTONEG_DISABLE)
1988 ctrl &= ~PHY_CT_ANE;
1990 ctrl |= PHY_CT_RESET;
1991 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
1997 if (skge->autoneg == AUTONEG_ENABLE) {
1999 if (skge->advertising & ADVERTISED_1000baseT_Full)
2000 ct1000 |= PHY_M_1000C_AFD;
2001 if (skge->advertising & ADVERTISED_1000baseT_Half)
2002 ct1000 |= PHY_M_1000C_AHD;
2003 if (skge->advertising & ADVERTISED_100baseT_Full)
2004 adv |= PHY_M_AN_100_FD;
2005 if (skge->advertising & ADVERTISED_100baseT_Half)
2006 adv |= PHY_M_AN_100_HD;
2007 if (skge->advertising & ADVERTISED_10baseT_Full)
2008 adv |= PHY_M_AN_10_FD;
2009 if (skge->advertising & ADVERTISED_10baseT_Half)
2010 adv |= PHY_M_AN_10_HD;
2012 /* Set Flow-control capabilities */
2013 adv |= phy_pause_map[skge->flow_control];
2015 if (skge->advertising & ADVERTISED_1000baseT_Full)
2016 adv |= PHY_M_AN_1000X_AFD;
2017 if (skge->advertising & ADVERTISED_1000baseT_Half)
2018 adv |= PHY_M_AN_1000X_AHD;
2020 adv |= fiber_pause_map[skge->flow_control];
2023 /* Restart Auto-negotiation */
2024 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
2026 /* forced speed/duplex settings */
2027 ct1000 = PHY_M_1000C_MSE;
2029 if (skge->duplex == DUPLEX_FULL)
2030 ctrl |= PHY_CT_DUP_MD;
2032 switch (skge->speed) {
2034 ctrl |= PHY_CT_SP1000;
2037 ctrl |= PHY_CT_SP100;
2041 ctrl |= PHY_CT_RESET;
2044 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
2046 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
2047 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
2049 /* Enable phy interrupt on autonegotiation complete (or link up) */
2050 if (skge->autoneg == AUTONEG_ENABLE)
2051 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_MSK);
2053 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
2056 static void yukon_reset(struct skge_hw *hw, int port)
2058 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);/* disable PHY IRQs */
2059 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
2060 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
2061 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
2062 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
2064 gma_write16(hw, port, GM_RX_CTRL,
2065 gma_read16(hw, port, GM_RX_CTRL)
2066 | GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2069 /* Apparently, early versions of Yukon-Lite had wrong chip_id? */
2070 static int is_yukon_lite_a0(struct skge_hw *hw)
2075 if (hw->chip_id != CHIP_ID_YUKON)
2078 reg = skge_read32(hw, B2_FAR);
2079 skge_write8(hw, B2_FAR + 3, 0xff);
2080 ret = (skge_read8(hw, B2_FAR + 3) != 0);
2081 skge_write32(hw, B2_FAR, reg);
2085 static void yukon_mac_init(struct skge_hw *hw, int port)
2087 struct skge_port *skge = netdev_priv(hw->dev[port]);
2090 const u8 *addr = hw->dev[port]->dev_addr;
2092 /* WA code for COMA mode -- set PHY reset */
2093 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
2094 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
2095 reg = skge_read32(hw, B2_GP_IO);
2096 reg |= GP_DIR_9 | GP_IO_9;
2097 skge_write32(hw, B2_GP_IO, reg);
2101 skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
2102 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
2104 /* WA code for COMA mode -- clear PHY reset */
2105 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
2106 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
2107 reg = skge_read32(hw, B2_GP_IO);
2110 skge_write32(hw, B2_GP_IO, reg);
2113 /* Set hardware config mode */
2114 reg = GPC_INT_POL_HI | GPC_DIS_FC | GPC_DIS_SLEEP |
2115 GPC_ENA_XC | GPC_ANEG_ADV_ALL_M | GPC_ENA_PAUSE;
2116 reg |= hw->copper ? GPC_HWCFG_GMII_COP : GPC_HWCFG_GMII_FIB;
2118 /* Clear GMC reset */
2119 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_SET);
2120 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_CLR);
2121 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR);
2123 if (skge->autoneg == AUTONEG_DISABLE) {
2124 reg = GM_GPCR_AU_ALL_DIS;
2125 gma_write16(hw, port, GM_GP_CTRL,
2126 gma_read16(hw, port, GM_GP_CTRL) | reg);
2128 switch (skge->speed) {
2130 reg &= ~GM_GPCR_SPEED_100;
2131 reg |= GM_GPCR_SPEED_1000;
2134 reg &= ~GM_GPCR_SPEED_1000;
2135 reg |= GM_GPCR_SPEED_100;
2138 reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
2142 if (skge->duplex == DUPLEX_FULL)
2143 reg |= GM_GPCR_DUP_FULL;
2145 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
2147 switch (skge->flow_control) {
2148 case FLOW_MODE_NONE:
2149 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2150 reg |= GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
2152 case FLOW_MODE_LOC_SEND:
2153 /* disable Rx flow-control */
2154 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
2156 case FLOW_MODE_SYMMETRIC:
2157 case FLOW_MODE_SYM_OR_REM:
2158 /* enable Tx & Rx flow-control */
2162 gma_write16(hw, port, GM_GP_CTRL, reg);
2163 skge_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
2165 yukon_init(hw, port);
2168 reg = gma_read16(hw, port, GM_PHY_ADDR);
2169 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
2171 for (i = 0; i < GM_MIB_CNT_SIZE; i++)
2172 gma_read16(hw, port, GM_MIB_CNT_BASE + 8*i);
2173 gma_write16(hw, port, GM_PHY_ADDR, reg);
2175 /* transmit control */
2176 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
2178 /* receive control reg: unicast + multicast + no FCS */
2179 gma_write16(hw, port, GM_RX_CTRL,
2180 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
2182 /* transmit flow control */
2183 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
2185 /* transmit parameter */
2186 gma_write16(hw, port, GM_TX_PARAM,
2187 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
2188 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
2189 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF));
2191 /* configure the Serial Mode Register */
2192 reg = DATA_BLIND_VAL(DATA_BLIND_DEF)
2194 | IPG_DATA_VAL(IPG_DATA_DEF);
2196 if (hw->dev[port]->mtu > ETH_DATA_LEN)
2197 reg |= GM_SMOD_JUMBO_ENA;
2199 gma_write16(hw, port, GM_SERIAL_MODE, reg);
2201 /* physical address: used for pause frames */
2202 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
2203 /* virtual address for data */
2204 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
2206 /* enable interrupt mask for counter overflows */
2207 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
2208 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
2209 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
2211 /* Initialize Mac Fifo */
2213 /* Configure Rx MAC FIFO */
2214 skge_write16(hw, SK_REG(port, RX_GMF_FL_MSK), RX_FF_FL_DEF_MSK);
2215 reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
2217 /* disable Rx GMAC FIFO Flush for YUKON-Lite Rev. A0 only */
2218 if (is_yukon_lite_a0(hw))
2219 reg &= ~GMF_RX_F_FL_ON;
2221 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
2222 skge_write16(hw, SK_REG(port, RX_GMF_CTRL_T), reg);
2224 * because Pause Packet Truncation in GMAC is not working
2225 * we have to increase the Flush Threshold to 64 bytes
2226 * in order to flush pause packets in Rx FIFO on Yukon-1
2228 skge_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
2230 /* Configure Tx MAC FIFO */
2231 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
2232 skge_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
2235 /* Go into power down mode */
2236 static void yukon_suspend(struct skge_hw *hw, int port)
2240 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
2241 ctrl |= PHY_M_PC_POL_R_DIS;
2242 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
2244 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
2245 ctrl |= PHY_CT_RESET;
2246 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
2248 /* switch IEEE compatible power down mode on */
2249 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
2250 ctrl |= PHY_CT_PDOWN;
2251 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
2254 static void yukon_stop(struct skge_port *skge)
2256 struct skge_hw *hw = skge->hw;
2257 int port = skge->port;
2259 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
2260 yukon_reset(hw, port);
2262 gma_write16(hw, port, GM_GP_CTRL,
2263 gma_read16(hw, port, GM_GP_CTRL)
2264 & ~(GM_GPCR_TX_ENA|GM_GPCR_RX_ENA));
2265 gma_read16(hw, port, GM_GP_CTRL);
2267 yukon_suspend(hw, port);
2269 /* set GPHY Control reset */
2270 skge_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
2271 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
2274 static void yukon_get_stats(struct skge_port *skge, u64 *data)
2276 struct skge_hw *hw = skge->hw;
2277 int port = skge->port;
2280 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
2281 | gma_read32(hw, port, GM_TXO_OK_LO);
2282 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
2283 | gma_read32(hw, port, GM_RXO_OK_LO);
2285 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
2286 data[i] = gma_read32(hw, port,
2287 skge_stats[i].gma_offset);
2290 static void yukon_mac_intr(struct skge_hw *hw, int port)
2292 struct net_device *dev = hw->dev[port];
2293 struct skge_port *skge = netdev_priv(dev);
2294 u8 status = skge_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2296 netif_printk(skge, intr, KERN_DEBUG, skge->netdev,
2297 "mac interrupt status 0x%x\n", status);
2299 if (status & GM_IS_RX_FF_OR) {
2300 ++dev->stats.rx_fifo_errors;
2301 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2304 if (status & GM_IS_TX_FF_UR) {
2305 ++dev->stats.tx_fifo_errors;
2306 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2311 static u16 yukon_speed(const struct skge_hw *hw, u16 aux)
2313 switch (aux & PHY_M_PS_SPEED_MSK) {
2314 case PHY_M_PS_SPEED_1000:
2316 case PHY_M_PS_SPEED_100:
2323 static void yukon_link_up(struct skge_port *skge)
2325 struct skge_hw *hw = skge->hw;
2326 int port = skge->port;
2329 /* Enable Transmit FIFO Underrun */
2330 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
2332 reg = gma_read16(hw, port, GM_GP_CTRL);
2333 if (skge->duplex == DUPLEX_FULL || skge->autoneg == AUTONEG_ENABLE)
2334 reg |= GM_GPCR_DUP_FULL;
2337 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
2338 gma_write16(hw, port, GM_GP_CTRL, reg);
2340 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
2344 static void yukon_link_down(struct skge_port *skge)
2346 struct skge_hw *hw = skge->hw;
2347 int port = skge->port;
2350 ctrl = gma_read16(hw, port, GM_GP_CTRL);
2351 ctrl &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
2352 gma_write16(hw, port, GM_GP_CTRL, ctrl);
2354 if (skge->flow_status == FLOW_STAT_REM_SEND) {
2355 ctrl = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
2356 ctrl |= PHY_M_AN_ASP;
2357 /* restore Asymmetric Pause bit */
2358 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, ctrl);
2361 skge_link_down(skge);
2363 yukon_init(hw, port);
2366 static void yukon_phy_intr(struct skge_port *skge)
2368 struct skge_hw *hw = skge->hw;
2369 int port = skge->port;
2370 const char *reason = NULL;
2371 u16 istatus, phystat;
2373 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
2374 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
2376 netif_printk(skge, intr, KERN_DEBUG, skge->netdev,
2377 "phy interrupt status 0x%x 0x%x\n", istatus, phystat);
2379 if (istatus & PHY_M_IS_AN_COMPL) {
2380 if (gm_phy_read(hw, port, PHY_MARV_AUNE_LP)
2382 reason = "remote fault";
2386 if (gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
2387 reason = "master/slave fault";
2391 if (!(phystat & PHY_M_PS_SPDUP_RES)) {
2392 reason = "speed/duplex";
2396 skge->duplex = (phystat & PHY_M_PS_FULL_DUP)
2397 ? DUPLEX_FULL : DUPLEX_HALF;
2398 skge->speed = yukon_speed(hw, phystat);
2400 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
2401 switch (phystat & PHY_M_PS_PAUSE_MSK) {
2402 case PHY_M_PS_PAUSE_MSK:
2403 skge->flow_status = FLOW_STAT_SYMMETRIC;
2405 case PHY_M_PS_RX_P_EN:
2406 skge->flow_status = FLOW_STAT_REM_SEND;
2408 case PHY_M_PS_TX_P_EN:
2409 skge->flow_status = FLOW_STAT_LOC_SEND;
2412 skge->flow_status = FLOW_STAT_NONE;
2415 if (skge->flow_status == FLOW_STAT_NONE ||
2416 (skge->speed < SPEED_1000 && skge->duplex == DUPLEX_HALF))
2417 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2419 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
2420 yukon_link_up(skge);
2424 if (istatus & PHY_M_IS_LSP_CHANGE)
2425 skge->speed = yukon_speed(hw, phystat);
2427 if (istatus & PHY_M_IS_DUP_CHANGE)
2428 skge->duplex = (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2429 if (istatus & PHY_M_IS_LST_CHANGE) {
2430 if (phystat & PHY_M_PS_LINK_UP)
2431 yukon_link_up(skge);
2433 yukon_link_down(skge);
2437 printk(KERN_ERR PFX "%s: autonegotiation failed (%s)\n",
2438 skge->netdev->name, reason);
2440 /* XXX restart autonegotiation? */
2443 static void skge_phy_reset(struct skge_port *skge)
2445 struct skge_hw *hw = skge->hw;
2446 int port = skge->port;
2447 struct net_device *dev = hw->dev[port];
2449 netif_stop_queue(skge->netdev);
2450 netif_carrier_off(skge->netdev);
2452 spin_lock_bh(&hw->phy_lock);
2453 if (hw->chip_id == CHIP_ID_GENESIS) {
2454 genesis_reset(hw, port);
2455 genesis_mac_init(hw, port);
2457 yukon_reset(hw, port);
2458 yukon_init(hw, port);
2460 spin_unlock_bh(&hw->phy_lock);
2462 skge_set_multicast(dev);
2465 /* Basic MII support */
2466 static int skge_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2468 struct mii_ioctl_data *data = if_mii(ifr);
2469 struct skge_port *skge = netdev_priv(dev);
2470 struct skge_hw *hw = skge->hw;
2471 int err = -EOPNOTSUPP;
2473 if (!netif_running(dev))
2474 return -ENODEV; /* Phy still in reset */
2478 data->phy_id = hw->phy_addr;
2483 spin_lock_bh(&hw->phy_lock);
2484 if (hw->chip_id == CHIP_ID_GENESIS)
2485 err = __xm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
2487 err = __gm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
2488 spin_unlock_bh(&hw->phy_lock);
2489 data->val_out = val;
2494 spin_lock_bh(&hw->phy_lock);
2495 if (hw->chip_id == CHIP_ID_GENESIS)
2496 err = xm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2499 err = gm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2501 spin_unlock_bh(&hw->phy_lock);
2507 static void skge_ramset(struct skge_hw *hw, u16 q, u32 start, size_t len)
2513 end = start + len - 1;
2515 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
2516 skge_write32(hw, RB_ADDR(q, RB_START), start);
2517 skge_write32(hw, RB_ADDR(q, RB_WP), start);
2518 skge_write32(hw, RB_ADDR(q, RB_RP), start);
2519 skge_write32(hw, RB_ADDR(q, RB_END), end);
2521 if (q == Q_R1 || q == Q_R2) {
2522 /* Set thresholds on receive queue's */
2523 skge_write32(hw, RB_ADDR(q, RB_RX_UTPP),
2525 skge_write32(hw, RB_ADDR(q, RB_RX_LTPP),
2528 /* Enable store & forward on Tx queue's because
2529 * Tx FIFO is only 4K on Genesis and 1K on Yukon
2531 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
2534 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
2537 /* Setup Bus Memory Interface */
2538 static void skge_qset(struct skge_port *skge, u16 q,
2539 const struct skge_element *e)
2541 struct skge_hw *hw = skge->hw;
2542 u32 watermark = 0x600;
2543 u64 base = skge->dma + (e->desc - skge->mem);
2545 /* optimization to reduce window on 32bit/33mhz */
2546 if ((skge_read16(hw, B0_CTST) & (CS_BUS_CLOCK | CS_BUS_SLOT_SZ)) == 0)
2549 skge_write32(hw, Q_ADDR(q, Q_CSR), CSR_CLR_RESET);
2550 skge_write32(hw, Q_ADDR(q, Q_F), watermark);
2551 skge_write32(hw, Q_ADDR(q, Q_DA_H), (u32)(base >> 32));
2552 skge_write32(hw, Q_ADDR(q, Q_DA_L), (u32)base);
2555 static int skge_up(struct net_device *dev)
2557 struct skge_port *skge = netdev_priv(dev);
2558 struct skge_hw *hw = skge->hw;
2559 int port = skge->port;
2560 u32 chunk, ram_addr;
2561 size_t rx_size, tx_size;
2564 if (!is_valid_ether_addr(dev->dev_addr))
2567 netif_info(skge, ifup, skge->netdev, "enabling interface\n");
2569 if (dev->mtu > RX_BUF_SIZE)
2570 skge->rx_buf_size = dev->mtu + ETH_HLEN;
2572 skge->rx_buf_size = RX_BUF_SIZE;
2575 rx_size = skge->rx_ring.count * sizeof(struct skge_rx_desc);
2576 tx_size = skge->tx_ring.count * sizeof(struct skge_tx_desc);
2577 skge->mem_size = tx_size + rx_size;
2578 skge->mem = pci_alloc_consistent(hw->pdev, skge->mem_size, &skge->dma);
2582 BUG_ON(skge->dma & 7);
2584 if ((u64)skge->dma >> 32 != ((u64) skge->dma + skge->mem_size) >> 32) {
2585 dev_err(&hw->pdev->dev, "pci_alloc_consistent region crosses 4G boundary\n");
2590 memset(skge->mem, 0, skge->mem_size);
2592 err = skge_ring_alloc(&skge->rx_ring, skge->mem, skge->dma);
2596 err = skge_rx_fill(dev);
2600 err = skge_ring_alloc(&skge->tx_ring, skge->mem + rx_size,
2601 skge->dma + rx_size);
2605 /* Initialize MAC */
2606 spin_lock_bh(&hw->phy_lock);
2607 if (hw->chip_id == CHIP_ID_GENESIS)
2608 genesis_mac_init(hw, port);
2610 yukon_mac_init(hw, port);
2611 spin_unlock_bh(&hw->phy_lock);
2613 /* Configure RAMbuffers - equally between ports and tx/rx */
2614 chunk = (hw->ram_size - hw->ram_offset) / (hw->ports * 2);
2615 ram_addr = hw->ram_offset + 2 * chunk * port;
2617 skge_ramset(hw, rxqaddr[port], ram_addr, chunk);
2618 skge_qset(skge, rxqaddr[port], skge->rx_ring.to_clean);
2620 BUG_ON(skge->tx_ring.to_use != skge->tx_ring.to_clean);
2621 skge_ramset(hw, txqaddr[port], ram_addr+chunk, chunk);
2622 skge_qset(skge, txqaddr[port], skge->tx_ring.to_use);
2624 /* Start receiver BMU */
2626 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F);
2627 skge_led(skge, LED_MODE_ON);
2629 spin_lock_irq(&hw->hw_lock);
2630 hw->intr_mask |= portmask[port];
2631 skge_write32(hw, B0_IMSK, hw->intr_mask);
2632 spin_unlock_irq(&hw->hw_lock);
2634 napi_enable(&skge->napi);
2638 skge_rx_clean(skge);
2639 kfree(skge->rx_ring.start);
2641 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
2648 static void skge_rx_stop(struct skge_hw *hw, int port)
2650 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_STOP);
2651 skge_write32(hw, RB_ADDR(port ? Q_R2 : Q_R1, RB_CTRL),
2652 RB_RST_SET|RB_DIS_OP_MD);
2653 skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET);
2656 static int skge_down(struct net_device *dev)
2658 struct skge_port *skge = netdev_priv(dev);
2659 struct skge_hw *hw = skge->hw;
2660 int port = skge->port;
2662 if (skge->mem == NULL)
2665 netif_info(skge, ifdown, skge->netdev, "disabling interface\n");
2667 netif_tx_disable(dev);
2669 if (hw->chip_id == CHIP_ID_GENESIS && hw->phy_type == SK_PHY_XMAC)
2670 del_timer_sync(&skge->link_timer);
2672 napi_disable(&skge->napi);
2673 netif_carrier_off(dev);
2675 spin_lock_irq(&hw->hw_lock);
2676 hw->intr_mask &= ~portmask[port];
2677 skge_write32(hw, B0_IMSK, hw->intr_mask);
2678 spin_unlock_irq(&hw->hw_lock);
2680 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
2681 if (hw->chip_id == CHIP_ID_GENESIS)
2686 /* Stop transmitter */
2687 skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP);
2688 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
2689 RB_RST_SET|RB_DIS_OP_MD);
2692 /* Disable Force Sync bit and Enable Alloc bit */
2693 skge_write8(hw, SK_REG(port, TXA_CTRL),
2694 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
2696 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
2697 skge_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
2698 skge_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
2700 /* Reset PCI FIFO */
2701 skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET);
2702 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
2704 /* Reset the RAM Buffer async Tx queue */
2705 skge_write8(hw, RB_ADDR(port == 0 ? Q_XA1 : Q_XA2, RB_CTRL), RB_RST_SET);
2707 skge_rx_stop(hw, port);
2709 if (hw->chip_id == CHIP_ID_GENESIS) {
2710 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_SET);
2711 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_SET);
2713 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
2714 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
2717 skge_led(skge, LED_MODE_OFF);
2719 netif_tx_lock_bh(dev);
2721 netif_tx_unlock_bh(dev);
2723 skge_rx_clean(skge);
2725 kfree(skge->rx_ring.start);
2726 kfree(skge->tx_ring.start);
2727 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
2732 static inline int skge_avail(const struct skge_ring *ring)
2735 return ((ring->to_clean > ring->to_use) ? 0 : ring->count)
2736 + (ring->to_clean - ring->to_use) - 1;
2739 static netdev_tx_t skge_xmit_frame(struct sk_buff *skb,
2740 struct net_device *dev)
2742 struct skge_port *skge = netdev_priv(dev);
2743 struct skge_hw *hw = skge->hw;
2744 struct skge_element *e;
2745 struct skge_tx_desc *td;
2750 if (skb_padto(skb, ETH_ZLEN))
2751 return NETDEV_TX_OK;
2753 if (unlikely(skge_avail(&skge->tx_ring) < skb_shinfo(skb)->nr_frags + 1))
2754 return NETDEV_TX_BUSY;
2756 e = skge->tx_ring.to_use;
2758 BUG_ON(td->control & BMU_OWN);
2760 len = skb_headlen(skb);
2761 map = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
2762 pci_unmap_addr_set(e, mapaddr, map);
2763 pci_unmap_len_set(e, maplen, len);
2766 td->dma_hi = map >> 32;
2768 if (skb->ip_summed == CHECKSUM_PARTIAL) {
2769 const int offset = skb_transport_offset(skb);
2771 /* This seems backwards, but it is what the sk98lin
2772 * does. Looks like hardware is wrong?
2774 if (ipip_hdr(skb)->protocol == IPPROTO_UDP &&
2775 hw->chip_rev == 0 && hw->chip_id == CHIP_ID_YUKON)
2776 control = BMU_TCP_CHECK;
2778 control = BMU_UDP_CHECK;
2781 td->csum_start = offset;
2782 td->csum_write = offset + skb->csum_offset;
2784 control = BMU_CHECK;
2786 if (!skb_shinfo(skb)->nr_frags) /* single buffer i.e. no fragments */
2787 control |= BMU_EOF| BMU_IRQ_EOF;
2789 struct skge_tx_desc *tf = td;
2791 control |= BMU_STFWD;
2792 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2793 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2795 map = pci_map_page(hw->pdev, frag->page, frag->page_offset,
2796 frag->size, PCI_DMA_TODEVICE);
2801 BUG_ON(tf->control & BMU_OWN);
2804 tf->dma_hi = (u64) map >> 32;
2805 pci_unmap_addr_set(e, mapaddr, map);
2806 pci_unmap_len_set(e, maplen, frag->size);
2808 tf->control = BMU_OWN | BMU_SW | control | frag->size;
2810 tf->control |= BMU_EOF | BMU_IRQ_EOF;
2812 /* Make sure all the descriptors written */
2814 td->control = BMU_OWN | BMU_SW | BMU_STF | control | len;
2817 skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_START);
2819 netif_printk(skge, tx_queued, KERN_DEBUG, skge->netdev,
2820 "tx queued, slot %td, len %d\n",
2821 e - skge->tx_ring.start, skb->len);
2823 skge->tx_ring.to_use = e->next;
2826 if (skge_avail(&skge->tx_ring) <= TX_LOW_WATER) {
2827 pr_debug("%s: transmit queue full\n", dev->name);
2828 netif_stop_queue(dev);
2831 return NETDEV_TX_OK;
2835 /* Free resources associated with this reing element */
2836 static void skge_tx_free(struct skge_port *skge, struct skge_element *e,
2839 struct pci_dev *pdev = skge->hw->pdev;
2841 /* skb header vs. fragment */
2842 if (control & BMU_STF)
2843 pci_unmap_single(pdev, pci_unmap_addr(e, mapaddr),
2844 pci_unmap_len(e, maplen),
2847 pci_unmap_page(pdev, pci_unmap_addr(e, mapaddr),
2848 pci_unmap_len(e, maplen),
2851 if (control & BMU_EOF) {
2852 netif_printk(skge, tx_done, KERN_DEBUG, skge->netdev,
2853 "tx done slot %td\n", e - skge->tx_ring.start);
2855 dev_kfree_skb(e->skb);
2859 /* Free all buffers in transmit ring */
2860 static void skge_tx_clean(struct net_device *dev)
2862 struct skge_port *skge = netdev_priv(dev);
2863 struct skge_element *e;
2865 for (e = skge->tx_ring.to_clean; e != skge->tx_ring.to_use; e = e->next) {
2866 struct skge_tx_desc *td = e->desc;
2867 skge_tx_free(skge, e, td->control);
2871 skge->tx_ring.to_clean = e;
2874 static void skge_tx_timeout(struct net_device *dev)
2876 struct skge_port *skge = netdev_priv(dev);
2878 netif_printk(skge, timer, KERN_DEBUG, skge->netdev, "tx timeout\n");
2880 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_STOP);
2882 netif_wake_queue(dev);
2885 static int skge_change_mtu(struct net_device *dev, int new_mtu)
2889 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2892 if (!netif_running(dev)) {
2908 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
2910 static void genesis_add_filter(u8 filter[8], const u8 *addr)
2914 crc = ether_crc_le(ETH_ALEN, addr);
2916 filter[bit/8] |= 1 << (bit%8);
2919 static void genesis_set_multicast(struct net_device *dev)
2921 struct skge_port *skge = netdev_priv(dev);
2922 struct skge_hw *hw = skge->hw;
2923 int port = skge->port;
2924 int i, count = netdev_mc_count(dev);
2925 struct dev_mc_list *list = dev->mc_list;
2929 mode = xm_read32(hw, port, XM_MODE);
2930 mode |= XM_MD_ENA_HASH;
2931 if (dev->flags & IFF_PROMISC)
2932 mode |= XM_MD_ENA_PROM;
2934 mode &= ~XM_MD_ENA_PROM;
2936 if (dev->flags & IFF_ALLMULTI)
2937 memset(filter, 0xff, sizeof(filter));
2939 memset(filter, 0, sizeof(filter));
2941 if (skge->flow_status == FLOW_STAT_REM_SEND ||
2942 skge->flow_status == FLOW_STAT_SYMMETRIC)
2943 genesis_add_filter(filter, pause_mc_addr);
2945 for (i = 0; list && i < count; i++, list = list->next)
2946 genesis_add_filter(filter, list->dmi_addr);
2949 xm_write32(hw, port, XM_MODE, mode);
2950 xm_outhash(hw, port, XM_HSM, filter);
2953 static void yukon_add_filter(u8 filter[8], const u8 *addr)
2955 u32 bit = ether_crc(ETH_ALEN, addr) & 0x3f;
2956 filter[bit/8] |= 1 << (bit%8);
2959 static void yukon_set_multicast(struct net_device *dev)
2961 struct skge_port *skge = netdev_priv(dev);
2962 struct skge_hw *hw = skge->hw;
2963 int port = skge->port;
2964 struct dev_mc_list *list = dev->mc_list;
2965 int rx_pause = (skge->flow_status == FLOW_STAT_REM_SEND ||
2966 skge->flow_status == FLOW_STAT_SYMMETRIC);
2970 memset(filter, 0, sizeof(filter));
2972 reg = gma_read16(hw, port, GM_RX_CTRL);
2973 reg |= GM_RXCR_UCF_ENA;
2975 if (dev->flags & IFF_PROMISC) /* promiscuous */
2976 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2977 else if (dev->flags & IFF_ALLMULTI) /* all multicast */
2978 memset(filter, 0xff, sizeof(filter));
2979 else if (netdev_mc_empty(dev) && !rx_pause)/* no multicast */
2980 reg &= ~GM_RXCR_MCF_ENA;
2983 reg |= GM_RXCR_MCF_ENA;
2986 yukon_add_filter(filter, pause_mc_addr);
2988 for (i = 0; list && i < netdev_mc_count(dev); i++, list = list->next)
2989 yukon_add_filter(filter, list->dmi_addr);
2993 gma_write16(hw, port, GM_MC_ADDR_H1,
2994 (u16)filter[0] | ((u16)filter[1] << 8));
2995 gma_write16(hw, port, GM_MC_ADDR_H2,
2996 (u16)filter[2] | ((u16)filter[3] << 8));
2997 gma_write16(hw, port, GM_MC_ADDR_H3,
2998 (u16)filter[4] | ((u16)filter[5] << 8));
2999 gma_write16(hw, port, GM_MC_ADDR_H4,
3000 (u16)filter[6] | ((u16)filter[7] << 8));
3002 gma_write16(hw, port, GM_RX_CTRL, reg);
3005 static inline u16 phy_length(const struct skge_hw *hw, u32 status)
3007 if (hw->chip_id == CHIP_ID_GENESIS)
3008 return status >> XMR_FS_LEN_SHIFT;
3010 return status >> GMR_FS_LEN_SHIFT;
3013 static inline int bad_phy_status(const struct skge_hw *hw, u32 status)
3015 if (hw->chip_id == CHIP_ID_GENESIS)
3016 return (status & (XMR_FS_ERR | XMR_FS_2L_VLAN)) != 0;
3018 return (status & GMR_FS_ANY_ERR) ||
3019 (status & GMR_FS_RX_OK) == 0;
3022 static void skge_set_multicast(struct net_device *dev)
3024 struct skge_port *skge = netdev_priv(dev);
3025 struct skge_hw *hw = skge->hw;
3027 if (hw->chip_id == CHIP_ID_GENESIS)
3028 genesis_set_multicast(dev);
3030 yukon_set_multicast(dev);
3035 /* Get receive buffer from descriptor.
3036 * Handles copy of small buffers and reallocation failures
3038 static struct sk_buff *skge_rx_get(struct net_device *dev,
3039 struct skge_element *e,
3040 u32 control, u32 status, u16 csum)
3042 struct skge_port *skge = netdev_priv(dev);
3043 struct sk_buff *skb;
3044 u16 len = control & BMU_BBC;
3046 netif_printk(skge, rx_status, KERN_DEBUG, skge->netdev,
3047 "rx slot %td status 0x%x len %d\n",
3048 e - skge->rx_ring.start, status, len);
3050 if (len > skge->rx_buf_size)
3053 if ((control & (BMU_EOF|BMU_STF)) != (BMU_STF|BMU_EOF))
3056 if (bad_phy_status(skge->hw, status))
3059 if (phy_length(skge->hw, status) != len)
3062 if (len < RX_COPY_THRESHOLD) {
3063 skb = netdev_alloc_skb_ip_align(dev, len);
3067 pci_dma_sync_single_for_cpu(skge->hw->pdev,
3068 pci_unmap_addr(e, mapaddr),
3069 len, PCI_DMA_FROMDEVICE);
3070 skb_copy_from_linear_data(e->skb, skb->data, len);
3071 pci_dma_sync_single_for_device(skge->hw->pdev,
3072 pci_unmap_addr(e, mapaddr),
3073 len, PCI_DMA_FROMDEVICE);
3074 skge_rx_reuse(e, skge->rx_buf_size);
3076 struct sk_buff *nskb;
3078 nskb = netdev_alloc_skb_ip_align(dev, skge->rx_buf_size);
3082 pci_unmap_single(skge->hw->pdev,
3083 pci_unmap_addr(e, mapaddr),
3084 pci_unmap_len(e, maplen),
3085 PCI_DMA_FROMDEVICE);
3087 prefetch(skb->data);
3088 skge_rx_setup(skge, e, nskb, skge->rx_buf_size);
3092 if (skge->rx_csum) {
3094 skb->ip_summed = CHECKSUM_COMPLETE;
3097 skb->protocol = eth_type_trans(skb, dev);
3102 netif_printk(skge, rx_err, KERN_DEBUG, skge->netdev,
3103 "rx err, slot %td control 0x%x status 0x%x\n",
3104 e - skge->rx_ring.start, control, status);
3106 if (skge->hw->chip_id == CHIP_ID_GENESIS) {
3107 if (status & (XMR_FS_RUNT|XMR_FS_LNG_ERR))
3108 dev->stats.rx_length_errors++;
3109 if (status & XMR_FS_FRA_ERR)
3110 dev->stats.rx_frame_errors++;
3111 if (status & XMR_FS_FCS_ERR)
3112 dev->stats.rx_crc_errors++;
3114 if (status & (GMR_FS_LONG_ERR|GMR_FS_UN_SIZE))
3115 dev->stats.rx_length_errors++;
3116 if (status & GMR_FS_FRAGMENT)
3117 dev->stats.rx_frame_errors++;
3118 if (status & GMR_FS_CRC_ERR)
3119 dev->stats.rx_crc_errors++;
3123 skge_rx_reuse(e, skge->rx_buf_size);
3127 /* Free all buffers in Tx ring which are no longer owned by device */
3128 static void skge_tx_done(struct net_device *dev)
3130 struct skge_port *skge = netdev_priv(dev);
3131 struct skge_ring *ring = &skge->tx_ring;
3132 struct skge_element *e;
3134 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
3136 for (e = ring->to_clean; e != ring->to_use; e = e->next) {
3137 u32 control = ((const struct skge_tx_desc *) e->desc)->control;
3139 if (control & BMU_OWN)
3142 skge_tx_free(skge, e, control);
3144 skge->tx_ring.to_clean = e;
3146 /* Can run lockless until we need to synchronize to restart queue. */
3149 if (unlikely(netif_queue_stopped(dev) &&
3150 skge_avail(&skge->tx_ring) > TX_LOW_WATER)) {
3152 if (unlikely(netif_queue_stopped(dev) &&
3153 skge_avail(&skge->tx_ring) > TX_LOW_WATER)) {
3154 netif_wake_queue(dev);
3157 netif_tx_unlock(dev);
3161 static int skge_poll(struct napi_struct *napi, int to_do)
3163 struct skge_port *skge = container_of(napi, struct skge_port, napi);
3164 struct net_device *dev = skge->netdev;
3165 struct skge_hw *hw = skge->hw;
3166 struct skge_ring *ring = &skge->rx_ring;
3167 struct skge_element *e;
3172 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
3174 for (e = ring->to_clean; prefetch(e->next), work_done < to_do; e = e->next) {
3175 struct skge_rx_desc *rd = e->desc;
3176 struct sk_buff *skb;
3180 control = rd->control;
3181 if (control & BMU_OWN)
3184 skb = skge_rx_get(dev, e, control, rd->status, rd->csum2);
3186 netif_receive_skb(skb);
3193 /* restart receiver */
3195 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_START);
3197 if (work_done < to_do) {
3198 unsigned long flags;
3200 spin_lock_irqsave(&hw->hw_lock, flags);
3201 __napi_complete(napi);
3202 hw->intr_mask |= napimask[skge->port];
3203 skge_write32(hw, B0_IMSK, hw->intr_mask);
3204 skge_read32(hw, B0_IMSK);
3205 spin_unlock_irqrestore(&hw->hw_lock, flags);
3211 /* Parity errors seem to happen when Genesis is connected to a switch
3212 * with no other ports present. Heartbeat error??
3214 static void skge_mac_parity(struct skge_hw *hw, int port)
3216 struct net_device *dev = hw->dev[port];
3218 ++dev->stats.tx_heartbeat_errors;
3220 if (hw->chip_id == CHIP_ID_GENESIS)
3221 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
3224 /* HW-Bug #8: cleared by GMF_CLI_TX_FC instead of GMF_CLI_TX_PE */
3225 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T),
3226 (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)
3227 ? GMF_CLI_TX_FC : GMF_CLI_TX_PE);
3230 static void skge_mac_intr(struct skge_hw *hw, int port)
3232 if (hw->chip_id == CHIP_ID_GENESIS)
3233 genesis_mac_intr(hw, port);
3235 yukon_mac_intr(hw, port);
3238 /* Handle device specific framing and timeout interrupts */
3239 static void skge_error_irq(struct skge_hw *hw)
3241 struct pci_dev *pdev = hw->pdev;
3242 u32 hwstatus = skge_read32(hw, B0_HWE_ISRC);
3244 if (hw->chip_id == CHIP_ID_GENESIS) {
3245 /* clear xmac errors */
3246 if (hwstatus & (IS_NO_STAT_M1|IS_NO_TIST_M1))
3247 skge_write16(hw, RX_MFF_CTRL1, MFF_CLR_INSTAT);
3248 if (hwstatus & (IS_NO_STAT_M2|IS_NO_TIST_M2))
3249 skge_write16(hw, RX_MFF_CTRL2, MFF_CLR_INSTAT);
3251 /* Timestamp (unused) overflow */
3252 if (hwstatus & IS_IRQ_TIST_OV)
3253 skge_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
3256 if (hwstatus & IS_RAM_RD_PAR) {
3257 dev_err(&pdev->dev, "Ram read data parity error\n");
3258 skge_write16(hw, B3_RI_CTRL, RI_CLR_RD_PERR);
3261 if (hwstatus & IS_RAM_WR_PAR) {
3262 dev_err(&pdev->dev, "Ram write data parity error\n");
3263 skge_write16(hw, B3_RI_CTRL, RI_CLR_WR_PERR);
3266 if (hwstatus & IS_M1_PAR_ERR)
3267 skge_mac_parity(hw, 0);
3269 if (hwstatus & IS_M2_PAR_ERR)
3270 skge_mac_parity(hw, 1);
3272 if (hwstatus & IS_R1_PAR_ERR) {
3273 dev_err(&pdev->dev, "%s: receive queue parity error\n",
3275 skge_write32(hw, B0_R1_CSR, CSR_IRQ_CL_P);
3278 if (hwstatus & IS_R2_PAR_ERR) {
3279 dev_err(&pdev->dev, "%s: receive queue parity error\n",
3281 skge_write32(hw, B0_R2_CSR, CSR_IRQ_CL_P);
3284 if (hwstatus & (IS_IRQ_MST_ERR|IS_IRQ_STAT)) {
3285 u16 pci_status, pci_cmd;
3287 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
3288 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
3290 dev_err(&pdev->dev, "PCI error cmd=%#x status=%#x\n",
3291 pci_cmd, pci_status);
3293 /* Write the error bits back to clear them. */
3294 pci_status &= PCI_STATUS_ERROR_BITS;
3295 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3296 pci_write_config_word(pdev, PCI_COMMAND,
3297 pci_cmd | PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
3298 pci_write_config_word(pdev, PCI_STATUS, pci_status);
3299 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3301 /* if error still set then just ignore it */
3302 hwstatus = skge_read32(hw, B0_HWE_ISRC);
3303 if (hwstatus & IS_IRQ_STAT) {
3304 dev_warn(&hw->pdev->dev, "unable to clear error (so ignoring them)\n");
3305 hw->intr_mask &= ~IS_HW_ERR;
3311 * Interrupt from PHY are handled in tasklet (softirq)
3312 * because accessing phy registers requires spin wait which might
3313 * cause excess interrupt latency.
3315 static void skge_extirq(unsigned long arg)
3317 struct skge_hw *hw = (struct skge_hw *) arg;
3320 for (port = 0; port < hw->ports; port++) {
3321 struct net_device *dev = hw->dev[port];
3323 if (netif_running(dev)) {
3324 struct skge_port *skge = netdev_priv(dev);
3326 spin_lock(&hw->phy_lock);
3327 if (hw->chip_id != CHIP_ID_GENESIS)
3328 yukon_phy_intr(skge);
3329 else if (hw->phy_type == SK_PHY_BCOM)
3330 bcom_phy_intr(skge);
3331 spin_unlock(&hw->phy_lock);
3335 spin_lock_irq(&hw->hw_lock);
3336 hw->intr_mask |= IS_EXT_REG;
3337 skge_write32(hw, B0_IMSK, hw->intr_mask);
3338 skge_read32(hw, B0_IMSK);
3339 spin_unlock_irq(&hw->hw_lock);
3342 static irqreturn_t skge_intr(int irq, void *dev_id)
3344 struct skge_hw *hw = dev_id;
3348 spin_lock(&hw->hw_lock);
3349 /* Reading this register masks IRQ */
3350 status = skge_read32(hw, B0_SP_ISRC);
3351 if (status == 0 || status == ~0)
3355 status &= hw->intr_mask;
3356 if (status & IS_EXT_REG) {
3357 hw->intr_mask &= ~IS_EXT_REG;
3358 tasklet_schedule(&hw->phy_task);
3361 if (status & (IS_XA1_F|IS_R1_F)) {
3362 struct skge_port *skge = netdev_priv(hw->dev[0]);
3363 hw->intr_mask &= ~(IS_XA1_F|IS_R1_F);
3364 napi_schedule(&skge->napi);
3367 if (status & IS_PA_TO_TX1)
3368 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX1);
3370 if (status & IS_PA_TO_RX1) {
3371 ++hw->dev[0]->stats.rx_over_errors;
3372 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX1);
3376 if (status & IS_MAC1)
3377 skge_mac_intr(hw, 0);
3380 struct skge_port *skge = netdev_priv(hw->dev[1]);
3382 if (status & (IS_XA2_F|IS_R2_F)) {
3383 hw->intr_mask &= ~(IS_XA2_F|IS_R2_F);
3384 napi_schedule(&skge->napi);
3387 if (status & IS_PA_TO_RX2) {
3388 ++hw->dev[1]->stats.rx_over_errors;
3389 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX2);
3392 if (status & IS_PA_TO_TX2)
3393 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX2);
3395 if (status & IS_MAC2)
3396 skge_mac_intr(hw, 1);
3399 if (status & IS_HW_ERR)
3402 skge_write32(hw, B0_IMSK, hw->intr_mask);
3403 skge_read32(hw, B0_IMSK);
3405 spin_unlock(&hw->hw_lock);
3407 return IRQ_RETVAL(handled);
3410 #ifdef CONFIG_NET_POLL_CONTROLLER
3411 static void skge_netpoll(struct net_device *dev)
3413 struct skge_port *skge = netdev_priv(dev);
3415 disable_irq(dev->irq);
3416 skge_intr(dev->irq, skge->hw);
3417 enable_irq(dev->irq);
3421 static int skge_set_mac_address(struct net_device *dev, void *p)
3423 struct skge_port *skge = netdev_priv(dev);
3424 struct skge_hw *hw = skge->hw;
3425 unsigned port = skge->port;
3426 const struct sockaddr *addr = p;
3429 if (!is_valid_ether_addr(addr->sa_data))
3430 return -EADDRNOTAVAIL;
3432 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
3434 if (!netif_running(dev)) {
3435 memcpy_toio(hw->regs + B2_MAC_1 + port*8, dev->dev_addr, ETH_ALEN);
3436 memcpy_toio(hw->regs + B2_MAC_2 + port*8, dev->dev_addr, ETH_ALEN);
3439 spin_lock_bh(&hw->phy_lock);
3440 ctrl = gma_read16(hw, port, GM_GP_CTRL);
3441 gma_write16(hw, port, GM_GP_CTRL, ctrl & ~GM_GPCR_RX_ENA);
3443 memcpy_toio(hw->regs + B2_MAC_1 + port*8, dev->dev_addr, ETH_ALEN);
3444 memcpy_toio(hw->regs + B2_MAC_2 + port*8, dev->dev_addr, ETH_ALEN);
3446 if (hw->chip_id == CHIP_ID_GENESIS)
3447 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
3449 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
3450 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3453 gma_write16(hw, port, GM_GP_CTRL, ctrl);
3454 spin_unlock_bh(&hw->phy_lock);
3460 static const struct {
3464 { CHIP_ID_GENESIS, "Genesis" },
3465 { CHIP_ID_YUKON, "Yukon" },
3466 { CHIP_ID_YUKON_LITE, "Yukon-Lite"},
3467 { CHIP_ID_YUKON_LP, "Yukon-LP"},
3470 static const char *skge_board_name(const struct skge_hw *hw)
3473 static char buf[16];
3475 for (i = 0; i < ARRAY_SIZE(skge_chips); i++)
3476 if (skge_chips[i].id == hw->chip_id)
3477 return skge_chips[i].name;
3479 snprintf(buf, sizeof buf, "chipid 0x%x", hw->chip_id);
3485 * Setup the board data structure, but don't bring up
3488 static int skge_reset(struct skge_hw *hw)
3491 u16 ctst, pci_status;
3492 u8 t8, mac_cfg, pmd_type;
3495 ctst = skge_read16(hw, B0_CTST);
3498 skge_write8(hw, B0_CTST, CS_RST_SET);
3499 skge_write8(hw, B0_CTST, CS_RST_CLR);
3501 /* clear PCI errors, if any */
3502 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3503 skge_write8(hw, B2_TST_CTRL2, 0);
3505 pci_read_config_word(hw->pdev, PCI_STATUS, &pci_status);
3506 pci_write_config_word(hw->pdev, PCI_STATUS,
3507 pci_status | PCI_STATUS_ERROR_BITS);
3508 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3509 skge_write8(hw, B0_CTST, CS_MRST_CLR);
3511 /* restore CLK_RUN bits (for Yukon-Lite) */
3512 skge_write16(hw, B0_CTST,
3513 ctst & (CS_CLK_RUN_HOT|CS_CLK_RUN_RST|CS_CLK_RUN_ENA));
3515 hw->chip_id = skge_read8(hw, B2_CHIP_ID);
3516 hw->phy_type = skge_read8(hw, B2_E_1) & 0xf;
3517 pmd_type = skge_read8(hw, B2_PMD_TYP);
3518 hw->copper = (pmd_type == 'T' || pmd_type == '1');
3520 switch (hw->chip_id) {
3521 case CHIP_ID_GENESIS:
3522 switch (hw->phy_type) {
3524 hw->phy_addr = PHY_ADDR_XMAC;
3527 hw->phy_addr = PHY_ADDR_BCOM;
3530 dev_err(&hw->pdev->dev, "unsupported phy type 0x%x\n",
3537 case CHIP_ID_YUKON_LITE:
3538 case CHIP_ID_YUKON_LP:
3539 if (hw->phy_type < SK_PHY_MARV_COPPER && pmd_type != 'S')
3542 hw->phy_addr = PHY_ADDR_MARV;
3546 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
3551 mac_cfg = skge_read8(hw, B2_MAC_CFG);
3552 hw->ports = (mac_cfg & CFG_SNG_MAC) ? 1 : 2;
3553 hw->chip_rev = (mac_cfg & CFG_CHIP_R_MSK) >> 4;
3555 /* read the adapters RAM size */
3556 t8 = skge_read8(hw, B2_E_0);
3557 if (hw->chip_id == CHIP_ID_GENESIS) {
3559 /* special case: 4 x 64k x 36, offset = 0x80000 */
3560 hw->ram_size = 0x100000;
3561 hw->ram_offset = 0x80000;
3563 hw->ram_size = t8 * 512;
3566 hw->ram_size = 0x20000;
3568 hw->ram_size = t8 * 4096;
3570 hw->intr_mask = IS_HW_ERR;
3572 /* Use PHY IRQ for all but fiber based Genesis board */
3573 if (!(hw->chip_id == CHIP_ID_GENESIS && hw->phy_type == SK_PHY_XMAC))
3574 hw->intr_mask |= IS_EXT_REG;
3576 if (hw->chip_id == CHIP_ID_GENESIS)
3579 /* switch power to VCC (WA for VAUX problem) */
3580 skge_write8(hw, B0_POWER_CTRL,
3581 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
3583 /* avoid boards with stuck Hardware error bits */
3584 if ((skge_read32(hw, B0_ISRC) & IS_HW_ERR) &&
3585 (skge_read32(hw, B0_HWE_ISRC) & IS_IRQ_SENSOR)) {
3586 dev_warn(&hw->pdev->dev, "stuck hardware sensor bit\n");
3587 hw->intr_mask &= ~IS_HW_ERR;
3590 /* Clear PHY COMA */
3591 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3592 pci_read_config_dword(hw->pdev, PCI_DEV_REG1, ®);
3593 reg &= ~PCI_PHY_COMA;
3594 pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg);
3595 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3598 for (i = 0; i < hw->ports; i++) {
3599 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
3600 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
3604 /* turn off hardware timer (unused) */
3605 skge_write8(hw, B2_TI_CTRL, TIM_STOP);
3606 skge_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
3607 skge_write8(hw, B0_LED, LED_STAT_ON);
3609 /* enable the Tx Arbiters */
3610 for (i = 0; i < hw->ports; i++)
3611 skge_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
3613 /* Initialize ram interface */
3614 skge_write16(hw, B3_RI_CTRL, RI_RST_CLR);
3616 skge_write8(hw, B3_RI_WTO_R1, SK_RI_TO_53);
3617 skge_write8(hw, B3_RI_WTO_XA1, SK_RI_TO_53);
3618 skge_write8(hw, B3_RI_WTO_XS1, SK_RI_TO_53);
3619 skge_write8(hw, B3_RI_RTO_R1, SK_RI_TO_53);
3620 skge_write8(hw, B3_RI_RTO_XA1, SK_RI_TO_53);
3621 skge_write8(hw, B3_RI_RTO_XS1, SK_RI_TO_53);
3622 skge_write8(hw, B3_RI_WTO_R2, SK_RI_TO_53);
3623 skge_write8(hw, B3_RI_WTO_XA2, SK_RI_TO_53);
3624 skge_write8(hw, B3_RI_WTO_XS2, SK_RI_TO_53);
3625 skge_write8(hw, B3_RI_RTO_R2, SK_RI_TO_53);
3626 skge_write8(hw, B3_RI_RTO_XA2, SK_RI_TO_53);
3627 skge_write8(hw, B3_RI_RTO_XS2, SK_RI_TO_53);
3629 skge_write32(hw, B0_HWE_IMSK, IS_ERR_MSK);
3631 /* Set interrupt moderation for Transmit only
3632 * Receive interrupts avoided by NAPI
3634 skge_write32(hw, B2_IRQM_MSK, IS_XA1_F|IS_XA2_F);
3635 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, 100));
3636 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
3638 skge_write32(hw, B0_IMSK, hw->intr_mask);
3640 for (i = 0; i < hw->ports; i++) {
3641 if (hw->chip_id == CHIP_ID_GENESIS)
3642 genesis_reset(hw, i);
3651 #ifdef CONFIG_SKGE_DEBUG
3653 static struct dentry *skge_debug;
3655 static int skge_debug_show(struct seq_file *seq, void *v)
3657 struct net_device *dev = seq->private;
3658 const struct skge_port *skge = netdev_priv(dev);
3659 const struct skge_hw *hw = skge->hw;
3660 const struct skge_element *e;
3662 if (!netif_running(dev))
3665 seq_printf(seq, "IRQ src=%x mask=%x\n", skge_read32(hw, B0_ISRC),
3666 skge_read32(hw, B0_IMSK));
3668 seq_printf(seq, "Tx Ring: (%d)\n", skge_avail(&skge->tx_ring));
3669 for (e = skge->tx_ring.to_clean; e != skge->tx_ring.to_use; e = e->next) {
3670 const struct skge_tx_desc *t = e->desc;
3671 seq_printf(seq, "%#x dma=%#x%08x %#x csum=%#x/%x/%x\n",
3672 t->control, t->dma_hi, t->dma_lo, t->status,
3673 t->csum_offs, t->csum_write, t->csum_start);
3676 seq_printf(seq, "\nRx Ring: \n");
3677 for (e = skge->rx_ring.to_clean; ; e = e->next) {
3678 const struct skge_rx_desc *r = e->desc;
3680 if (r->control & BMU_OWN)
3683 seq_printf(seq, "%#x dma=%#x%08x %#x %#x csum=%#x/%x\n",
3684 r->control, r->dma_hi, r->dma_lo, r->status,
3685 r->timestamp, r->csum1, r->csum1_start);
3691 static int skge_debug_open(struct inode *inode, struct file *file)
3693 return single_open(file, skge_debug_show, inode->i_private);
3696 static const struct file_operations skge_debug_fops = {
3697 .owner = THIS_MODULE,
3698 .open = skge_debug_open,
3700 .llseek = seq_lseek,
3701 .release = single_release,
3705 * Use network device events to create/remove/rename
3706 * debugfs file entries
3708 static int skge_device_event(struct notifier_block *unused,
3709 unsigned long event, void *ptr)
3711 struct net_device *dev = ptr;
3712 struct skge_port *skge;
3715 if (dev->netdev_ops->ndo_open != &skge_up || !skge_debug)
3718 skge = netdev_priv(dev);
3720 case NETDEV_CHANGENAME:
3721 if (skge->debugfs) {
3722 d = debugfs_rename(skge_debug, skge->debugfs,
3723 skge_debug, dev->name);
3727 pr_info(PFX "%s: rename failed\n", dev->name);
3728 debugfs_remove(skge->debugfs);
3733 case NETDEV_GOING_DOWN:
3734 if (skge->debugfs) {
3735 debugfs_remove(skge->debugfs);
3736 skge->debugfs = NULL;
3741 d = debugfs_create_file(dev->name, S_IRUGO,
3744 if (!d || IS_ERR(d))
3745 pr_info(PFX "%s: debugfs create failed\n",
3756 static struct notifier_block skge_notifier = {
3757 .notifier_call = skge_device_event,
3761 static __init void skge_debug_init(void)
3765 ent = debugfs_create_dir("skge", NULL);
3766 if (!ent || IS_ERR(ent)) {
3767 pr_info(PFX "debugfs create directory failed\n");
3772 register_netdevice_notifier(&skge_notifier);
3775 static __exit void skge_debug_cleanup(void)
3778 unregister_netdevice_notifier(&skge_notifier);
3779 debugfs_remove(skge_debug);
3785 #define skge_debug_init()
3786 #define skge_debug_cleanup()
3789 static const struct net_device_ops skge_netdev_ops = {
3790 .ndo_open = skge_up,
3791 .ndo_stop = skge_down,
3792 .ndo_start_xmit = skge_xmit_frame,
3793 .ndo_do_ioctl = skge_ioctl,
3794 .ndo_get_stats = skge_get_stats,
3795 .ndo_tx_timeout = skge_tx_timeout,
3796 .ndo_change_mtu = skge_change_mtu,
3797 .ndo_validate_addr = eth_validate_addr,
3798 .ndo_set_multicast_list = skge_set_multicast,
3799 .ndo_set_mac_address = skge_set_mac_address,
3800 #ifdef CONFIG_NET_POLL_CONTROLLER
3801 .ndo_poll_controller = skge_netpoll,
3806 /* Initialize network device */
3807 static struct net_device *skge_devinit(struct skge_hw *hw, int port,
3810 struct skge_port *skge;
3811 struct net_device *dev = alloc_etherdev(sizeof(*skge));
3814 dev_err(&hw->pdev->dev, "etherdev alloc failed\n");
3818 SET_NETDEV_DEV(dev, &hw->pdev->dev);
3819 dev->netdev_ops = &skge_netdev_ops;
3820 dev->ethtool_ops = &skge_ethtool_ops;
3821 dev->watchdog_timeo = TX_WATCHDOG;
3822 dev->irq = hw->pdev->irq;
3825 dev->features |= NETIF_F_HIGHDMA;
3827 skge = netdev_priv(dev);
3828 netif_napi_add(dev, &skge->napi, skge_poll, NAPI_WEIGHT);
3831 skge->msg_enable = netif_msg_init(debug, default_msg);
3833 skge->tx_ring.count = DEFAULT_TX_RING_SIZE;
3834 skge->rx_ring.count = DEFAULT_RX_RING_SIZE;
3836 /* Auto speed and flow control */
3837 skge->autoneg = AUTONEG_ENABLE;
3838 skge->flow_control = FLOW_MODE_SYM_OR_REM;
3841 skge->advertising = skge_supported_modes(hw);
3843 if (device_can_wakeup(&hw->pdev->dev)) {
3844 skge->wol = wol_supported(hw) & WAKE_MAGIC;
3845 device_set_wakeup_enable(&hw->pdev->dev, skge->wol);
3848 hw->dev[port] = dev;
3852 /* Only used for Genesis XMAC */
3853 setup_timer(&skge->link_timer, xm_link_timer, (unsigned long) skge);
3855 if (hw->chip_id != CHIP_ID_GENESIS) {
3856 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
3860 /* read the mac address */
3861 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port*8, ETH_ALEN);
3862 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
3864 /* device is off until link detection */
3865 netif_carrier_off(dev);
3866 netif_stop_queue(dev);
3871 static void __devinit skge_show_addr(struct net_device *dev)
3873 const struct skge_port *skge = netdev_priv(dev);
3875 netif_info(skge, probe, skge->netdev, "addr %pM\n", dev->dev_addr);
3878 static int __devinit skge_probe(struct pci_dev *pdev,
3879 const struct pci_device_id *ent)
3881 struct net_device *dev, *dev1;
3883 int err, using_dac = 0;
3885 err = pci_enable_device(pdev);
3887 dev_err(&pdev->dev, "cannot enable PCI device\n");
3891 err = pci_request_regions(pdev, DRV_NAME);
3893 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
3894 goto err_out_disable_pdev;
3897 pci_set_master(pdev);
3899 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
3901 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
3902 } else if (!(err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)))) {
3904 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
3908 dev_err(&pdev->dev, "no usable DMA configuration\n");
3909 goto err_out_free_regions;
3913 /* byte swap descriptors in hardware */
3917 pci_read_config_dword(pdev, PCI_DEV_REG2, ®);
3918 reg |= PCI_REV_DESC;
3919 pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
3924 /* space for skge@pci:0000:04:00.0 */
3925 hw = kzalloc(sizeof(*hw) + strlen(DRV_NAME "@pci:" )
3926 + strlen(pci_name(pdev)) + 1, GFP_KERNEL);
3928 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
3929 goto err_out_free_regions;
3931 sprintf(hw->irq_name, DRV_NAME "@pci:%s", pci_name(pdev));
3934 spin_lock_init(&hw->hw_lock);
3935 spin_lock_init(&hw->phy_lock);
3936 tasklet_init(&hw->phy_task, skge_extirq, (unsigned long) hw);
3938 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3940 dev_err(&pdev->dev, "cannot map device registers\n");
3941 goto err_out_free_hw;
3944 err = skge_reset(hw);
3946 goto err_out_iounmap;
3948 printk(KERN_INFO PFX DRV_VERSION " addr 0x%llx irq %d chip %s rev %d\n",
3949 (unsigned long long)pci_resource_start(pdev, 0), pdev->irq,
3950 skge_board_name(hw), hw->chip_rev);
3952 dev = skge_devinit(hw, 0, using_dac);
3954 goto err_out_led_off;
3956 /* Some motherboards are broken and has zero in ROM. */
3957 if (!is_valid_ether_addr(dev->dev_addr))
3958 dev_warn(&pdev->dev, "bad (zero?) ethernet address in rom\n");
3960 err = register_netdev(dev);
3962 dev_err(&pdev->dev, "cannot register net device\n");
3963 goto err_out_free_netdev;
3966 err = request_irq(pdev->irq, skge_intr, IRQF_SHARED, hw->irq_name, hw);
3968 dev_err(&pdev->dev, "%s: cannot assign irq %d\n",
3969 dev->name, pdev->irq);
3970 goto err_out_unregister;
3972 skge_show_addr(dev);
3974 if (hw->ports > 1) {
3975 dev1 = skge_devinit(hw, 1, using_dac);
3976 if (dev1 && register_netdev(dev1) == 0)
3977 skge_show_addr(dev1);
3979 /* Failure to register second port need not be fatal */
3980 dev_warn(&pdev->dev, "register of second port failed\n");
3987 pci_set_drvdata(pdev, hw);
3992 unregister_netdev(dev);
3993 err_out_free_netdev:
3996 skge_write16(hw, B0_LED, LED_STAT_OFF);
4001 err_out_free_regions:
4002 pci_release_regions(pdev);
4003 err_out_disable_pdev:
4004 pci_disable_device(pdev);
4005 pci_set_drvdata(pdev, NULL);
4010 static void __devexit skge_remove(struct pci_dev *pdev)
4012 struct skge_hw *hw = pci_get_drvdata(pdev);
4013 struct net_device *dev0, *dev1;
4018 flush_scheduled_work();
4020 if ((dev1 = hw->dev[1]))
4021 unregister_netdev(dev1);
4023 unregister_netdev(dev0);
4025 tasklet_disable(&hw->phy_task);
4027 spin_lock_irq(&hw->hw_lock);
4029 skge_write32(hw, B0_IMSK, 0);
4030 skge_read32(hw, B0_IMSK);
4031 spin_unlock_irq(&hw->hw_lock);
4033 skge_write16(hw, B0_LED, LED_STAT_OFF);
4034 skge_write8(hw, B0_CTST, CS_RST_SET);
4036 free_irq(pdev->irq, hw);
4037 pci_release_regions(pdev);
4038 pci_disable_device(pdev);
4045 pci_set_drvdata(pdev, NULL);
4049 static int skge_suspend(struct pci_dev *pdev, pm_message_t state)
4051 struct skge_hw *hw = pci_get_drvdata(pdev);
4052 int i, err, wol = 0;
4057 err = pci_save_state(pdev);
4061 for (i = 0; i < hw->ports; i++) {
4062 struct net_device *dev = hw->dev[i];
4063 struct skge_port *skge = netdev_priv(dev);
4065 if (netif_running(dev))
4068 skge_wol_init(skge);
4073 skge_write32(hw, B0_IMSK, 0);
4075 pci_prepare_to_sleep(pdev);
4080 static int skge_resume(struct pci_dev *pdev)
4082 struct skge_hw *hw = pci_get_drvdata(pdev);
4088 err = pci_back_from_sleep(pdev);
4092 err = pci_restore_state(pdev);
4096 err = skge_reset(hw);
4100 for (i = 0; i < hw->ports; i++) {
4101 struct net_device *dev = hw->dev[i];
4103 if (netif_running(dev)) {
4107 printk(KERN_ERR PFX "%s: could not up: %d\n",
4119 static void skge_shutdown(struct pci_dev *pdev)
4121 struct skge_hw *hw = pci_get_drvdata(pdev);
4127 for (i = 0; i < hw->ports; i++) {
4128 struct net_device *dev = hw->dev[i];
4129 struct skge_port *skge = netdev_priv(dev);
4132 skge_wol_init(skge);
4136 if (pci_enable_wake(pdev, PCI_D3cold, wol))
4137 pci_enable_wake(pdev, PCI_D3hot, wol);
4139 pci_disable_device(pdev);
4140 pci_set_power_state(pdev, PCI_D3hot);
4144 static struct pci_driver skge_driver = {
4146 .id_table = skge_id_table,
4147 .probe = skge_probe,
4148 .remove = __devexit_p(skge_remove),
4150 .suspend = skge_suspend,
4151 .resume = skge_resume,
4153 .shutdown = skge_shutdown,
4156 static int __init skge_init_module(void)
4159 return pci_register_driver(&skge_driver);
4162 static void __exit skge_cleanup_module(void)
4164 pci_unregister_driver(&skge_driver);
4165 skge_debug_cleanup();
4168 module_init(skge_init_module);
4169 module_exit(skge_cleanup_module);