2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 #include <linux/crc32.h>
26 #include <linux/kernel.h>
27 #include <linux/module.h>
28 #include <linux/netdevice.h>
29 #include <linux/dma-mapping.h>
30 #include <linux/etherdevice.h>
31 #include <linux/ethtool.h>
32 #include <linux/pci.h>
35 #include <linux/tcp.h>
37 #include <linux/delay.h>
38 #include <linux/workqueue.h>
39 #include <linux/if_vlan.h>
40 #include <linux/prefetch.h>
41 #include <linux/debugfs.h>
42 #include <linux/mii.h>
46 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
47 #define SKY2_VLAN_TAG_USED 1
52 #define DRV_NAME "sky2"
53 #define DRV_VERSION "1.24"
54 #define PFX DRV_NAME " "
57 * The Yukon II chipset takes 64 bit command blocks (called list elements)
58 * that are organized into three (receive, transmit, status) different rings
62 #define RX_LE_SIZE 1024
63 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
64 #define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
65 #define RX_DEF_PENDING RX_MAX_PENDING
67 /* This is the worst case number of transmit list elements for a single skb:
68 VLAN + TSO + CKSUM + Data + skb_frags * DMA */
69 #define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
70 #define TX_MIN_PENDING (MAX_SKB_TX_LE+1)
71 #define TX_MAX_PENDING 4096
72 #define TX_DEF_PENDING 127
74 #define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
75 #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
76 #define TX_WATCHDOG (5 * HZ)
77 #define NAPI_WEIGHT 64
78 #define PHY_RETRIES 1000
80 #define SKY2_EEPROM_MAGIC 0x9955aabb
83 #define RING_NEXT(x,s) (((x)+1) & ((s)-1))
85 static const u32 default_msg =
86 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
87 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
88 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
90 static int debug = -1; /* defaults above */
91 module_param(debug, int, 0);
92 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
94 static int copybreak __read_mostly = 128;
95 module_param(copybreak, int, 0);
96 MODULE_PARM_DESC(copybreak, "Receive copy threshold");
98 static int disable_msi = 0;
99 module_param(disable_msi, int, 0);
100 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
102 static DEFINE_PCI_DEVICE_TABLE(sky2_id_table) = {
103 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
104 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
105 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
108 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4354) }, /* 88E8040 */
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4355) }, /* 88E8040T */
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4357) }, /* 88E8042 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x435A) }, /* 88E8048 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) }, /* 88E8070 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
136 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
137 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
138 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436C) }, /* 88E8072 */
139 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436D) }, /* 88E8055 */
140 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4370) }, /* 88E8075 */
141 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4380) }, /* 88E8057 */
145 MODULE_DEVICE_TABLE(pci, sky2_id_table);
147 /* Avoid conditionals by using array */
148 static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
149 static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
150 static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
152 static void sky2_set_multicast(struct net_device *dev);
154 /* Access to PHY via serial interconnect */
155 static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
159 gma_write16(hw, port, GM_SMI_DATA, val);
160 gma_write16(hw, port, GM_SMI_CTRL,
161 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
163 for (i = 0; i < PHY_RETRIES; i++) {
164 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
168 if (!(ctrl & GM_SMI_CT_BUSY))
174 dev_warn(&hw->pdev->dev,"%s: phy write timeout\n", hw->dev[port]->name);
178 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
182 static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
186 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
187 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
189 for (i = 0; i < PHY_RETRIES; i++) {
190 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
194 if (ctrl & GM_SMI_CT_RD_VAL) {
195 *val = gma_read16(hw, port, GM_SMI_DATA);
202 dev_warn(&hw->pdev->dev, "%s: phy read timeout\n", hw->dev[port]->name);
205 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
209 static inline u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
212 __gm_phy_read(hw, port, reg, &v);
217 static void sky2_power_on(struct sky2_hw *hw)
219 /* switch power to VCC (WA for VAUX problem) */
220 sky2_write8(hw, B0_POWER_CTRL,
221 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
223 /* disable Core Clock Division, */
224 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
226 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
227 /* enable bits are inverted */
228 sky2_write8(hw, B2_Y2_CLK_GATE,
229 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
230 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
231 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
233 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
235 if (hw->flags & SKY2_HW_ADV_POWER_CTL) {
238 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
240 reg = sky2_pci_read32(hw, PCI_DEV_REG4);
241 /* set all bits to 0 except bits 15..12 and 8 */
242 reg &= P_ASPM_CONTROL_MSK;
243 sky2_pci_write32(hw, PCI_DEV_REG4, reg);
245 reg = sky2_pci_read32(hw, PCI_DEV_REG5);
246 /* set all bits to 0 except bits 28 & 27 */
247 reg &= P_CTL_TIM_VMAIN_AV_MSK;
248 sky2_pci_write32(hw, PCI_DEV_REG5, reg);
250 sky2_pci_write32(hw, PCI_CFG_REG_1, 0);
252 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
253 reg = sky2_read32(hw, B2_GP_IO);
254 reg |= GLB_GPIO_STAT_RACE_DIS;
255 sky2_write32(hw, B2_GP_IO, reg);
257 sky2_read32(hw, B2_GP_IO);
261 static void sky2_power_aux(struct sky2_hw *hw)
263 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
264 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
266 /* enable bits are inverted */
267 sky2_write8(hw, B2_Y2_CLK_GATE,
268 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
269 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
270 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
272 /* switch power to VAUX */
273 if (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL)
274 sky2_write8(hw, B0_POWER_CTRL,
275 (PC_VAUX_ENA | PC_VCC_ENA |
276 PC_VAUX_ON | PC_VCC_OFF));
279 static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
283 /* disable all GMAC IRQ's */
284 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
286 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
287 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
288 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
289 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
291 reg = gma_read16(hw, port, GM_RX_CTRL);
292 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
293 gma_write16(hw, port, GM_RX_CTRL, reg);
296 /* flow control to advertise bits */
297 static const u16 copper_fc_adv[] = {
299 [FC_TX] = PHY_M_AN_ASP,
300 [FC_RX] = PHY_M_AN_PC,
301 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
304 /* flow control to advertise bits when using 1000BaseX */
305 static const u16 fiber_fc_adv[] = {
306 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
307 [FC_TX] = PHY_M_P_ASYM_MD_X,
308 [FC_RX] = PHY_M_P_SYM_MD_X,
309 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
312 /* flow control to GMA disable bits */
313 static const u16 gm_fc_disable[] = {
314 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
315 [FC_TX] = GM_GPCR_FC_RX_DIS,
316 [FC_RX] = GM_GPCR_FC_TX_DIS,
321 static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
323 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
324 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
326 if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED) &&
327 !(hw->flags & SKY2_HW_NEWER_PHY)) {
328 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
330 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
332 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
334 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
335 if (hw->chip_id == CHIP_ID_YUKON_EC)
336 /* set downshift counter to 3x and enable downshift */
337 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
339 /* set master & slave downshift counter to 1x */
340 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
342 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
345 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
346 if (sky2_is_copper(hw)) {
347 if (!(hw->flags & SKY2_HW_GIGABIT)) {
348 /* enable automatic crossover */
349 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
351 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
352 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
355 /* Enable Class A driver for FE+ A0 */
356 spec = gm_phy_read(hw, port, PHY_MARV_FE_SPEC_2);
357 spec |= PHY_M_FESC_SEL_CL_A;
358 gm_phy_write(hw, port, PHY_MARV_FE_SPEC_2, spec);
361 /* disable energy detect */
362 ctrl &= ~PHY_M_PC_EN_DET_MSK;
364 /* enable automatic crossover */
365 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
367 /* downshift on PHY 88E1112 and 88E1149 is changed */
368 if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED)
369 && (hw->flags & SKY2_HW_NEWER_PHY)) {
370 /* set downshift counter to 3x and enable downshift */
371 ctrl &= ~PHY_M_PC_DSC_MSK;
372 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
376 /* workaround for deviation #4.88 (CRC errors) */
377 /* disable Automatic Crossover */
379 ctrl &= ~PHY_M_PC_MDIX_MSK;
382 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
384 /* special setup for PHY 88E1112 Fiber */
385 if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) {
386 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
388 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
389 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
390 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
391 ctrl &= ~PHY_M_MAC_MD_MSK;
392 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
393 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
395 if (hw->pmd_type == 'P') {
396 /* select page 1 to access Fiber registers */
397 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
399 /* for SFP-module set SIGDET polarity to low */
400 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
401 ctrl |= PHY_M_FIB_SIGD_POL;
402 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
405 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
413 if (sky2->flags & SKY2_FLAG_AUTO_SPEED) {
414 if (sky2_is_copper(hw)) {
415 if (sky2->advertising & ADVERTISED_1000baseT_Full)
416 ct1000 |= PHY_M_1000C_AFD;
417 if (sky2->advertising & ADVERTISED_1000baseT_Half)
418 ct1000 |= PHY_M_1000C_AHD;
419 if (sky2->advertising & ADVERTISED_100baseT_Full)
420 adv |= PHY_M_AN_100_FD;
421 if (sky2->advertising & ADVERTISED_100baseT_Half)
422 adv |= PHY_M_AN_100_HD;
423 if (sky2->advertising & ADVERTISED_10baseT_Full)
424 adv |= PHY_M_AN_10_FD;
425 if (sky2->advertising & ADVERTISED_10baseT_Half)
426 adv |= PHY_M_AN_10_HD;
428 } else { /* special defines for FIBER (88E1040S only) */
429 if (sky2->advertising & ADVERTISED_1000baseT_Full)
430 adv |= PHY_M_AN_1000X_AFD;
431 if (sky2->advertising & ADVERTISED_1000baseT_Half)
432 adv |= PHY_M_AN_1000X_AHD;
435 /* Restart Auto-negotiation */
436 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
438 /* forced speed/duplex settings */
439 ct1000 = PHY_M_1000C_MSE;
441 /* Disable auto update for duplex flow control and duplex */
442 reg |= GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_SPD_DIS;
444 switch (sky2->speed) {
446 ctrl |= PHY_CT_SP1000;
447 reg |= GM_GPCR_SPEED_1000;
450 ctrl |= PHY_CT_SP100;
451 reg |= GM_GPCR_SPEED_100;
455 if (sky2->duplex == DUPLEX_FULL) {
456 reg |= GM_GPCR_DUP_FULL;
457 ctrl |= PHY_CT_DUP_MD;
458 } else if (sky2->speed < SPEED_1000)
459 sky2->flow_mode = FC_NONE;
462 if (sky2->flags & SKY2_FLAG_AUTO_PAUSE) {
463 if (sky2_is_copper(hw))
464 adv |= copper_fc_adv[sky2->flow_mode];
466 adv |= fiber_fc_adv[sky2->flow_mode];
468 reg |= GM_GPCR_AU_FCT_DIS;
469 reg |= gm_fc_disable[sky2->flow_mode];
471 /* Forward pause packets to GMAC? */
472 if (sky2->flow_mode & FC_RX)
473 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
475 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
478 gma_write16(hw, port, GM_GP_CTRL, reg);
480 if (hw->flags & SKY2_HW_GIGABIT)
481 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
483 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
484 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
486 /* Setup Phy LED's */
487 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
490 switch (hw->chip_id) {
491 case CHIP_ID_YUKON_FE:
492 /* on 88E3082 these bits are at 11..9 (shifted left) */
493 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
495 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
497 /* delete ACT LED control bits */
498 ctrl &= ~PHY_M_FELP_LED1_MSK;
499 /* change ACT LED control to blink mode */
500 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
501 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
504 case CHIP_ID_YUKON_FE_P:
505 /* Enable Link Partner Next Page */
506 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
507 ctrl |= PHY_M_PC_ENA_LIP_NP;
509 /* disable Energy Detect and enable scrambler */
510 ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB);
511 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
513 /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */
514 ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) |
515 PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK) |
516 PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED);
518 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
521 case CHIP_ID_YUKON_XL:
522 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
524 /* select page 3 to access LED control register */
525 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
527 /* set LED Function Control register */
528 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
529 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
530 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
531 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
532 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
534 /* set Polarity Control register */
535 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
536 (PHY_M_POLC_LS1_P_MIX(4) |
537 PHY_M_POLC_IS0_P_MIX(4) |
538 PHY_M_POLC_LOS_CTRL(2) |
539 PHY_M_POLC_INIT_CTRL(2) |
540 PHY_M_POLC_STA1_CTRL(2) |
541 PHY_M_POLC_STA0_CTRL(2)));
543 /* restore page register */
544 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
547 case CHIP_ID_YUKON_EC_U:
548 case CHIP_ID_YUKON_EX:
549 case CHIP_ID_YUKON_SUPR:
550 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
552 /* select page 3 to access LED control register */
553 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
555 /* set LED Function Control register */
556 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
557 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
558 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
559 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
560 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
562 /* set Blink Rate in LED Timer Control Register */
563 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
564 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
565 /* restore page register */
566 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
570 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
571 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
573 /* turn off the Rx LED (LED_RX) */
574 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
577 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_UL_2) {
578 /* apply fixes in PHY AFE */
579 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
581 /* increase differential signal amplitude in 10BASE-T */
582 gm_phy_write(hw, port, 0x18, 0xaa99);
583 gm_phy_write(hw, port, 0x17, 0x2011);
585 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
586 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
587 gm_phy_write(hw, port, 0x18, 0xa204);
588 gm_phy_write(hw, port, 0x17, 0x2002);
591 /* set page register to 0 */
592 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
593 } else if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
594 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
595 /* apply workaround for integrated resistors calibration */
596 gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17);
597 gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60);
598 } else if (hw->chip_id != CHIP_ID_YUKON_EX &&
599 hw->chip_id < CHIP_ID_YUKON_SUPR) {
600 /* no effect on Yukon-XL */
601 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
603 if ( !(sky2->flags & SKY2_FLAG_AUTO_SPEED)
604 || sky2->speed == SPEED_100) {
605 /* turn on 100 Mbps LED (LED_LINK100) */
606 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
610 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
614 /* Enable phy interrupt on auto-negotiation complete (or link up) */
615 if (sky2->flags & SKY2_FLAG_AUTO_SPEED)
616 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
618 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
621 static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
622 static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA };
624 static void sky2_phy_power_up(struct sky2_hw *hw, unsigned port)
628 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
629 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
630 reg1 &= ~phy_power[port];
632 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
633 reg1 |= coma_mode[port];
635 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
636 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
637 sky2_pci_read32(hw, PCI_DEV_REG1);
639 if (hw->chip_id == CHIP_ID_YUKON_FE)
640 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_ANE);
641 else if (hw->flags & SKY2_HW_ADV_POWER_CTL)
642 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
645 static void sky2_phy_power_down(struct sky2_hw *hw, unsigned port)
650 /* release GPHY Control reset */
651 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
653 /* release GMAC reset */
654 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
656 if (hw->flags & SKY2_HW_NEWER_PHY) {
657 /* select page 2 to access MAC control register */
658 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
660 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
661 /* allow GMII Power Down */
662 ctrl &= ~PHY_M_MAC_GMIF_PUP;
663 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
665 /* set page register back to 0 */
666 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
669 /* setup General Purpose Control Register */
670 gma_write16(hw, port, GM_GP_CTRL,
671 GM_GPCR_FL_PASS | GM_GPCR_SPEED_100 |
672 GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS |
675 if (hw->chip_id != CHIP_ID_YUKON_EC) {
676 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
677 /* select page 2 to access MAC control register */
678 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
680 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
681 /* enable Power Down */
682 ctrl |= PHY_M_PC_POW_D_ENA;
683 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
685 /* set page register back to 0 */
686 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
689 /* set IEEE compatible Power Down Mode (dev. #4.99) */
690 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_PDOWN);
693 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
694 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
695 reg1 |= phy_power[port]; /* set PHY to PowerDown/COMA Mode */
696 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
697 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
700 /* Force a renegotiation */
701 static void sky2_phy_reinit(struct sky2_port *sky2)
703 spin_lock_bh(&sky2->phy_lock);
704 sky2_phy_init(sky2->hw, sky2->port);
705 spin_unlock_bh(&sky2->phy_lock);
708 /* Put device in state to listen for Wake On Lan */
709 static void sky2_wol_init(struct sky2_port *sky2)
711 struct sky2_hw *hw = sky2->hw;
712 unsigned port = sky2->port;
713 enum flow_control save_mode;
717 /* Bring hardware out of reset */
718 sky2_write16(hw, B0_CTST, CS_RST_CLR);
719 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
721 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
722 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
725 * sky2_reset will re-enable on resume
727 save_mode = sky2->flow_mode;
728 ctrl = sky2->advertising;
730 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
731 sky2->flow_mode = FC_NONE;
733 spin_lock_bh(&sky2->phy_lock);
734 sky2_phy_power_up(hw, port);
735 sky2_phy_init(hw, port);
736 spin_unlock_bh(&sky2->phy_lock);
738 sky2->flow_mode = save_mode;
739 sky2->advertising = ctrl;
741 /* Set GMAC to no flow control and auto update for speed/duplex */
742 gma_write16(hw, port, GM_GP_CTRL,
743 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
744 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
746 /* Set WOL address */
747 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
748 sky2->netdev->dev_addr, ETH_ALEN);
750 /* Turn on appropriate WOL control bits */
751 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
753 if (sky2->wol & WAKE_PHY)
754 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
756 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
758 if (sky2->wol & WAKE_MAGIC)
759 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
761 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;;
763 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
764 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
766 /* Turn on legacy PCI-Express PME mode */
767 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
768 reg1 |= PCI_Y2_PME_LEGACY;
769 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
772 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
776 static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
778 struct net_device *dev = hw->dev[port];
780 if ( (hw->chip_id == CHIP_ID_YUKON_EX &&
781 hw->chip_rev != CHIP_REV_YU_EX_A0) ||
782 hw->chip_id == CHIP_ID_YUKON_FE_P ||
783 hw->chip_id == CHIP_ID_YUKON_SUPR) {
784 /* Yukon-Extreme B0 and further Extreme devices */
785 /* enable Store & Forward mode for TX */
787 if (dev->mtu <= ETH_DATA_LEN)
788 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
789 TX_JUMBO_DIS | TX_STFW_ENA);
792 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
793 TX_JUMBO_ENA| TX_STFW_ENA);
795 if (dev->mtu <= ETH_DATA_LEN)
796 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
798 /* set Tx GMAC FIFO Almost Empty Threshold */
799 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
800 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
802 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
804 /* Can't do offload because of lack of store/forward */
805 dev->features &= ~(NETIF_F_TSO | NETIF_F_SG | NETIF_F_ALL_CSUM);
810 static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
812 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
816 const u8 *addr = hw->dev[port]->dev_addr;
818 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
819 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
821 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
823 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
824 /* WA DEV_472 -- looks like crossed wires on port 2 */
825 /* clear GMAC 1 Control reset */
826 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
828 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
829 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
830 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
831 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
832 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
835 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
837 /* Enable Transmit FIFO Underrun */
838 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
840 spin_lock_bh(&sky2->phy_lock);
841 sky2_phy_power_up(hw, port);
842 sky2_phy_init(hw, port);
843 spin_unlock_bh(&sky2->phy_lock);
846 reg = gma_read16(hw, port, GM_PHY_ADDR);
847 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
849 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
850 gma_read16(hw, port, i);
851 gma_write16(hw, port, GM_PHY_ADDR, reg);
853 /* transmit control */
854 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
856 /* receive control reg: unicast + multicast + no FCS */
857 gma_write16(hw, port, GM_RX_CTRL,
858 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
860 /* transmit flow control */
861 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
863 /* transmit parameter */
864 gma_write16(hw, port, GM_TX_PARAM,
865 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
866 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
867 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
868 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
870 /* serial mode register */
871 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
872 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
874 if (hw->dev[port]->mtu > ETH_DATA_LEN)
875 reg |= GM_SMOD_JUMBO_ENA;
877 gma_write16(hw, port, GM_SERIAL_MODE, reg);
879 /* virtual address for data */
880 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
882 /* physical address: used for pause frames */
883 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
885 /* ignore counter overflows */
886 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
887 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
888 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
890 /* Configure Rx MAC FIFO */
891 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
892 rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
893 if (hw->chip_id == CHIP_ID_YUKON_EX ||
894 hw->chip_id == CHIP_ID_YUKON_FE_P)
895 rx_reg |= GMF_RX_OVER_ON;
897 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg);
899 if (hw->chip_id == CHIP_ID_YUKON_XL) {
900 /* Hardware errata - clear flush mask */
901 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), 0);
903 /* Flush Rx MAC FIFO on any flow control or error */
904 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
907 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
908 reg = RX_GMF_FL_THR_DEF + 1;
909 /* Another magic mystery workaround from sk98lin */
910 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
911 hw->chip_rev == CHIP_REV_YU_FE2_A0)
913 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg);
915 /* Configure Tx MAC FIFO */
916 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
917 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
919 /* On chips without ram buffer, pause is controled by MAC level */
920 if (!(hw->flags & SKY2_HW_RAM_BUFFER)) {
921 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
922 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
924 sky2_set_tx_stfwd(hw, port);
927 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
928 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
929 /* disable dynamic watermark */
930 reg = sky2_read16(hw, SK_REG(port, TX_GMF_EA));
931 reg &= ~TX_DYN_WM_ENA;
932 sky2_write16(hw, SK_REG(port, TX_GMF_EA), reg);
936 /* Assign Ram Buffer allocation to queue */
937 static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
941 /* convert from K bytes to qwords used for hw register */
944 end = start + space - 1;
946 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
947 sky2_write32(hw, RB_ADDR(q, RB_START), start);
948 sky2_write32(hw, RB_ADDR(q, RB_END), end);
949 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
950 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
952 if (q == Q_R1 || q == Q_R2) {
953 u32 tp = space - space/4;
955 /* On receive queue's set the thresholds
956 * give receiver priority when > 3/4 full
957 * send pause when down to 2K
959 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
960 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
963 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
964 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
966 /* Enable store & forward on Tx queue's because
967 * Tx FIFO is only 1K on Yukon
969 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
972 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
973 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
976 /* Setup Bus Memory Interface */
977 static void sky2_qset(struct sky2_hw *hw, u16 q)
979 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
980 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
981 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
982 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
985 /* Setup prefetch unit registers. This is the interface between
986 * hardware and driver list elements
988 static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
989 dma_addr_t addr, u32 last)
991 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
992 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
993 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), upper_32_bits(addr));
994 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), lower_32_bits(addr));
995 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
996 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
998 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
1001 static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2, u16 *slot)
1003 struct sky2_tx_le *le = sky2->tx_le + *slot;
1005 *slot = RING_NEXT(*slot, sky2->tx_ring_size);
1010 static void tx_init(struct sky2_port *sky2)
1012 struct sky2_tx_le *le;
1014 sky2->tx_prod = sky2->tx_cons = 0;
1015 sky2->tx_tcpsum = 0;
1016 sky2->tx_last_mss = 0;
1018 le = get_tx_le(sky2, &sky2->tx_prod);
1020 le->opcode = OP_ADDR64 | HW_OWNER;
1021 sky2->tx_last_upper = 0;
1024 static inline struct tx_ring_info *tx_le_re(struct sky2_port *sky2,
1025 struct sky2_tx_le *le)
1027 return sky2->tx_ring + (le - sky2->tx_le);
1030 /* Update chip's next pointer */
1031 static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
1033 /* Make sure write' to descriptors are complete before we tell hardware */
1035 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
1037 /* Synchronize I/O on since next processor may write to tail */
1042 static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
1044 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
1045 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
1050 /* Build description to hardware for one receive segment */
1051 static void sky2_rx_add(struct sky2_port *sky2, u8 op,
1052 dma_addr_t map, unsigned len)
1054 struct sky2_rx_le *le;
1056 if (sizeof(dma_addr_t) > sizeof(u32)) {
1057 le = sky2_next_rx(sky2);
1058 le->addr = cpu_to_le32(upper_32_bits(map));
1059 le->opcode = OP_ADDR64 | HW_OWNER;
1062 le = sky2_next_rx(sky2);
1063 le->addr = cpu_to_le32(lower_32_bits(map));
1064 le->length = cpu_to_le16(len);
1065 le->opcode = op | HW_OWNER;
1068 /* Build description to hardware for one possibly fragmented skb */
1069 static void sky2_rx_submit(struct sky2_port *sky2,
1070 const struct rx_ring_info *re)
1074 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
1076 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
1077 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
1081 static int sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
1084 struct sk_buff *skb = re->skb;
1087 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
1088 if (unlikely(pci_dma_mapping_error(pdev, re->data_addr)))
1091 pci_unmap_len_set(re, data_size, size);
1093 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1094 re->frag_addr[i] = pci_map_page(pdev,
1095 skb_shinfo(skb)->frags[i].page,
1096 skb_shinfo(skb)->frags[i].page_offset,
1097 skb_shinfo(skb)->frags[i].size,
1098 PCI_DMA_FROMDEVICE);
1102 static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
1104 struct sk_buff *skb = re->skb;
1107 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
1108 PCI_DMA_FROMDEVICE);
1110 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1111 pci_unmap_page(pdev, re->frag_addr[i],
1112 skb_shinfo(skb)->frags[i].size,
1113 PCI_DMA_FROMDEVICE);
1116 /* Tell chip where to start receive checksum.
1117 * Actually has two checksums, but set both same to avoid possible byte
1120 static void rx_set_checksum(struct sky2_port *sky2)
1122 struct sky2_rx_le *le = sky2_next_rx(sky2);
1124 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
1126 le->opcode = OP_TCPSTART | HW_OWNER;
1128 sky2_write32(sky2->hw,
1129 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1130 (sky2->flags & SKY2_FLAG_RX_CHECKSUM)
1131 ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
1135 * The RX Stop command will not work for Yukon-2 if the BMU does not
1136 * reach the end of packet and since we can't make sure that we have
1137 * incoming data, we must reset the BMU while it is not doing a DMA
1138 * transfer. Since it is possible that the RX path is still active,
1139 * the RX RAM buffer will be stopped first, so any possible incoming
1140 * data will not trigger a DMA. After the RAM buffer is stopped, the
1141 * BMU is polled until any DMA in progress is ended and only then it
1144 static void sky2_rx_stop(struct sky2_port *sky2)
1146 struct sky2_hw *hw = sky2->hw;
1147 unsigned rxq = rxqaddr[sky2->port];
1150 /* disable the RAM Buffer receive queue */
1151 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
1153 for (i = 0; i < 0xffff; i++)
1154 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
1155 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
1158 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
1159 sky2->netdev->name);
1161 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
1163 /* reset the Rx prefetch unit */
1164 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1168 /* Clean out receive buffer area, assumes receiver hardware stopped */
1169 static void sky2_rx_clean(struct sky2_port *sky2)
1173 memset(sky2->rx_le, 0, RX_LE_BYTES);
1174 for (i = 0; i < sky2->rx_pending; i++) {
1175 struct rx_ring_info *re = sky2->rx_ring + i;
1178 sky2_rx_unmap_skb(sky2->hw->pdev, re);
1183 skb_queue_purge(&sky2->rx_recycle);
1186 /* Basic MII support */
1187 static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1189 struct mii_ioctl_data *data = if_mii(ifr);
1190 struct sky2_port *sky2 = netdev_priv(dev);
1191 struct sky2_hw *hw = sky2->hw;
1192 int err = -EOPNOTSUPP;
1194 if (!netif_running(dev))
1195 return -ENODEV; /* Phy still in reset */
1199 data->phy_id = PHY_ADDR_MARV;
1205 spin_lock_bh(&sky2->phy_lock);
1206 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
1207 spin_unlock_bh(&sky2->phy_lock);
1209 data->val_out = val;
1214 if (!capable(CAP_NET_ADMIN))
1217 spin_lock_bh(&sky2->phy_lock);
1218 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1220 spin_unlock_bh(&sky2->phy_lock);
1226 #ifdef SKY2_VLAN_TAG_USED
1227 static void sky2_set_vlan_mode(struct sky2_hw *hw, u16 port, bool onoff)
1230 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1232 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1235 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1237 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1242 static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1244 struct sky2_port *sky2 = netdev_priv(dev);
1245 struct sky2_hw *hw = sky2->hw;
1246 u16 port = sky2->port;
1248 netif_tx_lock_bh(dev);
1249 napi_disable(&hw->napi);
1252 sky2_set_vlan_mode(hw, port, grp != NULL);
1254 sky2_read32(hw, B0_Y2_SP_LISR);
1255 napi_enable(&hw->napi);
1256 netif_tx_unlock_bh(dev);
1260 /* Amount of required worst case padding in rx buffer */
1261 static inline unsigned sky2_rx_pad(const struct sky2_hw *hw)
1263 return (hw->flags & SKY2_HW_RAM_BUFFER) ? 8 : 2;
1267 * Allocate an skb for receiving. If the MTU is large enough
1268 * make the skb non-linear with a fragment list of pages.
1270 static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
1272 struct sk_buff *skb;
1275 skb = __skb_dequeue(&sky2->rx_recycle);
1277 skb = netdev_alloc_skb(sky2->netdev, sky2->rx_data_size
1278 + sky2_rx_pad(sky2->hw));
1282 if (sky2->hw->flags & SKY2_HW_RAM_BUFFER) {
1283 unsigned char *start;
1285 * Workaround for a bug in FIFO that cause hang
1286 * if the FIFO if the receive buffer is not 64 byte aligned.
1287 * The buffer returned from netdev_alloc_skb is
1288 * aligned except if slab debugging is enabled.
1290 start = PTR_ALIGN(skb->data, 8);
1291 skb_reserve(skb, start - skb->data);
1293 skb_reserve(skb, NET_IP_ALIGN);
1295 for (i = 0; i < sky2->rx_nfrags; i++) {
1296 struct page *page = alloc_page(GFP_ATOMIC);
1300 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
1310 static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq)
1312 sky2_put_idx(sky2->hw, rxq, sky2->rx_put);
1316 * Allocate and setup receiver buffer pool.
1317 * Normal case this ends up creating one list element for skb
1318 * in the receive ring. Worst case if using large MTU and each
1319 * allocation falls on a different 64 bit region, that results
1320 * in 6 list elements per ring entry.
1321 * One element is used for checksum enable/disable, and one
1322 * extra to avoid wrap.
1324 static int sky2_rx_start(struct sky2_port *sky2)
1326 struct sky2_hw *hw = sky2->hw;
1327 struct rx_ring_info *re;
1328 unsigned rxq = rxqaddr[sky2->port];
1329 unsigned i, size, thresh;
1331 sky2->rx_put = sky2->rx_next = 0;
1334 /* On PCI express lowering the watermark gives better performance */
1335 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
1336 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1338 /* These chips have no ram buffer?
1339 * MAC Rx RAM Read is controlled by hardware */
1340 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
1341 (hw->chip_rev == CHIP_REV_YU_EC_U_A1
1342 || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
1343 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
1345 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1347 if (!(hw->flags & SKY2_HW_NEW_LE))
1348 rx_set_checksum(sky2);
1350 /* Space needed for frame data + headers rounded up */
1351 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
1353 /* Stopping point for hardware truncation */
1354 thresh = (size - 8) / sizeof(u32);
1356 sky2->rx_nfrags = size >> PAGE_SHIFT;
1357 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1359 /* Compute residue after pages */
1360 size -= sky2->rx_nfrags << PAGE_SHIFT;
1362 /* Optimize to handle small packets and headers */
1363 if (size < copybreak)
1365 if (size < ETH_HLEN)
1368 sky2->rx_data_size = size;
1370 skb_queue_head_init(&sky2->rx_recycle);
1373 for (i = 0; i < sky2->rx_pending; i++) {
1374 re = sky2->rx_ring + i;
1376 re->skb = sky2_rx_alloc(sky2);
1380 if (sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size)) {
1381 dev_kfree_skb(re->skb);
1386 sky2_rx_submit(sky2, re);
1390 * The receiver hangs if it receives frames larger than the
1391 * packet buffer. As a workaround, truncate oversize frames, but
1392 * the register is limited to 9 bits, so if you do frames > 2052
1393 * you better get the MTU right!
1396 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1398 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1399 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1402 /* Tell chip about available buffers */
1403 sky2_rx_update(sky2, rxq);
1406 sky2_rx_clean(sky2);
1410 /* Bring up network interface. */
1411 static int sky2_up(struct net_device *dev)
1413 struct sky2_port *sky2 = netdev_priv(dev);
1414 struct sky2_hw *hw = sky2->hw;
1415 unsigned port = sky2->port;
1417 int cap, err = -ENOMEM;
1418 struct net_device *otherdev = hw->dev[sky2->port^1];
1421 * On dual port PCI-X card, there is an problem where status
1422 * can be received out of order due to split transactions
1424 if (otherdev && netif_running(otherdev) &&
1425 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1428 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
1429 cmd &= ~PCI_X_CMD_MAX_SPLIT;
1430 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1434 netif_carrier_off(dev);
1436 /* must be power of 2 */
1437 sky2->tx_le = pci_alloc_consistent(hw->pdev,
1438 sky2->tx_ring_size *
1439 sizeof(struct sky2_tx_le),
1444 sky2->tx_ring = kcalloc(sky2->tx_ring_size, sizeof(struct tx_ring_info),
1451 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1455 memset(sky2->rx_le, 0, RX_LE_BYTES);
1457 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
1462 sky2_mac_init(hw, port);
1464 /* Register is number of 4K blocks on internal RAM buffer. */
1465 ramsize = sky2_read8(hw, B2_E_0) * 4;
1469 hw->flags |= SKY2_HW_RAM_BUFFER;
1470 pr_debug(PFX "%s: ram buffer %dK\n", dev->name, ramsize);
1472 rxspace = ramsize / 2;
1474 rxspace = 8 + (2*(ramsize - 16))/3;
1476 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1477 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1479 /* Make sure SyncQ is disabled */
1480 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1484 sky2_qset(hw, txqaddr[port]);
1486 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1487 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0)
1488 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF);
1490 /* Set almost empty threshold */
1491 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1492 && hw->chip_rev == CHIP_REV_YU_EC_U_A0)
1493 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
1495 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1496 sky2->tx_ring_size - 1);
1498 #ifdef SKY2_VLAN_TAG_USED
1499 sky2_set_vlan_mode(hw, port, sky2->vlgrp != NULL);
1502 err = sky2_rx_start(sky2);
1506 /* Enable interrupts from phy/mac for port */
1507 imask = sky2_read32(hw, B0_IMSK);
1508 imask |= portirq_msk[port];
1509 sky2_write32(hw, B0_IMSK, imask);
1510 sky2_read32(hw, B0_IMSK);
1512 if (netif_msg_ifup(sky2))
1513 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1519 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1520 sky2->rx_le, sky2->rx_le_map);
1524 pci_free_consistent(hw->pdev,
1525 sky2->tx_ring_size * sizeof(struct sky2_tx_le),
1526 sky2->tx_le, sky2->tx_le_map);
1529 kfree(sky2->tx_ring);
1530 kfree(sky2->rx_ring);
1532 sky2->tx_ring = NULL;
1533 sky2->rx_ring = NULL;
1537 /* Modular subtraction in ring */
1538 static inline int tx_inuse(const struct sky2_port *sky2)
1540 return (sky2->tx_prod - sky2->tx_cons) & (sky2->tx_ring_size - 1);
1543 /* Number of list elements available for next tx */
1544 static inline int tx_avail(const struct sky2_port *sky2)
1546 return sky2->tx_pending - tx_inuse(sky2);
1549 /* Estimate of number of transmit list elements required */
1550 static unsigned tx_le_req(const struct sk_buff *skb)
1554 count = sizeof(dma_addr_t) / sizeof(u32);
1555 count += skb_shinfo(skb)->nr_frags * count;
1557 if (skb_is_gso(skb))
1560 if (skb->ip_summed == CHECKSUM_PARTIAL)
1567 * Put one packet in ring for transmit.
1568 * A single packet can generate multiple list elements, and
1569 * the number of ring elements will probably be less than the number
1570 * of list elements used.
1572 static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1574 struct sky2_port *sky2 = netdev_priv(dev);
1575 struct sky2_hw *hw = sky2->hw;
1576 struct sky2_tx_le *le = NULL;
1577 struct tx_ring_info *re;
1585 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1586 return NETDEV_TX_BUSY;
1588 len = skb_headlen(skb);
1589 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
1591 if (pci_dma_mapping_error(hw->pdev, mapping))
1594 slot = sky2->tx_prod;
1595 if (unlikely(netif_msg_tx_queued(sky2)))
1596 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1597 dev->name, slot, skb->len);
1599 /* Send high bits if needed */
1600 upper = upper_32_bits(mapping);
1601 if (upper != sky2->tx_last_upper) {
1602 le = get_tx_le(sky2, &slot);
1603 le->addr = cpu_to_le32(upper);
1604 sky2->tx_last_upper = upper;
1605 le->opcode = OP_ADDR64 | HW_OWNER;
1608 /* Check for TCP Segmentation Offload */
1609 mss = skb_shinfo(skb)->gso_size;
1612 if (!(hw->flags & SKY2_HW_NEW_LE))
1613 mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb);
1615 if (mss != sky2->tx_last_mss) {
1616 le = get_tx_le(sky2, &slot);
1617 le->addr = cpu_to_le32(mss);
1619 if (hw->flags & SKY2_HW_NEW_LE)
1620 le->opcode = OP_MSS | HW_OWNER;
1622 le->opcode = OP_LRGLEN | HW_OWNER;
1623 sky2->tx_last_mss = mss;
1628 #ifdef SKY2_VLAN_TAG_USED
1629 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1630 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1632 le = get_tx_le(sky2, &slot);
1634 le->opcode = OP_VLAN|HW_OWNER;
1636 le->opcode |= OP_VLAN;
1637 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1642 /* Handle TCP checksum offload */
1643 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1644 /* On Yukon EX (some versions) encoding change. */
1645 if (hw->flags & SKY2_HW_AUTO_TX_SUM)
1646 ctrl |= CALSUM; /* auto checksum */
1648 const unsigned offset = skb_transport_offset(skb);
1651 tcpsum = offset << 16; /* sum start */
1652 tcpsum |= offset + skb->csum_offset; /* sum write */
1654 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1655 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1658 if (tcpsum != sky2->tx_tcpsum) {
1659 sky2->tx_tcpsum = tcpsum;
1661 le = get_tx_le(sky2, &slot);
1662 le->addr = cpu_to_le32(tcpsum);
1663 le->length = 0; /* initial checksum value */
1664 le->ctrl = 1; /* one packet */
1665 le->opcode = OP_TCPLISW | HW_OWNER;
1670 le = get_tx_le(sky2, &slot);
1671 le->addr = cpu_to_le32(lower_32_bits(mapping));
1672 le->length = cpu_to_le16(len);
1674 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
1676 re = tx_le_re(sky2, le);
1678 pci_unmap_addr_set(re, mapaddr, mapping);
1679 pci_unmap_len_set(re, maplen, len);
1681 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1682 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1684 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1685 frag->size, PCI_DMA_TODEVICE);
1687 if (pci_dma_mapping_error(hw->pdev, mapping))
1688 goto mapping_unwind;
1690 upper = upper_32_bits(mapping);
1691 if (upper != sky2->tx_last_upper) {
1692 le = get_tx_le(sky2, &slot);
1693 le->addr = cpu_to_le32(upper);
1694 sky2->tx_last_upper = upper;
1695 le->opcode = OP_ADDR64 | HW_OWNER;
1698 le = get_tx_le(sky2, &slot);
1699 le->addr = cpu_to_le32(lower_32_bits(mapping));
1700 le->length = cpu_to_le16(frag->size);
1702 le->opcode = OP_BUFFER | HW_OWNER;
1704 re = tx_le_re(sky2, le);
1706 pci_unmap_addr_set(re, mapaddr, mapping);
1707 pci_unmap_len_set(re, maplen, frag->size);
1712 sky2->tx_prod = slot;
1714 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1715 netif_stop_queue(dev);
1717 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
1719 return NETDEV_TX_OK;
1722 for (i = sky2->tx_prod; i != slot; i = RING_NEXT(i, sky2->tx_ring_size)) {
1723 le = sky2->tx_le + i;
1724 re = sky2->tx_ring + i;
1726 switch(le->opcode & ~HW_OWNER) {
1729 pci_unmap_single(hw->pdev,
1730 pci_unmap_addr(re, mapaddr),
1731 pci_unmap_len(re, maplen),
1735 pci_unmap_page(hw->pdev, pci_unmap_addr(re, mapaddr),
1736 pci_unmap_len(re, maplen),
1743 if (net_ratelimit())
1744 dev_warn(&hw->pdev->dev, "%s: tx mapping error\n", dev->name);
1746 return NETDEV_TX_OK;
1750 * Free ring elements from starting at tx_cons until "done"
1753 * 1. The hardware will tell us about partial completion of multi-part
1754 * buffers so make sure not to free skb to early.
1755 * 2. This may run in parallel start_xmit because the it only
1756 * looks at the tail of the queue of FIFO (tx_cons), not
1757 * the head (tx_prod)
1759 static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
1761 struct net_device *dev = sky2->netdev;
1762 struct pci_dev *pdev = sky2->hw->pdev;
1765 BUG_ON(done >= sky2->tx_ring_size);
1767 for (idx = sky2->tx_cons; idx != done;
1768 idx = RING_NEXT(idx, sky2->tx_ring_size)) {
1769 struct sky2_tx_le *le = sky2->tx_le + idx;
1770 struct tx_ring_info *re = sky2->tx_ring + idx;
1772 switch(le->opcode & ~HW_OWNER) {
1775 pci_unmap_single(pdev,
1776 pci_unmap_addr(re, mapaddr),
1777 pci_unmap_len(re, maplen),
1781 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1782 pci_unmap_len(re, maplen),
1787 if (le->ctrl & EOP) {
1788 struct sk_buff *skb = re->skb;
1790 if (unlikely(netif_msg_tx_done(sky2)))
1791 printk(KERN_DEBUG "%s: tx done %u\n",
1794 dev->stats.tx_packets++;
1795 dev->stats.tx_bytes += skb->len;
1797 if (skb_queue_len(&sky2->rx_recycle) < sky2->rx_pending
1798 && skb_recycle_check(skb, sky2->rx_data_size
1799 + sky2_rx_pad(sky2->hw)))
1800 __skb_queue_head(&sky2->rx_recycle, skb);
1802 dev_kfree_skb_any(skb);
1804 sky2->tx_next = RING_NEXT(idx, sky2->tx_ring_size);
1808 sky2->tx_cons = idx;
1811 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
1812 netif_wake_queue(dev);
1815 static void sky2_tx_reset(struct sky2_hw *hw, unsigned port)
1817 /* Disable Force Sync bit and Enable Alloc bit */
1818 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1819 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1821 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1822 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1823 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1825 /* Reset the PCI FIFO of the async Tx queue */
1826 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1827 BMU_RST_SET | BMU_FIFO_RST);
1829 /* Reset the Tx prefetch units */
1830 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1833 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1834 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1837 /* Network shutdown */
1838 static int sky2_down(struct net_device *dev)
1840 struct sky2_port *sky2 = netdev_priv(dev);
1841 struct sky2_hw *hw = sky2->hw;
1842 unsigned port = sky2->port;
1846 /* Never really got started! */
1850 if (netif_msg_ifdown(sky2))
1851 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1853 /* Force flow control off */
1854 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1856 /* Stop transmitter */
1857 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1858 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1860 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
1861 RB_RST_SET | RB_DIS_OP_MD);
1863 ctrl = gma_read16(hw, port, GM_GP_CTRL);
1864 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
1865 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1867 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1869 /* Workaround shared GMAC reset */
1870 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1871 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
1872 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1874 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1876 /* Force any delayed status interrrupt and NAPI */
1877 sky2_write32(hw, STAT_LEV_TIMER_CNT, 0);
1878 sky2_write32(hw, STAT_TX_TIMER_CNT, 0);
1879 sky2_write32(hw, STAT_ISR_TIMER_CNT, 0);
1880 sky2_read8(hw, STAT_ISR_TIMER_CTRL);
1884 /* Disable port IRQ */
1885 imask = sky2_read32(hw, B0_IMSK);
1886 imask &= ~portirq_msk[port];
1887 sky2_write32(hw, B0_IMSK, imask);
1888 sky2_read32(hw, B0_IMSK);
1890 synchronize_irq(hw->pdev->irq);
1891 napi_synchronize(&hw->napi);
1893 spin_lock_bh(&sky2->phy_lock);
1894 sky2_phy_power_down(hw, port);
1895 spin_unlock_bh(&sky2->phy_lock);
1897 /* turn off LED's */
1898 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1900 sky2_tx_reset(hw, port);
1902 /* Free any pending frames stuck in HW queue */
1903 sky2_tx_complete(sky2, sky2->tx_prod);
1905 sky2_rx_clean(sky2);
1907 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1908 sky2->rx_le, sky2->rx_le_map);
1909 kfree(sky2->rx_ring);
1911 pci_free_consistent(hw->pdev,
1912 sky2->tx_ring_size * sizeof(struct sky2_tx_le),
1913 sky2->tx_le, sky2->tx_le_map);
1914 kfree(sky2->tx_ring);
1919 sky2->rx_ring = NULL;
1920 sky2->tx_ring = NULL;
1925 static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1927 if (hw->flags & SKY2_HW_FIBRE_PHY)
1930 if (!(hw->flags & SKY2_HW_GIGABIT)) {
1931 if (aux & PHY_M_PS_SPEED_100)
1937 switch (aux & PHY_M_PS_SPEED_MSK) {
1938 case PHY_M_PS_SPEED_1000:
1940 case PHY_M_PS_SPEED_100:
1947 static void sky2_link_up(struct sky2_port *sky2)
1949 struct sky2_hw *hw = sky2->hw;
1950 unsigned port = sky2->port;
1952 static const char *fc_name[] = {
1960 reg = gma_read16(hw, port, GM_GP_CTRL);
1961 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1962 gma_write16(hw, port, GM_GP_CTRL, reg);
1964 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1966 netif_carrier_on(sky2->netdev);
1968 mod_timer(&hw->watchdog_timer, jiffies + 1);
1970 /* Turn on link LED */
1971 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
1972 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1974 if (netif_msg_link(sky2))
1975 printk(KERN_INFO PFX
1976 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
1977 sky2->netdev->name, sky2->speed,
1978 sky2->duplex == DUPLEX_FULL ? "full" : "half",
1979 fc_name[sky2->flow_status]);
1982 static void sky2_link_down(struct sky2_port *sky2)
1984 struct sky2_hw *hw = sky2->hw;
1985 unsigned port = sky2->port;
1988 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1990 reg = gma_read16(hw, port, GM_GP_CTRL);
1991 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1992 gma_write16(hw, port, GM_GP_CTRL, reg);
1994 netif_carrier_off(sky2->netdev);
1996 /* Turn on link LED */
1997 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1999 if (netif_msg_link(sky2))
2000 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
2002 sky2_phy_init(hw, port);
2005 static enum flow_control sky2_flow(int rx, int tx)
2008 return tx ? FC_BOTH : FC_RX;
2010 return tx ? FC_TX : FC_NONE;
2013 static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
2015 struct sky2_hw *hw = sky2->hw;
2016 unsigned port = sky2->port;
2019 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
2020 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
2021 if (lpa & PHY_M_AN_RF) {
2022 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
2026 if (!(aux & PHY_M_PS_SPDUP_RES)) {
2027 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
2028 sky2->netdev->name);
2032 sky2->speed = sky2_phy_speed(hw, aux);
2033 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2035 /* Since the pause result bits seem to in different positions on
2036 * different chips. look at registers.
2038 if (hw->flags & SKY2_HW_FIBRE_PHY) {
2039 /* Shift for bits in fiber PHY */
2040 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
2041 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
2043 if (advert & ADVERTISE_1000XPAUSE)
2044 advert |= ADVERTISE_PAUSE_CAP;
2045 if (advert & ADVERTISE_1000XPSE_ASYM)
2046 advert |= ADVERTISE_PAUSE_ASYM;
2047 if (lpa & LPA_1000XPAUSE)
2048 lpa |= LPA_PAUSE_CAP;
2049 if (lpa & LPA_1000XPAUSE_ASYM)
2050 lpa |= LPA_PAUSE_ASYM;
2053 sky2->flow_status = FC_NONE;
2054 if (advert & ADVERTISE_PAUSE_CAP) {
2055 if (lpa & LPA_PAUSE_CAP)
2056 sky2->flow_status = FC_BOTH;
2057 else if (advert & ADVERTISE_PAUSE_ASYM)
2058 sky2->flow_status = FC_RX;
2059 } else if (advert & ADVERTISE_PAUSE_ASYM) {
2060 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
2061 sky2->flow_status = FC_TX;
2064 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000
2065 && !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
2066 sky2->flow_status = FC_NONE;
2068 if (sky2->flow_status & FC_TX)
2069 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
2071 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2076 /* Interrupt from PHY */
2077 static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
2079 struct net_device *dev = hw->dev[port];
2080 struct sky2_port *sky2 = netdev_priv(dev);
2081 u16 istatus, phystat;
2083 if (!netif_running(dev))
2086 spin_lock(&sky2->phy_lock);
2087 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
2088 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
2090 if (netif_msg_intr(sky2))
2091 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
2092 sky2->netdev->name, istatus, phystat);
2094 if (istatus & PHY_M_IS_AN_COMPL) {
2095 if (sky2_autoneg_done(sky2, phystat) == 0)
2100 if (istatus & PHY_M_IS_LSP_CHANGE)
2101 sky2->speed = sky2_phy_speed(hw, phystat);
2103 if (istatus & PHY_M_IS_DUP_CHANGE)
2105 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2107 if (istatus & PHY_M_IS_LST_CHANGE) {
2108 if (phystat & PHY_M_PS_LINK_UP)
2111 sky2_link_down(sky2);
2114 spin_unlock(&sky2->phy_lock);
2117 /* Transmit timeout is only called if we are running, carrier is up
2118 * and tx queue is full (stopped).
2120 static void sky2_tx_timeout(struct net_device *dev)
2122 struct sky2_port *sky2 = netdev_priv(dev);
2123 struct sky2_hw *hw = sky2->hw;
2125 if (netif_msg_timer(sky2))
2126 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
2128 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
2129 dev->name, sky2->tx_cons, sky2->tx_prod,
2130 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
2131 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
2133 /* can't restart safely under softirq */
2134 schedule_work(&hw->restart_work);
2137 static int sky2_change_mtu(struct net_device *dev, int new_mtu)
2139 struct sky2_port *sky2 = netdev_priv(dev);
2140 struct sky2_hw *hw = sky2->hw;
2141 unsigned port = sky2->port;
2146 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2149 if (new_mtu > ETH_DATA_LEN &&
2150 (hw->chip_id == CHIP_ID_YUKON_FE ||
2151 hw->chip_id == CHIP_ID_YUKON_FE_P))
2154 if (!netif_running(dev)) {
2159 imask = sky2_read32(hw, B0_IMSK);
2160 sky2_write32(hw, B0_IMSK, 0);
2162 dev->trans_start = jiffies; /* prevent tx timeout */
2163 netif_stop_queue(dev);
2164 napi_disable(&hw->napi);
2166 synchronize_irq(hw->pdev->irq);
2168 if (!(hw->flags & SKY2_HW_RAM_BUFFER))
2169 sky2_set_tx_stfwd(hw, port);
2171 ctl = gma_read16(hw, port, GM_GP_CTRL);
2172 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
2174 sky2_rx_clean(sky2);
2178 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
2179 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
2181 if (dev->mtu > ETH_DATA_LEN)
2182 mode |= GM_SMOD_JUMBO_ENA;
2184 gma_write16(hw, port, GM_SERIAL_MODE, mode);
2186 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
2188 err = sky2_rx_start(sky2);
2189 sky2_write32(hw, B0_IMSK, imask);
2191 sky2_read32(hw, B0_Y2_SP_LISR);
2192 napi_enable(&hw->napi);
2197 gma_write16(hw, port, GM_GP_CTRL, ctl);
2199 netif_wake_queue(dev);
2205 /* For small just reuse existing skb for next receive */
2206 static struct sk_buff *receive_copy(struct sky2_port *sky2,
2207 const struct rx_ring_info *re,
2210 struct sk_buff *skb;
2212 skb = netdev_alloc_skb(sky2->netdev, length + 2);
2214 skb_reserve(skb, 2);
2215 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
2216 length, PCI_DMA_FROMDEVICE);
2217 skb_copy_from_linear_data(re->skb, skb->data, length);
2218 skb->ip_summed = re->skb->ip_summed;
2219 skb->csum = re->skb->csum;
2220 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
2221 length, PCI_DMA_FROMDEVICE);
2222 re->skb->ip_summed = CHECKSUM_NONE;
2223 skb_put(skb, length);
2228 /* Adjust length of skb with fragments to match received data */
2229 static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
2230 unsigned int length)
2235 /* put header into skb */
2236 size = min(length, hdr_space);
2241 num_frags = skb_shinfo(skb)->nr_frags;
2242 for (i = 0; i < num_frags; i++) {
2243 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2246 /* don't need this page */
2247 __free_page(frag->page);
2248 --skb_shinfo(skb)->nr_frags;
2250 size = min(length, (unsigned) PAGE_SIZE);
2253 skb->data_len += size;
2254 skb->truesize += size;
2261 /* Normal packet - take skb from ring element and put in a new one */
2262 static struct sk_buff *receive_new(struct sky2_port *sky2,
2263 struct rx_ring_info *re,
2264 unsigned int length)
2266 struct sk_buff *skb, *nskb;
2267 unsigned hdr_space = sky2->rx_data_size;
2269 /* Don't be tricky about reusing pages (yet) */
2270 nskb = sky2_rx_alloc(sky2);
2271 if (unlikely(!nskb))
2275 sky2_rx_unmap_skb(sky2->hw->pdev, re);
2277 prefetch(skb->data);
2279 if (sky2_rx_map_skb(sky2->hw->pdev, re, hdr_space)) {
2280 dev_kfree_skb(nskb);
2285 if (skb_shinfo(skb)->nr_frags)
2286 skb_put_frags(skb, hdr_space, length);
2288 skb_put(skb, length);
2293 * Receive one packet.
2294 * For larger packets, get new buffer.
2296 static struct sk_buff *sky2_receive(struct net_device *dev,
2297 u16 length, u32 status)
2299 struct sky2_port *sky2 = netdev_priv(dev);
2300 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
2301 struct sk_buff *skb = NULL;
2302 u16 count = (status & GMR_FS_LEN) >> 16;
2304 #ifdef SKY2_VLAN_TAG_USED
2305 /* Account for vlan tag */
2306 if (sky2->vlgrp && (status & GMR_FS_VLAN))
2310 if (unlikely(netif_msg_rx_status(sky2)))
2311 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
2312 dev->name, sky2->rx_next, status, length);
2314 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
2315 prefetch(sky2->rx_ring + sky2->rx_next);
2317 /* This chip has hardware problems that generates bogus status.
2318 * So do only marginal checking and expect higher level protocols
2319 * to handle crap frames.
2321 if (sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
2322 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0 &&
2326 if (status & GMR_FS_ANY_ERR)
2329 if (!(status & GMR_FS_RX_OK))
2332 /* if length reported by DMA does not match PHY, packet was truncated */
2333 if (length != count)
2337 if (length < copybreak)
2338 skb = receive_copy(sky2, re, length);
2340 skb = receive_new(sky2, re, length);
2342 sky2_rx_submit(sky2, re);
2347 /* Truncation of overlength packets
2348 causes PHY length to not match MAC length */
2349 ++dev->stats.rx_length_errors;
2350 if (netif_msg_rx_err(sky2) && net_ratelimit())
2351 pr_info(PFX "%s: rx length error: status %#x length %d\n",
2352 dev->name, status, length);
2356 ++dev->stats.rx_errors;
2357 if (status & GMR_FS_RX_FF_OV) {
2358 dev->stats.rx_over_errors++;
2362 if (netif_msg_rx_err(sky2) && net_ratelimit())
2363 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
2364 dev->name, status, length);
2366 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
2367 dev->stats.rx_length_errors++;
2368 if (status & GMR_FS_FRAGMENT)
2369 dev->stats.rx_frame_errors++;
2370 if (status & GMR_FS_CRC_ERR)
2371 dev->stats.rx_crc_errors++;
2376 /* Transmit complete */
2377 static inline void sky2_tx_done(struct net_device *dev, u16 last)
2379 struct sky2_port *sky2 = netdev_priv(dev);
2381 if (netif_running(dev))
2382 sky2_tx_complete(sky2, last);
2385 static inline void sky2_skb_rx(const struct sky2_port *sky2,
2386 u32 status, struct sk_buff *skb)
2388 #ifdef SKY2_VLAN_TAG_USED
2389 u16 vlan_tag = be16_to_cpu(sky2->rx_tag);
2390 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2391 if (skb->ip_summed == CHECKSUM_NONE)
2392 vlan_hwaccel_receive_skb(skb, sky2->vlgrp, vlan_tag);
2394 vlan_gro_receive(&sky2->hw->napi, sky2->vlgrp,
2399 if (skb->ip_summed == CHECKSUM_NONE)
2400 netif_receive_skb(skb);
2402 napi_gro_receive(&sky2->hw->napi, skb);
2405 static inline void sky2_rx_done(struct sky2_hw *hw, unsigned port,
2406 unsigned packets, unsigned bytes)
2409 struct net_device *dev = hw->dev[port];
2411 dev->stats.rx_packets += packets;
2412 dev->stats.rx_bytes += bytes;
2413 dev->last_rx = jiffies;
2414 sky2_rx_update(netdev_priv(dev), rxqaddr[port]);
2418 /* Process status response ring */
2419 static int sky2_status_intr(struct sky2_hw *hw, int to_do, u16 idx)
2422 unsigned int total_bytes[2] = { 0 };
2423 unsigned int total_packets[2] = { 0 };
2427 struct sky2_port *sky2;
2428 struct sky2_status_le *le = hw->st_le + hw->st_idx;
2430 struct net_device *dev;
2431 struct sk_buff *skb;
2434 u8 opcode = le->opcode;
2436 if (!(opcode & HW_OWNER))
2439 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
2441 port = le->css & CSS_LINK_BIT;
2442 dev = hw->dev[port];
2443 sky2 = netdev_priv(dev);
2444 length = le16_to_cpu(le->length);
2445 status = le32_to_cpu(le->status);
2448 switch (opcode & ~HW_OWNER) {
2450 total_packets[port]++;
2451 total_bytes[port] += length;
2452 skb = sky2_receive(dev, length, status);
2453 if (unlikely(!skb)) {
2454 dev->stats.rx_dropped++;
2458 /* This chip reports checksum status differently */
2459 if (hw->flags & SKY2_HW_NEW_LE) {
2460 if ((sky2->flags & SKY2_FLAG_RX_CHECKSUM) &&
2461 (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) &&
2462 (le->css & CSS_TCPUDPCSOK))
2463 skb->ip_summed = CHECKSUM_UNNECESSARY;
2465 skb->ip_summed = CHECKSUM_NONE;
2468 skb->protocol = eth_type_trans(skb, dev);
2470 sky2_skb_rx(sky2, status, skb);
2472 /* Stop after net poll weight */
2473 if (++work_done >= to_do)
2477 #ifdef SKY2_VLAN_TAG_USED
2479 sky2->rx_tag = length;
2483 sky2->rx_tag = length;
2487 if (!(sky2->flags & SKY2_FLAG_RX_CHECKSUM))
2490 /* If this happens then driver assuming wrong format */
2491 if (unlikely(hw->flags & SKY2_HW_NEW_LE)) {
2492 if (net_ratelimit())
2493 printk(KERN_NOTICE "%s: unexpected"
2494 " checksum status\n",
2499 /* Both checksum counters are programmed to start at
2500 * the same offset, so unless there is a problem they
2501 * should match. This failure is an early indication that
2502 * hardware receive checksumming won't work.
2504 if (likely(status >> 16 == (status & 0xffff))) {
2505 skb = sky2->rx_ring[sky2->rx_next].skb;
2506 skb->ip_summed = CHECKSUM_COMPLETE;
2507 skb->csum = le16_to_cpu(status);
2509 printk(KERN_NOTICE PFX "%s: hardware receive "
2510 "checksum problem (status = %#x)\n",
2512 sky2->flags &= ~SKY2_FLAG_RX_CHECKSUM;
2514 sky2_write32(sky2->hw,
2515 Q_ADDR(rxqaddr[port], Q_CSR),
2521 /* TX index reports status for both ports */
2522 sky2_tx_done(hw->dev[0], status & 0xfff);
2524 sky2_tx_done(hw->dev[1],
2525 ((status >> 24) & 0xff)
2526 | (u16)(length & 0xf) << 8);
2530 if (net_ratelimit())
2531 printk(KERN_WARNING PFX
2532 "unknown status opcode 0x%x\n", opcode);
2534 } while (hw->st_idx != idx);
2536 /* Fully processed status ring so clear irq */
2537 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2540 sky2_rx_done(hw, 0, total_packets[0], total_bytes[0]);
2541 sky2_rx_done(hw, 1, total_packets[1], total_bytes[1]);
2546 static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2548 struct net_device *dev = hw->dev[port];
2550 if (net_ratelimit())
2551 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2554 if (status & Y2_IS_PAR_RD1) {
2555 if (net_ratelimit())
2556 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2559 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2562 if (status & Y2_IS_PAR_WR1) {
2563 if (net_ratelimit())
2564 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2567 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2570 if (status & Y2_IS_PAR_MAC1) {
2571 if (net_ratelimit())
2572 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
2573 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2576 if (status & Y2_IS_PAR_RX1) {
2577 if (net_ratelimit())
2578 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
2579 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2582 if (status & Y2_IS_TCP_TXA1) {
2583 if (net_ratelimit())
2584 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2586 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2590 static void sky2_hw_intr(struct sky2_hw *hw)
2592 struct pci_dev *pdev = hw->pdev;
2593 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2594 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2598 if (status & Y2_IS_TIST_OV)
2599 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2601 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
2604 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2605 pci_err = sky2_pci_read16(hw, PCI_STATUS);
2606 if (net_ratelimit())
2607 dev_err(&pdev->dev, "PCI hardware error (0x%x)\n",
2610 sky2_pci_write16(hw, PCI_STATUS,
2611 pci_err | PCI_STATUS_ERROR_BITS);
2612 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2615 if (status & Y2_IS_PCI_EXP) {
2616 /* PCI-Express uncorrectable Error occurred */
2619 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2620 err = sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2621 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2623 if (net_ratelimit())
2624 dev_err(&pdev->dev, "PCI Express error (0x%x)\n", err);
2626 sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2627 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2630 if (status & Y2_HWE_L1_MASK)
2631 sky2_hw_error(hw, 0, status);
2633 if (status & Y2_HWE_L1_MASK)
2634 sky2_hw_error(hw, 1, status);
2637 static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2639 struct net_device *dev = hw->dev[port];
2640 struct sky2_port *sky2 = netdev_priv(dev);
2641 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2643 if (netif_msg_intr(sky2))
2644 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2647 if (status & GM_IS_RX_CO_OV)
2648 gma_read16(hw, port, GM_RX_IRQ_SRC);
2650 if (status & GM_IS_TX_CO_OV)
2651 gma_read16(hw, port, GM_TX_IRQ_SRC);
2653 if (status & GM_IS_RX_FF_OR) {
2654 ++dev->stats.rx_fifo_errors;
2655 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2658 if (status & GM_IS_TX_FF_UR) {
2659 ++dev->stats.tx_fifo_errors;
2660 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2664 /* This should never happen it is a bug. */
2665 static void sky2_le_error(struct sky2_hw *hw, unsigned port, u16 q)
2667 struct net_device *dev = hw->dev[port];
2668 u16 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
2670 dev_err(&hw->pdev->dev, PFX
2671 "%s: descriptor error q=%#x get=%u put=%u\n",
2672 dev->name, (unsigned) q, (unsigned) idx,
2673 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
2675 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
2678 static int sky2_rx_hung(struct net_device *dev)
2680 struct sky2_port *sky2 = netdev_priv(dev);
2681 struct sky2_hw *hw = sky2->hw;
2682 unsigned port = sky2->port;
2683 unsigned rxq = rxqaddr[port];
2684 u32 mac_rp = sky2_read32(hw, SK_REG(port, RX_GMF_RP));
2685 u8 mac_lev = sky2_read8(hw, SK_REG(port, RX_GMF_RLEV));
2686 u8 fifo_rp = sky2_read8(hw, Q_ADDR(rxq, Q_RP));
2687 u8 fifo_lev = sky2_read8(hw, Q_ADDR(rxq, Q_RL));
2689 /* If idle and MAC or PCI is stuck */
2690 if (sky2->check.last == dev->last_rx &&
2691 ((mac_rp == sky2->check.mac_rp &&
2692 mac_lev != 0 && mac_lev >= sky2->check.mac_lev) ||
2693 /* Check if the PCI RX hang */
2694 (fifo_rp == sky2->check.fifo_rp &&
2695 fifo_lev != 0 && fifo_lev >= sky2->check.fifo_lev))) {
2696 printk(KERN_DEBUG PFX "%s: hung mac %d:%d fifo %d (%d:%d)\n",
2697 dev->name, mac_lev, mac_rp, fifo_lev, fifo_rp,
2698 sky2_read8(hw, Q_ADDR(rxq, Q_WP)));
2701 sky2->check.last = dev->last_rx;
2702 sky2->check.mac_rp = mac_rp;
2703 sky2->check.mac_lev = mac_lev;
2704 sky2->check.fifo_rp = fifo_rp;
2705 sky2->check.fifo_lev = fifo_lev;
2710 static void sky2_watchdog(unsigned long arg)
2712 struct sky2_hw *hw = (struct sky2_hw *) arg;
2714 /* Check for lost IRQ once a second */
2715 if (sky2_read32(hw, B0_ISRC)) {
2716 napi_schedule(&hw->napi);
2720 for (i = 0; i < hw->ports; i++) {
2721 struct net_device *dev = hw->dev[i];
2722 if (!netif_running(dev))
2726 /* For chips with Rx FIFO, check if stuck */
2727 if ((hw->flags & SKY2_HW_RAM_BUFFER) &&
2728 sky2_rx_hung(dev)) {
2729 pr_info(PFX "%s: receiver hang detected\n",
2731 schedule_work(&hw->restart_work);
2740 mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ));
2743 /* Hardware/software error handling */
2744 static void sky2_err_intr(struct sky2_hw *hw, u32 status)
2746 if (net_ratelimit())
2747 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
2749 if (status & Y2_IS_HW_ERR)
2752 if (status & Y2_IS_IRQ_MAC1)
2753 sky2_mac_intr(hw, 0);
2755 if (status & Y2_IS_IRQ_MAC2)
2756 sky2_mac_intr(hw, 1);
2758 if (status & Y2_IS_CHK_RX1)
2759 sky2_le_error(hw, 0, Q_R1);
2761 if (status & Y2_IS_CHK_RX2)
2762 sky2_le_error(hw, 1, Q_R2);
2764 if (status & Y2_IS_CHK_TXA1)
2765 sky2_le_error(hw, 0, Q_XA1);
2767 if (status & Y2_IS_CHK_TXA2)
2768 sky2_le_error(hw, 1, Q_XA2);
2771 static int sky2_poll(struct napi_struct *napi, int work_limit)
2773 struct sky2_hw *hw = container_of(napi, struct sky2_hw, napi);
2774 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
2778 if (unlikely(status & Y2_IS_ERROR))
2779 sky2_err_intr(hw, status);
2781 if (status & Y2_IS_IRQ_PHY1)
2782 sky2_phy_intr(hw, 0);
2784 if (status & Y2_IS_IRQ_PHY2)
2785 sky2_phy_intr(hw, 1);
2787 while ((idx = sky2_read16(hw, STAT_PUT_IDX)) != hw->st_idx) {
2788 work_done += sky2_status_intr(hw, work_limit - work_done, idx);
2790 if (work_done >= work_limit)
2794 napi_complete(napi);
2795 sky2_read32(hw, B0_Y2_SP_LISR);
2801 static irqreturn_t sky2_intr(int irq, void *dev_id)
2803 struct sky2_hw *hw = dev_id;
2806 /* Reading this mask interrupts as side effect */
2807 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2808 if (status == 0 || status == ~0)
2811 prefetch(&hw->st_le[hw->st_idx]);
2813 napi_schedule(&hw->napi);
2818 #ifdef CONFIG_NET_POLL_CONTROLLER
2819 static void sky2_netpoll(struct net_device *dev)
2821 struct sky2_port *sky2 = netdev_priv(dev);
2823 napi_schedule(&sky2->hw->napi);
2827 /* Chip internal frequency for clock calculations */
2828 static u32 sky2_mhz(const struct sky2_hw *hw)
2830 switch (hw->chip_id) {
2831 case CHIP_ID_YUKON_EC:
2832 case CHIP_ID_YUKON_EC_U:
2833 case CHIP_ID_YUKON_EX:
2834 case CHIP_ID_YUKON_SUPR:
2835 case CHIP_ID_YUKON_UL_2:
2838 case CHIP_ID_YUKON_FE:
2841 case CHIP_ID_YUKON_FE_P:
2844 case CHIP_ID_YUKON_XL:
2852 static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
2854 return sky2_mhz(hw) * us;
2857 static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
2859 return clk / sky2_mhz(hw);
2863 static int __devinit sky2_init(struct sky2_hw *hw)
2867 /* Enable all clocks and check for bad PCI access */
2868 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
2870 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2872 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2873 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2875 switch(hw->chip_id) {
2876 case CHIP_ID_YUKON_XL:
2877 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_NEWER_PHY;
2880 case CHIP_ID_YUKON_EC_U:
2881 hw->flags = SKY2_HW_GIGABIT
2883 | SKY2_HW_ADV_POWER_CTL;
2886 case CHIP_ID_YUKON_EX:
2887 hw->flags = SKY2_HW_GIGABIT
2890 | SKY2_HW_ADV_POWER_CTL;
2892 /* New transmit checksum */
2893 if (hw->chip_rev != CHIP_REV_YU_EX_B0)
2894 hw->flags |= SKY2_HW_AUTO_TX_SUM;
2897 case CHIP_ID_YUKON_EC:
2898 /* This rev is really old, and requires untested workarounds */
2899 if (hw->chip_rev == CHIP_REV_YU_EC_A1) {
2900 dev_err(&hw->pdev->dev, "unsupported revision Yukon-EC rev A1\n");
2903 hw->flags = SKY2_HW_GIGABIT;
2906 case CHIP_ID_YUKON_FE:
2909 case CHIP_ID_YUKON_FE_P:
2910 hw->flags = SKY2_HW_NEWER_PHY
2912 | SKY2_HW_AUTO_TX_SUM
2913 | SKY2_HW_ADV_POWER_CTL;
2916 case CHIP_ID_YUKON_SUPR:
2917 hw->flags = SKY2_HW_GIGABIT
2920 | SKY2_HW_AUTO_TX_SUM
2921 | SKY2_HW_ADV_POWER_CTL;
2924 case CHIP_ID_YUKON_UL_2:
2925 hw->flags = SKY2_HW_GIGABIT
2926 | SKY2_HW_ADV_POWER_CTL;
2930 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
2935 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
2936 if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P')
2937 hw->flags |= SKY2_HW_FIBRE_PHY;
2940 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2941 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2942 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2949 static void sky2_reset(struct sky2_hw *hw)
2951 struct pci_dev *pdev = hw->pdev;
2954 u32 hwe_mask = Y2_HWE_ALL_MASK;
2957 if (hw->chip_id == CHIP_ID_YUKON_EX) {
2958 status = sky2_read16(hw, HCU_CCSR);
2959 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
2960 HCU_CCSR_UC_STATE_MSK);
2961 sky2_write16(hw, HCU_CCSR, status);
2963 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2964 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
2967 sky2_write8(hw, B0_CTST, CS_RST_SET);
2968 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2970 /* allow writes to PCI config */
2971 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2973 /* clear PCI errors, if any */
2974 status = sky2_pci_read16(hw, PCI_STATUS);
2975 status |= PCI_STATUS_ERROR_BITS;
2976 sky2_pci_write16(hw, PCI_STATUS, status);
2978 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2980 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
2982 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2985 /* If error bit is stuck on ignore it */
2986 if (sky2_read32(hw, B0_HWE_ISRC) & Y2_IS_PCI_EXP)
2987 dev_info(&pdev->dev, "ignoring stuck error report bit\n");
2989 hwe_mask |= Y2_IS_PCI_EXP;
2993 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2995 for (i = 0; i < hw->ports; i++) {
2996 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2997 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2999 if (hw->chip_id == CHIP_ID_YUKON_EX ||
3000 hw->chip_id == CHIP_ID_YUKON_SUPR)
3001 sky2_write16(hw, SK_REG(i, GMAC_CTRL),
3002 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON
3006 /* Clear I2C IRQ noise */
3007 sky2_write32(hw, B2_I2C_IRQ, 1);
3009 /* turn off hardware timer (unused) */
3010 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
3011 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
3013 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
3015 /* Turn off descriptor polling */
3016 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
3018 /* Turn off receive timestamp */
3019 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
3020 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
3022 /* enable the Tx Arbiters */
3023 for (i = 0; i < hw->ports; i++)
3024 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
3026 /* Initialize ram interface */
3027 for (i = 0; i < hw->ports; i++) {
3028 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
3030 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
3031 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
3032 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
3033 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
3034 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
3035 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
3036 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
3037 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
3038 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
3039 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
3040 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
3041 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
3044 sky2_write32(hw, B0_HWE_IMSK, hwe_mask);
3046 for (i = 0; i < hw->ports; i++)
3047 sky2_gmac_reset(hw, i);
3049 memset(hw->st_le, 0, STATUS_LE_BYTES);
3052 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
3053 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
3055 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
3056 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
3058 /* Set the list last index */
3059 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
3061 sky2_write16(hw, STAT_TX_IDX_TH, 10);
3062 sky2_write8(hw, STAT_FIFO_WM, 16);
3064 /* set Status-FIFO ISR watermark */
3065 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
3066 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
3068 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
3070 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
3071 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
3072 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
3074 /* enable status unit */
3075 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
3077 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3078 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3079 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3082 /* Take device down (offline).
3083 * Equivalent to doing dev_stop() but this does not
3084 * inform upper layers of the transistion.
3086 static void sky2_detach(struct net_device *dev)
3088 if (netif_running(dev)) {
3089 netif_device_detach(dev); /* stop txq */
3094 /* Bring device back after doing sky2_detach */
3095 static int sky2_reattach(struct net_device *dev)
3099 if (netif_running(dev)) {
3102 printk(KERN_INFO PFX "%s: could not restart %d\n",
3106 netif_device_attach(dev);
3107 sky2_set_multicast(dev);
3114 static void sky2_restart(struct work_struct *work)
3116 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
3120 for (i = 0; i < hw->ports; i++)
3121 sky2_detach(hw->dev[i]);
3123 napi_disable(&hw->napi);
3124 sky2_write32(hw, B0_IMSK, 0);
3126 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
3127 napi_enable(&hw->napi);
3129 for (i = 0; i < hw->ports; i++)
3130 sky2_reattach(hw->dev[i]);
3135 static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
3137 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
3140 static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3142 const struct sky2_port *sky2 = netdev_priv(dev);
3144 wol->supported = sky2_wol_supported(sky2->hw);
3145 wol->wolopts = sky2->wol;
3148 static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3150 struct sky2_port *sky2 = netdev_priv(dev);
3151 struct sky2_hw *hw = sky2->hw;
3153 if ((wol->wolopts & ~sky2_wol_supported(sky2->hw))
3154 || !device_can_wakeup(&hw->pdev->dev))
3157 sky2->wol = wol->wolopts;
3159 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3160 hw->chip_id == CHIP_ID_YUKON_EX ||
3161 hw->chip_id == CHIP_ID_YUKON_FE_P)
3162 sky2_write32(hw, B0_CTST, sky2->wol
3163 ? Y2_HW_WOL_ON : Y2_HW_WOL_OFF);
3165 device_set_wakeup_enable(&hw->pdev->dev, sky2->wol);
3167 if (!netif_running(dev))
3168 sky2_wol_init(sky2);
3172 static u32 sky2_supported_modes(const struct sky2_hw *hw)
3174 if (sky2_is_copper(hw)) {
3175 u32 modes = SUPPORTED_10baseT_Half
3176 | SUPPORTED_10baseT_Full
3177 | SUPPORTED_100baseT_Half
3178 | SUPPORTED_100baseT_Full
3179 | SUPPORTED_Autoneg | SUPPORTED_TP;
3181 if (hw->flags & SKY2_HW_GIGABIT)
3182 modes |= SUPPORTED_1000baseT_Half
3183 | SUPPORTED_1000baseT_Full;
3186 return SUPPORTED_1000baseT_Half
3187 | SUPPORTED_1000baseT_Full
3192 static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3194 struct sky2_port *sky2 = netdev_priv(dev);
3195 struct sky2_hw *hw = sky2->hw;
3197 ecmd->transceiver = XCVR_INTERNAL;
3198 ecmd->supported = sky2_supported_modes(hw);
3199 ecmd->phy_address = PHY_ADDR_MARV;
3200 if (sky2_is_copper(hw)) {
3201 ecmd->port = PORT_TP;
3202 ecmd->speed = sky2->speed;
3204 ecmd->speed = SPEED_1000;
3205 ecmd->port = PORT_FIBRE;
3208 ecmd->advertising = sky2->advertising;
3209 ecmd->autoneg = (sky2->flags & SKY2_FLAG_AUTO_SPEED)
3210 ? AUTONEG_ENABLE : AUTONEG_DISABLE;
3211 ecmd->duplex = sky2->duplex;
3215 static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3217 struct sky2_port *sky2 = netdev_priv(dev);
3218 const struct sky2_hw *hw = sky2->hw;
3219 u32 supported = sky2_supported_modes(hw);
3221 if (ecmd->autoneg == AUTONEG_ENABLE) {
3222 sky2->flags |= SKY2_FLAG_AUTO_SPEED;
3223 ecmd->advertising = supported;
3229 switch (ecmd->speed) {
3231 if (ecmd->duplex == DUPLEX_FULL)
3232 setting = SUPPORTED_1000baseT_Full;
3233 else if (ecmd->duplex == DUPLEX_HALF)
3234 setting = SUPPORTED_1000baseT_Half;
3239 if (ecmd->duplex == DUPLEX_FULL)
3240 setting = SUPPORTED_100baseT_Full;
3241 else if (ecmd->duplex == DUPLEX_HALF)
3242 setting = SUPPORTED_100baseT_Half;
3248 if (ecmd->duplex == DUPLEX_FULL)
3249 setting = SUPPORTED_10baseT_Full;
3250 else if (ecmd->duplex == DUPLEX_HALF)
3251 setting = SUPPORTED_10baseT_Half;
3259 if ((setting & supported) == 0)
3262 sky2->speed = ecmd->speed;
3263 sky2->duplex = ecmd->duplex;
3264 sky2->flags &= ~SKY2_FLAG_AUTO_SPEED;
3267 sky2->advertising = ecmd->advertising;
3269 if (netif_running(dev)) {
3270 sky2_phy_reinit(sky2);
3271 sky2_set_multicast(dev);
3277 static void sky2_get_drvinfo(struct net_device *dev,
3278 struct ethtool_drvinfo *info)
3280 struct sky2_port *sky2 = netdev_priv(dev);
3282 strcpy(info->driver, DRV_NAME);
3283 strcpy(info->version, DRV_VERSION);
3284 strcpy(info->fw_version, "N/A");
3285 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
3288 static const struct sky2_stat {
3289 char name[ETH_GSTRING_LEN];
3292 { "tx_bytes", GM_TXO_OK_HI },
3293 { "rx_bytes", GM_RXO_OK_HI },
3294 { "tx_broadcast", GM_TXF_BC_OK },
3295 { "rx_broadcast", GM_RXF_BC_OK },
3296 { "tx_multicast", GM_TXF_MC_OK },
3297 { "rx_multicast", GM_RXF_MC_OK },
3298 { "tx_unicast", GM_TXF_UC_OK },
3299 { "rx_unicast", GM_RXF_UC_OK },
3300 { "tx_mac_pause", GM_TXF_MPAUSE },
3301 { "rx_mac_pause", GM_RXF_MPAUSE },
3302 { "collisions", GM_TXF_COL },
3303 { "late_collision",GM_TXF_LAT_COL },
3304 { "aborted", GM_TXF_ABO_COL },
3305 { "single_collisions", GM_TXF_SNG_COL },
3306 { "multi_collisions", GM_TXF_MUL_COL },
3308 { "rx_short", GM_RXF_SHT },
3309 { "rx_runt", GM_RXE_FRAG },
3310 { "rx_64_byte_packets", GM_RXF_64B },
3311 { "rx_65_to_127_byte_packets", GM_RXF_127B },
3312 { "rx_128_to_255_byte_packets", GM_RXF_255B },
3313 { "rx_256_to_511_byte_packets", GM_RXF_511B },
3314 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
3315 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
3316 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
3317 { "rx_too_long", GM_RXF_LNG_ERR },
3318 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
3319 { "rx_jabber", GM_RXF_JAB_PKT },
3320 { "rx_fcs_error", GM_RXF_FCS_ERR },
3322 { "tx_64_byte_packets", GM_TXF_64B },
3323 { "tx_65_to_127_byte_packets", GM_TXF_127B },
3324 { "tx_128_to_255_byte_packets", GM_TXF_255B },
3325 { "tx_256_to_511_byte_packets", GM_TXF_511B },
3326 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
3327 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
3328 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
3329 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
3332 static u32 sky2_get_rx_csum(struct net_device *dev)
3334 struct sky2_port *sky2 = netdev_priv(dev);
3336 return !!(sky2->flags & SKY2_FLAG_RX_CHECKSUM);
3339 static int sky2_set_rx_csum(struct net_device *dev, u32 data)
3341 struct sky2_port *sky2 = netdev_priv(dev);
3344 sky2->flags |= SKY2_FLAG_RX_CHECKSUM;
3346 sky2->flags &= ~SKY2_FLAG_RX_CHECKSUM;
3348 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
3349 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
3354 static u32 sky2_get_msglevel(struct net_device *netdev)
3356 struct sky2_port *sky2 = netdev_priv(netdev);
3357 return sky2->msg_enable;
3360 static int sky2_nway_reset(struct net_device *dev)
3362 struct sky2_port *sky2 = netdev_priv(dev);
3364 if (!netif_running(dev) || !(sky2->flags & SKY2_FLAG_AUTO_SPEED))
3367 sky2_phy_reinit(sky2);
3368 sky2_set_multicast(dev);
3373 static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
3375 struct sky2_hw *hw = sky2->hw;
3376 unsigned port = sky2->port;
3379 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
3380 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
3381 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
3382 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
3384 for (i = 2; i < count; i++)
3385 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
3388 static void sky2_set_msglevel(struct net_device *netdev, u32 value)
3390 struct sky2_port *sky2 = netdev_priv(netdev);
3391 sky2->msg_enable = value;
3394 static int sky2_get_sset_count(struct net_device *dev, int sset)
3398 return ARRAY_SIZE(sky2_stats);
3404 static void sky2_get_ethtool_stats(struct net_device *dev,
3405 struct ethtool_stats *stats, u64 * data)
3407 struct sky2_port *sky2 = netdev_priv(dev);
3409 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
3412 static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
3416 switch (stringset) {
3418 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
3419 memcpy(data + i * ETH_GSTRING_LEN,
3420 sky2_stats[i].name, ETH_GSTRING_LEN);
3425 static int sky2_set_mac_address(struct net_device *dev, void *p)
3427 struct sky2_port *sky2 = netdev_priv(dev);
3428 struct sky2_hw *hw = sky2->hw;
3429 unsigned port = sky2->port;
3430 const struct sockaddr *addr = p;
3432 if (!is_valid_ether_addr(addr->sa_data))
3433 return -EADDRNOTAVAIL;
3435 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
3436 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
3437 dev->dev_addr, ETH_ALEN);
3438 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
3439 dev->dev_addr, ETH_ALEN);
3441 /* virtual address for data */
3442 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3444 /* physical address: used for pause frames */
3445 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
3450 static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
3454 bit = ether_crc(ETH_ALEN, addr) & 63;
3455 filter[bit >> 3] |= 1 << (bit & 7);
3458 static void sky2_set_multicast(struct net_device *dev)
3460 struct sky2_port *sky2 = netdev_priv(dev);
3461 struct sky2_hw *hw = sky2->hw;
3462 unsigned port = sky2->port;
3463 struct dev_mc_list *list = dev->mc_list;
3467 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
3469 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
3470 memset(filter, 0, sizeof(filter));
3472 reg = gma_read16(hw, port, GM_RX_CTRL);
3473 reg |= GM_RXCR_UCF_ENA;
3475 if (dev->flags & IFF_PROMISC) /* promiscuous */
3476 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
3477 else if (dev->flags & IFF_ALLMULTI)
3478 memset(filter, 0xff, sizeof(filter));
3479 else if (dev->mc_count == 0 && !rx_pause)
3480 reg &= ~GM_RXCR_MCF_ENA;
3483 reg |= GM_RXCR_MCF_ENA;
3486 sky2_add_filter(filter, pause_mc_addr);
3488 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
3489 sky2_add_filter(filter, list->dmi_addr);
3492 gma_write16(hw, port, GM_MC_ADDR_H1,
3493 (u16) filter[0] | ((u16) filter[1] << 8));
3494 gma_write16(hw, port, GM_MC_ADDR_H2,
3495 (u16) filter[2] | ((u16) filter[3] << 8));
3496 gma_write16(hw, port, GM_MC_ADDR_H3,
3497 (u16) filter[4] | ((u16) filter[5] << 8));
3498 gma_write16(hw, port, GM_MC_ADDR_H4,
3499 (u16) filter[6] | ((u16) filter[7] << 8));
3501 gma_write16(hw, port, GM_RX_CTRL, reg);
3504 /* Can have one global because blinking is controlled by
3505 * ethtool and that is always under RTNL mutex
3507 static void sky2_led(struct sky2_port *sky2, enum led_mode mode)
3509 struct sky2_hw *hw = sky2->hw;
3510 unsigned port = sky2->port;
3512 spin_lock_bh(&sky2->phy_lock);
3513 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3514 hw->chip_id == CHIP_ID_YUKON_EX ||
3515 hw->chip_id == CHIP_ID_YUKON_SUPR) {
3517 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3518 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3522 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3523 PHY_M_LEDC_LOS_CTRL(8) |
3524 PHY_M_LEDC_INIT_CTRL(8) |
3525 PHY_M_LEDC_STA1_CTRL(8) |
3526 PHY_M_LEDC_STA0_CTRL(8));
3529 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3530 PHY_M_LEDC_LOS_CTRL(9) |
3531 PHY_M_LEDC_INIT_CTRL(9) |
3532 PHY_M_LEDC_STA1_CTRL(9) |
3533 PHY_M_LEDC_STA0_CTRL(9));
3536 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3537 PHY_M_LEDC_LOS_CTRL(0xa) |
3538 PHY_M_LEDC_INIT_CTRL(0xa) |
3539 PHY_M_LEDC_STA1_CTRL(0xa) |
3540 PHY_M_LEDC_STA0_CTRL(0xa));
3543 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3544 PHY_M_LEDC_LOS_CTRL(1) |
3545 PHY_M_LEDC_INIT_CTRL(8) |
3546 PHY_M_LEDC_STA1_CTRL(7) |
3547 PHY_M_LEDC_STA0_CTRL(7));
3550 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3552 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
3553 PHY_M_LED_MO_DUP(mode) |
3554 PHY_M_LED_MO_10(mode) |
3555 PHY_M_LED_MO_100(mode) |
3556 PHY_M_LED_MO_1000(mode) |
3557 PHY_M_LED_MO_RX(mode) |
3558 PHY_M_LED_MO_TX(mode));
3560 spin_unlock_bh(&sky2->phy_lock);
3563 /* blink LED's for finding board */
3564 static int sky2_phys_id(struct net_device *dev, u32 data)
3566 struct sky2_port *sky2 = netdev_priv(dev);
3572 for (i = 0; i < data; i++) {
3573 sky2_led(sky2, MO_LED_ON);
3574 if (msleep_interruptible(500))
3576 sky2_led(sky2, MO_LED_OFF);
3577 if (msleep_interruptible(500))
3580 sky2_led(sky2, MO_LED_NORM);
3585 static void sky2_get_pauseparam(struct net_device *dev,
3586 struct ethtool_pauseparam *ecmd)
3588 struct sky2_port *sky2 = netdev_priv(dev);
3590 switch (sky2->flow_mode) {
3592 ecmd->tx_pause = ecmd->rx_pause = 0;
3595 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3598 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3601 ecmd->tx_pause = ecmd->rx_pause = 1;
3604 ecmd->autoneg = (sky2->flags & SKY2_FLAG_AUTO_PAUSE)
3605 ? AUTONEG_ENABLE : AUTONEG_DISABLE;
3608 static int sky2_set_pauseparam(struct net_device *dev,
3609 struct ethtool_pauseparam *ecmd)
3611 struct sky2_port *sky2 = netdev_priv(dev);
3613 if (ecmd->autoneg == AUTONEG_ENABLE)
3614 sky2->flags |= SKY2_FLAG_AUTO_PAUSE;
3616 sky2->flags &= ~SKY2_FLAG_AUTO_PAUSE;
3618 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
3620 if (netif_running(dev))
3621 sky2_phy_reinit(sky2);
3626 static int sky2_get_coalesce(struct net_device *dev,
3627 struct ethtool_coalesce *ecmd)
3629 struct sky2_port *sky2 = netdev_priv(dev);
3630 struct sky2_hw *hw = sky2->hw;
3632 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3633 ecmd->tx_coalesce_usecs = 0;
3635 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3636 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3638 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3640 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3641 ecmd->rx_coalesce_usecs = 0;
3643 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3644 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3646 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3648 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3649 ecmd->rx_coalesce_usecs_irq = 0;
3651 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3652 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3655 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3660 /* Note: this affect both ports */
3661 static int sky2_set_coalesce(struct net_device *dev,
3662 struct ethtool_coalesce *ecmd)
3664 struct sky2_port *sky2 = netdev_priv(dev);
3665 struct sky2_hw *hw = sky2->hw;
3666 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
3668 if (ecmd->tx_coalesce_usecs > tmax ||
3669 ecmd->rx_coalesce_usecs > tmax ||
3670 ecmd->rx_coalesce_usecs_irq > tmax)
3673 if (ecmd->tx_max_coalesced_frames >= sky2->tx_ring_size-1)
3675 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
3677 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
3680 if (ecmd->tx_coalesce_usecs == 0)
3681 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3683 sky2_write32(hw, STAT_TX_TIMER_INI,
3684 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3685 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3687 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3689 if (ecmd->rx_coalesce_usecs == 0)
3690 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3692 sky2_write32(hw, STAT_LEV_TIMER_INI,
3693 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3694 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3696 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3698 if (ecmd->rx_coalesce_usecs_irq == 0)
3699 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3701 sky2_write32(hw, STAT_ISR_TIMER_INI,
3702 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3703 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3705 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3709 static void sky2_get_ringparam(struct net_device *dev,
3710 struct ethtool_ringparam *ering)
3712 struct sky2_port *sky2 = netdev_priv(dev);
3714 ering->rx_max_pending = RX_MAX_PENDING;
3715 ering->rx_mini_max_pending = 0;
3716 ering->rx_jumbo_max_pending = 0;
3717 ering->tx_max_pending = TX_MAX_PENDING;
3719 ering->rx_pending = sky2->rx_pending;
3720 ering->rx_mini_pending = 0;
3721 ering->rx_jumbo_pending = 0;
3722 ering->tx_pending = sky2->tx_pending;
3725 static int sky2_set_ringparam(struct net_device *dev,
3726 struct ethtool_ringparam *ering)
3728 struct sky2_port *sky2 = netdev_priv(dev);
3730 if (ering->rx_pending > RX_MAX_PENDING ||
3731 ering->rx_pending < 8 ||
3732 ering->tx_pending < TX_MIN_PENDING ||
3733 ering->tx_pending > TX_MAX_PENDING)
3738 sky2->rx_pending = ering->rx_pending;
3739 sky2->tx_pending = ering->tx_pending;
3740 sky2->tx_ring_size = roundup_pow_of_two(sky2->tx_pending+1);
3742 return sky2_reattach(dev);
3745 static int sky2_get_regs_len(struct net_device *dev)
3751 * Returns copy of control register region
3752 * Note: ethtool_get_regs always provides full size (16k) buffer
3754 static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3757 const struct sky2_port *sky2 = netdev_priv(dev);
3758 const void __iomem *io = sky2->hw->regs;
3763 for (b = 0; b < 128; b++) {
3764 /* This complicated switch statement is to make sure and
3765 * only access regions that are unreserved.
3766 * Some blocks are only valid on dual port cards.
3767 * and block 3 has some special diagnostic registers that
3772 /* skip diagnostic ram region */
3773 memcpy_fromio(p + 0x10, io + 0x10, 128 - 0x10);
3776 /* dual port cards only */
3777 case 5: /* Tx Arbiter 2 */
3779 case 14 ... 15: /* TX2 */
3780 case 17: case 19: /* Ram Buffer 2 */
3781 case 22 ... 23: /* Tx Ram Buffer 2 */
3782 case 25: /* Rx MAC Fifo 1 */
3783 case 27: /* Tx MAC Fifo 2 */
3784 case 31: /* GPHY 2 */
3785 case 40 ... 47: /* Pattern Ram 2 */
3786 case 52: case 54: /* TCP Segmentation 2 */
3787 case 112 ... 116: /* GMAC 2 */
3788 if (sky2->hw->ports == 1)
3791 case 0: /* Control */
3792 case 2: /* Mac address */
3793 case 4: /* Tx Arbiter 1 */
3794 case 7: /* PCI express reg */
3796 case 12 ... 13: /* TX1 */
3797 case 16: case 18:/* Rx Ram Buffer 1 */
3798 case 20 ... 21: /* Tx Ram Buffer 1 */
3799 case 24: /* Rx MAC Fifo 1 */
3800 case 26: /* Tx MAC Fifo 1 */
3801 case 28 ... 29: /* Descriptor and status unit */
3802 case 30: /* GPHY 1*/
3803 case 32 ... 39: /* Pattern Ram 1 */
3804 case 48: case 50: /* TCP Segmentation 1 */
3805 case 56 ... 60: /* PCI space */
3806 case 80 ... 84: /* GMAC 1 */
3807 memcpy_fromio(p, io, 128);
3819 /* In order to do Jumbo packets on these chips, need to turn off the
3820 * transmit store/forward. Therefore checksum offload won't work.
3822 static int no_tx_offload(struct net_device *dev)
3824 const struct sky2_port *sky2 = netdev_priv(dev);
3825 const struct sky2_hw *hw = sky2->hw;
3827 return dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U;
3830 static int sky2_set_tx_csum(struct net_device *dev, u32 data)
3832 if (data && no_tx_offload(dev))
3835 return ethtool_op_set_tx_csum(dev, data);
3839 static int sky2_set_tso(struct net_device *dev, u32 data)
3841 if (data && no_tx_offload(dev))
3844 return ethtool_op_set_tso(dev, data);
3847 static int sky2_get_eeprom_len(struct net_device *dev)
3849 struct sky2_port *sky2 = netdev_priv(dev);
3850 struct sky2_hw *hw = sky2->hw;
3853 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
3854 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
3857 static int sky2_vpd_wait(const struct sky2_hw *hw, int cap, u16 busy)
3859 unsigned long start = jiffies;
3861 while ( (sky2_pci_read16(hw, cap + PCI_VPD_ADDR) & PCI_VPD_ADDR_F) == busy) {
3862 /* Can take up to 10.6 ms for write */
3863 if (time_after(jiffies, start + HZ/4)) {
3864 dev_err(&hw->pdev->dev, PFX "VPD cycle timed out");
3873 static int sky2_vpd_read(struct sky2_hw *hw, int cap, void *data,
3874 u16 offset, size_t length)
3878 while (length > 0) {
3881 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset);
3882 rc = sky2_vpd_wait(hw, cap, 0);
3886 val = sky2_pci_read32(hw, cap + PCI_VPD_DATA);
3888 memcpy(data, &val, min(sizeof(val), length));
3889 offset += sizeof(u32);
3890 data += sizeof(u32);
3891 length -= sizeof(u32);
3897 static int sky2_vpd_write(struct sky2_hw *hw, int cap, const void *data,
3898 u16 offset, unsigned int length)
3903 for (i = 0; i < length; i += sizeof(u32)) {
3904 u32 val = *(u32 *)(data + i);
3906 sky2_pci_write32(hw, cap + PCI_VPD_DATA, val);
3907 sky2_pci_write32(hw, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F);
3909 rc = sky2_vpd_wait(hw, cap, PCI_VPD_ADDR_F);
3916 static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3919 struct sky2_port *sky2 = netdev_priv(dev);
3920 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
3925 eeprom->magic = SKY2_EEPROM_MAGIC;
3927 return sky2_vpd_read(sky2->hw, cap, data, eeprom->offset, eeprom->len);
3930 static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3933 struct sky2_port *sky2 = netdev_priv(dev);
3934 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
3939 if (eeprom->magic != SKY2_EEPROM_MAGIC)
3942 /* Partial writes not supported */
3943 if ((eeprom->offset & 3) || (eeprom->len & 3))
3946 return sky2_vpd_write(sky2->hw, cap, data, eeprom->offset, eeprom->len);
3950 static const struct ethtool_ops sky2_ethtool_ops = {
3951 .get_settings = sky2_get_settings,
3952 .set_settings = sky2_set_settings,
3953 .get_drvinfo = sky2_get_drvinfo,
3954 .get_wol = sky2_get_wol,
3955 .set_wol = sky2_set_wol,
3956 .get_msglevel = sky2_get_msglevel,
3957 .set_msglevel = sky2_set_msglevel,
3958 .nway_reset = sky2_nway_reset,
3959 .get_regs_len = sky2_get_regs_len,
3960 .get_regs = sky2_get_regs,
3961 .get_link = ethtool_op_get_link,
3962 .get_eeprom_len = sky2_get_eeprom_len,
3963 .get_eeprom = sky2_get_eeprom,
3964 .set_eeprom = sky2_set_eeprom,
3965 .set_sg = ethtool_op_set_sg,
3966 .set_tx_csum = sky2_set_tx_csum,
3967 .set_tso = sky2_set_tso,
3968 .get_rx_csum = sky2_get_rx_csum,
3969 .set_rx_csum = sky2_set_rx_csum,
3970 .get_strings = sky2_get_strings,
3971 .get_coalesce = sky2_get_coalesce,
3972 .set_coalesce = sky2_set_coalesce,
3973 .get_ringparam = sky2_get_ringparam,
3974 .set_ringparam = sky2_set_ringparam,
3975 .get_pauseparam = sky2_get_pauseparam,
3976 .set_pauseparam = sky2_set_pauseparam,
3977 .phys_id = sky2_phys_id,
3978 .get_sset_count = sky2_get_sset_count,
3979 .get_ethtool_stats = sky2_get_ethtool_stats,
3982 #ifdef CONFIG_SKY2_DEBUG
3984 static struct dentry *sky2_debug;
3988 * Read and parse the first part of Vital Product Data
3990 #define VPD_SIZE 128
3991 #define VPD_MAGIC 0x82
3993 static const struct vpd_tag {
3997 { "PN", "Part Number" },
3998 { "EC", "Engineering Level" },
3999 { "MN", "Manufacturer" },
4000 { "SN", "Serial Number" },
4001 { "YA", "Asset Tag" },
4002 { "VL", "First Error Log Message" },
4003 { "VF", "Second Error Log Message" },
4004 { "VB", "Boot Agent ROM Configuration" },
4005 { "VE", "EFI UNDI Configuration" },
4008 static void sky2_show_vpd(struct seq_file *seq, struct sky2_hw *hw)
4016 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
4017 vpd_size = 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
4019 seq_printf(seq, "%s Product Data\n", pci_name(hw->pdev));
4020 buf = kmalloc(vpd_size, GFP_KERNEL);
4022 seq_puts(seq, "no memory!\n");
4026 if (pci_read_vpd(hw->pdev, 0, vpd_size, buf) < 0) {
4027 seq_puts(seq, "VPD read failed\n");
4031 if (buf[0] != VPD_MAGIC) {
4032 seq_printf(seq, "VPD tag mismatch: %#x\n", buf[0]);
4036 if (len == 0 || len > vpd_size - 4) {
4037 seq_printf(seq, "Invalid id length: %d\n", len);
4041 seq_printf(seq, "%.*s\n", len, buf + 3);
4044 while (offs < vpd_size - 4) {
4047 if (!memcmp("RW", buf + offs, 2)) /* end marker */
4049 len = buf[offs + 2];
4050 if (offs + len + 3 >= vpd_size)
4053 for (i = 0; i < ARRAY_SIZE(vpd_tags); i++) {
4054 if (!memcmp(vpd_tags[i].tag, buf + offs, 2)) {
4055 seq_printf(seq, " %s: %.*s\n",
4056 vpd_tags[i].label, len, buf + offs + 3);
4066 static int sky2_debug_show(struct seq_file *seq, void *v)
4068 struct net_device *dev = seq->private;
4069 const struct sky2_port *sky2 = netdev_priv(dev);
4070 struct sky2_hw *hw = sky2->hw;
4071 unsigned port = sky2->port;
4075 sky2_show_vpd(seq, hw);
4077 seq_printf(seq, "\nIRQ src=%x mask=%x control=%x\n",
4078 sky2_read32(hw, B0_ISRC),
4079 sky2_read32(hw, B0_IMSK),
4080 sky2_read32(hw, B0_Y2_SP_ICR));
4082 if (!netif_running(dev)) {
4083 seq_printf(seq, "network not running\n");
4087 napi_disable(&hw->napi);
4088 last = sky2_read16(hw, STAT_PUT_IDX);
4090 if (hw->st_idx == last)
4091 seq_puts(seq, "Status ring (empty)\n");
4093 seq_puts(seq, "Status ring\n");
4094 for (idx = hw->st_idx; idx != last && idx < STATUS_RING_SIZE;
4095 idx = RING_NEXT(idx, STATUS_RING_SIZE)) {
4096 const struct sky2_status_le *le = hw->st_le + idx;
4097 seq_printf(seq, "[%d] %#x %d %#x\n",
4098 idx, le->opcode, le->length, le->status);
4100 seq_puts(seq, "\n");
4103 seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n",
4104 sky2->tx_cons, sky2->tx_prod,
4105 sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
4106 sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE)));
4108 /* Dump contents of tx ring */
4110 for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < sky2->tx_ring_size;
4111 idx = RING_NEXT(idx, sky2->tx_ring_size)) {
4112 const struct sky2_tx_le *le = sky2->tx_le + idx;
4113 u32 a = le32_to_cpu(le->addr);
4116 seq_printf(seq, "%u:", idx);
4119 switch(le->opcode & ~HW_OWNER) {
4121 seq_printf(seq, " %#x:", a);
4124 seq_printf(seq, " mtu=%d", a);
4127 seq_printf(seq, " vlan=%d", be16_to_cpu(le->length));
4130 seq_printf(seq, " csum=%#x", a);
4133 seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length));
4136 seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length));
4139 seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length));
4142 seq_printf(seq, " op=%#x,%#x(%d)", le->opcode,
4143 a, le16_to_cpu(le->length));
4146 if (le->ctrl & EOP) {
4147 seq_putc(seq, '\n');
4152 seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n",
4153 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)),
4154 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)),
4155 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX)));
4157 sky2_read32(hw, B0_Y2_SP_LISR);
4158 napi_enable(&hw->napi);
4162 static int sky2_debug_open(struct inode *inode, struct file *file)
4164 return single_open(file, sky2_debug_show, inode->i_private);
4167 static const struct file_operations sky2_debug_fops = {
4168 .owner = THIS_MODULE,
4169 .open = sky2_debug_open,
4171 .llseek = seq_lseek,
4172 .release = single_release,
4176 * Use network device events to create/remove/rename
4177 * debugfs file entries
4179 static int sky2_device_event(struct notifier_block *unused,
4180 unsigned long event, void *ptr)
4182 struct net_device *dev = ptr;
4183 struct sky2_port *sky2 = netdev_priv(dev);
4185 if (dev->netdev_ops->ndo_open != sky2_up || !sky2_debug)
4189 case NETDEV_CHANGENAME:
4190 if (sky2->debugfs) {
4191 sky2->debugfs = debugfs_rename(sky2_debug, sky2->debugfs,
4192 sky2_debug, dev->name);
4196 case NETDEV_GOING_DOWN:
4197 if (sky2->debugfs) {
4198 printk(KERN_DEBUG PFX "%s: remove debugfs\n",
4200 debugfs_remove(sky2->debugfs);
4201 sky2->debugfs = NULL;
4206 sky2->debugfs = debugfs_create_file(dev->name, S_IRUGO,
4209 if (IS_ERR(sky2->debugfs))
4210 sky2->debugfs = NULL;
4216 static struct notifier_block sky2_notifier = {
4217 .notifier_call = sky2_device_event,
4221 static __init void sky2_debug_init(void)
4225 ent = debugfs_create_dir("sky2", NULL);
4226 if (!ent || IS_ERR(ent))
4230 register_netdevice_notifier(&sky2_notifier);
4233 static __exit void sky2_debug_cleanup(void)
4236 unregister_netdevice_notifier(&sky2_notifier);
4237 debugfs_remove(sky2_debug);
4243 #define sky2_debug_init()
4244 #define sky2_debug_cleanup()
4247 /* Two copies of network device operations to handle special case of
4248 not allowing netpoll on second port */
4249 static const struct net_device_ops sky2_netdev_ops[2] = {
4251 .ndo_open = sky2_up,
4252 .ndo_stop = sky2_down,
4253 .ndo_start_xmit = sky2_xmit_frame,
4254 .ndo_do_ioctl = sky2_ioctl,
4255 .ndo_validate_addr = eth_validate_addr,
4256 .ndo_set_mac_address = sky2_set_mac_address,
4257 .ndo_set_multicast_list = sky2_set_multicast,
4258 .ndo_change_mtu = sky2_change_mtu,
4259 .ndo_tx_timeout = sky2_tx_timeout,
4260 #ifdef SKY2_VLAN_TAG_USED
4261 .ndo_vlan_rx_register = sky2_vlan_rx_register,
4263 #ifdef CONFIG_NET_POLL_CONTROLLER
4264 .ndo_poll_controller = sky2_netpoll,
4268 .ndo_open = sky2_up,
4269 .ndo_stop = sky2_down,
4270 .ndo_start_xmit = sky2_xmit_frame,
4271 .ndo_do_ioctl = sky2_ioctl,
4272 .ndo_validate_addr = eth_validate_addr,
4273 .ndo_set_mac_address = sky2_set_mac_address,
4274 .ndo_set_multicast_list = sky2_set_multicast,
4275 .ndo_change_mtu = sky2_change_mtu,
4276 .ndo_tx_timeout = sky2_tx_timeout,
4277 #ifdef SKY2_VLAN_TAG_USED
4278 .ndo_vlan_rx_register = sky2_vlan_rx_register,
4283 /* Initialize network device */
4284 static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
4286 int highmem, int wol)
4288 struct sky2_port *sky2;
4289 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
4292 dev_err(&hw->pdev->dev, "etherdev alloc failed\n");
4296 SET_NETDEV_DEV(dev, &hw->pdev->dev);
4297 dev->irq = hw->pdev->irq;
4298 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
4299 dev->watchdog_timeo = TX_WATCHDOG;
4300 dev->netdev_ops = &sky2_netdev_ops[port];
4302 sky2 = netdev_priv(dev);
4305 sky2->msg_enable = netif_msg_init(debug, default_msg);
4307 /* Auto speed and flow control */
4308 sky2->flags = SKY2_FLAG_AUTO_SPEED | SKY2_FLAG_AUTO_PAUSE;
4309 if (hw->chip_id != CHIP_ID_YUKON_XL)
4310 sky2->flags |= SKY2_FLAG_RX_CHECKSUM;
4312 sky2->flow_mode = FC_BOTH;
4316 sky2->advertising = sky2_supported_modes(hw);
4319 spin_lock_init(&sky2->phy_lock);
4321 sky2->tx_pending = TX_DEF_PENDING;
4322 sky2->tx_ring_size = roundup_pow_of_two(TX_DEF_PENDING+1);
4323 sky2->rx_pending = RX_DEF_PENDING;
4325 hw->dev[port] = dev;
4329 dev->features |= NETIF_F_TSO | NETIF_F_IP_CSUM | NETIF_F_SG;
4331 dev->features |= NETIF_F_HIGHDMA;
4333 #ifdef SKY2_VLAN_TAG_USED
4334 /* The workaround for FE+ status conflicts with VLAN tag detection. */
4335 if (!(sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
4336 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0)) {
4337 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
4341 /* read the mac address */
4342 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
4343 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
4348 static void __devinit sky2_show_addr(struct net_device *dev)
4350 const struct sky2_port *sky2 = netdev_priv(dev);
4352 if (netif_msg_probe(sky2))
4353 printk(KERN_INFO PFX "%s: addr %pM\n",
4354 dev->name, dev->dev_addr);
4357 /* Handle software interrupt used during MSI test */
4358 static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
4360 struct sky2_hw *hw = dev_id;
4361 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
4366 if (status & Y2_IS_IRQ_SW) {
4367 hw->flags |= SKY2_HW_USE_MSI;
4368 wake_up(&hw->msi_wait);
4369 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4371 sky2_write32(hw, B0_Y2_SP_ICR, 2);
4376 /* Test interrupt path by forcing a a software IRQ */
4377 static int __devinit sky2_test_msi(struct sky2_hw *hw)
4379 struct pci_dev *pdev = hw->pdev;
4382 init_waitqueue_head (&hw->msi_wait);
4384 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
4386 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
4388 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
4392 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
4393 sky2_read8(hw, B0_CTST);
4395 wait_event_timeout(hw->msi_wait, (hw->flags & SKY2_HW_USE_MSI), HZ/10);
4397 if (!(hw->flags & SKY2_HW_USE_MSI)) {
4398 /* MSI test failed, go back to INTx mode */
4399 dev_info(&pdev->dev, "No interrupt generated using MSI, "
4400 "switching to INTx mode.\n");
4403 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4406 sky2_write32(hw, B0_IMSK, 0);
4407 sky2_read32(hw, B0_IMSK);
4409 free_irq(pdev->irq, hw);
4414 /* This driver supports yukon2 chipset only */
4415 static const char *sky2_name(u8 chipid, char *buf, int sz)
4417 const char *name[] = {
4419 "EC Ultra", /* 0xb4 */
4420 "Extreme", /* 0xb5 */
4424 "Supreme", /* 0xb9 */
4428 if (chipid >= CHIP_ID_YUKON_XL && chipid < CHIP_ID_YUKON_UL_2)
4429 strncpy(buf, name[chipid - CHIP_ID_YUKON_XL], sz);
4431 snprintf(buf, sz, "(chip %#x)", chipid);
4435 static int __devinit sky2_probe(struct pci_dev *pdev,
4436 const struct pci_device_id *ent)
4438 struct net_device *dev;
4440 int err, using_dac = 0, wol_default;
4444 err = pci_enable_device(pdev);
4446 dev_err(&pdev->dev, "cannot enable PCI device\n");
4450 /* Get configuration information
4451 * Note: only regular PCI config access once to test for HW issues
4452 * other PCI access through shared memory for speed and to
4453 * avoid MMCONFIG problems.
4455 err = pci_read_config_dword(pdev, PCI_DEV_REG2, ®);
4457 dev_err(&pdev->dev, "PCI read config failed\n");
4462 dev_err(&pdev->dev, "PCI configuration read error\n");
4466 err = pci_request_regions(pdev, DRV_NAME);
4468 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
4469 goto err_out_disable;
4472 pci_set_master(pdev);
4474 if (sizeof(dma_addr_t) > sizeof(u32) &&
4475 !(err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)))) {
4477 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
4479 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
4480 "for consistent allocations\n");
4481 goto err_out_free_regions;
4484 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
4486 dev_err(&pdev->dev, "no usable DMA configuration\n");
4487 goto err_out_free_regions;
4493 /* The sk98lin vendor driver uses hardware byte swapping but
4494 * this driver uses software swapping.
4496 reg &= ~PCI_REV_DESC;
4497 err = pci_write_config_dword(pdev,PCI_DEV_REG2, reg);
4499 dev_err(&pdev->dev, "PCI write config failed\n");
4500 goto err_out_free_regions;
4504 wol_default = device_may_wakeup(&pdev->dev) ? WAKE_MAGIC : 0;
4507 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
4509 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
4510 goto err_out_free_regions;
4515 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
4517 dev_err(&pdev->dev, "cannot map device registers\n");
4518 goto err_out_free_hw;
4521 /* ring for status responses */
4522 hw->st_le = pci_alloc_consistent(pdev, STATUS_LE_BYTES, &hw->st_dma);
4524 goto err_out_iounmap;
4526 err = sky2_init(hw);
4528 goto err_out_iounmap;
4530 dev_info(&pdev->dev, "Yukon-2 %s chip revision %d\n",
4531 sky2_name(hw->chip_id, buf1, sizeof(buf1)), hw->chip_rev);
4535 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
4538 goto err_out_free_pci;
4541 if (!disable_msi && pci_enable_msi(pdev) == 0) {
4542 err = sky2_test_msi(hw);
4543 if (err == -EOPNOTSUPP)
4544 pci_disable_msi(pdev);
4546 goto err_out_free_netdev;
4549 err = register_netdev(dev);
4551 dev_err(&pdev->dev, "cannot register net device\n");
4552 goto err_out_free_netdev;
4555 netif_napi_add(dev, &hw->napi, sky2_poll, NAPI_WEIGHT);
4557 err = request_irq(pdev->irq, sky2_intr,
4558 (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED,
4561 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
4562 goto err_out_unregister;
4564 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
4565 napi_enable(&hw->napi);
4567 sky2_show_addr(dev);
4569 if (hw->ports > 1) {
4570 struct net_device *dev1;
4572 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
4574 dev_warn(&pdev->dev, "allocation for second device failed\n");
4575 else if ((err = register_netdev(dev1))) {
4576 dev_warn(&pdev->dev,
4577 "register of second port failed (%d)\n", err);
4581 sky2_show_addr(dev1);
4584 setup_timer(&hw->watchdog_timer, sky2_watchdog, (unsigned long) hw);
4585 INIT_WORK(&hw->restart_work, sky2_restart);
4587 pci_set_drvdata(pdev, hw);
4592 if (hw->flags & SKY2_HW_USE_MSI)
4593 pci_disable_msi(pdev);
4594 unregister_netdev(dev);
4595 err_out_free_netdev:
4598 sky2_write8(hw, B0_CTST, CS_RST_SET);
4599 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
4604 err_out_free_regions:
4605 pci_release_regions(pdev);
4607 pci_disable_device(pdev);
4609 pci_set_drvdata(pdev, NULL);
4613 static void __devexit sky2_remove(struct pci_dev *pdev)
4615 struct sky2_hw *hw = pci_get_drvdata(pdev);
4621 del_timer_sync(&hw->watchdog_timer);
4622 cancel_work_sync(&hw->restart_work);
4624 for (i = hw->ports-1; i >= 0; --i)
4625 unregister_netdev(hw->dev[i]);
4627 sky2_write32(hw, B0_IMSK, 0);
4631 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
4632 sky2_write8(hw, B0_CTST, CS_RST_SET);
4633 sky2_read8(hw, B0_CTST);
4635 free_irq(pdev->irq, hw);
4636 if (hw->flags & SKY2_HW_USE_MSI)
4637 pci_disable_msi(pdev);
4638 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
4639 pci_release_regions(pdev);
4640 pci_disable_device(pdev);
4642 for (i = hw->ports-1; i >= 0; --i)
4643 free_netdev(hw->dev[i]);
4648 pci_set_drvdata(pdev, NULL);
4652 static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
4654 struct sky2_hw *hw = pci_get_drvdata(pdev);
4660 del_timer_sync(&hw->watchdog_timer);
4661 cancel_work_sync(&hw->restart_work);
4664 for (i = 0; i < hw->ports; i++) {
4665 struct net_device *dev = hw->dev[i];
4666 struct sky2_port *sky2 = netdev_priv(dev);
4671 sky2_wol_init(sky2);
4676 sky2_write32(hw, B0_IMSK, 0);
4677 napi_disable(&hw->napi);
4681 pci_save_state(pdev);
4682 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
4683 pci_set_power_state(pdev, pci_choose_state(pdev, state));
4688 static int sky2_resume(struct pci_dev *pdev)
4690 struct sky2_hw *hw = pci_get_drvdata(pdev);
4696 err = pci_set_power_state(pdev, PCI_D0);
4700 err = pci_restore_state(pdev);
4704 pci_enable_wake(pdev, PCI_D0, 0);
4706 /* Re-enable all clocks */
4707 if (hw->chip_id == CHIP_ID_YUKON_EX ||
4708 hw->chip_id == CHIP_ID_YUKON_EC_U ||
4709 hw->chip_id == CHIP_ID_YUKON_FE_P)
4710 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
4713 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
4714 napi_enable(&hw->napi);
4717 for (i = 0; i < hw->ports; i++) {
4718 err = sky2_reattach(hw->dev[i]);
4728 dev_err(&pdev->dev, "resume failed (%d)\n", err);
4729 pci_disable_device(pdev);
4734 static void sky2_shutdown(struct pci_dev *pdev)
4736 struct sky2_hw *hw = pci_get_drvdata(pdev);
4743 del_timer_sync(&hw->watchdog_timer);
4745 for (i = 0; i < hw->ports; i++) {
4746 struct net_device *dev = hw->dev[i];
4747 struct sky2_port *sky2 = netdev_priv(dev);
4751 sky2_wol_init(sky2);
4759 pci_enable_wake(pdev, PCI_D3hot, wol);
4760 pci_enable_wake(pdev, PCI_D3cold, wol);
4762 pci_disable_device(pdev);
4763 pci_set_power_state(pdev, PCI_D3hot);
4766 static struct pci_driver sky2_driver = {
4768 .id_table = sky2_id_table,
4769 .probe = sky2_probe,
4770 .remove = __devexit_p(sky2_remove),
4772 .suspend = sky2_suspend,
4773 .resume = sky2_resume,
4775 .shutdown = sky2_shutdown,
4778 static int __init sky2_init_module(void)
4780 pr_info(PFX "driver version " DRV_VERSION "\n");
4783 return pci_register_driver(&sky2_driver);
4786 static void __exit sky2_cleanup_module(void)
4788 pci_unregister_driver(&sky2_driver);
4789 sky2_debug_cleanup();
4792 module_init(sky2_init_module);
4793 module_exit(sky2_cleanup_module);
4795 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
4796 MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
4797 MODULE_LICENSE("GPL");
4798 MODULE_VERSION(DRV_VERSION);