2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 #include <linux/crc32.h>
26 #include <linux/kernel.h>
27 #include <linux/module.h>
28 #include <linux/netdevice.h>
29 #include <linux/dma-mapping.h>
30 #include <linux/etherdevice.h>
31 #include <linux/ethtool.h>
32 #include <linux/pci.h>
35 #include <linux/tcp.h>
37 #include <linux/delay.h>
38 #include <linux/workqueue.h>
39 #include <linux/if_vlan.h>
40 #include <linux/prefetch.h>
41 #include <linux/debugfs.h>
42 #include <linux/mii.h>
46 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
47 #define SKY2_VLAN_TAG_USED 1
52 #define DRV_NAME "sky2"
53 #define DRV_VERSION "1.25"
54 #define PFX DRV_NAME " "
57 * The Yukon II chipset takes 64 bit command blocks (called list elements)
58 * that are organized into three (receive, transmit, status) different rings
62 #define RX_LE_SIZE 1024
63 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
64 #define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
65 #define RX_DEF_PENDING RX_MAX_PENDING
67 /* This is the worst case number of transmit list elements for a single skb:
68 VLAN + TSO + CKSUM + Data + skb_frags * DMA */
69 #define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
70 #define TX_MIN_PENDING (MAX_SKB_TX_LE+1)
71 #define TX_MAX_PENDING 4096
72 #define TX_DEF_PENDING 127
74 #define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
75 #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
76 #define TX_WATCHDOG (5 * HZ)
77 #define NAPI_WEIGHT 64
78 #define PHY_RETRIES 1000
80 #define SKY2_EEPROM_MAGIC 0x9955aabb
83 #define RING_NEXT(x,s) (((x)+1) & ((s)-1))
85 static const u32 default_msg =
86 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
87 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
88 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
90 static int debug = -1; /* defaults above */
91 module_param(debug, int, 0);
92 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
94 static int copybreak __read_mostly = 128;
95 module_param(copybreak, int, 0);
96 MODULE_PARM_DESC(copybreak, "Receive copy threshold");
98 static int disable_msi = 0;
99 module_param(disable_msi, int, 0);
100 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
102 static DEFINE_PCI_DEVICE_TABLE(sky2_id_table) = {
103 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
104 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
105 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
108 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4354) }, /* 88E8040 */
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4355) }, /* 88E8040T */
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4357) }, /* 88E8042 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x435A) }, /* 88E8048 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) }, /* 88E8070 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
136 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
137 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
138 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436C) }, /* 88E8072 */
139 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436D) }, /* 88E8055 */
140 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4370) }, /* 88E8075 */
141 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4380) }, /* 88E8057 */
145 MODULE_DEVICE_TABLE(pci, sky2_id_table);
147 /* Avoid conditionals by using array */
148 static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
149 static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
150 static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
152 static void sky2_set_multicast(struct net_device *dev);
154 /* Access to PHY via serial interconnect */
155 static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
159 gma_write16(hw, port, GM_SMI_DATA, val);
160 gma_write16(hw, port, GM_SMI_CTRL,
161 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
163 for (i = 0; i < PHY_RETRIES; i++) {
164 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
168 if (!(ctrl & GM_SMI_CT_BUSY))
174 dev_warn(&hw->pdev->dev,"%s: phy write timeout\n", hw->dev[port]->name);
178 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
182 static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
186 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
187 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
189 for (i = 0; i < PHY_RETRIES; i++) {
190 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
194 if (ctrl & GM_SMI_CT_RD_VAL) {
195 *val = gma_read16(hw, port, GM_SMI_DATA);
202 dev_warn(&hw->pdev->dev, "%s: phy read timeout\n", hw->dev[port]->name);
205 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
209 static inline u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
212 __gm_phy_read(hw, port, reg, &v);
217 static void sky2_power_on(struct sky2_hw *hw)
219 /* switch power to VCC (WA for VAUX problem) */
220 sky2_write8(hw, B0_POWER_CTRL,
221 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
223 /* disable Core Clock Division, */
224 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
226 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
227 /* enable bits are inverted */
228 sky2_write8(hw, B2_Y2_CLK_GATE,
229 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
230 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
231 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
233 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
235 if (hw->flags & SKY2_HW_ADV_POWER_CTL) {
238 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
240 reg = sky2_pci_read32(hw, PCI_DEV_REG4);
241 /* set all bits to 0 except bits 15..12 and 8 */
242 reg &= P_ASPM_CONTROL_MSK;
243 sky2_pci_write32(hw, PCI_DEV_REG4, reg);
245 reg = sky2_pci_read32(hw, PCI_DEV_REG5);
246 /* set all bits to 0 except bits 28 & 27 */
247 reg &= P_CTL_TIM_VMAIN_AV_MSK;
248 sky2_pci_write32(hw, PCI_DEV_REG5, reg);
250 sky2_pci_write32(hw, PCI_CFG_REG_1, 0);
252 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
253 reg = sky2_read32(hw, B2_GP_IO);
254 reg |= GLB_GPIO_STAT_RACE_DIS;
255 sky2_write32(hw, B2_GP_IO, reg);
257 sky2_read32(hw, B2_GP_IO);
260 /* Turn on "driver loaded" LED */
261 sky2_write16(hw, B0_CTST, Y2_LED_STAT_ON);
264 static void sky2_power_aux(struct sky2_hw *hw)
266 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
267 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
269 /* enable bits are inverted */
270 sky2_write8(hw, B2_Y2_CLK_GATE,
271 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
272 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
273 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
275 /* switch power to VAUX if supported and PME from D3cold */
276 if ( (sky2_read32(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
277 pci_pme_capable(hw->pdev, PCI_D3cold))
278 sky2_write8(hw, B0_POWER_CTRL,
279 (PC_VAUX_ENA | PC_VCC_ENA |
280 PC_VAUX_ON | PC_VCC_OFF));
282 /* turn off "driver loaded LED" */
283 sky2_write16(hw, B0_CTST, Y2_LED_STAT_OFF);
286 static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
290 /* disable all GMAC IRQ's */
291 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
293 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
294 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
295 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
296 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
298 reg = gma_read16(hw, port, GM_RX_CTRL);
299 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
300 gma_write16(hw, port, GM_RX_CTRL, reg);
303 /* flow control to advertise bits */
304 static const u16 copper_fc_adv[] = {
306 [FC_TX] = PHY_M_AN_ASP,
307 [FC_RX] = PHY_M_AN_PC,
308 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
311 /* flow control to advertise bits when using 1000BaseX */
312 static const u16 fiber_fc_adv[] = {
313 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
314 [FC_TX] = PHY_M_P_ASYM_MD_X,
315 [FC_RX] = PHY_M_P_SYM_MD_X,
316 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
319 /* flow control to GMA disable bits */
320 static const u16 gm_fc_disable[] = {
321 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
322 [FC_TX] = GM_GPCR_FC_RX_DIS,
323 [FC_RX] = GM_GPCR_FC_TX_DIS,
328 static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
330 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
331 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
333 if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED) &&
334 !(hw->flags & SKY2_HW_NEWER_PHY)) {
335 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
337 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
339 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
341 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
342 if (hw->chip_id == CHIP_ID_YUKON_EC)
343 /* set downshift counter to 3x and enable downshift */
344 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
346 /* set master & slave downshift counter to 1x */
347 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
349 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
352 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
353 if (sky2_is_copper(hw)) {
354 if (!(hw->flags & SKY2_HW_GIGABIT)) {
355 /* enable automatic crossover */
356 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
358 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
359 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
362 /* Enable Class A driver for FE+ A0 */
363 spec = gm_phy_read(hw, port, PHY_MARV_FE_SPEC_2);
364 spec |= PHY_M_FESC_SEL_CL_A;
365 gm_phy_write(hw, port, PHY_MARV_FE_SPEC_2, spec);
368 /* disable energy detect */
369 ctrl &= ~PHY_M_PC_EN_DET_MSK;
371 /* enable automatic crossover */
372 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
374 /* downshift on PHY 88E1112 and 88E1149 is changed */
375 if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED)
376 && (hw->flags & SKY2_HW_NEWER_PHY)) {
377 /* set downshift counter to 3x and enable downshift */
378 ctrl &= ~PHY_M_PC_DSC_MSK;
379 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
383 /* workaround for deviation #4.88 (CRC errors) */
384 /* disable Automatic Crossover */
386 ctrl &= ~PHY_M_PC_MDIX_MSK;
389 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
391 /* special setup for PHY 88E1112 Fiber */
392 if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) {
393 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
395 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
396 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
397 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
398 ctrl &= ~PHY_M_MAC_MD_MSK;
399 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
400 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
402 if (hw->pmd_type == 'P') {
403 /* select page 1 to access Fiber registers */
404 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
406 /* for SFP-module set SIGDET polarity to low */
407 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
408 ctrl |= PHY_M_FIB_SIGD_POL;
409 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
412 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
420 if (sky2->flags & SKY2_FLAG_AUTO_SPEED) {
421 if (sky2_is_copper(hw)) {
422 if (sky2->advertising & ADVERTISED_1000baseT_Full)
423 ct1000 |= PHY_M_1000C_AFD;
424 if (sky2->advertising & ADVERTISED_1000baseT_Half)
425 ct1000 |= PHY_M_1000C_AHD;
426 if (sky2->advertising & ADVERTISED_100baseT_Full)
427 adv |= PHY_M_AN_100_FD;
428 if (sky2->advertising & ADVERTISED_100baseT_Half)
429 adv |= PHY_M_AN_100_HD;
430 if (sky2->advertising & ADVERTISED_10baseT_Full)
431 adv |= PHY_M_AN_10_FD;
432 if (sky2->advertising & ADVERTISED_10baseT_Half)
433 adv |= PHY_M_AN_10_HD;
435 } else { /* special defines for FIBER (88E1040S only) */
436 if (sky2->advertising & ADVERTISED_1000baseT_Full)
437 adv |= PHY_M_AN_1000X_AFD;
438 if (sky2->advertising & ADVERTISED_1000baseT_Half)
439 adv |= PHY_M_AN_1000X_AHD;
442 /* Restart Auto-negotiation */
443 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
445 /* forced speed/duplex settings */
446 ct1000 = PHY_M_1000C_MSE;
448 /* Disable auto update for duplex flow control and duplex */
449 reg |= GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_SPD_DIS;
451 switch (sky2->speed) {
453 ctrl |= PHY_CT_SP1000;
454 reg |= GM_GPCR_SPEED_1000;
457 ctrl |= PHY_CT_SP100;
458 reg |= GM_GPCR_SPEED_100;
462 if (sky2->duplex == DUPLEX_FULL) {
463 reg |= GM_GPCR_DUP_FULL;
464 ctrl |= PHY_CT_DUP_MD;
465 } else if (sky2->speed < SPEED_1000)
466 sky2->flow_mode = FC_NONE;
469 if (sky2->flags & SKY2_FLAG_AUTO_PAUSE) {
470 if (sky2_is_copper(hw))
471 adv |= copper_fc_adv[sky2->flow_mode];
473 adv |= fiber_fc_adv[sky2->flow_mode];
475 reg |= GM_GPCR_AU_FCT_DIS;
476 reg |= gm_fc_disable[sky2->flow_mode];
478 /* Forward pause packets to GMAC? */
479 if (sky2->flow_mode & FC_RX)
480 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
482 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
485 gma_write16(hw, port, GM_GP_CTRL, reg);
487 if (hw->flags & SKY2_HW_GIGABIT)
488 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
490 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
491 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
493 /* Setup Phy LED's */
494 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
497 switch (hw->chip_id) {
498 case CHIP_ID_YUKON_FE:
499 /* on 88E3082 these bits are at 11..9 (shifted left) */
500 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
502 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
504 /* delete ACT LED control bits */
505 ctrl &= ~PHY_M_FELP_LED1_MSK;
506 /* change ACT LED control to blink mode */
507 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
508 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
511 case CHIP_ID_YUKON_FE_P:
512 /* Enable Link Partner Next Page */
513 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
514 ctrl |= PHY_M_PC_ENA_LIP_NP;
516 /* disable Energy Detect and enable scrambler */
517 ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB);
518 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
520 /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */
521 ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) |
522 PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK) |
523 PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED);
525 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
528 case CHIP_ID_YUKON_XL:
529 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
531 /* select page 3 to access LED control register */
532 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
534 /* set LED Function Control register */
535 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
536 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
537 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
538 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
539 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
541 /* set Polarity Control register */
542 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
543 (PHY_M_POLC_LS1_P_MIX(4) |
544 PHY_M_POLC_IS0_P_MIX(4) |
545 PHY_M_POLC_LOS_CTRL(2) |
546 PHY_M_POLC_INIT_CTRL(2) |
547 PHY_M_POLC_STA1_CTRL(2) |
548 PHY_M_POLC_STA0_CTRL(2)));
550 /* restore page register */
551 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
554 case CHIP_ID_YUKON_EC_U:
555 case CHIP_ID_YUKON_EX:
556 case CHIP_ID_YUKON_SUPR:
557 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
559 /* select page 3 to access LED control register */
560 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
562 /* set LED Function Control register */
563 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
564 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
565 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
566 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
567 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
569 /* set Blink Rate in LED Timer Control Register */
570 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
571 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
572 /* restore page register */
573 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
577 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
578 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
580 /* turn off the Rx LED (LED_RX) */
581 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
584 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_UL_2) {
585 /* apply fixes in PHY AFE */
586 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
588 /* increase differential signal amplitude in 10BASE-T */
589 gm_phy_write(hw, port, 0x18, 0xaa99);
590 gm_phy_write(hw, port, 0x17, 0x2011);
592 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
593 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
594 gm_phy_write(hw, port, 0x18, 0xa204);
595 gm_phy_write(hw, port, 0x17, 0x2002);
598 /* set page register to 0 */
599 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
600 } else if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
601 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
602 /* apply workaround for integrated resistors calibration */
603 gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17);
604 gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60);
605 } else if (hw->chip_id != CHIP_ID_YUKON_EX &&
606 hw->chip_id < CHIP_ID_YUKON_SUPR) {
607 /* no effect on Yukon-XL */
608 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
610 if ( !(sky2->flags & SKY2_FLAG_AUTO_SPEED)
611 || sky2->speed == SPEED_100) {
612 /* turn on 100 Mbps LED (LED_LINK100) */
613 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
617 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
621 /* Enable phy interrupt on auto-negotiation complete (or link up) */
622 if (sky2->flags & SKY2_FLAG_AUTO_SPEED)
623 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
625 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
628 static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
629 static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA };
631 static void sky2_phy_power_up(struct sky2_hw *hw, unsigned port)
635 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
636 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
637 reg1 &= ~phy_power[port];
639 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
640 reg1 |= coma_mode[port];
642 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
643 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
644 sky2_pci_read32(hw, PCI_DEV_REG1);
646 if (hw->chip_id == CHIP_ID_YUKON_FE)
647 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_ANE);
648 else if (hw->flags & SKY2_HW_ADV_POWER_CTL)
649 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
652 static void sky2_phy_power_down(struct sky2_hw *hw, unsigned port)
657 /* release GPHY Control reset */
658 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
660 /* release GMAC reset */
661 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
663 if (hw->flags & SKY2_HW_NEWER_PHY) {
664 /* select page 2 to access MAC control register */
665 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
667 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
668 /* allow GMII Power Down */
669 ctrl &= ~PHY_M_MAC_GMIF_PUP;
670 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
672 /* set page register back to 0 */
673 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
676 /* setup General Purpose Control Register */
677 gma_write16(hw, port, GM_GP_CTRL,
678 GM_GPCR_FL_PASS | GM_GPCR_SPEED_100 |
679 GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS |
682 if (hw->chip_id != CHIP_ID_YUKON_EC) {
683 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
684 /* select page 2 to access MAC control register */
685 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
687 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
688 /* enable Power Down */
689 ctrl |= PHY_M_PC_POW_D_ENA;
690 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
692 /* set page register back to 0 */
693 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
696 /* set IEEE compatible Power Down Mode (dev. #4.99) */
697 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_PDOWN);
700 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
701 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
702 reg1 |= phy_power[port]; /* set PHY to PowerDown/COMA Mode */
703 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
704 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
707 /* Force a renegotiation */
708 static void sky2_phy_reinit(struct sky2_port *sky2)
710 spin_lock_bh(&sky2->phy_lock);
711 sky2_phy_init(sky2->hw, sky2->port);
712 spin_unlock_bh(&sky2->phy_lock);
715 /* Put device in state to listen for Wake On Lan */
716 static void sky2_wol_init(struct sky2_port *sky2)
718 struct sky2_hw *hw = sky2->hw;
719 unsigned port = sky2->port;
720 enum flow_control save_mode;
724 /* Bring hardware out of reset */
725 sky2_write16(hw, B0_CTST, CS_RST_CLR);
726 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
728 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
729 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
732 * sky2_reset will re-enable on resume
734 save_mode = sky2->flow_mode;
735 ctrl = sky2->advertising;
737 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
738 sky2->flow_mode = FC_NONE;
740 spin_lock_bh(&sky2->phy_lock);
741 sky2_phy_power_up(hw, port);
742 sky2_phy_init(hw, port);
743 spin_unlock_bh(&sky2->phy_lock);
745 sky2->flow_mode = save_mode;
746 sky2->advertising = ctrl;
748 /* Set GMAC to no flow control and auto update for speed/duplex */
749 gma_write16(hw, port, GM_GP_CTRL,
750 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
751 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
753 /* Set WOL address */
754 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
755 sky2->netdev->dev_addr, ETH_ALEN);
757 /* Turn on appropriate WOL control bits */
758 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
760 if (sky2->wol & WAKE_PHY)
761 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
763 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
765 if (sky2->wol & WAKE_MAGIC)
766 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
768 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;;
770 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
771 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
773 /* Turn on legacy PCI-Express PME mode */
774 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
775 reg1 |= PCI_Y2_PME_LEGACY;
776 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
779 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
783 static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
785 struct net_device *dev = hw->dev[port];
787 if ( (hw->chip_id == CHIP_ID_YUKON_EX &&
788 hw->chip_rev != CHIP_REV_YU_EX_A0) ||
789 hw->chip_id == CHIP_ID_YUKON_FE_P ||
790 hw->chip_id == CHIP_ID_YUKON_SUPR) {
791 /* Yukon-Extreme B0 and further Extreme devices */
792 /* enable Store & Forward mode for TX */
794 if (dev->mtu <= ETH_DATA_LEN)
795 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
796 TX_JUMBO_DIS | TX_STFW_ENA);
799 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
800 TX_JUMBO_ENA| TX_STFW_ENA);
802 if (dev->mtu <= ETH_DATA_LEN)
803 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
805 /* set Tx GMAC FIFO Almost Empty Threshold */
806 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
807 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
809 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
811 /* Can't do offload because of lack of store/forward */
812 dev->features &= ~(NETIF_F_TSO | NETIF_F_SG | NETIF_F_ALL_CSUM);
817 static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
819 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
823 const u8 *addr = hw->dev[port]->dev_addr;
825 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
826 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
828 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
830 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
831 /* WA DEV_472 -- looks like crossed wires on port 2 */
832 /* clear GMAC 1 Control reset */
833 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
835 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
836 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
837 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
838 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
839 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
842 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
844 /* Enable Transmit FIFO Underrun */
845 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
847 spin_lock_bh(&sky2->phy_lock);
848 sky2_phy_power_up(hw, port);
849 sky2_phy_init(hw, port);
850 spin_unlock_bh(&sky2->phy_lock);
853 reg = gma_read16(hw, port, GM_PHY_ADDR);
854 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
856 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
857 gma_read16(hw, port, i);
858 gma_write16(hw, port, GM_PHY_ADDR, reg);
860 /* transmit control */
861 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
863 /* receive control reg: unicast + multicast + no FCS */
864 gma_write16(hw, port, GM_RX_CTRL,
865 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
867 /* transmit flow control */
868 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
870 /* transmit parameter */
871 gma_write16(hw, port, GM_TX_PARAM,
872 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
873 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
874 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
875 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
877 /* serial mode register */
878 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
879 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
881 if (hw->dev[port]->mtu > ETH_DATA_LEN)
882 reg |= GM_SMOD_JUMBO_ENA;
884 gma_write16(hw, port, GM_SERIAL_MODE, reg);
886 /* virtual address for data */
887 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
889 /* physical address: used for pause frames */
890 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
892 /* ignore counter overflows */
893 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
894 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
895 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
897 /* Configure Rx MAC FIFO */
898 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
899 rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
900 if (hw->chip_id == CHIP_ID_YUKON_EX ||
901 hw->chip_id == CHIP_ID_YUKON_FE_P)
902 rx_reg |= GMF_RX_OVER_ON;
904 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg);
906 if (hw->chip_id == CHIP_ID_YUKON_XL) {
907 /* Hardware errata - clear flush mask */
908 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), 0);
910 /* Flush Rx MAC FIFO on any flow control or error */
911 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
914 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
915 reg = RX_GMF_FL_THR_DEF + 1;
916 /* Another magic mystery workaround from sk98lin */
917 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
918 hw->chip_rev == CHIP_REV_YU_FE2_A0)
920 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg);
922 /* Configure Tx MAC FIFO */
923 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
924 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
926 /* On chips without ram buffer, pause is controled by MAC level */
927 if (!(hw->flags & SKY2_HW_RAM_BUFFER)) {
928 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
929 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
931 sky2_set_tx_stfwd(hw, port);
934 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
935 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
936 /* disable dynamic watermark */
937 reg = sky2_read16(hw, SK_REG(port, TX_GMF_EA));
938 reg &= ~TX_DYN_WM_ENA;
939 sky2_write16(hw, SK_REG(port, TX_GMF_EA), reg);
943 /* Assign Ram Buffer allocation to queue */
944 static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
948 /* convert from K bytes to qwords used for hw register */
951 end = start + space - 1;
953 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
954 sky2_write32(hw, RB_ADDR(q, RB_START), start);
955 sky2_write32(hw, RB_ADDR(q, RB_END), end);
956 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
957 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
959 if (q == Q_R1 || q == Q_R2) {
960 u32 tp = space - space/4;
962 /* On receive queue's set the thresholds
963 * give receiver priority when > 3/4 full
964 * send pause when down to 2K
966 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
967 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
970 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
971 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
973 /* Enable store & forward on Tx queue's because
974 * Tx FIFO is only 1K on Yukon
976 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
979 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
980 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
983 /* Setup Bus Memory Interface */
984 static void sky2_qset(struct sky2_hw *hw, u16 q)
986 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
987 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
988 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
989 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
992 /* Setup prefetch unit registers. This is the interface between
993 * hardware and driver list elements
995 static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
996 dma_addr_t addr, u32 last)
998 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
999 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
1000 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), upper_32_bits(addr));
1001 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), lower_32_bits(addr));
1002 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
1003 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
1005 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
1008 static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2, u16 *slot)
1010 struct sky2_tx_le *le = sky2->tx_le + *slot;
1011 struct tx_ring_info *re = sky2->tx_ring + *slot;
1013 *slot = RING_NEXT(*slot, sky2->tx_ring_size);
1020 static void tx_init(struct sky2_port *sky2)
1022 struct sky2_tx_le *le;
1024 sky2->tx_prod = sky2->tx_cons = 0;
1025 sky2->tx_tcpsum = 0;
1026 sky2->tx_last_mss = 0;
1028 le = get_tx_le(sky2, &sky2->tx_prod);
1030 le->opcode = OP_ADDR64 | HW_OWNER;
1031 sky2->tx_last_upper = 0;
1034 /* Update chip's next pointer */
1035 static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
1037 /* Make sure write' to descriptors are complete before we tell hardware */
1039 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
1041 /* Synchronize I/O on since next processor may write to tail */
1046 static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
1048 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
1049 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
1054 /* Build description to hardware for one receive segment */
1055 static void sky2_rx_add(struct sky2_port *sky2, u8 op,
1056 dma_addr_t map, unsigned len)
1058 struct sky2_rx_le *le;
1060 if (sizeof(dma_addr_t) > sizeof(u32)) {
1061 le = sky2_next_rx(sky2);
1062 le->addr = cpu_to_le32(upper_32_bits(map));
1063 le->opcode = OP_ADDR64 | HW_OWNER;
1066 le = sky2_next_rx(sky2);
1067 le->addr = cpu_to_le32(lower_32_bits(map));
1068 le->length = cpu_to_le16(len);
1069 le->opcode = op | HW_OWNER;
1072 /* Build description to hardware for one possibly fragmented skb */
1073 static void sky2_rx_submit(struct sky2_port *sky2,
1074 const struct rx_ring_info *re)
1078 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
1080 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
1081 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
1085 static int sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
1088 struct sk_buff *skb = re->skb;
1091 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
1092 if (unlikely(pci_dma_mapping_error(pdev, re->data_addr)))
1095 pci_unmap_len_set(re, data_size, size);
1097 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1098 re->frag_addr[i] = pci_map_page(pdev,
1099 skb_shinfo(skb)->frags[i].page,
1100 skb_shinfo(skb)->frags[i].page_offset,
1101 skb_shinfo(skb)->frags[i].size,
1102 PCI_DMA_FROMDEVICE);
1106 static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
1108 struct sk_buff *skb = re->skb;
1111 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
1112 PCI_DMA_FROMDEVICE);
1114 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1115 pci_unmap_page(pdev, re->frag_addr[i],
1116 skb_shinfo(skb)->frags[i].size,
1117 PCI_DMA_FROMDEVICE);
1120 /* Tell chip where to start receive checksum.
1121 * Actually has two checksums, but set both same to avoid possible byte
1124 static void rx_set_checksum(struct sky2_port *sky2)
1126 struct sky2_rx_le *le = sky2_next_rx(sky2);
1128 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
1130 le->opcode = OP_TCPSTART | HW_OWNER;
1132 sky2_write32(sky2->hw,
1133 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1134 (sky2->flags & SKY2_FLAG_RX_CHECKSUM)
1135 ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
1139 * The RX Stop command will not work for Yukon-2 if the BMU does not
1140 * reach the end of packet and since we can't make sure that we have
1141 * incoming data, we must reset the BMU while it is not doing a DMA
1142 * transfer. Since it is possible that the RX path is still active,
1143 * the RX RAM buffer will be stopped first, so any possible incoming
1144 * data will not trigger a DMA. After the RAM buffer is stopped, the
1145 * BMU is polled until any DMA in progress is ended and only then it
1148 static void sky2_rx_stop(struct sky2_port *sky2)
1150 struct sky2_hw *hw = sky2->hw;
1151 unsigned rxq = rxqaddr[sky2->port];
1154 /* disable the RAM Buffer receive queue */
1155 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
1157 for (i = 0; i < 0xffff; i++)
1158 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
1159 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
1162 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
1163 sky2->netdev->name);
1165 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
1167 /* reset the Rx prefetch unit */
1168 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1172 /* Clean out receive buffer area, assumes receiver hardware stopped */
1173 static void sky2_rx_clean(struct sky2_port *sky2)
1177 memset(sky2->rx_le, 0, RX_LE_BYTES);
1178 for (i = 0; i < sky2->rx_pending; i++) {
1179 struct rx_ring_info *re = sky2->rx_ring + i;
1182 sky2_rx_unmap_skb(sky2->hw->pdev, re);
1189 /* Basic MII support */
1190 static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1192 struct mii_ioctl_data *data = if_mii(ifr);
1193 struct sky2_port *sky2 = netdev_priv(dev);
1194 struct sky2_hw *hw = sky2->hw;
1195 int err = -EOPNOTSUPP;
1197 if (!netif_running(dev))
1198 return -ENODEV; /* Phy still in reset */
1202 data->phy_id = PHY_ADDR_MARV;
1208 spin_lock_bh(&sky2->phy_lock);
1209 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
1210 spin_unlock_bh(&sky2->phy_lock);
1212 data->val_out = val;
1217 if (!capable(CAP_NET_ADMIN))
1220 spin_lock_bh(&sky2->phy_lock);
1221 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1223 spin_unlock_bh(&sky2->phy_lock);
1229 #ifdef SKY2_VLAN_TAG_USED
1230 static void sky2_set_vlan_mode(struct sky2_hw *hw, u16 port, bool onoff)
1233 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1235 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1238 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1240 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1245 static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1247 struct sky2_port *sky2 = netdev_priv(dev);
1248 struct sky2_hw *hw = sky2->hw;
1249 u16 port = sky2->port;
1251 netif_tx_lock_bh(dev);
1252 napi_disable(&hw->napi);
1255 sky2_set_vlan_mode(hw, port, grp != NULL);
1257 sky2_read32(hw, B0_Y2_SP_LISR);
1258 napi_enable(&hw->napi);
1259 netif_tx_unlock_bh(dev);
1263 /* Amount of required worst case padding in rx buffer */
1264 static inline unsigned sky2_rx_pad(const struct sky2_hw *hw)
1266 return (hw->flags & SKY2_HW_RAM_BUFFER) ? 8 : 2;
1270 * Allocate an skb for receiving. If the MTU is large enough
1271 * make the skb non-linear with a fragment list of pages.
1273 static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
1275 struct sk_buff *skb;
1278 skb = netdev_alloc_skb(sky2->netdev,
1279 sky2->rx_data_size + sky2_rx_pad(sky2->hw));
1283 if (sky2->hw->flags & SKY2_HW_RAM_BUFFER) {
1284 unsigned char *start;
1286 * Workaround for a bug in FIFO that cause hang
1287 * if the FIFO if the receive buffer is not 64 byte aligned.
1288 * The buffer returned from netdev_alloc_skb is
1289 * aligned except if slab debugging is enabled.
1291 start = PTR_ALIGN(skb->data, 8);
1292 skb_reserve(skb, start - skb->data);
1294 skb_reserve(skb, NET_IP_ALIGN);
1296 for (i = 0; i < sky2->rx_nfrags; i++) {
1297 struct page *page = alloc_page(GFP_ATOMIC);
1301 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
1311 static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq)
1313 sky2_put_idx(sky2->hw, rxq, sky2->rx_put);
1317 * Allocate and setup receiver buffer pool.
1318 * Normal case this ends up creating one list element for skb
1319 * in the receive ring. Worst case if using large MTU and each
1320 * allocation falls on a different 64 bit region, that results
1321 * in 6 list elements per ring entry.
1322 * One element is used for checksum enable/disable, and one
1323 * extra to avoid wrap.
1325 static int sky2_rx_start(struct sky2_port *sky2)
1327 struct sky2_hw *hw = sky2->hw;
1328 struct rx_ring_info *re;
1329 unsigned rxq = rxqaddr[sky2->port];
1330 unsigned i, size, thresh;
1332 sky2->rx_put = sky2->rx_next = 0;
1335 /* On PCI express lowering the watermark gives better performance */
1336 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
1337 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1339 /* These chips have no ram buffer?
1340 * MAC Rx RAM Read is controlled by hardware */
1341 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
1342 (hw->chip_rev == CHIP_REV_YU_EC_U_A1
1343 || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
1344 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
1346 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1348 if (!(hw->flags & SKY2_HW_NEW_LE))
1349 rx_set_checksum(sky2);
1351 /* Space needed for frame data + headers rounded up */
1352 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
1354 /* Stopping point for hardware truncation */
1355 thresh = (size - 8) / sizeof(u32);
1357 sky2->rx_nfrags = size >> PAGE_SHIFT;
1358 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1360 /* Compute residue after pages */
1361 size -= sky2->rx_nfrags << PAGE_SHIFT;
1363 /* Optimize to handle small packets and headers */
1364 if (size < copybreak)
1366 if (size < ETH_HLEN)
1369 sky2->rx_data_size = size;
1372 for (i = 0; i < sky2->rx_pending; i++) {
1373 re = sky2->rx_ring + i;
1375 re->skb = sky2_rx_alloc(sky2);
1379 if (sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size)) {
1380 dev_kfree_skb(re->skb);
1385 sky2_rx_submit(sky2, re);
1389 * The receiver hangs if it receives frames larger than the
1390 * packet buffer. As a workaround, truncate oversize frames, but
1391 * the register is limited to 9 bits, so if you do frames > 2052
1392 * you better get the MTU right!
1395 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1397 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1398 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1401 /* Tell chip about available buffers */
1402 sky2_rx_update(sky2, rxq);
1405 sky2_rx_clean(sky2);
1409 static int sky2_alloc_buffers(struct sky2_port *sky2)
1411 struct sky2_hw *hw = sky2->hw;
1413 /* must be power of 2 */
1414 sky2->tx_le = pci_alloc_consistent(hw->pdev,
1415 sky2->tx_ring_size *
1416 sizeof(struct sky2_tx_le),
1421 sky2->tx_ring = kcalloc(sky2->tx_ring_size, sizeof(struct tx_ring_info),
1426 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1430 memset(sky2->rx_le, 0, RX_LE_BYTES);
1432 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
1442 static void sky2_free_buffers(struct sky2_port *sky2)
1444 struct sky2_hw *hw = sky2->hw;
1447 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1448 sky2->rx_le, sky2->rx_le_map);
1452 pci_free_consistent(hw->pdev,
1453 sky2->tx_ring_size * sizeof(struct sky2_tx_le),
1454 sky2->tx_le, sky2->tx_le_map);
1457 kfree(sky2->tx_ring);
1458 kfree(sky2->rx_ring);
1460 sky2->tx_ring = NULL;
1461 sky2->rx_ring = NULL;
1464 /* Bring up network interface. */
1465 static int sky2_up(struct net_device *dev)
1467 struct sky2_port *sky2 = netdev_priv(dev);
1468 struct sky2_hw *hw = sky2->hw;
1469 unsigned port = sky2->port;
1472 struct net_device *otherdev = hw->dev[sky2->port^1];
1475 * On dual port PCI-X card, there is an problem where status
1476 * can be received out of order due to split transactions
1478 if (otherdev && netif_running(otherdev) &&
1479 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1482 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
1483 cmd &= ~PCI_X_CMD_MAX_SPLIT;
1484 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1488 netif_carrier_off(dev);
1490 err = sky2_alloc_buffers(sky2);
1496 sky2_mac_init(hw, port);
1498 /* Register is number of 4K blocks on internal RAM buffer. */
1499 ramsize = sky2_read8(hw, B2_E_0) * 4;
1503 hw->flags |= SKY2_HW_RAM_BUFFER;
1504 pr_debug(PFX "%s: ram buffer %dK\n", dev->name, ramsize);
1506 rxspace = ramsize / 2;
1508 rxspace = 8 + (2*(ramsize - 16))/3;
1510 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1511 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1513 /* Make sure SyncQ is disabled */
1514 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1518 sky2_qset(hw, txqaddr[port]);
1520 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1521 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0)
1522 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF);
1524 /* Set almost empty threshold */
1525 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1526 && hw->chip_rev == CHIP_REV_YU_EC_U_A0)
1527 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
1529 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1530 sky2->tx_ring_size - 1);
1532 #ifdef SKY2_VLAN_TAG_USED
1533 sky2_set_vlan_mode(hw, port, sky2->vlgrp != NULL);
1536 err = sky2_rx_start(sky2);
1540 /* Enable interrupts from phy/mac for port */
1541 imask = sky2_read32(hw, B0_IMSK);
1542 imask |= portirq_msk[port];
1543 sky2_write32(hw, B0_IMSK, imask);
1544 sky2_read32(hw, B0_IMSK);
1546 if (netif_msg_ifup(sky2))
1547 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1552 sky2_free_buffers(sky2);
1556 /* Modular subtraction in ring */
1557 static inline int tx_inuse(const struct sky2_port *sky2)
1559 return (sky2->tx_prod - sky2->tx_cons) & (sky2->tx_ring_size - 1);
1562 /* Number of list elements available for next tx */
1563 static inline int tx_avail(const struct sky2_port *sky2)
1565 return sky2->tx_pending - tx_inuse(sky2);
1568 /* Estimate of number of transmit list elements required */
1569 static unsigned tx_le_req(const struct sk_buff *skb)
1573 count = sizeof(dma_addr_t) / sizeof(u32);
1574 count += skb_shinfo(skb)->nr_frags * count;
1576 if (skb_is_gso(skb))
1579 if (skb->ip_summed == CHECKSUM_PARTIAL)
1585 static void sky2_tx_unmap(struct pci_dev *pdev,
1586 const struct tx_ring_info *re)
1588 if (re->flags & TX_MAP_SINGLE)
1589 pci_unmap_single(pdev, pci_unmap_addr(re, mapaddr),
1590 pci_unmap_len(re, maplen),
1592 else if (re->flags & TX_MAP_PAGE)
1593 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1594 pci_unmap_len(re, maplen),
1599 * Put one packet in ring for transmit.
1600 * A single packet can generate multiple list elements, and
1601 * the number of ring elements will probably be less than the number
1602 * of list elements used.
1604 static netdev_tx_t sky2_xmit_frame(struct sk_buff *skb,
1605 struct net_device *dev)
1607 struct sky2_port *sky2 = netdev_priv(dev);
1608 struct sky2_hw *hw = sky2->hw;
1609 struct sky2_tx_le *le = NULL;
1610 struct tx_ring_info *re;
1618 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1619 return NETDEV_TX_BUSY;
1621 len = skb_headlen(skb);
1622 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
1624 if (pci_dma_mapping_error(hw->pdev, mapping))
1627 slot = sky2->tx_prod;
1628 if (unlikely(netif_msg_tx_queued(sky2)))
1629 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1630 dev->name, slot, skb->len);
1632 /* Send high bits if needed */
1633 upper = upper_32_bits(mapping);
1634 if (upper != sky2->tx_last_upper) {
1635 le = get_tx_le(sky2, &slot);
1636 le->addr = cpu_to_le32(upper);
1637 sky2->tx_last_upper = upper;
1638 le->opcode = OP_ADDR64 | HW_OWNER;
1641 /* Check for TCP Segmentation Offload */
1642 mss = skb_shinfo(skb)->gso_size;
1645 if (!(hw->flags & SKY2_HW_NEW_LE))
1646 mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb);
1648 if (mss != sky2->tx_last_mss) {
1649 le = get_tx_le(sky2, &slot);
1650 le->addr = cpu_to_le32(mss);
1652 if (hw->flags & SKY2_HW_NEW_LE)
1653 le->opcode = OP_MSS | HW_OWNER;
1655 le->opcode = OP_LRGLEN | HW_OWNER;
1656 sky2->tx_last_mss = mss;
1661 #ifdef SKY2_VLAN_TAG_USED
1662 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1663 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1665 le = get_tx_le(sky2, &slot);
1667 le->opcode = OP_VLAN|HW_OWNER;
1669 le->opcode |= OP_VLAN;
1670 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1675 /* Handle TCP checksum offload */
1676 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1677 /* On Yukon EX (some versions) encoding change. */
1678 if (hw->flags & SKY2_HW_AUTO_TX_SUM)
1679 ctrl |= CALSUM; /* auto checksum */
1681 const unsigned offset = skb_transport_offset(skb);
1684 tcpsum = offset << 16; /* sum start */
1685 tcpsum |= offset + skb->csum_offset; /* sum write */
1687 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1688 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1691 if (tcpsum != sky2->tx_tcpsum) {
1692 sky2->tx_tcpsum = tcpsum;
1694 le = get_tx_le(sky2, &slot);
1695 le->addr = cpu_to_le32(tcpsum);
1696 le->length = 0; /* initial checksum value */
1697 le->ctrl = 1; /* one packet */
1698 le->opcode = OP_TCPLISW | HW_OWNER;
1703 re = sky2->tx_ring + slot;
1704 re->flags = TX_MAP_SINGLE;
1705 pci_unmap_addr_set(re, mapaddr, mapping);
1706 pci_unmap_len_set(re, maplen, len);
1708 le = get_tx_le(sky2, &slot);
1709 le->addr = cpu_to_le32(lower_32_bits(mapping));
1710 le->length = cpu_to_le16(len);
1712 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
1715 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1716 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1718 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1719 frag->size, PCI_DMA_TODEVICE);
1721 if (pci_dma_mapping_error(hw->pdev, mapping))
1722 goto mapping_unwind;
1724 upper = upper_32_bits(mapping);
1725 if (upper != sky2->tx_last_upper) {
1726 le = get_tx_le(sky2, &slot);
1727 le->addr = cpu_to_le32(upper);
1728 sky2->tx_last_upper = upper;
1729 le->opcode = OP_ADDR64 | HW_OWNER;
1732 re = sky2->tx_ring + slot;
1733 re->flags = TX_MAP_PAGE;
1734 pci_unmap_addr_set(re, mapaddr, mapping);
1735 pci_unmap_len_set(re, maplen, frag->size);
1737 le = get_tx_le(sky2, &slot);
1738 le->addr = cpu_to_le32(lower_32_bits(mapping));
1739 le->length = cpu_to_le16(frag->size);
1741 le->opcode = OP_BUFFER | HW_OWNER;
1747 sky2->tx_prod = slot;
1749 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1750 netif_stop_queue(dev);
1752 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
1754 return NETDEV_TX_OK;
1757 for (i = sky2->tx_prod; i != slot; i = RING_NEXT(i, sky2->tx_ring_size)) {
1758 re = sky2->tx_ring + i;
1760 sky2_tx_unmap(hw->pdev, re);
1764 if (net_ratelimit())
1765 dev_warn(&hw->pdev->dev, "%s: tx mapping error\n", dev->name);
1767 return NETDEV_TX_OK;
1771 * Free ring elements from starting at tx_cons until "done"
1774 * 1. The hardware will tell us about partial completion of multi-part
1775 * buffers so make sure not to free skb to early.
1776 * 2. This may run in parallel start_xmit because the it only
1777 * looks at the tail of the queue of FIFO (tx_cons), not
1778 * the head (tx_prod)
1780 static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
1782 struct net_device *dev = sky2->netdev;
1785 BUG_ON(done >= sky2->tx_ring_size);
1787 for (idx = sky2->tx_cons; idx != done;
1788 idx = RING_NEXT(idx, sky2->tx_ring_size)) {
1789 struct tx_ring_info *re = sky2->tx_ring + idx;
1790 struct sk_buff *skb = re->skb;
1792 sky2_tx_unmap(sky2->hw->pdev, re);
1795 if (unlikely(netif_msg_tx_done(sky2)))
1796 printk(KERN_DEBUG "%s: tx done %u\n",
1799 dev->stats.tx_packets++;
1800 dev->stats.tx_bytes += skb->len;
1802 dev_kfree_skb_any(skb);
1804 sky2->tx_next = RING_NEXT(idx, sky2->tx_ring_size);
1808 sky2->tx_cons = idx;
1811 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
1812 netif_wake_queue(dev);
1815 static void sky2_tx_reset(struct sky2_hw *hw, unsigned port)
1817 /* Disable Force Sync bit and Enable Alloc bit */
1818 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1819 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1821 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1822 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1823 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1825 /* Reset the PCI FIFO of the async Tx queue */
1826 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1827 BMU_RST_SET | BMU_FIFO_RST);
1829 /* Reset the Tx prefetch units */
1830 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1833 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1834 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1837 /* Network shutdown */
1838 static int sky2_down(struct net_device *dev)
1840 struct sky2_port *sky2 = netdev_priv(dev);
1841 struct sky2_hw *hw = sky2->hw;
1842 unsigned port = sky2->port;
1846 /* Never really got started! */
1850 if (netif_msg_ifdown(sky2))
1851 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1853 /* Force flow control off */
1854 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1856 /* Stop transmitter */
1857 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1858 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1860 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
1861 RB_RST_SET | RB_DIS_OP_MD);
1863 ctrl = gma_read16(hw, port, GM_GP_CTRL);
1864 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
1865 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1867 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1869 /* Workaround shared GMAC reset */
1870 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1871 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
1872 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1874 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1876 /* Force any delayed status interrrupt and NAPI */
1877 sky2_write32(hw, STAT_LEV_TIMER_CNT, 0);
1878 sky2_write32(hw, STAT_TX_TIMER_CNT, 0);
1879 sky2_write32(hw, STAT_ISR_TIMER_CNT, 0);
1880 sky2_read8(hw, STAT_ISR_TIMER_CTRL);
1884 /* Disable port IRQ */
1885 imask = sky2_read32(hw, B0_IMSK);
1886 imask &= ~portirq_msk[port];
1887 sky2_write32(hw, B0_IMSK, imask);
1888 sky2_read32(hw, B0_IMSK);
1890 synchronize_irq(hw->pdev->irq);
1891 napi_synchronize(&hw->napi);
1893 spin_lock_bh(&sky2->phy_lock);
1894 sky2_phy_power_down(hw, port);
1895 spin_unlock_bh(&sky2->phy_lock);
1897 sky2_tx_reset(hw, port);
1899 /* Free any pending frames stuck in HW queue */
1900 sky2_tx_complete(sky2, sky2->tx_prod);
1902 sky2_rx_clean(sky2);
1904 sky2_free_buffers(sky2);
1909 static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1911 if (hw->flags & SKY2_HW_FIBRE_PHY)
1914 if (!(hw->flags & SKY2_HW_GIGABIT)) {
1915 if (aux & PHY_M_PS_SPEED_100)
1921 switch (aux & PHY_M_PS_SPEED_MSK) {
1922 case PHY_M_PS_SPEED_1000:
1924 case PHY_M_PS_SPEED_100:
1931 static void sky2_link_up(struct sky2_port *sky2)
1933 struct sky2_hw *hw = sky2->hw;
1934 unsigned port = sky2->port;
1936 static const char *fc_name[] = {
1944 reg = gma_read16(hw, port, GM_GP_CTRL);
1945 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1946 gma_write16(hw, port, GM_GP_CTRL, reg);
1948 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1950 netif_carrier_on(sky2->netdev);
1952 mod_timer(&hw->watchdog_timer, jiffies + 1);
1954 /* Turn on link LED */
1955 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
1956 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1958 if (netif_msg_link(sky2))
1959 printk(KERN_INFO PFX
1960 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
1961 sky2->netdev->name, sky2->speed,
1962 sky2->duplex == DUPLEX_FULL ? "full" : "half",
1963 fc_name[sky2->flow_status]);
1966 static void sky2_link_down(struct sky2_port *sky2)
1968 struct sky2_hw *hw = sky2->hw;
1969 unsigned port = sky2->port;
1972 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1974 reg = gma_read16(hw, port, GM_GP_CTRL);
1975 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1976 gma_write16(hw, port, GM_GP_CTRL, reg);
1978 netif_carrier_off(sky2->netdev);
1980 /* Turn on link LED */
1981 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1983 if (netif_msg_link(sky2))
1984 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
1986 sky2_phy_init(hw, port);
1989 static enum flow_control sky2_flow(int rx, int tx)
1992 return tx ? FC_BOTH : FC_RX;
1994 return tx ? FC_TX : FC_NONE;
1997 static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1999 struct sky2_hw *hw = sky2->hw;
2000 unsigned port = sky2->port;
2003 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
2004 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
2005 if (lpa & PHY_M_AN_RF) {
2006 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
2010 if (!(aux & PHY_M_PS_SPDUP_RES)) {
2011 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
2012 sky2->netdev->name);
2016 sky2->speed = sky2_phy_speed(hw, aux);
2017 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2019 /* Since the pause result bits seem to in different positions on
2020 * different chips. look at registers.
2022 if (hw->flags & SKY2_HW_FIBRE_PHY) {
2023 /* Shift for bits in fiber PHY */
2024 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
2025 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
2027 if (advert & ADVERTISE_1000XPAUSE)
2028 advert |= ADVERTISE_PAUSE_CAP;
2029 if (advert & ADVERTISE_1000XPSE_ASYM)
2030 advert |= ADVERTISE_PAUSE_ASYM;
2031 if (lpa & LPA_1000XPAUSE)
2032 lpa |= LPA_PAUSE_CAP;
2033 if (lpa & LPA_1000XPAUSE_ASYM)
2034 lpa |= LPA_PAUSE_ASYM;
2037 sky2->flow_status = FC_NONE;
2038 if (advert & ADVERTISE_PAUSE_CAP) {
2039 if (lpa & LPA_PAUSE_CAP)
2040 sky2->flow_status = FC_BOTH;
2041 else if (advert & ADVERTISE_PAUSE_ASYM)
2042 sky2->flow_status = FC_RX;
2043 } else if (advert & ADVERTISE_PAUSE_ASYM) {
2044 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
2045 sky2->flow_status = FC_TX;
2048 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000
2049 && !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
2050 sky2->flow_status = FC_NONE;
2052 if (sky2->flow_status & FC_TX)
2053 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
2055 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2060 /* Interrupt from PHY */
2061 static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
2063 struct net_device *dev = hw->dev[port];
2064 struct sky2_port *sky2 = netdev_priv(dev);
2065 u16 istatus, phystat;
2067 if (!netif_running(dev))
2070 spin_lock(&sky2->phy_lock);
2071 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
2072 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
2074 if (netif_msg_intr(sky2))
2075 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
2076 sky2->netdev->name, istatus, phystat);
2078 if (istatus & PHY_M_IS_AN_COMPL) {
2079 if (sky2_autoneg_done(sky2, phystat) == 0)
2084 if (istatus & PHY_M_IS_LSP_CHANGE)
2085 sky2->speed = sky2_phy_speed(hw, phystat);
2087 if (istatus & PHY_M_IS_DUP_CHANGE)
2089 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2091 if (istatus & PHY_M_IS_LST_CHANGE) {
2092 if (phystat & PHY_M_PS_LINK_UP)
2095 sky2_link_down(sky2);
2098 spin_unlock(&sky2->phy_lock);
2101 /* Transmit timeout is only called if we are running, carrier is up
2102 * and tx queue is full (stopped).
2104 static void sky2_tx_timeout(struct net_device *dev)
2106 struct sky2_port *sky2 = netdev_priv(dev);
2107 struct sky2_hw *hw = sky2->hw;
2109 if (netif_msg_timer(sky2))
2110 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
2112 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
2113 dev->name, sky2->tx_cons, sky2->tx_prod,
2114 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
2115 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
2117 /* can't restart safely under softirq */
2118 schedule_work(&hw->restart_work);
2121 static int sky2_change_mtu(struct net_device *dev, int new_mtu)
2123 struct sky2_port *sky2 = netdev_priv(dev);
2124 struct sky2_hw *hw = sky2->hw;
2125 unsigned port = sky2->port;
2130 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2133 if (new_mtu > ETH_DATA_LEN &&
2134 (hw->chip_id == CHIP_ID_YUKON_FE ||
2135 hw->chip_id == CHIP_ID_YUKON_FE_P))
2138 if (!netif_running(dev)) {
2143 imask = sky2_read32(hw, B0_IMSK);
2144 sky2_write32(hw, B0_IMSK, 0);
2146 dev->trans_start = jiffies; /* prevent tx timeout */
2147 netif_stop_queue(dev);
2148 napi_disable(&hw->napi);
2150 synchronize_irq(hw->pdev->irq);
2152 if (!(hw->flags & SKY2_HW_RAM_BUFFER))
2153 sky2_set_tx_stfwd(hw, port);
2155 ctl = gma_read16(hw, port, GM_GP_CTRL);
2156 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
2158 sky2_rx_clean(sky2);
2162 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
2163 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
2165 if (dev->mtu > ETH_DATA_LEN)
2166 mode |= GM_SMOD_JUMBO_ENA;
2168 gma_write16(hw, port, GM_SERIAL_MODE, mode);
2170 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
2172 err = sky2_rx_start(sky2);
2173 sky2_write32(hw, B0_IMSK, imask);
2175 sky2_read32(hw, B0_Y2_SP_LISR);
2176 napi_enable(&hw->napi);
2181 gma_write16(hw, port, GM_GP_CTRL, ctl);
2183 netif_wake_queue(dev);
2189 /* For small just reuse existing skb for next receive */
2190 static struct sk_buff *receive_copy(struct sky2_port *sky2,
2191 const struct rx_ring_info *re,
2194 struct sk_buff *skb;
2196 skb = netdev_alloc_skb(sky2->netdev, length + 2);
2198 skb_reserve(skb, 2);
2199 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
2200 length, PCI_DMA_FROMDEVICE);
2201 skb_copy_from_linear_data(re->skb, skb->data, length);
2202 skb->ip_summed = re->skb->ip_summed;
2203 skb->csum = re->skb->csum;
2204 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
2205 length, PCI_DMA_FROMDEVICE);
2206 re->skb->ip_summed = CHECKSUM_NONE;
2207 skb_put(skb, length);
2212 /* Adjust length of skb with fragments to match received data */
2213 static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
2214 unsigned int length)
2219 /* put header into skb */
2220 size = min(length, hdr_space);
2225 num_frags = skb_shinfo(skb)->nr_frags;
2226 for (i = 0; i < num_frags; i++) {
2227 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2230 /* don't need this page */
2231 __free_page(frag->page);
2232 --skb_shinfo(skb)->nr_frags;
2234 size = min(length, (unsigned) PAGE_SIZE);
2237 skb->data_len += size;
2238 skb->truesize += size;
2245 /* Normal packet - take skb from ring element and put in a new one */
2246 static struct sk_buff *receive_new(struct sky2_port *sky2,
2247 struct rx_ring_info *re,
2248 unsigned int length)
2250 struct sk_buff *skb, *nskb;
2251 unsigned hdr_space = sky2->rx_data_size;
2253 /* Don't be tricky about reusing pages (yet) */
2254 nskb = sky2_rx_alloc(sky2);
2255 if (unlikely(!nskb))
2259 sky2_rx_unmap_skb(sky2->hw->pdev, re);
2261 prefetch(skb->data);
2263 if (sky2_rx_map_skb(sky2->hw->pdev, re, hdr_space)) {
2264 dev_kfree_skb(nskb);
2269 if (skb_shinfo(skb)->nr_frags)
2270 skb_put_frags(skb, hdr_space, length);
2272 skb_put(skb, length);
2277 * Receive one packet.
2278 * For larger packets, get new buffer.
2280 static struct sk_buff *sky2_receive(struct net_device *dev,
2281 u16 length, u32 status)
2283 struct sky2_port *sky2 = netdev_priv(dev);
2284 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
2285 struct sk_buff *skb = NULL;
2286 u16 count = (status & GMR_FS_LEN) >> 16;
2288 #ifdef SKY2_VLAN_TAG_USED
2289 /* Account for vlan tag */
2290 if (sky2->vlgrp && (status & GMR_FS_VLAN))
2294 if (unlikely(netif_msg_rx_status(sky2)))
2295 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
2296 dev->name, sky2->rx_next, status, length);
2298 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
2299 prefetch(sky2->rx_ring + sky2->rx_next);
2301 /* This chip has hardware problems that generates bogus status.
2302 * So do only marginal checking and expect higher level protocols
2303 * to handle crap frames.
2305 if (sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
2306 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0 &&
2310 if (status & GMR_FS_ANY_ERR)
2313 if (!(status & GMR_FS_RX_OK))
2316 /* if length reported by DMA does not match PHY, packet was truncated */
2317 if (length != count)
2321 if (length < copybreak)
2322 skb = receive_copy(sky2, re, length);
2324 skb = receive_new(sky2, re, length);
2326 sky2_rx_submit(sky2, re);
2331 /* Truncation of overlength packets
2332 causes PHY length to not match MAC length */
2333 ++dev->stats.rx_length_errors;
2334 if (netif_msg_rx_err(sky2) && net_ratelimit())
2335 pr_info(PFX "%s: rx length error: status %#x length %d\n",
2336 dev->name, status, length);
2340 ++dev->stats.rx_errors;
2341 if (status & GMR_FS_RX_FF_OV) {
2342 dev->stats.rx_over_errors++;
2346 if (netif_msg_rx_err(sky2) && net_ratelimit())
2347 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
2348 dev->name, status, length);
2350 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
2351 dev->stats.rx_length_errors++;
2352 if (status & GMR_FS_FRAGMENT)
2353 dev->stats.rx_frame_errors++;
2354 if (status & GMR_FS_CRC_ERR)
2355 dev->stats.rx_crc_errors++;
2360 /* Transmit complete */
2361 static inline void sky2_tx_done(struct net_device *dev, u16 last)
2363 struct sky2_port *sky2 = netdev_priv(dev);
2365 if (netif_running(dev))
2366 sky2_tx_complete(sky2, last);
2369 static inline void sky2_skb_rx(const struct sky2_port *sky2,
2370 u32 status, struct sk_buff *skb)
2372 #ifdef SKY2_VLAN_TAG_USED
2373 u16 vlan_tag = be16_to_cpu(sky2->rx_tag);
2374 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2375 if (skb->ip_summed == CHECKSUM_NONE)
2376 vlan_hwaccel_receive_skb(skb, sky2->vlgrp, vlan_tag);
2378 vlan_gro_receive(&sky2->hw->napi, sky2->vlgrp,
2383 if (skb->ip_summed == CHECKSUM_NONE)
2384 netif_receive_skb(skb);
2386 napi_gro_receive(&sky2->hw->napi, skb);
2389 static inline void sky2_rx_done(struct sky2_hw *hw, unsigned port,
2390 unsigned packets, unsigned bytes)
2393 struct net_device *dev = hw->dev[port];
2395 dev->stats.rx_packets += packets;
2396 dev->stats.rx_bytes += bytes;
2397 dev->last_rx = jiffies;
2398 sky2_rx_update(netdev_priv(dev), rxqaddr[port]);
2402 /* Process status response ring */
2403 static int sky2_status_intr(struct sky2_hw *hw, int to_do, u16 idx)
2406 unsigned int total_bytes[2] = { 0 };
2407 unsigned int total_packets[2] = { 0 };
2411 struct sky2_port *sky2;
2412 struct sky2_status_le *le = hw->st_le + hw->st_idx;
2414 struct net_device *dev;
2415 struct sk_buff *skb;
2418 u8 opcode = le->opcode;
2420 if (!(opcode & HW_OWNER))
2423 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
2425 port = le->css & CSS_LINK_BIT;
2426 dev = hw->dev[port];
2427 sky2 = netdev_priv(dev);
2428 length = le16_to_cpu(le->length);
2429 status = le32_to_cpu(le->status);
2432 switch (opcode & ~HW_OWNER) {
2434 total_packets[port]++;
2435 total_bytes[port] += length;
2436 skb = sky2_receive(dev, length, status);
2437 if (unlikely(!skb)) {
2438 dev->stats.rx_dropped++;
2442 /* This chip reports checksum status differently */
2443 if (hw->flags & SKY2_HW_NEW_LE) {
2444 if ((sky2->flags & SKY2_FLAG_RX_CHECKSUM) &&
2445 (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) &&
2446 (le->css & CSS_TCPUDPCSOK))
2447 skb->ip_summed = CHECKSUM_UNNECESSARY;
2449 skb->ip_summed = CHECKSUM_NONE;
2452 skb->protocol = eth_type_trans(skb, dev);
2454 sky2_skb_rx(sky2, status, skb);
2456 /* Stop after net poll weight */
2457 if (++work_done >= to_do)
2461 #ifdef SKY2_VLAN_TAG_USED
2463 sky2->rx_tag = length;
2467 sky2->rx_tag = length;
2471 if (!(sky2->flags & SKY2_FLAG_RX_CHECKSUM))
2474 /* If this happens then driver assuming wrong format */
2475 if (unlikely(hw->flags & SKY2_HW_NEW_LE)) {
2476 if (net_ratelimit())
2477 printk(KERN_NOTICE "%s: unexpected"
2478 " checksum status\n",
2483 /* Both checksum counters are programmed to start at
2484 * the same offset, so unless there is a problem they
2485 * should match. This failure is an early indication that
2486 * hardware receive checksumming won't work.
2488 if (likely(status >> 16 == (status & 0xffff))) {
2489 skb = sky2->rx_ring[sky2->rx_next].skb;
2490 skb->ip_summed = CHECKSUM_COMPLETE;
2491 skb->csum = le16_to_cpu(status);
2493 printk(KERN_NOTICE PFX "%s: hardware receive "
2494 "checksum problem (status = %#x)\n",
2496 sky2->flags &= ~SKY2_FLAG_RX_CHECKSUM;
2498 sky2_write32(sky2->hw,
2499 Q_ADDR(rxqaddr[port], Q_CSR),
2505 /* TX index reports status for both ports */
2506 sky2_tx_done(hw->dev[0], status & 0xfff);
2508 sky2_tx_done(hw->dev[1],
2509 ((status >> 24) & 0xff)
2510 | (u16)(length & 0xf) << 8);
2514 if (net_ratelimit())
2515 printk(KERN_WARNING PFX
2516 "unknown status opcode 0x%x\n", opcode);
2518 } while (hw->st_idx != idx);
2520 /* Fully processed status ring so clear irq */
2521 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2524 sky2_rx_done(hw, 0, total_packets[0], total_bytes[0]);
2525 sky2_rx_done(hw, 1, total_packets[1], total_bytes[1]);
2530 static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2532 struct net_device *dev = hw->dev[port];
2534 if (net_ratelimit())
2535 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2538 if (status & Y2_IS_PAR_RD1) {
2539 if (net_ratelimit())
2540 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2543 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2546 if (status & Y2_IS_PAR_WR1) {
2547 if (net_ratelimit())
2548 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2551 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2554 if (status & Y2_IS_PAR_MAC1) {
2555 if (net_ratelimit())
2556 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
2557 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2560 if (status & Y2_IS_PAR_RX1) {
2561 if (net_ratelimit())
2562 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
2563 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2566 if (status & Y2_IS_TCP_TXA1) {
2567 if (net_ratelimit())
2568 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2570 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2574 static void sky2_hw_intr(struct sky2_hw *hw)
2576 struct pci_dev *pdev = hw->pdev;
2577 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2578 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2582 if (status & Y2_IS_TIST_OV)
2583 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2585 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
2588 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2589 pci_err = sky2_pci_read16(hw, PCI_STATUS);
2590 if (net_ratelimit())
2591 dev_err(&pdev->dev, "PCI hardware error (0x%x)\n",
2594 sky2_pci_write16(hw, PCI_STATUS,
2595 pci_err | PCI_STATUS_ERROR_BITS);
2596 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2599 if (status & Y2_IS_PCI_EXP) {
2600 /* PCI-Express uncorrectable Error occurred */
2603 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2604 err = sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2605 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2607 if (net_ratelimit())
2608 dev_err(&pdev->dev, "PCI Express error (0x%x)\n", err);
2610 sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2611 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2614 if (status & Y2_HWE_L1_MASK)
2615 sky2_hw_error(hw, 0, status);
2617 if (status & Y2_HWE_L1_MASK)
2618 sky2_hw_error(hw, 1, status);
2621 static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2623 struct net_device *dev = hw->dev[port];
2624 struct sky2_port *sky2 = netdev_priv(dev);
2625 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2627 if (netif_msg_intr(sky2))
2628 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2631 if (status & GM_IS_RX_CO_OV)
2632 gma_read16(hw, port, GM_RX_IRQ_SRC);
2634 if (status & GM_IS_TX_CO_OV)
2635 gma_read16(hw, port, GM_TX_IRQ_SRC);
2637 if (status & GM_IS_RX_FF_OR) {
2638 ++dev->stats.rx_fifo_errors;
2639 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2642 if (status & GM_IS_TX_FF_UR) {
2643 ++dev->stats.tx_fifo_errors;
2644 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2648 /* This should never happen it is a bug. */
2649 static void sky2_le_error(struct sky2_hw *hw, unsigned port, u16 q)
2651 struct net_device *dev = hw->dev[port];
2652 u16 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
2654 dev_err(&hw->pdev->dev, PFX
2655 "%s: descriptor error q=%#x get=%u put=%u\n",
2656 dev->name, (unsigned) q, (unsigned) idx,
2657 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
2659 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
2662 static int sky2_rx_hung(struct net_device *dev)
2664 struct sky2_port *sky2 = netdev_priv(dev);
2665 struct sky2_hw *hw = sky2->hw;
2666 unsigned port = sky2->port;
2667 unsigned rxq = rxqaddr[port];
2668 u32 mac_rp = sky2_read32(hw, SK_REG(port, RX_GMF_RP));
2669 u8 mac_lev = sky2_read8(hw, SK_REG(port, RX_GMF_RLEV));
2670 u8 fifo_rp = sky2_read8(hw, Q_ADDR(rxq, Q_RP));
2671 u8 fifo_lev = sky2_read8(hw, Q_ADDR(rxq, Q_RL));
2673 /* If idle and MAC or PCI is stuck */
2674 if (sky2->check.last == dev->last_rx &&
2675 ((mac_rp == sky2->check.mac_rp &&
2676 mac_lev != 0 && mac_lev >= sky2->check.mac_lev) ||
2677 /* Check if the PCI RX hang */
2678 (fifo_rp == sky2->check.fifo_rp &&
2679 fifo_lev != 0 && fifo_lev >= sky2->check.fifo_lev))) {
2680 printk(KERN_DEBUG PFX "%s: hung mac %d:%d fifo %d (%d:%d)\n",
2681 dev->name, mac_lev, mac_rp, fifo_lev, fifo_rp,
2682 sky2_read8(hw, Q_ADDR(rxq, Q_WP)));
2685 sky2->check.last = dev->last_rx;
2686 sky2->check.mac_rp = mac_rp;
2687 sky2->check.mac_lev = mac_lev;
2688 sky2->check.fifo_rp = fifo_rp;
2689 sky2->check.fifo_lev = fifo_lev;
2694 static void sky2_watchdog(unsigned long arg)
2696 struct sky2_hw *hw = (struct sky2_hw *) arg;
2698 /* Check for lost IRQ once a second */
2699 if (sky2_read32(hw, B0_ISRC)) {
2700 napi_schedule(&hw->napi);
2704 for (i = 0; i < hw->ports; i++) {
2705 struct net_device *dev = hw->dev[i];
2706 if (!netif_running(dev))
2710 /* For chips with Rx FIFO, check if stuck */
2711 if ((hw->flags & SKY2_HW_RAM_BUFFER) &&
2712 sky2_rx_hung(dev)) {
2713 pr_info(PFX "%s: receiver hang detected\n",
2715 schedule_work(&hw->restart_work);
2724 mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ));
2727 /* Hardware/software error handling */
2728 static void sky2_err_intr(struct sky2_hw *hw, u32 status)
2730 if (net_ratelimit())
2731 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
2733 if (status & Y2_IS_HW_ERR)
2736 if (status & Y2_IS_IRQ_MAC1)
2737 sky2_mac_intr(hw, 0);
2739 if (status & Y2_IS_IRQ_MAC2)
2740 sky2_mac_intr(hw, 1);
2742 if (status & Y2_IS_CHK_RX1)
2743 sky2_le_error(hw, 0, Q_R1);
2745 if (status & Y2_IS_CHK_RX2)
2746 sky2_le_error(hw, 1, Q_R2);
2748 if (status & Y2_IS_CHK_TXA1)
2749 sky2_le_error(hw, 0, Q_XA1);
2751 if (status & Y2_IS_CHK_TXA2)
2752 sky2_le_error(hw, 1, Q_XA2);
2755 static int sky2_poll(struct napi_struct *napi, int work_limit)
2757 struct sky2_hw *hw = container_of(napi, struct sky2_hw, napi);
2758 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
2762 if (unlikely(status & Y2_IS_ERROR))
2763 sky2_err_intr(hw, status);
2765 if (status & Y2_IS_IRQ_PHY1)
2766 sky2_phy_intr(hw, 0);
2768 if (status & Y2_IS_IRQ_PHY2)
2769 sky2_phy_intr(hw, 1);
2771 while ((idx = sky2_read16(hw, STAT_PUT_IDX)) != hw->st_idx) {
2772 work_done += sky2_status_intr(hw, work_limit - work_done, idx);
2774 if (work_done >= work_limit)
2778 napi_complete(napi);
2779 sky2_read32(hw, B0_Y2_SP_LISR);
2785 static irqreturn_t sky2_intr(int irq, void *dev_id)
2787 struct sky2_hw *hw = dev_id;
2790 /* Reading this mask interrupts as side effect */
2791 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2792 if (status == 0 || status == ~0)
2795 prefetch(&hw->st_le[hw->st_idx]);
2797 napi_schedule(&hw->napi);
2802 #ifdef CONFIG_NET_POLL_CONTROLLER
2803 static void sky2_netpoll(struct net_device *dev)
2805 struct sky2_port *sky2 = netdev_priv(dev);
2807 napi_schedule(&sky2->hw->napi);
2811 /* Chip internal frequency for clock calculations */
2812 static u32 sky2_mhz(const struct sky2_hw *hw)
2814 switch (hw->chip_id) {
2815 case CHIP_ID_YUKON_EC:
2816 case CHIP_ID_YUKON_EC_U:
2817 case CHIP_ID_YUKON_EX:
2818 case CHIP_ID_YUKON_SUPR:
2819 case CHIP_ID_YUKON_UL_2:
2822 case CHIP_ID_YUKON_FE:
2825 case CHIP_ID_YUKON_FE_P:
2828 case CHIP_ID_YUKON_XL:
2836 static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
2838 return sky2_mhz(hw) * us;
2841 static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
2843 return clk / sky2_mhz(hw);
2847 static int __devinit sky2_init(struct sky2_hw *hw)
2851 /* Enable all clocks and check for bad PCI access */
2852 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
2854 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2856 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2857 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2859 switch(hw->chip_id) {
2860 case CHIP_ID_YUKON_XL:
2861 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_NEWER_PHY;
2864 case CHIP_ID_YUKON_EC_U:
2865 hw->flags = SKY2_HW_GIGABIT
2867 | SKY2_HW_ADV_POWER_CTL;
2870 case CHIP_ID_YUKON_EX:
2871 hw->flags = SKY2_HW_GIGABIT
2874 | SKY2_HW_ADV_POWER_CTL;
2876 /* New transmit checksum */
2877 if (hw->chip_rev != CHIP_REV_YU_EX_B0)
2878 hw->flags |= SKY2_HW_AUTO_TX_SUM;
2881 case CHIP_ID_YUKON_EC:
2882 /* This rev is really old, and requires untested workarounds */
2883 if (hw->chip_rev == CHIP_REV_YU_EC_A1) {
2884 dev_err(&hw->pdev->dev, "unsupported revision Yukon-EC rev A1\n");
2887 hw->flags = SKY2_HW_GIGABIT;
2890 case CHIP_ID_YUKON_FE:
2893 case CHIP_ID_YUKON_FE_P:
2894 hw->flags = SKY2_HW_NEWER_PHY
2896 | SKY2_HW_AUTO_TX_SUM
2897 | SKY2_HW_ADV_POWER_CTL;
2900 case CHIP_ID_YUKON_SUPR:
2901 hw->flags = SKY2_HW_GIGABIT
2904 | SKY2_HW_AUTO_TX_SUM
2905 | SKY2_HW_ADV_POWER_CTL;
2908 case CHIP_ID_YUKON_UL_2:
2909 hw->flags = SKY2_HW_GIGABIT
2910 | SKY2_HW_ADV_POWER_CTL;
2914 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
2919 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
2920 if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P')
2921 hw->flags |= SKY2_HW_FIBRE_PHY;
2924 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2925 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2926 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2933 static void sky2_reset(struct sky2_hw *hw)
2935 struct pci_dev *pdev = hw->pdev;
2938 u32 hwe_mask = Y2_HWE_ALL_MASK;
2941 if (hw->chip_id == CHIP_ID_YUKON_EX) {
2942 status = sky2_read16(hw, HCU_CCSR);
2943 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
2944 HCU_CCSR_UC_STATE_MSK);
2945 sky2_write16(hw, HCU_CCSR, status);
2947 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2948 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
2951 sky2_write8(hw, B0_CTST, CS_RST_SET);
2952 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2954 /* allow writes to PCI config */
2955 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2957 /* clear PCI errors, if any */
2958 status = sky2_pci_read16(hw, PCI_STATUS);
2959 status |= PCI_STATUS_ERROR_BITS;
2960 sky2_pci_write16(hw, PCI_STATUS, status);
2962 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2964 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
2966 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2969 /* If error bit is stuck on ignore it */
2970 if (sky2_read32(hw, B0_HWE_ISRC) & Y2_IS_PCI_EXP)
2971 dev_info(&pdev->dev, "ignoring stuck error report bit\n");
2973 hwe_mask |= Y2_IS_PCI_EXP;
2977 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2979 for (i = 0; i < hw->ports; i++) {
2980 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2981 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2983 if (hw->chip_id == CHIP_ID_YUKON_EX ||
2984 hw->chip_id == CHIP_ID_YUKON_SUPR)
2985 sky2_write16(hw, SK_REG(i, GMAC_CTRL),
2986 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON
2990 /* Clear I2C IRQ noise */
2991 sky2_write32(hw, B2_I2C_IRQ, 1);
2993 /* turn off hardware timer (unused) */
2994 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2995 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
2997 /* Turn off descriptor polling */
2998 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
3000 /* Turn off receive timestamp */
3001 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
3002 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
3004 /* enable the Tx Arbiters */
3005 for (i = 0; i < hw->ports; i++)
3006 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
3008 /* Initialize ram interface */
3009 for (i = 0; i < hw->ports; i++) {
3010 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
3012 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
3013 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
3014 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
3015 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
3016 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
3017 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
3018 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
3019 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
3020 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
3021 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
3022 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
3023 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
3026 sky2_write32(hw, B0_HWE_IMSK, hwe_mask);
3028 for (i = 0; i < hw->ports; i++)
3029 sky2_gmac_reset(hw, i);
3031 memset(hw->st_le, 0, STATUS_LE_BYTES);
3034 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
3035 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
3037 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
3038 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
3040 /* Set the list last index */
3041 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
3043 sky2_write16(hw, STAT_TX_IDX_TH, 10);
3044 sky2_write8(hw, STAT_FIFO_WM, 16);
3046 /* set Status-FIFO ISR watermark */
3047 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
3048 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
3050 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
3052 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
3053 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
3054 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
3056 /* enable status unit */
3057 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
3059 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3060 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3061 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3064 /* Take device down (offline).
3065 * Equivalent to doing dev_stop() but this does not
3066 * inform upper layers of the transistion.
3068 static void sky2_detach(struct net_device *dev)
3070 if (netif_running(dev)) {
3071 netif_device_detach(dev); /* stop txq */
3076 /* Bring device back after doing sky2_detach */
3077 static int sky2_reattach(struct net_device *dev)
3081 if (netif_running(dev)) {
3084 printk(KERN_INFO PFX "%s: could not restart %d\n",
3088 netif_device_attach(dev);
3089 sky2_set_multicast(dev);
3096 static void sky2_restart(struct work_struct *work)
3098 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
3102 for (i = 0; i < hw->ports; i++)
3103 sky2_detach(hw->dev[i]);
3105 napi_disable(&hw->napi);
3106 sky2_write32(hw, B0_IMSK, 0);
3108 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
3109 napi_enable(&hw->napi);
3111 for (i = 0; i < hw->ports; i++)
3112 sky2_reattach(hw->dev[i]);
3117 static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
3119 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
3122 static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3124 const struct sky2_port *sky2 = netdev_priv(dev);
3126 wol->supported = sky2_wol_supported(sky2->hw);
3127 wol->wolopts = sky2->wol;
3130 static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3132 struct sky2_port *sky2 = netdev_priv(dev);
3133 struct sky2_hw *hw = sky2->hw;
3135 if ((wol->wolopts & ~sky2_wol_supported(sky2->hw))
3136 || !device_can_wakeup(&hw->pdev->dev))
3139 sky2->wol = wol->wolopts;
3141 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3142 hw->chip_id == CHIP_ID_YUKON_EX ||
3143 hw->chip_id == CHIP_ID_YUKON_FE_P)
3144 sky2_write32(hw, B0_CTST, sky2->wol
3145 ? Y2_HW_WOL_ON : Y2_HW_WOL_OFF);
3147 device_set_wakeup_enable(&hw->pdev->dev, sky2->wol);
3149 if (!netif_running(dev))
3150 sky2_wol_init(sky2);
3154 static u32 sky2_supported_modes(const struct sky2_hw *hw)
3156 if (sky2_is_copper(hw)) {
3157 u32 modes = SUPPORTED_10baseT_Half
3158 | SUPPORTED_10baseT_Full
3159 | SUPPORTED_100baseT_Half
3160 | SUPPORTED_100baseT_Full
3161 | SUPPORTED_Autoneg | SUPPORTED_TP;
3163 if (hw->flags & SKY2_HW_GIGABIT)
3164 modes |= SUPPORTED_1000baseT_Half
3165 | SUPPORTED_1000baseT_Full;
3168 return SUPPORTED_1000baseT_Half
3169 | SUPPORTED_1000baseT_Full
3174 static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3176 struct sky2_port *sky2 = netdev_priv(dev);
3177 struct sky2_hw *hw = sky2->hw;
3179 ecmd->transceiver = XCVR_INTERNAL;
3180 ecmd->supported = sky2_supported_modes(hw);
3181 ecmd->phy_address = PHY_ADDR_MARV;
3182 if (sky2_is_copper(hw)) {
3183 ecmd->port = PORT_TP;
3184 ecmd->speed = sky2->speed;
3186 ecmd->speed = SPEED_1000;
3187 ecmd->port = PORT_FIBRE;
3190 ecmd->advertising = sky2->advertising;
3191 ecmd->autoneg = (sky2->flags & SKY2_FLAG_AUTO_SPEED)
3192 ? AUTONEG_ENABLE : AUTONEG_DISABLE;
3193 ecmd->duplex = sky2->duplex;
3197 static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3199 struct sky2_port *sky2 = netdev_priv(dev);
3200 const struct sky2_hw *hw = sky2->hw;
3201 u32 supported = sky2_supported_modes(hw);
3203 if (ecmd->autoneg == AUTONEG_ENABLE) {
3204 sky2->flags |= SKY2_FLAG_AUTO_SPEED;
3205 ecmd->advertising = supported;
3211 switch (ecmd->speed) {
3213 if (ecmd->duplex == DUPLEX_FULL)
3214 setting = SUPPORTED_1000baseT_Full;
3215 else if (ecmd->duplex == DUPLEX_HALF)
3216 setting = SUPPORTED_1000baseT_Half;
3221 if (ecmd->duplex == DUPLEX_FULL)
3222 setting = SUPPORTED_100baseT_Full;
3223 else if (ecmd->duplex == DUPLEX_HALF)
3224 setting = SUPPORTED_100baseT_Half;
3230 if (ecmd->duplex == DUPLEX_FULL)
3231 setting = SUPPORTED_10baseT_Full;
3232 else if (ecmd->duplex == DUPLEX_HALF)
3233 setting = SUPPORTED_10baseT_Half;
3241 if ((setting & supported) == 0)
3244 sky2->speed = ecmd->speed;
3245 sky2->duplex = ecmd->duplex;
3246 sky2->flags &= ~SKY2_FLAG_AUTO_SPEED;
3249 sky2->advertising = ecmd->advertising;
3251 if (netif_running(dev)) {
3252 sky2_phy_reinit(sky2);
3253 sky2_set_multicast(dev);
3259 static void sky2_get_drvinfo(struct net_device *dev,
3260 struct ethtool_drvinfo *info)
3262 struct sky2_port *sky2 = netdev_priv(dev);
3264 strcpy(info->driver, DRV_NAME);
3265 strcpy(info->version, DRV_VERSION);
3266 strcpy(info->fw_version, "N/A");
3267 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
3270 static const struct sky2_stat {
3271 char name[ETH_GSTRING_LEN];
3274 { "tx_bytes", GM_TXO_OK_HI },
3275 { "rx_bytes", GM_RXO_OK_HI },
3276 { "tx_broadcast", GM_TXF_BC_OK },
3277 { "rx_broadcast", GM_RXF_BC_OK },
3278 { "tx_multicast", GM_TXF_MC_OK },
3279 { "rx_multicast", GM_RXF_MC_OK },
3280 { "tx_unicast", GM_TXF_UC_OK },
3281 { "rx_unicast", GM_RXF_UC_OK },
3282 { "tx_mac_pause", GM_TXF_MPAUSE },
3283 { "rx_mac_pause", GM_RXF_MPAUSE },
3284 { "collisions", GM_TXF_COL },
3285 { "late_collision",GM_TXF_LAT_COL },
3286 { "aborted", GM_TXF_ABO_COL },
3287 { "single_collisions", GM_TXF_SNG_COL },
3288 { "multi_collisions", GM_TXF_MUL_COL },
3290 { "rx_short", GM_RXF_SHT },
3291 { "rx_runt", GM_RXE_FRAG },
3292 { "rx_64_byte_packets", GM_RXF_64B },
3293 { "rx_65_to_127_byte_packets", GM_RXF_127B },
3294 { "rx_128_to_255_byte_packets", GM_RXF_255B },
3295 { "rx_256_to_511_byte_packets", GM_RXF_511B },
3296 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
3297 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
3298 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
3299 { "rx_too_long", GM_RXF_LNG_ERR },
3300 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
3301 { "rx_jabber", GM_RXF_JAB_PKT },
3302 { "rx_fcs_error", GM_RXF_FCS_ERR },
3304 { "tx_64_byte_packets", GM_TXF_64B },
3305 { "tx_65_to_127_byte_packets", GM_TXF_127B },
3306 { "tx_128_to_255_byte_packets", GM_TXF_255B },
3307 { "tx_256_to_511_byte_packets", GM_TXF_511B },
3308 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
3309 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
3310 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
3311 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
3314 static u32 sky2_get_rx_csum(struct net_device *dev)
3316 struct sky2_port *sky2 = netdev_priv(dev);
3318 return !!(sky2->flags & SKY2_FLAG_RX_CHECKSUM);
3321 static int sky2_set_rx_csum(struct net_device *dev, u32 data)
3323 struct sky2_port *sky2 = netdev_priv(dev);
3326 sky2->flags |= SKY2_FLAG_RX_CHECKSUM;
3328 sky2->flags &= ~SKY2_FLAG_RX_CHECKSUM;
3330 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
3331 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
3336 static u32 sky2_get_msglevel(struct net_device *netdev)
3338 struct sky2_port *sky2 = netdev_priv(netdev);
3339 return sky2->msg_enable;
3342 static int sky2_nway_reset(struct net_device *dev)
3344 struct sky2_port *sky2 = netdev_priv(dev);
3346 if (!netif_running(dev) || !(sky2->flags & SKY2_FLAG_AUTO_SPEED))
3349 sky2_phy_reinit(sky2);
3350 sky2_set_multicast(dev);
3355 static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
3357 struct sky2_hw *hw = sky2->hw;
3358 unsigned port = sky2->port;
3361 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
3362 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
3363 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
3364 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
3366 for (i = 2; i < count; i++)
3367 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
3370 static void sky2_set_msglevel(struct net_device *netdev, u32 value)
3372 struct sky2_port *sky2 = netdev_priv(netdev);
3373 sky2->msg_enable = value;
3376 static int sky2_get_sset_count(struct net_device *dev, int sset)
3380 return ARRAY_SIZE(sky2_stats);
3386 static void sky2_get_ethtool_stats(struct net_device *dev,
3387 struct ethtool_stats *stats, u64 * data)
3389 struct sky2_port *sky2 = netdev_priv(dev);
3391 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
3394 static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
3398 switch (stringset) {
3400 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
3401 memcpy(data + i * ETH_GSTRING_LEN,
3402 sky2_stats[i].name, ETH_GSTRING_LEN);
3407 static int sky2_set_mac_address(struct net_device *dev, void *p)
3409 struct sky2_port *sky2 = netdev_priv(dev);
3410 struct sky2_hw *hw = sky2->hw;
3411 unsigned port = sky2->port;
3412 const struct sockaddr *addr = p;
3414 if (!is_valid_ether_addr(addr->sa_data))
3415 return -EADDRNOTAVAIL;
3417 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
3418 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
3419 dev->dev_addr, ETH_ALEN);
3420 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
3421 dev->dev_addr, ETH_ALEN);
3423 /* virtual address for data */
3424 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3426 /* physical address: used for pause frames */
3427 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
3432 static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
3436 bit = ether_crc(ETH_ALEN, addr) & 63;
3437 filter[bit >> 3] |= 1 << (bit & 7);
3440 static void sky2_set_multicast(struct net_device *dev)
3442 struct sky2_port *sky2 = netdev_priv(dev);
3443 struct sky2_hw *hw = sky2->hw;
3444 unsigned port = sky2->port;
3445 struct dev_mc_list *list = dev->mc_list;
3449 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
3451 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
3452 memset(filter, 0, sizeof(filter));
3454 reg = gma_read16(hw, port, GM_RX_CTRL);
3455 reg |= GM_RXCR_UCF_ENA;
3457 if (dev->flags & IFF_PROMISC) /* promiscuous */
3458 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
3459 else if (dev->flags & IFF_ALLMULTI)
3460 memset(filter, 0xff, sizeof(filter));
3461 else if (dev->mc_count == 0 && !rx_pause)
3462 reg &= ~GM_RXCR_MCF_ENA;
3465 reg |= GM_RXCR_MCF_ENA;
3468 sky2_add_filter(filter, pause_mc_addr);
3470 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
3471 sky2_add_filter(filter, list->dmi_addr);
3474 gma_write16(hw, port, GM_MC_ADDR_H1,
3475 (u16) filter[0] | ((u16) filter[1] << 8));
3476 gma_write16(hw, port, GM_MC_ADDR_H2,
3477 (u16) filter[2] | ((u16) filter[3] << 8));
3478 gma_write16(hw, port, GM_MC_ADDR_H3,
3479 (u16) filter[4] | ((u16) filter[5] << 8));
3480 gma_write16(hw, port, GM_MC_ADDR_H4,
3481 (u16) filter[6] | ((u16) filter[7] << 8));
3483 gma_write16(hw, port, GM_RX_CTRL, reg);
3486 /* Can have one global because blinking is controlled by
3487 * ethtool and that is always under RTNL mutex
3489 static void sky2_led(struct sky2_port *sky2, enum led_mode mode)
3491 struct sky2_hw *hw = sky2->hw;
3492 unsigned port = sky2->port;
3494 spin_lock_bh(&sky2->phy_lock);
3495 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3496 hw->chip_id == CHIP_ID_YUKON_EX ||
3497 hw->chip_id == CHIP_ID_YUKON_SUPR) {
3499 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3500 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3504 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3505 PHY_M_LEDC_LOS_CTRL(8) |
3506 PHY_M_LEDC_INIT_CTRL(8) |
3507 PHY_M_LEDC_STA1_CTRL(8) |
3508 PHY_M_LEDC_STA0_CTRL(8));
3511 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3512 PHY_M_LEDC_LOS_CTRL(9) |
3513 PHY_M_LEDC_INIT_CTRL(9) |
3514 PHY_M_LEDC_STA1_CTRL(9) |
3515 PHY_M_LEDC_STA0_CTRL(9));
3518 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3519 PHY_M_LEDC_LOS_CTRL(0xa) |
3520 PHY_M_LEDC_INIT_CTRL(0xa) |
3521 PHY_M_LEDC_STA1_CTRL(0xa) |
3522 PHY_M_LEDC_STA0_CTRL(0xa));
3525 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3526 PHY_M_LEDC_LOS_CTRL(1) |
3527 PHY_M_LEDC_INIT_CTRL(8) |
3528 PHY_M_LEDC_STA1_CTRL(7) |
3529 PHY_M_LEDC_STA0_CTRL(7));
3532 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3534 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
3535 PHY_M_LED_MO_DUP(mode) |
3536 PHY_M_LED_MO_10(mode) |
3537 PHY_M_LED_MO_100(mode) |
3538 PHY_M_LED_MO_1000(mode) |
3539 PHY_M_LED_MO_RX(mode) |
3540 PHY_M_LED_MO_TX(mode));
3542 spin_unlock_bh(&sky2->phy_lock);
3545 /* blink LED's for finding board */
3546 static int sky2_phys_id(struct net_device *dev, u32 data)
3548 struct sky2_port *sky2 = netdev_priv(dev);
3554 for (i = 0; i < data; i++) {
3555 sky2_led(sky2, MO_LED_ON);
3556 if (msleep_interruptible(500))
3558 sky2_led(sky2, MO_LED_OFF);
3559 if (msleep_interruptible(500))
3562 sky2_led(sky2, MO_LED_NORM);
3567 static void sky2_get_pauseparam(struct net_device *dev,
3568 struct ethtool_pauseparam *ecmd)
3570 struct sky2_port *sky2 = netdev_priv(dev);
3572 switch (sky2->flow_mode) {
3574 ecmd->tx_pause = ecmd->rx_pause = 0;
3577 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3580 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3583 ecmd->tx_pause = ecmd->rx_pause = 1;
3586 ecmd->autoneg = (sky2->flags & SKY2_FLAG_AUTO_PAUSE)
3587 ? AUTONEG_ENABLE : AUTONEG_DISABLE;
3590 static int sky2_set_pauseparam(struct net_device *dev,
3591 struct ethtool_pauseparam *ecmd)
3593 struct sky2_port *sky2 = netdev_priv(dev);
3595 if (ecmd->autoneg == AUTONEG_ENABLE)
3596 sky2->flags |= SKY2_FLAG_AUTO_PAUSE;
3598 sky2->flags &= ~SKY2_FLAG_AUTO_PAUSE;
3600 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
3602 if (netif_running(dev))
3603 sky2_phy_reinit(sky2);
3608 static int sky2_get_coalesce(struct net_device *dev,
3609 struct ethtool_coalesce *ecmd)
3611 struct sky2_port *sky2 = netdev_priv(dev);
3612 struct sky2_hw *hw = sky2->hw;
3614 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3615 ecmd->tx_coalesce_usecs = 0;
3617 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3618 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3620 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3622 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3623 ecmd->rx_coalesce_usecs = 0;
3625 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3626 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3628 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3630 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3631 ecmd->rx_coalesce_usecs_irq = 0;
3633 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3634 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3637 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3642 /* Note: this affect both ports */
3643 static int sky2_set_coalesce(struct net_device *dev,
3644 struct ethtool_coalesce *ecmd)
3646 struct sky2_port *sky2 = netdev_priv(dev);
3647 struct sky2_hw *hw = sky2->hw;
3648 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
3650 if (ecmd->tx_coalesce_usecs > tmax ||
3651 ecmd->rx_coalesce_usecs > tmax ||
3652 ecmd->rx_coalesce_usecs_irq > tmax)
3655 if (ecmd->tx_max_coalesced_frames >= sky2->tx_ring_size-1)
3657 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
3659 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
3662 if (ecmd->tx_coalesce_usecs == 0)
3663 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3665 sky2_write32(hw, STAT_TX_TIMER_INI,
3666 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3667 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3669 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3671 if (ecmd->rx_coalesce_usecs == 0)
3672 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3674 sky2_write32(hw, STAT_LEV_TIMER_INI,
3675 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3676 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3678 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3680 if (ecmd->rx_coalesce_usecs_irq == 0)
3681 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3683 sky2_write32(hw, STAT_ISR_TIMER_INI,
3684 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3685 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3687 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3691 static void sky2_get_ringparam(struct net_device *dev,
3692 struct ethtool_ringparam *ering)
3694 struct sky2_port *sky2 = netdev_priv(dev);
3696 ering->rx_max_pending = RX_MAX_PENDING;
3697 ering->rx_mini_max_pending = 0;
3698 ering->rx_jumbo_max_pending = 0;
3699 ering->tx_max_pending = TX_MAX_PENDING;
3701 ering->rx_pending = sky2->rx_pending;
3702 ering->rx_mini_pending = 0;
3703 ering->rx_jumbo_pending = 0;
3704 ering->tx_pending = sky2->tx_pending;
3707 static int sky2_set_ringparam(struct net_device *dev,
3708 struct ethtool_ringparam *ering)
3710 struct sky2_port *sky2 = netdev_priv(dev);
3712 if (ering->rx_pending > RX_MAX_PENDING ||
3713 ering->rx_pending < 8 ||
3714 ering->tx_pending < TX_MIN_PENDING ||
3715 ering->tx_pending > TX_MAX_PENDING)
3720 sky2->rx_pending = ering->rx_pending;
3721 sky2->tx_pending = ering->tx_pending;
3722 sky2->tx_ring_size = roundup_pow_of_two(sky2->tx_pending+1);
3724 return sky2_reattach(dev);
3727 static int sky2_get_regs_len(struct net_device *dev)
3733 * Returns copy of control register region
3734 * Note: ethtool_get_regs always provides full size (16k) buffer
3736 static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3739 const struct sky2_port *sky2 = netdev_priv(dev);
3740 const void __iomem *io = sky2->hw->regs;
3745 for (b = 0; b < 128; b++) {
3746 /* This complicated switch statement is to make sure and
3747 * only access regions that are unreserved.
3748 * Some blocks are only valid on dual port cards.
3749 * and block 3 has some special diagnostic registers that
3754 /* skip diagnostic ram region */
3755 memcpy_fromio(p + 0x10, io + 0x10, 128 - 0x10);
3758 /* dual port cards only */
3759 case 5: /* Tx Arbiter 2 */
3761 case 14 ... 15: /* TX2 */
3762 case 17: case 19: /* Ram Buffer 2 */
3763 case 22 ... 23: /* Tx Ram Buffer 2 */
3764 case 25: /* Rx MAC Fifo 1 */
3765 case 27: /* Tx MAC Fifo 2 */
3766 case 31: /* GPHY 2 */
3767 case 40 ... 47: /* Pattern Ram 2 */
3768 case 52: case 54: /* TCP Segmentation 2 */
3769 case 112 ... 116: /* GMAC 2 */
3770 if (sky2->hw->ports == 1)
3773 case 0: /* Control */
3774 case 2: /* Mac address */
3775 case 4: /* Tx Arbiter 1 */
3776 case 7: /* PCI express reg */
3778 case 12 ... 13: /* TX1 */
3779 case 16: case 18:/* Rx Ram Buffer 1 */
3780 case 20 ... 21: /* Tx Ram Buffer 1 */
3781 case 24: /* Rx MAC Fifo 1 */
3782 case 26: /* Tx MAC Fifo 1 */
3783 case 28 ... 29: /* Descriptor and status unit */
3784 case 30: /* GPHY 1*/
3785 case 32 ... 39: /* Pattern Ram 1 */
3786 case 48: case 50: /* TCP Segmentation 1 */
3787 case 56 ... 60: /* PCI space */
3788 case 80 ... 84: /* GMAC 1 */
3789 memcpy_fromio(p, io, 128);
3801 /* In order to do Jumbo packets on these chips, need to turn off the
3802 * transmit store/forward. Therefore checksum offload won't work.
3804 static int no_tx_offload(struct net_device *dev)
3806 const struct sky2_port *sky2 = netdev_priv(dev);
3807 const struct sky2_hw *hw = sky2->hw;
3809 return dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U;
3812 static int sky2_set_tx_csum(struct net_device *dev, u32 data)
3814 if (data && no_tx_offload(dev))
3817 return ethtool_op_set_tx_csum(dev, data);
3821 static int sky2_set_tso(struct net_device *dev, u32 data)
3823 if (data && no_tx_offload(dev))
3826 return ethtool_op_set_tso(dev, data);
3829 static int sky2_get_eeprom_len(struct net_device *dev)
3831 struct sky2_port *sky2 = netdev_priv(dev);
3832 struct sky2_hw *hw = sky2->hw;
3835 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
3836 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
3839 static int sky2_vpd_wait(const struct sky2_hw *hw, int cap, u16 busy)
3841 unsigned long start = jiffies;
3843 while ( (sky2_pci_read16(hw, cap + PCI_VPD_ADDR) & PCI_VPD_ADDR_F) == busy) {
3844 /* Can take up to 10.6 ms for write */
3845 if (time_after(jiffies, start + HZ/4)) {
3846 dev_err(&hw->pdev->dev, PFX "VPD cycle timed out");
3855 static int sky2_vpd_read(struct sky2_hw *hw, int cap, void *data,
3856 u16 offset, size_t length)
3860 while (length > 0) {
3863 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset);
3864 rc = sky2_vpd_wait(hw, cap, 0);
3868 val = sky2_pci_read32(hw, cap + PCI_VPD_DATA);
3870 memcpy(data, &val, min(sizeof(val), length));
3871 offset += sizeof(u32);
3872 data += sizeof(u32);
3873 length -= sizeof(u32);
3879 static int sky2_vpd_write(struct sky2_hw *hw, int cap, const void *data,
3880 u16 offset, unsigned int length)
3885 for (i = 0; i < length; i += sizeof(u32)) {
3886 u32 val = *(u32 *)(data + i);
3888 sky2_pci_write32(hw, cap + PCI_VPD_DATA, val);
3889 sky2_pci_write32(hw, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F);
3891 rc = sky2_vpd_wait(hw, cap, PCI_VPD_ADDR_F);
3898 static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3901 struct sky2_port *sky2 = netdev_priv(dev);
3902 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
3907 eeprom->magic = SKY2_EEPROM_MAGIC;
3909 return sky2_vpd_read(sky2->hw, cap, data, eeprom->offset, eeprom->len);
3912 static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3915 struct sky2_port *sky2 = netdev_priv(dev);
3916 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
3921 if (eeprom->magic != SKY2_EEPROM_MAGIC)
3924 /* Partial writes not supported */
3925 if ((eeprom->offset & 3) || (eeprom->len & 3))
3928 return sky2_vpd_write(sky2->hw, cap, data, eeprom->offset, eeprom->len);
3932 static const struct ethtool_ops sky2_ethtool_ops = {
3933 .get_settings = sky2_get_settings,
3934 .set_settings = sky2_set_settings,
3935 .get_drvinfo = sky2_get_drvinfo,
3936 .get_wol = sky2_get_wol,
3937 .set_wol = sky2_set_wol,
3938 .get_msglevel = sky2_get_msglevel,
3939 .set_msglevel = sky2_set_msglevel,
3940 .nway_reset = sky2_nway_reset,
3941 .get_regs_len = sky2_get_regs_len,
3942 .get_regs = sky2_get_regs,
3943 .get_link = ethtool_op_get_link,
3944 .get_eeprom_len = sky2_get_eeprom_len,
3945 .get_eeprom = sky2_get_eeprom,
3946 .set_eeprom = sky2_set_eeprom,
3947 .set_sg = ethtool_op_set_sg,
3948 .set_tx_csum = sky2_set_tx_csum,
3949 .set_tso = sky2_set_tso,
3950 .get_rx_csum = sky2_get_rx_csum,
3951 .set_rx_csum = sky2_set_rx_csum,
3952 .get_strings = sky2_get_strings,
3953 .get_coalesce = sky2_get_coalesce,
3954 .set_coalesce = sky2_set_coalesce,
3955 .get_ringparam = sky2_get_ringparam,
3956 .set_ringparam = sky2_set_ringparam,
3957 .get_pauseparam = sky2_get_pauseparam,
3958 .set_pauseparam = sky2_set_pauseparam,
3959 .phys_id = sky2_phys_id,
3960 .get_sset_count = sky2_get_sset_count,
3961 .get_ethtool_stats = sky2_get_ethtool_stats,
3964 #ifdef CONFIG_SKY2_DEBUG
3966 static struct dentry *sky2_debug;
3970 * Read and parse the first part of Vital Product Data
3972 #define VPD_SIZE 128
3973 #define VPD_MAGIC 0x82
3975 static const struct vpd_tag {
3979 { "PN", "Part Number" },
3980 { "EC", "Engineering Level" },
3981 { "MN", "Manufacturer" },
3982 { "SN", "Serial Number" },
3983 { "YA", "Asset Tag" },
3984 { "VL", "First Error Log Message" },
3985 { "VF", "Second Error Log Message" },
3986 { "VB", "Boot Agent ROM Configuration" },
3987 { "VE", "EFI UNDI Configuration" },
3990 static void sky2_show_vpd(struct seq_file *seq, struct sky2_hw *hw)
3998 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
3999 vpd_size = 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
4001 seq_printf(seq, "%s Product Data\n", pci_name(hw->pdev));
4002 buf = kmalloc(vpd_size, GFP_KERNEL);
4004 seq_puts(seq, "no memory!\n");
4008 if (pci_read_vpd(hw->pdev, 0, vpd_size, buf) < 0) {
4009 seq_puts(seq, "VPD read failed\n");
4013 if (buf[0] != VPD_MAGIC) {
4014 seq_printf(seq, "VPD tag mismatch: %#x\n", buf[0]);
4018 if (len == 0 || len > vpd_size - 4) {
4019 seq_printf(seq, "Invalid id length: %d\n", len);
4023 seq_printf(seq, "%.*s\n", len, buf + 3);
4026 while (offs < vpd_size - 4) {
4029 if (!memcmp("RW", buf + offs, 2)) /* end marker */
4031 len = buf[offs + 2];
4032 if (offs + len + 3 >= vpd_size)
4035 for (i = 0; i < ARRAY_SIZE(vpd_tags); i++) {
4036 if (!memcmp(vpd_tags[i].tag, buf + offs, 2)) {
4037 seq_printf(seq, " %s: %.*s\n",
4038 vpd_tags[i].label, len, buf + offs + 3);
4048 static int sky2_debug_show(struct seq_file *seq, void *v)
4050 struct net_device *dev = seq->private;
4051 const struct sky2_port *sky2 = netdev_priv(dev);
4052 struct sky2_hw *hw = sky2->hw;
4053 unsigned port = sky2->port;
4057 sky2_show_vpd(seq, hw);
4059 seq_printf(seq, "\nIRQ src=%x mask=%x control=%x\n",
4060 sky2_read32(hw, B0_ISRC),
4061 sky2_read32(hw, B0_IMSK),
4062 sky2_read32(hw, B0_Y2_SP_ICR));
4064 if (!netif_running(dev)) {
4065 seq_printf(seq, "network not running\n");
4069 napi_disable(&hw->napi);
4070 last = sky2_read16(hw, STAT_PUT_IDX);
4072 if (hw->st_idx == last)
4073 seq_puts(seq, "Status ring (empty)\n");
4075 seq_puts(seq, "Status ring\n");
4076 for (idx = hw->st_idx; idx != last && idx < STATUS_RING_SIZE;
4077 idx = RING_NEXT(idx, STATUS_RING_SIZE)) {
4078 const struct sky2_status_le *le = hw->st_le + idx;
4079 seq_printf(seq, "[%d] %#x %d %#x\n",
4080 idx, le->opcode, le->length, le->status);
4082 seq_puts(seq, "\n");
4085 seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n",
4086 sky2->tx_cons, sky2->tx_prod,
4087 sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
4088 sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE)));
4090 /* Dump contents of tx ring */
4092 for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < sky2->tx_ring_size;
4093 idx = RING_NEXT(idx, sky2->tx_ring_size)) {
4094 const struct sky2_tx_le *le = sky2->tx_le + idx;
4095 u32 a = le32_to_cpu(le->addr);
4098 seq_printf(seq, "%u:", idx);
4101 switch(le->opcode & ~HW_OWNER) {
4103 seq_printf(seq, " %#x:", a);
4106 seq_printf(seq, " mtu=%d", a);
4109 seq_printf(seq, " vlan=%d", be16_to_cpu(le->length));
4112 seq_printf(seq, " csum=%#x", a);
4115 seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length));
4118 seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length));
4121 seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length));
4124 seq_printf(seq, " op=%#x,%#x(%d)", le->opcode,
4125 a, le16_to_cpu(le->length));
4128 if (le->ctrl & EOP) {
4129 seq_putc(seq, '\n');
4134 seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n",
4135 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)),
4136 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)),
4137 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX)));
4139 sky2_read32(hw, B0_Y2_SP_LISR);
4140 napi_enable(&hw->napi);
4144 static int sky2_debug_open(struct inode *inode, struct file *file)
4146 return single_open(file, sky2_debug_show, inode->i_private);
4149 static const struct file_operations sky2_debug_fops = {
4150 .owner = THIS_MODULE,
4151 .open = sky2_debug_open,
4153 .llseek = seq_lseek,
4154 .release = single_release,
4158 * Use network device events to create/remove/rename
4159 * debugfs file entries
4161 static int sky2_device_event(struct notifier_block *unused,
4162 unsigned long event, void *ptr)
4164 struct net_device *dev = ptr;
4165 struct sky2_port *sky2 = netdev_priv(dev);
4167 if (dev->netdev_ops->ndo_open != sky2_up || !sky2_debug)
4171 case NETDEV_CHANGENAME:
4172 if (sky2->debugfs) {
4173 sky2->debugfs = debugfs_rename(sky2_debug, sky2->debugfs,
4174 sky2_debug, dev->name);
4178 case NETDEV_GOING_DOWN:
4179 if (sky2->debugfs) {
4180 printk(KERN_DEBUG PFX "%s: remove debugfs\n",
4182 debugfs_remove(sky2->debugfs);
4183 sky2->debugfs = NULL;
4188 sky2->debugfs = debugfs_create_file(dev->name, S_IRUGO,
4191 if (IS_ERR(sky2->debugfs))
4192 sky2->debugfs = NULL;
4198 static struct notifier_block sky2_notifier = {
4199 .notifier_call = sky2_device_event,
4203 static __init void sky2_debug_init(void)
4207 ent = debugfs_create_dir("sky2", NULL);
4208 if (!ent || IS_ERR(ent))
4212 register_netdevice_notifier(&sky2_notifier);
4215 static __exit void sky2_debug_cleanup(void)
4218 unregister_netdevice_notifier(&sky2_notifier);
4219 debugfs_remove(sky2_debug);
4225 #define sky2_debug_init()
4226 #define sky2_debug_cleanup()
4229 /* Two copies of network device operations to handle special case of
4230 not allowing netpoll on second port */
4231 static const struct net_device_ops sky2_netdev_ops[2] = {
4233 .ndo_open = sky2_up,
4234 .ndo_stop = sky2_down,
4235 .ndo_start_xmit = sky2_xmit_frame,
4236 .ndo_do_ioctl = sky2_ioctl,
4237 .ndo_validate_addr = eth_validate_addr,
4238 .ndo_set_mac_address = sky2_set_mac_address,
4239 .ndo_set_multicast_list = sky2_set_multicast,
4240 .ndo_change_mtu = sky2_change_mtu,
4241 .ndo_tx_timeout = sky2_tx_timeout,
4242 #ifdef SKY2_VLAN_TAG_USED
4243 .ndo_vlan_rx_register = sky2_vlan_rx_register,
4245 #ifdef CONFIG_NET_POLL_CONTROLLER
4246 .ndo_poll_controller = sky2_netpoll,
4250 .ndo_open = sky2_up,
4251 .ndo_stop = sky2_down,
4252 .ndo_start_xmit = sky2_xmit_frame,
4253 .ndo_do_ioctl = sky2_ioctl,
4254 .ndo_validate_addr = eth_validate_addr,
4255 .ndo_set_mac_address = sky2_set_mac_address,
4256 .ndo_set_multicast_list = sky2_set_multicast,
4257 .ndo_change_mtu = sky2_change_mtu,
4258 .ndo_tx_timeout = sky2_tx_timeout,
4259 #ifdef SKY2_VLAN_TAG_USED
4260 .ndo_vlan_rx_register = sky2_vlan_rx_register,
4265 /* Initialize network device */
4266 static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
4268 int highmem, int wol)
4270 struct sky2_port *sky2;
4271 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
4274 dev_err(&hw->pdev->dev, "etherdev alloc failed\n");
4278 SET_NETDEV_DEV(dev, &hw->pdev->dev);
4279 dev->irq = hw->pdev->irq;
4280 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
4281 dev->watchdog_timeo = TX_WATCHDOG;
4282 dev->netdev_ops = &sky2_netdev_ops[port];
4284 sky2 = netdev_priv(dev);
4287 sky2->msg_enable = netif_msg_init(debug, default_msg);
4289 /* Auto speed and flow control */
4290 sky2->flags = SKY2_FLAG_AUTO_SPEED | SKY2_FLAG_AUTO_PAUSE;
4291 if (hw->chip_id != CHIP_ID_YUKON_XL)
4292 sky2->flags |= SKY2_FLAG_RX_CHECKSUM;
4294 sky2->flow_mode = FC_BOTH;
4298 sky2->advertising = sky2_supported_modes(hw);
4301 spin_lock_init(&sky2->phy_lock);
4303 sky2->tx_pending = TX_DEF_PENDING;
4304 sky2->tx_ring_size = roundup_pow_of_two(TX_DEF_PENDING+1);
4305 sky2->rx_pending = RX_DEF_PENDING;
4307 hw->dev[port] = dev;
4311 dev->features |= NETIF_F_TSO | NETIF_F_IP_CSUM | NETIF_F_SG;
4313 dev->features |= NETIF_F_HIGHDMA;
4315 #ifdef SKY2_VLAN_TAG_USED
4316 /* The workaround for FE+ status conflicts with VLAN tag detection. */
4317 if (!(sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
4318 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0)) {
4319 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
4323 /* read the mac address */
4324 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
4325 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
4330 static void __devinit sky2_show_addr(struct net_device *dev)
4332 const struct sky2_port *sky2 = netdev_priv(dev);
4334 if (netif_msg_probe(sky2))
4335 printk(KERN_INFO PFX "%s: addr %pM\n",
4336 dev->name, dev->dev_addr);
4339 /* Handle software interrupt used during MSI test */
4340 static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
4342 struct sky2_hw *hw = dev_id;
4343 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
4348 if (status & Y2_IS_IRQ_SW) {
4349 hw->flags |= SKY2_HW_USE_MSI;
4350 wake_up(&hw->msi_wait);
4351 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4353 sky2_write32(hw, B0_Y2_SP_ICR, 2);
4358 /* Test interrupt path by forcing a a software IRQ */
4359 static int __devinit sky2_test_msi(struct sky2_hw *hw)
4361 struct pci_dev *pdev = hw->pdev;
4364 init_waitqueue_head (&hw->msi_wait);
4366 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
4368 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
4370 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
4374 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
4375 sky2_read8(hw, B0_CTST);
4377 wait_event_timeout(hw->msi_wait, (hw->flags & SKY2_HW_USE_MSI), HZ/10);
4379 if (!(hw->flags & SKY2_HW_USE_MSI)) {
4380 /* MSI test failed, go back to INTx mode */
4381 dev_info(&pdev->dev, "No interrupt generated using MSI, "
4382 "switching to INTx mode.\n");
4385 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4388 sky2_write32(hw, B0_IMSK, 0);
4389 sky2_read32(hw, B0_IMSK);
4391 free_irq(pdev->irq, hw);
4396 /* This driver supports yukon2 chipset only */
4397 static const char *sky2_name(u8 chipid, char *buf, int sz)
4399 const char *name[] = {
4401 "EC Ultra", /* 0xb4 */
4402 "Extreme", /* 0xb5 */
4406 "Supreme", /* 0xb9 */
4410 if (chipid >= CHIP_ID_YUKON_XL && chipid < CHIP_ID_YUKON_UL_2)
4411 strncpy(buf, name[chipid - CHIP_ID_YUKON_XL], sz);
4413 snprintf(buf, sz, "(chip %#x)", chipid);
4417 static int __devinit sky2_probe(struct pci_dev *pdev,
4418 const struct pci_device_id *ent)
4420 struct net_device *dev;
4422 int err, using_dac = 0, wol_default;
4426 err = pci_enable_device(pdev);
4428 dev_err(&pdev->dev, "cannot enable PCI device\n");
4432 /* Get configuration information
4433 * Note: only regular PCI config access once to test for HW issues
4434 * other PCI access through shared memory for speed and to
4435 * avoid MMCONFIG problems.
4437 err = pci_read_config_dword(pdev, PCI_DEV_REG2, ®);
4439 dev_err(&pdev->dev, "PCI read config failed\n");
4444 dev_err(&pdev->dev, "PCI configuration read error\n");
4448 err = pci_request_regions(pdev, DRV_NAME);
4450 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
4451 goto err_out_disable;
4454 pci_set_master(pdev);
4456 if (sizeof(dma_addr_t) > sizeof(u32) &&
4457 !(err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)))) {
4459 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
4461 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
4462 "for consistent allocations\n");
4463 goto err_out_free_regions;
4466 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
4468 dev_err(&pdev->dev, "no usable DMA configuration\n");
4469 goto err_out_free_regions;
4475 /* The sk98lin vendor driver uses hardware byte swapping but
4476 * this driver uses software swapping.
4478 reg &= ~PCI_REV_DESC;
4479 err = pci_write_config_dword(pdev,PCI_DEV_REG2, reg);
4481 dev_err(&pdev->dev, "PCI write config failed\n");
4482 goto err_out_free_regions;
4486 wol_default = device_may_wakeup(&pdev->dev) ? WAKE_MAGIC : 0;
4489 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
4491 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
4492 goto err_out_free_regions;
4497 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
4499 dev_err(&pdev->dev, "cannot map device registers\n");
4500 goto err_out_free_hw;
4503 /* ring for status responses */
4504 hw->st_le = pci_alloc_consistent(pdev, STATUS_LE_BYTES, &hw->st_dma);
4506 goto err_out_iounmap;
4508 err = sky2_init(hw);
4510 goto err_out_iounmap;
4512 dev_info(&pdev->dev, "Yukon-2 %s chip revision %d\n",
4513 sky2_name(hw->chip_id, buf1, sizeof(buf1)), hw->chip_rev);
4517 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
4520 goto err_out_free_pci;
4523 if (!disable_msi && pci_enable_msi(pdev) == 0) {
4524 err = sky2_test_msi(hw);
4525 if (err == -EOPNOTSUPP)
4526 pci_disable_msi(pdev);
4528 goto err_out_free_netdev;
4531 err = register_netdev(dev);
4533 dev_err(&pdev->dev, "cannot register net device\n");
4534 goto err_out_free_netdev;
4537 netif_napi_add(dev, &hw->napi, sky2_poll, NAPI_WEIGHT);
4539 err = request_irq(pdev->irq, sky2_intr,
4540 (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED,
4543 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
4544 goto err_out_unregister;
4546 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
4547 napi_enable(&hw->napi);
4549 sky2_show_addr(dev);
4551 if (hw->ports > 1) {
4552 struct net_device *dev1;
4554 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
4556 dev_warn(&pdev->dev, "allocation for second device failed\n");
4557 else if ((err = register_netdev(dev1))) {
4558 dev_warn(&pdev->dev,
4559 "register of second port failed (%d)\n", err);
4563 sky2_show_addr(dev1);
4566 setup_timer(&hw->watchdog_timer, sky2_watchdog, (unsigned long) hw);
4567 INIT_WORK(&hw->restart_work, sky2_restart);
4569 pci_set_drvdata(pdev, hw);
4574 if (hw->flags & SKY2_HW_USE_MSI)
4575 pci_disable_msi(pdev);
4576 unregister_netdev(dev);
4577 err_out_free_netdev:
4580 sky2_write8(hw, B0_CTST, CS_RST_SET);
4581 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
4586 err_out_free_regions:
4587 pci_release_regions(pdev);
4589 pci_disable_device(pdev);
4591 pci_set_drvdata(pdev, NULL);
4595 static void __devexit sky2_remove(struct pci_dev *pdev)
4597 struct sky2_hw *hw = pci_get_drvdata(pdev);
4603 del_timer_sync(&hw->watchdog_timer);
4604 cancel_work_sync(&hw->restart_work);
4606 for (i = hw->ports-1; i >= 0; --i)
4607 unregister_netdev(hw->dev[i]);
4609 sky2_write32(hw, B0_IMSK, 0);
4613 sky2_write8(hw, B0_CTST, CS_RST_SET);
4614 sky2_read8(hw, B0_CTST);
4616 free_irq(pdev->irq, hw);
4617 if (hw->flags & SKY2_HW_USE_MSI)
4618 pci_disable_msi(pdev);
4619 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
4620 pci_release_regions(pdev);
4621 pci_disable_device(pdev);
4623 for (i = hw->ports-1; i >= 0; --i)
4624 free_netdev(hw->dev[i]);
4629 pci_set_drvdata(pdev, NULL);
4633 static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
4635 struct sky2_hw *hw = pci_get_drvdata(pdev);
4641 del_timer_sync(&hw->watchdog_timer);
4642 cancel_work_sync(&hw->restart_work);
4645 for (i = 0; i < hw->ports; i++) {
4646 struct net_device *dev = hw->dev[i];
4647 struct sky2_port *sky2 = netdev_priv(dev);
4652 sky2_wol_init(sky2);
4657 sky2_write32(hw, B0_IMSK, 0);
4658 napi_disable(&hw->napi);
4662 pci_save_state(pdev);
4663 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
4664 pci_set_power_state(pdev, pci_choose_state(pdev, state));
4669 static int sky2_resume(struct pci_dev *pdev)
4671 struct sky2_hw *hw = pci_get_drvdata(pdev);
4677 err = pci_set_power_state(pdev, PCI_D0);
4681 err = pci_restore_state(pdev);
4685 pci_enable_wake(pdev, PCI_D0, 0);
4687 /* Re-enable all clocks */
4688 if (hw->chip_id == CHIP_ID_YUKON_EX ||
4689 hw->chip_id == CHIP_ID_YUKON_EC_U ||
4690 hw->chip_id == CHIP_ID_YUKON_FE_P)
4691 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
4694 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
4695 napi_enable(&hw->napi);
4698 for (i = 0; i < hw->ports; i++) {
4699 err = sky2_reattach(hw->dev[i]);
4709 dev_err(&pdev->dev, "resume failed (%d)\n", err);
4710 pci_disable_device(pdev);
4715 static void sky2_shutdown(struct pci_dev *pdev)
4717 struct sky2_hw *hw = pci_get_drvdata(pdev);
4724 del_timer_sync(&hw->watchdog_timer);
4726 for (i = 0; i < hw->ports; i++) {
4727 struct net_device *dev = hw->dev[i];
4728 struct sky2_port *sky2 = netdev_priv(dev);
4732 sky2_wol_init(sky2);
4740 pci_enable_wake(pdev, PCI_D3hot, wol);
4741 pci_enable_wake(pdev, PCI_D3cold, wol);
4743 pci_disable_device(pdev);
4744 pci_set_power_state(pdev, PCI_D3hot);
4747 static struct pci_driver sky2_driver = {
4749 .id_table = sky2_id_table,
4750 .probe = sky2_probe,
4751 .remove = __devexit_p(sky2_remove),
4753 .suspend = sky2_suspend,
4754 .resume = sky2_resume,
4756 .shutdown = sky2_shutdown,
4759 static int __init sky2_init_module(void)
4761 pr_info(PFX "driver version " DRV_VERSION "\n");
4764 return pci_register_driver(&sky2_driver);
4767 static void __exit sky2_cleanup_module(void)
4769 pci_unregister_driver(&sky2_driver);
4770 sky2_debug_cleanup();
4773 module_init(sky2_init_module);
4774 module_exit(sky2_cleanup_module);
4776 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
4777 MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
4778 MODULE_LICENSE("GPL");
4779 MODULE_VERSION(DRV_VERSION);