2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26 #include <linux/config.h>
27 #include <linux/crc32.h>
28 #include <linux/kernel.h>
29 #include <linux/version.h>
30 #include <linux/module.h>
31 #include <linux/netdevice.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/etherdevice.h>
34 #include <linux/ethtool.h>
35 #include <linux/pci.h>
37 #include <linux/tcp.h>
39 #include <linux/delay.h>
40 #include <linux/workqueue.h>
41 #include <linux/if_vlan.h>
42 #include <linux/prefetch.h>
43 #include <linux/mii.h>
47 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
48 #define SKY2_VLAN_TAG_USED 1
53 #define DRV_NAME "sky2"
54 #define DRV_VERSION "0.15"
55 #define PFX DRV_NAME " "
58 * The Yukon II chipset takes 64 bit command blocks (called list elements)
59 * that are organized into three (receive, transmit, status) different rings
60 * similar to Tigon3. A transmit can require several elements;
61 * a receive requires one (or two if using 64 bit dma).
64 #define RX_LE_SIZE 512
65 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
66 #define RX_MAX_PENDING (RX_LE_SIZE/2 - 2)
67 #define RX_DEF_PENDING RX_MAX_PENDING
68 #define RX_SKB_ALIGN 8
70 #define TX_RING_SIZE 512
71 #define TX_DEF_PENDING (TX_RING_SIZE - 1)
72 #define TX_MIN_PENDING 64
73 #define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
75 #define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
76 #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
77 #define ETH_JUMBO_MTU 9000
78 #define TX_WATCHDOG (5 * HZ)
79 #define NAPI_WEIGHT 64
80 #define PHY_RETRIES 1000
82 static const u32 default_msg =
83 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
84 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
85 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
87 static int debug = -1; /* defaults above */
88 module_param(debug, int, 0);
89 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
91 static int copybreak __read_mostly = 256;
92 module_param(copybreak, int, 0);
93 MODULE_PARM_DESC(copybreak, "Receive copy threshold");
95 static const struct pci_device_id sky2_id_table[] = {
96 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) },
97 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) },
98 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) },
99 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b01) },
100 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) },
101 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) },
102 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) },
103 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) },
104 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) },
105 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) },
106 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) },
107 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) },
108 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) },
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) },
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) },
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) },
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) },
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) },
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) },
118 MODULE_DEVICE_TABLE(pci, sky2_id_table);
120 /* Avoid conditionals by using array */
121 static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
122 static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
124 /* This driver supports yukon2 chipset only */
125 static const char *yukon2_name[] = {
127 "EC Ultra", /* 0xb4 */
128 "UNKNOWN", /* 0xb5 */
133 /* Access to external PHY */
134 static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
138 gma_write16(hw, port, GM_SMI_DATA, val);
139 gma_write16(hw, port, GM_SMI_CTRL,
140 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
142 for (i = 0; i < PHY_RETRIES; i++) {
143 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
148 printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
152 static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
156 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
157 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
159 for (i = 0; i < PHY_RETRIES; i++) {
160 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) {
161 *val = gma_read16(hw, port, GM_SMI_DATA);
171 static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
175 if (__gm_phy_read(hw, port, reg, &v) != 0)
176 printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
180 static int sky2_set_power_state(struct sky2_hw *hw, pci_power_t state)
187 pr_debug("sky2_set_power_state %d\n", state);
188 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
190 power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_PMC);
191 vaux = (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
192 (power_control & PCI_PM_CAP_PME_D3cold);
194 power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_CTRL);
196 power_control |= PCI_PM_CTRL_PME_STATUS;
197 power_control &= ~(PCI_PM_CTRL_STATE_MASK);
201 /* switch power to VCC (WA for VAUX problem) */
202 sky2_write8(hw, B0_POWER_CTRL,
203 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
205 /* disable Core Clock Division, */
206 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
208 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
209 /* enable bits are inverted */
210 sky2_write8(hw, B2_Y2_CLK_GATE,
211 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
212 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
213 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
215 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
217 /* Turn off phy power saving */
218 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
219 reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
221 /* looks like this XL is back asswards .. */
222 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) {
223 reg1 |= PCI_Y2_PHY1_COMA;
225 reg1 |= PCI_Y2_PHY2_COMA;
228 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
229 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
230 reg1 = sky2_pci_read32(hw, PCI_DEV_REG4);
231 reg1 &= P_ASPM_CONTROL_MSK;
232 sky2_pci_write32(hw, PCI_DEV_REG4, reg1);
233 sky2_pci_write32(hw, PCI_DEV_REG5, 0);
236 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
242 /* Turn on phy power saving */
243 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
244 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
245 reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
247 reg1 |= (PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
248 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
250 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
251 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
253 /* enable bits are inverted */
254 sky2_write8(hw, B2_Y2_CLK_GATE,
255 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
256 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
257 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
259 /* switch power to VAUX */
260 if (vaux && state != PCI_D3cold)
261 sky2_write8(hw, B0_POWER_CTRL,
262 (PC_VAUX_ENA | PC_VCC_ENA |
263 PC_VAUX_ON | PC_VCC_OFF));
266 printk(KERN_ERR PFX "Unknown power state %d\n", state);
270 sky2_pci_write16(hw, hw->pm_cap + PCI_PM_CTRL, power_control);
271 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
275 static void sky2_phy_reset(struct sky2_hw *hw, unsigned port)
279 /* disable all GMAC IRQ's */
280 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
281 /* disable PHY IRQs */
282 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
284 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
285 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
286 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
287 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
289 reg = gma_read16(hw, port, GM_RX_CTRL);
290 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
291 gma_write16(hw, port, GM_RX_CTRL, reg);
294 static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
296 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
297 u16 ctrl, ct1000, adv, pg, ledctrl, ledover;
299 if (sky2->autoneg == AUTONEG_ENABLE && hw->chip_id != CHIP_ID_YUKON_XL) {
300 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
302 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
304 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
306 if (hw->chip_id == CHIP_ID_YUKON_EC)
307 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
309 ectrl |= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3);
311 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
314 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
316 if (hw->chip_id == CHIP_ID_YUKON_FE) {
317 /* enable automatic crossover */
318 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
320 /* disable energy detect */
321 ctrl &= ~PHY_M_PC_EN_DET_MSK;
323 /* enable automatic crossover */
324 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
326 if (sky2->autoneg == AUTONEG_ENABLE &&
327 hw->chip_id == CHIP_ID_YUKON_XL) {
328 ctrl &= ~PHY_M_PC_DSC_MSK;
329 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
332 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
334 /* workaround for deviation #4.88 (CRC errors) */
335 /* disable Automatic Crossover */
337 ctrl &= ~PHY_M_PC_MDIX_MSK;
338 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
340 if (hw->chip_id == CHIP_ID_YUKON_XL) {
341 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
342 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
343 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
344 ctrl &= ~PHY_M_MAC_MD_MSK;
345 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
346 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
348 /* select page 1 to access Fiber registers */
349 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
353 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
354 if (sky2->autoneg == AUTONEG_DISABLE)
359 ctrl |= PHY_CT_RESET;
360 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
366 if (sky2->autoneg == AUTONEG_ENABLE) {
368 if (sky2->advertising & ADVERTISED_1000baseT_Full)
369 ct1000 |= PHY_M_1000C_AFD;
370 if (sky2->advertising & ADVERTISED_1000baseT_Half)
371 ct1000 |= PHY_M_1000C_AHD;
372 if (sky2->advertising & ADVERTISED_100baseT_Full)
373 adv |= PHY_M_AN_100_FD;
374 if (sky2->advertising & ADVERTISED_100baseT_Half)
375 adv |= PHY_M_AN_100_HD;
376 if (sky2->advertising & ADVERTISED_10baseT_Full)
377 adv |= PHY_M_AN_10_FD;
378 if (sky2->advertising & ADVERTISED_10baseT_Half)
379 adv |= PHY_M_AN_10_HD;
380 } else /* special defines for FIBER (88E1011S only) */
381 adv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD;
383 /* Set Flow-control capabilities */
384 if (sky2->tx_pause && sky2->rx_pause)
385 adv |= PHY_AN_PAUSE_CAP; /* symmetric */
386 else if (sky2->rx_pause && !sky2->tx_pause)
387 adv |= PHY_AN_PAUSE_ASYM | PHY_AN_PAUSE_CAP;
388 else if (!sky2->rx_pause && sky2->tx_pause)
389 adv |= PHY_AN_PAUSE_ASYM; /* local */
391 /* Restart Auto-negotiation */
392 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
394 /* forced speed/duplex settings */
395 ct1000 = PHY_M_1000C_MSE;
397 if (sky2->duplex == DUPLEX_FULL)
398 ctrl |= PHY_CT_DUP_MD;
400 switch (sky2->speed) {
402 ctrl |= PHY_CT_SP1000;
405 ctrl |= PHY_CT_SP100;
409 ctrl |= PHY_CT_RESET;
412 if (hw->chip_id != CHIP_ID_YUKON_FE)
413 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
415 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
416 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
418 /* Setup Phy LED's */
419 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
422 switch (hw->chip_id) {
423 case CHIP_ID_YUKON_FE:
424 /* on 88E3082 these bits are at 11..9 (shifted left) */
425 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
427 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
429 /* delete ACT LED control bits */
430 ctrl &= ~PHY_M_FELP_LED1_MSK;
431 /* change ACT LED control to blink mode */
432 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
433 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
436 case CHIP_ID_YUKON_XL:
437 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
439 /* select page 3 to access LED control register */
440 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
442 /* set LED Function Control register */
443 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
444 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
445 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
446 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
448 /* set Polarity Control register */
449 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
450 (PHY_M_POLC_LS1_P_MIX(4) |
451 PHY_M_POLC_IS0_P_MIX(4) |
452 PHY_M_POLC_LOS_CTRL(2) |
453 PHY_M_POLC_INIT_CTRL(2) |
454 PHY_M_POLC_STA1_CTRL(2) |
455 PHY_M_POLC_STA0_CTRL(2)));
457 /* restore page register */
458 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
462 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
463 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
464 /* turn off the Rx LED (LED_RX) */
465 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
468 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev >= 2) {
469 /* apply fixes in PHY AFE */
470 gm_phy_write(hw, port, 22, 255);
471 /* increase differential signal amplitude in 10BASE-T */
472 gm_phy_write(hw, port, 24, 0xaa99);
473 gm_phy_write(hw, port, 23, 0x2011);
475 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
476 gm_phy_write(hw, port, 24, 0xa204);
477 gm_phy_write(hw, port, 23, 0x2002);
479 /* set page register to 0 */
480 gm_phy_write(hw, port, 22, 0);
482 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
484 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
485 /* turn on 100 Mbps LED (LED_LINK100) */
486 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
490 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
493 /* Enable phy interrupt on auto-negotiation complete (or link up) */
494 if (sky2->autoneg == AUTONEG_ENABLE)
495 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
497 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
500 /* Force a renegotiation */
501 static void sky2_phy_reinit(struct sky2_port *sky2)
503 down(&sky2->phy_sema);
504 sky2_phy_init(sky2->hw, sky2->port);
508 static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
510 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
513 const u8 *addr = hw->dev[port]->dev_addr;
515 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
516 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR|GPC_ENA_PAUSE);
518 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
520 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
521 /* WA DEV_472 -- looks like crossed wires on port 2 */
522 /* clear GMAC 1 Control reset */
523 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
525 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
526 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
527 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
528 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
529 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
532 if (sky2->autoneg == AUTONEG_DISABLE) {
533 reg = gma_read16(hw, port, GM_GP_CTRL);
534 reg |= GM_GPCR_AU_ALL_DIS;
535 gma_write16(hw, port, GM_GP_CTRL, reg);
536 gma_read16(hw, port, GM_GP_CTRL);
538 switch (sky2->speed) {
540 reg &= ~GM_GPCR_SPEED_100;
541 reg |= GM_GPCR_SPEED_1000;
544 reg &= ~GM_GPCR_SPEED_1000;
545 reg |= GM_GPCR_SPEED_100;
548 reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
552 if (sky2->duplex == DUPLEX_FULL)
553 reg |= GM_GPCR_DUP_FULL;
555 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
557 if (!sky2->tx_pause && !sky2->rx_pause) {
558 sky2_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
560 GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
561 } else if (sky2->tx_pause && !sky2->rx_pause) {
562 /* disable Rx flow-control */
563 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
566 gma_write16(hw, port, GM_GP_CTRL, reg);
568 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
570 down(&sky2->phy_sema);
571 sky2_phy_init(hw, port);
575 reg = gma_read16(hw, port, GM_PHY_ADDR);
576 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
578 for (i = 0; i < GM_MIB_CNT_SIZE; i++)
579 gma_read16(hw, port, GM_MIB_CNT_BASE + 8 * i);
580 gma_write16(hw, port, GM_PHY_ADDR, reg);
582 /* transmit control */
583 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
585 /* receive control reg: unicast + multicast + no FCS */
586 gma_write16(hw, port, GM_RX_CTRL,
587 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
589 /* transmit flow control */
590 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
592 /* transmit parameter */
593 gma_write16(hw, port, GM_TX_PARAM,
594 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
595 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
596 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
597 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
599 /* serial mode register */
600 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
601 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
603 if (hw->dev[port]->mtu > ETH_DATA_LEN)
604 reg |= GM_SMOD_JUMBO_ENA;
606 gma_write16(hw, port, GM_SERIAL_MODE, reg);
608 /* virtual address for data */
609 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
611 /* physical address: used for pause frames */
612 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
614 /* ignore counter overflows */
615 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
616 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
617 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
619 /* Configure Rx MAC FIFO */
620 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
621 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
622 GMF_OPER_ON | GMF_RX_F_FL_ON);
624 /* Flush Rx MAC FIFO on any flow control or error */
625 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
627 /* Set threshold to 0xa (64 bytes)
628 * ASF disabled so no need to do WA dev #4.30
630 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF);
632 /* Configure Tx MAC FIFO */
633 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
634 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
636 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
637 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
638 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
639 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
640 /* set Tx GMAC FIFO Almost Empty Threshold */
641 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR), 0x180);
642 /* Disable Store & Forward mode for TX */
643 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
649 /* Assign Ram Buffer allocation.
650 * start and end are in units of 4k bytes
651 * ram registers are in units of 64bit words
653 static void sky2_ramset(struct sky2_hw *hw, u16 q, u8 startk, u8 endk)
657 start = startk * 4096/8;
658 end = (endk * 4096/8) - 1;
660 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
661 sky2_write32(hw, RB_ADDR(q, RB_START), start);
662 sky2_write32(hw, RB_ADDR(q, RB_END), end);
663 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
664 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
666 if (q == Q_R1 || q == Q_R2) {
667 u32 space = (endk - startk) * 4096/8;
668 u32 tp = space - space/4;
670 /* On receive queue's set the thresholds
671 * give receiver priority when > 3/4 full
672 * send pause when down to 2K
674 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
675 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
678 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
679 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
681 /* Enable store & forward on Tx queue's because
682 * Tx FIFO is only 1K on Yukon
684 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
687 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
688 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
691 /* Setup Bus Memory Interface */
692 static void sky2_qset(struct sky2_hw *hw, u16 q)
694 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
695 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
696 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
697 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
700 /* Setup prefetch unit registers. This is the interface between
701 * hardware and driver list elements
703 static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
706 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
707 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
708 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
709 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
710 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
711 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
713 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
716 static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
718 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
720 sky2->tx_prod = (sky2->tx_prod + 1) % TX_RING_SIZE;
724 /* Update chip's next pointer */
725 static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
728 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
733 static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
735 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
736 sky2->rx_put = (sky2->rx_put + 1) % RX_LE_SIZE;
740 /* Return high part of DMA address (could be 32 or 64 bit) */
741 static inline u32 high32(dma_addr_t a)
743 return sizeof(a) > sizeof(u32) ? (a >> 16) >> 16 : 0;
746 /* Build description to hardware about buffer */
747 static void sky2_rx_add(struct sky2_port *sky2, dma_addr_t map)
749 struct sky2_rx_le *le;
750 u32 hi = high32(map);
751 u16 len = sky2->rx_bufsize;
753 if (sky2->rx_addr64 != hi) {
754 le = sky2_next_rx(sky2);
755 le->addr = cpu_to_le32(hi);
757 le->opcode = OP_ADDR64 | HW_OWNER;
758 sky2->rx_addr64 = high32(map + len);
761 le = sky2_next_rx(sky2);
762 le->addr = cpu_to_le32((u32) map);
763 le->length = cpu_to_le16(len);
765 le->opcode = OP_PACKET | HW_OWNER;
769 /* Tell chip where to start receive checksum.
770 * Actually has two checksums, but set both same to avoid possible byte
773 static void rx_set_checksum(struct sky2_port *sky2)
775 struct sky2_rx_le *le;
777 le = sky2_next_rx(sky2);
778 le->addr = (ETH_HLEN << 16) | ETH_HLEN;
780 le->opcode = OP_TCPSTART | HW_OWNER;
782 sky2_write32(sky2->hw,
783 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
784 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
789 * The RX Stop command will not work for Yukon-2 if the BMU does not
790 * reach the end of packet and since we can't make sure that we have
791 * incoming data, we must reset the BMU while it is not doing a DMA
792 * transfer. Since it is possible that the RX path is still active,
793 * the RX RAM buffer will be stopped first, so any possible incoming
794 * data will not trigger a DMA. After the RAM buffer is stopped, the
795 * BMU is polled until any DMA in progress is ended and only then it
798 static void sky2_rx_stop(struct sky2_port *sky2)
800 struct sky2_hw *hw = sky2->hw;
801 unsigned rxq = rxqaddr[sky2->port];
804 /* disable the RAM Buffer receive queue */
805 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
807 for (i = 0; i < 0xffff; i++)
808 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
809 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
812 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
815 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
817 /* reset the Rx prefetch unit */
818 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
821 /* Clean out receive buffer area, assumes receiver hardware stopped */
822 static void sky2_rx_clean(struct sky2_port *sky2)
826 memset(sky2->rx_le, 0, RX_LE_BYTES);
827 for (i = 0; i < sky2->rx_pending; i++) {
828 struct ring_info *re = sky2->rx_ring + i;
831 pci_unmap_single(sky2->hw->pdev,
832 re->mapaddr, sky2->rx_bufsize,
840 /* Basic MII support */
841 static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
843 struct mii_ioctl_data *data = if_mii(ifr);
844 struct sky2_port *sky2 = netdev_priv(dev);
845 struct sky2_hw *hw = sky2->hw;
846 int err = -EOPNOTSUPP;
848 if (!netif_running(dev))
849 return -ENODEV; /* Phy still in reset */
853 data->phy_id = PHY_ADDR_MARV;
859 down(&sky2->phy_sema);
860 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
868 if (!capable(CAP_NET_ADMIN))
871 down(&sky2->phy_sema);
872 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
880 #ifdef SKY2_VLAN_TAG_USED
881 static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
883 struct sky2_port *sky2 = netdev_priv(dev);
884 struct sky2_hw *hw = sky2->hw;
885 u16 port = sky2->port;
887 spin_lock_bh(&sky2->tx_lock);
889 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_ON);
890 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_ON);
893 spin_unlock_bh(&sky2->tx_lock);
896 static void sky2_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
898 struct sky2_port *sky2 = netdev_priv(dev);
899 struct sky2_hw *hw = sky2->hw;
900 u16 port = sky2->port;
902 spin_lock_bh(&sky2->tx_lock);
904 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_OFF);
905 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_OFF);
907 sky2->vlgrp->vlan_devices[vid] = NULL;
909 spin_unlock_bh(&sky2->tx_lock);
914 * It appears the hardware has a bug in the FIFO logic that
915 * cause it to hang if the FIFO gets overrun and the receive buffer
916 * is not aligned. ALso alloc_skb() won't align properly if slab
917 * debugging is enabled.
919 static inline struct sk_buff *sky2_alloc_skb(unsigned int size, gfp_t gfp_mask)
923 skb = alloc_skb(size + RX_SKB_ALIGN, gfp_mask);
925 unsigned long p = (unsigned long) skb->data;
927 ((p + RX_SKB_ALIGN - 1) & ~(RX_SKB_ALIGN - 1)) - p);
934 * Allocate and setup receiver buffer pool.
935 * In case of 64 bit dma, there are 2X as many list elements
936 * available as ring entries
937 * and need to reserve one list element so we don't wrap around.
939 static int sky2_rx_start(struct sky2_port *sky2)
941 struct sky2_hw *hw = sky2->hw;
942 unsigned rxq = rxqaddr[sky2->port];
945 sky2->rx_put = sky2->rx_next = 0;
948 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev >= 2) {
949 /* MAC Rx RAM Read is controlled by hardware */
950 sky2_write32(hw, Q_ADDR(rxq, Q_F), F_M_RX_RAM_DIS);
953 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
955 rx_set_checksum(sky2);
956 for (i = 0; i < sky2->rx_pending; i++) {
957 struct ring_info *re = sky2->rx_ring + i;
959 re->skb = sky2_alloc_skb(sky2->rx_bufsize, GFP_KERNEL);
963 re->mapaddr = pci_map_single(hw->pdev, re->skb->data,
964 sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
965 sky2_rx_add(sky2, re->mapaddr);
968 /* Truncate oversize frames */
969 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), sky2->rx_bufsize - 8);
970 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
972 /* Tell chip about available buffers */
973 sky2_write16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX), sky2->rx_put);
980 /* Bring up network interface. */
981 static int sky2_up(struct net_device *dev)
983 struct sky2_port *sky2 = netdev_priv(dev);
984 struct sky2_hw *hw = sky2->hw;
985 unsigned port = sky2->port;
986 u32 ramsize, rxspace;
989 if (netif_msg_ifup(sky2))
990 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
992 /* must be power of 2 */
993 sky2->tx_le = pci_alloc_consistent(hw->pdev,
995 sizeof(struct sky2_tx_le),
1000 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
1004 sky2->tx_prod = sky2->tx_cons = 0;
1006 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1010 memset(sky2->rx_le, 0, RX_LE_BYTES);
1012 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct ring_info),
1017 sky2_mac_init(hw, port);
1019 /* Determine available ram buffer space (in 4K blocks).
1020 * Note: not sure about the FE setting below yet
1022 if (hw->chip_id == CHIP_ID_YUKON_FE)
1025 ramsize = sky2_read8(hw, B2_E_0);
1027 /* Give transmitter one third (rounded up) */
1028 rxspace = ramsize - (ramsize + 2) / 3;
1030 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1031 sky2_ramset(hw, txqaddr[port], rxspace, ramsize);
1033 /* Make sure SyncQ is disabled */
1034 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1037 sky2_qset(hw, txqaddr[port]);
1039 /* Set almost empty threshold */
1040 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev == 1)
1041 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), 0x1a0);
1043 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1046 err = sky2_rx_start(sky2);
1050 /* Enable interrupts from phy/mac for port */
1051 spin_lock_irq(&hw->hw_lock);
1052 hw->intr_mask |= (port == 0) ? Y2_IS_PORT_1 : Y2_IS_PORT_2;
1053 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1054 spin_unlock_irq(&hw->hw_lock);
1059 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1060 sky2->rx_le, sky2->rx_le_map);
1064 pci_free_consistent(hw->pdev,
1065 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1066 sky2->tx_le, sky2->tx_le_map);
1069 kfree(sky2->tx_ring);
1070 kfree(sky2->rx_ring);
1072 sky2->tx_ring = NULL;
1073 sky2->rx_ring = NULL;
1077 /* Modular subtraction in ring */
1078 static inline int tx_dist(unsigned tail, unsigned head)
1080 return (head - tail) % TX_RING_SIZE;
1083 /* Number of list elements available for next tx */
1084 static inline int tx_avail(const struct sky2_port *sky2)
1086 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
1089 /* Estimate of number of transmit list elements required */
1090 static unsigned tx_le_req(const struct sk_buff *skb)
1094 count = sizeof(dma_addr_t) / sizeof(u32);
1095 count += skb_shinfo(skb)->nr_frags * count;
1097 if (skb_shinfo(skb)->tso_size)
1100 if (skb->ip_summed == CHECKSUM_HW)
1107 * Put one packet in ring for transmit.
1108 * A single packet can generate multiple list elements, and
1109 * the number of ring elements will probably be less than the number
1110 * of list elements used.
1112 * No BH disabling for tx_lock here (like tg3)
1114 static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1116 struct sky2_port *sky2 = netdev_priv(dev);
1117 struct sky2_hw *hw = sky2->hw;
1118 struct sky2_tx_le *le = NULL;
1119 struct tx_ring_info *re;
1127 /* No BH disabling for tx_lock here. We are running in BH disabled
1128 * context and TX reclaim runs via poll inside of a software
1129 * interrupt, and no related locks in IRQ processing.
1131 if (!spin_trylock(&sky2->tx_lock))
1132 return NETDEV_TX_LOCKED;
1134 if (unlikely(tx_avail(sky2) < tx_le_req(skb))) {
1135 /* There is a known but harmless race with lockless tx
1136 * and netif_stop_queue.
1138 if (!netif_queue_stopped(dev)) {
1139 netif_stop_queue(dev);
1140 if (net_ratelimit())
1141 printk(KERN_WARNING PFX "%s: ring full when queue awake!\n",
1144 spin_unlock(&sky2->tx_lock);
1146 return NETDEV_TX_BUSY;
1149 if (unlikely(netif_msg_tx_queued(sky2)))
1150 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1151 dev->name, sky2->tx_prod, skb->len);
1153 len = skb_headlen(skb);
1154 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
1155 addr64 = high32(mapping);
1157 re = sky2->tx_ring + sky2->tx_prod;
1159 /* Send high bits if changed or crosses boundary */
1160 if (addr64 != sky2->tx_addr64 || high32(mapping + len) != sky2->tx_addr64) {
1161 le = get_tx_le(sky2);
1162 le->tx.addr = cpu_to_le32(addr64);
1164 le->opcode = OP_ADDR64 | HW_OWNER;
1165 sky2->tx_addr64 = high32(mapping + len);
1168 /* Check for TCP Segmentation Offload */
1169 mss = skb_shinfo(skb)->tso_size;
1171 /* just drop the packet if non-linear expansion fails */
1172 if (skb_header_cloned(skb) &&
1173 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
1174 dev_kfree_skb_any(skb);
1178 mss += ((skb->h.th->doff - 5) * 4); /* TCP options */
1179 mss += (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
1183 if (mss != sky2->tx_last_mss) {
1184 le = get_tx_le(sky2);
1185 le->tx.tso.size = cpu_to_le16(mss);
1186 le->tx.tso.rsvd = 0;
1187 le->opcode = OP_LRGLEN | HW_OWNER;
1189 sky2->tx_last_mss = mss;
1193 #ifdef SKY2_VLAN_TAG_USED
1194 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1195 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1197 le = get_tx_le(sky2);
1199 le->opcode = OP_VLAN|HW_OWNER;
1202 le->opcode |= OP_VLAN;
1203 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1208 /* Handle TCP checksum offload */
1209 if (skb->ip_summed == CHECKSUM_HW) {
1210 u16 hdr = skb->h.raw - skb->data;
1211 u16 offset = hdr + skb->csum;
1213 ctrl = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1214 if (skb->nh.iph->protocol == IPPROTO_UDP)
1217 le = get_tx_le(sky2);
1218 le->tx.csum.start = cpu_to_le16(hdr);
1219 le->tx.csum.offset = cpu_to_le16(offset);
1220 le->length = 0; /* initial checksum value */
1221 le->ctrl = 1; /* one packet */
1222 le->opcode = OP_TCPLISW | HW_OWNER;
1225 le = get_tx_le(sky2);
1226 le->tx.addr = cpu_to_le32((u32) mapping);
1227 le->length = cpu_to_le16(len);
1229 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
1231 /* Record the transmit mapping info */
1233 pci_unmap_addr_set(re, mapaddr, mapping);
1235 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1236 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1237 struct tx_ring_info *fre;
1239 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1240 frag->size, PCI_DMA_TODEVICE);
1241 addr64 = high32(mapping);
1242 if (addr64 != sky2->tx_addr64) {
1243 le = get_tx_le(sky2);
1244 le->tx.addr = cpu_to_le32(addr64);
1246 le->opcode = OP_ADDR64 | HW_OWNER;
1247 sky2->tx_addr64 = addr64;
1250 le = get_tx_le(sky2);
1251 le->tx.addr = cpu_to_le32((u32) mapping);
1252 le->length = cpu_to_le16(frag->size);
1254 le->opcode = OP_BUFFER | HW_OWNER;
1257 + ((re - sky2->tx_ring) + i + 1) % TX_RING_SIZE;
1258 pci_unmap_addr_set(fre, mapaddr, mapping);
1261 re->idx = sky2->tx_prod;
1264 avail = tx_avail(sky2);
1265 if (mss != 0 || avail < TX_MIN_PENDING) {
1266 le->ctrl |= FRC_STAT;
1267 if (avail <= MAX_SKB_TX_LE)
1268 netif_stop_queue(dev);
1271 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
1274 spin_unlock(&sky2->tx_lock);
1276 dev->trans_start = jiffies;
1277 return NETDEV_TX_OK;
1281 * Free ring elements from starting at tx_cons until "done"
1283 * NB: the hardware will tell us about partial completion of multi-part
1284 * buffers; these are deferred until completion.
1286 static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
1288 struct net_device *dev = sky2->netdev;
1289 struct pci_dev *pdev = sky2->hw->pdev;
1293 BUG_ON(done >= TX_RING_SIZE);
1295 if (unlikely(netif_msg_tx_done(sky2)))
1296 printk(KERN_DEBUG "%s: tx done, up to %u\n",
1299 for (put = sky2->tx_cons; put != done; put = nxt) {
1300 struct tx_ring_info *re = sky2->tx_ring + put;
1301 struct sk_buff *skb = re->skb;
1304 BUG_ON(nxt >= TX_RING_SIZE);
1305 prefetch(sky2->tx_ring + nxt);
1307 /* Check for partial status */
1308 if (tx_dist(put, done) < tx_dist(put, nxt))
1312 pci_unmap_single(pdev, pci_unmap_addr(re, mapaddr),
1313 skb_headlen(skb), PCI_DMA_TODEVICE);
1315 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1316 struct tx_ring_info *fre;
1317 fre = sky2->tx_ring + (put + i + 1) % TX_RING_SIZE;
1318 pci_unmap_page(pdev, pci_unmap_addr(fre, mapaddr),
1319 skb_shinfo(skb)->frags[i].size,
1323 dev_kfree_skb_any(skb);
1326 sky2->tx_cons = put;
1327 if (netif_queue_stopped(dev) && tx_avail(sky2) > MAX_SKB_TX_LE)
1328 netif_wake_queue(dev);
1331 /* Cleanup all untransmitted buffers, assume transmitter not running */
1332 static void sky2_tx_clean(struct sky2_port *sky2)
1334 spin_lock_bh(&sky2->tx_lock);
1335 sky2_tx_complete(sky2, sky2->tx_prod);
1336 spin_unlock_bh(&sky2->tx_lock);
1339 /* Network shutdown */
1340 static int sky2_down(struct net_device *dev)
1342 struct sky2_port *sky2 = netdev_priv(dev);
1343 struct sky2_hw *hw = sky2->hw;
1344 unsigned port = sky2->port;
1347 /* Never really got started! */
1351 if (netif_msg_ifdown(sky2))
1352 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1354 /* Stop more packets from being queued */
1355 netif_stop_queue(dev);
1357 /* Disable port IRQ */
1358 spin_lock_irq(&hw->hw_lock);
1359 hw->intr_mask &= ~((sky2->port == 0) ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2);
1360 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1361 spin_unlock_irq(&hw->hw_lock);
1363 flush_scheduled_work();
1365 sky2_phy_reset(hw, port);
1367 /* Stop transmitter */
1368 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1369 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1371 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
1372 RB_RST_SET | RB_DIS_OP_MD);
1374 ctrl = gma_read16(hw, port, GM_GP_CTRL);
1375 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
1376 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1378 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1380 /* Workaround shared GMAC reset */
1381 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1382 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
1383 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1385 /* Disable Force Sync bit and Enable Alloc bit */
1386 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1387 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1389 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1390 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1391 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1393 /* Reset the PCI FIFO of the async Tx queue */
1394 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1395 BMU_RST_SET | BMU_FIFO_RST);
1397 /* Reset the Tx prefetch units */
1398 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1401 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1405 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1406 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1408 /* turn off LED's */
1409 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1411 synchronize_irq(hw->pdev->irq);
1413 sky2_tx_clean(sky2);
1414 sky2_rx_clean(sky2);
1416 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1417 sky2->rx_le, sky2->rx_le_map);
1418 kfree(sky2->rx_ring);
1420 pci_free_consistent(hw->pdev,
1421 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1422 sky2->tx_le, sky2->tx_le_map);
1423 kfree(sky2->tx_ring);
1428 sky2->rx_ring = NULL;
1429 sky2->tx_ring = NULL;
1434 static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1439 if (hw->chip_id == CHIP_ID_YUKON_FE)
1440 return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10;
1442 switch (aux & PHY_M_PS_SPEED_MSK) {
1443 case PHY_M_PS_SPEED_1000:
1445 case PHY_M_PS_SPEED_100:
1452 static void sky2_link_up(struct sky2_port *sky2)
1454 struct sky2_hw *hw = sky2->hw;
1455 unsigned port = sky2->port;
1458 /* Enable Transmit FIFO Underrun */
1459 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
1461 reg = gma_read16(hw, port, GM_GP_CTRL);
1462 if (sky2->autoneg == AUTONEG_DISABLE) {
1463 reg |= GM_GPCR_AU_ALL_DIS;
1465 /* Is write/read necessary? Copied from sky2_mac_init */
1466 gma_write16(hw, port, GM_GP_CTRL, reg);
1467 gma_read16(hw, port, GM_GP_CTRL);
1469 switch (sky2->speed) {
1471 reg &= ~GM_GPCR_SPEED_100;
1472 reg |= GM_GPCR_SPEED_1000;
1475 reg &= ~GM_GPCR_SPEED_1000;
1476 reg |= GM_GPCR_SPEED_100;
1479 reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
1483 reg &= ~GM_GPCR_AU_ALL_DIS;
1485 if (sky2->duplex == DUPLEX_FULL || sky2->autoneg == AUTONEG_ENABLE)
1486 reg |= GM_GPCR_DUP_FULL;
1489 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1490 gma_write16(hw, port, GM_GP_CTRL, reg);
1491 gma_read16(hw, port, GM_GP_CTRL);
1493 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1495 netif_carrier_on(sky2->netdev);
1496 netif_wake_queue(sky2->netdev);
1498 /* Turn on link LED */
1499 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
1500 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1502 if (hw->chip_id == CHIP_ID_YUKON_XL) {
1503 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
1505 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
1506 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
1507 PHY_M_LEDC_INIT_CTRL(sky2->speed ==
1509 PHY_M_LEDC_STA1_CTRL(sky2->speed ==
1510 SPEED_100 ? 7 : 0) |
1511 PHY_M_LEDC_STA0_CTRL(sky2->speed ==
1512 SPEED_1000 ? 7 : 0));
1513 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
1516 if (netif_msg_link(sky2))
1517 printk(KERN_INFO PFX
1518 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
1519 sky2->netdev->name, sky2->speed,
1520 sky2->duplex == DUPLEX_FULL ? "full" : "half",
1521 (sky2->tx_pause && sky2->rx_pause) ? "both" :
1522 sky2->tx_pause ? "tx" : sky2->rx_pause ? "rx" : "none");
1525 static void sky2_link_down(struct sky2_port *sky2)
1527 struct sky2_hw *hw = sky2->hw;
1528 unsigned port = sky2->port;
1531 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1533 reg = gma_read16(hw, port, GM_GP_CTRL);
1534 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1535 gma_write16(hw, port, GM_GP_CTRL, reg);
1536 gma_read16(hw, port, GM_GP_CTRL); /* PCI post */
1538 if (sky2->rx_pause && !sky2->tx_pause) {
1539 /* restore Asymmetric Pause bit */
1540 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
1541 gm_phy_read(hw, port, PHY_MARV_AUNE_ADV)
1545 netif_carrier_off(sky2->netdev);
1546 netif_stop_queue(sky2->netdev);
1548 /* Turn on link LED */
1549 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1551 if (netif_msg_link(sky2))
1552 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
1553 sky2_phy_init(hw, port);
1556 static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1558 struct sky2_hw *hw = sky2->hw;
1559 unsigned port = sky2->port;
1562 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
1564 if (lpa & PHY_M_AN_RF) {
1565 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1569 if (hw->chip_id != CHIP_ID_YUKON_FE &&
1570 gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
1571 printk(KERN_ERR PFX "%s: master/slave fault",
1572 sky2->netdev->name);
1576 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1577 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1578 sky2->netdev->name);
1582 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1584 sky2->speed = sky2_phy_speed(hw, aux);
1586 /* Pause bits are offset (9..8) */
1587 if (hw->chip_id == CHIP_ID_YUKON_XL)
1590 sky2->rx_pause = (aux & PHY_M_PS_RX_P_EN) != 0;
1591 sky2->tx_pause = (aux & PHY_M_PS_TX_P_EN) != 0;
1593 if ((sky2->tx_pause || sky2->rx_pause)
1594 && !(sky2->speed < SPEED_1000 && sky2->duplex == DUPLEX_HALF))
1595 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1597 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1603 * Interrupt from PHY are handled outside of interrupt context
1604 * because accessing phy registers requires spin wait which might
1605 * cause excess interrupt latency.
1607 static void sky2_phy_task(void *arg)
1609 struct sky2_port *sky2 = arg;
1610 struct sky2_hw *hw = sky2->hw;
1611 u16 istatus, phystat;
1613 down(&sky2->phy_sema);
1614 istatus = gm_phy_read(hw, sky2->port, PHY_MARV_INT_STAT);
1615 phystat = gm_phy_read(hw, sky2->port, PHY_MARV_PHY_STAT);
1617 if (netif_msg_intr(sky2))
1618 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1619 sky2->netdev->name, istatus, phystat);
1621 if (istatus & PHY_M_IS_AN_COMPL) {
1622 if (sky2_autoneg_done(sky2, phystat) == 0)
1627 if (istatus & PHY_M_IS_LSP_CHANGE)
1628 sky2->speed = sky2_phy_speed(hw, phystat);
1630 if (istatus & PHY_M_IS_DUP_CHANGE)
1632 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1634 if (istatus & PHY_M_IS_LST_CHANGE) {
1635 if (phystat & PHY_M_PS_LINK_UP)
1638 sky2_link_down(sky2);
1641 up(&sky2->phy_sema);
1643 spin_lock_irq(&hw->hw_lock);
1644 hw->intr_mask |= (sky2->port == 0) ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2;
1645 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1646 spin_unlock_irq(&hw->hw_lock);
1650 /* Transmit timeout is only called if we are running, carries is up
1651 * and tx queue is full (stopped).
1653 static void sky2_tx_timeout(struct net_device *dev)
1655 struct sky2_port *sky2 = netdev_priv(dev);
1656 struct sky2_hw *hw = sky2->hw;
1657 unsigned txq = txqaddr[sky2->port];
1660 /* Maybe we just missed an status interrupt */
1661 spin_lock(&sky2->tx_lock);
1662 ridx = sky2_read16(hw,
1663 sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX);
1664 sky2_tx_complete(sky2, ridx);
1665 spin_unlock(&sky2->tx_lock);
1667 if (!netif_queue_stopped(dev)) {
1668 if (net_ratelimit())
1669 pr_info(PFX "transmit interrupt missed? recovered\n");
1673 if (netif_msg_timer(sky2))
1674 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1676 sky2_write32(hw, Q_ADDR(txq, Q_CSR), BMU_STOP);
1677 sky2_write32(hw, Y2_QADDR(txq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1679 sky2_tx_clean(sky2);
1682 sky2_prefetch_init(hw, txq, sky2->tx_le_map, TX_RING_SIZE - 1);
1686 #define roundup(x, y) ((((x)+((y)-1))/(y))*(y))
1687 /* Want receive buffer size to be multiple of 64 bits
1688 * and incl room for vlan and truncation
1690 static inline unsigned sky2_buf_size(int mtu)
1692 return roundup(mtu + ETH_HLEN + VLAN_HLEN, 8) + 8;
1695 static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1697 struct sky2_port *sky2 = netdev_priv(dev);
1698 struct sky2_hw *hw = sky2->hw;
1702 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
1705 if (hw->chip_id == CHIP_ID_YUKON_EC_U && new_mtu > ETH_DATA_LEN)
1708 if (!netif_running(dev)) {
1713 sky2_write32(hw, B0_IMSK, 0);
1715 dev->trans_start = jiffies; /* prevent tx timeout */
1716 netif_stop_queue(dev);
1717 netif_poll_disable(hw->dev[0]);
1719 ctl = gma_read16(hw, sky2->port, GM_GP_CTRL);
1720 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
1722 sky2_rx_clean(sky2);
1725 sky2->rx_bufsize = sky2_buf_size(new_mtu);
1726 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
1727 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1729 if (dev->mtu > ETH_DATA_LEN)
1730 mode |= GM_SMOD_JUMBO_ENA;
1732 gma_write16(hw, sky2->port, GM_SERIAL_MODE, mode);
1734 sky2_write8(hw, RB_ADDR(rxqaddr[sky2->port], RB_CTRL), RB_ENA_OP_MD);
1736 err = sky2_rx_start(sky2);
1737 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1742 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl);
1744 netif_poll_enable(hw->dev[0]);
1745 netif_wake_queue(dev);
1752 * Receive one packet.
1753 * For small packets or errors, just reuse existing skb.
1754 * For larger packets, get new buffer.
1756 static struct sk_buff *sky2_receive(struct sky2_port *sky2,
1757 u16 length, u32 status)
1759 struct ring_info *re = sky2->rx_ring + sky2->rx_next;
1760 struct sk_buff *skb = NULL;
1762 if (unlikely(netif_msg_rx_status(sky2)))
1763 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
1764 sky2->netdev->name, sky2->rx_next, status, length);
1766 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
1767 prefetch(sky2->rx_ring + sky2->rx_next);
1769 if (status & GMR_FS_ANY_ERR)
1772 if (!(status & GMR_FS_RX_OK))
1775 if (length > sky2->netdev->mtu + ETH_HLEN)
1778 if (length < copybreak) {
1779 skb = alloc_skb(length + 2, GFP_ATOMIC);
1783 skb_reserve(skb, 2);
1784 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->mapaddr,
1785 length, PCI_DMA_FROMDEVICE);
1786 memcpy(skb->data, re->skb->data, length);
1787 skb->ip_summed = re->skb->ip_summed;
1788 skb->csum = re->skb->csum;
1789 pci_dma_sync_single_for_device(sky2->hw->pdev, re->mapaddr,
1790 length, PCI_DMA_FROMDEVICE);
1792 struct sk_buff *nskb;
1794 nskb = sky2_alloc_skb(sky2->rx_bufsize, GFP_ATOMIC);
1800 pci_unmap_single(sky2->hw->pdev, re->mapaddr,
1801 sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
1802 prefetch(skb->data);
1804 re->mapaddr = pci_map_single(sky2->hw->pdev, nskb->data,
1805 sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
1808 skb_put(skb, length);
1810 re->skb->ip_summed = CHECKSUM_NONE;
1811 sky2_rx_add(sky2, re->mapaddr);
1813 /* Tell receiver about new buffers. */
1814 sky2_put_idx(sky2->hw, rxqaddr[sky2->port], sky2->rx_put);
1819 ++sky2->net_stats.rx_over_errors;
1823 ++sky2->net_stats.rx_errors;
1825 if (netif_msg_rx_err(sky2) && net_ratelimit())
1826 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
1827 sky2->netdev->name, status, length);
1829 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
1830 sky2->net_stats.rx_length_errors++;
1831 if (status & GMR_FS_FRAGMENT)
1832 sky2->net_stats.rx_frame_errors++;
1833 if (status & GMR_FS_CRC_ERR)
1834 sky2->net_stats.rx_crc_errors++;
1835 if (status & GMR_FS_RX_FF_OV)
1836 sky2->net_stats.rx_fifo_errors++;
1842 * Check for transmit complete
1844 #define TX_NO_STATUS 0xffff
1846 static void sky2_tx_check(struct sky2_hw *hw, int port, u16 last)
1848 if (last != TX_NO_STATUS) {
1849 struct net_device *dev = hw->dev[port];
1850 if (dev && netif_running(dev)) {
1851 struct sky2_port *sky2 = netdev_priv(dev);
1853 spin_lock(&sky2->tx_lock);
1854 sky2_tx_complete(sky2, last);
1855 spin_unlock(&sky2->tx_lock);
1861 * Both ports share the same status interrupt, therefore there is only
1864 static int sky2_poll(struct net_device *dev0, int *budget)
1866 struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw;
1867 unsigned int to_do = min(dev0->quota, *budget);
1868 unsigned int work_done = 0;
1870 u16 tx_done[2] = { TX_NO_STATUS, TX_NO_STATUS };
1872 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
1875 * Kick the STAT_LEV_TIMER_CTRL timer.
1876 * This fixes my hangs on Yukon-EC (0xb6) rev 1.
1877 * The if clause is there to start the timer only if it has been
1878 * configured correctly and not been disabled via ethtool.
1880 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_START) {
1881 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
1882 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
1885 hwidx = sky2_read16(hw, STAT_PUT_IDX);
1886 BUG_ON(hwidx >= STATUS_RING_SIZE);
1889 while (hwidx != hw->st_idx) {
1890 struct sky2_status_le *le = hw->st_le + hw->st_idx;
1891 struct net_device *dev;
1892 struct sky2_port *sky2;
1893 struct sk_buff *skb;
1897 le = hw->st_le + hw->st_idx;
1898 hw->st_idx = (hw->st_idx + 1) % STATUS_RING_SIZE;
1899 prefetch(hw->st_le + hw->st_idx);
1901 BUG_ON(le->link >= 2);
1902 dev = hw->dev[le->link];
1903 if (dev == NULL || !netif_running(dev))
1906 sky2 = netdev_priv(dev);
1907 status = le32_to_cpu(le->status);
1908 length = le16_to_cpu(le->length);
1910 switch (le->opcode & ~HW_OWNER) {
1912 skb = sky2_receive(sky2, length, status);
1917 skb->protocol = eth_type_trans(skb, dev);
1918 dev->last_rx = jiffies;
1920 #ifdef SKY2_VLAN_TAG_USED
1921 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
1922 vlan_hwaccel_receive_skb(skb,
1924 be16_to_cpu(sky2->rx_tag));
1927 netif_receive_skb(skb);
1929 if (++work_done >= to_do)
1933 #ifdef SKY2_VLAN_TAG_USED
1935 sky2->rx_tag = length;
1939 sky2->rx_tag = length;
1943 skb = sky2->rx_ring[sky2->rx_next].skb;
1944 skb->ip_summed = CHECKSUM_HW;
1945 skb->csum = le16_to_cpu(status);
1949 /* TX index reports status for both ports */
1950 tx_done[0] = status & 0xffff;
1951 tx_done[1] = ((status >> 24) & 0xff)
1952 | (u16)(length & 0xf) << 8;
1956 if (net_ratelimit())
1957 printk(KERN_WARNING PFX
1958 "unknown status opcode 0x%x\n", le->opcode);
1964 sky2_tx_check(hw, 0, tx_done[0]);
1965 sky2_tx_check(hw, 1, tx_done[1]);
1967 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_START) {
1968 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
1969 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
1972 if (likely(work_done < to_do)) {
1973 spin_lock_irq(&hw->hw_lock);
1974 __netif_rx_complete(dev0);
1976 hw->intr_mask |= Y2_IS_STAT_BMU;
1977 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1978 spin_unlock_irq(&hw->hw_lock);
1982 *budget -= work_done;
1983 dev0->quota -= work_done;
1988 static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
1990 struct net_device *dev = hw->dev[port];
1992 if (net_ratelimit())
1993 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
1996 if (status & Y2_IS_PAR_RD1) {
1997 if (net_ratelimit())
1998 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2001 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2004 if (status & Y2_IS_PAR_WR1) {
2005 if (net_ratelimit())
2006 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2009 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2012 if (status & Y2_IS_PAR_MAC1) {
2013 if (net_ratelimit())
2014 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
2015 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2018 if (status & Y2_IS_PAR_RX1) {
2019 if (net_ratelimit())
2020 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
2021 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2024 if (status & Y2_IS_TCP_TXA1) {
2025 if (net_ratelimit())
2026 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2028 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2032 static void sky2_hw_intr(struct sky2_hw *hw)
2034 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2036 if (status & Y2_IS_TIST_OV)
2037 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2039 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
2042 pci_err = sky2_pci_read16(hw, PCI_STATUS);
2043 if (net_ratelimit())
2044 printk(KERN_ERR PFX "%s: pci hw error (0x%x)\n",
2045 pci_name(hw->pdev), pci_err);
2047 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2048 sky2_pci_write16(hw, PCI_STATUS,
2049 pci_err | PCI_STATUS_ERROR_BITS);
2050 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2053 if (status & Y2_IS_PCI_EXP) {
2054 /* PCI-Express uncorrectable Error occurred */
2057 pex_err = sky2_pci_read32(hw, PEX_UNC_ERR_STAT);
2059 if (net_ratelimit())
2060 printk(KERN_ERR PFX "%s: pci express error (0x%x)\n",
2061 pci_name(hw->pdev), pex_err);
2063 /* clear the interrupt */
2064 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2065 sky2_pci_write32(hw, PEX_UNC_ERR_STAT,
2067 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2069 if (pex_err & PEX_FATAL_ERRORS) {
2070 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2071 hwmsk &= ~Y2_IS_PCI_EXP;
2072 sky2_write32(hw, B0_HWE_IMSK, hwmsk);
2076 if (status & Y2_HWE_L1_MASK)
2077 sky2_hw_error(hw, 0, status);
2079 if (status & Y2_HWE_L1_MASK)
2080 sky2_hw_error(hw, 1, status);
2083 static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2085 struct net_device *dev = hw->dev[port];
2086 struct sky2_port *sky2 = netdev_priv(dev);
2087 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2089 if (netif_msg_intr(sky2))
2090 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2093 if (status & GM_IS_RX_FF_OR) {
2094 ++sky2->net_stats.rx_fifo_errors;
2095 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2098 if (status & GM_IS_TX_FF_UR) {
2099 ++sky2->net_stats.tx_fifo_errors;
2100 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2104 static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
2106 struct net_device *dev = hw->dev[port];
2107 struct sky2_port *sky2 = netdev_priv(dev);
2109 hw->intr_mask &= ~(port == 0 ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2);
2110 sky2_write32(hw, B0_IMSK, hw->intr_mask);
2112 schedule_work(&sky2->phy_task);
2115 static irqreturn_t sky2_intr(int irq, void *dev_id, struct pt_regs *regs)
2117 struct sky2_hw *hw = dev_id;
2118 struct net_device *dev0 = hw->dev[0];
2121 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2122 if (status == 0 || status == ~0)
2125 spin_lock(&hw->hw_lock);
2126 if (status & Y2_IS_HW_ERR)
2129 /* Do NAPI for Rx and Tx status */
2130 if (status & Y2_IS_STAT_BMU) {
2131 hw->intr_mask &= ~Y2_IS_STAT_BMU;
2132 sky2_write32(hw, B0_IMSK, hw->intr_mask);
2134 if (likely(__netif_rx_schedule_prep(dev0))) {
2135 prefetch(&hw->st_le[hw->st_idx]);
2136 __netif_rx_schedule(dev0);
2140 if (status & Y2_IS_IRQ_PHY1)
2141 sky2_phy_intr(hw, 0);
2143 if (status & Y2_IS_IRQ_PHY2)
2144 sky2_phy_intr(hw, 1);
2146 if (status & Y2_IS_IRQ_MAC1)
2147 sky2_mac_intr(hw, 0);
2149 if (status & Y2_IS_IRQ_MAC2)
2150 sky2_mac_intr(hw, 1);
2152 sky2_write32(hw, B0_Y2_SP_ICR, 2);
2154 spin_unlock(&hw->hw_lock);
2159 #ifdef CONFIG_NET_POLL_CONTROLLER
2160 static void sky2_netpoll(struct net_device *dev)
2162 struct sky2_port *sky2 = netdev_priv(dev);
2164 sky2_intr(sky2->hw->pdev->irq, sky2->hw, NULL);
2168 /* Chip internal frequency for clock calculations */
2169 static inline u32 sky2_mhz(const struct sky2_hw *hw)
2171 switch (hw->chip_id) {
2172 case CHIP_ID_YUKON_EC:
2173 case CHIP_ID_YUKON_EC_U:
2174 return 125; /* 125 Mhz */
2175 case CHIP_ID_YUKON_FE:
2176 return 100; /* 100 Mhz */
2177 default: /* YUKON_XL */
2178 return 156; /* 156 Mhz */
2182 static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
2184 return sky2_mhz(hw) * us;
2187 static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
2189 return clk / sky2_mhz(hw);
2193 static int sky2_reset(struct sky2_hw *hw)
2199 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2201 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2202 if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) {
2203 printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",
2204 pci_name(hw->pdev), hw->chip_id);
2208 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2210 /* This rev is really old, and requires untested workarounds */
2211 if (hw->chip_id == CHIP_ID_YUKON_EC && hw->chip_rev == CHIP_REV_YU_EC_A1) {
2212 printk(KERN_ERR PFX "%s: unsupported revision Yukon-%s (0x%x) rev %d\n",
2213 pci_name(hw->pdev), yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
2214 hw->chip_id, hw->chip_rev);
2218 /* This chip is new and not tested yet */
2219 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
2220 pr_info(PFX "%s: is a version of Yukon 2 chipset that has not been tested yet.\n",
2221 pci_name(hw->pdev));
2222 pr_info("Please report success/failure to maintainer <shemminger@osdl.org>\n");
2226 if (hw->chip_id <= CHIP_ID_YUKON_EC) {
2227 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2228 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
2232 sky2_write8(hw, B0_CTST, CS_RST_SET);
2233 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2235 /* clear PCI errors, if any */
2236 status = sky2_pci_read16(hw, PCI_STATUS);
2238 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2239 sky2_pci_write16(hw, PCI_STATUS, status | PCI_STATUS_ERROR_BITS);
2242 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2244 /* clear any PEX errors */
2245 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
2246 sky2_pci_write32(hw, PEX_UNC_ERR_STAT, 0xffffffffUL);
2249 pmd_type = sky2_read8(hw, B2_PMD_TYP);
2250 hw->copper = !(pmd_type == 'L' || pmd_type == 'S');
2253 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2254 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2255 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2259 sky2_set_power_state(hw, PCI_D0);
2261 for (i = 0; i < hw->ports; i++) {
2262 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2263 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2266 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2268 /* Clear I2C IRQ noise */
2269 sky2_write32(hw, B2_I2C_IRQ, 1);
2271 /* turn off hardware timer (unused) */
2272 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2273 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
2275 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2277 /* Turn off descriptor polling */
2278 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
2280 /* Turn off receive timestamp */
2281 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
2282 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2284 /* enable the Tx Arbiters */
2285 for (i = 0; i < hw->ports; i++)
2286 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2288 /* Initialize ram interface */
2289 for (i = 0; i < hw->ports; i++) {
2290 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
2292 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2293 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2294 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2295 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2296 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2297 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2298 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2299 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2300 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2301 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2302 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2303 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2306 sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);
2308 for (i = 0; i < hw->ports; i++)
2309 sky2_phy_reset(hw, i);
2311 memset(hw->st_le, 0, STATUS_LE_BYTES);
2314 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2315 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2317 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
2318 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
2320 /* Set the list last index */
2321 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
2323 /* These status setup values are copied from SysKonnect's driver */
2324 sky2_write16(hw, STAT_TX_IDX_TH, 10);
2325 sky2_write8(hw, STAT_FIFO_WM, 16);
2327 /* set Status-FIFO ISR watermark */
2328 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2329 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
2331 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
2333 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
2334 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 7));
2336 /* enable status unit */
2337 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2339 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2340 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2341 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2346 static u32 sky2_supported_modes(const struct sky2_hw *hw)
2350 modes = SUPPORTED_10baseT_Half
2351 | SUPPORTED_10baseT_Full
2352 | SUPPORTED_100baseT_Half
2353 | SUPPORTED_100baseT_Full
2354 | SUPPORTED_Autoneg | SUPPORTED_TP;
2356 if (hw->chip_id != CHIP_ID_YUKON_FE)
2357 modes |= SUPPORTED_1000baseT_Half
2358 | SUPPORTED_1000baseT_Full;
2360 modes = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE
2361 | SUPPORTED_Autoneg;
2365 static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2367 struct sky2_port *sky2 = netdev_priv(dev);
2368 struct sky2_hw *hw = sky2->hw;
2370 ecmd->transceiver = XCVR_INTERNAL;
2371 ecmd->supported = sky2_supported_modes(hw);
2372 ecmd->phy_address = PHY_ADDR_MARV;
2374 ecmd->supported = SUPPORTED_10baseT_Half
2375 | SUPPORTED_10baseT_Full
2376 | SUPPORTED_100baseT_Half
2377 | SUPPORTED_100baseT_Full
2378 | SUPPORTED_1000baseT_Half
2379 | SUPPORTED_1000baseT_Full
2380 | SUPPORTED_Autoneg | SUPPORTED_TP;
2381 ecmd->port = PORT_TP;
2383 ecmd->port = PORT_FIBRE;
2385 ecmd->advertising = sky2->advertising;
2386 ecmd->autoneg = sky2->autoneg;
2387 ecmd->speed = sky2->speed;
2388 ecmd->duplex = sky2->duplex;
2392 static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2394 struct sky2_port *sky2 = netdev_priv(dev);
2395 const struct sky2_hw *hw = sky2->hw;
2396 u32 supported = sky2_supported_modes(hw);
2398 if (ecmd->autoneg == AUTONEG_ENABLE) {
2399 ecmd->advertising = supported;
2405 switch (ecmd->speed) {
2407 if (ecmd->duplex == DUPLEX_FULL)
2408 setting = SUPPORTED_1000baseT_Full;
2409 else if (ecmd->duplex == DUPLEX_HALF)
2410 setting = SUPPORTED_1000baseT_Half;
2415 if (ecmd->duplex == DUPLEX_FULL)
2416 setting = SUPPORTED_100baseT_Full;
2417 else if (ecmd->duplex == DUPLEX_HALF)
2418 setting = SUPPORTED_100baseT_Half;
2424 if (ecmd->duplex == DUPLEX_FULL)
2425 setting = SUPPORTED_10baseT_Full;
2426 else if (ecmd->duplex == DUPLEX_HALF)
2427 setting = SUPPORTED_10baseT_Half;
2435 if ((setting & supported) == 0)
2438 sky2->speed = ecmd->speed;
2439 sky2->duplex = ecmd->duplex;
2442 sky2->autoneg = ecmd->autoneg;
2443 sky2->advertising = ecmd->advertising;
2445 if (netif_running(dev))
2446 sky2_phy_reinit(sky2);
2451 static void sky2_get_drvinfo(struct net_device *dev,
2452 struct ethtool_drvinfo *info)
2454 struct sky2_port *sky2 = netdev_priv(dev);
2456 strcpy(info->driver, DRV_NAME);
2457 strcpy(info->version, DRV_VERSION);
2458 strcpy(info->fw_version, "N/A");
2459 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
2462 static const struct sky2_stat {
2463 char name[ETH_GSTRING_LEN];
2466 { "tx_bytes", GM_TXO_OK_HI },
2467 { "rx_bytes", GM_RXO_OK_HI },
2468 { "tx_broadcast", GM_TXF_BC_OK },
2469 { "rx_broadcast", GM_RXF_BC_OK },
2470 { "tx_multicast", GM_TXF_MC_OK },
2471 { "rx_multicast", GM_RXF_MC_OK },
2472 { "tx_unicast", GM_TXF_UC_OK },
2473 { "rx_unicast", GM_RXF_UC_OK },
2474 { "tx_mac_pause", GM_TXF_MPAUSE },
2475 { "rx_mac_pause", GM_RXF_MPAUSE },
2476 { "collisions", GM_TXF_SNG_COL },
2477 { "late_collision",GM_TXF_LAT_COL },
2478 { "aborted", GM_TXF_ABO_COL },
2479 { "multi_collisions", GM_TXF_MUL_COL },
2480 { "fifo_underrun", GM_TXE_FIFO_UR },
2481 { "fifo_overflow", GM_RXE_FIFO_OV },
2482 { "rx_toolong", GM_RXF_LNG_ERR },
2483 { "rx_jabber", GM_RXF_JAB_PKT },
2484 { "rx_runt", GM_RXE_FRAG },
2485 { "rx_too_long", GM_RXF_LNG_ERR },
2486 { "rx_fcs_error", GM_RXF_FCS_ERR },
2489 static u32 sky2_get_rx_csum(struct net_device *dev)
2491 struct sky2_port *sky2 = netdev_priv(dev);
2493 return sky2->rx_csum;
2496 static int sky2_set_rx_csum(struct net_device *dev, u32 data)
2498 struct sky2_port *sky2 = netdev_priv(dev);
2500 sky2->rx_csum = data;
2502 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2503 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
2508 static u32 sky2_get_msglevel(struct net_device *netdev)
2510 struct sky2_port *sky2 = netdev_priv(netdev);
2511 return sky2->msg_enable;
2514 static int sky2_nway_reset(struct net_device *dev)
2516 struct sky2_port *sky2 = netdev_priv(dev);
2518 if (sky2->autoneg != AUTONEG_ENABLE)
2521 sky2_phy_reinit(sky2);
2526 static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
2528 struct sky2_hw *hw = sky2->hw;
2529 unsigned port = sky2->port;
2532 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
2533 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
2534 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
2535 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
2537 for (i = 2; i < count; i++)
2538 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
2541 static void sky2_set_msglevel(struct net_device *netdev, u32 value)
2543 struct sky2_port *sky2 = netdev_priv(netdev);
2544 sky2->msg_enable = value;
2547 static int sky2_get_stats_count(struct net_device *dev)
2549 return ARRAY_SIZE(sky2_stats);
2552 static void sky2_get_ethtool_stats(struct net_device *dev,
2553 struct ethtool_stats *stats, u64 * data)
2555 struct sky2_port *sky2 = netdev_priv(dev);
2557 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
2560 static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
2564 switch (stringset) {
2566 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
2567 memcpy(data + i * ETH_GSTRING_LEN,
2568 sky2_stats[i].name, ETH_GSTRING_LEN);
2573 /* Use hardware MIB variables for critical path statistics and
2574 * transmit feedback not reported at interrupt.
2575 * Other errors are accounted for in interrupt handler.
2577 static struct net_device_stats *sky2_get_stats(struct net_device *dev)
2579 struct sky2_port *sky2 = netdev_priv(dev);
2582 sky2_phy_stats(sky2, data, ARRAY_SIZE(data));
2584 sky2->net_stats.tx_bytes = data[0];
2585 sky2->net_stats.rx_bytes = data[1];
2586 sky2->net_stats.tx_packets = data[2] + data[4] + data[6];
2587 sky2->net_stats.rx_packets = data[3] + data[5] + data[7];
2588 sky2->net_stats.multicast = data[5] + data[7];
2589 sky2->net_stats.collisions = data[10];
2590 sky2->net_stats.tx_aborted_errors = data[12];
2592 return &sky2->net_stats;
2595 static int sky2_set_mac_address(struct net_device *dev, void *p)
2597 struct sky2_port *sky2 = netdev_priv(dev);
2598 struct sky2_hw *hw = sky2->hw;
2599 unsigned port = sky2->port;
2600 const struct sockaddr *addr = p;
2602 if (!is_valid_ether_addr(addr->sa_data))
2603 return -EADDRNOTAVAIL;
2605 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
2606 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
2607 dev->dev_addr, ETH_ALEN);
2608 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
2609 dev->dev_addr, ETH_ALEN);
2611 /* virtual address for data */
2612 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
2614 /* physical address: used for pause frames */
2615 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
2620 static void sky2_set_multicast(struct net_device *dev)
2622 struct sky2_port *sky2 = netdev_priv(dev);
2623 struct sky2_hw *hw = sky2->hw;
2624 unsigned port = sky2->port;
2625 struct dev_mc_list *list = dev->mc_list;
2629 memset(filter, 0, sizeof(filter));
2631 reg = gma_read16(hw, port, GM_RX_CTRL);
2632 reg |= GM_RXCR_UCF_ENA;
2634 if (dev->flags & IFF_PROMISC) /* promiscuous */
2635 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2636 else if ((dev->flags & IFF_ALLMULTI) || dev->mc_count > 16) /* all multicast */
2637 memset(filter, 0xff, sizeof(filter));
2638 else if (dev->mc_count == 0) /* no multicast */
2639 reg &= ~GM_RXCR_MCF_ENA;
2642 reg |= GM_RXCR_MCF_ENA;
2644 for (i = 0; list && i < dev->mc_count; i++, list = list->next) {
2645 u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;
2646 filter[bit / 8] |= 1 << (bit % 8);
2650 gma_write16(hw, port, GM_MC_ADDR_H1,
2651 (u16) filter[0] | ((u16) filter[1] << 8));
2652 gma_write16(hw, port, GM_MC_ADDR_H2,
2653 (u16) filter[2] | ((u16) filter[3] << 8));
2654 gma_write16(hw, port, GM_MC_ADDR_H3,
2655 (u16) filter[4] | ((u16) filter[5] << 8));
2656 gma_write16(hw, port, GM_MC_ADDR_H4,
2657 (u16) filter[6] | ((u16) filter[7] << 8));
2659 gma_write16(hw, port, GM_RX_CTRL, reg);
2662 /* Can have one global because blinking is controlled by
2663 * ethtool and that is always under RTNL mutex
2665 static void sky2_led(struct sky2_hw *hw, unsigned port, int on)
2669 switch (hw->chip_id) {
2670 case CHIP_ID_YUKON_XL:
2671 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2672 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2673 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
2674 on ? (PHY_M_LEDC_LOS_CTRL(1) |
2675 PHY_M_LEDC_INIT_CTRL(7) |
2676 PHY_M_LEDC_STA1_CTRL(7) |
2677 PHY_M_LEDC_STA0_CTRL(7))
2680 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2684 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
2685 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
2686 on ? PHY_M_LED_MO_DUP(MO_LED_ON) |
2687 PHY_M_LED_MO_10(MO_LED_ON) |
2688 PHY_M_LED_MO_100(MO_LED_ON) |
2689 PHY_M_LED_MO_1000(MO_LED_ON) |
2690 PHY_M_LED_MO_RX(MO_LED_ON)
2691 : PHY_M_LED_MO_DUP(MO_LED_OFF) |
2692 PHY_M_LED_MO_10(MO_LED_OFF) |
2693 PHY_M_LED_MO_100(MO_LED_OFF) |
2694 PHY_M_LED_MO_1000(MO_LED_OFF) |
2695 PHY_M_LED_MO_RX(MO_LED_OFF));
2700 /* blink LED's for finding board */
2701 static int sky2_phys_id(struct net_device *dev, u32 data)
2703 struct sky2_port *sky2 = netdev_priv(dev);
2704 struct sky2_hw *hw = sky2->hw;
2705 unsigned port = sky2->port;
2706 u16 ledctrl, ledover = 0;
2711 if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
2712 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
2716 /* save initial values */
2717 down(&sky2->phy_sema);
2718 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2719 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2720 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2721 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
2722 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2724 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
2725 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
2729 while (!interrupted && ms > 0) {
2730 sky2_led(hw, port, onoff);
2733 up(&sky2->phy_sema);
2734 interrupted = msleep_interruptible(250);
2735 down(&sky2->phy_sema);
2740 /* resume regularly scheduled programming */
2741 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2742 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2743 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2744 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
2745 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2747 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
2748 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
2750 up(&sky2->phy_sema);
2755 static void sky2_get_pauseparam(struct net_device *dev,
2756 struct ethtool_pauseparam *ecmd)
2758 struct sky2_port *sky2 = netdev_priv(dev);
2760 ecmd->tx_pause = sky2->tx_pause;
2761 ecmd->rx_pause = sky2->rx_pause;
2762 ecmd->autoneg = sky2->autoneg;
2765 static int sky2_set_pauseparam(struct net_device *dev,
2766 struct ethtool_pauseparam *ecmd)
2768 struct sky2_port *sky2 = netdev_priv(dev);
2771 sky2->autoneg = ecmd->autoneg;
2772 sky2->tx_pause = ecmd->tx_pause != 0;
2773 sky2->rx_pause = ecmd->rx_pause != 0;
2775 sky2_phy_reinit(sky2);
2781 static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2783 struct sky2_port *sky2 = netdev_priv(dev);
2785 wol->supported = WAKE_MAGIC;
2786 wol->wolopts = sky2->wol ? WAKE_MAGIC : 0;
2789 static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2791 struct sky2_port *sky2 = netdev_priv(dev);
2792 struct sky2_hw *hw = sky2->hw;
2794 if (wol->wolopts != WAKE_MAGIC && wol->wolopts != 0)
2797 sky2->wol = wol->wolopts == WAKE_MAGIC;
2800 memcpy_toio(hw->regs + WOL_MAC_ADDR, dev->dev_addr, ETH_ALEN);
2802 sky2_write16(hw, WOL_CTRL_STAT,
2803 WOL_CTL_ENA_PME_ON_MAGIC_PKT |
2804 WOL_CTL_ENA_MAGIC_PKT_UNIT);
2806 sky2_write16(hw, WOL_CTRL_STAT, WOL_CTL_DEFAULT);
2812 static int sky2_get_coalesce(struct net_device *dev,
2813 struct ethtool_coalesce *ecmd)
2815 struct sky2_port *sky2 = netdev_priv(dev);
2816 struct sky2_hw *hw = sky2->hw;
2818 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
2819 ecmd->tx_coalesce_usecs = 0;
2821 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
2822 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
2824 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
2826 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
2827 ecmd->rx_coalesce_usecs = 0;
2829 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
2830 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
2832 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
2834 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
2835 ecmd->rx_coalesce_usecs_irq = 0;
2837 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
2838 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
2841 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
2846 /* Note: this affect both ports */
2847 static int sky2_set_coalesce(struct net_device *dev,
2848 struct ethtool_coalesce *ecmd)
2850 struct sky2_port *sky2 = netdev_priv(dev);
2851 struct sky2_hw *hw = sky2->hw;
2852 const u32 tmin = sky2_clk2us(hw, 1);
2853 const u32 tmax = 5000;
2855 if (ecmd->tx_coalesce_usecs != 0 &&
2856 (ecmd->tx_coalesce_usecs < tmin || ecmd->tx_coalesce_usecs > tmax))
2859 if (ecmd->rx_coalesce_usecs != 0 &&
2860 (ecmd->rx_coalesce_usecs < tmin || ecmd->rx_coalesce_usecs > tmax))
2863 if (ecmd->rx_coalesce_usecs_irq != 0 &&
2864 (ecmd->rx_coalesce_usecs_irq < tmin || ecmd->rx_coalesce_usecs_irq > tmax))
2867 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
2869 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
2871 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
2874 if (ecmd->tx_coalesce_usecs == 0)
2875 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
2877 sky2_write32(hw, STAT_TX_TIMER_INI,
2878 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
2879 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2881 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
2883 if (ecmd->rx_coalesce_usecs == 0)
2884 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
2886 sky2_write32(hw, STAT_LEV_TIMER_INI,
2887 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
2888 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2890 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
2892 if (ecmd->rx_coalesce_usecs_irq == 0)
2893 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
2895 sky2_write32(hw, STAT_ISR_TIMER_INI,
2896 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
2897 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2899 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
2903 static void sky2_get_ringparam(struct net_device *dev,
2904 struct ethtool_ringparam *ering)
2906 struct sky2_port *sky2 = netdev_priv(dev);
2908 ering->rx_max_pending = RX_MAX_PENDING;
2909 ering->rx_mini_max_pending = 0;
2910 ering->rx_jumbo_max_pending = 0;
2911 ering->tx_max_pending = TX_RING_SIZE - 1;
2913 ering->rx_pending = sky2->rx_pending;
2914 ering->rx_mini_pending = 0;
2915 ering->rx_jumbo_pending = 0;
2916 ering->tx_pending = sky2->tx_pending;
2919 static int sky2_set_ringparam(struct net_device *dev,
2920 struct ethtool_ringparam *ering)
2922 struct sky2_port *sky2 = netdev_priv(dev);
2925 if (ering->rx_pending > RX_MAX_PENDING ||
2926 ering->rx_pending < 8 ||
2927 ering->tx_pending < MAX_SKB_TX_LE ||
2928 ering->tx_pending > TX_RING_SIZE - 1)
2931 if (netif_running(dev))
2934 sky2->rx_pending = ering->rx_pending;
2935 sky2->tx_pending = ering->tx_pending;
2937 if (netif_running(dev)) {
2942 sky2_set_multicast(dev);
2948 static int sky2_get_regs_len(struct net_device *dev)
2954 * Returns copy of control register region
2955 * Note: access to the RAM address register set will cause timeouts.
2957 static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
2960 const struct sky2_port *sky2 = netdev_priv(dev);
2961 const void __iomem *io = sky2->hw->regs;
2963 BUG_ON(regs->len < B3_RI_WTO_R1);
2965 memset(p, 0, regs->len);
2967 memcpy_fromio(p, io, B3_RAM_ADDR);
2969 memcpy_fromio(p + B3_RI_WTO_R1,
2971 regs->len - B3_RI_WTO_R1);
2974 static struct ethtool_ops sky2_ethtool_ops = {
2975 .get_settings = sky2_get_settings,
2976 .set_settings = sky2_set_settings,
2977 .get_drvinfo = sky2_get_drvinfo,
2978 .get_msglevel = sky2_get_msglevel,
2979 .set_msglevel = sky2_set_msglevel,
2980 .nway_reset = sky2_nway_reset,
2981 .get_regs_len = sky2_get_regs_len,
2982 .get_regs = sky2_get_regs,
2983 .get_link = ethtool_op_get_link,
2984 .get_sg = ethtool_op_get_sg,
2985 .set_sg = ethtool_op_set_sg,
2986 .get_tx_csum = ethtool_op_get_tx_csum,
2987 .set_tx_csum = ethtool_op_set_tx_csum,
2988 .get_tso = ethtool_op_get_tso,
2989 .set_tso = ethtool_op_set_tso,
2990 .get_rx_csum = sky2_get_rx_csum,
2991 .set_rx_csum = sky2_set_rx_csum,
2992 .get_strings = sky2_get_strings,
2993 .get_coalesce = sky2_get_coalesce,
2994 .set_coalesce = sky2_set_coalesce,
2995 .get_ringparam = sky2_get_ringparam,
2996 .set_ringparam = sky2_set_ringparam,
2997 .get_pauseparam = sky2_get_pauseparam,
2998 .set_pauseparam = sky2_set_pauseparam,
3000 .get_wol = sky2_get_wol,
3001 .set_wol = sky2_set_wol,
3003 .phys_id = sky2_phys_id,
3004 .get_stats_count = sky2_get_stats_count,
3005 .get_ethtool_stats = sky2_get_ethtool_stats,
3006 .get_perm_addr = ethtool_op_get_perm_addr,
3009 /* Initialize network device */
3010 static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
3011 unsigned port, int highmem)
3013 struct sky2_port *sky2;
3014 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
3017 printk(KERN_ERR "sky2 etherdev alloc failed");
3021 SET_MODULE_OWNER(dev);
3022 SET_NETDEV_DEV(dev, &hw->pdev->dev);
3023 dev->irq = hw->pdev->irq;
3024 dev->open = sky2_up;
3025 dev->stop = sky2_down;
3026 dev->do_ioctl = sky2_ioctl;
3027 dev->hard_start_xmit = sky2_xmit_frame;
3028 dev->get_stats = sky2_get_stats;
3029 dev->set_multicast_list = sky2_set_multicast;
3030 dev->set_mac_address = sky2_set_mac_address;
3031 dev->change_mtu = sky2_change_mtu;
3032 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
3033 dev->tx_timeout = sky2_tx_timeout;
3034 dev->watchdog_timeo = TX_WATCHDOG;
3036 dev->poll = sky2_poll;
3037 dev->weight = NAPI_WEIGHT;
3038 #ifdef CONFIG_NET_POLL_CONTROLLER
3039 dev->poll_controller = sky2_netpoll;
3042 sky2 = netdev_priv(dev);
3045 sky2->msg_enable = netif_msg_init(debug, default_msg);
3047 spin_lock_init(&sky2->tx_lock);
3048 /* Auto speed and flow control */
3049 sky2->autoneg = AUTONEG_ENABLE;
3054 sky2->advertising = sky2_supported_modes(hw);
3056 /* Receive checksum disabled for Yukon XL
3057 * because of observed problems with incorrect
3058 * values when multiple packets are received in one interrupt
3060 sky2->rx_csum = (hw->chip_id != CHIP_ID_YUKON_XL);
3062 INIT_WORK(&sky2->phy_task, sky2_phy_task, sky2);
3063 init_MUTEX(&sky2->phy_sema);
3064 sky2->tx_pending = TX_DEF_PENDING;
3065 sky2->rx_pending = RX_DEF_PENDING;
3066 sky2->rx_bufsize = sky2_buf_size(ETH_DATA_LEN);
3068 hw->dev[port] = dev;
3072 dev->features |= NETIF_F_LLTX;
3073 if (hw->chip_id != CHIP_ID_YUKON_EC_U)
3074 dev->features |= NETIF_F_TSO;
3076 dev->features |= NETIF_F_HIGHDMA;
3077 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
3079 #ifdef SKY2_VLAN_TAG_USED
3080 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3081 dev->vlan_rx_register = sky2_vlan_rx_register;
3082 dev->vlan_rx_kill_vid = sky2_vlan_rx_kill_vid;
3085 /* read the mac address */
3086 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
3087 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
3089 /* device is off until link detection */
3090 netif_carrier_off(dev);
3091 netif_stop_queue(dev);
3096 static void __devinit sky2_show_addr(struct net_device *dev)
3098 const struct sky2_port *sky2 = netdev_priv(dev);
3100 if (netif_msg_probe(sky2))
3101 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3103 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3104 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3107 static int __devinit sky2_probe(struct pci_dev *pdev,
3108 const struct pci_device_id *ent)
3110 struct net_device *dev, *dev1 = NULL;
3112 int err, pm_cap, using_dac = 0;
3114 err = pci_enable_device(pdev);
3116 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
3121 err = pci_request_regions(pdev, DRV_NAME);
3123 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
3128 pci_set_master(pdev);
3130 /* Find power-management capability. */
3131 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
3133 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
3136 goto err_out_free_regions;
3139 if (sizeof(dma_addr_t) > sizeof(u32) &&
3140 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
3142 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3144 printk(KERN_ERR PFX "%s unable to obtain 64 bit DMA "
3145 "for consistent allocations\n", pci_name(pdev));
3146 goto err_out_free_regions;
3150 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3152 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
3154 goto err_out_free_regions;
3159 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
3161 printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",
3163 goto err_out_free_regions;
3168 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3170 printk(KERN_ERR PFX "%s: cannot map device registers\n",
3172 goto err_out_free_hw;
3174 hw->pm_cap = pm_cap;
3175 spin_lock_init(&hw->hw_lock);
3178 /* byte swap descriptors in hardware */
3182 reg = sky2_pci_read32(hw, PCI_DEV_REG2);
3183 reg |= PCI_REV_DESC;
3184 sky2_pci_write32(hw, PCI_DEV_REG2, reg);
3188 /* ring for status responses */
3189 hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,
3192 goto err_out_iounmap;
3194 err = sky2_reset(hw);
3196 goto err_out_iounmap;
3198 printk(KERN_INFO PFX "v%s addr 0x%lx irq %d Yukon-%s (0x%x) rev %d\n",
3199 DRV_VERSION, pci_resource_start(pdev, 0), pdev->irq,
3200 yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
3201 hw->chip_id, hw->chip_rev);
3203 dev = sky2_init_netdev(hw, 0, using_dac);
3205 goto err_out_free_pci;
3207 err = register_netdev(dev);
3209 printk(KERN_ERR PFX "%s: cannot register net device\n",
3211 goto err_out_free_netdev;
3214 sky2_show_addr(dev);
3216 if (hw->ports > 1 && (dev1 = sky2_init_netdev(hw, 1, using_dac))) {
3217 if (register_netdev(dev1) == 0)
3218 sky2_show_addr(dev1);
3220 /* Failure to register second port need not be fatal */
3221 printk(KERN_WARNING PFX
3222 "register of second port failed\n");
3228 err = request_irq(pdev->irq, sky2_intr, SA_SHIRQ, DRV_NAME, hw);
3230 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3231 pci_name(pdev), pdev->irq);
3232 goto err_out_unregister;
3235 hw->intr_mask = Y2_IS_BASE;
3236 sky2_write32(hw, B0_IMSK, hw->intr_mask);
3238 pci_set_drvdata(pdev, hw);
3244 unregister_netdev(dev1);
3247 unregister_netdev(dev);
3248 err_out_free_netdev:
3251 sky2_write8(hw, B0_CTST, CS_RST_SET);
3252 pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3257 err_out_free_regions:
3258 pci_release_regions(pdev);
3259 pci_disable_device(pdev);
3264 static void __devexit sky2_remove(struct pci_dev *pdev)
3266 struct sky2_hw *hw = pci_get_drvdata(pdev);
3267 struct net_device *dev0, *dev1;
3275 unregister_netdev(dev1);
3276 unregister_netdev(dev0);
3278 sky2_write32(hw, B0_IMSK, 0);
3279 sky2_set_power_state(hw, PCI_D3hot);
3280 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
3281 sky2_write8(hw, B0_CTST, CS_RST_SET);
3282 sky2_read8(hw, B0_CTST);
3284 free_irq(pdev->irq, hw);
3285 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3286 pci_release_regions(pdev);
3287 pci_disable_device(pdev);
3295 pci_set_drvdata(pdev, NULL);
3299 static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
3301 struct sky2_hw *hw = pci_get_drvdata(pdev);
3304 for (i = 0; i < 2; i++) {
3305 struct net_device *dev = hw->dev[i];
3308 if (!netif_running(dev))
3312 netif_device_detach(dev);
3316 return sky2_set_power_state(hw, pci_choose_state(pdev, state));
3319 static int sky2_resume(struct pci_dev *pdev)
3321 struct sky2_hw *hw = pci_get_drvdata(pdev);
3324 pci_restore_state(pdev);
3325 pci_enable_wake(pdev, PCI_D0, 0);
3326 err = sky2_set_power_state(hw, PCI_D0);
3330 err = sky2_reset(hw);
3334 for (i = 0; i < 2; i++) {
3335 struct net_device *dev = hw->dev[i];
3336 if (dev && netif_running(dev)) {
3337 netif_device_attach(dev);
3340 printk(KERN_ERR PFX "%s: could not up: %d\n",
3352 static struct pci_driver sky2_driver = {
3354 .id_table = sky2_id_table,
3355 .probe = sky2_probe,
3356 .remove = __devexit_p(sky2_remove),
3358 .suspend = sky2_suspend,
3359 .resume = sky2_resume,
3363 static int __init sky2_init_module(void)
3365 return pci_register_driver(&sky2_driver);
3368 static void __exit sky2_cleanup_module(void)
3370 pci_unregister_driver(&sky2_driver);
3373 module_init(sky2_init_module);
3374 module_exit(sky2_cleanup_module);
3376 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
3377 MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
3378 MODULE_LICENSE("GPL");
3379 MODULE_VERSION(DRV_VERSION);