2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26 #include <linux/config.h>
27 #include <linux/crc32.h>
28 #include <linux/kernel.h>
29 #include <linux/version.h>
30 #include <linux/module.h>
31 #include <linux/netdevice.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/etherdevice.h>
34 #include <linux/ethtool.h>
35 #include <linux/pci.h>
37 #include <linux/tcp.h>
39 #include <linux/delay.h>
40 #include <linux/workqueue.h>
41 #include <linux/if_vlan.h>
42 #include <linux/prefetch.h>
43 #include <linux/mii.h>
47 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
48 #define SKY2_VLAN_TAG_USED 1
53 #define DRV_NAME "sky2"
54 #define DRV_VERSION "0.15"
55 #define PFX DRV_NAME " "
58 * The Yukon II chipset takes 64 bit command blocks (called list elements)
59 * that are organized into three (receive, transmit, status) different rings
60 * similar to Tigon3. A transmit can require several elements;
61 * a receive requires one (or two if using 64 bit dma).
64 #define is_ec_a1(hw) \
65 unlikely((hw)->chip_id == CHIP_ID_YUKON_EC && \
66 (hw)->chip_rev == CHIP_REV_YU_EC_A1)
68 #define RX_LE_SIZE 512
69 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
70 #define RX_MAX_PENDING (RX_LE_SIZE/2 - 2)
71 #define RX_DEF_PENDING RX_MAX_PENDING
72 #define RX_SKB_ALIGN 8
74 #define TX_RING_SIZE 512
75 #define TX_DEF_PENDING (TX_RING_SIZE - 1)
76 #define TX_MIN_PENDING 64
77 #define MAX_SKB_TX_LE (4 + 2*MAX_SKB_FRAGS)
79 #define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
80 #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
81 #define ETH_JUMBO_MTU 9000
82 #define TX_WATCHDOG (5 * HZ)
83 #define NAPI_WEIGHT 64
84 #define PHY_RETRIES 1000
86 static const u32 default_msg =
87 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
88 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
89 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
91 static int debug = -1; /* defaults above */
92 module_param(debug, int, 0);
93 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
95 static int copybreak __read_mostly = 256;
96 module_param(copybreak, int, 0);
97 MODULE_PARM_DESC(copybreak, "Receive copy threshold");
99 static int disable_msi = 0;
100 module_param(disable_msi, int, 0);
101 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
103 static const struct pci_device_id sky2_id_table[] = {
104 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) },
105 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) },
106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) },
107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b01) },
108 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) },
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) },
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) },
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) },
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) },
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) },
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) },
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) },
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) },
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) },
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) },
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) },
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) },
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) },
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) },
126 MODULE_DEVICE_TABLE(pci, sky2_id_table);
128 /* Avoid conditionals by using array */
129 static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
130 static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
132 /* This driver supports yukon2 chipset only */
133 static const char *yukon2_name[] = {
135 "EC Ultra", /* 0xb4 */
136 "UNKNOWN", /* 0xb5 */
141 /* Access to external PHY */
142 static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
146 gma_write16(hw, port, GM_SMI_DATA, val);
147 gma_write16(hw, port, GM_SMI_CTRL,
148 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
150 for (i = 0; i < PHY_RETRIES; i++) {
151 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
156 printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
160 static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
164 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
165 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
167 for (i = 0; i < PHY_RETRIES; i++) {
168 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) {
169 *val = gma_read16(hw, port, GM_SMI_DATA);
179 static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
183 if (__gm_phy_read(hw, port, reg, &v) != 0)
184 printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
188 static int sky2_set_power_state(struct sky2_hw *hw, pci_power_t state)
195 pr_debug("sky2_set_power_state %d\n", state);
196 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
198 power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_PMC);
199 vaux = (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
200 (power_control & PCI_PM_CAP_PME_D3cold);
202 power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_CTRL);
204 power_control |= PCI_PM_CTRL_PME_STATUS;
205 power_control &= ~(PCI_PM_CTRL_STATE_MASK);
209 /* switch power to VCC (WA for VAUX problem) */
210 sky2_write8(hw, B0_POWER_CTRL,
211 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
213 /* disable Core Clock Division, */
214 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
216 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
217 /* enable bits are inverted */
218 sky2_write8(hw, B2_Y2_CLK_GATE,
219 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
220 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
221 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
223 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
225 /* Turn off phy power saving */
226 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
227 reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
229 /* looks like this XL is back asswards .. */
230 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) {
231 reg1 |= PCI_Y2_PHY1_COMA;
233 reg1 |= PCI_Y2_PHY2_COMA;
236 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
237 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
238 reg1 = sky2_pci_read32(hw, PCI_DEV_REG4);
239 reg1 &= P_ASPM_CONTROL_MSK;
240 sky2_pci_write32(hw, PCI_DEV_REG4, reg1);
241 sky2_pci_write32(hw, PCI_DEV_REG5, 0);
244 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
250 /* Turn on phy power saving */
251 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
252 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
253 reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
255 reg1 |= (PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
256 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
258 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
259 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
261 /* enable bits are inverted */
262 sky2_write8(hw, B2_Y2_CLK_GATE,
263 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
264 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
265 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
267 /* switch power to VAUX */
268 if (vaux && state != PCI_D3cold)
269 sky2_write8(hw, B0_POWER_CTRL,
270 (PC_VAUX_ENA | PC_VCC_ENA |
271 PC_VAUX_ON | PC_VCC_OFF));
274 printk(KERN_ERR PFX "Unknown power state %d\n", state);
278 sky2_pci_write16(hw, hw->pm_cap + PCI_PM_CTRL, power_control);
279 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
283 static void sky2_phy_reset(struct sky2_hw *hw, unsigned port)
287 /* disable all GMAC IRQ's */
288 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
289 /* disable PHY IRQs */
290 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
292 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
293 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
294 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
295 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
297 reg = gma_read16(hw, port, GM_RX_CTRL);
298 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
299 gma_write16(hw, port, GM_RX_CTRL, reg);
302 static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
304 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
305 u16 ctrl, ct1000, adv, pg, ledctrl, ledover;
307 if (sky2->autoneg == AUTONEG_ENABLE && hw->chip_id != CHIP_ID_YUKON_XL) {
308 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
310 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
312 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
314 if (hw->chip_id == CHIP_ID_YUKON_EC)
315 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
317 ectrl |= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3);
319 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
322 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
324 if (hw->chip_id == CHIP_ID_YUKON_FE) {
325 /* enable automatic crossover */
326 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
328 /* disable energy detect */
329 ctrl &= ~PHY_M_PC_EN_DET_MSK;
331 /* enable automatic crossover */
332 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
334 if (sky2->autoneg == AUTONEG_ENABLE &&
335 hw->chip_id == CHIP_ID_YUKON_XL) {
336 ctrl &= ~PHY_M_PC_DSC_MSK;
337 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
340 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
342 /* workaround for deviation #4.88 (CRC errors) */
343 /* disable Automatic Crossover */
345 ctrl &= ~PHY_M_PC_MDIX_MSK;
346 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
348 if (hw->chip_id == CHIP_ID_YUKON_XL) {
349 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
350 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
351 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
352 ctrl &= ~PHY_M_MAC_MD_MSK;
353 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
354 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
356 /* select page 1 to access Fiber registers */
357 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
361 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
362 if (sky2->autoneg == AUTONEG_DISABLE)
367 ctrl |= PHY_CT_RESET;
368 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
374 if (sky2->autoneg == AUTONEG_ENABLE) {
376 if (sky2->advertising & ADVERTISED_1000baseT_Full)
377 ct1000 |= PHY_M_1000C_AFD;
378 if (sky2->advertising & ADVERTISED_1000baseT_Half)
379 ct1000 |= PHY_M_1000C_AHD;
380 if (sky2->advertising & ADVERTISED_100baseT_Full)
381 adv |= PHY_M_AN_100_FD;
382 if (sky2->advertising & ADVERTISED_100baseT_Half)
383 adv |= PHY_M_AN_100_HD;
384 if (sky2->advertising & ADVERTISED_10baseT_Full)
385 adv |= PHY_M_AN_10_FD;
386 if (sky2->advertising & ADVERTISED_10baseT_Half)
387 adv |= PHY_M_AN_10_HD;
388 } else /* special defines for FIBER (88E1011S only) */
389 adv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD;
391 /* Set Flow-control capabilities */
392 if (sky2->tx_pause && sky2->rx_pause)
393 adv |= PHY_AN_PAUSE_CAP; /* symmetric */
394 else if (sky2->rx_pause && !sky2->tx_pause)
395 adv |= PHY_AN_PAUSE_ASYM | PHY_AN_PAUSE_CAP;
396 else if (!sky2->rx_pause && sky2->tx_pause)
397 adv |= PHY_AN_PAUSE_ASYM; /* local */
399 /* Restart Auto-negotiation */
400 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
402 /* forced speed/duplex settings */
403 ct1000 = PHY_M_1000C_MSE;
405 if (sky2->duplex == DUPLEX_FULL)
406 ctrl |= PHY_CT_DUP_MD;
408 switch (sky2->speed) {
410 ctrl |= PHY_CT_SP1000;
413 ctrl |= PHY_CT_SP100;
417 ctrl |= PHY_CT_RESET;
420 if (hw->chip_id != CHIP_ID_YUKON_FE)
421 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
423 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
424 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
426 /* Setup Phy LED's */
427 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
430 switch (hw->chip_id) {
431 case CHIP_ID_YUKON_FE:
432 /* on 88E3082 these bits are at 11..9 (shifted left) */
433 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
435 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
437 /* delete ACT LED control bits */
438 ctrl &= ~PHY_M_FELP_LED1_MSK;
439 /* change ACT LED control to blink mode */
440 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
441 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
444 case CHIP_ID_YUKON_XL:
445 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
447 /* select page 3 to access LED control register */
448 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
450 /* set LED Function Control register */
451 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
452 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
453 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
454 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
456 /* set Polarity Control register */
457 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
458 (PHY_M_POLC_LS1_P_MIX(4) |
459 PHY_M_POLC_IS0_P_MIX(4) |
460 PHY_M_POLC_LOS_CTRL(2) |
461 PHY_M_POLC_INIT_CTRL(2) |
462 PHY_M_POLC_STA1_CTRL(2) |
463 PHY_M_POLC_STA0_CTRL(2)));
465 /* restore page register */
466 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
470 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
471 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
472 /* turn off the Rx LED (LED_RX) */
473 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
476 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev >= 2) {
477 /* apply fixes in PHY AFE */
478 gm_phy_write(hw, port, 22, 255);
479 /* increase differential signal amplitude in 10BASE-T */
480 gm_phy_write(hw, port, 24, 0xaa99);
481 gm_phy_write(hw, port, 23, 0x2011);
483 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
484 gm_phy_write(hw, port, 24, 0xa204);
485 gm_phy_write(hw, port, 23, 0x2002);
487 /* set page register to 0 */
488 gm_phy_write(hw, port, 22, 0);
490 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
492 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
493 /* turn on 100 Mbps LED (LED_LINK100) */
494 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
498 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
501 /* Enable phy interrupt on auto-negotiation complete (or link up) */
502 if (sky2->autoneg == AUTONEG_ENABLE)
503 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
505 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
508 /* Force a renegotiation */
509 static void sky2_phy_reinit(struct sky2_port *sky2)
511 down(&sky2->phy_sema);
512 sky2_phy_init(sky2->hw, sky2->port);
516 static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
518 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
521 const u8 *addr = hw->dev[port]->dev_addr;
523 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
524 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR|GPC_ENA_PAUSE);
526 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
528 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
529 /* WA DEV_472 -- looks like crossed wires on port 2 */
530 /* clear GMAC 1 Control reset */
531 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
533 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
534 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
535 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
536 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
537 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
540 if (sky2->autoneg == AUTONEG_DISABLE) {
541 reg = gma_read16(hw, port, GM_GP_CTRL);
542 reg |= GM_GPCR_AU_ALL_DIS;
543 gma_write16(hw, port, GM_GP_CTRL, reg);
544 gma_read16(hw, port, GM_GP_CTRL);
546 switch (sky2->speed) {
548 reg &= ~GM_GPCR_SPEED_100;
549 reg |= GM_GPCR_SPEED_1000;
552 reg &= ~GM_GPCR_SPEED_1000;
553 reg |= GM_GPCR_SPEED_100;
556 reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
560 if (sky2->duplex == DUPLEX_FULL)
561 reg |= GM_GPCR_DUP_FULL;
563 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
565 if (!sky2->tx_pause && !sky2->rx_pause) {
566 sky2_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
568 GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
569 } else if (sky2->tx_pause && !sky2->rx_pause) {
570 /* disable Rx flow-control */
571 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
574 gma_write16(hw, port, GM_GP_CTRL, reg);
576 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
578 down(&sky2->phy_sema);
579 sky2_phy_init(hw, port);
583 reg = gma_read16(hw, port, GM_PHY_ADDR);
584 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
586 for (i = 0; i < GM_MIB_CNT_SIZE; i++)
587 gma_read16(hw, port, GM_MIB_CNT_BASE + 8 * i);
588 gma_write16(hw, port, GM_PHY_ADDR, reg);
590 /* transmit control */
591 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
593 /* receive control reg: unicast + multicast + no FCS */
594 gma_write16(hw, port, GM_RX_CTRL,
595 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
597 /* transmit flow control */
598 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
600 /* transmit parameter */
601 gma_write16(hw, port, GM_TX_PARAM,
602 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
603 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
604 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
605 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
607 /* serial mode register */
608 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
609 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
611 if (hw->dev[port]->mtu > ETH_DATA_LEN)
612 reg |= GM_SMOD_JUMBO_ENA;
614 gma_write16(hw, port, GM_SERIAL_MODE, reg);
616 /* virtual address for data */
617 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
619 /* physical address: used for pause frames */
620 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
622 /* ignore counter overflows */
623 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
624 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
625 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
627 /* Configure Rx MAC FIFO */
628 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
629 sky2_write16(hw, SK_REG(port, RX_GMF_CTRL_T),
632 /* Flush Rx MAC FIFO on any flow control or error */
633 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
635 /* Set threshold to 0xa (64 bytes)
636 * ASF disabled so no need to do WA dev #4.30
638 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF);
640 /* Configure Tx MAC FIFO */
641 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
642 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
644 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
645 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
646 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
647 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
648 /* set Tx GMAC FIFO Almost Empty Threshold */
649 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR), 0x180);
650 /* Disable Store & Forward mode for TX */
651 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
657 /* Assign Ram Buffer allocation.
658 * start and end are in units of 4k bytes
659 * ram registers are in units of 64bit words
661 static void sky2_ramset(struct sky2_hw *hw, u16 q, u8 startk, u8 endk)
665 start = startk * 4096/8;
666 end = (endk * 4096/8) - 1;
668 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
669 sky2_write32(hw, RB_ADDR(q, RB_START), start);
670 sky2_write32(hw, RB_ADDR(q, RB_END), end);
671 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
672 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
674 if (q == Q_R1 || q == Q_R2) {
675 u32 space = (endk - startk) * 4096/8;
676 u32 tp = space - space/4;
678 /* On receive queue's set the thresholds
679 * give receiver priority when > 3/4 full
680 * send pause when down to 2K
682 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
683 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
686 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
687 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
689 /* Enable store & forward on Tx queue's because
690 * Tx FIFO is only 1K on Yukon
692 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
695 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
696 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
699 /* Setup Bus Memory Interface */
700 static void sky2_qset(struct sky2_hw *hw, u16 q)
702 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
703 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
704 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
705 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
708 /* Setup prefetch unit registers. This is the interface between
709 * hardware and driver list elements
711 static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
714 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
715 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
716 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
717 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
718 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
719 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
721 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
724 static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
726 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
728 sky2->tx_prod = (sky2->tx_prod + 1) % TX_RING_SIZE;
733 * This is a workaround code taken from SysKonnect sk98lin driver
734 * to deal with chip bug on Yukon EC rev 0 in the wraparound case.
736 static void sky2_put_idx(struct sky2_hw *hw, unsigned q,
737 u16 idx, u16 *last, u16 size)
740 if (is_ec_a1(hw) && idx < *last) {
741 u16 hwget = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
744 /* Start prefetching again */
745 sky2_write8(hw, Y2_QADDR(q, PREF_UNIT_FIFO_WM), 0xe0);
749 if (hwget == size - 1) {
750 /* set watermark to one list element */
751 sky2_write8(hw, Y2_QADDR(q, PREF_UNIT_FIFO_WM), 8);
753 /* set put index to first list element */
754 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), 0);
755 } else /* have hardware go to end of list */
756 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX),
760 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
767 static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
769 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
770 sky2->rx_put = (sky2->rx_put + 1) % RX_LE_SIZE;
774 /* Return high part of DMA address (could be 32 or 64 bit) */
775 static inline u32 high32(dma_addr_t a)
777 return sizeof(a) > sizeof(u32) ? (a >> 16) >> 16 : 0;
780 /* Build description to hardware about buffer */
781 static void sky2_rx_add(struct sky2_port *sky2, dma_addr_t map)
783 struct sky2_rx_le *le;
784 u32 hi = high32(map);
785 u16 len = sky2->rx_bufsize;
787 if (sky2->rx_addr64 != hi) {
788 le = sky2_next_rx(sky2);
789 le->addr = cpu_to_le32(hi);
791 le->opcode = OP_ADDR64 | HW_OWNER;
792 sky2->rx_addr64 = high32(map + len);
795 le = sky2_next_rx(sky2);
796 le->addr = cpu_to_le32((u32) map);
797 le->length = cpu_to_le16(len);
799 le->opcode = OP_PACKET | HW_OWNER;
803 /* Tell chip where to start receive checksum.
804 * Actually has two checksums, but set both same to avoid possible byte
807 static void rx_set_checksum(struct sky2_port *sky2)
809 struct sky2_rx_le *le;
811 le = sky2_next_rx(sky2);
812 le->addr = (ETH_HLEN << 16) | ETH_HLEN;
814 le->opcode = OP_TCPSTART | HW_OWNER;
816 sky2_write32(sky2->hw,
817 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
818 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
823 * The RX Stop command will not work for Yukon-2 if the BMU does not
824 * reach the end of packet and since we can't make sure that we have
825 * incoming data, we must reset the BMU while it is not doing a DMA
826 * transfer. Since it is possible that the RX path is still active,
827 * the RX RAM buffer will be stopped first, so any possible incoming
828 * data will not trigger a DMA. After the RAM buffer is stopped, the
829 * BMU is polled until any DMA in progress is ended and only then it
832 static void sky2_rx_stop(struct sky2_port *sky2)
834 struct sky2_hw *hw = sky2->hw;
835 unsigned rxq = rxqaddr[sky2->port];
838 /* disable the RAM Buffer receive queue */
839 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
841 for (i = 0; i < 0xffff; i++)
842 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
843 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
846 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
849 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
851 /* reset the Rx prefetch unit */
852 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
855 /* Clean out receive buffer area, assumes receiver hardware stopped */
856 static void sky2_rx_clean(struct sky2_port *sky2)
860 memset(sky2->rx_le, 0, RX_LE_BYTES);
861 for (i = 0; i < sky2->rx_pending; i++) {
862 struct ring_info *re = sky2->rx_ring + i;
865 pci_unmap_single(sky2->hw->pdev,
866 re->mapaddr, sky2->rx_bufsize,
874 /* Basic MII support */
875 static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
877 struct mii_ioctl_data *data = if_mii(ifr);
878 struct sky2_port *sky2 = netdev_priv(dev);
879 struct sky2_hw *hw = sky2->hw;
880 int err = -EOPNOTSUPP;
882 if (!netif_running(dev))
883 return -ENODEV; /* Phy still in reset */
887 data->phy_id = PHY_ADDR_MARV;
893 down(&sky2->phy_sema);
894 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
902 if (!capable(CAP_NET_ADMIN))
905 down(&sky2->phy_sema);
906 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
914 #ifdef SKY2_VLAN_TAG_USED
915 static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
917 struct sky2_port *sky2 = netdev_priv(dev);
918 struct sky2_hw *hw = sky2->hw;
919 u16 port = sky2->port;
921 spin_lock_bh(&sky2->tx_lock);
923 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_ON);
924 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_ON);
927 spin_unlock_bh(&sky2->tx_lock);
930 static void sky2_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
932 struct sky2_port *sky2 = netdev_priv(dev);
933 struct sky2_hw *hw = sky2->hw;
934 u16 port = sky2->port;
936 spin_lock_bh(&sky2->tx_lock);
938 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_OFF);
939 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_OFF);
941 sky2->vlgrp->vlan_devices[vid] = NULL;
943 spin_unlock_bh(&sky2->tx_lock);
948 * It appears the hardware has a bug in the FIFO logic that
949 * cause it to hang if the FIFO gets overrun and the receive buffer
950 * is not aligned. ALso alloc_skb() won't align properly if slab
951 * debugging is enabled.
953 static inline struct sk_buff *sky2_alloc_skb(unsigned int size, gfp_t gfp_mask)
957 skb = alloc_skb(size + RX_SKB_ALIGN, gfp_mask);
959 unsigned long p = (unsigned long) skb->data;
961 ((p + RX_SKB_ALIGN - 1) & ~(RX_SKB_ALIGN - 1)) - p);
968 * Allocate and setup receiver buffer pool.
969 * In case of 64 bit dma, there are 2X as many list elements
970 * available as ring entries
971 * and need to reserve one list element so we don't wrap around.
973 static int sky2_rx_start(struct sky2_port *sky2)
975 struct sky2_hw *hw = sky2->hw;
976 unsigned rxq = rxqaddr[sky2->port];
979 sky2->rx_put = sky2->rx_next = 0;
982 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev >= 2) {
983 /* MAC Rx RAM Read is controlled by hardware */
984 sky2_write32(hw, Q_ADDR(rxq, Q_F), F_M_RX_RAM_DIS);
987 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
989 rx_set_checksum(sky2);
990 for (i = 0; i < sky2->rx_pending; i++) {
991 struct ring_info *re = sky2->rx_ring + i;
993 re->skb = sky2_alloc_skb(sky2->rx_bufsize, GFP_KERNEL);
997 re->mapaddr = pci_map_single(hw->pdev, re->skb->data,
998 sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
999 sky2_rx_add(sky2, re->mapaddr);
1002 /* Tell chip about available buffers */
1003 sky2_write16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX), sky2->rx_put);
1004 sky2->rx_last_put = sky2_read16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX));
1007 sky2_rx_clean(sky2);
1011 /* Bring up network interface. */
1012 static int sky2_up(struct net_device *dev)
1014 struct sky2_port *sky2 = netdev_priv(dev);
1015 struct sky2_hw *hw = sky2->hw;
1016 unsigned port = sky2->port;
1017 u32 ramsize, rxspace;
1020 if (netif_msg_ifup(sky2))
1021 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1023 /* must be power of 2 */
1024 sky2->tx_le = pci_alloc_consistent(hw->pdev,
1026 sizeof(struct sky2_tx_le),
1031 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
1035 sky2->tx_prod = sky2->tx_cons = 0;
1037 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1041 memset(sky2->rx_le, 0, RX_LE_BYTES);
1043 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct ring_info),
1048 sky2_mac_init(hw, port);
1050 /* Determine available ram buffer space (in 4K blocks).
1051 * Note: not sure about the FE setting below yet
1053 if (hw->chip_id == CHIP_ID_YUKON_FE)
1056 ramsize = sky2_read8(hw, B2_E_0);
1058 /* Give transmitter one third (rounded up) */
1059 rxspace = ramsize - (ramsize + 2) / 3;
1061 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1062 sky2_ramset(hw, txqaddr[port], rxspace, ramsize);
1064 /* Make sure SyncQ is disabled */
1065 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1068 sky2_qset(hw, txqaddr[port]);
1070 /* Set almost empty threshold */
1071 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev == 1)
1072 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), 0x1a0);
1074 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1077 err = sky2_rx_start(sky2);
1081 /* Enable interrupts from phy/mac for port */
1082 spin_lock_irq(&hw->hw_lock);
1083 hw->intr_mask |= (port == 0) ? Y2_IS_PORT_1 : Y2_IS_PORT_2;
1084 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1085 spin_unlock_irq(&hw->hw_lock);
1090 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1091 sky2->rx_le, sky2->rx_le_map);
1095 pci_free_consistent(hw->pdev,
1096 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1097 sky2->tx_le, sky2->tx_le_map);
1100 kfree(sky2->tx_ring);
1101 kfree(sky2->rx_ring);
1103 sky2->tx_ring = NULL;
1104 sky2->rx_ring = NULL;
1108 /* Modular subtraction in ring */
1109 static inline int tx_dist(unsigned tail, unsigned head)
1111 return (head - tail) % TX_RING_SIZE;
1114 /* Number of list elements available for next tx */
1115 static inline int tx_avail(const struct sky2_port *sky2)
1117 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
1120 /* Estimate of number of transmit list elements required */
1121 static unsigned tx_le_req(const struct sk_buff *skb)
1125 count = sizeof(dma_addr_t) / sizeof(u32);
1126 count += skb_shinfo(skb)->nr_frags * count;
1128 if (skb_shinfo(skb)->tso_size)
1131 if (skb->ip_summed == CHECKSUM_HW)
1138 * Put one packet in ring for transmit.
1139 * A single packet can generate multiple list elements, and
1140 * the number of ring elements will probably be less than the number
1141 * of list elements used.
1143 * No BH disabling for tx_lock here (like tg3)
1145 static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1147 struct sky2_port *sky2 = netdev_priv(dev);
1148 struct sky2_hw *hw = sky2->hw;
1149 struct sky2_tx_le *le = NULL;
1150 struct tx_ring_info *re;
1157 /* No BH disabling for tx_lock here. We are running in BH disabled
1158 * context and TX reclaim runs via poll inside of a software
1159 * interrupt, and no related locks in IRQ processing.
1161 if (!spin_trylock(&sky2->tx_lock))
1162 return NETDEV_TX_LOCKED;
1164 if (unlikely(tx_avail(sky2) < tx_le_req(skb))) {
1165 /* There is a known but harmless race with lockless tx
1166 * and netif_stop_queue.
1168 if (!netif_queue_stopped(dev)) {
1169 netif_stop_queue(dev);
1170 if (net_ratelimit())
1171 printk(KERN_WARNING PFX "%s: ring full when queue awake!\n",
1174 spin_unlock(&sky2->tx_lock);
1176 return NETDEV_TX_BUSY;
1179 if (unlikely(netif_msg_tx_queued(sky2)))
1180 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1181 dev->name, sky2->tx_prod, skb->len);
1183 len = skb_headlen(skb);
1184 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
1185 addr64 = high32(mapping);
1187 re = sky2->tx_ring + sky2->tx_prod;
1189 /* Send high bits if changed or crosses boundary */
1190 if (addr64 != sky2->tx_addr64 || high32(mapping + len) != sky2->tx_addr64) {
1191 le = get_tx_le(sky2);
1192 le->tx.addr = cpu_to_le32(addr64);
1194 le->opcode = OP_ADDR64 | HW_OWNER;
1195 sky2->tx_addr64 = high32(mapping + len);
1198 /* Check for TCP Segmentation Offload */
1199 mss = skb_shinfo(skb)->tso_size;
1201 /* just drop the packet if non-linear expansion fails */
1202 if (skb_header_cloned(skb) &&
1203 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
1204 dev_kfree_skb_any(skb);
1208 mss += ((skb->h.th->doff - 5) * 4); /* TCP options */
1209 mss += (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
1213 if (mss != sky2->tx_last_mss) {
1214 le = get_tx_le(sky2);
1215 le->tx.tso.size = cpu_to_le16(mss);
1216 le->tx.tso.rsvd = 0;
1217 le->opcode = OP_LRGLEN | HW_OWNER;
1219 sky2->tx_last_mss = mss;
1223 #ifdef SKY2_VLAN_TAG_USED
1224 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1225 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1227 le = get_tx_le(sky2);
1229 le->opcode = OP_VLAN|HW_OWNER;
1232 le->opcode |= OP_VLAN;
1233 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1238 /* Handle TCP checksum offload */
1239 if (skb->ip_summed == CHECKSUM_HW) {
1240 u16 hdr = skb->h.raw - skb->data;
1241 u16 offset = hdr + skb->csum;
1243 ctrl = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1244 if (skb->nh.iph->protocol == IPPROTO_UDP)
1247 le = get_tx_le(sky2);
1248 le->tx.csum.start = cpu_to_le16(hdr);
1249 le->tx.csum.offset = cpu_to_le16(offset);
1250 le->length = 0; /* initial checksum value */
1251 le->ctrl = 1; /* one packet */
1252 le->opcode = OP_TCPLISW | HW_OWNER;
1255 le = get_tx_le(sky2);
1256 le->tx.addr = cpu_to_le32((u32) mapping);
1257 le->length = cpu_to_le16(len);
1259 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
1261 /* Record the transmit mapping info */
1263 pci_unmap_addr_set(re, mapaddr, mapping);
1265 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1266 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1267 struct tx_ring_info *fre;
1269 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1270 frag->size, PCI_DMA_TODEVICE);
1271 addr64 = high32(mapping);
1272 if (addr64 != sky2->tx_addr64) {
1273 le = get_tx_le(sky2);
1274 le->tx.addr = cpu_to_le32(addr64);
1276 le->opcode = OP_ADDR64 | HW_OWNER;
1277 sky2->tx_addr64 = addr64;
1280 le = get_tx_le(sky2);
1281 le->tx.addr = cpu_to_le32((u32) mapping);
1282 le->length = cpu_to_le16(frag->size);
1284 le->opcode = OP_BUFFER | HW_OWNER;
1287 + ((re - sky2->tx_ring) + i + 1) % TX_RING_SIZE;
1288 pci_unmap_addr_set(fre, mapaddr, mapping);
1291 re->idx = sky2->tx_prod;
1294 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod,
1295 &sky2->tx_last_put, TX_RING_SIZE);
1297 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1298 netif_stop_queue(dev);
1301 spin_unlock(&sky2->tx_lock);
1303 dev->trans_start = jiffies;
1304 return NETDEV_TX_OK;
1308 * Free ring elements from starting at tx_cons until "done"
1310 * NB: the hardware will tell us about partial completion of multi-part
1311 * buffers; these are deferred until completion.
1313 static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
1315 struct net_device *dev = sky2->netdev;
1316 struct pci_dev *pdev = sky2->hw->pdev;
1320 BUG_ON(done >= TX_RING_SIZE);
1322 if (unlikely(netif_msg_tx_done(sky2)))
1323 printk(KERN_DEBUG "%s: tx done, up to %u\n",
1326 for (put = sky2->tx_cons; put != done; put = nxt) {
1327 struct tx_ring_info *re = sky2->tx_ring + put;
1328 struct sk_buff *skb = re->skb;
1331 BUG_ON(nxt >= TX_RING_SIZE);
1332 prefetch(sky2->tx_ring + nxt);
1334 /* Check for partial status */
1335 if (tx_dist(put, done) < tx_dist(put, nxt))
1339 pci_unmap_single(pdev, pci_unmap_addr(re, mapaddr),
1340 skb_headlen(skb), PCI_DMA_TODEVICE);
1342 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1343 struct tx_ring_info *fre;
1344 fre = sky2->tx_ring + (put + i + 1) % TX_RING_SIZE;
1345 pci_unmap_page(pdev, pci_unmap_addr(fre, mapaddr),
1346 skb_shinfo(skb)->frags[i].size,
1350 dev_kfree_skb_any(skb);
1353 sky2->tx_cons = put;
1354 if (netif_queue_stopped(dev) && tx_avail(sky2) > MAX_SKB_TX_LE)
1355 netif_wake_queue(dev);
1358 /* Cleanup all untransmitted buffers, assume transmitter not running */
1359 static void sky2_tx_clean(struct sky2_port *sky2)
1361 spin_lock_bh(&sky2->tx_lock);
1362 sky2_tx_complete(sky2, sky2->tx_prod);
1363 spin_unlock_bh(&sky2->tx_lock);
1366 /* Network shutdown */
1367 static int sky2_down(struct net_device *dev)
1369 struct sky2_port *sky2 = netdev_priv(dev);
1370 struct sky2_hw *hw = sky2->hw;
1371 unsigned port = sky2->port;
1374 /* Never really got started! */
1378 if (netif_msg_ifdown(sky2))
1379 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1381 /* Stop more packets from being queued */
1382 netif_stop_queue(dev);
1384 /* Disable port IRQ */
1385 spin_lock_irq(&hw->hw_lock);
1386 hw->intr_mask &= ~((sky2->port == 0) ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2);
1387 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1388 spin_unlock_irq(&hw->hw_lock);
1390 flush_scheduled_work();
1392 sky2_phy_reset(hw, port);
1394 /* Stop transmitter */
1395 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1396 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1398 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
1399 RB_RST_SET | RB_DIS_OP_MD);
1401 ctrl = gma_read16(hw, port, GM_GP_CTRL);
1402 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
1403 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1405 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1407 /* Workaround shared GMAC reset */
1408 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1409 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
1410 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1412 /* Disable Force Sync bit and Enable Alloc bit */
1413 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1414 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1416 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1417 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1418 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1420 /* Reset the PCI FIFO of the async Tx queue */
1421 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1422 BMU_RST_SET | BMU_FIFO_RST);
1424 /* Reset the Tx prefetch units */
1425 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1428 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1432 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1433 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1435 /* turn off LED's */
1436 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1438 synchronize_irq(hw->pdev->irq);
1440 sky2_tx_clean(sky2);
1441 sky2_rx_clean(sky2);
1443 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1444 sky2->rx_le, sky2->rx_le_map);
1445 kfree(sky2->rx_ring);
1447 pci_free_consistent(hw->pdev,
1448 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1449 sky2->tx_le, sky2->tx_le_map);
1450 kfree(sky2->tx_ring);
1455 sky2->rx_ring = NULL;
1456 sky2->tx_ring = NULL;
1461 static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1466 if (hw->chip_id == CHIP_ID_YUKON_FE)
1467 return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10;
1469 switch (aux & PHY_M_PS_SPEED_MSK) {
1470 case PHY_M_PS_SPEED_1000:
1472 case PHY_M_PS_SPEED_100:
1479 static void sky2_link_up(struct sky2_port *sky2)
1481 struct sky2_hw *hw = sky2->hw;
1482 unsigned port = sky2->port;
1485 /* Enable Transmit FIFO Underrun */
1486 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
1488 reg = gma_read16(hw, port, GM_GP_CTRL);
1489 if (sky2->autoneg == AUTONEG_DISABLE) {
1490 reg |= GM_GPCR_AU_ALL_DIS;
1492 /* Is write/read necessary? Copied from sky2_mac_init */
1493 gma_write16(hw, port, GM_GP_CTRL, reg);
1494 gma_read16(hw, port, GM_GP_CTRL);
1496 switch (sky2->speed) {
1498 reg &= ~GM_GPCR_SPEED_100;
1499 reg |= GM_GPCR_SPEED_1000;
1502 reg &= ~GM_GPCR_SPEED_1000;
1503 reg |= GM_GPCR_SPEED_100;
1506 reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
1510 reg &= ~GM_GPCR_AU_ALL_DIS;
1512 if (sky2->duplex == DUPLEX_FULL || sky2->autoneg == AUTONEG_ENABLE)
1513 reg |= GM_GPCR_DUP_FULL;
1516 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1517 gma_write16(hw, port, GM_GP_CTRL, reg);
1518 gma_read16(hw, port, GM_GP_CTRL);
1520 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1522 netif_carrier_on(sky2->netdev);
1523 netif_wake_queue(sky2->netdev);
1525 /* Turn on link LED */
1526 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
1527 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1529 if (hw->chip_id == CHIP_ID_YUKON_XL) {
1530 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
1532 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
1533 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
1534 PHY_M_LEDC_INIT_CTRL(sky2->speed ==
1536 PHY_M_LEDC_STA1_CTRL(sky2->speed ==
1537 SPEED_100 ? 7 : 0) |
1538 PHY_M_LEDC_STA0_CTRL(sky2->speed ==
1539 SPEED_1000 ? 7 : 0));
1540 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
1543 if (netif_msg_link(sky2))
1544 printk(KERN_INFO PFX
1545 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
1546 sky2->netdev->name, sky2->speed,
1547 sky2->duplex == DUPLEX_FULL ? "full" : "half",
1548 (sky2->tx_pause && sky2->rx_pause) ? "both" :
1549 sky2->tx_pause ? "tx" : sky2->rx_pause ? "rx" : "none");
1552 static void sky2_link_down(struct sky2_port *sky2)
1554 struct sky2_hw *hw = sky2->hw;
1555 unsigned port = sky2->port;
1558 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1560 reg = gma_read16(hw, port, GM_GP_CTRL);
1561 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1562 gma_write16(hw, port, GM_GP_CTRL, reg);
1563 gma_read16(hw, port, GM_GP_CTRL); /* PCI post */
1565 if (sky2->rx_pause && !sky2->tx_pause) {
1566 /* restore Asymmetric Pause bit */
1567 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
1568 gm_phy_read(hw, port, PHY_MARV_AUNE_ADV)
1572 netif_carrier_off(sky2->netdev);
1573 netif_stop_queue(sky2->netdev);
1575 /* Turn on link LED */
1576 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1578 if (netif_msg_link(sky2))
1579 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
1580 sky2_phy_init(hw, port);
1583 static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1585 struct sky2_hw *hw = sky2->hw;
1586 unsigned port = sky2->port;
1589 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
1591 if (lpa & PHY_M_AN_RF) {
1592 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1596 if (hw->chip_id != CHIP_ID_YUKON_FE &&
1597 gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
1598 printk(KERN_ERR PFX "%s: master/slave fault",
1599 sky2->netdev->name);
1603 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1604 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1605 sky2->netdev->name);
1609 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1611 sky2->speed = sky2_phy_speed(hw, aux);
1613 /* Pause bits are offset (9..8) */
1614 if (hw->chip_id == CHIP_ID_YUKON_XL)
1617 sky2->rx_pause = (aux & PHY_M_PS_RX_P_EN) != 0;
1618 sky2->tx_pause = (aux & PHY_M_PS_TX_P_EN) != 0;
1620 if ((sky2->tx_pause || sky2->rx_pause)
1621 && !(sky2->speed < SPEED_1000 && sky2->duplex == DUPLEX_HALF))
1622 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1624 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1630 * Interrupt from PHY are handled outside of interrupt context
1631 * because accessing phy registers requires spin wait which might
1632 * cause excess interrupt latency.
1634 static void sky2_phy_task(void *arg)
1636 struct sky2_port *sky2 = arg;
1637 struct sky2_hw *hw = sky2->hw;
1638 u16 istatus, phystat;
1640 down(&sky2->phy_sema);
1641 istatus = gm_phy_read(hw, sky2->port, PHY_MARV_INT_STAT);
1642 phystat = gm_phy_read(hw, sky2->port, PHY_MARV_PHY_STAT);
1644 if (netif_msg_intr(sky2))
1645 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1646 sky2->netdev->name, istatus, phystat);
1648 if (istatus & PHY_M_IS_AN_COMPL) {
1649 if (sky2_autoneg_done(sky2, phystat) == 0)
1654 if (istatus & PHY_M_IS_LSP_CHANGE)
1655 sky2->speed = sky2_phy_speed(hw, phystat);
1657 if (istatus & PHY_M_IS_DUP_CHANGE)
1659 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1661 if (istatus & PHY_M_IS_LST_CHANGE) {
1662 if (phystat & PHY_M_PS_LINK_UP)
1665 sky2_link_down(sky2);
1668 up(&sky2->phy_sema);
1670 spin_lock_irq(&hw->hw_lock);
1671 hw->intr_mask |= (sky2->port == 0) ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2;
1672 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1673 spin_unlock_irq(&hw->hw_lock);
1677 /* Transmit timeout is only called if we are running, carries is up
1678 * and tx queue is full (stopped).
1680 static void sky2_tx_timeout(struct net_device *dev)
1682 struct sky2_port *sky2 = netdev_priv(dev);
1683 struct sky2_hw *hw = sky2->hw;
1684 unsigned txq = txqaddr[sky2->port];
1687 /* Maybe we just missed an status interrupt */
1688 spin_lock(&sky2->tx_lock);
1689 ridx = sky2_read16(hw,
1690 sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX);
1691 sky2_tx_complete(sky2, ridx);
1692 spin_unlock(&sky2->tx_lock);
1694 if (!netif_queue_stopped(dev)) {
1695 if (net_ratelimit())
1696 pr_info(PFX "transmit interrupt missed? recovered\n");
1700 if (netif_msg_timer(sky2))
1701 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1703 sky2_write32(hw, Q_ADDR(txq, Q_CSR), BMU_STOP);
1704 sky2_write32(hw, Y2_QADDR(txq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1706 sky2_tx_clean(sky2);
1709 sky2_prefetch_init(hw, txq, sky2->tx_le_map, TX_RING_SIZE - 1);
1713 #define roundup(x, y) ((((x)+((y)-1))/(y))*(y))
1714 /* Want receive buffer size to be multiple of 64 bits, and incl room for vlan */
1715 static inline unsigned sky2_buf_size(int mtu)
1717 return roundup(mtu + ETH_HLEN + 4, 8);
1720 static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1722 struct sky2_port *sky2 = netdev_priv(dev);
1723 struct sky2_hw *hw = sky2->hw;
1727 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
1730 if (hw->chip_id == CHIP_ID_YUKON_EC_U && new_mtu > ETH_DATA_LEN)
1733 if (!netif_running(dev)) {
1738 sky2_write32(hw, B0_IMSK, 0);
1740 dev->trans_start = jiffies; /* prevent tx timeout */
1741 netif_stop_queue(dev);
1742 netif_poll_disable(hw->dev[0]);
1744 ctl = gma_read16(hw, sky2->port, GM_GP_CTRL);
1745 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
1747 sky2_rx_clean(sky2);
1750 sky2->rx_bufsize = sky2_buf_size(new_mtu);
1751 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
1752 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1754 if (dev->mtu > ETH_DATA_LEN)
1755 mode |= GM_SMOD_JUMBO_ENA;
1757 gma_write16(hw, sky2->port, GM_SERIAL_MODE, mode);
1759 sky2_write8(hw, RB_ADDR(rxqaddr[sky2->port], RB_CTRL), RB_ENA_OP_MD);
1761 err = sky2_rx_start(sky2);
1762 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1767 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl);
1769 netif_poll_enable(hw->dev[0]);
1770 netif_wake_queue(dev);
1777 * Receive one packet.
1778 * For small packets or errors, just reuse existing skb.
1779 * For larger packets, get new buffer.
1781 static struct sk_buff *sky2_receive(struct sky2_port *sky2,
1782 u16 length, u32 status)
1784 struct ring_info *re = sky2->rx_ring + sky2->rx_next;
1785 struct sk_buff *skb = NULL;
1787 if (unlikely(netif_msg_rx_status(sky2)))
1788 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
1789 sky2->netdev->name, sky2->rx_next, status, length);
1791 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
1792 prefetch(sky2->rx_ring + sky2->rx_next);
1794 if (status & GMR_FS_ANY_ERR)
1797 if (!(status & GMR_FS_RX_OK))
1800 if ((status >> 16) != length || length > sky2->rx_bufsize)
1803 if (length < copybreak) {
1804 skb = alloc_skb(length + 2, GFP_ATOMIC);
1808 skb_reserve(skb, 2);
1809 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->mapaddr,
1810 length, PCI_DMA_FROMDEVICE);
1811 memcpy(skb->data, re->skb->data, length);
1812 skb->ip_summed = re->skb->ip_summed;
1813 skb->csum = re->skb->csum;
1814 pci_dma_sync_single_for_device(sky2->hw->pdev, re->mapaddr,
1815 length, PCI_DMA_FROMDEVICE);
1817 struct sk_buff *nskb;
1819 nskb = sky2_alloc_skb(sky2->rx_bufsize, GFP_ATOMIC);
1825 pci_unmap_single(sky2->hw->pdev, re->mapaddr,
1826 sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
1827 prefetch(skb->data);
1829 re->mapaddr = pci_map_single(sky2->hw->pdev, nskb->data,
1830 sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
1833 skb_put(skb, length);
1835 re->skb->ip_summed = CHECKSUM_NONE;
1836 sky2_rx_add(sky2, re->mapaddr);
1838 /* Tell receiver about new buffers. */
1839 sky2_put_idx(sky2->hw, rxqaddr[sky2->port], sky2->rx_put,
1840 &sky2->rx_last_put, RX_LE_SIZE);
1845 ++sky2->net_stats.rx_over_errors;
1849 ++sky2->net_stats.rx_errors;
1851 if (netif_msg_rx_err(sky2) && net_ratelimit())
1852 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
1853 sky2->netdev->name, status, length);
1855 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
1856 sky2->net_stats.rx_length_errors++;
1857 if (status & GMR_FS_FRAGMENT)
1858 sky2->net_stats.rx_frame_errors++;
1859 if (status & GMR_FS_CRC_ERR)
1860 sky2->net_stats.rx_crc_errors++;
1861 if (status & GMR_FS_RX_FF_OV)
1862 sky2->net_stats.rx_fifo_errors++;
1868 * Check for transmit complete
1870 #define TX_NO_STATUS 0xffff
1872 static void sky2_tx_check(struct sky2_hw *hw, int port, u16 last)
1874 if (last != TX_NO_STATUS) {
1875 struct net_device *dev = hw->dev[port];
1876 if (dev && netif_running(dev)) {
1877 struct sky2_port *sky2 = netdev_priv(dev);
1879 spin_lock(&sky2->tx_lock);
1880 sky2_tx_complete(sky2, last);
1881 spin_unlock(&sky2->tx_lock);
1887 * Both ports share the same status interrupt, therefore there is only
1890 static int sky2_poll(struct net_device *dev0, int *budget)
1892 struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw;
1893 unsigned int to_do = min(dev0->quota, *budget);
1894 unsigned int work_done = 0;
1896 u16 tx_done[2] = { TX_NO_STATUS, TX_NO_STATUS };
1898 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
1901 * Kick the STAT_LEV_TIMER_CTRL timer.
1902 * This fixes my hangs on Yukon-EC (0xb6) rev 1.
1903 * The if clause is there to start the timer only if it has been
1904 * configured correctly and not been disabled via ethtool.
1906 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_START) {
1907 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
1908 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
1911 hwidx = sky2_read16(hw, STAT_PUT_IDX);
1912 BUG_ON(hwidx >= STATUS_RING_SIZE);
1915 while (hwidx != hw->st_idx) {
1916 struct sky2_status_le *le = hw->st_le + hw->st_idx;
1917 struct net_device *dev;
1918 struct sky2_port *sky2;
1919 struct sk_buff *skb;
1923 le = hw->st_le + hw->st_idx;
1924 hw->st_idx = (hw->st_idx + 1) % STATUS_RING_SIZE;
1925 prefetch(hw->st_le + hw->st_idx);
1927 BUG_ON(le->link >= 2);
1928 dev = hw->dev[le->link];
1929 if (dev == NULL || !netif_running(dev))
1932 sky2 = netdev_priv(dev);
1933 status = le32_to_cpu(le->status);
1934 length = le16_to_cpu(le->length);
1936 switch (le->opcode & ~HW_OWNER) {
1938 skb = sky2_receive(sky2, length, status);
1943 skb->protocol = eth_type_trans(skb, dev);
1944 dev->last_rx = jiffies;
1946 #ifdef SKY2_VLAN_TAG_USED
1947 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
1948 vlan_hwaccel_receive_skb(skb,
1950 be16_to_cpu(sky2->rx_tag));
1953 netif_receive_skb(skb);
1955 if (++work_done >= to_do)
1959 #ifdef SKY2_VLAN_TAG_USED
1961 sky2->rx_tag = length;
1965 sky2->rx_tag = length;
1969 skb = sky2->rx_ring[sky2->rx_next].skb;
1970 skb->ip_summed = CHECKSUM_HW;
1971 skb->csum = le16_to_cpu(status);
1975 /* TX index reports status for both ports */
1976 tx_done[0] = status & 0xffff;
1977 tx_done[1] = ((status >> 24) & 0xff)
1978 | (u16)(length & 0xf) << 8;
1982 if (net_ratelimit())
1983 printk(KERN_WARNING PFX
1984 "unknown status opcode 0x%x\n", le->opcode);
1990 sky2_tx_check(hw, 0, tx_done[0]);
1991 sky2_tx_check(hw, 1, tx_done[1]);
1993 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_START) {
1994 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
1995 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
1998 if (likely(work_done < to_do)) {
1999 spin_lock_irq(&hw->hw_lock);
2000 __netif_rx_complete(dev0);
2002 hw->intr_mask |= Y2_IS_STAT_BMU;
2003 sky2_write32(hw, B0_IMSK, hw->intr_mask);
2004 spin_unlock_irq(&hw->hw_lock);
2008 *budget -= work_done;
2009 dev0->quota -= work_done;
2014 static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2016 struct net_device *dev = hw->dev[port];
2018 if (net_ratelimit())
2019 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2022 if (status & Y2_IS_PAR_RD1) {
2023 if (net_ratelimit())
2024 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2027 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2030 if (status & Y2_IS_PAR_WR1) {
2031 if (net_ratelimit())
2032 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2035 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2038 if (status & Y2_IS_PAR_MAC1) {
2039 if (net_ratelimit())
2040 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
2041 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2044 if (status & Y2_IS_PAR_RX1) {
2045 if (net_ratelimit())
2046 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
2047 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2050 if (status & Y2_IS_TCP_TXA1) {
2051 if (net_ratelimit())
2052 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2054 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2058 static void sky2_hw_intr(struct sky2_hw *hw)
2060 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2062 if (status & Y2_IS_TIST_OV)
2063 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2065 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
2068 pci_err = sky2_pci_read16(hw, PCI_STATUS);
2069 if (net_ratelimit())
2070 printk(KERN_ERR PFX "%s: pci hw error (0x%x)\n",
2071 pci_name(hw->pdev), pci_err);
2073 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2074 sky2_pci_write16(hw, PCI_STATUS,
2075 pci_err | PCI_STATUS_ERROR_BITS);
2076 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2079 if (status & Y2_IS_PCI_EXP) {
2080 /* PCI-Express uncorrectable Error occurred */
2083 pex_err = sky2_pci_read32(hw, PEX_UNC_ERR_STAT);
2085 if (net_ratelimit())
2086 printk(KERN_ERR PFX "%s: pci express error (0x%x)\n",
2087 pci_name(hw->pdev), pex_err);
2089 /* clear the interrupt */
2090 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2091 sky2_pci_write32(hw, PEX_UNC_ERR_STAT,
2093 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2095 if (pex_err & PEX_FATAL_ERRORS) {
2096 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2097 hwmsk &= ~Y2_IS_PCI_EXP;
2098 sky2_write32(hw, B0_HWE_IMSK, hwmsk);
2102 if (status & Y2_HWE_L1_MASK)
2103 sky2_hw_error(hw, 0, status);
2105 if (status & Y2_HWE_L1_MASK)
2106 sky2_hw_error(hw, 1, status);
2109 static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2111 struct net_device *dev = hw->dev[port];
2112 struct sky2_port *sky2 = netdev_priv(dev);
2113 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2115 if (netif_msg_intr(sky2))
2116 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2119 if (status & GM_IS_RX_FF_OR) {
2120 ++sky2->net_stats.rx_fifo_errors;
2121 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2124 if (status & GM_IS_TX_FF_UR) {
2125 ++sky2->net_stats.tx_fifo_errors;
2126 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2130 static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
2132 struct net_device *dev = hw->dev[port];
2133 struct sky2_port *sky2 = netdev_priv(dev);
2135 hw->intr_mask &= ~(port == 0 ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2);
2136 sky2_write32(hw, B0_IMSK, hw->intr_mask);
2138 schedule_work(&sky2->phy_task);
2141 static irqreturn_t sky2_intr(int irq, void *dev_id, struct pt_regs *regs)
2143 struct sky2_hw *hw = dev_id;
2144 struct net_device *dev0 = hw->dev[0];
2147 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2148 if (status == 0 || status == ~0)
2151 spin_lock(&hw->hw_lock);
2152 if (status & Y2_IS_HW_ERR)
2155 /* Do NAPI for Rx and Tx status */
2156 if (status & Y2_IS_STAT_BMU) {
2157 hw->intr_mask &= ~Y2_IS_STAT_BMU;
2158 sky2_write32(hw, B0_IMSK, hw->intr_mask);
2160 if (likely(__netif_rx_schedule_prep(dev0))) {
2161 prefetch(&hw->st_le[hw->st_idx]);
2162 __netif_rx_schedule(dev0);
2166 if (status & Y2_IS_IRQ_PHY1)
2167 sky2_phy_intr(hw, 0);
2169 if (status & Y2_IS_IRQ_PHY2)
2170 sky2_phy_intr(hw, 1);
2172 if (status & Y2_IS_IRQ_MAC1)
2173 sky2_mac_intr(hw, 0);
2175 if (status & Y2_IS_IRQ_MAC2)
2176 sky2_mac_intr(hw, 1);
2178 sky2_write32(hw, B0_Y2_SP_ICR, 2);
2180 spin_unlock(&hw->hw_lock);
2185 #ifdef CONFIG_NET_POLL_CONTROLLER
2186 static void sky2_netpoll(struct net_device *dev)
2188 struct sky2_port *sky2 = netdev_priv(dev);
2190 sky2_intr(sky2->hw->pdev->irq, sky2->hw, NULL);
2194 /* Chip internal frequency for clock calculations */
2195 static inline u32 sky2_mhz(const struct sky2_hw *hw)
2197 switch (hw->chip_id) {
2198 case CHIP_ID_YUKON_EC:
2199 case CHIP_ID_YUKON_EC_U:
2200 return 125; /* 125 Mhz */
2201 case CHIP_ID_YUKON_FE:
2202 return 100; /* 100 Mhz */
2203 default: /* YUKON_XL */
2204 return 156; /* 156 Mhz */
2208 static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
2210 return sky2_mhz(hw) * us;
2213 static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
2215 return clk / sky2_mhz(hw);
2219 static int sky2_reset(struct sky2_hw *hw)
2225 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2227 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2228 if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) {
2229 printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",
2230 pci_name(hw->pdev), hw->chip_id);
2235 if (hw->chip_id <= CHIP_ID_YUKON_EC) {
2236 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2237 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
2241 sky2_write8(hw, B0_CTST, CS_RST_SET);
2242 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2244 /* clear PCI errors, if any */
2245 status = sky2_pci_read16(hw, PCI_STATUS);
2247 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2248 sky2_pci_write16(hw, PCI_STATUS, status | PCI_STATUS_ERROR_BITS);
2251 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2253 /* clear any PEX errors */
2254 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
2255 sky2_pci_write32(hw, PEX_UNC_ERR_STAT, 0xffffffffUL);
2258 pmd_type = sky2_read8(hw, B2_PMD_TYP);
2259 hw->copper = !(pmd_type == 'L' || pmd_type == 'S');
2262 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2263 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2264 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2267 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2269 sky2_set_power_state(hw, PCI_D0);
2271 for (i = 0; i < hw->ports; i++) {
2272 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2273 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2276 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2278 /* Clear I2C IRQ noise */
2279 sky2_write32(hw, B2_I2C_IRQ, 1);
2281 /* turn off hardware timer (unused) */
2282 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2283 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
2285 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2287 /* Turn off descriptor polling */
2288 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
2290 /* Turn off receive timestamp */
2291 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
2292 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2294 /* enable the Tx Arbiters */
2295 for (i = 0; i < hw->ports; i++)
2296 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2298 /* Initialize ram interface */
2299 for (i = 0; i < hw->ports; i++) {
2300 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
2302 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2303 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2304 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2305 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2306 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2307 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2308 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2309 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2310 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2311 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2312 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2313 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2316 sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);
2318 for (i = 0; i < hw->ports; i++)
2319 sky2_phy_reset(hw, i);
2321 memset(hw->st_le, 0, STATUS_LE_BYTES);
2324 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2325 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2327 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
2328 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
2330 /* Set the list last index */
2331 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
2333 /* These status setup values are copied from SysKonnect's driver */
2335 /* WA for dev. #4.3 */
2336 sky2_write16(hw, STAT_TX_IDX_TH, 0xfff); /* Tx Threshold */
2338 /* set Status-FIFO watermark */
2339 sky2_write8(hw, STAT_FIFO_WM, 0x21); /* WA for dev. #4.18 */
2341 /* set Status-FIFO ISR watermark */
2342 sky2_write8(hw, STAT_FIFO_ISR_WM, 0x07); /* WA for dev. #4.18 */
2343 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 10000));
2345 sky2_write16(hw, STAT_TX_IDX_TH, 10);
2346 sky2_write8(hw, STAT_FIFO_WM, 16);
2348 /* set Status-FIFO ISR watermark */
2349 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2350 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
2352 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
2354 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
2355 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 7));
2358 /* enable status unit */
2359 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2361 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2362 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2363 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2368 static u32 sky2_supported_modes(const struct sky2_hw *hw)
2372 modes = SUPPORTED_10baseT_Half
2373 | SUPPORTED_10baseT_Full
2374 | SUPPORTED_100baseT_Half
2375 | SUPPORTED_100baseT_Full
2376 | SUPPORTED_Autoneg | SUPPORTED_TP;
2378 if (hw->chip_id != CHIP_ID_YUKON_FE)
2379 modes |= SUPPORTED_1000baseT_Half
2380 | SUPPORTED_1000baseT_Full;
2382 modes = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE
2383 | SUPPORTED_Autoneg;
2387 static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2389 struct sky2_port *sky2 = netdev_priv(dev);
2390 struct sky2_hw *hw = sky2->hw;
2392 ecmd->transceiver = XCVR_INTERNAL;
2393 ecmd->supported = sky2_supported_modes(hw);
2394 ecmd->phy_address = PHY_ADDR_MARV;
2396 ecmd->supported = SUPPORTED_10baseT_Half
2397 | SUPPORTED_10baseT_Full
2398 | SUPPORTED_100baseT_Half
2399 | SUPPORTED_100baseT_Full
2400 | SUPPORTED_1000baseT_Half
2401 | SUPPORTED_1000baseT_Full
2402 | SUPPORTED_Autoneg | SUPPORTED_TP;
2403 ecmd->port = PORT_TP;
2405 ecmd->port = PORT_FIBRE;
2407 ecmd->advertising = sky2->advertising;
2408 ecmd->autoneg = sky2->autoneg;
2409 ecmd->speed = sky2->speed;
2410 ecmd->duplex = sky2->duplex;
2414 static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2416 struct sky2_port *sky2 = netdev_priv(dev);
2417 const struct sky2_hw *hw = sky2->hw;
2418 u32 supported = sky2_supported_modes(hw);
2420 if (ecmd->autoneg == AUTONEG_ENABLE) {
2421 ecmd->advertising = supported;
2427 switch (ecmd->speed) {
2429 if (ecmd->duplex == DUPLEX_FULL)
2430 setting = SUPPORTED_1000baseT_Full;
2431 else if (ecmd->duplex == DUPLEX_HALF)
2432 setting = SUPPORTED_1000baseT_Half;
2437 if (ecmd->duplex == DUPLEX_FULL)
2438 setting = SUPPORTED_100baseT_Full;
2439 else if (ecmd->duplex == DUPLEX_HALF)
2440 setting = SUPPORTED_100baseT_Half;
2446 if (ecmd->duplex == DUPLEX_FULL)
2447 setting = SUPPORTED_10baseT_Full;
2448 else if (ecmd->duplex == DUPLEX_HALF)
2449 setting = SUPPORTED_10baseT_Half;
2457 if ((setting & supported) == 0)
2460 sky2->speed = ecmd->speed;
2461 sky2->duplex = ecmd->duplex;
2464 sky2->autoneg = ecmd->autoneg;
2465 sky2->advertising = ecmd->advertising;
2467 if (netif_running(dev))
2468 sky2_phy_reinit(sky2);
2473 static void sky2_get_drvinfo(struct net_device *dev,
2474 struct ethtool_drvinfo *info)
2476 struct sky2_port *sky2 = netdev_priv(dev);
2478 strcpy(info->driver, DRV_NAME);
2479 strcpy(info->version, DRV_VERSION);
2480 strcpy(info->fw_version, "N/A");
2481 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
2484 static const struct sky2_stat {
2485 char name[ETH_GSTRING_LEN];
2488 { "tx_bytes", GM_TXO_OK_HI },
2489 { "rx_bytes", GM_RXO_OK_HI },
2490 { "tx_broadcast", GM_TXF_BC_OK },
2491 { "rx_broadcast", GM_RXF_BC_OK },
2492 { "tx_multicast", GM_TXF_MC_OK },
2493 { "rx_multicast", GM_RXF_MC_OK },
2494 { "tx_unicast", GM_TXF_UC_OK },
2495 { "rx_unicast", GM_RXF_UC_OK },
2496 { "tx_mac_pause", GM_TXF_MPAUSE },
2497 { "rx_mac_pause", GM_RXF_MPAUSE },
2498 { "collisions", GM_TXF_SNG_COL },
2499 { "late_collision",GM_TXF_LAT_COL },
2500 { "aborted", GM_TXF_ABO_COL },
2501 { "multi_collisions", GM_TXF_MUL_COL },
2502 { "fifo_underrun", GM_TXE_FIFO_UR },
2503 { "fifo_overflow", GM_RXE_FIFO_OV },
2504 { "rx_toolong", GM_RXF_LNG_ERR },
2505 { "rx_jabber", GM_RXF_JAB_PKT },
2506 { "rx_runt", GM_RXE_FRAG },
2507 { "rx_too_long", GM_RXF_LNG_ERR },
2508 { "rx_fcs_error", GM_RXF_FCS_ERR },
2511 static u32 sky2_get_rx_csum(struct net_device *dev)
2513 struct sky2_port *sky2 = netdev_priv(dev);
2515 return sky2->rx_csum;
2518 static int sky2_set_rx_csum(struct net_device *dev, u32 data)
2520 struct sky2_port *sky2 = netdev_priv(dev);
2522 sky2->rx_csum = data;
2524 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2525 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
2530 static u32 sky2_get_msglevel(struct net_device *netdev)
2532 struct sky2_port *sky2 = netdev_priv(netdev);
2533 return sky2->msg_enable;
2536 static int sky2_nway_reset(struct net_device *dev)
2538 struct sky2_port *sky2 = netdev_priv(dev);
2540 if (sky2->autoneg != AUTONEG_ENABLE)
2543 sky2_phy_reinit(sky2);
2548 static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
2550 struct sky2_hw *hw = sky2->hw;
2551 unsigned port = sky2->port;
2554 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
2555 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
2556 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
2557 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
2559 for (i = 2; i < count; i++)
2560 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
2563 static void sky2_set_msglevel(struct net_device *netdev, u32 value)
2565 struct sky2_port *sky2 = netdev_priv(netdev);
2566 sky2->msg_enable = value;
2569 static int sky2_get_stats_count(struct net_device *dev)
2571 return ARRAY_SIZE(sky2_stats);
2574 static void sky2_get_ethtool_stats(struct net_device *dev,
2575 struct ethtool_stats *stats, u64 * data)
2577 struct sky2_port *sky2 = netdev_priv(dev);
2579 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
2582 static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
2586 switch (stringset) {
2588 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
2589 memcpy(data + i * ETH_GSTRING_LEN,
2590 sky2_stats[i].name, ETH_GSTRING_LEN);
2595 /* Use hardware MIB variables for critical path statistics and
2596 * transmit feedback not reported at interrupt.
2597 * Other errors are accounted for in interrupt handler.
2599 static struct net_device_stats *sky2_get_stats(struct net_device *dev)
2601 struct sky2_port *sky2 = netdev_priv(dev);
2604 sky2_phy_stats(sky2, data, ARRAY_SIZE(data));
2606 sky2->net_stats.tx_bytes = data[0];
2607 sky2->net_stats.rx_bytes = data[1];
2608 sky2->net_stats.tx_packets = data[2] + data[4] + data[6];
2609 sky2->net_stats.rx_packets = data[3] + data[5] + data[7];
2610 sky2->net_stats.multicast = data[5] + data[7];
2611 sky2->net_stats.collisions = data[10];
2612 sky2->net_stats.tx_aborted_errors = data[12];
2614 return &sky2->net_stats;
2617 static int sky2_set_mac_address(struct net_device *dev, void *p)
2619 struct sky2_port *sky2 = netdev_priv(dev);
2620 struct sky2_hw *hw = sky2->hw;
2621 unsigned port = sky2->port;
2622 const struct sockaddr *addr = p;
2624 if (!is_valid_ether_addr(addr->sa_data))
2625 return -EADDRNOTAVAIL;
2627 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
2628 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
2629 dev->dev_addr, ETH_ALEN);
2630 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
2631 dev->dev_addr, ETH_ALEN);
2633 /* virtual address for data */
2634 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
2636 /* physical address: used for pause frames */
2637 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
2642 static void sky2_set_multicast(struct net_device *dev)
2644 struct sky2_port *sky2 = netdev_priv(dev);
2645 struct sky2_hw *hw = sky2->hw;
2646 unsigned port = sky2->port;
2647 struct dev_mc_list *list = dev->mc_list;
2651 memset(filter, 0, sizeof(filter));
2653 reg = gma_read16(hw, port, GM_RX_CTRL);
2654 reg |= GM_RXCR_UCF_ENA;
2656 if (dev->flags & IFF_PROMISC) /* promiscuous */
2657 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2658 else if ((dev->flags & IFF_ALLMULTI) || dev->mc_count > 16) /* all multicast */
2659 memset(filter, 0xff, sizeof(filter));
2660 else if (dev->mc_count == 0) /* no multicast */
2661 reg &= ~GM_RXCR_MCF_ENA;
2664 reg |= GM_RXCR_MCF_ENA;
2666 for (i = 0; list && i < dev->mc_count; i++, list = list->next) {
2667 u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;
2668 filter[bit / 8] |= 1 << (bit % 8);
2672 gma_write16(hw, port, GM_MC_ADDR_H1,
2673 (u16) filter[0] | ((u16) filter[1] << 8));
2674 gma_write16(hw, port, GM_MC_ADDR_H2,
2675 (u16) filter[2] | ((u16) filter[3] << 8));
2676 gma_write16(hw, port, GM_MC_ADDR_H3,
2677 (u16) filter[4] | ((u16) filter[5] << 8));
2678 gma_write16(hw, port, GM_MC_ADDR_H4,
2679 (u16) filter[6] | ((u16) filter[7] << 8));
2681 gma_write16(hw, port, GM_RX_CTRL, reg);
2684 /* Can have one global because blinking is controlled by
2685 * ethtool and that is always under RTNL mutex
2687 static void sky2_led(struct sky2_hw *hw, unsigned port, int on)
2691 switch (hw->chip_id) {
2692 case CHIP_ID_YUKON_XL:
2693 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2694 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2695 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
2696 on ? (PHY_M_LEDC_LOS_CTRL(1) |
2697 PHY_M_LEDC_INIT_CTRL(7) |
2698 PHY_M_LEDC_STA1_CTRL(7) |
2699 PHY_M_LEDC_STA0_CTRL(7))
2702 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2706 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
2707 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
2708 on ? PHY_M_LED_MO_DUP(MO_LED_ON) |
2709 PHY_M_LED_MO_10(MO_LED_ON) |
2710 PHY_M_LED_MO_100(MO_LED_ON) |
2711 PHY_M_LED_MO_1000(MO_LED_ON) |
2712 PHY_M_LED_MO_RX(MO_LED_ON)
2713 : PHY_M_LED_MO_DUP(MO_LED_OFF) |
2714 PHY_M_LED_MO_10(MO_LED_OFF) |
2715 PHY_M_LED_MO_100(MO_LED_OFF) |
2716 PHY_M_LED_MO_1000(MO_LED_OFF) |
2717 PHY_M_LED_MO_RX(MO_LED_OFF));
2722 /* blink LED's for finding board */
2723 static int sky2_phys_id(struct net_device *dev, u32 data)
2725 struct sky2_port *sky2 = netdev_priv(dev);
2726 struct sky2_hw *hw = sky2->hw;
2727 unsigned port = sky2->port;
2728 u16 ledctrl, ledover = 0;
2733 if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
2734 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
2738 /* save initial values */
2739 down(&sky2->phy_sema);
2740 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2741 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2742 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2743 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
2744 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2746 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
2747 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
2751 while (!interrupted && ms > 0) {
2752 sky2_led(hw, port, onoff);
2755 up(&sky2->phy_sema);
2756 interrupted = msleep_interruptible(250);
2757 down(&sky2->phy_sema);
2762 /* resume regularly scheduled programming */
2763 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2764 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2765 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2766 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
2767 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2769 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
2770 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
2772 up(&sky2->phy_sema);
2777 static void sky2_get_pauseparam(struct net_device *dev,
2778 struct ethtool_pauseparam *ecmd)
2780 struct sky2_port *sky2 = netdev_priv(dev);
2782 ecmd->tx_pause = sky2->tx_pause;
2783 ecmd->rx_pause = sky2->rx_pause;
2784 ecmd->autoneg = sky2->autoneg;
2787 static int sky2_set_pauseparam(struct net_device *dev,
2788 struct ethtool_pauseparam *ecmd)
2790 struct sky2_port *sky2 = netdev_priv(dev);
2793 sky2->autoneg = ecmd->autoneg;
2794 sky2->tx_pause = ecmd->tx_pause != 0;
2795 sky2->rx_pause = ecmd->rx_pause != 0;
2797 sky2_phy_reinit(sky2);
2803 static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2805 struct sky2_port *sky2 = netdev_priv(dev);
2807 wol->supported = WAKE_MAGIC;
2808 wol->wolopts = sky2->wol ? WAKE_MAGIC : 0;
2811 static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2813 struct sky2_port *sky2 = netdev_priv(dev);
2814 struct sky2_hw *hw = sky2->hw;
2816 if (wol->wolopts != WAKE_MAGIC && wol->wolopts != 0)
2819 sky2->wol = wol->wolopts == WAKE_MAGIC;
2822 memcpy_toio(hw->regs + WOL_MAC_ADDR, dev->dev_addr, ETH_ALEN);
2824 sky2_write16(hw, WOL_CTRL_STAT,
2825 WOL_CTL_ENA_PME_ON_MAGIC_PKT |
2826 WOL_CTL_ENA_MAGIC_PKT_UNIT);
2828 sky2_write16(hw, WOL_CTRL_STAT, WOL_CTL_DEFAULT);
2834 static int sky2_get_coalesce(struct net_device *dev,
2835 struct ethtool_coalesce *ecmd)
2837 struct sky2_port *sky2 = netdev_priv(dev);
2838 struct sky2_hw *hw = sky2->hw;
2840 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
2841 ecmd->tx_coalesce_usecs = 0;
2843 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
2844 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
2846 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
2848 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
2849 ecmd->rx_coalesce_usecs = 0;
2851 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
2852 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
2854 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
2856 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
2857 ecmd->rx_coalesce_usecs_irq = 0;
2859 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
2860 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
2863 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
2868 /* Note: this affect both ports */
2869 static int sky2_set_coalesce(struct net_device *dev,
2870 struct ethtool_coalesce *ecmd)
2872 struct sky2_port *sky2 = netdev_priv(dev);
2873 struct sky2_hw *hw = sky2->hw;
2874 const u32 tmin = sky2_clk2us(hw, 1);
2875 const u32 tmax = 5000;
2877 if (ecmd->tx_coalesce_usecs != 0 &&
2878 (ecmd->tx_coalesce_usecs < tmin || ecmd->tx_coalesce_usecs > tmax))
2881 if (ecmd->rx_coalesce_usecs != 0 &&
2882 (ecmd->rx_coalesce_usecs < tmin || ecmd->rx_coalesce_usecs > tmax))
2885 if (ecmd->rx_coalesce_usecs_irq != 0 &&
2886 (ecmd->rx_coalesce_usecs_irq < tmin || ecmd->rx_coalesce_usecs_irq > tmax))
2889 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
2891 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
2893 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
2896 if (ecmd->tx_coalesce_usecs == 0)
2897 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
2899 sky2_write32(hw, STAT_TX_TIMER_INI,
2900 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
2901 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2903 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
2905 if (ecmd->rx_coalesce_usecs == 0)
2906 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
2908 sky2_write32(hw, STAT_LEV_TIMER_INI,
2909 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
2910 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2912 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
2914 if (ecmd->rx_coalesce_usecs_irq == 0)
2915 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
2917 sky2_write32(hw, STAT_ISR_TIMER_INI,
2918 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
2919 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2921 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
2925 static void sky2_get_ringparam(struct net_device *dev,
2926 struct ethtool_ringparam *ering)
2928 struct sky2_port *sky2 = netdev_priv(dev);
2930 ering->rx_max_pending = RX_MAX_PENDING;
2931 ering->rx_mini_max_pending = 0;
2932 ering->rx_jumbo_max_pending = 0;
2933 ering->tx_max_pending = TX_RING_SIZE - 1;
2935 ering->rx_pending = sky2->rx_pending;
2936 ering->rx_mini_pending = 0;
2937 ering->rx_jumbo_pending = 0;
2938 ering->tx_pending = sky2->tx_pending;
2941 static int sky2_set_ringparam(struct net_device *dev,
2942 struct ethtool_ringparam *ering)
2944 struct sky2_port *sky2 = netdev_priv(dev);
2947 if (ering->rx_pending > RX_MAX_PENDING ||
2948 ering->rx_pending < 8 ||
2949 ering->tx_pending < MAX_SKB_TX_LE ||
2950 ering->tx_pending > TX_RING_SIZE - 1)
2953 if (netif_running(dev))
2956 sky2->rx_pending = ering->rx_pending;
2957 sky2->tx_pending = ering->tx_pending;
2959 if (netif_running(dev)) {
2964 sky2_set_multicast(dev);
2970 static int sky2_get_regs_len(struct net_device *dev)
2976 * Returns copy of control register region
2977 * Note: access to the RAM address register set will cause timeouts.
2979 static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
2982 const struct sky2_port *sky2 = netdev_priv(dev);
2983 const void __iomem *io = sky2->hw->regs;
2985 BUG_ON(regs->len < B3_RI_WTO_R1);
2987 memset(p, 0, regs->len);
2989 memcpy_fromio(p, io, B3_RAM_ADDR);
2991 memcpy_fromio(p + B3_RI_WTO_R1,
2993 regs->len - B3_RI_WTO_R1);
2996 static struct ethtool_ops sky2_ethtool_ops = {
2997 .get_settings = sky2_get_settings,
2998 .set_settings = sky2_set_settings,
2999 .get_drvinfo = sky2_get_drvinfo,
3000 .get_msglevel = sky2_get_msglevel,
3001 .set_msglevel = sky2_set_msglevel,
3002 .nway_reset = sky2_nway_reset,
3003 .get_regs_len = sky2_get_regs_len,
3004 .get_regs = sky2_get_regs,
3005 .get_link = ethtool_op_get_link,
3006 .get_sg = ethtool_op_get_sg,
3007 .set_sg = ethtool_op_set_sg,
3008 .get_tx_csum = ethtool_op_get_tx_csum,
3009 .set_tx_csum = ethtool_op_set_tx_csum,
3010 .get_tso = ethtool_op_get_tso,
3011 .set_tso = ethtool_op_set_tso,
3012 .get_rx_csum = sky2_get_rx_csum,
3013 .set_rx_csum = sky2_set_rx_csum,
3014 .get_strings = sky2_get_strings,
3015 .get_coalesce = sky2_get_coalesce,
3016 .set_coalesce = sky2_set_coalesce,
3017 .get_ringparam = sky2_get_ringparam,
3018 .set_ringparam = sky2_set_ringparam,
3019 .get_pauseparam = sky2_get_pauseparam,
3020 .set_pauseparam = sky2_set_pauseparam,
3022 .get_wol = sky2_get_wol,
3023 .set_wol = sky2_set_wol,
3025 .phys_id = sky2_phys_id,
3026 .get_stats_count = sky2_get_stats_count,
3027 .get_ethtool_stats = sky2_get_ethtool_stats,
3028 .get_perm_addr = ethtool_op_get_perm_addr,
3031 /* Initialize network device */
3032 static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
3033 unsigned port, int highmem)
3035 struct sky2_port *sky2;
3036 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
3039 printk(KERN_ERR "sky2 etherdev alloc failed");
3043 SET_MODULE_OWNER(dev);
3044 SET_NETDEV_DEV(dev, &hw->pdev->dev);
3045 dev->irq = hw->pdev->irq;
3046 dev->open = sky2_up;
3047 dev->stop = sky2_down;
3048 dev->do_ioctl = sky2_ioctl;
3049 dev->hard_start_xmit = sky2_xmit_frame;
3050 dev->get_stats = sky2_get_stats;
3051 dev->set_multicast_list = sky2_set_multicast;
3052 dev->set_mac_address = sky2_set_mac_address;
3053 dev->change_mtu = sky2_change_mtu;
3054 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
3055 dev->tx_timeout = sky2_tx_timeout;
3056 dev->watchdog_timeo = TX_WATCHDOG;
3058 dev->poll = sky2_poll;
3059 dev->weight = NAPI_WEIGHT;
3060 #ifdef CONFIG_NET_POLL_CONTROLLER
3061 dev->poll_controller = sky2_netpoll;
3064 sky2 = netdev_priv(dev);
3067 sky2->msg_enable = netif_msg_init(debug, default_msg);
3069 spin_lock_init(&sky2->tx_lock);
3070 /* Auto speed and flow control */
3071 sky2->autoneg = AUTONEG_ENABLE;
3076 sky2->advertising = sky2_supported_modes(hw);
3078 /* Receive checksum disabled for Yukon XL
3079 * because of observed problems with incorrect
3080 * values when multiple packets are received in one interrupt
3082 sky2->rx_csum = (hw->chip_id != CHIP_ID_YUKON_XL);
3084 INIT_WORK(&sky2->phy_task, sky2_phy_task, sky2);
3085 init_MUTEX(&sky2->phy_sema);
3086 sky2->tx_pending = TX_DEF_PENDING;
3087 sky2->rx_pending = is_ec_a1(hw) ? 8 : RX_DEF_PENDING;
3088 sky2->rx_bufsize = sky2_buf_size(ETH_DATA_LEN);
3090 hw->dev[port] = dev;
3094 dev->features |= NETIF_F_LLTX;
3095 if (hw->chip_id != CHIP_ID_YUKON_EC_U)
3096 dev->features |= NETIF_F_TSO;
3098 dev->features |= NETIF_F_HIGHDMA;
3099 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
3101 #ifdef SKY2_VLAN_TAG_USED
3102 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3103 dev->vlan_rx_register = sky2_vlan_rx_register;
3104 dev->vlan_rx_kill_vid = sky2_vlan_rx_kill_vid;
3107 /* read the mac address */
3108 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
3109 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
3111 /* device is off until link detection */
3112 netif_carrier_off(dev);
3113 netif_stop_queue(dev);
3118 static void __devinit sky2_show_addr(struct net_device *dev)
3120 const struct sky2_port *sky2 = netdev_priv(dev);
3122 if (netif_msg_probe(sky2))
3123 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3125 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3126 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3129 /* Handle software interrupt used during MSI test */
3130 static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id,
3131 struct pt_regs *regs)
3133 struct sky2_hw *hw = dev_id;
3134 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
3139 if (status & Y2_IS_IRQ_SW) {
3140 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3143 sky2_write32(hw, B0_Y2_SP_ICR, 2);
3145 sky2_read32(hw, B0_IMSK);
3149 /* Test interrupt path by forcing a a software IRQ */
3150 static int __devinit sky2_test_msi(struct sky2_hw *hw)
3152 struct pci_dev *pdev = hw->pdev;
3155 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
3157 err = request_irq(pdev->irq, sky2_test_intr, SA_SHIRQ, DRV_NAME, hw);
3159 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3160 pci_name(pdev), pdev->irq);
3164 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
3167 for (i = 0; i < 10; i++) {
3175 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3177 sky2_write32(hw, B0_IMSK, 0);
3179 free_irq(pdev->irq, hw);
3184 static int __devinit sky2_probe(struct pci_dev *pdev,
3185 const struct pci_device_id *ent)
3187 struct net_device *dev, *dev1 = NULL;
3189 int err, pm_cap, using_dac = 0;
3191 err = pci_enable_device(pdev);
3193 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
3198 err = pci_request_regions(pdev, DRV_NAME);
3200 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
3205 pci_set_master(pdev);
3207 /* Find power-management capability. */
3208 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
3210 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
3213 goto err_out_free_regions;
3216 if (sizeof(dma_addr_t) > sizeof(u32) &&
3217 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
3219 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3221 printk(KERN_ERR PFX "%s unable to obtain 64 bit DMA "
3222 "for consistent allocations\n", pci_name(pdev));
3223 goto err_out_free_regions;
3227 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3229 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
3231 goto err_out_free_regions;
3236 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
3238 printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",
3240 goto err_out_free_regions;
3245 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3247 printk(KERN_ERR PFX "%s: cannot map device registers\n",
3249 goto err_out_free_hw;
3251 hw->pm_cap = pm_cap;
3252 spin_lock_init(&hw->hw_lock);
3255 /* byte swap descriptors in hardware */
3259 reg = sky2_pci_read32(hw, PCI_DEV_REG2);
3260 reg |= PCI_REV_DESC;
3261 sky2_pci_write32(hw, PCI_DEV_REG2, reg);
3265 /* ring for status responses */
3266 hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,
3269 goto err_out_iounmap;
3271 err = sky2_reset(hw);
3273 goto err_out_iounmap;
3275 printk(KERN_INFO PFX "v%s addr 0x%lx irq %d Yukon-%s (0x%x) rev %d\n",
3276 DRV_VERSION, pci_resource_start(pdev, 0), pdev->irq,
3277 yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
3278 hw->chip_id, hw->chip_rev);
3280 dev = sky2_init_netdev(hw, 0, using_dac);
3282 goto err_out_free_pci;
3284 err = register_netdev(dev);
3286 printk(KERN_ERR PFX "%s: cannot register net device\n",
3288 goto err_out_free_netdev;
3291 sky2_show_addr(dev);
3293 if (hw->ports > 1 && (dev1 = sky2_init_netdev(hw, 1, using_dac))) {
3294 if (register_netdev(dev1) == 0)
3295 sky2_show_addr(dev1);
3297 /* Failure to register second port need not be fatal */
3298 printk(KERN_WARNING PFX
3299 "register of second port failed\n");
3305 if (!disable_msi && pci_enable_msi(pdev) == 0) {
3306 err = sky2_test_msi(hw);
3307 if (err == -EOPNOTSUPP) {
3308 /* MSI test failed, go back to INTx mode */
3309 printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
3310 "switching to INTx mode. Please report this failure to "
3311 "the PCI maintainer and include system chipset information.\n",
3313 pci_disable_msi(pdev);
3316 goto err_out_unregister;
3319 err = request_irq(pdev->irq, sky2_intr, SA_SHIRQ | SA_SAMPLE_RANDOM,
3322 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3323 pci_name(pdev), pdev->irq);
3324 goto err_out_unregister;
3327 hw->intr_mask = Y2_IS_BASE;
3328 sky2_write32(hw, B0_IMSK, hw->intr_mask);
3330 pci_set_drvdata(pdev, hw);
3336 pci_disable_msi(pdev);
3338 unregister_netdev(dev1);
3341 unregister_netdev(dev);
3342 err_out_free_netdev:
3345 sky2_write8(hw, B0_CTST, CS_RST_SET);
3346 pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3351 err_out_free_regions:
3352 pci_release_regions(pdev);
3353 pci_disable_device(pdev);
3358 static void __devexit sky2_remove(struct pci_dev *pdev)
3360 struct sky2_hw *hw = pci_get_drvdata(pdev);
3361 struct net_device *dev0, *dev1;
3369 unregister_netdev(dev1);
3370 unregister_netdev(dev0);
3372 sky2_write32(hw, B0_IMSK, 0);
3373 sky2_set_power_state(hw, PCI_D3hot);
3374 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
3375 sky2_write8(hw, B0_CTST, CS_RST_SET);
3376 sky2_read8(hw, B0_CTST);
3378 free_irq(pdev->irq, hw);
3380 pci_disable_msi(pdev);
3381 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3382 pci_release_regions(pdev);
3383 pci_disable_device(pdev);
3391 pci_set_drvdata(pdev, NULL);
3395 static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
3397 struct sky2_hw *hw = pci_get_drvdata(pdev);
3400 for (i = 0; i < 2; i++) {
3401 struct net_device *dev = hw->dev[i];
3404 if (!netif_running(dev))
3408 netif_device_detach(dev);
3412 return sky2_set_power_state(hw, pci_choose_state(pdev, state));
3415 static int sky2_resume(struct pci_dev *pdev)
3417 struct sky2_hw *hw = pci_get_drvdata(pdev);
3420 pci_restore_state(pdev);
3421 pci_enable_wake(pdev, PCI_D0, 0);
3422 err = sky2_set_power_state(hw, PCI_D0);
3426 err = sky2_reset(hw);
3430 for (i = 0; i < 2; i++) {
3431 struct net_device *dev = hw->dev[i];
3432 if (dev && netif_running(dev)) {
3433 netif_device_attach(dev);
3436 printk(KERN_ERR PFX "%s: could not up: %d\n",
3448 static struct pci_driver sky2_driver = {
3450 .id_table = sky2_id_table,
3451 .probe = sky2_probe,
3452 .remove = __devexit_p(sky2_remove),
3454 .suspend = sky2_suspend,
3455 .resume = sky2_resume,
3459 static int __init sky2_init_module(void)
3461 return pci_register_driver(&sky2_driver);
3464 static void __exit sky2_cleanup_module(void)
3466 pci_unregister_driver(&sky2_driver);
3469 module_init(sky2_init_module);
3470 module_exit(sky2_cleanup_module);
3472 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
3473 MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
3474 MODULE_LICENSE("GPL");
3475 MODULE_VERSION(DRV_VERSION);