1 /*------------------------------------------------------------------------
2 . smc91x.h - macros for SMSC's 91C9x/91C1xx single-chip Ethernet device.
4 . Copyright (C) 1996 by Erik Stahlman
5 . Copyright (C) 2001 Standard Microsystems Corporation
6 . Developed by Simple Network Magic Corporation
7 . Copyright (C) 2003 Monta Vista Software, Inc.
8 . Unified SMC91x driver by Nicolas Pitre
10 . This program is free software; you can redistribute it and/or modify
11 . it under the terms of the GNU General Public License as published by
12 . the Free Software Foundation; either version 2 of the License, or
13 . (at your option) any later version.
15 . This program is distributed in the hope that it will be useful,
16 . but WITHOUT ANY WARRANTY; without even the implied warranty of
17 . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 . GNU General Public License for more details.
20 . You should have received a copy of the GNU General Public License
21 . along with this program; if not, write to the Free Software
22 . Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 . Information contained in this file was obtained from the LAN91C111
25 . manual from SMC. To get a copy, if you really want one, you can find
26 . information under www.smsc.com.
29 . Erik Stahlman <erik@vt.edu>
30 . Daris A Nevil <dnevil@snmc.com>
31 . Nicolas Pitre <nico@cam.org>
33 ---------------------------------------------------------------------------*/
37 #include <linux/smc91x.h>
40 * Define your architecture specific bus configuration parameters here.
43 #if defined(CONFIG_ARCH_LUBBOCK) ||\
44 defined(CONFIG_MACH_MAINSTONE) ||\
45 defined(CONFIG_MACH_ZYLONITE) ||\
46 defined(CONFIG_MACH_LITTLETON) ||\
47 defined(CONFIG_ARCH_VIPER)
49 #include <asm/mach-types.h>
51 /* Now the bus width is specified in the platform data
52 * pretend here to support all I/O access types
54 #define SMC_CAN_USE_8BIT 1
55 #define SMC_CAN_USE_16BIT 1
56 #define SMC_CAN_USE_32BIT 1
59 #define SMC_IO_SHIFT (lp->io_shift)
61 #define SMC_inb(a, r) readb((a) + (r))
62 #define SMC_inw(a, r) readw((a) + (r))
63 #define SMC_inl(a, r) readl((a) + (r))
64 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
65 #define SMC_outl(v, a, r) writel(v, (a) + (r))
66 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
67 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
68 #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
69 #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
70 #define SMC_IRQ_FLAGS (-1) /* from resource */
72 /* We actually can't write halfwords properly if not word aligned */
73 static inline void SMC_outw(u16 val, void __iomem *ioaddr, int reg)
75 if (machine_is_mainstone() && reg & 2) {
76 unsigned int v = val << 16;
77 v |= readl(ioaddr + (reg & ~2)) & 0xffff;
78 writel(v, ioaddr + (reg & ~2));
80 writew(val, ioaddr + reg);
84 #elif defined(CONFIG_BLACKFIN)
86 #define SMC_IRQ_FLAGS IRQF_TRIGGER_HIGH
87 #define RPC_LSA_DEFAULT RPC_LED_100_10
88 #define RPC_LSB_DEFAULT RPC_LED_TX_RX
90 #define SMC_CAN_USE_8BIT 0
91 #define SMC_CAN_USE_16BIT 1
92 # if defined(CONFIG_BF561)
93 #define SMC_CAN_USE_32BIT 1
95 #define SMC_CAN_USE_32BIT 0
97 #define SMC_IO_SHIFT 0
99 #define SMC_USE_BFIN_DMA 0
101 #define SMC_inw(a, r) readw((a) + (r))
102 #define SMC_outw(v, a, r) writew(v, (a) + (r))
103 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
104 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
105 # if SMC_CAN_USE_32BIT
106 #define SMC_inl(a, r) readl((a) + (r))
107 #define SMC_outl(v, a, r) writel(v, (a) + (r))
108 #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
109 #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
112 #elif defined(CONFIG_REDWOOD_5) || defined(CONFIG_REDWOOD_6)
114 /* We can only do 16-bit reads and writes in the static memory space. */
115 #define SMC_CAN_USE_8BIT 0
116 #define SMC_CAN_USE_16BIT 1
117 #define SMC_CAN_USE_32BIT 0
120 #define SMC_IO_SHIFT 0
122 #define SMC_inw(a, r) in_be16((volatile u16 *)((a) + (r)))
123 #define SMC_outw(v, a, r) out_be16((volatile u16 *)((a) + (r)), v)
124 #define SMC_insw(a, r, p, l) \
126 unsigned long __port = (a) + (r); \
127 u16 *__p = (u16 *)(p); \
129 insw(__port, __p, __l); \
131 *__p = swab16(*__p); \
136 #define SMC_outsw(a, r, p, l) \
138 unsigned long __port = (a) + (r); \
139 u16 *__p = (u16 *)(p); \
142 /* Believe it or not, the swab isn't needed. */ \
143 outw( /* swab16 */ (*__p++), __port); \
147 #define SMC_IRQ_FLAGS (0)
149 #elif defined(CONFIG_SA1100_PLEB)
150 /* We can only do 16-bit reads and writes in the static memory space. */
151 #define SMC_CAN_USE_8BIT 1
152 #define SMC_CAN_USE_16BIT 1
153 #define SMC_CAN_USE_32BIT 0
154 #define SMC_IO_SHIFT 0
157 #define SMC_inb(a, r) readb((a) + (r))
158 #define SMC_insb(a, r, p, l) readsb((a) + (r), p, (l))
159 #define SMC_inw(a, r) readw((a) + (r))
160 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
161 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
162 #define SMC_outsb(a, r, p, l) writesb((a) + (r), p, (l))
163 #define SMC_outw(v, a, r) writew(v, (a) + (r))
164 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
166 #define SMC_IRQ_FLAGS (-1)
168 #elif defined(CONFIG_SA1100_ASSABET)
170 #include <mach/neponset.h>
172 /* We can only do 8-bit reads and writes in the static memory space. */
173 #define SMC_CAN_USE_8BIT 1
174 #define SMC_CAN_USE_16BIT 0
175 #define SMC_CAN_USE_32BIT 0
178 /* The first two address lines aren't connected... */
179 #define SMC_IO_SHIFT 2
181 #define SMC_inb(a, r) readb((a) + (r))
182 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
183 #define SMC_insb(a, r, p, l) readsb((a) + (r), p, (l))
184 #define SMC_outsb(a, r, p, l) writesb((a) + (r), p, (l))
185 #define SMC_IRQ_FLAGS (-1) /* from resource */
187 #elif defined(CONFIG_MACH_LOGICPD_PXA270)
189 #define SMC_CAN_USE_8BIT 0
190 #define SMC_CAN_USE_16BIT 1
191 #define SMC_CAN_USE_32BIT 0
192 #define SMC_IO_SHIFT 0
195 #define SMC_inw(a, r) readw((a) + (r))
196 #define SMC_outw(v, a, r) writew(v, (a) + (r))
197 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
198 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
200 #elif defined(CONFIG_ARCH_INNOKOM) || \
201 defined(CONFIG_ARCH_PXA_IDP) || \
202 defined(CONFIG_ARCH_RAMSES) || \
203 defined(CONFIG_ARCH_PCM027)
205 #define SMC_CAN_USE_8BIT 1
206 #define SMC_CAN_USE_16BIT 1
207 #define SMC_CAN_USE_32BIT 1
208 #define SMC_IO_SHIFT 0
210 #define SMC_USE_PXA_DMA 1
212 #define SMC_inb(a, r) readb((a) + (r))
213 #define SMC_inw(a, r) readw((a) + (r))
214 #define SMC_inl(a, r) readl((a) + (r))
215 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
216 #define SMC_outl(v, a, r) writel(v, (a) + (r))
217 #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
218 #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
219 #define SMC_IRQ_FLAGS (-1) /* from resource */
221 /* We actually can't write halfwords properly if not word aligned */
223 SMC_outw(u16 val, void __iomem *ioaddr, int reg)
226 unsigned int v = val << 16;
227 v |= readl(ioaddr + (reg & ~2)) & 0xffff;
228 writel(v, ioaddr + (reg & ~2));
230 writew(val, ioaddr + reg);
234 #elif defined(CONFIG_ARCH_OMAP)
236 /* We can only do 16-bit reads and writes in the static memory space. */
237 #define SMC_CAN_USE_8BIT 0
238 #define SMC_CAN_USE_16BIT 1
239 #define SMC_CAN_USE_32BIT 0
240 #define SMC_IO_SHIFT 0
243 #define SMC_inw(a, r) readw((a) + (r))
244 #define SMC_outw(v, a, r) writew(v, (a) + (r))
245 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
246 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
247 #define SMC_IRQ_FLAGS (-1) /* from resource */
249 #elif defined(CONFIG_SH_SH4202_MICRODEV)
251 #define SMC_CAN_USE_8BIT 0
252 #define SMC_CAN_USE_16BIT 1
253 #define SMC_CAN_USE_32BIT 0
255 #define SMC_inb(a, r) inb((a) + (r) - 0xa0000000)
256 #define SMC_inw(a, r) inw((a) + (r) - 0xa0000000)
257 #define SMC_inl(a, r) inl((a) + (r) - 0xa0000000)
258 #define SMC_outb(v, a, r) outb(v, (a) + (r) - 0xa0000000)
259 #define SMC_outw(v, a, r) outw(v, (a) + (r) - 0xa0000000)
260 #define SMC_outl(v, a, r) outl(v, (a) + (r) - 0xa0000000)
261 #define SMC_insl(a, r, p, l) insl((a) + (r) - 0xa0000000, p, l)
262 #define SMC_outsl(a, r, p, l) outsl((a) + (r) - 0xa0000000, p, l)
263 #define SMC_insw(a, r, p, l) insw((a) + (r) - 0xa0000000, p, l)
264 #define SMC_outsw(a, r, p, l) outsw((a) + (r) - 0xa0000000, p, l)
266 #define SMC_IRQ_FLAGS (0)
268 #elif defined(CONFIG_ISA)
270 #define SMC_CAN_USE_8BIT 1
271 #define SMC_CAN_USE_16BIT 1
272 #define SMC_CAN_USE_32BIT 0
274 #define SMC_inb(a, r) inb((a) + (r))
275 #define SMC_inw(a, r) inw((a) + (r))
276 #define SMC_outb(v, a, r) outb(v, (a) + (r))
277 #define SMC_outw(v, a, r) outw(v, (a) + (r))
278 #define SMC_insw(a, r, p, l) insw((a) + (r), p, l)
279 #define SMC_outsw(a, r, p, l) outsw((a) + (r), p, l)
281 #elif defined(CONFIG_M32R)
283 #define SMC_CAN_USE_8BIT 0
284 #define SMC_CAN_USE_16BIT 1
285 #define SMC_CAN_USE_32BIT 0
287 #define SMC_inb(a, r) inb(((u32)a) + (r))
288 #define SMC_inw(a, r) inw(((u32)a) + (r))
289 #define SMC_outb(v, a, r) outb(v, ((u32)a) + (r))
290 #define SMC_outw(v, a, r) outw(v, ((u32)a) + (r))
291 #define SMC_insw(a, r, p, l) insw(((u32)a) + (r), p, l)
292 #define SMC_outsw(a, r, p, l) outsw(((u32)a) + (r), p, l)
294 #define SMC_IRQ_FLAGS (0)
296 #define RPC_LSA_DEFAULT RPC_LED_TX_RX
297 #define RPC_LSB_DEFAULT RPC_LED_100_10
299 #elif defined(CONFIG_MACH_LPD79520) \
300 || defined(CONFIG_MACH_LPD7A400) \
301 || defined(CONFIG_MACH_LPD7A404)
303 /* The LPD7X_IOBARRIER is necessary to overcome a mismatch between the
304 * way that the CPU handles chip selects and the way that the SMC chip
305 * expects the chip select to operate. Refer to
306 * Documentation/arm/Sharp-LH/IOBarrier for details. The read from
307 * IOBARRIER is a byte, in order that we read the least-common
308 * denominator. It would be wasteful to read 32 bits from an 8-bit
311 * There is no explicit protection against interrupts intervening
312 * between the writew and the IOBARRIER. In SMC ISR there is a
313 * preamble that performs an IOBARRIER in the extremely unlikely event
314 * that the driver interrupts itself between a writew to the chip an
315 * the IOBARRIER that follows *and* the cache is large enough that the
316 * first off-chip access while handing the interrupt is to the SMC
317 * chip. Other devices in the same address space as the SMC chip must
318 * be aware of the potential for trouble and perform a similar
319 * IOBARRIER on entry to their ISR.
322 #include <mach/constants.h> /* IOBARRIER_VIRT */
324 #define SMC_CAN_USE_8BIT 0
325 #define SMC_CAN_USE_16BIT 1
326 #define SMC_CAN_USE_32BIT 0
328 #define LPD7X_IOBARRIER readb (IOBARRIER_VIRT)
330 #define SMC_inw(a,r)\
331 ({ unsigned short v = readw ((void*) ((a) + (r))); LPD7X_IOBARRIER; v; })
332 #define SMC_outw(v,a,r) ({ writew ((v), (a) + (r)); LPD7X_IOBARRIER; })
334 #define SMC_insw LPD7_SMC_insw
335 static inline void LPD7_SMC_insw (unsigned char* a, int r,
336 unsigned char* p, int l)
338 unsigned short* ps = (unsigned short*) p;
340 *ps++ = readw (a + r);
345 #define SMC_outsw LPD7_SMC_outsw
346 static inline void LPD7_SMC_outsw (unsigned char* a, int r,
347 unsigned char* p, int l)
349 unsigned short* ps = (unsigned short*) p;
351 writew (*ps++, a + r);
356 #define SMC_INTERRUPT_PREAMBLE LPD7X_IOBARRIER
358 #define RPC_LSA_DEFAULT RPC_LED_TX_RX
359 #define RPC_LSB_DEFAULT RPC_LED_100_10
361 #elif defined(CONFIG_SOC_AU1X00)
365 /* We can only do 16-bit reads and writes in the static memory space. */
366 #define SMC_CAN_USE_8BIT 0
367 #define SMC_CAN_USE_16BIT 1
368 #define SMC_CAN_USE_32BIT 0
369 #define SMC_IO_SHIFT 0
372 #define SMC_inw(a, r) au_readw((unsigned long)((a) + (r)))
373 #define SMC_insw(a, r, p, l) \
375 unsigned long _a = (unsigned long)((a) + (r)); \
377 u16 *_p = (u16 *)(p); \
379 *_p++ = au_readw(_a); \
381 #define SMC_outw(v, a, r) au_writew(v, (unsigned long)((a) + (r)))
382 #define SMC_outsw(a, r, p, l) \
384 unsigned long _a = (unsigned long)((a) + (r)); \
386 const u16 *_p = (const u16 *)(p); \
388 au_writew(*_p++ , _a); \
391 #define SMC_IRQ_FLAGS (0)
393 #elif defined(CONFIG_ARCH_VERSATILE)
395 #define SMC_CAN_USE_8BIT 1
396 #define SMC_CAN_USE_16BIT 1
397 #define SMC_CAN_USE_32BIT 1
400 #define SMC_inb(a, r) readb((a) + (r))
401 #define SMC_inw(a, r) readw((a) + (r))
402 #define SMC_inl(a, r) readl((a) + (r))
403 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
404 #define SMC_outw(v, a, r) writew(v, (a) + (r))
405 #define SMC_outl(v, a, r) writel(v, (a) + (r))
406 #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
407 #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
408 #define SMC_IRQ_FLAGS (-1) /* from resource */
410 #elif defined(CONFIG_MN10300)
413 * MN10300/AM33 configuration
416 #include <asm/unit/smc91111.h>
421 * Default configuration
424 #define SMC_CAN_USE_8BIT 1
425 #define SMC_CAN_USE_16BIT 1
426 #define SMC_CAN_USE_32BIT 1
429 #define SMC_IO_SHIFT (lp->io_shift)
431 #define SMC_inb(a, r) readb((a) + (r))
432 #define SMC_inw(a, r) readw((a) + (r))
433 #define SMC_inl(a, r) readl((a) + (r))
434 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
435 #define SMC_outw(v, a, r) writew(v, (a) + (r))
436 #define SMC_outl(v, a, r) writel(v, (a) + (r))
437 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
438 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
439 #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
440 #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
442 #define RPC_LSA_DEFAULT RPC_LED_100_10
443 #define RPC_LSB_DEFAULT RPC_LED_TX_RX
448 /* store this information for the driver.. */
451 * If I have to wait until memory is available to send a
452 * packet, I will store the skbuff here, until I get the
453 * desired memory. Then, I'll send it out and free it.
455 struct sk_buff *pending_tx_skb;
456 struct tasklet_struct tx_task;
458 /* version/revision of the SMC91x chip */
461 /* Contains the current active transmission mode */
464 /* Contains the current active receive mode */
467 /* Contains the current active receive/phy mode */
474 struct mii_if_info mii;
477 struct work_struct phy_configure;
478 struct net_device *dev;
483 #ifdef CONFIG_ARCH_PXA
484 /* DMA needs the physical address of the chip */
486 struct device *device;
489 void __iomem *datacs;
491 /* the low address lines on some platforms aren't connected... */
494 struct smc91x_platdata cfg;
497 #define SMC_8BIT(p) ((p)->cfg.flags & SMC91X_USE_8BIT)
498 #define SMC_16BIT(p) ((p)->cfg.flags & SMC91X_USE_16BIT)
499 #define SMC_32BIT(p) ((p)->cfg.flags & SMC91X_USE_32BIT)
501 #ifdef CONFIG_ARCH_PXA
503 * Let's use the DMA engine on the XScale PXA2xx for RX packets. This is
504 * always happening in irq context so no need to worry about races. TX is
505 * different and probably not worth it for that reason, and not as critical
506 * as RX which can overrun memory and lose packets.
508 #include <linux/dma-mapping.h>
510 #include <mach/pxa-regs.h>
514 #define SMC_insl(a, r, p, l) \
515 smc_pxa_dma_insl(a, lp, r, dev->dma, p, l)
517 smc_pxa_dma_insl(void __iomem *ioaddr, struct smc_local *lp, int reg, int dma,
518 u_char *buf, int len)
520 u_long physaddr = lp->physaddr;
523 /* fallback if no DMA available */
524 if (dma == (unsigned char)-1) {
525 readsl(ioaddr + reg, buf, len);
529 /* 64 bit alignment is required for memory to memory DMA */
531 *((u32 *)buf) = SMC_inl(ioaddr, reg);
537 dmabuf = dma_map_single(lp->device, buf, len, DMA_FROM_DEVICE);
538 DCSR(dma) = DCSR_NODESC;
540 DSADR(dma) = physaddr + reg;
541 DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 |
542 DCMD_WIDTH4 | (DCMD_LENGTH & len));
543 DCSR(dma) = DCSR_NODESC | DCSR_RUN;
544 while (!(DCSR(dma) & DCSR_STOPSTATE))
547 dma_unmap_single(lp->device, dmabuf, len, DMA_FROM_DEVICE);
553 #define SMC_insw(a, r, p, l) \
554 smc_pxa_dma_insw(a, lp, r, dev->dma, p, l)
556 smc_pxa_dma_insw(void __iomem *ioaddr, struct smc_local *lp, int reg, int dma,
557 u_char *buf, int len)
559 u_long physaddr = lp->physaddr;
562 /* fallback if no DMA available */
563 if (dma == (unsigned char)-1) {
564 readsw(ioaddr + reg, buf, len);
568 /* 64 bit alignment is required for memory to memory DMA */
569 while ((long)buf & 6) {
570 *((u16 *)buf) = SMC_inw(ioaddr, reg);
576 dmabuf = dma_map_single(lp->device, buf, len, DMA_FROM_DEVICE);
577 DCSR(dma) = DCSR_NODESC;
579 DSADR(dma) = physaddr + reg;
580 DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 |
581 DCMD_WIDTH2 | (DCMD_LENGTH & len));
582 DCSR(dma) = DCSR_NODESC | DCSR_RUN;
583 while (!(DCSR(dma) & DCSR_STOPSTATE))
586 dma_unmap_single(lp->device, dmabuf, len, DMA_FROM_DEVICE);
591 smc_pxa_dma_irq(int dma, void *dummy)
595 #endif /* CONFIG_ARCH_PXA */
599 * Everything a particular hardware setup needs should have been defined
600 * at this point. Add stubs for the undefined cases, mainly to avoid
601 * compilation warnings since they'll be optimized away, or to prevent buggy
605 #if ! SMC_CAN_USE_32BIT
606 #define SMC_inl(ioaddr, reg) ({ BUG(); 0; })
607 #define SMC_outl(x, ioaddr, reg) BUG()
608 #define SMC_insl(a, r, p, l) BUG()
609 #define SMC_outsl(a, r, p, l) BUG()
612 #if !defined(SMC_insl) || !defined(SMC_outsl)
613 #define SMC_insl(a, r, p, l) BUG()
614 #define SMC_outsl(a, r, p, l) BUG()
617 #if ! SMC_CAN_USE_16BIT
620 * Any 16-bit access is performed with two 8-bit accesses if the hardware
621 * can't do it directly. Most registers are 16-bit so those are mandatory.
623 #define SMC_outw(x, ioaddr, reg) \
625 unsigned int __val16 = (x); \
626 SMC_outb( __val16, ioaddr, reg ); \
627 SMC_outb( __val16 >> 8, ioaddr, reg + (1 << SMC_IO_SHIFT));\
629 #define SMC_inw(ioaddr, reg) \
631 unsigned int __val16; \
632 __val16 = SMC_inb( ioaddr, reg ); \
633 __val16 |= SMC_inb( ioaddr, reg + (1 << SMC_IO_SHIFT)) << 8; \
637 #define SMC_insw(a, r, p, l) BUG()
638 #define SMC_outsw(a, r, p, l) BUG()
642 #if !defined(SMC_insw) || !defined(SMC_outsw)
643 #define SMC_insw(a, r, p, l) BUG()
644 #define SMC_outsw(a, r, p, l) BUG()
647 #if ! SMC_CAN_USE_8BIT
648 #define SMC_inb(ioaddr, reg) ({ BUG(); 0; })
649 #define SMC_outb(x, ioaddr, reg) BUG()
650 #define SMC_insb(a, r, p, l) BUG()
651 #define SMC_outsb(a, r, p, l) BUG()
654 #if !defined(SMC_insb) || !defined(SMC_outsb)
655 #define SMC_insb(a, r, p, l) BUG()
656 #define SMC_outsb(a, r, p, l) BUG()
659 #ifndef SMC_CAN_USE_DATACS
660 #define SMC_CAN_USE_DATACS 0
664 #define SMC_IO_SHIFT 0
667 #ifndef SMC_IRQ_FLAGS
668 #define SMC_IRQ_FLAGS IRQF_TRIGGER_RISING
671 #ifndef SMC_INTERRUPT_PREAMBLE
672 #define SMC_INTERRUPT_PREAMBLE
676 /* Because of bank switching, the LAN91x uses only 16 I/O ports */
677 #define SMC_IO_EXTENT (16 << SMC_IO_SHIFT)
678 #define SMC_DATA_EXTENT (4)
681 . Bank Select Register:
683 . yyyy yyyy 0000 00xx
685 . yyyy yyyy = 0x33, for identification purposes.
687 #define BANK_SELECT (14 << SMC_IO_SHIFT)
690 // Transmit Control Register
692 #define TCR_REG(lp) SMC_REG(lp, 0x0000, 0)
693 #define TCR_ENABLE 0x0001 // When 1 we can transmit
694 #define TCR_LOOP 0x0002 // Controls output pin LBK
695 #define TCR_FORCOL 0x0004 // When 1 will force a collision
696 #define TCR_PAD_EN 0x0080 // When 1 will pad tx frames < 64 bytes w/0
697 #define TCR_NOCRC 0x0100 // When 1 will not append CRC to tx frames
698 #define TCR_MON_CSN 0x0400 // When 1 tx monitors carrier
699 #define TCR_FDUPLX 0x0800 // When 1 enables full duplex operation
700 #define TCR_STP_SQET 0x1000 // When 1 stops tx if Signal Quality Error
701 #define TCR_EPH_LOOP 0x2000 // When 1 enables EPH block loopback
702 #define TCR_SWFDUP 0x8000 // When 1 enables Switched Full Duplex mode
704 #define TCR_CLEAR 0 /* do NOTHING */
705 /* the default settings for the TCR register : */
706 #define TCR_DEFAULT (TCR_ENABLE | TCR_PAD_EN)
709 // EPH Status Register
711 #define EPH_STATUS_REG(lp) SMC_REG(lp, 0x0002, 0)
712 #define ES_TX_SUC 0x0001 // Last TX was successful
713 #define ES_SNGL_COL 0x0002 // Single collision detected for last tx
714 #define ES_MUL_COL 0x0004 // Multiple collisions detected for last tx
715 #define ES_LTX_MULT 0x0008 // Last tx was a multicast
716 #define ES_16COL 0x0010 // 16 Collisions Reached
717 #define ES_SQET 0x0020 // Signal Quality Error Test
718 #define ES_LTXBRD 0x0040 // Last tx was a broadcast
719 #define ES_TXDEFR 0x0080 // Transmit Deferred
720 #define ES_LATCOL 0x0200 // Late collision detected on last tx
721 #define ES_LOSTCARR 0x0400 // Lost Carrier Sense
722 #define ES_EXC_DEF 0x0800 // Excessive Deferral
723 #define ES_CTR_ROL 0x1000 // Counter Roll Over indication
724 #define ES_LINK_OK 0x4000 // Driven by inverted value of nLNK pin
725 #define ES_TXUNRN 0x8000 // Tx Underrun
728 // Receive Control Register
730 #define RCR_REG(lp) SMC_REG(lp, 0x0004, 0)
731 #define RCR_RX_ABORT 0x0001 // Set if a rx frame was aborted
732 #define RCR_PRMS 0x0002 // Enable promiscuous mode
733 #define RCR_ALMUL 0x0004 // When set accepts all multicast frames
734 #define RCR_RXEN 0x0100 // IFF this is set, we can receive packets
735 #define RCR_STRIP_CRC 0x0200 // When set strips CRC from rx packets
736 #define RCR_ABORT_ENB 0x0200 // When set will abort rx on collision
737 #define RCR_FILT_CAR 0x0400 // When set filters leading 12 bit s of carrier
738 #define RCR_SOFTRST 0x8000 // resets the chip
740 /* the normal settings for the RCR register : */
741 #define RCR_DEFAULT (RCR_STRIP_CRC | RCR_RXEN)
742 #define RCR_CLEAR 0x0 // set it to a base state
747 #define COUNTER_REG(lp) SMC_REG(lp, 0x0006, 0)
750 // Memory Information Register
752 #define MIR_REG(lp) SMC_REG(lp, 0x0008, 0)
755 // Receive/Phy Control Register
757 #define RPC_REG(lp) SMC_REG(lp, 0x000A, 0)
758 #define RPC_SPEED 0x2000 // When 1 PHY is in 100Mbps mode.
759 #define RPC_DPLX 0x1000 // When 1 PHY is in Full-Duplex Mode
760 #define RPC_ANEG 0x0800 // When 1 PHY is in Auto-Negotiate Mode
761 #define RPC_LSXA_SHFT 5 // Bits to shift LS2A,LS1A,LS0A to lsb
762 #define RPC_LSXB_SHFT 2 // Bits to get LS2B,LS1B,LS0B to lsb
764 #ifndef RPC_LSA_DEFAULT
765 #define RPC_LSA_DEFAULT RPC_LED_100
767 #ifndef RPC_LSB_DEFAULT
768 #define RPC_LSB_DEFAULT RPC_LED_FD
771 #define RPC_DEFAULT (RPC_ANEG | RPC_SPEED | RPC_DPLX)
774 /* Bank 0 0x0C is reserved */
776 // Bank Select Register
778 #define BSR_REG 0x000E
783 #define CONFIG_REG(lp) SMC_REG(lp, 0x0000, 1)
784 #define CONFIG_EXT_PHY 0x0200 // 1=external MII, 0=internal Phy
785 #define CONFIG_GPCNTRL 0x0400 // Inverse value drives pin nCNTRL
786 #define CONFIG_NO_WAIT 0x1000 // When 1 no extra wait states on ISA bus
787 #define CONFIG_EPH_POWER_EN 0x8000 // When 0 EPH is placed into low power mode.
789 // Default is powered-up, Internal Phy, Wait States, and pin nCNTRL=low
790 #define CONFIG_DEFAULT (CONFIG_EPH_POWER_EN)
793 // Base Address Register
795 #define BASE_REG(lp) SMC_REG(lp, 0x0002, 1)
798 // Individual Address Registers
800 #define ADDR0_REG(lp) SMC_REG(lp, 0x0004, 1)
801 #define ADDR1_REG(lp) SMC_REG(lp, 0x0006, 1)
802 #define ADDR2_REG(lp) SMC_REG(lp, 0x0008, 1)
805 // General Purpose Register
807 #define GP_REG(lp) SMC_REG(lp, 0x000A, 1)
812 #define CTL_REG(lp) SMC_REG(lp, 0x000C, 1)
813 #define CTL_RCV_BAD 0x4000 // When 1 bad CRC packets are received
814 #define CTL_AUTO_RELEASE 0x0800 // When 1 tx pages are released automatically
815 #define CTL_LE_ENABLE 0x0080 // When 1 enables Link Error interrupt
816 #define CTL_CR_ENABLE 0x0040 // When 1 enables Counter Rollover interrupt
817 #define CTL_TE_ENABLE 0x0020 // When 1 enables Transmit Error interrupt
818 #define CTL_EEPROM_SELECT 0x0004 // Controls EEPROM reload & store
819 #define CTL_RELOAD 0x0002 // When set reads EEPROM into registers
820 #define CTL_STORE 0x0001 // When set stores registers into EEPROM
823 // MMU Command Register
825 #define MMU_CMD_REG(lp) SMC_REG(lp, 0x0000, 2)
826 #define MC_BUSY 1 // When 1 the last release has not completed
827 #define MC_NOP (0<<5) // No Op
828 #define MC_ALLOC (1<<5) // OR with number of 256 byte packets
829 #define MC_RESET (2<<5) // Reset MMU to initial state
830 #define MC_REMOVE (3<<5) // Remove the current rx packet
831 #define MC_RELEASE (4<<5) // Remove and release the current rx packet
832 #define MC_FREEPKT (5<<5) // Release packet in PNR register
833 #define MC_ENQUEUE (6<<5) // Enqueue the packet for transmit
834 #define MC_RSTTXFIFO (7<<5) // Reset the TX FIFOs
837 // Packet Number Register
839 #define PN_REG(lp) SMC_REG(lp, 0x0002, 2)
842 // Allocation Result Register
844 #define AR_REG(lp) SMC_REG(lp, 0x0003, 2)
845 #define AR_FAILED 0x80 // Alocation Failed
848 // TX FIFO Ports Register
850 #define TXFIFO_REG(lp) SMC_REG(lp, 0x0004, 2)
851 #define TXFIFO_TEMPTY 0x80 // TX FIFO Empty
853 // RX FIFO Ports Register
855 #define RXFIFO_REG(lp) SMC_REG(lp, 0x0005, 2)
856 #define RXFIFO_REMPTY 0x80 // RX FIFO Empty
858 #define FIFO_REG(lp) SMC_REG(lp, 0x0004, 2)
862 #define PTR_REG(lp) SMC_REG(lp, 0x0006, 2)
863 #define PTR_RCV 0x8000 // 1=Receive area, 0=Transmit area
864 #define PTR_AUTOINC 0x4000 // Auto increment the pointer on each access
865 #define PTR_READ 0x2000 // When 1 the operation is a read
870 #define DATA_REG(lp) SMC_REG(lp, 0x0008, 2)
873 // Interrupt Status/Acknowledge Register
875 #define INT_REG(lp) SMC_REG(lp, 0x000C, 2)
878 // Interrupt Mask Register
880 #define IM_REG(lp) SMC_REG(lp, 0x000D, 2)
881 #define IM_MDINT 0x80 // PHY MI Register 18 Interrupt
882 #define IM_ERCV_INT 0x40 // Early Receive Interrupt
883 #define IM_EPH_INT 0x20 // Set by Ethernet Protocol Handler section
884 #define IM_RX_OVRN_INT 0x10 // Set by Receiver Overruns
885 #define IM_ALLOC_INT 0x08 // Set when allocation request is completed
886 #define IM_TX_EMPTY_INT 0x04 // Set if the TX FIFO goes empty
887 #define IM_TX_INT 0x02 // Transmit Interrupt
888 #define IM_RCV_INT 0x01 // Receive Interrupt
891 // Multicast Table Registers
893 #define MCAST_REG1(lp) SMC_REG(lp, 0x0000, 3)
894 #define MCAST_REG2(lp) SMC_REG(lp, 0x0002, 3)
895 #define MCAST_REG3(lp) SMC_REG(lp, 0x0004, 3)
896 #define MCAST_REG4(lp) SMC_REG(lp, 0x0006, 3)
899 // Management Interface Register (MII)
901 #define MII_REG(lp) SMC_REG(lp, 0x0008, 3)
902 #define MII_MSK_CRS100 0x4000 // Disables CRS100 detection during tx half dup
903 #define MII_MDOE 0x0008 // MII Output Enable
904 #define MII_MCLK 0x0004 // MII Clock, pin MDCLK
905 #define MII_MDI 0x0002 // MII Input, pin MDI
906 #define MII_MDO 0x0001 // MII Output, pin MDO
911 /* ( hi: chip id low: rev # ) */
912 #define REV_REG(lp) SMC_REG(lp, 0x000A, 3)
915 // Early RCV Register
917 /* this is NOT on SMC9192 */
918 #define ERCV_REG(lp) SMC_REG(lp, 0x000C, 3)
919 #define ERCV_RCV_DISCRD 0x0080 // When 1 discards a packet being received
920 #define ERCV_THRESHOLD 0x001F // ERCV Threshold Mask
925 #define EXT_REG(lp) SMC_REG(lp, 0x0000, 7)
933 #define CHIP_91100FD 8
934 #define CHIP_91111FD 9
936 static const char * chip_ids[ 16 ] = {
938 /* 3 */ "SMC91C90/91C92",
943 /* 8 */ "SMC91C100FD",
944 /* 9 */ "SMC91C11xFD",
950 . Receive status bits
952 #define RS_ALGNERR 0x8000
953 #define RS_BRODCAST 0x4000
954 #define RS_BADCRC 0x2000
955 #define RS_ODDFRAME 0x1000
956 #define RS_TOOLONG 0x0800
957 #define RS_TOOSHORT 0x0400
958 #define RS_MULTICAST 0x0001
959 #define RS_ERRORS (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT)
964 * LAN83C183 == LAN91C111 Internal PHY
966 #define PHY_LAN83C183 0x0016f840
967 #define PHY_LAN83C180 0x02821c50
970 * PHY Register Addresses (LAN91C111 Internal PHY)
972 * Generic PHY registers can be found in <linux/mii.h>
974 * These phy registers are specific to our on-board phy.
977 // PHY Configuration Register 1
978 #define PHY_CFG1_REG 0x10
979 #define PHY_CFG1_LNKDIS 0x8000 // 1=Rx Link Detect Function disabled
980 #define PHY_CFG1_XMTDIS 0x4000 // 1=TP Transmitter Disabled
981 #define PHY_CFG1_XMTPDN 0x2000 // 1=TP Transmitter Powered Down
982 #define PHY_CFG1_BYPSCR 0x0400 // 1=Bypass scrambler/descrambler
983 #define PHY_CFG1_UNSCDS 0x0200 // 1=Unscramble Idle Reception Disable
984 #define PHY_CFG1_EQLZR 0x0100 // 1=Rx Equalizer Disabled
985 #define PHY_CFG1_CABLE 0x0080 // 1=STP(150ohm), 0=UTP(100ohm)
986 #define PHY_CFG1_RLVL0 0x0040 // 1=Rx Squelch level reduced by 4.5db
987 #define PHY_CFG1_TLVL_SHIFT 2 // Transmit Output Level Adjust
988 #define PHY_CFG1_TLVL_MASK 0x003C
989 #define PHY_CFG1_TRF_MASK 0x0003 // Transmitter Rise/Fall time
992 // PHY Configuration Register 2
993 #define PHY_CFG2_REG 0x11
994 #define PHY_CFG2_APOLDIS 0x0020 // 1=Auto Polarity Correction disabled
995 #define PHY_CFG2_JABDIS 0x0010 // 1=Jabber disabled
996 #define PHY_CFG2_MREG 0x0008 // 1=Multiple register access (MII mgt)
997 #define PHY_CFG2_INTMDIO 0x0004 // 1=Interrupt signaled with MDIO pulseo
999 // PHY Status Output (and Interrupt status) Register
1000 #define PHY_INT_REG 0x12 // Status Output (Interrupt Status)
1001 #define PHY_INT_INT 0x8000 // 1=bits have changed since last read
1002 #define PHY_INT_LNKFAIL 0x4000 // 1=Link Not detected
1003 #define PHY_INT_LOSSSYNC 0x2000 // 1=Descrambler has lost sync
1004 #define PHY_INT_CWRD 0x1000 // 1=Invalid 4B5B code detected on rx
1005 #define PHY_INT_SSD 0x0800 // 1=No Start Of Stream detected on rx
1006 #define PHY_INT_ESD 0x0400 // 1=No End Of Stream detected on rx
1007 #define PHY_INT_RPOL 0x0200 // 1=Reverse Polarity detected
1008 #define PHY_INT_JAB 0x0100 // 1=Jabber detected
1009 #define PHY_INT_SPDDET 0x0080 // 1=100Base-TX mode, 0=10Base-T mode
1010 #define PHY_INT_DPLXDET 0x0040 // 1=Device in Full Duplex
1012 // PHY Interrupt/Status Mask Register
1013 #define PHY_MASK_REG 0x13 // Interrupt Mask
1014 // Uses the same bit definitions as PHY_INT_REG
1018 * SMC91C96 ethernet config and status registers.
1019 * These are in the "attribute" space.
1022 #define ECOR_RESET 0x80
1023 #define ECOR_LEVEL_IRQ 0x40
1024 #define ECOR_WR_ATTRIB 0x04
1025 #define ECOR_ENABLE 0x01
1028 #define ECSR_IOIS8 0x20
1029 #define ECSR_PWRDWN 0x04
1030 #define ECSR_INT 0x02
1032 #define ATTRIB_SIZE ((64*1024) << SMC_IO_SHIFT)
1036 * Macros to abstract register access according to the data bus
1037 * capabilities. Please use those and not the in/out primitives.
1038 * Note: the following macros do *not* select the bank -- this must
1039 * be done separately as needed in the main code. The SMC_REG() macro
1040 * only uses the bank argument for debugging purposes (when enabled).
1042 * Note: despite inline functions being safer, everything leading to this
1043 * should preferably be macros to let BUG() display the line number in
1044 * the core source code since we're interested in the top call site
1045 * not in any inline function location.
1049 #define SMC_REG(lp, reg, bank) \
1051 int __b = SMC_CURRENT_BANK(lp); \
1052 if (unlikely((__b & ~0xf0) != (0x3300 | bank))) { \
1053 printk( "%s: bank reg screwed (0x%04x)\n", \
1057 reg<<SMC_IO_SHIFT; \
1060 #define SMC_REG(lp, reg, bank) (reg<<SMC_IO_SHIFT)
1064 * Hack Alert: Some setups just can't write 8 or 16 bits reliably when not
1065 * aligned to a 32 bit boundary. I tell you that does exist!
1066 * Fortunately the affected register accesses can be easily worked around
1067 * since we can write zeroes to the preceeding 16 bits without adverse
1068 * effects and use a 32-bit access.
1070 * Enforce it on any 32-bit capable setup for now.
1072 #define SMC_MUST_ALIGN_WRITE(lp) SMC_32BIT(lp)
1074 #define SMC_GET_PN(lp) \
1075 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, PN_REG(lp))) \
1076 : (SMC_inw(ioaddr, PN_REG(lp)) & 0xFF))
1078 #define SMC_SET_PN(lp, x) \
1080 if (SMC_MUST_ALIGN_WRITE(lp)) \
1081 SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 0, 2)); \
1082 else if (SMC_8BIT(lp)) \
1083 SMC_outb(x, ioaddr, PN_REG(lp)); \
1085 SMC_outw(x, ioaddr, PN_REG(lp)); \
1088 #define SMC_GET_AR(lp) \
1089 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, AR_REG(lp))) \
1090 : (SMC_inw(ioaddr, PN_REG(lp)) >> 8))
1092 #define SMC_GET_TXFIFO(lp) \
1093 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, TXFIFO_REG(lp))) \
1094 : (SMC_inw(ioaddr, TXFIFO_REG(lp)) & 0xFF))
1096 #define SMC_GET_RXFIFO(lp) \
1097 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, RXFIFO_REG(lp))) \
1098 : (SMC_inw(ioaddr, TXFIFO_REG(lp)) >> 8))
1100 #define SMC_GET_INT(lp) \
1101 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, INT_REG(lp))) \
1102 : (SMC_inw(ioaddr, INT_REG(lp)) & 0xFF))
1104 #define SMC_ACK_INT(lp, x) \
1107 SMC_outb(x, ioaddr, INT_REG(lp)); \
1109 unsigned long __flags; \
1111 local_irq_save(__flags); \
1112 __mask = SMC_inw(ioaddr, INT_REG(lp)) & ~0xff; \
1113 SMC_outw(__mask | (x), ioaddr, INT_REG(lp)); \
1114 local_irq_restore(__flags); \
1118 #define SMC_GET_INT_MASK(lp) \
1119 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, IM_REG(lp))) \
1120 : (SMC_inw(ioaddr, INT_REG(lp)) >> 8))
1122 #define SMC_SET_INT_MASK(lp, x) \
1125 SMC_outb(x, ioaddr, IM_REG(lp)); \
1127 SMC_outw((x) << 8, ioaddr, INT_REG(lp)); \
1130 #define SMC_CURRENT_BANK(lp) SMC_inw(ioaddr, BANK_SELECT)
1132 #define SMC_SELECT_BANK(lp, x) \
1134 if (SMC_MUST_ALIGN_WRITE(lp)) \
1135 SMC_outl((x)<<16, ioaddr, 12<<SMC_IO_SHIFT); \
1137 SMC_outw(x, ioaddr, BANK_SELECT); \
1140 #define SMC_GET_BASE(lp) SMC_inw(ioaddr, BASE_REG(lp))
1142 #define SMC_SET_BASE(lp, x) SMC_outw(x, ioaddr, BASE_REG(lp))
1144 #define SMC_GET_CONFIG(lp) SMC_inw(ioaddr, CONFIG_REG(lp))
1146 #define SMC_SET_CONFIG(lp, x) SMC_outw(x, ioaddr, CONFIG_REG(lp))
1148 #define SMC_GET_COUNTER(lp) SMC_inw(ioaddr, COUNTER_REG(lp))
1150 #define SMC_GET_CTL(lp) SMC_inw(ioaddr, CTL_REG(lp))
1152 #define SMC_SET_CTL(lp, x) SMC_outw(x, ioaddr, CTL_REG(lp))
1154 #define SMC_GET_MII(lp) SMC_inw(ioaddr, MII_REG(lp))
1156 #define SMC_SET_MII(lp, x) SMC_outw(x, ioaddr, MII_REG(lp))
1158 #define SMC_GET_MIR(lp) SMC_inw(ioaddr, MIR_REG(lp))
1160 #define SMC_SET_MIR(lp, x) SMC_outw(x, ioaddr, MIR_REG(lp))
1162 #define SMC_GET_MMU_CMD(lp) SMC_inw(ioaddr, MMU_CMD_REG(lp))
1164 #define SMC_SET_MMU_CMD(lp, x) SMC_outw(x, ioaddr, MMU_CMD_REG(lp))
1166 #define SMC_GET_FIFO(lp) SMC_inw(ioaddr, FIFO_REG(lp))
1168 #define SMC_GET_PTR(lp) SMC_inw(ioaddr, PTR_REG(lp))
1170 #define SMC_SET_PTR(lp, x) \
1172 if (SMC_MUST_ALIGN_WRITE(lp)) \
1173 SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 4, 2)); \
1175 SMC_outw(x, ioaddr, PTR_REG(lp)); \
1178 #define SMC_GET_EPH_STATUS(lp) SMC_inw(ioaddr, EPH_STATUS_REG(lp))
1180 #define SMC_GET_RCR(lp) SMC_inw(ioaddr, RCR_REG(lp))
1182 #define SMC_SET_RCR(lp, x) SMC_outw(x, ioaddr, RCR_REG(lp))
1184 #define SMC_GET_REV(lp) SMC_inw(ioaddr, REV_REG(lp))
1186 #define SMC_GET_RPC(lp) SMC_inw(ioaddr, RPC_REG(lp))
1188 #define SMC_SET_RPC(lp, x) \
1190 if (SMC_MUST_ALIGN_WRITE(lp)) \
1191 SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 8, 0)); \
1193 SMC_outw(x, ioaddr, RPC_REG(lp)); \
1196 #define SMC_GET_TCR(lp) SMC_inw(ioaddr, TCR_REG(lp))
1198 #define SMC_SET_TCR(lp, x) SMC_outw(x, ioaddr, TCR_REG(lp))
1200 #ifndef SMC_GET_MAC_ADDR
1201 #define SMC_GET_MAC_ADDR(lp, addr) \
1204 __v = SMC_inw(ioaddr, ADDR0_REG(lp)); \
1205 addr[0] = __v; addr[1] = __v >> 8; \
1206 __v = SMC_inw(ioaddr, ADDR1_REG(lp)); \
1207 addr[2] = __v; addr[3] = __v >> 8; \
1208 __v = SMC_inw(ioaddr, ADDR2_REG(lp)); \
1209 addr[4] = __v; addr[5] = __v >> 8; \
1213 #define SMC_SET_MAC_ADDR(lp, addr) \
1215 SMC_outw(addr[0]|(addr[1] << 8), ioaddr, ADDR0_REG(lp)); \
1216 SMC_outw(addr[2]|(addr[3] << 8), ioaddr, ADDR1_REG(lp)); \
1217 SMC_outw(addr[4]|(addr[5] << 8), ioaddr, ADDR2_REG(lp)); \
1220 #define SMC_SET_MCAST(lp, x) \
1222 const unsigned char *mt = (x); \
1223 SMC_outw(mt[0] | (mt[1] << 8), ioaddr, MCAST_REG1(lp)); \
1224 SMC_outw(mt[2] | (mt[3] << 8), ioaddr, MCAST_REG2(lp)); \
1225 SMC_outw(mt[4] | (mt[5] << 8), ioaddr, MCAST_REG3(lp)); \
1226 SMC_outw(mt[6] | (mt[7] << 8), ioaddr, MCAST_REG4(lp)); \
1229 #define SMC_PUT_PKT_HDR(lp, status, length) \
1231 if (SMC_32BIT(lp)) \
1232 SMC_outl((status) | (length)<<16, ioaddr, \
1235 SMC_outw(status, ioaddr, DATA_REG(lp)); \
1236 SMC_outw(length, ioaddr, DATA_REG(lp)); \
1240 #define SMC_GET_PKT_HDR(lp, status, length) \
1242 if (SMC_32BIT(lp)) { \
1243 unsigned int __val = SMC_inl(ioaddr, DATA_REG(lp)); \
1244 (status) = __val & 0xffff; \
1245 (length) = __val >> 16; \
1247 (status) = SMC_inw(ioaddr, DATA_REG(lp)); \
1248 (length) = SMC_inw(ioaddr, DATA_REG(lp)); \
1252 #define SMC_PUSH_DATA(lp, p, l) \
1254 if (SMC_32BIT(lp)) { \
1255 void *__ptr = (p); \
1257 void __iomem *__ioaddr = ioaddr; \
1258 if (__len >= 2 && (unsigned long)__ptr & 2) { \
1260 SMC_outw(*(u16 *)__ptr, ioaddr, \
1264 if (SMC_CAN_USE_DATACS && lp->datacs) \
1265 __ioaddr = lp->datacs; \
1266 SMC_outsl(__ioaddr, DATA_REG(lp), __ptr, __len>>2); \
1268 __ptr += (__len & ~3); \
1269 SMC_outw(*((u16 *)__ptr), ioaddr, \
1272 } else if (SMC_16BIT(lp)) \
1273 SMC_outsw(ioaddr, DATA_REG(lp), p, (l) >> 1); \
1274 else if (SMC_8BIT(lp)) \
1275 SMC_outsb(ioaddr, DATA_REG(lp), p, l); \
1278 #define SMC_PULL_DATA(lp, p, l) \
1280 if (SMC_32BIT(lp)) { \
1281 void *__ptr = (p); \
1283 void __iomem *__ioaddr = ioaddr; \
1284 if ((unsigned long)__ptr & 2) { \
1286 * We want 32bit alignment here. \
1287 * Since some buses perform a full \
1288 * 32bit fetch even for 16bit data \
1289 * we can't use SMC_inw() here. \
1290 * Back both source (on-chip) and \
1291 * destination pointers of 2 bytes. \
1292 * This is possible since the call to \
1293 * SMC_GET_PKT_HDR() already advanced \
1294 * the source pointer of 4 bytes, and \
1295 * the skb_reserve(skb, 2) advanced \
1296 * the destination pointer of 2 bytes. \
1301 2|PTR_READ|PTR_RCV|PTR_AUTOINC); \
1303 if (SMC_CAN_USE_DATACS && lp->datacs) \
1304 __ioaddr = lp->datacs; \
1306 SMC_insl(__ioaddr, DATA_REG(lp), __ptr, __len>>2); \
1307 } else if (SMC_16BIT(lp)) \
1308 SMC_insw(ioaddr, DATA_REG(lp), p, (l) >> 1); \
1309 else if (SMC_8BIT(lp)) \
1310 SMC_insb(ioaddr, DATA_REG(lp), p, l); \
1313 #endif /* _SMC91X_H_ */