1 /***************************************************************************
3 * Copyright (C) 2004-2008 SMSC
4 * Copyright (C) 2005-2008 ARM
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 ***************************************************************************/
21 #ifndef __SMSC911X_H__
22 #define __SMSC911X_H__
24 #define SMSC_CAN_USE_32BIT 1
25 #define TX_FIFO_LOW_THRESHOLD ((u32)1600)
26 #define SMSC911X_EEPROM_SIZE ((u32)7)
29 /* This is the maximum number of packets to be received every
31 #define SMSC_NAPI_WEIGHT 16
33 /* implements a PHY loopback test at initialisation time, to ensure a packet
34 * can be succesfully looped back */
35 #define USE_PHY_WORK_AROUND
37 #define DPRINTK(nlevel, klevel, fmt, args...) \
38 ((void)((NETIF_MSG_##nlevel & pdata->msg_enable) && \
39 printk(KERN_##klevel "%s: %s: " fmt "\n", \
40 pdata->dev->name, __func__, ## args)))
43 #define SMSC_WARNING(nlevel, fmt, args...) \
44 DPRINTK(nlevel, WARNING, fmt, ## args)
46 #define SMSC_WARNING(nlevel, fmt, args...) \
47 ({ do {} while (0); 0; })
51 #define SMSC_TRACE(nlevel, fmt, args...) \
52 DPRINTK(nlevel, INFO, fmt, ## args)
54 #define SMSC_TRACE(nlevel, fmt, args...) \
55 ({ do {} while (0); 0; })
58 #ifdef CONFIG_DEBUG_SPINLOCK
59 #define SMSC_ASSERT_MAC_LOCK(pdata) \
60 WARN_ON(!spin_is_locked(&pdata->mac_lock))
62 #define SMSC_ASSERT_MAC_LOCK(pdata) do {} while (0)
63 #endif /* CONFIG_DEBUG_SPINLOCK */
65 #define FLOW_CTRL_TX (1)
66 #define FLOW_CTRL_RX (2)
68 /* SMSC911x registers and bitfields */
69 #define RX_DATA_FIFO 0x00
71 #define TX_DATA_FIFO 0x20
72 #define TX_CMD_A_ON_COMP_ 0x80000000
73 #define TX_CMD_A_BUF_END_ALGN_ 0x03000000
74 #define TX_CMD_A_4_BYTE_ALGN_ 0x00000000
75 #define TX_CMD_A_16_BYTE_ALGN_ 0x01000000
76 #define TX_CMD_A_32_BYTE_ALGN_ 0x02000000
77 #define TX_CMD_A_DATA_OFFSET_ 0x001F0000
78 #define TX_CMD_A_FIRST_SEG_ 0x00002000
79 #define TX_CMD_A_LAST_SEG_ 0x00001000
80 #define TX_CMD_A_BUF_SIZE_ 0x000007FF
81 #define TX_CMD_B_PKT_TAG_ 0xFFFF0000
82 #define TX_CMD_B_ADD_CRC_DISABLE_ 0x00002000
83 #define TX_CMD_B_DISABLE_PADDING_ 0x00001000
84 #define TX_CMD_B_PKT_BYTE_LENGTH_ 0x000007FF
86 #define RX_STATUS_FIFO 0x40
87 #define RX_STS_ES_ 0x00008000
88 #define RX_STS_MCAST_ 0x00000400
90 #define RX_STATUS_FIFO_PEEK 0x44
92 #define TX_STATUS_FIFO 0x48
93 #define TX_STS_ES_ 0x00008000
95 #define TX_STATUS_FIFO_PEEK 0x4C
98 #define ID_REV_CHIP_ID_ 0xFFFF0000
99 #define ID_REV_REV_ID_ 0x0000FFFF
102 #define INT_CFG_INT_DEAS_ 0xFF000000
103 #define INT_CFG_INT_DEAS_CLR_ 0x00004000
104 #define INT_CFG_INT_DEAS_STS_ 0x00002000
105 #define INT_CFG_IRQ_INT_ 0x00001000
106 #define INT_CFG_IRQ_EN_ 0x00000100
107 #define INT_CFG_IRQ_POL_ 0x00000010
108 #define INT_CFG_IRQ_TYPE_ 0x00000001
111 #define INT_STS_SW_INT_ 0x80000000
112 #define INT_STS_TXSTOP_INT_ 0x02000000
113 #define INT_STS_RXSTOP_INT_ 0x01000000
114 #define INT_STS_RXDFH_INT_ 0x00800000
115 #define INT_STS_RXDF_INT_ 0x00400000
116 #define INT_STS_TX_IOC_ 0x00200000
117 #define INT_STS_RXD_INT_ 0x00100000
118 #define INT_STS_GPT_INT_ 0x00080000
119 #define INT_STS_PHY_INT_ 0x00040000
120 #define INT_STS_PME_INT_ 0x00020000
121 #define INT_STS_TXSO_ 0x00010000
122 #define INT_STS_RWT_ 0x00008000
123 #define INT_STS_RXE_ 0x00004000
124 #define INT_STS_TXE_ 0x00002000
125 #define INT_STS_TDFU_ 0x00000800
126 #define INT_STS_TDFO_ 0x00000400
127 #define INT_STS_TDFA_ 0x00000200
128 #define INT_STS_TSFF_ 0x00000100
129 #define INT_STS_TSFL_ 0x00000080
130 #define INT_STS_RXDF_ 0x00000040
131 #define INT_STS_RDFL_ 0x00000020
132 #define INT_STS_RSFF_ 0x00000010
133 #define INT_STS_RSFL_ 0x00000008
134 #define INT_STS_GPIO2_INT_ 0x00000004
135 #define INT_STS_GPIO1_INT_ 0x00000002
136 #define INT_STS_GPIO0_INT_ 0x00000001
139 #define INT_EN_SW_INT_EN_ 0x80000000
140 #define INT_EN_TXSTOP_INT_EN_ 0x02000000
141 #define INT_EN_RXSTOP_INT_EN_ 0x01000000
142 #define INT_EN_RXDFH_INT_EN_ 0x00800000
143 #define INT_EN_TIOC_INT_EN_ 0x00200000
144 #define INT_EN_RXD_INT_EN_ 0x00100000
145 #define INT_EN_GPT_INT_EN_ 0x00080000
146 #define INT_EN_PHY_INT_EN_ 0x00040000
147 #define INT_EN_PME_INT_EN_ 0x00020000
148 #define INT_EN_TXSO_EN_ 0x00010000
149 #define INT_EN_RWT_EN_ 0x00008000
150 #define INT_EN_RXE_EN_ 0x00004000
151 #define INT_EN_TXE_EN_ 0x00002000
152 #define INT_EN_TDFU_EN_ 0x00000800
153 #define INT_EN_TDFO_EN_ 0x00000400
154 #define INT_EN_TDFA_EN_ 0x00000200
155 #define INT_EN_TSFF_EN_ 0x00000100
156 #define INT_EN_TSFL_EN_ 0x00000080
157 #define INT_EN_RXDF_EN_ 0x00000040
158 #define INT_EN_RDFL_EN_ 0x00000020
159 #define INT_EN_RSFF_EN_ 0x00000010
160 #define INT_EN_RSFL_EN_ 0x00000008
161 #define INT_EN_GPIO2_INT_ 0x00000004
162 #define INT_EN_GPIO1_INT_ 0x00000002
163 #define INT_EN_GPIO0_INT_ 0x00000001
165 #define BYTE_TEST 0x64
167 #define FIFO_INT 0x68
168 #define FIFO_INT_TX_AVAIL_LEVEL_ 0xFF000000
169 #define FIFO_INT_TX_STS_LEVEL_ 0x00FF0000
170 #define FIFO_INT_RX_AVAIL_LEVEL_ 0x0000FF00
171 #define FIFO_INT_RX_STS_LEVEL_ 0x000000FF
174 #define RX_CFG_RX_END_ALGN_ 0xC0000000
175 #define RX_CFG_RX_END_ALGN4_ 0x00000000
176 #define RX_CFG_RX_END_ALGN16_ 0x40000000
177 #define RX_CFG_RX_END_ALGN32_ 0x80000000
178 #define RX_CFG_RX_DMA_CNT_ 0x0FFF0000
179 #define RX_CFG_RX_DUMP_ 0x00008000
180 #define RX_CFG_RXDOFF_ 0x00001F00
183 #define TX_CFG_TXS_DUMP_ 0x00008000
184 #define TX_CFG_TXD_DUMP_ 0x00004000
185 #define TX_CFG_TXSAO_ 0x00000004
186 #define TX_CFG_TX_ON_ 0x00000002
187 #define TX_CFG_STOP_TX_ 0x00000001
190 #define HW_CFG_TTM_ 0x00200000
191 #define HW_CFG_SF_ 0x00100000
192 #define HW_CFG_TX_FIF_SZ_ 0x000F0000
193 #define HW_CFG_TR_ 0x00003000
194 #define HW_CFG_SRST_ 0x00000001
196 /* only available on 115/117 */
197 #define HW_CFG_PHY_CLK_SEL_ 0x00000060
198 #define HW_CFG_PHY_CLK_SEL_INT_PHY_ 0x00000000
199 #define HW_CFG_PHY_CLK_SEL_EXT_PHY_ 0x00000020
200 #define HW_CFG_PHY_CLK_SEL_CLK_DIS_ 0x00000040
201 #define HW_CFG_SMI_SEL_ 0x00000010
202 #define HW_CFG_EXT_PHY_DET_ 0x00000008
203 #define HW_CFG_EXT_PHY_EN_ 0x00000004
204 #define HW_CFG_SRST_TO_ 0x00000002
206 /* only available on 116/118 */
207 #define HW_CFG_32_16_BIT_MODE_ 0x00000004
209 #define RX_DP_CTRL 0x78
210 #define RX_DP_CTRL_RX_FFWD_ 0x80000000
212 #define RX_FIFO_INF 0x7C
213 #define RX_FIFO_INF_RXSUSED_ 0x00FF0000
214 #define RX_FIFO_INF_RXDUSED_ 0x0000FFFF
216 #define TX_FIFO_INF 0x80
217 #define TX_FIFO_INF_TSUSED_ 0x00FF0000
218 #define TX_FIFO_INF_TDFREE_ 0x0000FFFF
220 #define PMT_CTRL 0x84
221 #define PMT_CTRL_PM_MODE_ 0x00003000
222 #define PMT_CTRL_PM_MODE_D0_ 0x00000000
223 #define PMT_CTRL_PM_MODE_D1_ 0x00001000
224 #define PMT_CTRL_PM_MODE_D2_ 0x00002000
225 #define PMT_CTRL_PM_MODE_D3_ 0x00003000
226 #define PMT_CTRL_PHY_RST_ 0x00000400
227 #define PMT_CTRL_WOL_EN_ 0x00000200
228 #define PMT_CTRL_ED_EN_ 0x00000100
229 #define PMT_CTRL_PME_TYPE_ 0x00000040
230 #define PMT_CTRL_WUPS_ 0x00000030
231 #define PMT_CTRL_WUPS_NOWAKE_ 0x00000000
232 #define PMT_CTRL_WUPS_ED_ 0x00000010
233 #define PMT_CTRL_WUPS_WOL_ 0x00000020
234 #define PMT_CTRL_WUPS_MULTI_ 0x00000030
235 #define PMT_CTRL_PME_IND_ 0x00000008
236 #define PMT_CTRL_PME_POL_ 0x00000004
237 #define PMT_CTRL_PME_EN_ 0x00000002
238 #define PMT_CTRL_READY_ 0x00000001
240 #define GPIO_CFG 0x88
241 #define GPIO_CFG_LED3_EN_ 0x40000000
242 #define GPIO_CFG_LED2_EN_ 0x20000000
243 #define GPIO_CFG_LED1_EN_ 0x10000000
244 #define GPIO_CFG_GPIO2_INT_POL_ 0x04000000
245 #define GPIO_CFG_GPIO1_INT_POL_ 0x02000000
246 #define GPIO_CFG_GPIO0_INT_POL_ 0x01000000
247 #define GPIO_CFG_EEPR_EN_ 0x00700000
248 #define GPIO_CFG_GPIOBUF2_ 0x00040000
249 #define GPIO_CFG_GPIOBUF1_ 0x00020000
250 #define GPIO_CFG_GPIOBUF0_ 0x00010000
251 #define GPIO_CFG_GPIODIR2_ 0x00000400
252 #define GPIO_CFG_GPIODIR1_ 0x00000200
253 #define GPIO_CFG_GPIODIR0_ 0x00000100
254 #define GPIO_CFG_GPIOD4_ 0x00000020
255 #define GPIO_CFG_GPIOD3_ 0x00000010
256 #define GPIO_CFG_GPIOD2_ 0x00000004
257 #define GPIO_CFG_GPIOD1_ 0x00000002
258 #define GPIO_CFG_GPIOD0_ 0x00000001
261 #define GPT_CFG_TIMER_EN_ 0x20000000
262 #define GPT_CFG_GPT_LOAD_ 0x0000FFFF
265 #define GPT_CNT_GPT_CNT_ 0x0000FFFF
267 #define WORD_SWAP 0x98
269 #define FREE_RUN 0x9C
273 #define MAC_CSR_CMD 0xA4
274 #define MAC_CSR_CMD_CSR_BUSY_ 0x80000000
275 #define MAC_CSR_CMD_R_NOT_W_ 0x40000000
276 #define MAC_CSR_CMD_CSR_ADDR_ 0x000000FF
278 #define MAC_CSR_DATA 0xA8
281 #define AFC_CFG_AFC_HI_ 0x00FF0000
282 #define AFC_CFG_AFC_LO_ 0x0000FF00
283 #define AFC_CFG_BACK_DUR_ 0x000000F0
284 #define AFC_CFG_FCMULT_ 0x00000008
285 #define AFC_CFG_FCBRD_ 0x00000004
286 #define AFC_CFG_FCADD_ 0x00000002
287 #define AFC_CFG_FCANY_ 0x00000001
290 #define E2P_CMD_EPC_BUSY_ 0x80000000
291 #define E2P_CMD_EPC_CMD_ 0x70000000
292 #define E2P_CMD_EPC_CMD_READ_ 0x00000000
293 #define E2P_CMD_EPC_CMD_EWDS_ 0x10000000
294 #define E2P_CMD_EPC_CMD_EWEN_ 0x20000000
295 #define E2P_CMD_EPC_CMD_WRITE_ 0x30000000
296 #define E2P_CMD_EPC_CMD_WRAL_ 0x40000000
297 #define E2P_CMD_EPC_CMD_ERASE_ 0x50000000
298 #define E2P_CMD_EPC_CMD_ERAL_ 0x60000000
299 #define E2P_CMD_EPC_CMD_RELOAD_ 0x70000000
300 #define E2P_CMD_EPC_TIMEOUT_ 0x00000200
301 #define E2P_CMD_MAC_ADDR_LOADED_ 0x00000100
302 #define E2P_CMD_EPC_ADDR_ 0x000000FF
304 #define E2P_DATA 0xB4
305 #define E2P_DATA_EEPROM_DATA_ 0x000000FF
306 #define LAN_REGISTER_EXTENT 0x00000100
309 * MAC Control and Status Register (Indirect Address)
310 * Offset (through the MAC_CSR CMD and DATA port)
313 #define MAC_CR_RXALL_ 0x80000000
314 #define MAC_CR_HBDIS_ 0x10000000
315 #define MAC_CR_RCVOWN_ 0x00800000
316 #define MAC_CR_LOOPBK_ 0x00200000
317 #define MAC_CR_FDPX_ 0x00100000
318 #define MAC_CR_MCPAS_ 0x00080000
319 #define MAC_CR_PRMS_ 0x00040000
320 #define MAC_CR_INVFILT_ 0x00020000
321 #define MAC_CR_PASSBAD_ 0x00010000
322 #define MAC_CR_HFILT_ 0x00008000
323 #define MAC_CR_HPFILT_ 0x00002000
324 #define MAC_CR_LCOLL_ 0x00001000
325 #define MAC_CR_BCAST_ 0x00000800
326 #define MAC_CR_DISRTY_ 0x00000400
327 #define MAC_CR_PADSTR_ 0x00000100
328 #define MAC_CR_BOLMT_MASK_ 0x000000C0
329 #define MAC_CR_DFCHK_ 0x00000020
330 #define MAC_CR_TXEN_ 0x00000008
331 #define MAC_CR_RXEN_ 0x00000004
342 #define MII_ACC_PHY_ADDR_ 0x0000F800
343 #define MII_ACC_MIIRINDA_ 0x000007C0
344 #define MII_ACC_MII_WRITE_ 0x00000002
345 #define MII_ACC_MII_BUSY_ 0x00000001
347 #define MII_DATA 0x07
350 #define FLOW_FCPT_ 0xFFFF0000
351 #define FLOW_FCPASS_ 0x00000004
352 #define FLOW_FCEN_ 0x00000002
353 #define FLOW_FCBSY_ 0x00000001
362 #define WUCSR_GUE_ 0x00000200
363 #define WUCSR_WUFR_ 0x00000040
364 #define WUCSR_MPR_ 0x00000020
365 #define WUCSR_WAKE_EN_ 0x00000004
366 #define WUCSR_MPEN_ 0x00000002
369 * Phy definitions (vendor-specific)
371 #define LAN9118_PHY_ID 0x00C0001C
373 #define MII_INTSTS 0x1D
375 #define MII_INTMSK 0x1E
376 #define PHY_INTMSK_AN_RCV_ (1 << 1)
377 #define PHY_INTMSK_PDFAULT_ (1 << 2)
378 #define PHY_INTMSK_AN_ACK_ (1 << 3)
379 #define PHY_INTMSK_LNKDOWN_ (1 << 4)
380 #define PHY_INTMSK_RFAULT_ (1 << 5)
381 #define PHY_INTMSK_AN_COMP_ (1 << 6)
382 #define PHY_INTMSK_ENERGYON_ (1 << 7)
383 #define PHY_INTMSK_DEFAULT_ (PHY_INTMSK_ENERGYON_ | \
384 PHY_INTMSK_AN_COMP_ | \
385 PHY_INTMSK_RFAULT_ | \
388 #define ADVERTISE_PAUSE_ALL (ADVERTISE_PAUSE_CAP | \
389 ADVERTISE_PAUSE_ASYM)
391 #define LPA_PAUSE_ALL (LPA_PAUSE_CAP | \
394 #endif /* __SMSC911X_H__ */