1 /* starfire.c: Linux device driver for the Adaptec Starfire network adapter. */
3 Written 1998-2000 by Donald Becker.
5 Current maintainer is Ion Badulescu <ionut ta badula tod org>. Please
6 send all bug reports to me, and not to Donald Becker, as this code
7 has been heavily modified from Donald's original version.
9 This software may be used and distributed according to the terms of
10 the GNU General Public License (GPL), incorporated herein by reference.
11 Drivers based on or derived from this code fall under the GPL and must
12 retain the authorship, copyright and license notice. This file is not
13 a complete program and may only be used when the entire operating
14 system is licensed under the GPL.
16 The information below comes from Donald Becker's original driver:
18 The author may be reached as becker@scyld.com, or C/O
19 Scyld Computing Corporation
20 410 Severn Ave., Suite 210
23 Support and updates available at
24 http://www.scyld.com/network/starfire.html
25 [link no longer provides useful info -jgarzik]
29 #define DRV_NAME "starfire"
30 #define DRV_VERSION "2.1"
31 #define DRV_RELDATE "July 6, 2008"
33 #include <linux/module.h>
34 #include <linux/kernel.h>
35 #include <linux/pci.h>
36 #include <linux/netdevice.h>
37 #include <linux/etherdevice.h>
38 #include <linux/init.h>
39 #include <linux/delay.h>
40 #include <linux/crc32.h>
41 #include <linux/ethtool.h>
42 #include <linux/mii.h>
43 #include <linux/if_vlan.h>
45 #include <asm/processor.h> /* Processor type for cache alignment. */
46 #include <asm/uaccess.h>
49 #include "starfire_firmware.h"
51 * The current frame processor firmware fails to checksum a fragment
52 * of length 1. If and when this is fixed, the #define below can be removed.
54 #define HAS_BROKEN_FIRMWARE
57 * If using the broken firmware, data must be padded to the next 32-bit boundary.
59 #ifdef HAS_BROKEN_FIRMWARE
60 #define PADDING_MASK 3
64 * Define this if using the driver with the zero-copy patch
68 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
72 /* The user-configurable values.
73 These may be modified when a driver module is loaded.*/
75 /* Used for tuning interrupt latency vs. overhead. */
76 static int intr_latency;
77 static int small_frames;
79 static int debug = 1; /* 1 normal messages, 0 quiet .. 7 verbose. */
80 static int max_interrupt_work = 20;
82 /* Maximum number of multicast addresses to filter (vs. rx-all-multicast).
83 The Starfire has a 512 element hash table based on the Ethernet CRC. */
84 static const int multicast_filter_limit = 512;
85 /* Whether to do TCP/UDP checksums in hardware */
86 static int enable_hw_cksum = 1;
88 #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
90 * Set the copy breakpoint for the copy-only-tiny-frames scheme.
91 * Setting to > 1518 effectively disables this feature.
94 * The ia64 doesn't allow for unaligned loads even of integers being
95 * misaligned on a 2 byte boundary. Thus always force copying of
96 * packets as the starfire doesn't allow for misaligned DMAs ;-(
99 * The Alpha and the Sparc don't like unaligned loads, either. On Sparc64,
100 * at least, having unaligned frames leads to a rather serious performance
103 #if defined(__ia64__) || defined(__alpha__) || defined(__sparc__)
104 static int rx_copybreak = PKT_BUF_SZ;
106 static int rx_copybreak /* = 0 */;
109 /* PCI DMA burst size -- on sparc64 we want to force it to 64 bytes, on the others the default of 128 is fine. */
111 #define DMA_BURST_SIZE 64
113 #define DMA_BURST_SIZE 128
116 /* Used to pass the media type, etc.
117 Both 'options[]' and 'full_duplex[]' exist for driver interoperability.
118 The media type is usually passed in 'options[]'.
119 These variables are deprecated, use ethtool instead. -Ion
121 #define MAX_UNITS 8 /* More are supported, limit only on options */
122 static int options[MAX_UNITS] = {0, };
123 static int full_duplex[MAX_UNITS] = {0, };
125 /* Operational parameters that are set at compile time. */
127 /* The "native" ring sizes are either 256 or 2048.
128 However in some modes a descriptor may be marked to wrap the ring earlier.
130 #define RX_RING_SIZE 256
131 #define TX_RING_SIZE 32
132 /* The completion queues are fixed at 1024 entries i.e. 4K or 8KB. */
133 #define DONE_Q_SIZE 1024
134 /* All queues must be aligned on a 256-byte boundary */
135 #define QUEUE_ALIGN 256
137 #if RX_RING_SIZE > 256
138 #define RX_Q_ENTRIES Rx2048QEntries
140 #define RX_Q_ENTRIES Rx256QEntries
143 /* Operational parameters that usually are not changed. */
144 /* Time in jiffies before concluding the transmitter is hung. */
145 #define TX_TIMEOUT (2 * HZ)
149 * We need a much better method to determine if dma_addr_t is 64-bit.
151 #if (defined(__i386__) && defined(CONFIG_HIGHMEM64G)) || defined(__x86_64__) || defined (__ia64__) || defined(__alpha__) || defined(__mips64__) || (defined(__mips__) && defined(CONFIG_HIGHMEM) && defined(CONFIG_64BIT_PHYS_ADDR))
152 /* 64-bit dma_addr_t */
153 #define ADDR_64BITS /* This chip uses 64 bit addresses. */
154 #define netdrv_addr_t __le64
155 #define cpu_to_dma(x) cpu_to_le64(x)
156 #define dma_to_cpu(x) le64_to_cpu(x)
157 #define RX_DESC_Q_ADDR_SIZE RxDescQAddr64bit
158 #define TX_DESC_Q_ADDR_SIZE TxDescQAddr64bit
159 #define RX_COMPL_Q_ADDR_SIZE RxComplQAddr64bit
160 #define TX_COMPL_Q_ADDR_SIZE TxComplQAddr64bit
161 #define RX_DESC_ADDR_SIZE RxDescAddr64bit
162 #else /* 32-bit dma_addr_t */
163 #define netdrv_addr_t __le32
164 #define cpu_to_dma(x) cpu_to_le32(x)
165 #define dma_to_cpu(x) le32_to_cpu(x)
166 #define RX_DESC_Q_ADDR_SIZE RxDescQAddr32bit
167 #define TX_DESC_Q_ADDR_SIZE TxDescQAddr32bit
168 #define RX_COMPL_Q_ADDR_SIZE RxComplQAddr32bit
169 #define TX_COMPL_Q_ADDR_SIZE TxComplQAddr32bit
170 #define RX_DESC_ADDR_SIZE RxDescAddr32bit
173 #define skb_first_frag_len(skb) skb_headlen(skb)
174 #define skb_num_frags(skb) (skb_shinfo(skb)->nr_frags + 1)
176 /* These identify the driver base version and may not be removed. */
177 static char version[] =
178 KERN_INFO "starfire.c:v1.03 7/26/2000 Written by Donald Becker <becker@scyld.com>\n"
179 KERN_INFO " (unofficial 2.2/2.4 kernel port, version " DRV_VERSION ", " DRV_RELDATE ")\n";
181 MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
182 MODULE_DESCRIPTION("Adaptec Starfire Ethernet driver");
183 MODULE_LICENSE("GPL");
184 MODULE_VERSION(DRV_VERSION);
186 module_param(max_interrupt_work, int, 0);
187 module_param(mtu, int, 0);
188 module_param(debug, int, 0);
189 module_param(rx_copybreak, int, 0);
190 module_param(intr_latency, int, 0);
191 module_param(small_frames, int, 0);
192 module_param_array(options, int, NULL, 0);
193 module_param_array(full_duplex, int, NULL, 0);
194 module_param(enable_hw_cksum, int, 0);
195 MODULE_PARM_DESC(max_interrupt_work, "Maximum events handled per interrupt");
196 MODULE_PARM_DESC(mtu, "MTU (all boards)");
197 MODULE_PARM_DESC(debug, "Debug level (0-6)");
198 MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
199 MODULE_PARM_DESC(intr_latency, "Maximum interrupt latency, in microseconds");
200 MODULE_PARM_DESC(small_frames, "Maximum size of receive frames that bypass interrupt latency (0,64,128,256,512)");
201 MODULE_PARM_DESC(options, "Deprecated: Bits 0-3: media type, bit 17: full duplex");
202 MODULE_PARM_DESC(full_duplex, "Deprecated: Forced full-duplex setting (0/1)");
203 MODULE_PARM_DESC(enable_hw_cksum, "Enable/disable hardware cksum support (0/1)");
208 I. Board Compatibility
210 This driver is for the Adaptec 6915 "Starfire" 64 bit PCI Ethernet adapter.
212 II. Board-specific settings
214 III. Driver operation
218 The Starfire hardware uses multiple fixed-size descriptor queues/rings. The
219 ring sizes are set fixed by the hardware, but may optionally be wrapped
220 earlier by the END bit in the descriptor.
221 This driver uses that hardware queue size for the Rx ring, where a large
222 number of entries has no ill effect beyond increases the potential backlog.
223 The Tx ring is wrapped with the END bit, since a large hardware Tx queue
224 disables the queue layer priority ordering and we have no mechanism to
225 utilize the hardware two-level priority queue. When modifying the
226 RX/TX_RING_SIZE pay close attention to page sizes and the ring-empty warning
229 IIIb/c. Transmit/Receive Structure
231 See the Adaptec manual for the many possible structures, and options for
232 each structure. There are far too many to document all of them here.
234 For transmit this driver uses type 0/1 transmit descriptors (depending
235 on the 32/64 bitness of the architecture), and relies on automatic
236 minimum-length padding. It does not use the completion queue
237 consumer index, but instead checks for non-zero status entries.
239 For receive this driver uses type 2/3 receive descriptors. The driver
240 allocates full frame size skbuffs for the Rx ring buffers, so all frames
241 should fit in a single descriptor. The driver does not use the completion
242 queue consumer index, but instead checks for non-zero status entries.
244 When an incoming frame is less than RX_COPYBREAK bytes long, a fresh skbuff
245 is allocated and the frame is copied to the new skbuff. When the incoming
246 frame is larger, the skbuff is passed directly up the protocol stack.
247 Buffers consumed this way are replaced by newly allocated skbuffs in a later
250 A notable aspect of operation is that unaligned buffers are not permitted by
251 the Starfire hardware. Thus the IP header at offset 14 in an ethernet frame
252 isn't longword aligned, which may cause problems on some machine
253 e.g. Alphas and IA64. For these architectures, the driver is forced to copy
254 the frame into a new skbuff unconditionally. Copied frames are put into the
255 skbuff at an offset of "+2", thus 16-byte aligning the IP header.
257 IIId. Synchronization
259 The driver runs as two independent, single-threaded flows of control. One
260 is the send-packet routine, which enforces single-threaded use by the
261 dev->tbusy flag. The other thread is the interrupt handler, which is single
262 threaded by the hardware and interrupt handling software.
264 The send packet thread has partial control over the Tx ring and the netif_queue
265 status. If the number of free Tx slots in the ring falls below a certain number
266 (currently hardcoded to 4), it signals the upper layer to stop the queue.
268 The interrupt handler has exclusive control over the Rx ring and records stats
269 from the Tx ring. After reaping the stats, it marks the Tx queue entry as
270 empty by incrementing the dirty_tx mark. Iff the netif_queue is stopped and the
271 number of free Tx slow is above the threshold, it signals the upper layer to
278 The Adaptec Starfire manuals, available only from Adaptec.
279 http://www.scyld.com/expert/100mbps.html
280 http://www.scyld.com/expert/NWay.html
284 - StopOnPerr is broken, don't enable
285 - Hardware ethernet padding exposes random data, perform software padding
286 instead (unverified -- works correctly for all the hardware I have)
292 enum chip_capability_flags {CanHaveMII=1, };
298 static struct pci_device_id starfire_pci_tbl[] = {
299 { 0x9004, 0x6915, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_6915 },
302 MODULE_DEVICE_TABLE(pci, starfire_pci_tbl);
304 /* A chip capabilities table, matching the CH_xxx entries in xxx_pci_tbl[] above. */
305 static const struct chip_info {
308 } netdrv_tbl[] __devinitdata = {
309 { "Adaptec Starfire 6915", CanHaveMII },
313 /* Offsets to the device registers.
314 Unlike software-only systems, device drivers interact with complex hardware.
315 It's not useful to define symbolic names for every register bit in the
316 device. The name can only partially document the semantics and make
317 the driver longer and more difficult to read.
318 In general, only the important configuration values or bits changed
319 multiple times should be defined symbolically.
321 enum register_offsets {
322 PCIDeviceConfig=0x50040, GenCtrl=0x50070, IntrTimerCtrl=0x50074,
323 IntrClear=0x50080, IntrStatus=0x50084, IntrEnable=0x50088,
324 MIICtrl=0x52000, TxStationAddr=0x50120, EEPROMCtrl=0x51000,
325 GPIOCtrl=0x5008C, TxDescCtrl=0x50090,
326 TxRingPtr=0x50098, HiPriTxRingPtr=0x50094, /* Low and High priority. */
327 TxRingHiAddr=0x5009C, /* 64 bit address extension. */
328 TxProducerIdx=0x500A0, TxConsumerIdx=0x500A4,
330 CompletionHiAddr=0x500B4, TxCompletionAddr=0x500B8,
331 RxCompletionAddr=0x500BC, RxCompletionQ2Addr=0x500C0,
332 CompletionQConsumerIdx=0x500C4, RxDMACtrl=0x500D0,
333 RxDescQCtrl=0x500D4, RxDescQHiAddr=0x500DC, RxDescQAddr=0x500E0,
334 RxDescQIdx=0x500E8, RxDMAStatus=0x500F0, RxFilterMode=0x500F4,
335 TxMode=0x55000, VlanType=0x55064,
336 PerfFilterTable=0x56000, HashTable=0x56100,
337 TxGfpMem=0x58000, RxGfpMem=0x5a000,
341 * Bits in the interrupt status/mask registers.
342 * Warning: setting Intr[Ab]NormalSummary in the IntrEnable register
343 * enables all the interrupt sources that are or'ed into those status bits.
345 enum intr_status_bits {
346 IntrLinkChange=0xf0000000, IntrStatsMax=0x08000000,
347 IntrAbnormalSummary=0x02000000, IntrGeneralTimer=0x01000000,
348 IntrSoftware=0x800000, IntrRxComplQ1Low=0x400000,
349 IntrTxComplQLow=0x200000, IntrPCI=0x100000,
350 IntrDMAErr=0x080000, IntrTxDataLow=0x040000,
351 IntrRxComplQ2Low=0x020000, IntrRxDescQ1Low=0x010000,
352 IntrNormalSummary=0x8000, IntrTxDone=0x4000,
353 IntrTxDMADone=0x2000, IntrTxEmpty=0x1000,
354 IntrEarlyRxQ2=0x0800, IntrEarlyRxQ1=0x0400,
355 IntrRxQ2Done=0x0200, IntrRxQ1Done=0x0100,
356 IntrRxGFPDead=0x80, IntrRxDescQ2Low=0x40,
357 IntrNoTxCsum=0x20, IntrTxBadID=0x10,
358 IntrHiPriTxBadID=0x08, IntrRxGfp=0x04,
359 IntrTxGfp=0x02, IntrPCIPad=0x01,
361 IntrRxDone=IntrRxQ2Done | IntrRxQ1Done,
362 IntrRxEmpty=IntrRxDescQ1Low | IntrRxDescQ2Low,
363 IntrNormalMask=0xff00, IntrAbnormalMask=0x3ff00fe,
366 /* Bits in the RxFilterMode register. */
368 AcceptBroadcast=0x04, AcceptAllMulticast=0x02, AcceptAll=0x01,
369 AcceptMulticast=0x10, PerfectFilter=0x40, HashFilter=0x30,
370 PerfectFilterVlan=0x80, MinVLANPrio=0xE000, VlanMode=0x0200,
374 /* Bits in the TxMode register */
376 MiiSoftReset=0x8000, MIILoopback=0x4000,
377 TxFlowEnable=0x0800, RxFlowEnable=0x0400,
378 PadEnable=0x04, FullDuplex=0x02, HugeFrame=0x01,
381 /* Bits in the TxDescCtrl register. */
383 TxDescSpaceUnlim=0x00, TxDescSpace32=0x10, TxDescSpace64=0x20,
384 TxDescSpace128=0x30, TxDescSpace256=0x40,
385 TxDescType0=0x00, TxDescType1=0x01, TxDescType2=0x02,
386 TxDescType3=0x03, TxDescType4=0x04,
387 TxNoDMACompletion=0x08,
388 TxDescQAddr64bit=0x80, TxDescQAddr32bit=0,
389 TxHiPriFIFOThreshShift=24, TxPadLenShift=16,
390 TxDMABurstSizeShift=8,
393 /* Bits in the RxDescQCtrl register. */
395 RxBufferLenShift=16, RxMinDescrThreshShift=0,
396 RxPrefetchMode=0x8000, RxVariableQ=0x2000,
397 Rx2048QEntries=0x4000, Rx256QEntries=0,
398 RxDescAddr64bit=0x1000, RxDescAddr32bit=0,
399 RxDescQAddr64bit=0x0100, RxDescQAddr32bit=0,
400 RxDescSpace4=0x000, RxDescSpace8=0x100,
401 RxDescSpace16=0x200, RxDescSpace32=0x300,
402 RxDescSpace64=0x400, RxDescSpace128=0x500,
406 /* Bits in the RxDMACtrl register. */
407 enum rx_dmactrl_bits {
408 RxReportBadFrames=0x80000000, RxDMAShortFrames=0x40000000,
409 RxDMABadFrames=0x20000000, RxDMACrcErrorFrames=0x10000000,
410 RxDMAControlFrame=0x08000000, RxDMAPauseFrame=0x04000000,
411 RxChecksumIgnore=0, RxChecksumRejectTCPUDP=0x02000000,
412 RxChecksumRejectTCPOnly=0x01000000,
413 RxCompletionQ2Enable=0x800000,
414 RxDMAQ2Disable=0, RxDMAQ2FPOnly=0x100000,
415 RxDMAQ2SmallPkt=0x200000, RxDMAQ2HighPrio=0x300000,
416 RxDMAQ2NonIP=0x400000,
417 RxUseBackupQueue=0x080000, RxDMACRC=0x040000,
418 RxEarlyIntThreshShift=12, RxHighPrioThreshShift=8,
422 /* Bits in the RxCompletionAddr register */
424 RxComplQAddr64bit=0x80, RxComplQAddr32bit=0,
425 RxComplProducerWrEn=0x40,
426 RxComplType0=0x00, RxComplType1=0x10,
427 RxComplType2=0x20, RxComplType3=0x30,
428 RxComplThreshShift=0,
431 /* Bits in the TxCompletionAddr register */
433 TxComplQAddr64bit=0x80, TxComplQAddr32bit=0,
434 TxComplProducerWrEn=0x40,
435 TxComplIntrStatus=0x20,
436 CommonQueueMode=0x10,
437 TxComplThreshShift=0,
440 /* Bits in the GenCtrl register */
442 RxEnable=0x05, TxEnable=0x0a,
443 RxGFPEnable=0x10, TxGFPEnable=0x20,
446 /* Bits in the IntrTimerCtrl register */
447 enum intr_ctrl_bits {
448 Timer10X=0x800, EnableIntrMasking=0x60, SmallFrameBypass=0x100,
449 SmallFrame64=0, SmallFrame128=0x200, SmallFrame256=0x400, SmallFrame512=0x600,
450 IntrLatencyMask=0x1f,
453 /* The Rx and Tx buffer descriptors. */
454 struct starfire_rx_desc {
455 netdrv_addr_t rxaddr;
458 RxDescValid=1, RxDescEndRing=2,
461 /* Completion queue entry. */
462 struct short_rx_done_desc {
463 __le32 status; /* Low 16 bits is length. */
465 struct basic_rx_done_desc {
466 __le32 status; /* Low 16 bits is length. */
470 struct csum_rx_done_desc {
471 __le32 status; /* Low 16 bits is length. */
472 __le16 csum; /* Partial checksum */
475 struct full_rx_done_desc {
476 __le32 status; /* Low 16 bits is length. */
480 __le16 csum; /* partial checksum */
483 /* XXX: this is ugly and I'm not sure it's worth the trouble -Ion */
485 typedef struct full_rx_done_desc rx_done_desc;
486 #define RxComplType RxComplType3
487 #else /* not VLAN_SUPPORT */
488 typedef struct csum_rx_done_desc rx_done_desc;
489 #define RxComplType RxComplType2
490 #endif /* not VLAN_SUPPORT */
493 RxOK=0x20000000, RxFIFOErr=0x10000000, RxBufQ2=0x08000000,
496 /* Type 1 Tx descriptor. */
497 struct starfire_tx_desc_1 {
498 __le32 status; /* Upper bits are status, lower 16 length. */
502 /* Type 2 Tx descriptor. */
503 struct starfire_tx_desc_2 {
504 __le32 status; /* Upper bits are status, lower 16 length. */
510 typedef struct starfire_tx_desc_2 starfire_tx_desc;
511 #define TX_DESC_TYPE TxDescType2
512 #else /* not ADDR_64BITS */
513 typedef struct starfire_tx_desc_1 starfire_tx_desc;
514 #define TX_DESC_TYPE TxDescType1
515 #endif /* not ADDR_64BITS */
516 #define TX_DESC_SPACING TxDescSpaceUnlim
520 TxCRCEn=0x01000000, TxDescIntr=0x08000000,
521 TxRingWrap=0x04000000, TxCalTCP=0x02000000,
523 struct tx_done_desc {
524 __le32 status; /* timestamp, index. */
526 __le32 intrstatus; /* interrupt status */
530 struct rx_ring_info {
534 struct tx_ring_info {
537 unsigned int used_slots;
541 struct netdev_private {
542 /* Descriptor rings first for alignment. */
543 struct starfire_rx_desc *rx_ring;
544 starfire_tx_desc *tx_ring;
545 dma_addr_t rx_ring_dma;
546 dma_addr_t tx_ring_dma;
547 /* The addresses of rx/tx-in-place skbuffs. */
548 struct rx_ring_info rx_info[RX_RING_SIZE];
549 struct tx_ring_info tx_info[TX_RING_SIZE];
550 /* Pointers to completion queues (full pages). */
551 rx_done_desc *rx_done_q;
552 dma_addr_t rx_done_q_dma;
553 unsigned int rx_done;
554 struct tx_done_desc *tx_done_q;
555 dma_addr_t tx_done_q_dma;
556 unsigned int tx_done;
557 struct napi_struct napi;
558 struct net_device *dev;
559 struct net_device_stats stats;
560 struct pci_dev *pci_dev;
562 struct vlan_group *vlgrp;
565 dma_addr_t queue_mem_dma;
566 size_t queue_mem_size;
568 /* Frequently used values: keep some adjacent for cache effect. */
570 unsigned int cur_rx, dirty_rx; /* Producer/consumer ring indices */
571 unsigned int cur_tx, dirty_tx, reap_tx;
572 unsigned int rx_buf_sz; /* Based on MTU+slack. */
573 /* These values keep track of the transceiver/media in use. */
574 int speed100; /* Set if speed == 100MBit. */
578 /* MII transceiver section. */
579 struct mii_if_info mii_if; /* MII lib hooks/info */
580 int phy_cnt; /* MII device addresses. */
581 unsigned char phys[PHY_CNT]; /* MII device addresses. */
586 static int mdio_read(struct net_device *dev, int phy_id, int location);
587 static void mdio_write(struct net_device *dev, int phy_id, int location, int value);
588 static int netdev_open(struct net_device *dev);
589 static void check_duplex(struct net_device *dev);
590 static void tx_timeout(struct net_device *dev);
591 static void init_ring(struct net_device *dev);
592 static int start_tx(struct sk_buff *skb, struct net_device *dev);
593 static irqreturn_t intr_handler(int irq, void *dev_instance);
594 static void netdev_error(struct net_device *dev, int intr_status);
595 static int __netdev_rx(struct net_device *dev, int *quota);
596 static int netdev_poll(struct napi_struct *napi, int budget);
597 static void refill_rx_ring(struct net_device *dev);
598 static void netdev_error(struct net_device *dev, int intr_status);
599 static void set_rx_mode(struct net_device *dev);
600 static struct net_device_stats *get_stats(struct net_device *dev);
601 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
602 static int netdev_close(struct net_device *dev);
603 static void netdev_media_change(struct net_device *dev);
604 static const struct ethtool_ops ethtool_ops;
608 static void netdev_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
610 struct netdev_private *np = netdev_priv(dev);
612 spin_lock(&np->lock);
614 printk("%s: Setting vlgrp to %p\n", dev->name, grp);
617 spin_unlock(&np->lock);
620 static void netdev_vlan_rx_add_vid(struct net_device *dev, unsigned short vid)
622 struct netdev_private *np = netdev_priv(dev);
624 spin_lock(&np->lock);
626 printk("%s: Adding vlanid %d to vlan filter\n", dev->name, vid);
628 spin_unlock(&np->lock);
631 static void netdev_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
633 struct netdev_private *np = netdev_priv(dev);
635 spin_lock(&np->lock);
637 printk("%s: removing vlanid %d from vlan filter\n", dev->name, vid);
638 vlan_group_set_device(np->vlgrp, vid, NULL);
640 spin_unlock(&np->lock);
642 #endif /* VLAN_SUPPORT */
645 static int __devinit starfire_init_one(struct pci_dev *pdev,
646 const struct pci_device_id *ent)
648 struct netdev_private *np;
649 int i, irq, option, chip_idx = ent->driver_data;
650 struct net_device *dev;
651 static int card_idx = -1;
654 int drv_flags, io_size;
657 /* when built into the kernel, we only print version if device is found */
659 static int printed_version;
660 if (!printed_version++)
666 if (pci_enable_device (pdev))
669 ioaddr = pci_resource_start(pdev, 0);
670 io_size = pci_resource_len(pdev, 0);
671 if (!ioaddr || ((pci_resource_flags(pdev, 0) & IORESOURCE_MEM) == 0)) {
672 printk(KERN_ERR DRV_NAME " %d: no PCI MEM resources, aborting\n", card_idx);
676 dev = alloc_etherdev(sizeof(*np));
678 printk(KERN_ERR DRV_NAME " %d: cannot alloc etherdev, aborting\n", card_idx);
681 SET_NETDEV_DEV(dev, &pdev->dev);
685 if (pci_request_regions (pdev, DRV_NAME)) {
686 printk(KERN_ERR DRV_NAME " %d: cannot reserve PCI resources, aborting\n", card_idx);
687 goto err_out_free_netdev;
690 base = ioremap(ioaddr, io_size);
692 printk(KERN_ERR DRV_NAME " %d: cannot remap %#x @ %#lx, aborting\n",
693 card_idx, io_size, ioaddr);
694 goto err_out_free_res;
697 pci_set_master(pdev);
699 /* enable MWI -- it vastly improves Rx performance on sparc64 */
700 pci_try_set_mwi(pdev);
703 /* Starfire can do TCP/UDP checksumming */
705 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
706 #endif /* ZEROCOPY */
708 dev->features |= NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_FILTER;
709 dev->vlan_rx_register = netdev_vlan_rx_register;
710 dev->vlan_rx_add_vid = netdev_vlan_rx_add_vid;
711 dev->vlan_rx_kill_vid = netdev_vlan_rx_kill_vid;
712 #endif /* VLAN_RX_KILL_VID */
714 dev->features |= NETIF_F_HIGHDMA;
715 #endif /* ADDR_64BITS */
717 /* Serial EEPROM reads are hidden by the hardware. */
718 for (i = 0; i < 6; i++)
719 dev->dev_addr[i] = readb(base + EEPROMCtrl + 20 - i);
721 #if ! defined(final_version) /* Dump the EEPROM contents during development. */
723 for (i = 0; i < 0x20; i++)
725 (unsigned int)readb(base + EEPROMCtrl + i),
726 i % 16 != 15 ? " " : "\n");
729 /* Issue soft reset */
730 writel(MiiSoftReset, base + TxMode);
732 writel(0, base + TxMode);
734 /* Reset the chip to erase previous misconfiguration. */
735 writel(1, base + PCIDeviceConfig);
737 while (--boguscnt > 0) {
739 if ((readl(base + PCIDeviceConfig) & 1) == 0)
743 printk("%s: chipset reset never completed!\n", dev->name);
744 /* wait a little longer */
747 dev->base_addr = (unsigned long)base;
750 np = netdev_priv(dev);
753 spin_lock_init(&np->lock);
754 pci_set_drvdata(pdev, dev);
758 np->mii_if.dev = dev;
759 np->mii_if.mdio_read = mdio_read;
760 np->mii_if.mdio_write = mdio_write;
761 np->mii_if.phy_id_mask = 0x1f;
762 np->mii_if.reg_num_mask = 0x1f;
764 drv_flags = netdrv_tbl[chip_idx].drv_flags;
766 option = card_idx < MAX_UNITS ? options[card_idx] : 0;
768 option = dev->mem_start;
770 /* The lower four bits are the media type. */
772 np->mii_if.full_duplex = 1;
774 if (card_idx < MAX_UNITS && full_duplex[card_idx] > 0)
775 np->mii_if.full_duplex = 1;
777 if (np->mii_if.full_duplex)
778 np->mii_if.force_media = 1;
780 np->mii_if.force_media = 0;
783 /* timer resolution is 128 * 0.8us */
784 np->intr_timer_ctrl = (((intr_latency * 10) / 1024) & IntrLatencyMask) |
785 Timer10X | EnableIntrMasking;
787 if (small_frames > 0) {
788 np->intr_timer_ctrl |= SmallFrameBypass;
789 switch (small_frames) {
791 np->intr_timer_ctrl |= SmallFrame64;
794 np->intr_timer_ctrl |= SmallFrame128;
797 np->intr_timer_ctrl |= SmallFrame256;
800 np->intr_timer_ctrl |= SmallFrame512;
801 if (small_frames > 512)
802 printk("Adjusting small_frames down to 512\n");
807 /* The chip-specific entries in the device structure. */
808 dev->open = &netdev_open;
809 dev->hard_start_xmit = &start_tx;
810 dev->tx_timeout = tx_timeout;
811 dev->watchdog_timeo = TX_TIMEOUT;
812 netif_napi_add(dev, &np->napi, netdev_poll, max_interrupt_work);
813 dev->stop = &netdev_close;
814 dev->get_stats = &get_stats;
815 dev->set_multicast_list = &set_rx_mode;
816 dev->do_ioctl = &netdev_ioctl;
817 SET_ETHTOOL_OPS(dev, ðtool_ops);
822 if (register_netdev(dev))
823 goto err_out_cleardev;
825 printk(KERN_INFO "%s: %s at %p, %pM, IRQ %d.\n",
826 dev->name, netdrv_tbl[chip_idx].name, base,
829 if (drv_flags & CanHaveMII) {
830 int phy, phy_idx = 0;
832 for (phy = 0; phy < 32 && phy_idx < PHY_CNT; phy++) {
833 mdio_write(dev, phy, MII_BMCR, BMCR_RESET);
836 while (--boguscnt > 0)
837 if ((mdio_read(dev, phy, MII_BMCR) & BMCR_RESET) == 0)
840 printk("%s: PHY#%d reset never completed!\n", dev->name, phy);
843 mii_status = mdio_read(dev, phy, MII_BMSR);
844 if (mii_status != 0) {
845 np->phys[phy_idx++] = phy;
846 np->mii_if.advertising = mdio_read(dev, phy, MII_ADVERTISE);
847 printk(KERN_INFO "%s: MII PHY found at address %d, status "
848 "%#4.4x advertising %#4.4x.\n",
849 dev->name, phy, mii_status, np->mii_if.advertising);
850 /* there can be only one PHY on-board */
854 np->phy_cnt = phy_idx;
856 np->mii_if.phy_id = np->phys[0];
858 memset(&np->mii_if, 0, sizeof(np->mii_if));
861 printk(KERN_INFO "%s: scatter-gather and hardware TCP cksumming %s.\n",
862 dev->name, enable_hw_cksum ? "enabled" : "disabled");
866 pci_set_drvdata(pdev, NULL);
869 pci_release_regions (pdev);
876 /* Read the MII Management Data I/O (MDIO) interfaces. */
877 static int mdio_read(struct net_device *dev, int phy_id, int location)
879 struct netdev_private *np = netdev_priv(dev);
880 void __iomem *mdio_addr = np->base + MIICtrl + (phy_id<<7) + (location<<2);
881 int result, boguscnt=1000;
882 /* ??? Should we add a busy-wait here? */
884 result = readl(mdio_addr);
885 while ((result & 0xC0000000) != 0x80000000 && --boguscnt > 0);
888 if ((result & 0xffff) == 0xffff)
890 return result & 0xffff;
894 static void mdio_write(struct net_device *dev, int phy_id, int location, int value)
896 struct netdev_private *np = netdev_priv(dev);
897 void __iomem *mdio_addr = np->base + MIICtrl + (phy_id<<7) + (location<<2);
898 writel(value, mdio_addr);
899 /* The busy-wait will occur before a read. */
903 static int netdev_open(struct net_device *dev)
905 struct netdev_private *np = netdev_priv(dev);
906 void __iomem *ioaddr = np->base;
908 size_t tx_done_q_size, rx_done_q_size, tx_ring_size, rx_ring_size;
910 /* Do we ever need to reset the chip??? */
912 retval = request_irq(dev->irq, &intr_handler, IRQF_SHARED, dev->name, dev);
916 /* Disable the Rx and Tx, and reset the chip. */
917 writel(0, ioaddr + GenCtrl);
918 writel(1, ioaddr + PCIDeviceConfig);
920 printk(KERN_DEBUG "%s: netdev_open() irq %d.\n",
921 dev->name, dev->irq);
923 /* Allocate the various queues. */
924 if (!np->queue_mem) {
925 tx_done_q_size = ((sizeof(struct tx_done_desc) * DONE_Q_SIZE + QUEUE_ALIGN - 1) / QUEUE_ALIGN) * QUEUE_ALIGN;
926 rx_done_q_size = ((sizeof(rx_done_desc) * DONE_Q_SIZE + QUEUE_ALIGN - 1) / QUEUE_ALIGN) * QUEUE_ALIGN;
927 tx_ring_size = ((sizeof(starfire_tx_desc) * TX_RING_SIZE + QUEUE_ALIGN - 1) / QUEUE_ALIGN) * QUEUE_ALIGN;
928 rx_ring_size = sizeof(struct starfire_rx_desc) * RX_RING_SIZE;
929 np->queue_mem_size = tx_done_q_size + rx_done_q_size + tx_ring_size + rx_ring_size;
930 np->queue_mem = pci_alloc_consistent(np->pci_dev, np->queue_mem_size, &np->queue_mem_dma);
931 if (np->queue_mem == NULL) {
932 free_irq(dev->irq, dev);
936 np->tx_done_q = np->queue_mem;
937 np->tx_done_q_dma = np->queue_mem_dma;
938 np->rx_done_q = (void *) np->tx_done_q + tx_done_q_size;
939 np->rx_done_q_dma = np->tx_done_q_dma + tx_done_q_size;
940 np->tx_ring = (void *) np->rx_done_q + rx_done_q_size;
941 np->tx_ring_dma = np->rx_done_q_dma + rx_done_q_size;
942 np->rx_ring = (void *) np->tx_ring + tx_ring_size;
943 np->rx_ring_dma = np->tx_ring_dma + tx_ring_size;
946 /* Start with no carrier, it gets adjusted later */
947 netif_carrier_off(dev);
949 /* Set the size of the Rx buffers. */
950 writel((np->rx_buf_sz << RxBufferLenShift) |
951 (0 << RxMinDescrThreshShift) |
952 RxPrefetchMode | RxVariableQ |
954 RX_DESC_Q_ADDR_SIZE | RX_DESC_ADDR_SIZE |
956 ioaddr + RxDescQCtrl);
958 /* Set up the Rx DMA controller. */
959 writel(RxChecksumIgnore |
960 (0 << RxEarlyIntThreshShift) |
961 (6 << RxHighPrioThreshShift) |
962 ((DMA_BURST_SIZE / 32) << RxBurstSizeShift),
965 /* Set Tx descriptor */
966 writel((2 << TxHiPriFIFOThreshShift) |
967 (0 << TxPadLenShift) |
968 ((DMA_BURST_SIZE / 32) << TxDMABurstSizeShift) |
969 TX_DESC_Q_ADDR_SIZE |
970 TX_DESC_SPACING | TX_DESC_TYPE,
971 ioaddr + TxDescCtrl);
973 writel( (np->queue_mem_dma >> 16) >> 16, ioaddr + RxDescQHiAddr);
974 writel( (np->queue_mem_dma >> 16) >> 16, ioaddr + TxRingHiAddr);
975 writel( (np->queue_mem_dma >> 16) >> 16, ioaddr + CompletionHiAddr);
976 writel(np->rx_ring_dma, ioaddr + RxDescQAddr);
977 writel(np->tx_ring_dma, ioaddr + TxRingPtr);
979 writel(np->tx_done_q_dma, ioaddr + TxCompletionAddr);
980 writel(np->rx_done_q_dma |
982 (0 << RxComplThreshShift),
983 ioaddr + RxCompletionAddr);
986 printk(KERN_DEBUG "%s: Filling in the station address.\n", dev->name);
988 /* Fill both the Tx SA register and the Rx perfect filter. */
989 for (i = 0; i < 6; i++)
990 writeb(dev->dev_addr[i], ioaddr + TxStationAddr + 5 - i);
991 /* The first entry is special because it bypasses the VLAN filter.
993 writew(0, ioaddr + PerfFilterTable);
994 writew(0, ioaddr + PerfFilterTable + 4);
995 writew(0, ioaddr + PerfFilterTable + 8);
996 for (i = 1; i < 16; i++) {
997 __be16 *eaddrs = (__be16 *)dev->dev_addr;
998 void __iomem *setup_frm = ioaddr + PerfFilterTable + i * 16;
999 writew(be16_to_cpu(eaddrs[2]), setup_frm); setup_frm += 4;
1000 writew(be16_to_cpu(eaddrs[1]), setup_frm); setup_frm += 4;
1001 writew(be16_to_cpu(eaddrs[0]), setup_frm); setup_frm += 8;
1004 /* Initialize other registers. */
1005 /* Configure the PCI bus bursts and FIFO thresholds. */
1006 np->tx_mode = TxFlowEnable|RxFlowEnable|PadEnable; /* modified when link is up. */
1007 writel(MiiSoftReset | np->tx_mode, ioaddr + TxMode);
1009 writel(np->tx_mode, ioaddr + TxMode);
1010 np->tx_threshold = 4;
1011 writel(np->tx_threshold, ioaddr + TxThreshold);
1013 writel(np->intr_timer_ctrl, ioaddr + IntrTimerCtrl);
1015 napi_enable(&np->napi);
1017 netif_start_queue(dev);
1020 printk(KERN_DEBUG "%s: Setting the Rx and Tx modes.\n", dev->name);
1023 np->mii_if.advertising = mdio_read(dev, np->phys[0], MII_ADVERTISE);
1026 /* Enable GPIO interrupts on link change */
1027 writel(0x0f00ff00, ioaddr + GPIOCtrl);
1029 /* Set the interrupt mask */
1030 writel(IntrRxDone | IntrRxEmpty | IntrDMAErr |
1031 IntrTxDMADone | IntrStatsMax | IntrLinkChange |
1032 IntrRxGFPDead | IntrNoTxCsum | IntrTxBadID,
1033 ioaddr + IntrEnable);
1034 /* Enable PCI interrupts. */
1035 writel(0x00800000 | readl(ioaddr + PCIDeviceConfig),
1036 ioaddr + PCIDeviceConfig);
1039 /* Set VLAN type to 802.1q */
1040 writel(ETH_P_8021Q, ioaddr + VlanType);
1041 #endif /* VLAN_SUPPORT */
1043 /* Load Rx/Tx firmware into the frame processors */
1044 for (i = 0; i < FIRMWARE_RX_SIZE * 2; i++)
1045 writel(firmware_rx[i], ioaddr + RxGfpMem + i * 4);
1046 for (i = 0; i < FIRMWARE_TX_SIZE * 2; i++)
1047 writel(firmware_tx[i], ioaddr + TxGfpMem + i * 4);
1048 if (enable_hw_cksum)
1049 /* Enable the Rx and Tx units, and the Rx/Tx frame processors. */
1050 writel(TxEnable|TxGFPEnable|RxEnable|RxGFPEnable, ioaddr + GenCtrl);
1052 /* Enable the Rx and Tx units only. */
1053 writel(TxEnable|RxEnable, ioaddr + GenCtrl);
1056 printk(KERN_DEBUG "%s: Done netdev_open().\n",
1063 static void check_duplex(struct net_device *dev)
1065 struct netdev_private *np = netdev_priv(dev);
1067 int silly_count = 1000;
1069 mdio_write(dev, np->phys[0], MII_ADVERTISE, np->mii_if.advertising);
1070 mdio_write(dev, np->phys[0], MII_BMCR, BMCR_RESET);
1072 while (--silly_count && mdio_read(dev, np->phys[0], MII_BMCR) & BMCR_RESET)
1075 printk("%s: MII reset failed!\n", dev->name);
1079 reg0 = mdio_read(dev, np->phys[0], MII_BMCR);
1081 if (!np->mii_if.force_media) {
1082 reg0 |= BMCR_ANENABLE | BMCR_ANRESTART;
1084 reg0 &= ~(BMCR_ANENABLE | BMCR_ANRESTART);
1086 reg0 |= BMCR_SPEED100;
1087 if (np->mii_if.full_duplex)
1088 reg0 |= BMCR_FULLDPLX;
1089 printk(KERN_DEBUG "%s: Link forced to %sMbit %s-duplex\n",
1091 np->speed100 ? "100" : "10",
1092 np->mii_if.full_duplex ? "full" : "half");
1094 mdio_write(dev, np->phys[0], MII_BMCR, reg0);
1098 static void tx_timeout(struct net_device *dev)
1100 struct netdev_private *np = netdev_priv(dev);
1101 void __iomem *ioaddr = np->base;
1104 printk(KERN_WARNING "%s: Transmit timed out, status %#8.8x, "
1105 "resetting...\n", dev->name, (int) readl(ioaddr + IntrStatus));
1107 /* Perhaps we should reinitialize the hardware here. */
1110 * Stop and restart the interface.
1111 * Cheat and increase the debug level temporarily.
1119 /* Trigger an immediate transmit demand. */
1121 dev->trans_start = jiffies;
1122 np->stats.tx_errors++;
1123 netif_wake_queue(dev);
1127 /* Initialize the Rx and Tx rings, along with various 'dev' bits. */
1128 static void init_ring(struct net_device *dev)
1130 struct netdev_private *np = netdev_priv(dev);
1133 np->cur_rx = np->cur_tx = np->reap_tx = 0;
1134 np->dirty_rx = np->dirty_tx = np->rx_done = np->tx_done = 0;
1136 np->rx_buf_sz = (dev->mtu <= 1500 ? PKT_BUF_SZ : dev->mtu + 32);
1138 /* Fill in the Rx buffers. Handle allocation failure gracefully. */
1139 for (i = 0; i < RX_RING_SIZE; i++) {
1140 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz);
1141 np->rx_info[i].skb = skb;
1144 np->rx_info[i].mapping = pci_map_single(np->pci_dev, skb->data, np->rx_buf_sz, PCI_DMA_FROMDEVICE);
1145 skb->dev = dev; /* Mark as being used by this device. */
1146 /* Grrr, we cannot offset to correctly align the IP header. */
1147 np->rx_ring[i].rxaddr = cpu_to_dma(np->rx_info[i].mapping | RxDescValid);
1149 writew(i - 1, np->base + RxDescQIdx);
1150 np->dirty_rx = (unsigned int)(i - RX_RING_SIZE);
1152 /* Clear the remainder of the Rx buffer ring. */
1153 for ( ; i < RX_RING_SIZE; i++) {
1154 np->rx_ring[i].rxaddr = 0;
1155 np->rx_info[i].skb = NULL;
1156 np->rx_info[i].mapping = 0;
1158 /* Mark the last entry as wrapping the ring. */
1159 np->rx_ring[RX_RING_SIZE - 1].rxaddr |= cpu_to_dma(RxDescEndRing);
1161 /* Clear the completion rings. */
1162 for (i = 0; i < DONE_Q_SIZE; i++) {
1163 np->rx_done_q[i].status = 0;
1164 np->tx_done_q[i].status = 0;
1167 for (i = 0; i < TX_RING_SIZE; i++)
1168 memset(&np->tx_info[i], 0, sizeof(np->tx_info[i]));
1174 static int start_tx(struct sk_buff *skb, struct net_device *dev)
1176 struct netdev_private *np = netdev_priv(dev);
1182 * be cautious here, wrapping the queue has weird semantics
1183 * and we may not have enough slots even when it seems we do.
1185 if ((np->cur_tx - np->dirty_tx) + skb_num_frags(skb) * 2 > TX_RING_SIZE) {
1186 netif_stop_queue(dev);
1190 #if defined(ZEROCOPY) && defined(HAS_BROKEN_FIRMWARE)
1191 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1192 if (skb_padto(skb, (skb->len + PADDING_MASK) & ~PADDING_MASK))
1193 return NETDEV_TX_OK;
1195 #endif /* ZEROCOPY && HAS_BROKEN_FIRMWARE */
1197 entry = np->cur_tx % TX_RING_SIZE;
1198 for (i = 0; i < skb_num_frags(skb); i++) {
1203 np->tx_info[entry].skb = skb;
1205 if (entry >= TX_RING_SIZE - skb_num_frags(skb)) {
1206 status |= TxRingWrap;
1210 status |= TxDescIntr;
1213 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1215 np->stats.tx_compressed++;
1217 status |= skb_first_frag_len(skb) | (skb_num_frags(skb) << 16);
1219 np->tx_info[entry].mapping =
1220 pci_map_single(np->pci_dev, skb->data, skb_first_frag_len(skb), PCI_DMA_TODEVICE);
1222 skb_frag_t *this_frag = &skb_shinfo(skb)->frags[i - 1];
1223 status |= this_frag->size;
1224 np->tx_info[entry].mapping =
1225 pci_map_single(np->pci_dev, page_address(this_frag->page) + this_frag->page_offset, this_frag->size, PCI_DMA_TODEVICE);
1228 np->tx_ring[entry].addr = cpu_to_dma(np->tx_info[entry].mapping);
1229 np->tx_ring[entry].status = cpu_to_le32(status);
1231 printk(KERN_DEBUG "%s: Tx #%d/#%d slot %d status %#8.8x.\n",
1232 dev->name, np->cur_tx, np->dirty_tx,
1235 np->tx_info[entry].used_slots = TX_RING_SIZE - entry;
1236 np->cur_tx += np->tx_info[entry].used_slots;
1239 np->tx_info[entry].used_slots = 1;
1240 np->cur_tx += np->tx_info[entry].used_slots;
1243 /* scavenge the tx descriptors twice per TX_RING_SIZE */
1244 if (np->cur_tx % (TX_RING_SIZE / 2) == 0)
1248 /* Non-x86: explicitly flush descriptor cache lines here. */
1249 /* Ensure all descriptors are written back before the transmit is
1253 /* Update the producer index. */
1254 writel(entry * (sizeof(starfire_tx_desc) / 8), np->base + TxProducerIdx);
1256 /* 4 is arbitrary, but should be ok */
1257 if ((np->cur_tx - np->dirty_tx) + 4 > TX_RING_SIZE)
1258 netif_stop_queue(dev);
1260 dev->trans_start = jiffies;
1266 /* The interrupt handler does all of the Rx thread work and cleans up
1267 after the Tx thread. */
1268 static irqreturn_t intr_handler(int irq, void *dev_instance)
1270 struct net_device *dev = dev_instance;
1271 struct netdev_private *np = netdev_priv(dev);
1272 void __iomem *ioaddr = np->base;
1273 int boguscnt = max_interrupt_work;
1279 u32 intr_status = readl(ioaddr + IntrClear);
1282 printk(KERN_DEBUG "%s: Interrupt status %#8.8x.\n",
1283 dev->name, intr_status);
1285 if (intr_status == 0 || intr_status == (u32) -1)
1290 if (intr_status & (IntrRxDone | IntrRxEmpty)) {
1293 if (likely(netif_rx_schedule_prep(dev, &np->napi))) {
1294 __netif_rx_schedule(dev, &np->napi);
1295 enable = readl(ioaddr + IntrEnable);
1296 enable &= ~(IntrRxDone | IntrRxEmpty);
1297 writel(enable, ioaddr + IntrEnable);
1298 /* flush PCI posting buffers */
1299 readl(ioaddr + IntrEnable);
1301 /* Paranoia check */
1302 enable = readl(ioaddr + IntrEnable);
1303 if (enable & (IntrRxDone | IntrRxEmpty)) {
1305 "%s: interrupt while in poll!\n",
1307 enable &= ~(IntrRxDone | IntrRxEmpty);
1308 writel(enable, ioaddr + IntrEnable);
1313 /* Scavenge the skbuff list based on the Tx-done queue.
1314 There are redundant checks here that may be cleaned up
1315 after the driver has proven to be reliable. */
1316 consumer = readl(ioaddr + TxConsumerIdx);
1318 printk(KERN_DEBUG "%s: Tx Consumer index is %d.\n",
1319 dev->name, consumer);
1321 while ((tx_status = le32_to_cpu(np->tx_done_q[np->tx_done].status)) != 0) {
1323 printk(KERN_DEBUG "%s: Tx completion #%d entry %d is %#8.8x.\n",
1324 dev->name, np->dirty_tx, np->tx_done, tx_status);
1325 if ((tx_status & 0xe0000000) == 0xa0000000) {
1326 np->stats.tx_packets++;
1327 } else if ((tx_status & 0xe0000000) == 0x80000000) {
1328 u16 entry = (tx_status & 0x7fff) / sizeof(starfire_tx_desc);
1329 struct sk_buff *skb = np->tx_info[entry].skb;
1330 np->tx_info[entry].skb = NULL;
1331 pci_unmap_single(np->pci_dev,
1332 np->tx_info[entry].mapping,
1333 skb_first_frag_len(skb),
1335 np->tx_info[entry].mapping = 0;
1336 np->dirty_tx += np->tx_info[entry].used_slots;
1337 entry = (entry + np->tx_info[entry].used_slots) % TX_RING_SIZE;
1340 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1341 pci_unmap_single(np->pci_dev,
1342 np->tx_info[entry].mapping,
1343 skb_shinfo(skb)->frags[i].size,
1350 dev_kfree_skb_irq(skb);
1352 np->tx_done_q[np->tx_done].status = 0;
1353 np->tx_done = (np->tx_done + 1) % DONE_Q_SIZE;
1355 writew(np->tx_done, ioaddr + CompletionQConsumerIdx + 2);
1357 if (netif_queue_stopped(dev) &&
1358 (np->cur_tx - np->dirty_tx + 4 < TX_RING_SIZE)) {
1359 /* The ring is no longer full, wake the queue. */
1360 netif_wake_queue(dev);
1363 /* Stats overflow */
1364 if (intr_status & IntrStatsMax)
1367 /* Media change interrupt. */
1368 if (intr_status & IntrLinkChange)
1369 netdev_media_change(dev);
1371 /* Abnormal error summary/uncommon events handlers. */
1372 if (intr_status & IntrAbnormalSummary)
1373 netdev_error(dev, intr_status);
1375 if (--boguscnt < 0) {
1377 printk(KERN_WARNING "%s: Too much work at interrupt, "
1379 dev->name, intr_status);
1385 printk(KERN_DEBUG "%s: exiting interrupt, status=%#8.8x.\n",
1386 dev->name, (int) readl(ioaddr + IntrStatus));
1387 return IRQ_RETVAL(handled);
1392 * This routine is logically part of the interrupt/poll handler, but separated
1393 * for clarity and better register allocation.
1395 static int __netdev_rx(struct net_device *dev, int *quota)
1397 struct netdev_private *np = netdev_priv(dev);
1401 /* If EOP is set on the next entry, it's a new packet. Send it up. */
1402 while ((desc_status = le32_to_cpu(np->rx_done_q[np->rx_done].status)) != 0) {
1403 struct sk_buff *skb;
1406 rx_done_desc *desc = &np->rx_done_q[np->rx_done];
1409 printk(KERN_DEBUG " netdev_rx() status of %d was %#8.8x.\n", np->rx_done, desc_status);
1410 if (!(desc_status & RxOK)) {
1411 /* There was an error. */
1413 printk(KERN_DEBUG " netdev_rx() Rx error was %#8.8x.\n", desc_status);
1414 np->stats.rx_errors++;
1415 if (desc_status & RxFIFOErr)
1416 np->stats.rx_fifo_errors++;
1420 if (*quota <= 0) { /* out of rx quota */
1426 pkt_len = desc_status; /* Implicitly Truncate */
1427 entry = (desc_status >> 16) & 0x7ff;
1430 printk(KERN_DEBUG " netdev_rx() normal Rx pkt length %d, quota %d.\n", pkt_len, *quota);
1431 /* Check if the packet is long enough to accept without copying
1432 to a minimally-sized skbuff. */
1433 if (pkt_len < rx_copybreak
1434 && (skb = dev_alloc_skb(pkt_len + 2)) != NULL) {
1435 skb_reserve(skb, 2); /* 16 byte align the IP header */
1436 pci_dma_sync_single_for_cpu(np->pci_dev,
1437 np->rx_info[entry].mapping,
1438 pkt_len, PCI_DMA_FROMDEVICE);
1439 skb_copy_to_linear_data(skb, np->rx_info[entry].skb->data, pkt_len);
1440 pci_dma_sync_single_for_device(np->pci_dev,
1441 np->rx_info[entry].mapping,
1442 pkt_len, PCI_DMA_FROMDEVICE);
1443 skb_put(skb, pkt_len);
1445 pci_unmap_single(np->pci_dev, np->rx_info[entry].mapping, np->rx_buf_sz, PCI_DMA_FROMDEVICE);
1446 skb = np->rx_info[entry].skb;
1447 skb_put(skb, pkt_len);
1448 np->rx_info[entry].skb = NULL;
1449 np->rx_info[entry].mapping = 0;
1451 #ifndef final_version /* Remove after testing. */
1452 /* You will want this info for the initial debug. */
1454 printk(KERN_DEBUG " Rx data %pM %pM %2.2x%2.2x.\n",
1455 skb->data, skb->data + 6,
1456 skb->data[12], skb->data[13]);
1460 skb->protocol = eth_type_trans(skb, dev);
1463 printk(KERN_DEBUG " netdev_rx() status2 of %d was %#4.4x.\n", np->rx_done, le16_to_cpu(desc->status2));
1465 if (le16_to_cpu(desc->status2) & 0x0100) {
1466 skb->ip_summed = CHECKSUM_UNNECESSARY;
1467 np->stats.rx_compressed++;
1470 * This feature doesn't seem to be working, at least
1471 * with the two firmware versions I have. If the GFP sees
1472 * an IP fragment, it either ignores it completely, or reports
1473 * "bad checksum" on it.
1475 * Maybe I missed something -- corrections are welcome.
1476 * Until then, the printk stays. :-) -Ion
1478 else if (le16_to_cpu(desc->status2) & 0x0040) {
1479 skb->ip_summed = CHECKSUM_COMPLETE;
1480 skb->csum = le16_to_cpu(desc->csum);
1481 printk(KERN_DEBUG "%s: checksum_hw, status2 = %#x\n", dev->name, le16_to_cpu(desc->status2));
1484 if (np->vlgrp && le16_to_cpu(desc->status2) & 0x0200) {
1485 u16 vlid = le16_to_cpu(desc->vlanid);
1488 printk(KERN_DEBUG " netdev_rx() vlanid = %d\n",
1492 * vlan_hwaccel_rx expects a packet with the VLAN tag
1495 vlan_hwaccel_rx(skb, np->vlgrp, vlid);
1497 #endif /* VLAN_SUPPORT */
1498 netif_receive_skb(skb);
1499 dev->last_rx = jiffies;
1500 np->stats.rx_packets++;
1505 np->rx_done = (np->rx_done + 1) % DONE_Q_SIZE;
1507 writew(np->rx_done, np->base + CompletionQConsumerIdx);
1510 refill_rx_ring(dev);
1512 printk(KERN_DEBUG " exiting netdev_rx(): %d, status of %d was %#8.8x.\n",
1513 retcode, np->rx_done, desc_status);
1517 static int netdev_poll(struct napi_struct *napi, int budget)
1519 struct netdev_private *np = container_of(napi, struct netdev_private, napi);
1520 struct net_device *dev = np->dev;
1522 void __iomem *ioaddr = np->base;
1526 writel(IntrRxDone | IntrRxEmpty, ioaddr + IntrClear);
1528 if (__netdev_rx(dev, "a))
1531 intr_status = readl(ioaddr + IntrStatus);
1532 } while (intr_status & (IntrRxDone | IntrRxEmpty));
1534 netif_rx_complete(dev, napi);
1535 intr_status = readl(ioaddr + IntrEnable);
1536 intr_status |= IntrRxDone | IntrRxEmpty;
1537 writel(intr_status, ioaddr + IntrEnable);
1541 printk(KERN_DEBUG " exiting netdev_poll(): %d.\n",
1544 /* Restart Rx engine if stopped. */
1545 return budget - quota;
1548 static void refill_rx_ring(struct net_device *dev)
1550 struct netdev_private *np = netdev_priv(dev);
1551 struct sk_buff *skb;
1554 /* Refill the Rx ring buffers. */
1555 for (; np->cur_rx - np->dirty_rx > 0; np->dirty_rx++) {
1556 entry = np->dirty_rx % RX_RING_SIZE;
1557 if (np->rx_info[entry].skb == NULL) {
1558 skb = dev_alloc_skb(np->rx_buf_sz);
1559 np->rx_info[entry].skb = skb;
1561 break; /* Better luck next round. */
1562 np->rx_info[entry].mapping =
1563 pci_map_single(np->pci_dev, skb->data, np->rx_buf_sz, PCI_DMA_FROMDEVICE);
1564 skb->dev = dev; /* Mark as being used by this device. */
1565 np->rx_ring[entry].rxaddr =
1566 cpu_to_dma(np->rx_info[entry].mapping | RxDescValid);
1568 if (entry == RX_RING_SIZE - 1)
1569 np->rx_ring[entry].rxaddr |= cpu_to_dma(RxDescEndRing);
1572 writew(entry, np->base + RxDescQIdx);
1576 static void netdev_media_change(struct net_device *dev)
1578 struct netdev_private *np = netdev_priv(dev);
1579 void __iomem *ioaddr = np->base;
1580 u16 reg0, reg1, reg4, reg5;
1582 u32 new_intr_timer_ctrl;
1584 /* reset status first */
1585 mdio_read(dev, np->phys[0], MII_BMCR);
1586 mdio_read(dev, np->phys[0], MII_BMSR);
1588 reg0 = mdio_read(dev, np->phys[0], MII_BMCR);
1589 reg1 = mdio_read(dev, np->phys[0], MII_BMSR);
1591 if (reg1 & BMSR_LSTATUS) {
1593 if (reg0 & BMCR_ANENABLE) {
1594 /* autonegotiation is enabled */
1595 reg4 = mdio_read(dev, np->phys[0], MII_ADVERTISE);
1596 reg5 = mdio_read(dev, np->phys[0], MII_LPA);
1597 if (reg4 & ADVERTISE_100FULL && reg5 & LPA_100FULL) {
1599 np->mii_if.full_duplex = 1;
1600 } else if (reg4 & ADVERTISE_100HALF && reg5 & LPA_100HALF) {
1602 np->mii_if.full_duplex = 0;
1603 } else if (reg4 & ADVERTISE_10FULL && reg5 & LPA_10FULL) {
1605 np->mii_if.full_duplex = 1;
1608 np->mii_if.full_duplex = 0;
1611 /* autonegotiation is disabled */
1612 if (reg0 & BMCR_SPEED100)
1616 if (reg0 & BMCR_FULLDPLX)
1617 np->mii_if.full_duplex = 1;
1619 np->mii_if.full_duplex = 0;
1621 netif_carrier_on(dev);
1622 printk(KERN_DEBUG "%s: Link is up, running at %sMbit %s-duplex\n",
1624 np->speed100 ? "100" : "10",
1625 np->mii_if.full_duplex ? "full" : "half");
1627 new_tx_mode = np->tx_mode & ~FullDuplex; /* duplex setting */
1628 if (np->mii_if.full_duplex)
1629 new_tx_mode |= FullDuplex;
1630 if (np->tx_mode != new_tx_mode) {
1631 np->tx_mode = new_tx_mode;
1632 writel(np->tx_mode | MiiSoftReset, ioaddr + TxMode);
1634 writel(np->tx_mode, ioaddr + TxMode);
1637 new_intr_timer_ctrl = np->intr_timer_ctrl & ~Timer10X;
1639 new_intr_timer_ctrl |= Timer10X;
1640 if (np->intr_timer_ctrl != new_intr_timer_ctrl) {
1641 np->intr_timer_ctrl = new_intr_timer_ctrl;
1642 writel(new_intr_timer_ctrl, ioaddr + IntrTimerCtrl);
1645 netif_carrier_off(dev);
1646 printk(KERN_DEBUG "%s: Link is down\n", dev->name);
1651 static void netdev_error(struct net_device *dev, int intr_status)
1653 struct netdev_private *np = netdev_priv(dev);
1655 /* Came close to underrunning the Tx FIFO, increase threshold. */
1656 if (intr_status & IntrTxDataLow) {
1657 if (np->tx_threshold <= PKT_BUF_SZ / 16) {
1658 writel(++np->tx_threshold, np->base + TxThreshold);
1659 printk(KERN_NOTICE "%s: PCI bus congestion, increasing Tx FIFO threshold to %d bytes\n",
1660 dev->name, np->tx_threshold * 16);
1662 printk(KERN_WARNING "%s: PCI Tx underflow -- adapter is probably malfunctioning\n", dev->name);
1664 if (intr_status & IntrRxGFPDead) {
1665 np->stats.rx_fifo_errors++;
1666 np->stats.rx_errors++;
1668 if (intr_status & (IntrNoTxCsum | IntrDMAErr)) {
1669 np->stats.tx_fifo_errors++;
1670 np->stats.tx_errors++;
1672 if ((intr_status & ~(IntrNormalMask | IntrAbnormalSummary | IntrLinkChange | IntrStatsMax | IntrTxDataLow | IntrRxGFPDead | IntrNoTxCsum | IntrPCIPad)) && debug)
1673 printk(KERN_ERR "%s: Something Wicked happened! %#8.8x.\n",
1674 dev->name, intr_status);
1678 static struct net_device_stats *get_stats(struct net_device *dev)
1680 struct netdev_private *np = netdev_priv(dev);
1681 void __iomem *ioaddr = np->base;
1683 /* This adapter architecture needs no SMP locks. */
1684 np->stats.tx_bytes = readl(ioaddr + 0x57010);
1685 np->stats.rx_bytes = readl(ioaddr + 0x57044);
1686 np->stats.tx_packets = readl(ioaddr + 0x57000);
1687 np->stats.tx_aborted_errors =
1688 readl(ioaddr + 0x57024) + readl(ioaddr + 0x57028);
1689 np->stats.tx_window_errors = readl(ioaddr + 0x57018);
1690 np->stats.collisions =
1691 readl(ioaddr + 0x57004) + readl(ioaddr + 0x57008);
1693 /* The chip only need report frame silently dropped. */
1694 np->stats.rx_dropped += readw(ioaddr + RxDMAStatus);
1695 writew(0, ioaddr + RxDMAStatus);
1696 np->stats.rx_crc_errors = readl(ioaddr + 0x5703C);
1697 np->stats.rx_frame_errors = readl(ioaddr + 0x57040);
1698 np->stats.rx_length_errors = readl(ioaddr + 0x57058);
1699 np->stats.rx_missed_errors = readl(ioaddr + 0x5707C);
1705 static void set_rx_mode(struct net_device *dev)
1707 struct netdev_private *np = netdev_priv(dev);
1708 void __iomem *ioaddr = np->base;
1709 u32 rx_mode = MinVLANPrio;
1710 struct dev_mc_list *mclist;
1714 rx_mode |= VlanMode;
1717 void __iomem *filter_addr = ioaddr + HashTable + 8;
1718 for (i = 0; i < VLAN_VID_MASK; i++) {
1719 if (vlan_group_get_device(np->vlgrp, i)) {
1720 if (vlan_count >= 32)
1722 writew(i, filter_addr);
1727 if (i == VLAN_VID_MASK) {
1728 rx_mode |= PerfectFilterVlan;
1729 while (vlan_count < 32) {
1730 writew(0, filter_addr);
1736 #endif /* VLAN_SUPPORT */
1738 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1739 rx_mode |= AcceptAll;
1740 } else if ((dev->mc_count > multicast_filter_limit)
1741 || (dev->flags & IFF_ALLMULTI)) {
1742 /* Too many to match, or accept all multicasts. */
1743 rx_mode |= AcceptBroadcast|AcceptAllMulticast|PerfectFilter;
1744 } else if (dev->mc_count <= 14) {
1745 /* Use the 16 element perfect filter, skip first two entries. */
1746 void __iomem *filter_addr = ioaddr + PerfFilterTable + 2 * 16;
1748 for (i = 2, mclist = dev->mc_list; mclist && i < dev->mc_count + 2;
1749 i++, mclist = mclist->next) {
1750 eaddrs = (__be16 *)mclist->dmi_addr;
1751 writew(be16_to_cpu(eaddrs[2]), filter_addr); filter_addr += 4;
1752 writew(be16_to_cpu(eaddrs[1]), filter_addr); filter_addr += 4;
1753 writew(be16_to_cpu(eaddrs[0]), filter_addr); filter_addr += 8;
1755 eaddrs = (__be16 *)dev->dev_addr;
1757 writew(be16_to_cpu(eaddrs[0]), filter_addr); filter_addr += 4;
1758 writew(be16_to_cpu(eaddrs[1]), filter_addr); filter_addr += 4;
1759 writew(be16_to_cpu(eaddrs[2]), filter_addr); filter_addr += 8;
1761 rx_mode |= AcceptBroadcast|PerfectFilter;
1763 /* Must use a multicast hash table. */
1764 void __iomem *filter_addr;
1766 __le16 mc_filter[32] __attribute__ ((aligned(sizeof(long)))); /* Multicast hash filter */
1768 memset(mc_filter, 0, sizeof(mc_filter));
1769 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1770 i++, mclist = mclist->next) {
1771 /* The chip uses the upper 9 CRC bits
1772 as index into the hash table */
1773 int bit_nr = ether_crc_le(ETH_ALEN, mclist->dmi_addr) >> 23;
1774 __le32 *fptr = (__le32 *) &mc_filter[(bit_nr >> 4) & ~1];
1776 *fptr |= cpu_to_le32(1 << (bit_nr & 31));
1778 /* Clear the perfect filter list, skip first two entries. */
1779 filter_addr = ioaddr + PerfFilterTable + 2 * 16;
1780 eaddrs = (__be16 *)dev->dev_addr;
1781 for (i = 2; i < 16; i++) {
1782 writew(be16_to_cpu(eaddrs[0]), filter_addr); filter_addr += 4;
1783 writew(be16_to_cpu(eaddrs[1]), filter_addr); filter_addr += 4;
1784 writew(be16_to_cpu(eaddrs[2]), filter_addr); filter_addr += 8;
1786 for (filter_addr = ioaddr + HashTable, i = 0; i < 32; filter_addr+= 16, i++)
1787 writew(mc_filter[i], filter_addr);
1788 rx_mode |= AcceptBroadcast|PerfectFilter|HashFilter;
1790 writel(rx_mode, ioaddr + RxFilterMode);
1793 static int check_if_running(struct net_device *dev)
1795 if (!netif_running(dev))
1800 static void get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1802 struct netdev_private *np = netdev_priv(dev);
1803 strcpy(info->driver, DRV_NAME);
1804 strcpy(info->version, DRV_VERSION);
1805 strcpy(info->bus_info, pci_name(np->pci_dev));
1808 static int get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
1810 struct netdev_private *np = netdev_priv(dev);
1811 spin_lock_irq(&np->lock);
1812 mii_ethtool_gset(&np->mii_if, ecmd);
1813 spin_unlock_irq(&np->lock);
1817 static int set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
1819 struct netdev_private *np = netdev_priv(dev);
1821 spin_lock_irq(&np->lock);
1822 res = mii_ethtool_sset(&np->mii_if, ecmd);
1823 spin_unlock_irq(&np->lock);
1828 static int nway_reset(struct net_device *dev)
1830 struct netdev_private *np = netdev_priv(dev);
1831 return mii_nway_restart(&np->mii_if);
1834 static u32 get_link(struct net_device *dev)
1836 struct netdev_private *np = netdev_priv(dev);
1837 return mii_link_ok(&np->mii_if);
1840 static u32 get_msglevel(struct net_device *dev)
1845 static void set_msglevel(struct net_device *dev, u32 val)
1850 static const struct ethtool_ops ethtool_ops = {
1851 .begin = check_if_running,
1852 .get_drvinfo = get_drvinfo,
1853 .get_settings = get_settings,
1854 .set_settings = set_settings,
1855 .nway_reset = nway_reset,
1856 .get_link = get_link,
1857 .get_msglevel = get_msglevel,
1858 .set_msglevel = set_msglevel,
1861 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1863 struct netdev_private *np = netdev_priv(dev);
1864 struct mii_ioctl_data *data = if_mii(rq);
1867 if (!netif_running(dev))
1870 spin_lock_irq(&np->lock);
1871 rc = generic_mii_ioctl(&np->mii_if, data, cmd, NULL);
1872 spin_unlock_irq(&np->lock);
1874 if ((cmd == SIOCSMIIREG) && (data->phy_id == np->phys[0]))
1880 static int netdev_close(struct net_device *dev)
1882 struct netdev_private *np = netdev_priv(dev);
1883 void __iomem *ioaddr = np->base;
1886 netif_stop_queue(dev);
1888 napi_disable(&np->napi);
1891 printk(KERN_DEBUG "%s: Shutting down ethercard, Intr status %#8.8x.\n",
1892 dev->name, (int) readl(ioaddr + IntrStatus));
1893 printk(KERN_DEBUG "%s: Queue pointers were Tx %d / %d, Rx %d / %d.\n",
1894 dev->name, np->cur_tx, np->dirty_tx,
1895 np->cur_rx, np->dirty_rx);
1898 /* Disable interrupts by clearing the interrupt mask. */
1899 writel(0, ioaddr + IntrEnable);
1901 /* Stop the chip's Tx and Rx processes. */
1902 writel(0, ioaddr + GenCtrl);
1903 readl(ioaddr + GenCtrl);
1906 printk(KERN_DEBUG" Tx ring at %#llx:\n",
1907 (long long) np->tx_ring_dma);
1908 for (i = 0; i < 8 /* TX_RING_SIZE is huge! */; i++)
1909 printk(KERN_DEBUG " #%d desc. %#8.8x %#llx -> %#8.8x.\n",
1910 i, le32_to_cpu(np->tx_ring[i].status),
1911 (long long) dma_to_cpu(np->tx_ring[i].addr),
1912 le32_to_cpu(np->tx_done_q[i].status));
1913 printk(KERN_DEBUG " Rx ring at %#llx -> %p:\n",
1914 (long long) np->rx_ring_dma, np->rx_done_q);
1916 for (i = 0; i < 8 /* RX_RING_SIZE */; i++) {
1917 printk(KERN_DEBUG " #%d desc. %#llx -> %#8.8x\n",
1918 i, (long long) dma_to_cpu(np->rx_ring[i].rxaddr), le32_to_cpu(np->rx_done_q[i].status));
1922 free_irq(dev->irq, dev);
1924 /* Free all the skbuffs in the Rx queue. */
1925 for (i = 0; i < RX_RING_SIZE; i++) {
1926 np->rx_ring[i].rxaddr = cpu_to_dma(0xBADF00D0); /* An invalid address. */
1927 if (np->rx_info[i].skb != NULL) {
1928 pci_unmap_single(np->pci_dev, np->rx_info[i].mapping, np->rx_buf_sz, PCI_DMA_FROMDEVICE);
1929 dev_kfree_skb(np->rx_info[i].skb);
1931 np->rx_info[i].skb = NULL;
1932 np->rx_info[i].mapping = 0;
1934 for (i = 0; i < TX_RING_SIZE; i++) {
1935 struct sk_buff *skb = np->tx_info[i].skb;
1938 pci_unmap_single(np->pci_dev,
1939 np->tx_info[i].mapping,
1940 skb_first_frag_len(skb), PCI_DMA_TODEVICE);
1941 np->tx_info[i].mapping = 0;
1943 np->tx_info[i].skb = NULL;
1950 static int starfire_suspend(struct pci_dev *pdev, pm_message_t state)
1952 struct net_device *dev = pci_get_drvdata(pdev);
1954 if (netif_running(dev)) {
1955 netif_device_detach(dev);
1959 pci_save_state(pdev);
1960 pci_set_power_state(pdev, pci_choose_state(pdev,state));
1965 static int starfire_resume(struct pci_dev *pdev)
1967 struct net_device *dev = pci_get_drvdata(pdev);
1969 pci_set_power_state(pdev, PCI_D0);
1970 pci_restore_state(pdev);
1972 if (netif_running(dev)) {
1974 netif_device_attach(dev);
1979 #endif /* CONFIG_PM */
1982 static void __devexit starfire_remove_one (struct pci_dev *pdev)
1984 struct net_device *dev = pci_get_drvdata(pdev);
1985 struct netdev_private *np = netdev_priv(dev);
1989 unregister_netdev(dev);
1992 pci_free_consistent(pdev, np->queue_mem_size, np->queue_mem, np->queue_mem_dma);
1995 /* XXX: add wakeup code -- requires firmware for MagicPacket */
1996 pci_set_power_state(pdev, PCI_D3hot); /* go to sleep in D3 mode */
1997 pci_disable_device(pdev);
2000 pci_release_regions(pdev);
2002 pci_set_drvdata(pdev, NULL);
2003 free_netdev(dev); /* Will also free np!! */
2007 static struct pci_driver starfire_driver = {
2009 .probe = starfire_init_one,
2010 .remove = __devexit_p(starfire_remove_one),
2012 .suspend = starfire_suspend,
2013 .resume = starfire_resume,
2014 #endif /* CONFIG_PM */
2015 .id_table = starfire_pci_tbl,
2019 static int __init starfire_init (void)
2021 /* when a module, this is printed whether or not devices are found in probe */
2025 printk(KERN_INFO DRV_NAME ": polling (NAPI) enabled\n");
2028 /* we can do this test only at run-time... sigh */
2029 if (sizeof(dma_addr_t) != sizeof(netdrv_addr_t)) {
2030 printk("This driver has dma_addr_t issues, please send email to maintainer\n");
2034 return pci_register_driver(&starfire_driver);
2038 static void __exit starfire_cleanup (void)
2040 pci_unregister_driver (&starfire_driver);
2044 module_init(starfire_init);
2045 module_exit(starfire_cleanup);