drivers/net/stmmac/dwmac1000_core.c

   1 /*******************************************************************************
   2   This is the driver for the GMAC on-chip Ethernet controller for ST SoCs.
   3   DWC Ether MAC 10/100/1000 Universal version 3.41a  has been used for
   4   developing this code.
   5
   6   This only implements the mac core functions for this chip.
   7
   8   Copyright (C) 2007-2009  STMicroelectronics Ltd
   9
  10   This program is free software; you can redistribute it and/or modify it
  11   under the terms and conditions of the GNU General Public License,
  12   version 2, as published by the Free Software Foundation.
  13
  14   This program is distributed in the hope it will be useful, but WITHOUT
  15   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  17   more details.
  18
  19   You should have received a copy of the GNU General Public License along with
  20   this program; if not, write to the Free Software Foundation, Inc.,
  21   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  22
  23   The full GNU General Public License is included in this distribution in
  24   the file called "COPYING".
  25
  26   Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
  27 *******************************************************************************/
  28
  29 #include <linux/crc32.h>
  30 #include "dwmac1000.h"
  31
  32 static void dwmac1000_core_init(unsigned long ioaddr)
  33 {
  34         u32 value = readl(ioaddr + GMAC_CONTROL);
  35         value |= GMAC_CORE_INIT;
  36         writel(value, ioaddr + GMAC_CONTROL);
  37
  38         /* STBus Bridge Configuration */
  39         /*writel(0xc5608, ioaddr + 0x00007000);*/
  40
  41         /* Freeze MMC counters */
  42         writel(0x8, ioaddr + GMAC_MMC_CTRL);
  43         /* Mask GMAC interrupts */
  44         writel(0x207, ioaddr + GMAC_INT_MASK);
  45
  46 #ifdef STMMAC_VLAN_TAG_USED
  47         /* Tag detection without filtering */
  48         writel(0x0, ioaddr + GMAC_VLAN_TAG);
  49 #endif
  50         return;
  51 }
  52
  53 static void dwmac1000_dump_regs(unsigned long ioaddr)
  54 {
  55         int i;
  56         pr_info("\tDWMAC1000 regs (base addr = 0x%8x)\n", (unsigned int)ioaddr);
  57
  58         for (i = 0; i < 55; i++) {
  59                 int offset = i * 4;
  60                 pr_info("\tReg No. %d (offset 0x%x): 0x%08x\n", i,
  61                         offset, readl(ioaddr + offset));
  62         }
  63         return;
  64 }
  65
  66 static void dwmac1000_set_umac_addr(unsigned long ioaddr, unsigned char *addr,
  67                                 unsigned int reg_n)
  68 {
  69         stmmac_set_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
  70                                 GMAC_ADDR_LOW(reg_n));
  71 }
  72
  73 static void dwmac1000_get_umac_addr(unsigned long ioaddr, unsigned char *addr,
  74                                 unsigned int reg_n)
  75 {
  76         stmmac_get_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
  77                                 GMAC_ADDR_LOW(reg_n));
  78 }
  79
  80 static void dwmac1000_set_filter(struct net_device *dev)
  81 {
  82         unsigned long ioaddr = dev->base_addr;
  83         unsigned int value = 0;
  84
  85         DBG(KERN_INFO "%s: # mcasts %d, # unicast %d\n",
  86             __func__, netdev_mc_count(dev), netdev_uc_count(dev));
  87
  88         if (dev->flags & IFF_PROMISC)
  89                 value = GMAC_FRAME_FILTER_PR;
  90         else if ((netdev_mc_count(dev) > HASH_TABLE_SIZE)
  91                    || (dev->flags & IFF_ALLMULTI)) {
  92                 value = GMAC_FRAME_FILTER_PM;   /* pass all multi */
  93                 writel(0xffffffff, ioaddr + GMAC_HASH_HIGH);
  94                 writel(0xffffffff, ioaddr + GMAC_HASH_LOW);
  95         } else if (!netdev_mc_empty(dev)) {
  96                 u32 mc_filter[2];
  97                 struct dev_mc_list *mclist;
  98
  99                 /* Hash filter for multicast */
 100                 value = GMAC_FRAME_FILTER_HMC;
 101
 102                 memset(mc_filter, 0, sizeof(mc_filter));
 103                 netdev_for_each_mc_addr(mclist, dev) {
 104                         /* The upper 6 bits of the calculated CRC are used to
 105                            index the contens of the hash table */
 106                         int bit_nr =
 107                             bitrev32(~crc32_le(~0, mclist->dmi_addr, 6)) >> 26;
 108                         /* The most significant bit determines the register to
 109                          * use (H/L) while the other 5 bits determine the bit
 110                          * within the register. */
 111                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
 112                 }
 113                 writel(mc_filter[0], ioaddr + GMAC_HASH_LOW);
 114                 writel(mc_filter[1], ioaddr + GMAC_HASH_HIGH);
 115         }
 116
 117         /* Handle multiple unicast addresses (perfect filtering)*/
 118         if (netdev_uc_count(dev) > GMAC_MAX_UNICAST_ADDRESSES)
 119                 /* Switch to promiscuous mode is more than 16 addrs
 120                    are required */
 121                 value |= GMAC_FRAME_FILTER_PR;
 122         else {
 123                 int reg = 1;
 124                 struct netdev_hw_addr *ha;
 125
 126                 netdev_for_each_uc_addr(ha, dev) {
 127                         dwmac1000_set_umac_addr(ioaddr, ha->addr, reg);
 128                         reg++;
 129                 }
 130         }
 131
 132 #ifdef FRAME_FILTER_DEBUG
 133         /* Enable Receive all mode (to debug filtering_fail errors) */
 134         value |= GMAC_FRAME_FILTER_RA;
 135 #endif
 136         writel(value, ioaddr + GMAC_FRAME_FILTER);
 137
 138         DBG(KERN_INFO "\tFrame Filter reg: 0x%08x\n\tHash regs: "
 139             "HI 0x%08x, LO 0x%08x\n", readl(ioaddr + GMAC_FRAME_FILTER),
 140             readl(ioaddr + GMAC_HASH_HIGH), readl(ioaddr + GMAC_HASH_LOW));
 141
 142         return;
 143 }
 144
 145 static void dwmac1000_flow_ctrl(unsigned long ioaddr, unsigned int duplex,
 146                            unsigned int fc, unsigned int pause_time)
 147 {
 148         unsigned int flow = 0;
 149
 150         DBG(KERN_DEBUG "GMAC Flow-Control:\n");
 151         if (fc & FLOW_RX) {
 152                 DBG(KERN_DEBUG "\tReceive Flow-Control ON\n");
 153                 flow |= GMAC_FLOW_CTRL_RFE;
 154         }
 155         if (fc & FLOW_TX) {
 156                 DBG(KERN_DEBUG "\tTransmit Flow-Control ON\n");
 157                 flow |= GMAC_FLOW_CTRL_TFE;
 158         }
 159
 160         if (duplex) {
 161                 DBG(KERN_DEBUG "\tduplex mode: pause time: %d\n", pause_time);
 162                 flow |= (pause_time << GMAC_FLOW_CTRL_PT_SHIFT);
 163         }
 164
 165         writel(flow, ioaddr + GMAC_FLOW_CTRL);
 166         return;
 167 }
 168
 169 static void dwmac1000_pmt(unsigned long ioaddr, unsigned long mode)
 170 {
 171         unsigned int pmt = 0;
 172
 173         if (mode == WAKE_MAGIC) {
 174                 DBG(KERN_DEBUG "GMAC: WOL Magic frame\n");
 175                 pmt |= power_down | magic_pkt_en;
 176         } else if (mode == WAKE_UCAST) {
 177                 DBG(KERN_DEBUG "GMAC: WOL on global unicast\n");
 178                 pmt |= global_unicast;
 179         }
 180
 181         writel(pmt, ioaddr + GMAC_PMT);
 182         return;
 183 }
 184
 185
 186 static void dwmac1000_irq_status(unsigned long ioaddr)
 187 {
 188         u32 intr_status = readl(ioaddr + GMAC_INT_STATUS);
 189
 190         /* Not used events (e.g. MMC interrupts) are not handled. */
 191         if ((intr_status & mmc_tx_irq))
 192                 DBG(KERN_DEBUG "GMAC: MMC tx interrupt: 0x%08x\n",
 193                     readl(ioaddr + GMAC_MMC_TX_INTR));
 194         if (unlikely(intr_status & mmc_rx_irq))
 195                 DBG(KERN_DEBUG "GMAC: MMC rx interrupt: 0x%08x\n",
 196                     readl(ioaddr + GMAC_MMC_RX_INTR));
 197         if (unlikely(intr_status & mmc_rx_csum_offload_irq))
 198                 DBG(KERN_DEBUG "GMAC: MMC rx csum offload: 0x%08x\n",
 199                     readl(ioaddr + GMAC_MMC_RX_CSUM_OFFLOAD));
 200         if (unlikely(intr_status & pmt_irq)) {
 201                 DBG(KERN_DEBUG "GMAC: received Magic frame\n");
 202                 /* clear the PMT bits 5 and 6 by reading the PMT
 203                  * status register. */
 204                 readl(ioaddr + GMAC_PMT);
 205         }
 206
 207         return;
 208 }
 209
 210 struct stmmac_ops dwmac1000_ops = {
 211         .core_init = dwmac1000_core_init,
 212         .dump_regs = dwmac1000_dump_regs,
 213         .host_irq_status = dwmac1000_irq_status,
 214         .set_filter = dwmac1000_set_filter,
 215         .flow_ctrl = dwmac1000_flow_ctrl,
 216         .pmt = dwmac1000_pmt,
 217         .set_umac_addr = dwmac1000_set_umac_addr,
 218         .get_umac_addr = dwmac1000_get_umac_addr,
 219 };
 220
 221 struct mac_device_info *dwmac1000_setup(unsigned long ioaddr)
 222 {
 223         struct mac_device_info *mac;
 224         u32 uid = readl(ioaddr + GMAC_VERSION);
 225
 226         pr_info("\tDWMAC1000 - user ID: 0x%x, Synopsys ID: 0x%x\n",
 227                 ((uid & 0x0000ff00) >> 8), (uid & 0x000000ff));
 228
 229         mac = kzalloc(sizeof(const struct mac_device_info), GFP_KERNEL);
 230
 231         mac->mac = &dwmac1000_ops;
 232         mac->desc = &dwmac1000_desc_ops;
 233         mac->dma = &dwmac1000_dma_ops;
 234
 235         mac->pmt = PMT_SUPPORTED;
 236         mac->link.port = GMAC_CONTROL_PS;
 237         mac->link.duplex = GMAC_CONTROL_DM;
 238         mac->link.speed = GMAC_CONTROL_FES;
 239         mac->mii.addr = GMAC_MII_ADDR;
 240         mac->mii.data = GMAC_MII_DATA;
 241
 242         return mac;
 243 }