1 /*******************************************************************************
2 Copyright (C) 2007-2009 STMicroelectronics Ltd
4 This program is free software; you can redistribute it and/or modify it
5 under the terms and conditions of the GNU General Public License,
6 version 2, as published by the Free Software Foundation.
8 This program is distributed in the hope it will be useful, but WITHOUT
9 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 You should have received a copy of the GNU General Public License along with
14 this program; if not, write to the Free Software Foundation, Inc.,
15 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
17 The full GNU General Public License is included in this distribution in
18 the file called "COPYING".
20 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
21 *******************************************************************************/
25 #include "dwmac_dma.h"
27 #undef DWMAC_DMA_DEBUG
28 #ifdef DWMAC_DMA_DEBUG
29 #define DBG(fmt, args...) printk(fmt, ## args)
31 #define DBG(fmt, args...) do { } while (0)
34 /* CSR1 enables the transmit DMA to check for new descriptor */
35 void dwmac_enable_dma_transmission(unsigned long ioaddr)
37 writel(1, ioaddr + DMA_XMT_POLL_DEMAND);
40 void dwmac_enable_dma_irq(unsigned long ioaddr)
42 writel(DMA_INTR_DEFAULT_MASK, ioaddr + DMA_INTR_ENA);
45 void dwmac_disable_dma_irq(unsigned long ioaddr)
47 writel(0, ioaddr + DMA_INTR_ENA);
50 void dwmac_dma_start_tx(unsigned long ioaddr)
52 u32 value = readl(ioaddr + DMA_CONTROL);
53 value |= DMA_CONTROL_ST;
54 writel(value, ioaddr + DMA_CONTROL);
58 void dwmac_dma_stop_tx(unsigned long ioaddr)
60 u32 value = readl(ioaddr + DMA_CONTROL);
61 value &= ~DMA_CONTROL_ST;
62 writel(value, ioaddr + DMA_CONTROL);
66 void dwmac_dma_start_rx(unsigned long ioaddr)
68 u32 value = readl(ioaddr + DMA_CONTROL);
69 value |= DMA_CONTROL_SR;
70 writel(value, ioaddr + DMA_CONTROL);
75 void dwmac_dma_stop_rx(unsigned long ioaddr)
77 u32 value = readl(ioaddr + DMA_CONTROL);
78 value &= ~DMA_CONTROL_SR;
79 writel(value, ioaddr + DMA_CONTROL);
84 #ifdef DWMAC_DMA_DEBUG
85 static void show_tx_process_state(unsigned int status)
88 state = (status & DMA_STATUS_TS_MASK) >> DMA_STATUS_TS_SHIFT;
92 pr_info("- TX (Stopped): Reset or Stop command\n");
95 pr_info("- TX (Running):Fetching the Tx desc\n");
98 pr_info("- TX (Running): Waiting for end of tx\n");
101 pr_info("- TX (Running): Reading the data "
102 "and queuing the data into the Tx buf\n");
105 pr_info("- TX (Suspended): Tx Buff Underflow "
106 "or an unavailable Transmit descriptor\n");
109 pr_info("- TX (Running): Closing Tx descriptor\n");
117 static void show_rx_process_state(unsigned int status)
120 state = (status & DMA_STATUS_RS_MASK) >> DMA_STATUS_RS_SHIFT;
124 pr_info("- RX (Stopped): Reset or Stop command\n");
127 pr_info("- RX (Running): Fetching the Rx desc\n");
130 pr_info("- RX (Running):Checking for end of pkt\n");
133 pr_info("- RX (Running): Waiting for Rx pkt\n");
136 pr_info("- RX (Suspended): Unavailable Rx buf\n");
139 pr_info("- RX (Running): Closing Rx descriptor\n");
142 pr_info("- RX(Running): Flushing the current frame"
143 " from the Rx buf\n");
146 pr_info("- RX (Running): Queuing the Rx frame"
147 " from the Rx buf into memory\n");
156 int dwmac_dma_interrupt(unsigned long ioaddr,
157 struct stmmac_extra_stats *x)
160 /* read the status register (CSR5) */
161 u32 intr_status = readl(ioaddr + DMA_STATUS);
163 DBG(INFO, "%s: [CSR5: 0x%08x]\n", __func__, intr_status);
164 #ifdef DWMAC_DMA_DEBUG
165 /* It displays the DMA process states (CSR5 register) */
166 show_tx_process_state(intr_status);
167 show_rx_process_state(intr_status);
169 /* ABNORMAL interrupts */
170 if (unlikely(intr_status & DMA_STATUS_AIS)) {
171 DBG(INFO, "CSR5[15] DMA ABNORMAL IRQ: ");
172 if (unlikely(intr_status & DMA_STATUS_UNF)) {
173 DBG(INFO, "transmit underflow\n");
174 ret = tx_hard_error_bump_tc;
175 x->tx_undeflow_irq++;
177 if (unlikely(intr_status & DMA_STATUS_TJT)) {
178 DBG(INFO, "transmit jabber\n");
181 if (unlikely(intr_status & DMA_STATUS_OVF)) {
182 DBG(INFO, "recv overflow\n");
183 x->rx_overflow_irq++;
185 if (unlikely(intr_status & DMA_STATUS_RU)) {
186 DBG(INFO, "receive buffer unavailable\n");
187 x->rx_buf_unav_irq++;
189 if (unlikely(intr_status & DMA_STATUS_RPS)) {
190 DBG(INFO, "receive process stopped\n");
191 x->rx_process_stopped_irq++;
193 if (unlikely(intr_status & DMA_STATUS_RWT)) {
194 DBG(INFO, "receive watchdog\n");
195 x->rx_watchdog_irq++;
197 if (unlikely(intr_status & DMA_STATUS_ETI)) {
198 DBG(INFO, "transmit early interrupt\n");
201 if (unlikely(intr_status & DMA_STATUS_TPS)) {
202 DBG(INFO, "transmit process stopped\n");
203 x->tx_process_stopped_irq++;
206 if (unlikely(intr_status & DMA_STATUS_FBI)) {
207 DBG(INFO, "fatal bus error\n");
208 x->fatal_bus_error_irq++;
212 /* TX/RX NORMAL interrupts */
213 if (intr_status & DMA_STATUS_NIS) {
215 if (likely((intr_status & DMA_STATUS_RI) ||
216 (intr_status & (DMA_STATUS_TI))))
219 /* Optional hardware blocks, interrupts should be disabled */
220 if (unlikely(intr_status &
221 (DMA_STATUS_GPI | DMA_STATUS_GMI | DMA_STATUS_GLI)))
222 pr_info("%s: unexpected status %08x\n", __func__, intr_status);
223 /* Clear the interrupt by writing a logic 1 to the CSR5[15-0] */
224 writel((intr_status & 0x1ffff), ioaddr + DMA_STATUS);
231 void stmmac_set_mac_addr(unsigned long ioaddr, u8 addr[6],
232 unsigned int high, unsigned int low)
236 data = (addr[5] << 8) | addr[4];
237 writel(data, ioaddr + high);
238 data = (addr[3] << 24) | (addr[2] << 16) | (addr[1] << 8) | addr[0];
239 writel(data, ioaddr + low);
244 void stmmac_get_mac_addr(unsigned long ioaddr, unsigned char *addr,
245 unsigned int high, unsigned int low)
247 unsigned int hi_addr, lo_addr;
249 /* Read the MAC address from the hardware */
250 hi_addr = readl(ioaddr + high);
251 lo_addr = readl(ioaddr + low);
253 /* Extract the MAC address from the high and low words */
254 addr[0] = lo_addr & 0xff;
255 addr[1] = (lo_addr >> 8) & 0xff;
256 addr[2] = (lo_addr >> 16) & 0xff;
257 addr[3] = (lo_addr >> 24) & 0xff;
258 addr[4] = hi_addr & 0xff;
259 addr[5] = (hi_addr >> 8) & 0xff;