1 /*******************************************************************************
2 STMMAC Ethernet Driver -- MDIO bus implementation
3 Provides Bus interface for MII registers
5 Copyright (C) 2007-2009 STMicroelectronics Ltd
7 This program is free software; you can redistribute it and/or modify it
8 under the terms and conditions of the GNU General Public License,
9 version 2, as published by the Free Software Foundation.
11 This program is distributed in the hope it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 You should have received a copy of the GNU General Public License along with
17 this program; if not, write to the Free Software Foundation, Inc.,
18 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
20 The full GNU General Public License is included in this distribution in
21 the file called "COPYING".
23 Author: Carl Shaw <carl.shaw@st.com>
24 Maintainer: Giuseppe Cavallaro <peppe.cavallaro@st.com>
25 *******************************************************************************/
27 #include <linux/mii.h>
28 #include <linux/phy.h>
32 #define MII_BUSY 0x00000001
33 #define MII_WRITE 0x00000002
37 * @bus: points to the mii_bus structure
38 * @phyaddr: MII addr reg bits 15-11
39 * @phyreg: MII addr reg bits 10-6
40 * Description: it reads data from the MII register from within the phy device.
41 * For the 7111 GMAC, we must set the bit 0 in the MII address register while
42 * accessing the PHY registers.
43 * Fortunately, it seems this has no drawback for the 7109 MAC.
45 static int stmmac_mdio_read(struct mii_bus *bus, int phyaddr, int phyreg)
47 struct net_device *ndev = bus->priv;
48 struct stmmac_priv *priv = netdev_priv(ndev);
49 unsigned long ioaddr = ndev->base_addr;
50 unsigned int mii_address = priv->hw->mii.addr;
51 unsigned int mii_data = priv->hw->mii.data;
54 u16 regValue = (((phyaddr << 11) & (0x0000F800)) |
55 ((phyreg << 6) & (0x000007C0)));
56 regValue |= MII_BUSY; /* in case of GMAC */
58 do {} while (((readl(ioaddr + mii_address)) & MII_BUSY) == 1);
59 writel(regValue, ioaddr + mii_address);
60 do {} while (((readl(ioaddr + mii_address)) & MII_BUSY) == 1);
62 /* Read the data from the MII data register */
63 data = (int)readl(ioaddr + mii_data);
70 * @bus: points to the mii_bus structure
71 * @phyaddr: MII addr reg bits 15-11
72 * @phyreg: MII addr reg bits 10-6
74 * Description: it writes the data into the MII register from within the device.
76 static int stmmac_mdio_write(struct mii_bus *bus, int phyaddr, int phyreg,
79 struct net_device *ndev = bus->priv;
80 struct stmmac_priv *priv = netdev_priv(ndev);
81 unsigned long ioaddr = ndev->base_addr;
82 unsigned int mii_address = priv->hw->mii.addr;
83 unsigned int mii_data = priv->hw->mii.data;
86 (((phyaddr << 11) & (0x0000F800)) | ((phyreg << 6) & (0x000007C0)))
91 /* Wait until any existing MII operation is complete */
92 do {} while (((readl(ioaddr + mii_address)) & MII_BUSY) == 1);
94 /* Set the MII address register to write */
95 writel(phydata, ioaddr + mii_data);
96 writel(value, ioaddr + mii_address);
98 /* Wait until any existing MII operation is complete */
99 do {} while (((readl(ioaddr + mii_address)) & MII_BUSY) == 1);
106 * @bus: points to the mii_bus structure
107 * Description: reset the MII bus
109 static int stmmac_mdio_reset(struct mii_bus *bus)
111 struct net_device *ndev = bus->priv;
112 struct stmmac_priv *priv = netdev_priv(ndev);
113 unsigned long ioaddr = ndev->base_addr;
114 unsigned int mii_address = priv->hw->mii.addr;
116 if (priv->phy_reset) {
117 pr_debug("stmmac_mdio_reset: calling phy_reset\n");
118 priv->phy_reset(priv->bsp_priv);
121 /* This is a workaround for problems with the STE101P PHY.
122 * It doesn't complete its reset until at least one clock cycle
123 * on MDC, so perform a dummy mdio read.
125 writel(0, ioaddr + mii_address);
131 * stmmac_mdio_register
132 * @ndev: net device structure
133 * Description: it registers the MII bus
135 int stmmac_mdio_register(struct net_device *ndev)
138 struct mii_bus *new_bus;
140 struct stmmac_priv *priv = netdev_priv(ndev);
143 new_bus = mdiobus_alloc();
147 irqlist = kzalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
148 if (irqlist == NULL) {
150 goto irqlist_alloc_fail;
153 /* Assign IRQ to phy at address phy_addr */
154 if (priv->phy_addr != -1)
155 irqlist[priv->phy_addr] = priv->phy_irq;
157 new_bus->name = "STMMAC MII Bus";
158 new_bus->read = &stmmac_mdio_read;
159 new_bus->write = &stmmac_mdio_write;
160 new_bus->reset = &stmmac_mdio_reset;
161 snprintf(new_bus->id, MII_BUS_ID_SIZE, "%x", priv->bus_id);
162 new_bus->priv = ndev;
163 new_bus->irq = irqlist;
164 new_bus->phy_mask = priv->phy_mask;
165 new_bus->parent = priv->device;
166 err = mdiobus_register(new_bus);
168 pr_err("%s: Cannot register as MDIO bus\n", new_bus->name);
169 goto bus_register_fail;
175 for (addr = 0; addr < 32; addr++) {
176 struct phy_device *phydev = new_bus->phy_map[addr];
178 if (priv->phy_addr == -1) {
179 priv->phy_addr = addr;
180 phydev->irq = priv->phy_irq;
181 irqlist[addr] = priv->phy_irq;
183 pr_info("%s: PHY ID %08x at %d IRQ %d (%s)%s\n",
184 ndev->name, phydev->phy_id, addr,
185 phydev->irq, dev_name(&phydev->dev),
186 (addr == priv->phy_addr) ? " active" : "");
192 pr_warning("%s: No PHY found\n", ndev->name);
203 * stmmac_mdio_unregister
204 * @ndev: net device structure
205 * Description: it unregisters the MII bus
207 int stmmac_mdio_unregister(struct net_device *ndev)
209 struct stmmac_priv *priv = netdev_priv(ndev);
211 mdiobus_unregister(priv->mii);
212 priv->mii->priv = NULL;