2 * tg3.c: Broadcom Tigon3 ethernet driver.
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
7 * Copyright (C) 2005-2009 Broadcom Corporation.
10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/kernel.h>
22 #include <linux/types.h>
23 #include <linux/compiler.h>
24 #include <linux/slab.h>
25 #include <linux/delay.h>
27 #include <linux/init.h>
28 #include <linux/ioport.h>
29 #include <linux/pci.h>
30 #include <linux/netdevice.h>
31 #include <linux/etherdevice.h>
32 #include <linux/skbuff.h>
33 #include <linux/ethtool.h>
34 #include <linux/mii.h>
35 #include <linux/phy.h>
36 #include <linux/brcmphy.h>
37 #include <linux/if_vlan.h>
39 #include <linux/tcp.h>
40 #include <linux/workqueue.h>
41 #include <linux/prefetch.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/firmware.h>
45 #include <net/checksum.h>
48 #include <asm/system.h>
50 #include <asm/byteorder.h>
51 #include <asm/uaccess.h>
54 #include <asm/idprom.h>
61 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
62 #define TG3_VLAN_TAG_USED 1
64 #define TG3_VLAN_TAG_USED 0
69 #define DRV_MODULE_NAME "tg3"
70 #define PFX DRV_MODULE_NAME ": "
71 #define DRV_MODULE_VERSION "3.104"
72 #define DRV_MODULE_RELDATE "November 13, 2009"
74 #define TG3_DEF_MAC_MODE 0
75 #define TG3_DEF_RX_MODE 0
76 #define TG3_DEF_TX_MODE 0
77 #define TG3_DEF_MSG_ENABLE \
87 /* length of time before we decide the hardware is borked,
88 * and dev->tx_timeout() should be called to fix the problem
90 #define TG3_TX_TIMEOUT (5 * HZ)
92 /* hardware minimum and maximum for a single frame's data payload */
93 #define TG3_MIN_MTU 60
94 #define TG3_MAX_MTU(tp) \
95 ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
97 /* These numbers seem to be hard coded in the NIC firmware somehow.
98 * You can't change the ring sizes, but you can change where you place
99 * them in the NIC onboard memory.
101 #define TG3_RX_RING_SIZE 512
102 #define TG3_DEF_RX_RING_PENDING 200
103 #define TG3_RX_JUMBO_RING_SIZE 256
104 #define TG3_DEF_RX_JUMBO_RING_PENDING 100
105 #define TG3_RSS_INDIR_TBL_SIZE 128
107 /* Do not place this n-ring entries value into the tp struct itself,
108 * we really want to expose these constants to GCC so that modulo et
109 * al. operations are done with shifts and masks instead of with
110 * hw multiply/modulo instructions. Another solution would be to
111 * replace things like '% foo' with '& (foo - 1)'.
113 #define TG3_RX_RCB_RING_SIZE(tp) \
114 (((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) && \
115 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) ? 1024 : 512)
117 #define TG3_TX_RING_SIZE 512
118 #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
120 #define TG3_RX_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
122 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_ext_rx_buffer_desc) * \
123 TG3_RX_JUMBO_RING_SIZE)
124 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
125 TG3_RX_RCB_RING_SIZE(tp))
126 #define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
128 #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
130 #define TG3_DMA_BYTE_ENAB 64
132 #define TG3_RX_STD_DMA_SZ 1536
133 #define TG3_RX_JMB_DMA_SZ 9046
135 #define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB)
137 #define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
138 #define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
140 #define TG3_RX_STD_BUFF_RING_SIZE \
141 (sizeof(struct ring_info) * TG3_RX_RING_SIZE)
143 #define TG3_RX_JMB_BUFF_RING_SIZE \
144 (sizeof(struct ring_info) * TG3_RX_JUMBO_RING_SIZE)
146 /* minimum number of free TX descriptors required to wake up TX process */
147 #define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
149 #define TG3_RAW_IP_ALIGN 2
151 /* number of ETHTOOL_GSTATS u64's */
152 #define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
154 #define TG3_NUM_TEST 6
156 #define FIRMWARE_TG3 "tigon/tg3.bin"
157 #define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
158 #define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
160 static char version[] __devinitdata =
161 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
163 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
164 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
165 MODULE_LICENSE("GPL");
166 MODULE_VERSION(DRV_MODULE_VERSION);
167 MODULE_FIRMWARE(FIRMWARE_TG3);
168 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
169 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
171 #define TG3_RSS_MIN_NUM_MSIX_VECS 2
173 static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
174 module_param(tg3_debug, int, 0);
175 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
177 static struct pci_device_id tg3_pci_tbl[] = {
178 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
179 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
180 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
181 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
182 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
183 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
184 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
185 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
186 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
187 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
188 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
189 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
190 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
191 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
192 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
193 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
194 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
195 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
196 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
197 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
198 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
199 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
200 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
201 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
202 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
203 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
204 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
205 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
206 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
207 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
208 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
209 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
210 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
211 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
212 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
213 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
214 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
215 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
216 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
217 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
218 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
219 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
220 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
221 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
222 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
223 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
224 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
225 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
226 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
227 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
228 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
229 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
230 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
231 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
232 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
233 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
234 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
235 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
236 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
237 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
238 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
239 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
240 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
241 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
242 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
243 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
244 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
245 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
246 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5724)},
247 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
248 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
249 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
250 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
251 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
252 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
253 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
257 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
259 static const struct {
260 const char string[ETH_GSTRING_LEN];
261 } ethtool_stats_keys[TG3_NUM_STATS] = {
264 { "rx_ucast_packets" },
265 { "rx_mcast_packets" },
266 { "rx_bcast_packets" },
268 { "rx_align_errors" },
269 { "rx_xon_pause_rcvd" },
270 { "rx_xoff_pause_rcvd" },
271 { "rx_mac_ctrl_rcvd" },
272 { "rx_xoff_entered" },
273 { "rx_frame_too_long_errors" },
275 { "rx_undersize_packets" },
276 { "rx_in_length_errors" },
277 { "rx_out_length_errors" },
278 { "rx_64_or_less_octet_packets" },
279 { "rx_65_to_127_octet_packets" },
280 { "rx_128_to_255_octet_packets" },
281 { "rx_256_to_511_octet_packets" },
282 { "rx_512_to_1023_octet_packets" },
283 { "rx_1024_to_1522_octet_packets" },
284 { "rx_1523_to_2047_octet_packets" },
285 { "rx_2048_to_4095_octet_packets" },
286 { "rx_4096_to_8191_octet_packets" },
287 { "rx_8192_to_9022_octet_packets" },
294 { "tx_flow_control" },
296 { "tx_single_collisions" },
297 { "tx_mult_collisions" },
299 { "tx_excessive_collisions" },
300 { "tx_late_collisions" },
301 { "tx_collide_2times" },
302 { "tx_collide_3times" },
303 { "tx_collide_4times" },
304 { "tx_collide_5times" },
305 { "tx_collide_6times" },
306 { "tx_collide_7times" },
307 { "tx_collide_8times" },
308 { "tx_collide_9times" },
309 { "tx_collide_10times" },
310 { "tx_collide_11times" },
311 { "tx_collide_12times" },
312 { "tx_collide_13times" },
313 { "tx_collide_14times" },
314 { "tx_collide_15times" },
315 { "tx_ucast_packets" },
316 { "tx_mcast_packets" },
317 { "tx_bcast_packets" },
318 { "tx_carrier_sense_errors" },
322 { "dma_writeq_full" },
323 { "dma_write_prioq_full" },
327 { "rx_threshold_hit" },
329 { "dma_readq_full" },
330 { "dma_read_prioq_full" },
331 { "tx_comp_queue_full" },
333 { "ring_set_send_prod_index" },
334 { "ring_status_update" },
336 { "nic_avoided_irqs" },
337 { "nic_tx_threshold_hit" }
340 static const struct {
341 const char string[ETH_GSTRING_LEN];
342 } ethtool_test_keys[TG3_NUM_TEST] = {
343 { "nvram test (online) " },
344 { "link test (online) " },
345 { "register test (offline)" },
346 { "memory test (offline)" },
347 { "loopback test (offline)" },
348 { "interrupt test (offline)" },
351 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
353 writel(val, tp->regs + off);
356 static u32 tg3_read32(struct tg3 *tp, u32 off)
358 return (readl(tp->regs + off));
361 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
363 writel(val, tp->aperegs + off);
366 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
368 return (readl(tp->aperegs + off));
371 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
375 spin_lock_irqsave(&tp->indirect_lock, flags);
376 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
377 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
378 spin_unlock_irqrestore(&tp->indirect_lock, flags);
381 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
383 writel(val, tp->regs + off);
384 readl(tp->regs + off);
387 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
392 spin_lock_irqsave(&tp->indirect_lock, flags);
393 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
394 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
395 spin_unlock_irqrestore(&tp->indirect_lock, flags);
399 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
403 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
404 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
405 TG3_64BIT_REG_LOW, val);
408 if (off == TG3_RX_STD_PROD_IDX_REG) {
409 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
410 TG3_64BIT_REG_LOW, val);
414 spin_lock_irqsave(&tp->indirect_lock, flags);
415 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
416 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
417 spin_unlock_irqrestore(&tp->indirect_lock, flags);
419 /* In indirect mode when disabling interrupts, we also need
420 * to clear the interrupt bit in the GRC local ctrl register.
422 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
424 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
425 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
429 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
434 spin_lock_irqsave(&tp->indirect_lock, flags);
435 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
436 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
437 spin_unlock_irqrestore(&tp->indirect_lock, flags);
441 /* usec_wait specifies the wait time in usec when writing to certain registers
442 * where it is unsafe to read back the register without some delay.
443 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
444 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
446 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
448 if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
449 (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
450 /* Non-posted methods */
451 tp->write32(tp, off, val);
454 tg3_write32(tp, off, val);
459 /* Wait again after the read for the posted method to guarantee that
460 * the wait time is met.
466 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
468 tp->write32_mbox(tp, off, val);
469 if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
470 !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
471 tp->read32_mbox(tp, off);
474 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
476 void __iomem *mbox = tp->regs + off;
478 if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
480 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
484 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
486 return (readl(tp->regs + off + GRCMBOX_BASE));
489 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
491 writel(val, tp->regs + off + GRCMBOX_BASE);
494 #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
495 #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
496 #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
497 #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
498 #define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
500 #define tw32(reg,val) tp->write32(tp, reg, val)
501 #define tw32_f(reg,val) _tw32_flush(tp,(reg),(val), 0)
502 #define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
503 #define tr32(reg) tp->read32(tp, reg)
505 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
509 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
510 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
513 spin_lock_irqsave(&tp->indirect_lock, flags);
514 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
515 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
516 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
518 /* Always leave this as zero. */
519 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
521 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
522 tw32_f(TG3PCI_MEM_WIN_DATA, val);
524 /* Always leave this as zero. */
525 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
527 spin_unlock_irqrestore(&tp->indirect_lock, flags);
530 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
534 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
535 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
540 spin_lock_irqsave(&tp->indirect_lock, flags);
541 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
542 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
543 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
545 /* Always leave this as zero. */
546 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
548 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
549 *val = tr32(TG3PCI_MEM_WIN_DATA);
551 /* Always leave this as zero. */
552 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
554 spin_unlock_irqrestore(&tp->indirect_lock, flags);
557 static void tg3_ape_lock_init(struct tg3 *tp)
561 /* Make sure the driver hasn't any stale locks. */
562 for (i = 0; i < 8; i++)
563 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + 4 * i,
564 APE_LOCK_GRANT_DRIVER);
567 static int tg3_ape_lock(struct tg3 *tp, int locknum)
573 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
577 case TG3_APE_LOCK_GRC:
578 case TG3_APE_LOCK_MEM:
586 tg3_ape_write32(tp, TG3_APE_LOCK_REQ + off, APE_LOCK_REQ_DRIVER);
588 /* Wait for up to 1 millisecond to acquire lock. */
589 for (i = 0; i < 100; i++) {
590 status = tg3_ape_read32(tp, TG3_APE_LOCK_GRANT + off);
591 if (status == APE_LOCK_GRANT_DRIVER)
596 if (status != APE_LOCK_GRANT_DRIVER) {
597 /* Revoke the lock request. */
598 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off,
599 APE_LOCK_GRANT_DRIVER);
607 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
611 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
615 case TG3_APE_LOCK_GRC:
616 case TG3_APE_LOCK_MEM:
623 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off, APE_LOCK_GRANT_DRIVER);
626 static void tg3_disable_ints(struct tg3 *tp)
630 tw32(TG3PCI_MISC_HOST_CTRL,
631 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
632 for (i = 0; i < tp->irq_max; i++)
633 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
636 static void tg3_enable_ints(struct tg3 *tp)
644 tw32(TG3PCI_MISC_HOST_CTRL,
645 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
647 for (i = 0; i < tp->irq_cnt; i++) {
648 struct tg3_napi *tnapi = &tp->napi[i];
649 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
650 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
651 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
653 coal_now |= tnapi->coal_now;
656 /* Force an initial interrupt */
657 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
658 (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
659 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
661 tw32(HOSTCC_MODE, tp->coalesce_mode |
662 HOSTCC_MODE_ENABLE | coal_now);
665 static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
667 struct tg3 *tp = tnapi->tp;
668 struct tg3_hw_status *sblk = tnapi->hw_status;
669 unsigned int work_exists = 0;
671 /* check for phy events */
672 if (!(tp->tg3_flags &
673 (TG3_FLAG_USE_LINKCHG_REG |
674 TG3_FLAG_POLL_SERDES))) {
675 if (sblk->status & SD_STATUS_LINK_CHG)
678 /* check for RX/TX work to do */
679 if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
680 *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
687 * similar to tg3_enable_ints, but it accurately determines whether there
688 * is new work pending and can return without flushing the PIO write
689 * which reenables interrupts
691 static void tg3_int_reenable(struct tg3_napi *tnapi)
693 struct tg3 *tp = tnapi->tp;
695 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
698 /* When doing tagged status, this work check is unnecessary.
699 * The last_tag we write above tells the chip which piece of
700 * work we've completed.
702 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
704 tw32(HOSTCC_MODE, tp->coalesce_mode |
705 HOSTCC_MODE_ENABLE | tnapi->coal_now);
708 static void tg3_napi_disable(struct tg3 *tp)
712 for (i = tp->irq_cnt - 1; i >= 0; i--)
713 napi_disable(&tp->napi[i].napi);
716 static void tg3_napi_enable(struct tg3 *tp)
720 for (i = 0; i < tp->irq_cnt; i++)
721 napi_enable(&tp->napi[i].napi);
724 static inline void tg3_netif_stop(struct tg3 *tp)
726 tp->dev->trans_start = jiffies; /* prevent tx timeout */
727 tg3_napi_disable(tp);
728 netif_tx_disable(tp->dev);
731 static inline void tg3_netif_start(struct tg3 *tp)
733 /* NOTE: unconditional netif_tx_wake_all_queues is only
734 * appropriate so long as all callers are assured to
735 * have free tx slots (such as after tg3_init_hw)
737 netif_tx_wake_all_queues(tp->dev);
740 tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
744 static void tg3_switch_clocks(struct tg3 *tp)
749 if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
750 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
753 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
755 orig_clock_ctrl = clock_ctrl;
756 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
757 CLOCK_CTRL_CLKRUN_OENABLE |
759 tp->pci_clock_ctrl = clock_ctrl;
761 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
762 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
763 tw32_wait_f(TG3PCI_CLOCK_CTRL,
764 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
766 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
767 tw32_wait_f(TG3PCI_CLOCK_CTRL,
769 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
771 tw32_wait_f(TG3PCI_CLOCK_CTRL,
772 clock_ctrl | (CLOCK_CTRL_ALTCLK),
775 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
778 #define PHY_BUSY_LOOPS 5000
780 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
786 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
788 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
794 frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
795 MI_COM_PHY_ADDR_MASK);
796 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
797 MI_COM_REG_ADDR_MASK);
798 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
800 tw32_f(MAC_MI_COM, frame_val);
802 loops = PHY_BUSY_LOOPS;
805 frame_val = tr32(MAC_MI_COM);
807 if ((frame_val & MI_COM_BUSY) == 0) {
809 frame_val = tr32(MAC_MI_COM);
817 *val = frame_val & MI_COM_DATA_MASK;
821 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
822 tw32_f(MAC_MI_MODE, tp->mi_mode);
829 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
835 if ((tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
836 (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
839 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
841 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
845 frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
846 MI_COM_PHY_ADDR_MASK);
847 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
848 MI_COM_REG_ADDR_MASK);
849 frame_val |= (val & MI_COM_DATA_MASK);
850 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
852 tw32_f(MAC_MI_COM, frame_val);
854 loops = PHY_BUSY_LOOPS;
857 frame_val = tr32(MAC_MI_COM);
858 if ((frame_val & MI_COM_BUSY) == 0) {
860 frame_val = tr32(MAC_MI_COM);
870 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
871 tw32_f(MAC_MI_MODE, tp->mi_mode);
878 static int tg3_bmcr_reset(struct tg3 *tp)
883 /* OK, reset it, and poll the BMCR_RESET bit until it
884 * clears or we time out.
886 phy_control = BMCR_RESET;
887 err = tg3_writephy(tp, MII_BMCR, phy_control);
893 err = tg3_readphy(tp, MII_BMCR, &phy_control);
897 if ((phy_control & BMCR_RESET) == 0) {
909 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
911 struct tg3 *tp = bp->priv;
914 spin_lock_bh(&tp->lock);
916 if (tg3_readphy(tp, reg, &val))
919 spin_unlock_bh(&tp->lock);
924 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
926 struct tg3 *tp = bp->priv;
929 spin_lock_bh(&tp->lock);
931 if (tg3_writephy(tp, reg, val))
934 spin_unlock_bh(&tp->lock);
939 static int tg3_mdio_reset(struct mii_bus *bp)
944 static void tg3_mdio_config_5785(struct tg3 *tp)
947 struct phy_device *phydev;
949 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
950 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
951 case TG3_PHY_ID_BCM50610:
952 case TG3_PHY_ID_BCM50610M:
953 val = MAC_PHYCFG2_50610_LED_MODES;
955 case TG3_PHY_ID_BCMAC131:
956 val = MAC_PHYCFG2_AC131_LED_MODES;
958 case TG3_PHY_ID_RTL8211C:
959 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
961 case TG3_PHY_ID_RTL8201E:
962 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
968 if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
969 tw32(MAC_PHYCFG2, val);
971 val = tr32(MAC_PHYCFG1);
972 val &= ~(MAC_PHYCFG1_RGMII_INT |
973 MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
974 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
975 tw32(MAC_PHYCFG1, val);
980 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE))
981 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
982 MAC_PHYCFG2_FMODE_MASK_MASK |
983 MAC_PHYCFG2_GMODE_MASK_MASK |
984 MAC_PHYCFG2_ACT_MASK_MASK |
985 MAC_PHYCFG2_QUAL_MASK_MASK |
986 MAC_PHYCFG2_INBAND_ENABLE;
988 tw32(MAC_PHYCFG2, val);
990 val = tr32(MAC_PHYCFG1);
991 val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
992 MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
993 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
994 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
995 val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
996 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
997 val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
999 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1000 MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1001 tw32(MAC_PHYCFG1, val);
1003 val = tr32(MAC_EXT_RGMII_MODE);
1004 val &= ~(MAC_RGMII_MODE_RX_INT_B |
1005 MAC_RGMII_MODE_RX_QUALITY |
1006 MAC_RGMII_MODE_RX_ACTIVITY |
1007 MAC_RGMII_MODE_RX_ENG_DET |
1008 MAC_RGMII_MODE_TX_ENABLE |
1009 MAC_RGMII_MODE_TX_LOWPWR |
1010 MAC_RGMII_MODE_TX_RESET);
1011 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
1012 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1013 val |= MAC_RGMII_MODE_RX_INT_B |
1014 MAC_RGMII_MODE_RX_QUALITY |
1015 MAC_RGMII_MODE_RX_ACTIVITY |
1016 MAC_RGMII_MODE_RX_ENG_DET;
1017 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1018 val |= MAC_RGMII_MODE_TX_ENABLE |
1019 MAC_RGMII_MODE_TX_LOWPWR |
1020 MAC_RGMII_MODE_TX_RESET;
1022 tw32(MAC_EXT_RGMII_MODE, val);
1025 static void tg3_mdio_start(struct tg3 *tp)
1027 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1028 tw32_f(MAC_MI_MODE, tp->mi_mode);
1031 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
1032 u32 funcnum, is_serdes;
1034 funcnum = tr32(TG3_CPMU_STATUS) & TG3_CPMU_STATUS_PCIE_FUNC;
1040 is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1044 tp->phy_addr = TG3_PHY_MII_ADDR;
1046 if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
1047 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1048 tg3_mdio_config_5785(tp);
1051 static int tg3_mdio_init(struct tg3 *tp)
1055 struct phy_device *phydev;
1059 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1060 (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1063 tp->mdio_bus = mdiobus_alloc();
1064 if (tp->mdio_bus == NULL)
1067 tp->mdio_bus->name = "tg3 mdio bus";
1068 snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1069 (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1070 tp->mdio_bus->priv = tp;
1071 tp->mdio_bus->parent = &tp->pdev->dev;
1072 tp->mdio_bus->read = &tg3_mdio_read;
1073 tp->mdio_bus->write = &tg3_mdio_write;
1074 tp->mdio_bus->reset = &tg3_mdio_reset;
1075 tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
1076 tp->mdio_bus->irq = &tp->mdio_irq[0];
1078 for (i = 0; i < PHY_MAX_ADDR; i++)
1079 tp->mdio_bus->irq[i] = PHY_POLL;
1081 /* The bus registration will look for all the PHYs on the mdio bus.
1082 * Unfortunately, it does not ensure the PHY is powered up before
1083 * accessing the PHY ID registers. A chip reset is the
1084 * quickest way to bring the device back to an operational state..
1086 if (tg3_readphy(tp, MII_BMCR, ®) || (reg & BMCR_PDOWN))
1089 i = mdiobus_register(tp->mdio_bus);
1091 printk(KERN_WARNING "%s: mdiobus_reg failed (0x%x)\n",
1093 mdiobus_free(tp->mdio_bus);
1097 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1099 if (!phydev || !phydev->drv) {
1100 printk(KERN_WARNING "%s: No PHY devices\n", tp->dev->name);
1101 mdiobus_unregister(tp->mdio_bus);
1102 mdiobus_free(tp->mdio_bus);
1106 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1107 case TG3_PHY_ID_BCM57780:
1108 phydev->interface = PHY_INTERFACE_MODE_GMII;
1109 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1111 case TG3_PHY_ID_BCM50610:
1112 case TG3_PHY_ID_BCM50610M:
1113 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
1114 PHY_BRCM_RX_REFCLK_UNUSED |
1115 PHY_BRCM_DIS_TXCRXC_NOENRGY |
1116 PHY_BRCM_AUTO_PWRDWN_ENABLE;
1117 if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)
1118 phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1119 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1120 phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1121 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1122 phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1124 case TG3_PHY_ID_RTL8211C:
1125 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1127 case TG3_PHY_ID_RTL8201E:
1128 case TG3_PHY_ID_BCMAC131:
1129 phydev->interface = PHY_INTERFACE_MODE_MII;
1130 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1131 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
1135 tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1137 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1138 tg3_mdio_config_5785(tp);
1143 static void tg3_mdio_fini(struct tg3 *tp)
1145 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1146 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
1147 mdiobus_unregister(tp->mdio_bus);
1148 mdiobus_free(tp->mdio_bus);
1152 /* tp->lock is held. */
1153 static inline void tg3_generate_fw_event(struct tg3 *tp)
1157 val = tr32(GRC_RX_CPU_EVENT);
1158 val |= GRC_RX_CPU_DRIVER_EVENT;
1159 tw32_f(GRC_RX_CPU_EVENT, val);
1161 tp->last_event_jiffies = jiffies;
1164 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1166 /* tp->lock is held. */
1167 static void tg3_wait_for_event_ack(struct tg3 *tp)
1170 unsigned int delay_cnt;
1173 /* If enough time has passed, no wait is necessary. */
1174 time_remain = (long)(tp->last_event_jiffies + 1 +
1175 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1177 if (time_remain < 0)
1180 /* Check if we can shorten the wait time. */
1181 delay_cnt = jiffies_to_usecs(time_remain);
1182 if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1183 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1184 delay_cnt = (delay_cnt >> 3) + 1;
1186 for (i = 0; i < delay_cnt; i++) {
1187 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1193 /* tp->lock is held. */
1194 static void tg3_ump_link_report(struct tg3 *tp)
1199 if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1200 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
1203 tg3_wait_for_event_ack(tp);
1205 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1207 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1210 if (!tg3_readphy(tp, MII_BMCR, ®))
1212 if (!tg3_readphy(tp, MII_BMSR, ®))
1213 val |= (reg & 0xffff);
1214 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1217 if (!tg3_readphy(tp, MII_ADVERTISE, ®))
1219 if (!tg3_readphy(tp, MII_LPA, ®))
1220 val |= (reg & 0xffff);
1221 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1224 if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) {
1225 if (!tg3_readphy(tp, MII_CTRL1000, ®))
1227 if (!tg3_readphy(tp, MII_STAT1000, ®))
1228 val |= (reg & 0xffff);
1230 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1232 if (!tg3_readphy(tp, MII_PHYADDR, ®))
1236 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1238 tg3_generate_fw_event(tp);
1241 static void tg3_link_report(struct tg3 *tp)
1243 if (!netif_carrier_ok(tp->dev)) {
1244 if (netif_msg_link(tp))
1245 printk(KERN_INFO PFX "%s: Link is down.\n",
1247 tg3_ump_link_report(tp);
1248 } else if (netif_msg_link(tp)) {
1249 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1251 (tp->link_config.active_speed == SPEED_1000 ?
1253 (tp->link_config.active_speed == SPEED_100 ?
1255 (tp->link_config.active_duplex == DUPLEX_FULL ?
1258 printk(KERN_INFO PFX
1259 "%s: Flow control is %s for TX and %s for RX.\n",
1261 (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1263 (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1265 tg3_ump_link_report(tp);
1269 static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1273 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1274 miireg = ADVERTISE_PAUSE_CAP;
1275 else if (flow_ctrl & FLOW_CTRL_TX)
1276 miireg = ADVERTISE_PAUSE_ASYM;
1277 else if (flow_ctrl & FLOW_CTRL_RX)
1278 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1285 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1289 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1290 miireg = ADVERTISE_1000XPAUSE;
1291 else if (flow_ctrl & FLOW_CTRL_TX)
1292 miireg = ADVERTISE_1000XPSE_ASYM;
1293 else if (flow_ctrl & FLOW_CTRL_RX)
1294 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1301 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1305 if (lcladv & ADVERTISE_1000XPAUSE) {
1306 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1307 if (rmtadv & LPA_1000XPAUSE)
1308 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1309 else if (rmtadv & LPA_1000XPAUSE_ASYM)
1312 if (rmtadv & LPA_1000XPAUSE)
1313 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1315 } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1316 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1323 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1327 u32 old_rx_mode = tp->rx_mode;
1328 u32 old_tx_mode = tp->tx_mode;
1330 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
1331 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
1333 autoneg = tp->link_config.autoneg;
1335 if (autoneg == AUTONEG_ENABLE &&
1336 (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1337 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1338 flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1340 flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1342 flowctrl = tp->link_config.flowctrl;
1344 tp->link_config.active_flowctrl = flowctrl;
1346 if (flowctrl & FLOW_CTRL_RX)
1347 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1349 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1351 if (old_rx_mode != tp->rx_mode)
1352 tw32_f(MAC_RX_MODE, tp->rx_mode);
1354 if (flowctrl & FLOW_CTRL_TX)
1355 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1357 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1359 if (old_tx_mode != tp->tx_mode)
1360 tw32_f(MAC_TX_MODE, tp->tx_mode);
1363 static void tg3_adjust_link(struct net_device *dev)
1365 u8 oldflowctrl, linkmesg = 0;
1366 u32 mac_mode, lcl_adv, rmt_adv;
1367 struct tg3 *tp = netdev_priv(dev);
1368 struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1370 spin_lock_bh(&tp->lock);
1372 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1373 MAC_MODE_HALF_DUPLEX);
1375 oldflowctrl = tp->link_config.active_flowctrl;
1381 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1382 mac_mode |= MAC_MODE_PORT_MODE_MII;
1383 else if (phydev->speed == SPEED_1000 ||
1384 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
1385 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1387 mac_mode |= MAC_MODE_PORT_MODE_MII;
1389 if (phydev->duplex == DUPLEX_HALF)
1390 mac_mode |= MAC_MODE_HALF_DUPLEX;
1392 lcl_adv = tg3_advert_flowctrl_1000T(
1393 tp->link_config.flowctrl);
1396 rmt_adv = LPA_PAUSE_CAP;
1397 if (phydev->asym_pause)
1398 rmt_adv |= LPA_PAUSE_ASYM;
1401 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1403 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1405 if (mac_mode != tp->mac_mode) {
1406 tp->mac_mode = mac_mode;
1407 tw32_f(MAC_MODE, tp->mac_mode);
1411 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1412 if (phydev->speed == SPEED_10)
1414 MAC_MI_STAT_10MBPS_MODE |
1415 MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1417 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1420 if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1421 tw32(MAC_TX_LENGTHS,
1422 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1423 (6 << TX_LENGTHS_IPG_SHIFT) |
1424 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1426 tw32(MAC_TX_LENGTHS,
1427 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1428 (6 << TX_LENGTHS_IPG_SHIFT) |
1429 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1431 if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1432 (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1433 phydev->speed != tp->link_config.active_speed ||
1434 phydev->duplex != tp->link_config.active_duplex ||
1435 oldflowctrl != tp->link_config.active_flowctrl)
1438 tp->link_config.active_speed = phydev->speed;
1439 tp->link_config.active_duplex = phydev->duplex;
1441 spin_unlock_bh(&tp->lock);
1444 tg3_link_report(tp);
1447 static int tg3_phy_init(struct tg3 *tp)
1449 struct phy_device *phydev;
1451 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
1454 /* Bring the PHY back to a known state. */
1457 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1459 /* Attach the MAC to the PHY. */
1460 phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
1461 phydev->dev_flags, phydev->interface);
1462 if (IS_ERR(phydev)) {
1463 printk(KERN_ERR "%s: Could not attach to PHY\n", tp->dev->name);
1464 return PTR_ERR(phydev);
1467 /* Mask with MAC supported features. */
1468 switch (phydev->interface) {
1469 case PHY_INTERFACE_MODE_GMII:
1470 case PHY_INTERFACE_MODE_RGMII:
1471 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1472 phydev->supported &= (PHY_GBIT_FEATURES |
1474 SUPPORTED_Asym_Pause);
1478 case PHY_INTERFACE_MODE_MII:
1479 phydev->supported &= (PHY_BASIC_FEATURES |
1481 SUPPORTED_Asym_Pause);
1484 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1488 tp->tg3_flags3 |= TG3_FLG3_PHY_CONNECTED;
1490 phydev->advertising = phydev->supported;
1495 static void tg3_phy_start(struct tg3 *tp)
1497 struct phy_device *phydev;
1499 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1502 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1504 if (tp->link_config.phy_is_low_power) {
1505 tp->link_config.phy_is_low_power = 0;
1506 phydev->speed = tp->link_config.orig_speed;
1507 phydev->duplex = tp->link_config.orig_duplex;
1508 phydev->autoneg = tp->link_config.orig_autoneg;
1509 phydev->advertising = tp->link_config.orig_advertising;
1514 phy_start_aneg(phydev);
1517 static void tg3_phy_stop(struct tg3 *tp)
1519 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1522 phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1525 static void tg3_phy_fini(struct tg3 *tp)
1527 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
1528 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1529 tp->tg3_flags3 &= ~TG3_FLG3_PHY_CONNECTED;
1533 static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1535 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1536 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1539 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1543 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1546 tg3_writephy(tp, MII_TG3_FET_TEST,
1547 phytest | MII_TG3_FET_SHADOW_EN);
1548 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1550 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1552 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1553 tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1555 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1559 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1563 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
1566 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1567 tg3_phy_fet_toggle_apd(tp, enable);
1571 reg = MII_TG3_MISC_SHDW_WREN |
1572 MII_TG3_MISC_SHDW_SCR5_SEL |
1573 MII_TG3_MISC_SHDW_SCR5_LPED |
1574 MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1575 MII_TG3_MISC_SHDW_SCR5_SDTL |
1576 MII_TG3_MISC_SHDW_SCR5_C125OE;
1577 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1578 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1580 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1583 reg = MII_TG3_MISC_SHDW_WREN |
1584 MII_TG3_MISC_SHDW_APD_SEL |
1585 MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1587 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1589 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1592 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1596 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1597 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1600 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1603 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1604 u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1606 tg3_writephy(tp, MII_TG3_FET_TEST,
1607 ephy | MII_TG3_FET_SHADOW_EN);
1608 if (!tg3_readphy(tp, reg, &phy)) {
1610 phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1612 phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1613 tg3_writephy(tp, reg, phy);
1615 tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
1618 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1619 MII_TG3_AUXCTL_SHDWSEL_MISC;
1620 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1621 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1623 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1625 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1626 phy |= MII_TG3_AUXCTL_MISC_WREN;
1627 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1632 static void tg3_phy_set_wirespeed(struct tg3 *tp)
1636 if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
1639 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1640 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1641 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1642 (val | (1 << 15) | (1 << 4)));
1645 static void tg3_phy_apply_otp(struct tg3 *tp)
1654 /* Enable SM_DSP clock and tx 6dB coding. */
1655 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1656 MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1657 MII_TG3_AUXCTL_ACTL_TX_6DB;
1658 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1660 phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1661 phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1662 tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1664 phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1665 ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1666 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1668 phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1669 phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1670 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1672 phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1673 tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1675 phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1676 tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1678 phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1679 ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1680 tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1682 /* Turn off SM_DSP clock. */
1683 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1684 MII_TG3_AUXCTL_ACTL_TX_6DB;
1685 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1688 static int tg3_wait_macro_done(struct tg3 *tp)
1695 if (!tg3_readphy(tp, 0x16, &tmp32)) {
1696 if ((tmp32 & 0x1000) == 0)
1706 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1708 static const u32 test_pat[4][6] = {
1709 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1710 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1711 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1712 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1716 for (chan = 0; chan < 4; chan++) {
1719 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1720 (chan * 0x2000) | 0x0200);
1721 tg3_writephy(tp, 0x16, 0x0002);
1723 for (i = 0; i < 6; i++)
1724 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1727 tg3_writephy(tp, 0x16, 0x0202);
1728 if (tg3_wait_macro_done(tp)) {
1733 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1734 (chan * 0x2000) | 0x0200);
1735 tg3_writephy(tp, 0x16, 0x0082);
1736 if (tg3_wait_macro_done(tp)) {
1741 tg3_writephy(tp, 0x16, 0x0802);
1742 if (tg3_wait_macro_done(tp)) {
1747 for (i = 0; i < 6; i += 2) {
1750 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1751 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1752 tg3_wait_macro_done(tp)) {
1758 if (low != test_pat[chan][i] ||
1759 high != test_pat[chan][i+1]) {
1760 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1761 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1762 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1772 static int tg3_phy_reset_chanpat(struct tg3 *tp)
1776 for (chan = 0; chan < 4; chan++) {
1779 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1780 (chan * 0x2000) | 0x0200);
1781 tg3_writephy(tp, 0x16, 0x0002);
1782 for (i = 0; i < 6; i++)
1783 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1784 tg3_writephy(tp, 0x16, 0x0202);
1785 if (tg3_wait_macro_done(tp))
1792 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1794 u32 reg32, phy9_orig;
1795 int retries, do_phy_reset, err;
1801 err = tg3_bmcr_reset(tp);
1807 /* Disable transmitter and interrupt. */
1808 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32))
1812 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1814 /* Set full-duplex, 1000 mbps. */
1815 tg3_writephy(tp, MII_BMCR,
1816 BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1818 /* Set to master mode. */
1819 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1822 tg3_writephy(tp, MII_TG3_CTRL,
1823 (MII_TG3_CTRL_AS_MASTER |
1824 MII_TG3_CTRL_ENABLE_AS_MASTER));
1826 /* Enable SM_DSP_CLOCK and 6dB. */
1827 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1829 /* Block the PHY control access. */
1830 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1831 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
1833 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1836 } while (--retries);
1838 err = tg3_phy_reset_chanpat(tp);
1842 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1843 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
1845 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1846 tg3_writephy(tp, 0x16, 0x0000);
1848 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1849 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1850 /* Set Extended packet length bit for jumbo frames */
1851 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1854 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1857 tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1859 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32)) {
1861 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1868 /* This will reset the tigon3 PHY if there is no valid
1869 * link unless the FORCE argument is non-zero.
1871 static int tg3_phy_reset(struct tg3 *tp)
1877 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1880 val = tr32(GRC_MISC_CFG);
1881 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1884 err = tg3_readphy(tp, MII_BMSR, &phy_status);
1885 err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1889 if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1890 netif_carrier_off(tp->dev);
1891 tg3_link_report(tp);
1894 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1895 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1896 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1897 err = tg3_phy_reset_5703_4_5(tp);
1904 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1905 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1906 cpmuctrl = tr32(TG3_CPMU_CTRL);
1907 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1909 cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1912 err = tg3_bmcr_reset(tp);
1916 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1919 phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1920 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy);
1922 tw32(TG3_CPMU_CTRL, cpmuctrl);
1925 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
1926 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
1929 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1930 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1931 CPMU_LSPD_1000MB_MACCLK_12_5) {
1932 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1934 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1938 tg3_phy_apply_otp(tp);
1940 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
1941 tg3_phy_toggle_apd(tp, true);
1943 tg3_phy_toggle_apd(tp, false);
1946 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1947 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1948 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1949 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1950 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1951 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
1952 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1954 if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
1955 tg3_writephy(tp, 0x1c, 0x8d68);
1956 tg3_writephy(tp, 0x1c, 0x8d68);
1958 if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1959 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1960 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1961 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1962 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1963 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1964 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1965 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1966 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1968 else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1969 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1970 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1971 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1972 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1973 tg3_writephy(tp, MII_TG3_TEST1,
1974 MII_TG3_TEST1_TRIM_EN | 0x4);
1976 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
1977 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1979 /* Set Extended packet length bit (bit 14) on all chips that */
1980 /* support jumbo frames */
1981 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1982 /* Cannot do read-modify-write on 5401 */
1983 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1984 } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1987 /* Set bit 14 with read-modify-write to preserve other bits */
1988 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1989 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1990 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1993 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1994 * jumbo frames transmission.
1996 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1999 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
2000 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2001 phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
2004 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2005 /* adjust output voltage */
2006 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
2009 tg3_phy_toggle_automdix(tp, 1);
2010 tg3_phy_set_wirespeed(tp);
2014 static void tg3_frob_aux_power(struct tg3 *tp)
2016 struct tg3 *tp_peer = tp;
2018 if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
2021 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2022 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
2023 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
2024 struct net_device *dev_peer;
2026 dev_peer = pci_get_drvdata(tp->pdev_peer);
2027 /* remove_one() may have been run on the peer. */
2031 tp_peer = netdev_priv(dev_peer);
2034 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2035 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
2036 (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2037 (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
2038 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2039 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2040 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2041 (GRC_LCLCTRL_GPIO_OE0 |
2042 GRC_LCLCTRL_GPIO_OE1 |
2043 GRC_LCLCTRL_GPIO_OE2 |
2044 GRC_LCLCTRL_GPIO_OUTPUT0 |
2045 GRC_LCLCTRL_GPIO_OUTPUT1),
2047 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2048 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2049 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2050 u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2051 GRC_LCLCTRL_GPIO_OE1 |
2052 GRC_LCLCTRL_GPIO_OE2 |
2053 GRC_LCLCTRL_GPIO_OUTPUT0 |
2054 GRC_LCLCTRL_GPIO_OUTPUT1 |
2056 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2058 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2059 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2061 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2062 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2065 u32 grc_local_ctrl = 0;
2067 if (tp_peer != tp &&
2068 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2071 /* Workaround to prevent overdrawing Amps. */
2072 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2074 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2075 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2076 grc_local_ctrl, 100);
2079 /* On 5753 and variants, GPIO2 cannot be used. */
2080 no_gpio2 = tp->nic_sram_data_cfg &
2081 NIC_SRAM_DATA_CFG_NO_GPIO2;
2083 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2084 GRC_LCLCTRL_GPIO_OE1 |
2085 GRC_LCLCTRL_GPIO_OE2 |
2086 GRC_LCLCTRL_GPIO_OUTPUT1 |
2087 GRC_LCLCTRL_GPIO_OUTPUT2;
2089 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2090 GRC_LCLCTRL_GPIO_OUTPUT2);
2092 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2093 grc_local_ctrl, 100);
2095 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2097 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2098 grc_local_ctrl, 100);
2101 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2102 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2103 grc_local_ctrl, 100);
2107 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2108 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2109 if (tp_peer != tp &&
2110 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2113 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2114 (GRC_LCLCTRL_GPIO_OE1 |
2115 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2117 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2118 GRC_LCLCTRL_GPIO_OE1, 100);
2120 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2121 (GRC_LCLCTRL_GPIO_OE1 |
2122 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2127 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2129 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2131 else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411) {
2132 if (speed != SPEED_10)
2134 } else if (speed == SPEED_10)
2140 static int tg3_setup_phy(struct tg3 *, int);
2142 #define RESET_KIND_SHUTDOWN 0
2143 #define RESET_KIND_INIT 1
2144 #define RESET_KIND_SUSPEND 2
2146 static void tg3_write_sig_post_reset(struct tg3 *, int);
2147 static int tg3_halt_cpu(struct tg3 *, u32);
2149 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2153 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2154 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2155 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2156 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2159 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2160 tw32(SG_DIG_CTRL, sg_dig_ctrl);
2161 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2166 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2168 val = tr32(GRC_MISC_CFG);
2169 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2172 } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
2174 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2177 tg3_writephy(tp, MII_ADVERTISE, 0);
2178 tg3_writephy(tp, MII_BMCR,
2179 BMCR_ANENABLE | BMCR_ANRESTART);
2181 tg3_writephy(tp, MII_TG3_FET_TEST,
2182 phytest | MII_TG3_FET_SHADOW_EN);
2183 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
2184 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
2186 MII_TG3_FET_SHDW_AUXMODE4,
2189 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2192 } else if (do_low_power) {
2193 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2194 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
2196 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2197 MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2198 MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2199 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2200 MII_TG3_AUXCTL_PCTL_VREG_11V);
2203 /* The PHY should not be powered down on some chips because
2206 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2207 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2208 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2209 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
2212 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2213 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2214 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2215 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2216 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2217 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2220 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2223 /* tp->lock is held. */
2224 static int tg3_nvram_lock(struct tg3 *tp)
2226 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2229 if (tp->nvram_lock_cnt == 0) {
2230 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2231 for (i = 0; i < 8000; i++) {
2232 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2237 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2241 tp->nvram_lock_cnt++;
2246 /* tp->lock is held. */
2247 static void tg3_nvram_unlock(struct tg3 *tp)
2249 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2250 if (tp->nvram_lock_cnt > 0)
2251 tp->nvram_lock_cnt--;
2252 if (tp->nvram_lock_cnt == 0)
2253 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2257 /* tp->lock is held. */
2258 static void tg3_enable_nvram_access(struct tg3 *tp)
2260 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2261 !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2262 u32 nvaccess = tr32(NVRAM_ACCESS);
2264 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2268 /* tp->lock is held. */
2269 static void tg3_disable_nvram_access(struct tg3 *tp)
2271 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2272 !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2273 u32 nvaccess = tr32(NVRAM_ACCESS);
2275 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2279 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2280 u32 offset, u32 *val)
2285 if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2288 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2289 EEPROM_ADDR_DEVID_MASK |
2291 tw32(GRC_EEPROM_ADDR,
2293 (0 << EEPROM_ADDR_DEVID_SHIFT) |
2294 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2295 EEPROM_ADDR_ADDR_MASK) |
2296 EEPROM_ADDR_READ | EEPROM_ADDR_START);
2298 for (i = 0; i < 1000; i++) {
2299 tmp = tr32(GRC_EEPROM_ADDR);
2301 if (tmp & EEPROM_ADDR_COMPLETE)
2305 if (!(tmp & EEPROM_ADDR_COMPLETE))
2308 tmp = tr32(GRC_EEPROM_DATA);
2311 * The data will always be opposite the native endian
2312 * format. Perform a blind byteswap to compensate.
2319 #define NVRAM_CMD_TIMEOUT 10000
2321 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2325 tw32(NVRAM_CMD, nvram_cmd);
2326 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2328 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2334 if (i == NVRAM_CMD_TIMEOUT)
2340 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2342 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2343 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2344 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2345 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2346 (tp->nvram_jedecnum == JEDEC_ATMEL))
2348 addr = ((addr / tp->nvram_pagesize) <<
2349 ATMEL_AT45DB0X1B_PAGE_POS) +
2350 (addr % tp->nvram_pagesize);
2355 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2357 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2358 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2359 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2360 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2361 (tp->nvram_jedecnum == JEDEC_ATMEL))
2363 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2364 tp->nvram_pagesize) +
2365 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2370 /* NOTE: Data read in from NVRAM is byteswapped according to
2371 * the byteswapping settings for all other register accesses.
2372 * tg3 devices are BE devices, so on a BE machine, the data
2373 * returned will be exactly as it is seen in NVRAM. On a LE
2374 * machine, the 32-bit value will be byteswapped.
2376 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2380 if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2381 return tg3_nvram_read_using_eeprom(tp, offset, val);
2383 offset = tg3_nvram_phys_addr(tp, offset);
2385 if (offset > NVRAM_ADDR_MSK)
2388 ret = tg3_nvram_lock(tp);
2392 tg3_enable_nvram_access(tp);
2394 tw32(NVRAM_ADDR, offset);
2395 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2396 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2399 *val = tr32(NVRAM_RDDATA);
2401 tg3_disable_nvram_access(tp);
2403 tg3_nvram_unlock(tp);
2408 /* Ensures NVRAM data is in bytestream format. */
2409 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
2412 int res = tg3_nvram_read(tp, offset, &v);
2414 *val = cpu_to_be32(v);
2418 /* tp->lock is held. */
2419 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2421 u32 addr_high, addr_low;
2424 addr_high = ((tp->dev->dev_addr[0] << 8) |
2425 tp->dev->dev_addr[1]);
2426 addr_low = ((tp->dev->dev_addr[2] << 24) |
2427 (tp->dev->dev_addr[3] << 16) |
2428 (tp->dev->dev_addr[4] << 8) |
2429 (tp->dev->dev_addr[5] << 0));
2430 for (i = 0; i < 4; i++) {
2431 if (i == 1 && skip_mac_1)
2433 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2434 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2437 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2438 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2439 for (i = 0; i < 12; i++) {
2440 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2441 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2445 addr_high = (tp->dev->dev_addr[0] +
2446 tp->dev->dev_addr[1] +
2447 tp->dev->dev_addr[2] +
2448 tp->dev->dev_addr[3] +
2449 tp->dev->dev_addr[4] +
2450 tp->dev->dev_addr[5]) &
2451 TX_BACKOFF_SEED_MASK;
2452 tw32(MAC_TX_BACKOFF_SEED, addr_high);
2455 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
2458 bool device_should_wake, do_low_power;
2460 /* Make sure register accesses (indirect or otherwise)
2461 * will function correctly.
2463 pci_write_config_dword(tp->pdev,
2464 TG3PCI_MISC_HOST_CTRL,
2465 tp->misc_host_ctrl);
2469 pci_enable_wake(tp->pdev, state, false);
2470 pci_set_power_state(tp->pdev, PCI_D0);
2472 /* Switch out of Vaux if it is a NIC */
2473 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
2474 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
2484 printk(KERN_ERR PFX "%s: Invalid power state (D%d) requested\n",
2485 tp->dev->name, state);
2489 /* Restore the CLKREQ setting. */
2490 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2493 pci_read_config_word(tp->pdev,
2494 tp->pcie_cap + PCI_EXP_LNKCTL,
2496 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2497 pci_write_config_word(tp->pdev,
2498 tp->pcie_cap + PCI_EXP_LNKCTL,
2502 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2503 tw32(TG3PCI_MISC_HOST_CTRL,
2504 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2506 device_should_wake = pci_pme_capable(tp->pdev, state) &&
2507 device_may_wakeup(&tp->pdev->dev) &&
2508 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2510 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
2511 do_low_power = false;
2512 if ((tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) &&
2513 !tp->link_config.phy_is_low_power) {
2514 struct phy_device *phydev;
2515 u32 phyid, advertising;
2517 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
2519 tp->link_config.phy_is_low_power = 1;
2521 tp->link_config.orig_speed = phydev->speed;
2522 tp->link_config.orig_duplex = phydev->duplex;
2523 tp->link_config.orig_autoneg = phydev->autoneg;
2524 tp->link_config.orig_advertising = phydev->advertising;
2526 advertising = ADVERTISED_TP |
2528 ADVERTISED_Autoneg |
2529 ADVERTISED_10baseT_Half;
2531 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2532 device_should_wake) {
2533 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2535 ADVERTISED_100baseT_Half |
2536 ADVERTISED_100baseT_Full |
2537 ADVERTISED_10baseT_Full;
2539 advertising |= ADVERTISED_10baseT_Full;
2542 phydev->advertising = advertising;
2544 phy_start_aneg(phydev);
2546 phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2547 if (phyid != TG3_PHY_ID_BCMAC131) {
2548 phyid &= TG3_PHY_OUI_MASK;
2549 if (phyid == TG3_PHY_OUI_1 ||
2550 phyid == TG3_PHY_OUI_2 ||
2551 phyid == TG3_PHY_OUI_3)
2552 do_low_power = true;
2556 do_low_power = true;
2558 if (tp->link_config.phy_is_low_power == 0) {
2559 tp->link_config.phy_is_low_power = 1;
2560 tp->link_config.orig_speed = tp->link_config.speed;
2561 tp->link_config.orig_duplex = tp->link_config.duplex;
2562 tp->link_config.orig_autoneg = tp->link_config.autoneg;
2565 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
2566 tp->link_config.speed = SPEED_10;
2567 tp->link_config.duplex = DUPLEX_HALF;
2568 tp->link_config.autoneg = AUTONEG_ENABLE;
2569 tg3_setup_phy(tp, 0);
2573 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2576 val = tr32(GRC_VCPU_EXT_CTRL);
2577 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2578 } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2582 for (i = 0; i < 200; i++) {
2583 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2584 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2589 if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2590 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2591 WOL_DRV_STATE_SHUTDOWN |
2595 if (device_should_wake) {
2598 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
2600 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2604 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
2605 mac_mode = MAC_MODE_PORT_MODE_GMII;
2607 mac_mode = MAC_MODE_PORT_MODE_MII;
2609 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2610 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2612 u32 speed = (tp->tg3_flags &
2613 TG3_FLAG_WOL_SPEED_100MB) ?
2614 SPEED_100 : SPEED_10;
2615 if (tg3_5700_link_polarity(tp, speed))
2616 mac_mode |= MAC_MODE_LINK_POLARITY;
2618 mac_mode &= ~MAC_MODE_LINK_POLARITY;
2621 mac_mode = MAC_MODE_PORT_MODE_TBI;
2624 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
2625 tw32(MAC_LED_CTRL, tp->led_ctrl);
2627 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2628 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2629 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2630 ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2631 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2632 mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
2634 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2635 mac_mode |= tp->mac_mode &
2636 (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
2637 if (mac_mode & MAC_MODE_APE_TX_EN)
2638 mac_mode |= MAC_MODE_TDE_ENABLE;
2641 tw32_f(MAC_MODE, mac_mode);
2644 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2648 if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2649 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2650 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2653 base_val = tp->pci_clock_ctrl;
2654 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2655 CLOCK_CTRL_TXCLK_DISABLE);
2657 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2658 CLOCK_CTRL_PWRDOWN_PLL133, 40);
2659 } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
2660 (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
2661 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
2663 } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2664 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2665 u32 newbits1, newbits2;
2667 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2668 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2669 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2670 CLOCK_CTRL_TXCLK_DISABLE |
2672 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2673 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2674 newbits1 = CLOCK_CTRL_625_CORE;
2675 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2677 newbits1 = CLOCK_CTRL_ALTCLK;
2678 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2681 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2684 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2687 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2690 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2691 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2692 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2693 CLOCK_CTRL_TXCLK_DISABLE |
2694 CLOCK_CTRL_44MHZ_CORE);
2696 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2699 tw32_wait_f(TG3PCI_CLOCK_CTRL,
2700 tp->pci_clock_ctrl | newbits3, 40);
2704 if (!(device_should_wake) &&
2705 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
2706 tg3_power_down_phy(tp, do_low_power);
2708 tg3_frob_aux_power(tp);
2710 /* Workaround for unstable PLL clock */
2711 if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2712 (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2713 u32 val = tr32(0x7d00);
2715 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2717 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2720 err = tg3_nvram_lock(tp);
2721 tg3_halt_cpu(tp, RX_CPU_BASE);
2723 tg3_nvram_unlock(tp);
2727 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2729 if (device_should_wake)
2730 pci_enable_wake(tp->pdev, state, true);
2732 /* Finally, set the new power state. */
2733 pci_set_power_state(tp->pdev, state);
2738 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2740 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2741 case MII_TG3_AUX_STAT_10HALF:
2743 *duplex = DUPLEX_HALF;
2746 case MII_TG3_AUX_STAT_10FULL:
2748 *duplex = DUPLEX_FULL;
2751 case MII_TG3_AUX_STAT_100HALF:
2753 *duplex = DUPLEX_HALF;
2756 case MII_TG3_AUX_STAT_100FULL:
2758 *duplex = DUPLEX_FULL;
2761 case MII_TG3_AUX_STAT_1000HALF:
2762 *speed = SPEED_1000;
2763 *duplex = DUPLEX_HALF;
2766 case MII_TG3_AUX_STAT_1000FULL:
2767 *speed = SPEED_1000;
2768 *duplex = DUPLEX_FULL;
2772 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
2773 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2775 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2779 *speed = SPEED_INVALID;
2780 *duplex = DUPLEX_INVALID;
2785 static void tg3_phy_copper_begin(struct tg3 *tp)
2790 if (tp->link_config.phy_is_low_power) {
2791 /* Entering low power mode. Disable gigabit and
2792 * 100baseT advertisements.
2794 tg3_writephy(tp, MII_TG3_CTRL, 0);
2796 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2797 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2798 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2799 new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2801 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2802 } else if (tp->link_config.speed == SPEED_INVALID) {
2803 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
2804 tp->link_config.advertising &=
2805 ~(ADVERTISED_1000baseT_Half |
2806 ADVERTISED_1000baseT_Full);
2808 new_adv = ADVERTISE_CSMA;
2809 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2810 new_adv |= ADVERTISE_10HALF;
2811 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2812 new_adv |= ADVERTISE_10FULL;
2813 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2814 new_adv |= ADVERTISE_100HALF;
2815 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2816 new_adv |= ADVERTISE_100FULL;
2818 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2820 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2822 if (tp->link_config.advertising &
2823 (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2825 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2826 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2827 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2828 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2829 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
2830 (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2831 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2832 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2833 MII_TG3_CTRL_ENABLE_AS_MASTER);
2834 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2836 tg3_writephy(tp, MII_TG3_CTRL, 0);
2839 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2840 new_adv |= ADVERTISE_CSMA;
2842 /* Asking for a specific link mode. */
2843 if (tp->link_config.speed == SPEED_1000) {
2844 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2846 if (tp->link_config.duplex == DUPLEX_FULL)
2847 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2849 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2850 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2851 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2852 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2853 MII_TG3_CTRL_ENABLE_AS_MASTER);
2855 if (tp->link_config.speed == SPEED_100) {
2856 if (tp->link_config.duplex == DUPLEX_FULL)
2857 new_adv |= ADVERTISE_100FULL;
2859 new_adv |= ADVERTISE_100HALF;
2861 if (tp->link_config.duplex == DUPLEX_FULL)
2862 new_adv |= ADVERTISE_10FULL;
2864 new_adv |= ADVERTISE_10HALF;
2866 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2871 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2874 if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2875 tp->link_config.speed != SPEED_INVALID) {
2876 u32 bmcr, orig_bmcr;
2878 tp->link_config.active_speed = tp->link_config.speed;
2879 tp->link_config.active_duplex = tp->link_config.duplex;
2882 switch (tp->link_config.speed) {
2888 bmcr |= BMCR_SPEED100;
2892 bmcr |= TG3_BMCR_SPEED1000;
2896 if (tp->link_config.duplex == DUPLEX_FULL)
2897 bmcr |= BMCR_FULLDPLX;
2899 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2900 (bmcr != orig_bmcr)) {
2901 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2902 for (i = 0; i < 1500; i++) {
2906 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2907 tg3_readphy(tp, MII_BMSR, &tmp))
2909 if (!(tmp & BMSR_LSTATUS)) {
2914 tg3_writephy(tp, MII_BMCR, bmcr);
2918 tg3_writephy(tp, MII_BMCR,
2919 BMCR_ANENABLE | BMCR_ANRESTART);
2923 static int tg3_init_5401phy_dsp(struct tg3 *tp)
2927 /* Turn off tap power management. */
2928 /* Set Extended packet length bit */
2929 err = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2931 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
2932 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
2934 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
2935 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
2937 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2938 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
2940 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2941 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
2943 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2944 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
2951 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
2953 u32 adv_reg, all_mask = 0;
2955 if (mask & ADVERTISED_10baseT_Half)
2956 all_mask |= ADVERTISE_10HALF;
2957 if (mask & ADVERTISED_10baseT_Full)
2958 all_mask |= ADVERTISE_10FULL;
2959 if (mask & ADVERTISED_100baseT_Half)
2960 all_mask |= ADVERTISE_100HALF;
2961 if (mask & ADVERTISED_100baseT_Full)
2962 all_mask |= ADVERTISE_100FULL;
2964 if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
2967 if ((adv_reg & all_mask) != all_mask)
2969 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
2973 if (mask & ADVERTISED_1000baseT_Half)
2974 all_mask |= ADVERTISE_1000HALF;
2975 if (mask & ADVERTISED_1000baseT_Full)
2976 all_mask |= ADVERTISE_1000FULL;
2978 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
2981 if ((tg3_ctrl & all_mask) != all_mask)
2987 static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
2991 if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
2994 curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2995 reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2997 if (tp->link_config.active_duplex == DUPLEX_FULL) {
2998 if (curadv != reqadv)
3001 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
3002 tg3_readphy(tp, MII_LPA, rmtadv);
3004 /* Reprogram the advertisement register, even if it
3005 * does not affect the current link. If the link
3006 * gets renegotiated in the future, we can save an
3007 * additional renegotiation cycle by advertising
3008 * it correctly in the first place.
3010 if (curadv != reqadv) {
3011 *lcladv &= ~(ADVERTISE_PAUSE_CAP |
3012 ADVERTISE_PAUSE_ASYM);
3013 tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
3020 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
3022 int current_link_up;
3024 u32 lcl_adv, rmt_adv;
3032 (MAC_STATUS_SYNC_CHANGED |
3033 MAC_STATUS_CFG_CHANGED |
3034 MAC_STATUS_MI_COMPLETION |
3035 MAC_STATUS_LNKSTATE_CHANGED));
3038 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
3040 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
3044 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
3046 /* Some third-party PHYs need to be reset on link going
3049 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3050 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
3051 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
3052 netif_carrier_ok(tp->dev)) {
3053 tg3_readphy(tp, MII_BMSR, &bmsr);
3054 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3055 !(bmsr & BMSR_LSTATUS))
3061 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
3062 tg3_readphy(tp, MII_BMSR, &bmsr);
3063 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
3064 !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
3067 if (!(bmsr & BMSR_LSTATUS)) {
3068 err = tg3_init_5401phy_dsp(tp);
3072 tg3_readphy(tp, MII_BMSR, &bmsr);
3073 for (i = 0; i < 1000; i++) {
3075 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3076 (bmsr & BMSR_LSTATUS)) {
3082 if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
3083 !(bmsr & BMSR_LSTATUS) &&
3084 tp->link_config.active_speed == SPEED_1000) {
3085 err = tg3_phy_reset(tp);
3087 err = tg3_init_5401phy_dsp(tp);
3092 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3093 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3094 /* 5701 {A0,B0} CRC bug workaround */
3095 tg3_writephy(tp, 0x15, 0x0a75);
3096 tg3_writephy(tp, 0x1c, 0x8c68);
3097 tg3_writephy(tp, 0x1c, 0x8d68);
3098 tg3_writephy(tp, 0x1c, 0x8c68);
3101 /* Clear pending interrupts... */
3102 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3103 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3105 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
3106 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
3107 else if (!(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
3108 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3110 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3111 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3112 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3113 tg3_writephy(tp, MII_TG3_EXT_CTRL,
3114 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3116 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3119 current_link_up = 0;
3120 current_speed = SPEED_INVALID;
3121 current_duplex = DUPLEX_INVALID;
3123 if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
3126 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3127 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3128 if (!(val & (1 << 10))) {
3130 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3136 for (i = 0; i < 100; i++) {
3137 tg3_readphy(tp, MII_BMSR, &bmsr);
3138 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3139 (bmsr & BMSR_LSTATUS))
3144 if (bmsr & BMSR_LSTATUS) {
3147 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3148 for (i = 0; i < 2000; i++) {
3150 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3155 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3160 for (i = 0; i < 200; i++) {
3161 tg3_readphy(tp, MII_BMCR, &bmcr);
3162 if (tg3_readphy(tp, MII_BMCR, &bmcr))
3164 if (bmcr && bmcr != 0x7fff)
3172 tp->link_config.active_speed = current_speed;
3173 tp->link_config.active_duplex = current_duplex;
3175 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3176 if ((bmcr & BMCR_ANENABLE) &&
3177 tg3_copper_is_advertising_all(tp,
3178 tp->link_config.advertising)) {
3179 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3181 current_link_up = 1;
3184 if (!(bmcr & BMCR_ANENABLE) &&
3185 tp->link_config.speed == current_speed &&
3186 tp->link_config.duplex == current_duplex &&
3187 tp->link_config.flowctrl ==
3188 tp->link_config.active_flowctrl) {
3189 current_link_up = 1;
3193 if (current_link_up == 1 &&
3194 tp->link_config.active_duplex == DUPLEX_FULL)
3195 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
3199 if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
3202 tg3_phy_copper_begin(tp);
3204 tg3_readphy(tp, MII_BMSR, &tmp);
3205 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
3206 (tmp & BMSR_LSTATUS))
3207 current_link_up = 1;
3210 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3211 if (current_link_up == 1) {
3212 if (tp->link_config.active_speed == SPEED_100 ||
3213 tp->link_config.active_speed == SPEED_10)
3214 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3216 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3217 } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)
3218 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3220 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3222 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3223 if (tp->link_config.active_duplex == DUPLEX_HALF)
3224 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3226 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
3227 if (current_link_up == 1 &&
3228 tg3_5700_link_polarity(tp, tp->link_config.active_speed))
3229 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
3231 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
3234 /* ??? Without this setting Netgear GA302T PHY does not
3235 * ??? send/receive packets...
3237 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
3238 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3239 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3240 tw32_f(MAC_MI_MODE, tp->mi_mode);
3244 tw32_f(MAC_MODE, tp->mac_mode);
3247 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3248 /* Polled via timer. */
3249 tw32_f(MAC_EVENT, 0);
3251 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3255 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3256 current_link_up == 1 &&
3257 tp->link_config.active_speed == SPEED_1000 &&
3258 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3259 (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3262 (MAC_STATUS_SYNC_CHANGED |
3263 MAC_STATUS_CFG_CHANGED));
3266 NIC_SRAM_FIRMWARE_MBOX,
3267 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3270 /* Prevent send BD corruption. */
3271 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3272 u16 oldlnkctl, newlnkctl;
3274 pci_read_config_word(tp->pdev,
3275 tp->pcie_cap + PCI_EXP_LNKCTL,
3277 if (tp->link_config.active_speed == SPEED_100 ||
3278 tp->link_config.active_speed == SPEED_10)
3279 newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3281 newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3282 if (newlnkctl != oldlnkctl)
3283 pci_write_config_word(tp->pdev,
3284 tp->pcie_cap + PCI_EXP_LNKCTL,
3288 if (current_link_up != netif_carrier_ok(tp->dev)) {
3289 if (current_link_up)
3290 netif_carrier_on(tp->dev);
3292 netif_carrier_off(tp->dev);
3293 tg3_link_report(tp);
3299 struct tg3_fiber_aneginfo {
3301 #define ANEG_STATE_UNKNOWN 0
3302 #define ANEG_STATE_AN_ENABLE 1
3303 #define ANEG_STATE_RESTART_INIT 2
3304 #define ANEG_STATE_RESTART 3
3305 #define ANEG_STATE_DISABLE_LINK_OK 4
3306 #define ANEG_STATE_ABILITY_DETECT_INIT 5
3307 #define ANEG_STATE_ABILITY_DETECT 6
3308 #define ANEG_STATE_ACK_DETECT_INIT 7
3309 #define ANEG_STATE_ACK_DETECT 8
3310 #define ANEG_STATE_COMPLETE_ACK_INIT 9
3311 #define ANEG_STATE_COMPLETE_ACK 10
3312 #define ANEG_STATE_IDLE_DETECT_INIT 11
3313 #define ANEG_STATE_IDLE_DETECT 12
3314 #define ANEG_STATE_LINK_OK 13
3315 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
3316 #define ANEG_STATE_NEXT_PAGE_WAIT 15
3319 #define MR_AN_ENABLE 0x00000001
3320 #define MR_RESTART_AN 0x00000002
3321 #define MR_AN_COMPLETE 0x00000004
3322 #define MR_PAGE_RX 0x00000008
3323 #define MR_NP_LOADED 0x00000010
3324 #define MR_TOGGLE_TX 0x00000020
3325 #define MR_LP_ADV_FULL_DUPLEX 0x00000040
3326 #define MR_LP_ADV_HALF_DUPLEX 0x00000080
3327 #define MR_LP_ADV_SYM_PAUSE 0x00000100
3328 #define MR_LP_ADV_ASYM_PAUSE 0x00000200
3329 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3330 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3331 #define MR_LP_ADV_NEXT_PAGE 0x00001000
3332 #define MR_TOGGLE_RX 0x00002000
3333 #define MR_NP_RX 0x00004000
3335 #define MR_LINK_OK 0x80000000
3337 unsigned long link_time, cur_time;
3339 u32 ability_match_cfg;
3340 int ability_match_count;
3342 char ability_match, idle_match, ack_match;
3344 u32 txconfig, rxconfig;
3345 #define ANEG_CFG_NP 0x00000080
3346 #define ANEG_CFG_ACK 0x00000040
3347 #define ANEG_CFG_RF2 0x00000020
3348 #define ANEG_CFG_RF1 0x00000010
3349 #define ANEG_CFG_PS2 0x00000001
3350 #define ANEG_CFG_PS1 0x00008000
3351 #define ANEG_CFG_HD 0x00004000
3352 #define ANEG_CFG_FD 0x00002000
3353 #define ANEG_CFG_INVAL 0x00001f06
3358 #define ANEG_TIMER_ENAB 2
3359 #define ANEG_FAILED -1
3361 #define ANEG_STATE_SETTLE_TIME 10000
3363 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3364 struct tg3_fiber_aneginfo *ap)
3367 unsigned long delta;
3371 if (ap->state == ANEG_STATE_UNKNOWN) {
3375 ap->ability_match_cfg = 0;
3376 ap->ability_match_count = 0;
3377 ap->ability_match = 0;
3383 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3384 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3386 if (rx_cfg_reg != ap->ability_match_cfg) {
3387 ap->ability_match_cfg = rx_cfg_reg;
3388 ap->ability_match = 0;
3389 ap->ability_match_count = 0;
3391 if (++ap->ability_match_count > 1) {
3392 ap->ability_match = 1;
3393 ap->ability_match_cfg = rx_cfg_reg;
3396 if (rx_cfg_reg & ANEG_CFG_ACK)
3404 ap->ability_match_cfg = 0;
3405 ap->ability_match_count = 0;
3406 ap->ability_match = 0;
3412 ap->rxconfig = rx_cfg_reg;
3416 case ANEG_STATE_UNKNOWN:
3417 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3418 ap->state = ANEG_STATE_AN_ENABLE;
3421 case ANEG_STATE_AN_ENABLE:
3422 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3423 if (ap->flags & MR_AN_ENABLE) {
3426 ap->ability_match_cfg = 0;
3427 ap->ability_match_count = 0;
3428 ap->ability_match = 0;
3432 ap->state = ANEG_STATE_RESTART_INIT;
3434 ap->state = ANEG_STATE_DISABLE_LINK_OK;
3438 case ANEG_STATE_RESTART_INIT:
3439 ap->link_time = ap->cur_time;
3440 ap->flags &= ~(MR_NP_LOADED);
3442 tw32(MAC_TX_AUTO_NEG, 0);
3443 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3444 tw32_f(MAC_MODE, tp->mac_mode);
3447 ret = ANEG_TIMER_ENAB;
3448 ap->state = ANEG_STATE_RESTART;
3451 case ANEG_STATE_RESTART:
3452 delta = ap->cur_time - ap->link_time;
3453 if (delta > ANEG_STATE_SETTLE_TIME) {
3454 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3456 ret = ANEG_TIMER_ENAB;
3460 case ANEG_STATE_DISABLE_LINK_OK:
3464 case ANEG_STATE_ABILITY_DETECT_INIT:
3465 ap->flags &= ~(MR_TOGGLE_TX);
3466 ap->txconfig = ANEG_CFG_FD;
3467 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3468 if (flowctrl & ADVERTISE_1000XPAUSE)
3469 ap->txconfig |= ANEG_CFG_PS1;
3470 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3471 ap->txconfig |= ANEG_CFG_PS2;
3472 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3473 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3474 tw32_f(MAC_MODE, tp->mac_mode);
3477 ap->state = ANEG_STATE_ABILITY_DETECT;
3480 case ANEG_STATE_ABILITY_DETECT:
3481 if (ap->ability_match != 0 && ap->rxconfig != 0) {
3482 ap->state = ANEG_STATE_ACK_DETECT_INIT;
3486 case ANEG_STATE_ACK_DETECT_INIT:
3487 ap->txconfig |= ANEG_CFG_ACK;
3488 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3489 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3490 tw32_f(MAC_MODE, tp->mac_mode);
3493 ap->state = ANEG_STATE_ACK_DETECT;
3496 case ANEG_STATE_ACK_DETECT:
3497 if (ap->ack_match != 0) {
3498 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3499 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3500 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3502 ap->state = ANEG_STATE_AN_ENABLE;
3504 } else if (ap->ability_match != 0 &&
3505 ap->rxconfig == 0) {
3506 ap->state = ANEG_STATE_AN_ENABLE;
3510 case ANEG_STATE_COMPLETE_ACK_INIT:
3511 if (ap->rxconfig & ANEG_CFG_INVAL) {
3515 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3516 MR_LP_ADV_HALF_DUPLEX |
3517 MR_LP_ADV_SYM_PAUSE |
3518 MR_LP_ADV_ASYM_PAUSE |
3519 MR_LP_ADV_REMOTE_FAULT1 |
3520 MR_LP_ADV_REMOTE_FAULT2 |
3521 MR_LP_ADV_NEXT_PAGE |
3524 if (ap->rxconfig & ANEG_CFG_FD)
3525 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3526 if (ap->rxconfig & ANEG_CFG_HD)
3527 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3528 if (ap->rxconfig & ANEG_CFG_PS1)
3529 ap->flags |= MR_LP_ADV_SYM_PAUSE;
3530 if (ap->rxconfig & ANEG_CFG_PS2)
3531 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3532 if (ap->rxconfig & ANEG_CFG_RF1)
3533 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3534 if (ap->rxconfig & ANEG_CFG_RF2)
3535 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3536 if (ap->rxconfig & ANEG_CFG_NP)
3537 ap->flags |= MR_LP_ADV_NEXT_PAGE;
3539 ap->link_time = ap->cur_time;
3541 ap->flags ^= (MR_TOGGLE_TX);
3542 if (ap->rxconfig & 0x0008)
3543 ap->flags |= MR_TOGGLE_RX;
3544 if (ap->rxconfig & ANEG_CFG_NP)
3545 ap->flags |= MR_NP_RX;
3546 ap->flags |= MR_PAGE_RX;
3548 ap->state = ANEG_STATE_COMPLETE_ACK;
3549 ret = ANEG_TIMER_ENAB;
3552 case ANEG_STATE_COMPLETE_ACK:
3553 if (ap->ability_match != 0 &&
3554 ap->rxconfig == 0) {
3555 ap->state = ANEG_STATE_AN_ENABLE;
3558 delta = ap->cur_time - ap->link_time;
3559 if (delta > ANEG_STATE_SETTLE_TIME) {
3560 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3561 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3563 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3564 !(ap->flags & MR_NP_RX)) {
3565 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3573 case ANEG_STATE_IDLE_DETECT_INIT:
3574 ap->link_time = ap->cur_time;
3575 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3576 tw32_f(MAC_MODE, tp->mac_mode);
3579 ap->state = ANEG_STATE_IDLE_DETECT;
3580 ret = ANEG_TIMER_ENAB;
3583 case ANEG_STATE_IDLE_DETECT:
3584 if (ap->ability_match != 0 &&
3585 ap->rxconfig == 0) {
3586 ap->state = ANEG_STATE_AN_ENABLE;
3589 delta = ap->cur_time - ap->link_time;
3590 if (delta > ANEG_STATE_SETTLE_TIME) {
3591 /* XXX another gem from the Broadcom driver :( */
3592 ap->state = ANEG_STATE_LINK_OK;
3596 case ANEG_STATE_LINK_OK:
3597 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3601 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3602 /* ??? unimplemented */
3605 case ANEG_STATE_NEXT_PAGE_WAIT:
3606 /* ??? unimplemented */
3617 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
3620 struct tg3_fiber_aneginfo aninfo;
3621 int status = ANEG_FAILED;
3625 tw32_f(MAC_TX_AUTO_NEG, 0);
3627 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3628 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3631 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3634 memset(&aninfo, 0, sizeof(aninfo));
3635 aninfo.flags |= MR_AN_ENABLE;
3636 aninfo.state = ANEG_STATE_UNKNOWN;
3637 aninfo.cur_time = 0;
3639 while (++tick < 195000) {
3640 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3641 if (status == ANEG_DONE || status == ANEG_FAILED)
3647 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3648 tw32_f(MAC_MODE, tp->mac_mode);
3651 *txflags = aninfo.txconfig;
3652 *rxflags = aninfo.flags;
3654 if (status == ANEG_DONE &&
3655 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3656 MR_LP_ADV_FULL_DUPLEX)))
3662 static void tg3_init_bcm8002(struct tg3 *tp)
3664 u32 mac_status = tr32(MAC_STATUS);
3667 /* Reset when initting first time or we have a link. */
3668 if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3669 !(mac_status & MAC_STATUS_PCS_SYNCED))
3672 /* Set PLL lock range. */
3673 tg3_writephy(tp, 0x16, 0x8007);
3676 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3678 /* Wait for reset to complete. */
3679 /* XXX schedule_timeout() ... */
3680 for (i = 0; i < 500; i++)
3683 /* Config mode; select PMA/Ch 1 regs. */
3684 tg3_writephy(tp, 0x10, 0x8411);
3686 /* Enable auto-lock and comdet, select txclk for tx. */
3687 tg3_writephy(tp, 0x11, 0x0a10);
3689 tg3_writephy(tp, 0x18, 0x00a0);
3690 tg3_writephy(tp, 0x16, 0x41ff);
3692 /* Assert and deassert POR. */
3693 tg3_writephy(tp, 0x13, 0x0400);
3695 tg3_writephy(tp, 0x13, 0x0000);
3697 tg3_writephy(tp, 0x11, 0x0a50);
3699 tg3_writephy(tp, 0x11, 0x0a10);
3701 /* Wait for signal to stabilize */
3702 /* XXX schedule_timeout() ... */
3703 for (i = 0; i < 15000; i++)
3706 /* Deselect the channel register so we can read the PHYID
3709 tg3_writephy(tp, 0x10, 0x8011);
3712 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3715 u32 sg_dig_ctrl, sg_dig_status;
3716 u32 serdes_cfg, expected_sg_dig_ctrl;
3717 int workaround, port_a;
3718 int current_link_up;
3721 expected_sg_dig_ctrl = 0;
3724 current_link_up = 0;
3726 if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3727 tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3729 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3732 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3733 /* preserve bits 20-23 for voltage regulator */
3734 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3737 sg_dig_ctrl = tr32(SG_DIG_CTRL);
3739 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
3740 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
3742 u32 val = serdes_cfg;
3748 tw32_f(MAC_SERDES_CFG, val);
3751 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3753 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3754 tg3_setup_flow_control(tp, 0, 0);
3755 current_link_up = 1;
3760 /* Want auto-negotiation. */
3761 expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
3763 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3764 if (flowctrl & ADVERTISE_1000XPAUSE)
3765 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3766 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3767 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
3769 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3770 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
3771 tp->serdes_counter &&
3772 ((mac_status & (MAC_STATUS_PCS_SYNCED |
3773 MAC_STATUS_RCVD_CFG)) ==
3774 MAC_STATUS_PCS_SYNCED)) {
3775 tp->serdes_counter--;
3776 current_link_up = 1;
3781 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
3782 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
3784 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3786 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3787 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3788 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3789 MAC_STATUS_SIGNAL_DET)) {
3790 sg_dig_status = tr32(SG_DIG_STATUS);
3791 mac_status = tr32(MAC_STATUS);
3793 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
3794 (mac_status & MAC_STATUS_PCS_SYNCED)) {
3795 u32 local_adv = 0, remote_adv = 0;
3797 if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3798 local_adv |= ADVERTISE_1000XPAUSE;
3799 if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3800 local_adv |= ADVERTISE_1000XPSE_ASYM;
3802 if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
3803 remote_adv |= LPA_1000XPAUSE;
3804 if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
3805 remote_adv |= LPA_1000XPAUSE_ASYM;
3807 tg3_setup_flow_control(tp, local_adv, remote_adv);
3808 current_link_up = 1;
3809 tp->serdes_counter = 0;
3810 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3811 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3812 if (tp->serdes_counter)
3813 tp->serdes_counter--;
3816 u32 val = serdes_cfg;
3823 tw32_f(MAC_SERDES_CFG, val);
3826 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3829 /* Link parallel detection - link is up */
3830 /* only if we have PCS_SYNC and not */
3831 /* receiving config code words */
3832 mac_status = tr32(MAC_STATUS);
3833 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3834 !(mac_status & MAC_STATUS_RCVD_CFG)) {
3835 tg3_setup_flow_control(tp, 0, 0);
3836 current_link_up = 1;
3838 TG3_FLG2_PARALLEL_DETECT;
3839 tp->serdes_counter =
3840 SERDES_PARALLEL_DET_TIMEOUT;
3842 goto restart_autoneg;
3846 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3847 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3851 return current_link_up;
3854 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3856 int current_link_up = 0;
3858 if (!(mac_status & MAC_STATUS_PCS_SYNCED))
3861 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3862 u32 txflags, rxflags;
3865 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3866 u32 local_adv = 0, remote_adv = 0;
3868 if (txflags & ANEG_CFG_PS1)
3869 local_adv |= ADVERTISE_1000XPAUSE;
3870 if (txflags & ANEG_CFG_PS2)
3871 local_adv |= ADVERTISE_1000XPSE_ASYM;
3873 if (rxflags & MR_LP_ADV_SYM_PAUSE)
3874 remote_adv |= LPA_1000XPAUSE;
3875 if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3876 remote_adv |= LPA_1000XPAUSE_ASYM;
3878 tg3_setup_flow_control(tp, local_adv, remote_adv);
3880 current_link_up = 1;
3882 for (i = 0; i < 30; i++) {
3885 (MAC_STATUS_SYNC_CHANGED |
3886 MAC_STATUS_CFG_CHANGED));
3888 if ((tr32(MAC_STATUS) &
3889 (MAC_STATUS_SYNC_CHANGED |
3890 MAC_STATUS_CFG_CHANGED)) == 0)
3894 mac_status = tr32(MAC_STATUS);
3895 if (current_link_up == 0 &&
3896 (mac_status & MAC_STATUS_PCS_SYNCED) &&
3897 !(mac_status & MAC_STATUS_RCVD_CFG))
3898 current_link_up = 1;
3900 tg3_setup_flow_control(tp, 0, 0);
3902 /* Forcing 1000FD link up. */
3903 current_link_up = 1;
3905 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3908 tw32_f(MAC_MODE, tp->mac_mode);
3913 return current_link_up;
3916 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3919 u16 orig_active_speed;
3920 u8 orig_active_duplex;
3922 int current_link_up;
3925 orig_pause_cfg = tp->link_config.active_flowctrl;
3926 orig_active_speed = tp->link_config.active_speed;
3927 orig_active_duplex = tp->link_config.active_duplex;
3929 if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3930 netif_carrier_ok(tp->dev) &&
3931 (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3932 mac_status = tr32(MAC_STATUS);
3933 mac_status &= (MAC_STATUS_PCS_SYNCED |
3934 MAC_STATUS_SIGNAL_DET |
3935 MAC_STATUS_CFG_CHANGED |
3936 MAC_STATUS_RCVD_CFG);
3937 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3938 MAC_STATUS_SIGNAL_DET)) {
3939 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3940 MAC_STATUS_CFG_CHANGED));
3945 tw32_f(MAC_TX_AUTO_NEG, 0);
3947 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
3948 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
3949 tw32_f(MAC_MODE, tp->mac_mode);
3952 if (tp->phy_id == PHY_ID_BCM8002)
3953 tg3_init_bcm8002(tp);
3955 /* Enable link change event even when serdes polling. */
3956 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3959 current_link_up = 0;
3960 mac_status = tr32(MAC_STATUS);
3962 if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
3963 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
3965 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
3967 tp->napi[0].hw_status->status =
3968 (SD_STATUS_UPDATED |
3969 (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
3971 for (i = 0; i < 100; i++) {
3972 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3973 MAC_STATUS_CFG_CHANGED));
3975 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3976 MAC_STATUS_CFG_CHANGED |
3977 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
3981 mac_status = tr32(MAC_STATUS);
3982 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
3983 current_link_up = 0;
3984 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
3985 tp->serdes_counter == 0) {
3986 tw32_f(MAC_MODE, (tp->mac_mode |
3987 MAC_MODE_SEND_CONFIGS));
3989 tw32_f(MAC_MODE, tp->mac_mode);
3993 if (current_link_up == 1) {
3994 tp->link_config.active_speed = SPEED_1000;
3995 tp->link_config.active_duplex = DUPLEX_FULL;
3996 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3997 LED_CTRL_LNKLED_OVERRIDE |
3998 LED_CTRL_1000MBPS_ON));
4000 tp->link_config.active_speed = SPEED_INVALID;
4001 tp->link_config.active_duplex = DUPLEX_INVALID;
4002 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4003 LED_CTRL_LNKLED_OVERRIDE |
4004 LED_CTRL_TRAFFIC_OVERRIDE));
4007 if (current_link_up != netif_carrier_ok(tp->dev)) {
4008 if (current_link_up)
4009 netif_carrier_on(tp->dev);
4011 netif_carrier_off(tp->dev);
4012 tg3_link_report(tp);
4014 u32 now_pause_cfg = tp->link_config.active_flowctrl;
4015 if (orig_pause_cfg != now_pause_cfg ||
4016 orig_active_speed != tp->link_config.active_speed ||
4017 orig_active_duplex != tp->link_config.active_duplex)
4018 tg3_link_report(tp);
4024 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
4026 int current_link_up, err = 0;
4030 u32 local_adv, remote_adv;
4032 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4033 tw32_f(MAC_MODE, tp->mac_mode);
4039 (MAC_STATUS_SYNC_CHANGED |
4040 MAC_STATUS_CFG_CHANGED |
4041 MAC_STATUS_MI_COMPLETION |
4042 MAC_STATUS_LNKSTATE_CHANGED));
4048 current_link_up = 0;
4049 current_speed = SPEED_INVALID;
4050 current_duplex = DUPLEX_INVALID;
4052 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4053 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4054 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
4055 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4056 bmsr |= BMSR_LSTATUS;
4058 bmsr &= ~BMSR_LSTATUS;
4061 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
4063 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
4064 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4065 /* do nothing, just check for link up at the end */
4066 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4069 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4070 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4071 ADVERTISE_1000XPAUSE |
4072 ADVERTISE_1000XPSE_ASYM |
4075 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4077 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4078 new_adv |= ADVERTISE_1000XHALF;
4079 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4080 new_adv |= ADVERTISE_1000XFULL;
4082 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4083 tg3_writephy(tp, MII_ADVERTISE, new_adv);
4084 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4085 tg3_writephy(tp, MII_BMCR, bmcr);
4087 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4088 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
4089 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4096 bmcr &= ~BMCR_SPEED1000;
4097 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4099 if (tp->link_config.duplex == DUPLEX_FULL)
4100 new_bmcr |= BMCR_FULLDPLX;
4102 if (new_bmcr != bmcr) {
4103 /* BMCR_SPEED1000 is a reserved bit that needs
4104 * to be set on write.
4106 new_bmcr |= BMCR_SPEED1000;
4108 /* Force a linkdown */
4109 if (netif_carrier_ok(tp->dev)) {
4112 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4113 adv &= ~(ADVERTISE_1000XFULL |
4114 ADVERTISE_1000XHALF |
4116 tg3_writephy(tp, MII_ADVERTISE, adv);
4117 tg3_writephy(tp, MII_BMCR, bmcr |
4121 netif_carrier_off(tp->dev);
4123 tg3_writephy(tp, MII_BMCR, new_bmcr);
4125 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4126 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4127 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4129 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4130 bmsr |= BMSR_LSTATUS;
4132 bmsr &= ~BMSR_LSTATUS;
4134 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4138 if (bmsr & BMSR_LSTATUS) {
4139 current_speed = SPEED_1000;
4140 current_link_up = 1;
4141 if (bmcr & BMCR_FULLDPLX)
4142 current_duplex = DUPLEX_FULL;
4144 current_duplex = DUPLEX_HALF;
4149 if (bmcr & BMCR_ANENABLE) {
4152 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4153 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4154 common = local_adv & remote_adv;
4155 if (common & (ADVERTISE_1000XHALF |
4156 ADVERTISE_1000XFULL)) {
4157 if (common & ADVERTISE_1000XFULL)
4158 current_duplex = DUPLEX_FULL;
4160 current_duplex = DUPLEX_HALF;
4163 current_link_up = 0;
4167 if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4168 tg3_setup_flow_control(tp, local_adv, remote_adv);
4170 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4171 if (tp->link_config.active_duplex == DUPLEX_HALF)
4172 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4174 tw32_f(MAC_MODE, tp->mac_mode);
4177 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4179 tp->link_config.active_speed = current_speed;
4180 tp->link_config.active_duplex = current_duplex;
4182 if (current_link_up != netif_carrier_ok(tp->dev)) {
4183 if (current_link_up)
4184 netif_carrier_on(tp->dev);
4186 netif_carrier_off(tp->dev);
4187 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4189 tg3_link_report(tp);
4194 static void tg3_serdes_parallel_detect(struct tg3 *tp)
4196 if (tp->serdes_counter) {
4197 /* Give autoneg time to complete. */
4198 tp->serdes_counter--;
4201 if (!netif_carrier_ok(tp->dev) &&
4202 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4205 tg3_readphy(tp, MII_BMCR, &bmcr);
4206 if (bmcr & BMCR_ANENABLE) {
4209 /* Select shadow register 0x1f */
4210 tg3_writephy(tp, 0x1c, 0x7c00);
4211 tg3_readphy(tp, 0x1c, &phy1);
4213 /* Select expansion interrupt status register */
4214 tg3_writephy(tp, 0x17, 0x0f01);
4215 tg3_readphy(tp, 0x15, &phy2);
4216 tg3_readphy(tp, 0x15, &phy2);
4218 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4219 /* We have signal detect and not receiving
4220 * config code words, link is up by parallel
4224 bmcr &= ~BMCR_ANENABLE;
4225 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4226 tg3_writephy(tp, MII_BMCR, bmcr);
4227 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
4231 else if (netif_carrier_ok(tp->dev) &&
4232 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4233 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4236 /* Select expansion interrupt status register */
4237 tg3_writephy(tp, 0x17, 0x0f01);
4238 tg3_readphy(tp, 0x15, &phy2);
4242 /* Config code words received, turn on autoneg. */
4243 tg3_readphy(tp, MII_BMCR, &bmcr);
4244 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4246 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4252 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4256 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
4257 err = tg3_setup_fiber_phy(tp, force_reset);
4258 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
4259 err = tg3_setup_fiber_mii_phy(tp, force_reset);
4261 err = tg3_setup_copper_phy(tp, force_reset);
4264 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
4267 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4268 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4270 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4275 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4276 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4277 tw32(GRC_MISC_CFG, val);
4280 if (tp->link_config.active_speed == SPEED_1000 &&
4281 tp->link_config.active_duplex == DUPLEX_HALF)
4282 tw32(MAC_TX_LENGTHS,
4283 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4284 (6 << TX_LENGTHS_IPG_SHIFT) |
4285 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
4287 tw32(MAC_TX_LENGTHS,
4288 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4289 (6 << TX_LENGTHS_IPG_SHIFT) |
4290 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
4292 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4293 if (netif_carrier_ok(tp->dev)) {
4294 tw32(HOSTCC_STAT_COAL_TICKS,
4295 tp->coal.stats_block_coalesce_usecs);
4297 tw32(HOSTCC_STAT_COAL_TICKS, 0);
4301 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4302 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
4303 if (!netif_carrier_ok(tp->dev))
4304 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4307 val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4308 tw32(PCIE_PWR_MGMT_THRESH, val);
4314 /* This is called whenever we suspect that the system chipset is re-
4315 * ordering the sequence of MMIO to the tx send mailbox. The symptom
4316 * is bogus tx completions. We try to recover by setting the
4317 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4320 static void tg3_tx_recover(struct tg3 *tp)
4322 BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4323 tp->write32_tx_mbox == tg3_write_indirect_mbox);
4325 printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
4326 "mapped I/O cycles to the network device, attempting to "
4327 "recover. Please report the problem to the driver maintainer "
4328 "and include system chipset information.\n", tp->dev->name);
4330 spin_lock(&tp->lock);
4331 tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
4332 spin_unlock(&tp->lock);
4335 static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
4338 return tnapi->tx_pending -
4339 ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
4342 /* Tigon3 never reports partial packet sends. So we do not
4343 * need special logic to handle SKBs that have not had all
4344 * of their frags sent yet, like SunGEM does.
4346 static void tg3_tx(struct tg3_napi *tnapi)
4348 struct tg3 *tp = tnapi->tp;
4349 u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
4350 u32 sw_idx = tnapi->tx_cons;
4351 struct netdev_queue *txq;
4352 int index = tnapi - tp->napi;
4354 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
4357 txq = netdev_get_tx_queue(tp->dev, index);
4359 while (sw_idx != hw_idx) {
4360 struct ring_info *ri = &tnapi->tx_buffers[sw_idx];
4361 struct sk_buff *skb = ri->skb;
4364 if (unlikely(skb == NULL)) {
4369 pci_unmap_single(tp->pdev,
4370 pci_unmap_addr(ri, mapping),
4376 sw_idx = NEXT_TX(sw_idx);
4378 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
4379 ri = &tnapi->tx_buffers[sw_idx];
4380 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4383 pci_unmap_page(tp->pdev,
4384 pci_unmap_addr(ri, mapping),
4385 skb_shinfo(skb)->frags[i].size,
4387 sw_idx = NEXT_TX(sw_idx);
4392 if (unlikely(tx_bug)) {
4398 tnapi->tx_cons = sw_idx;
4400 /* Need to make the tx_cons update visible to tg3_start_xmit()
4401 * before checking for netif_queue_stopped(). Without the
4402 * memory barrier, there is a small possibility that tg3_start_xmit()
4403 * will miss it and cause the queue to be stopped forever.
4407 if (unlikely(netif_tx_queue_stopped(txq) &&
4408 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
4409 __netif_tx_lock(txq, smp_processor_id());
4410 if (netif_tx_queue_stopped(txq) &&
4411 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
4412 netif_tx_wake_queue(txq);
4413 __netif_tx_unlock(txq);
4417 static void tg3_rx_skb_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
4422 pci_unmap_single(tp->pdev, pci_unmap_addr(ri, mapping),
4423 map_sz, PCI_DMA_FROMDEVICE);
4424 dev_kfree_skb_any(ri->skb);
4428 /* Returns size of skb allocated or < 0 on error.
4430 * We only need to fill in the address because the other members
4431 * of the RX descriptor are invariant, see tg3_init_rings.
4433 * Note the purposeful assymetry of cpu vs. chip accesses. For
4434 * posting buffers we only dirty the first cache line of the RX
4435 * descriptor (containing the address). Whereas for the RX status
4436 * buffers the cpu only reads the last cacheline of the RX descriptor
4437 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4439 static int tg3_alloc_rx_skb(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
4440 u32 opaque_key, u32 dest_idx_unmasked)
4442 struct tg3_rx_buffer_desc *desc;
4443 struct ring_info *map, *src_map;
4444 struct sk_buff *skb;
4446 int skb_size, dest_idx;
4449 switch (opaque_key) {
4450 case RXD_OPAQUE_RING_STD:
4451 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4452 desc = &tpr->rx_std[dest_idx];
4453 map = &tpr->rx_std_buffers[dest_idx];
4454 skb_size = tp->rx_pkt_map_sz;
4457 case RXD_OPAQUE_RING_JUMBO:
4458 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4459 desc = &tpr->rx_jmb[dest_idx].std;
4460 map = &tpr->rx_jmb_buffers[dest_idx];
4461 skb_size = TG3_RX_JMB_MAP_SZ;
4468 /* Do not overwrite any of the map or rp information
4469 * until we are sure we can commit to a new buffer.
4471 * Callers depend upon this behavior and assume that
4472 * we leave everything unchanged if we fail.
4474 skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset);
4478 skb_reserve(skb, tp->rx_offset);
4480 mapping = pci_map_single(tp->pdev, skb->data, skb_size,
4481 PCI_DMA_FROMDEVICE);
4482 if (pci_dma_mapping_error(tp->pdev, mapping)) {
4488 pci_unmap_addr_set(map, mapping, mapping);
4490 desc->addr_hi = ((u64)mapping >> 32);
4491 desc->addr_lo = ((u64)mapping & 0xffffffff);
4496 /* We only need to move over in the address because the other
4497 * members of the RX descriptor are invariant. See notes above
4498 * tg3_alloc_rx_skb for full details.
4500 static void tg3_recycle_rx(struct tg3_napi *tnapi,
4501 struct tg3_rx_prodring_set *dpr,
4502 u32 opaque_key, int src_idx,
4503 u32 dest_idx_unmasked)
4505 struct tg3 *tp = tnapi->tp;
4506 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4507 struct ring_info *src_map, *dest_map;
4509 struct tg3_rx_prodring_set *spr = &tp->prodring[0];
4511 switch (opaque_key) {
4512 case RXD_OPAQUE_RING_STD:
4513 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4514 dest_desc = &dpr->rx_std[dest_idx];
4515 dest_map = &dpr->rx_std_buffers[dest_idx];
4516 src_desc = &spr->rx_std[src_idx];
4517 src_map = &spr->rx_std_buffers[src_idx];
4520 case RXD_OPAQUE_RING_JUMBO:
4521 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4522 dest_desc = &dpr->rx_jmb[dest_idx].std;
4523 dest_map = &dpr->rx_jmb_buffers[dest_idx];
4524 src_desc = &spr->rx_jmb[src_idx].std;
4525 src_map = &spr->rx_jmb_buffers[src_idx];
4532 dest_map->skb = src_map->skb;
4533 pci_unmap_addr_set(dest_map, mapping,
4534 pci_unmap_addr(src_map, mapping));
4535 dest_desc->addr_hi = src_desc->addr_hi;
4536 dest_desc->addr_lo = src_desc->addr_lo;
4537 src_map->skb = NULL;
4540 /* The RX ring scheme is composed of multiple rings which post fresh
4541 * buffers to the chip, and one special ring the chip uses to report
4542 * status back to the host.
4544 * The special ring reports the status of received packets to the
4545 * host. The chip does not write into the original descriptor the
4546 * RX buffer was obtained from. The chip simply takes the original
4547 * descriptor as provided by the host, updates the status and length
4548 * field, then writes this into the next status ring entry.
4550 * Each ring the host uses to post buffers to the chip is described
4551 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
4552 * it is first placed into the on-chip ram. When the packet's length
4553 * is known, it walks down the TG3_BDINFO entries to select the ring.
4554 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4555 * which is within the range of the new packet's length is chosen.
4557 * The "separate ring for rx status" scheme may sound queer, but it makes
4558 * sense from a cache coherency perspective. If only the host writes
4559 * to the buffer post rings, and only the chip writes to the rx status
4560 * rings, then cache lines never move beyond shared-modified state.
4561 * If both the host and chip were to write into the same ring, cache line
4562 * eviction could occur since both entities want it in an exclusive state.
4564 static int tg3_rx(struct tg3_napi *tnapi, int budget)
4566 struct tg3 *tp = tnapi->tp;
4567 u32 work_mask, rx_std_posted = 0;
4568 u32 std_prod_idx, jmb_prod_idx;
4569 u32 sw_idx = tnapi->rx_rcb_ptr;
4572 struct tg3_rx_prodring_set *tpr = tnapi->prodring;
4574 hw_idx = *(tnapi->rx_rcb_prod_idx);
4576 * We need to order the read of hw_idx and the read of
4577 * the opaque cookie.
4582 std_prod_idx = tpr->rx_std_prod_idx;
4583 jmb_prod_idx = tpr->rx_jmb_prod_idx;
4584 while (sw_idx != hw_idx && budget > 0) {
4585 struct ring_info *ri;
4586 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
4588 struct sk_buff *skb;
4589 dma_addr_t dma_addr;
4590 u32 opaque_key, desc_idx, *post_ptr;
4592 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4593 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4594 if (opaque_key == RXD_OPAQUE_RING_STD) {
4595 ri = &tp->prodring[0].rx_std_buffers[desc_idx];
4596 dma_addr = pci_unmap_addr(ri, mapping);
4598 post_ptr = &std_prod_idx;
4600 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
4601 ri = &tp->prodring[0].rx_jmb_buffers[desc_idx];
4602 dma_addr = pci_unmap_addr(ri, mapping);
4604 post_ptr = &jmb_prod_idx;
4606 goto next_pkt_nopost;
4608 work_mask |= opaque_key;
4610 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4611 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4613 tg3_recycle_rx(tnapi, tpr, opaque_key,
4614 desc_idx, *post_ptr);
4616 /* Other statistics kept track of by card. */
4617 tp->net_stats.rx_dropped++;
4621 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4624 if (len > RX_COPY_THRESHOLD
4625 && tp->rx_offset == NET_IP_ALIGN
4626 /* rx_offset will likely not equal NET_IP_ALIGN
4627 * if this is a 5701 card running in PCI-X mode
4628 * [see tg3_get_invariants()]
4633 skb_size = tg3_alloc_rx_skb(tp, tpr, opaque_key,
4640 pci_unmap_single(tp->pdev, dma_addr, skb_size,
4641 PCI_DMA_FROMDEVICE);
4645 struct sk_buff *copy_skb;
4647 tg3_recycle_rx(tnapi, tpr, opaque_key,
4648 desc_idx, *post_ptr);
4650 copy_skb = netdev_alloc_skb(tp->dev,
4651 len + TG3_RAW_IP_ALIGN);
4652 if (copy_skb == NULL)
4653 goto drop_it_no_recycle;
4655 skb_reserve(copy_skb, TG3_RAW_IP_ALIGN);
4656 skb_put(copy_skb, len);
4657 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4658 skb_copy_from_linear_data(skb, copy_skb->data, len);
4659 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4661 /* We'll reuse the original ring buffer. */
4665 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4666 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4667 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4668 >> RXD_TCPCSUM_SHIFT) == 0xffff))
4669 skb->ip_summed = CHECKSUM_UNNECESSARY;
4671 skb->ip_summed = CHECKSUM_NONE;
4673 skb->protocol = eth_type_trans(skb, tp->dev);
4675 if (len > (tp->dev->mtu + ETH_HLEN) &&
4676 skb->protocol != htons(ETH_P_8021Q)) {
4681 #if TG3_VLAN_TAG_USED
4682 if (tp->vlgrp != NULL &&
4683 desc->type_flags & RXD_FLAG_VLAN) {
4684 vlan_gro_receive(&tnapi->napi, tp->vlgrp,
4685 desc->err_vlan & RXD_VLAN_MASK, skb);
4688 napi_gro_receive(&tnapi->napi, skb);
4696 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4697 u32 idx = *post_ptr % TG3_RX_RING_SIZE;
4698 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, idx);
4699 work_mask &= ~RXD_OPAQUE_RING_STD;
4704 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
4706 /* Refresh hw_idx to see if there is new work */
4707 if (sw_idx == hw_idx) {
4708 hw_idx = *(tnapi->rx_rcb_prod_idx);
4713 /* ACK the status ring. */
4714 tnapi->rx_rcb_ptr = sw_idx;
4715 tw32_rx_mbox(tnapi->consmbox, sw_idx);
4717 /* Refill RX ring(s). */
4718 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) || tnapi == &tp->napi[1]) {
4719 if (work_mask & RXD_OPAQUE_RING_STD) {
4720 tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4721 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4722 tpr->rx_std_prod_idx);
4724 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4725 tpr->rx_jmb_prod_idx = jmb_prod_idx %
4726 TG3_RX_JUMBO_RING_SIZE;
4727 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
4728 tpr->rx_jmb_prod_idx);
4731 } else if (work_mask) {
4732 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
4733 * updated before the producer indices can be updated.
4737 tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4738 tpr->rx_jmb_prod_idx = jmb_prod_idx % TG3_RX_JUMBO_RING_SIZE;
4740 napi_schedule(&tp->napi[1].napi);
4746 static void tg3_poll_link(struct tg3 *tp)
4748 /* handle link change and other phy events */
4749 if (!(tp->tg3_flags &
4750 (TG3_FLAG_USE_LINKCHG_REG |
4751 TG3_FLAG_POLL_SERDES))) {
4752 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
4754 if (sblk->status & SD_STATUS_LINK_CHG) {
4755 sblk->status = SD_STATUS_UPDATED |
4756 (sblk->status & ~SD_STATUS_LINK_CHG);
4757 spin_lock(&tp->lock);
4758 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4760 (MAC_STATUS_SYNC_CHANGED |
4761 MAC_STATUS_CFG_CHANGED |
4762 MAC_STATUS_MI_COMPLETION |
4763 MAC_STATUS_LNKSTATE_CHANGED));
4766 tg3_setup_phy(tp, 0);
4767 spin_unlock(&tp->lock);
4772 static void tg3_rx_prodring_xfer(struct tg3 *tp,
4773 struct tg3_rx_prodring_set *dpr,
4774 struct tg3_rx_prodring_set *spr)
4776 u32 si, di, cpycnt, src_prod_idx;
4780 src_prod_idx = spr->rx_std_prod_idx;
4782 /* Make sure updates to the rx_std_buffers[] entries and the
4783 * standard producer index are seen in the correct order.
4787 if (spr->rx_std_cons_idx == src_prod_idx)
4790 if (spr->rx_std_cons_idx < src_prod_idx)
4791 cpycnt = src_prod_idx - spr->rx_std_cons_idx;
4793 cpycnt = TG3_RX_RING_SIZE - spr->rx_std_cons_idx;
4795 cpycnt = min(cpycnt, TG3_RX_RING_SIZE - dpr->rx_std_prod_idx);
4797 si = spr->rx_std_cons_idx;
4798 di = dpr->rx_std_prod_idx;
4800 memcpy(&dpr->rx_std_buffers[di],
4801 &spr->rx_std_buffers[si],
4802 cpycnt * sizeof(struct ring_info));
4804 for (i = 0; i < cpycnt; i++, di++, si++) {
4805 struct tg3_rx_buffer_desc *sbd, *dbd;
4806 sbd = &spr->rx_std[si];
4807 dbd = &dpr->rx_std[di];
4808 dbd->addr_hi = sbd->addr_hi;
4809 dbd->addr_lo = sbd->addr_lo;
4812 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) %
4814 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) %
4819 src_prod_idx = spr->rx_jmb_prod_idx;
4821 /* Make sure updates to the rx_jmb_buffers[] entries and
4822 * the jumbo producer index are seen in the correct order.
4826 if (spr->rx_jmb_cons_idx == src_prod_idx)
4829 if (spr->rx_jmb_cons_idx < src_prod_idx)
4830 cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
4832 cpycnt = TG3_RX_JUMBO_RING_SIZE - spr->rx_jmb_cons_idx;
4834 cpycnt = min(cpycnt,
4835 TG3_RX_JUMBO_RING_SIZE - dpr->rx_jmb_prod_idx);
4837 si = spr->rx_jmb_cons_idx;
4838 di = dpr->rx_jmb_prod_idx;
4840 memcpy(&dpr->rx_jmb_buffers[di],
4841 &spr->rx_jmb_buffers[si],
4842 cpycnt * sizeof(struct ring_info));
4844 for (i = 0; i < cpycnt; i++, di++, si++) {
4845 struct tg3_rx_buffer_desc *sbd, *dbd;
4846 sbd = &spr->rx_jmb[si].std;
4847 dbd = &dpr->rx_jmb[di].std;
4848 dbd->addr_hi = sbd->addr_hi;
4849 dbd->addr_lo = sbd->addr_lo;
4852 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) %
4853 TG3_RX_JUMBO_RING_SIZE;
4854 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) %
4855 TG3_RX_JUMBO_RING_SIZE;
4859 static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
4861 struct tg3 *tp = tnapi->tp;
4863 /* run TX completion thread */
4864 if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
4866 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4870 /* run RX thread, within the bounds set by NAPI.
4871 * All RX "locking" is done by ensuring outside
4872 * code synchronizes with tg3->napi.poll()
4874 if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
4875 work_done += tg3_rx(tnapi, budget - work_done);
4877 if ((tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) && tnapi == &tp->napi[1]) {
4879 u32 std_prod_idx = tp->prodring[0].rx_std_prod_idx;
4880 u32 jmb_prod_idx = tp->prodring[0].rx_jmb_prod_idx;
4882 for (i = 2; i < tp->irq_cnt; i++)
4883 tg3_rx_prodring_xfer(tp, tnapi->prodring,
4884 tp->napi[i].prodring);
4888 if (std_prod_idx != tp->prodring[0].rx_std_prod_idx) {
4889 u32 mbox = TG3_RX_STD_PROD_IDX_REG;
4890 tw32_rx_mbox(mbox, tp->prodring[0].rx_std_prod_idx);
4893 if (jmb_prod_idx != tp->prodring[0].rx_jmb_prod_idx) {
4894 u32 mbox = TG3_RX_JMB_PROD_IDX_REG;
4895 tw32_rx_mbox(mbox, tp->prodring[0].rx_jmb_prod_idx);
4904 static int tg3_poll_msix(struct napi_struct *napi, int budget)
4906 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
4907 struct tg3 *tp = tnapi->tp;
4909 struct tg3_hw_status *sblk = tnapi->hw_status;
4912 work_done = tg3_poll_work(tnapi, work_done, budget);
4914 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4917 if (unlikely(work_done >= budget))
4920 /* tp->last_tag is used in tg3_restart_ints() below
4921 * to tell the hw how much work has been processed,
4922 * so we must read it before checking for more work.
4924 tnapi->last_tag = sblk->status_tag;
4925 tnapi->last_irq_tag = tnapi->last_tag;
4928 /* check for RX/TX work to do */
4929 if (sblk->idx[0].tx_consumer == tnapi->tx_cons &&
4930 *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr) {
4931 napi_complete(napi);
4932 /* Reenable interrupts. */
4933 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
4942 /* work_done is guaranteed to be less than budget. */
4943 napi_complete(napi);
4944 schedule_work(&tp->reset_task);
4948 static int tg3_poll(struct napi_struct *napi, int budget)
4950 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
4951 struct tg3 *tp = tnapi->tp;
4953 struct tg3_hw_status *sblk = tnapi->hw_status;
4958 work_done = tg3_poll_work(tnapi, work_done, budget);
4960 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4963 if (unlikely(work_done >= budget))
4966 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
4967 /* tp->last_tag is used in tg3_int_reenable() below
4968 * to tell the hw how much work has been processed,
4969 * so we must read it before checking for more work.
4971 tnapi->last_tag = sblk->status_tag;
4972 tnapi->last_irq_tag = tnapi->last_tag;
4975 sblk->status &= ~SD_STATUS_UPDATED;
4977 if (likely(!tg3_has_work(tnapi))) {
4978 napi_complete(napi);
4979 tg3_int_reenable(tnapi);
4987 /* work_done is guaranteed to be less than budget. */
4988 napi_complete(napi);
4989 schedule_work(&tp->reset_task);
4993 static void tg3_irq_quiesce(struct tg3 *tp)
4997 BUG_ON(tp->irq_sync);
5002 for (i = 0; i < tp->irq_cnt; i++)
5003 synchronize_irq(tp->napi[i].irq_vec);
5006 static inline int tg3_irq_sync(struct tg3 *tp)
5008 return tp->irq_sync;
5011 /* Fully shutdown all tg3 driver activity elsewhere in the system.
5012 * If irq_sync is non-zero, then the IRQ handler must be synchronized
5013 * with as well. Most of the time, this is not necessary except when
5014 * shutting down the device.
5016 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
5018 spin_lock_bh(&tp->lock);
5020 tg3_irq_quiesce(tp);
5023 static inline void tg3_full_unlock(struct tg3 *tp)
5025 spin_unlock_bh(&tp->lock);
5028 /* One-shot MSI handler - Chip automatically disables interrupt
5029 * after sending MSI so driver doesn't have to do it.
5031 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
5033 struct tg3_napi *tnapi = dev_id;
5034 struct tg3 *tp = tnapi->tp;
5036 prefetch(tnapi->hw_status);
5038 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5040 if (likely(!tg3_irq_sync(tp)))
5041 napi_schedule(&tnapi->napi);
5046 /* MSI ISR - No need to check for interrupt sharing and no need to
5047 * flush status block and interrupt mailbox. PCI ordering rules
5048 * guarantee that MSI will arrive after the status block.
5050 static irqreturn_t tg3_msi(int irq, void *dev_id)
5052 struct tg3_napi *tnapi = dev_id;
5053 struct tg3 *tp = tnapi->tp;
5055 prefetch(tnapi->hw_status);
5057 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5059 * Writing any value to intr-mbox-0 clears PCI INTA# and
5060 * chip-internal interrupt pending events.
5061 * Writing non-zero to intr-mbox-0 additional tells the
5062 * NIC to stop sending us irqs, engaging "in-intr-handler"
5065 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5066 if (likely(!tg3_irq_sync(tp)))
5067 napi_schedule(&tnapi->napi);
5069 return IRQ_RETVAL(1);
5072 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
5074 struct tg3_napi *tnapi = dev_id;
5075 struct tg3 *tp = tnapi->tp;
5076 struct tg3_hw_status *sblk = tnapi->hw_status;
5077 unsigned int handled = 1;
5079 /* In INTx mode, it is possible for the interrupt to arrive at
5080 * the CPU before the status block posted prior to the interrupt.
5081 * Reading the PCI State register will confirm whether the
5082 * interrupt is ours and will flush the status block.
5084 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
5085 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5086 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5093 * Writing any value to intr-mbox-0 clears PCI INTA# and
5094 * chip-internal interrupt pending events.
5095 * Writing non-zero to intr-mbox-0 additional tells the
5096 * NIC to stop sending us irqs, engaging "in-intr-handler"
5099 * Flush the mailbox to de-assert the IRQ immediately to prevent
5100 * spurious interrupts. The flush impacts performance but
5101 * excessive spurious interrupts can be worse in some cases.
5103 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5104 if (tg3_irq_sync(tp))
5106 sblk->status &= ~SD_STATUS_UPDATED;
5107 if (likely(tg3_has_work(tnapi))) {
5108 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5109 napi_schedule(&tnapi->napi);
5111 /* No work, shared interrupt perhaps? re-enable
5112 * interrupts, and flush that PCI write
5114 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
5118 return IRQ_RETVAL(handled);
5121 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
5123 struct tg3_napi *tnapi = dev_id;
5124 struct tg3 *tp = tnapi->tp;
5125 struct tg3_hw_status *sblk = tnapi->hw_status;
5126 unsigned int handled = 1;
5128 /* In INTx mode, it is possible for the interrupt to arrive at
5129 * the CPU before the status block posted prior to the interrupt.
5130 * Reading the PCI State register will confirm whether the
5131 * interrupt is ours and will flush the status block.
5133 if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
5134 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5135 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5142 * writing any value to intr-mbox-0 clears PCI INTA# and
5143 * chip-internal interrupt pending events.
5144 * writing non-zero to intr-mbox-0 additional tells the
5145 * NIC to stop sending us irqs, engaging "in-intr-handler"
5148 * Flush the mailbox to de-assert the IRQ immediately to prevent
5149 * spurious interrupts. The flush impacts performance but
5150 * excessive spurious interrupts can be worse in some cases.
5152 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5155 * In a shared interrupt configuration, sometimes other devices'
5156 * interrupts will scream. We record the current status tag here
5157 * so that the above check can report that the screaming interrupts
5158 * are unhandled. Eventually they will be silenced.
5160 tnapi->last_irq_tag = sblk->status_tag;
5162 if (tg3_irq_sync(tp))
5165 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5167 napi_schedule(&tnapi->napi);
5170 return IRQ_RETVAL(handled);
5173 /* ISR for interrupt test */
5174 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
5176 struct tg3_napi *tnapi = dev_id;
5177 struct tg3 *tp = tnapi->tp;
5178 struct tg3_hw_status *sblk = tnapi->hw_status;
5180 if ((sblk->status & SD_STATUS_UPDATED) ||
5181 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5182 tg3_disable_ints(tp);
5183 return IRQ_RETVAL(1);
5185 return IRQ_RETVAL(0);
5188 static int tg3_init_hw(struct tg3 *, int);
5189 static int tg3_halt(struct tg3 *, int, int);
5191 /* Restart hardware after configuration changes, self-test, etc.
5192 * Invoked with tp->lock held.
5194 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
5195 __releases(tp->lock)
5196 __acquires(tp->lock)
5200 err = tg3_init_hw(tp, reset_phy);
5202 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
5203 "aborting.\n", tp->dev->name);
5204 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5205 tg3_full_unlock(tp);
5206 del_timer_sync(&tp->timer);
5208 tg3_napi_enable(tp);
5210 tg3_full_lock(tp, 0);
5215 #ifdef CONFIG_NET_POLL_CONTROLLER
5216 static void tg3_poll_controller(struct net_device *dev)
5219 struct tg3 *tp = netdev_priv(dev);
5221 for (i = 0; i < tp->irq_cnt; i++)
5222 tg3_interrupt(tp->napi[i].irq_vec, dev);
5226 static void tg3_reset_task(struct work_struct *work)
5228 struct tg3 *tp = container_of(work, struct tg3, reset_task);
5230 unsigned int restart_timer;
5232 tg3_full_lock(tp, 0);
5234 if (!netif_running(tp->dev)) {
5235 tg3_full_unlock(tp);
5239 tg3_full_unlock(tp);
5245 tg3_full_lock(tp, 1);
5247 restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
5248 tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
5250 if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
5251 tp->write32_tx_mbox = tg3_write32_tx_mbox;
5252 tp->write32_rx_mbox = tg3_write_flush_reg32;
5253 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
5254 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
5257 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
5258 err = tg3_init_hw(tp, 1);
5262 tg3_netif_start(tp);
5265 mod_timer(&tp->timer, jiffies + 1);
5268 tg3_full_unlock(tp);
5274 static void tg3_dump_short_state(struct tg3 *tp)
5276 printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
5277 tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
5278 printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
5279 tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
5282 static void tg3_tx_timeout(struct net_device *dev)
5284 struct tg3 *tp = netdev_priv(dev);
5286 if (netif_msg_tx_err(tp)) {
5287 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
5289 tg3_dump_short_state(tp);
5292 schedule_work(&tp->reset_task);
5295 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5296 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
5298 u32 base = (u32) mapping & 0xffffffff;
5300 return ((base > 0xffffdcc0) &&
5301 (base + len + 8 < base));
5304 /* Test for DMA addresses > 40-bit */
5305 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
5308 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
5309 if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
5310 return (((u64) mapping + len) > DMA_BIT_MASK(40));
5317 static void tg3_set_txd(struct tg3_napi *, int, dma_addr_t, int, u32, u32);
5319 /* Workaround 4GB and 40-bit hardware DMA bugs. */
5320 static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
5321 struct sk_buff *skb, u32 last_plus_one,
5322 u32 *start, u32 base_flags, u32 mss)
5324 struct tg3 *tp = tnapi->tp;
5325 struct sk_buff *new_skb;
5326 dma_addr_t new_addr = 0;
5330 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5331 new_skb = skb_copy(skb, GFP_ATOMIC);
5333 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5335 new_skb = skb_copy_expand(skb,
5336 skb_headroom(skb) + more_headroom,
5337 skb_tailroom(skb), GFP_ATOMIC);
5343 /* New SKB is guaranteed to be linear. */
5345 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
5347 /* Make sure the mapping succeeded */
5348 if (pci_dma_mapping_error(tp->pdev, new_addr)) {
5350 dev_kfree_skb(new_skb);
5353 /* Make sure new skb does not cross any 4G boundaries.
5354 * Drop the packet if it does.
5356 } else if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5357 tg3_4g_overflow_test(new_addr, new_skb->len)) {
5358 pci_unmap_single(tp->pdev, new_addr, new_skb->len,
5361 dev_kfree_skb(new_skb);
5364 tg3_set_txd(tnapi, entry, new_addr, new_skb->len,
5365 base_flags, 1 | (mss << 1));
5366 *start = NEXT_TX(entry);
5370 /* Now clean up the sw ring entries. */
5372 while (entry != last_plus_one) {
5376 len = skb_headlen(skb);
5378 len = skb_shinfo(skb)->frags[i-1].size;
5380 pci_unmap_single(tp->pdev,
5381 pci_unmap_addr(&tnapi->tx_buffers[entry],
5383 len, PCI_DMA_TODEVICE);
5385 tnapi->tx_buffers[entry].skb = new_skb;
5386 pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5389 tnapi->tx_buffers[entry].skb = NULL;
5391 entry = NEXT_TX(entry);
5400 static void tg3_set_txd(struct tg3_napi *tnapi, int entry,
5401 dma_addr_t mapping, int len, u32 flags,
5404 struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry];
5405 int is_end = (mss_and_is_end & 0x1);
5406 u32 mss = (mss_and_is_end >> 1);
5410 flags |= TXD_FLAG_END;
5411 if (flags & TXD_FLAG_VLAN) {
5412 vlan_tag = flags >> 16;
5415 vlan_tag |= (mss << TXD_MSS_SHIFT);
5417 txd->addr_hi = ((u64) mapping >> 32);
5418 txd->addr_lo = ((u64) mapping & 0xffffffff);
5419 txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5420 txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5423 /* hard_start_xmit for devices that don't have any bugs and
5424 * support TG3_FLG2_HW_TSO_2 and TG3_FLG2_HW_TSO_3 only.
5426 static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
5427 struct net_device *dev)
5429 struct tg3 *tp = netdev_priv(dev);
5430 u32 len, entry, base_flags, mss;
5432 struct tg3_napi *tnapi;
5433 struct netdev_queue *txq;
5434 unsigned int i, last;
5437 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5438 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5439 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
5442 /* We are running in BH disabled context with netif_tx_lock
5443 * and TX reclaim runs via tp->napi.poll inside of a software
5444 * interrupt. Furthermore, IRQ processing runs lockless so we have
5445 * no IRQ context deadlocks to worry about either. Rejoice!
5447 if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5448 if (!netif_tx_queue_stopped(txq)) {
5449 netif_tx_stop_queue(txq);
5451 /* This is a hard error, log it. */
5452 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5453 "queue awake!\n", dev->name);
5455 return NETDEV_TX_BUSY;
5458 entry = tnapi->tx_prod;
5461 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5462 int tcp_opt_len, ip_tcp_len;
5465 if (skb_header_cloned(skb) &&
5466 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5471 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
5472 hdrlen = skb_headlen(skb) - ETH_HLEN;
5474 struct iphdr *iph = ip_hdr(skb);
5476 tcp_opt_len = tcp_optlen(skb);
5477 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5480 iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
5481 hdrlen = ip_tcp_len + tcp_opt_len;
5484 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5485 mss |= (hdrlen & 0xc) << 12;
5487 base_flags |= 0x00000010;
5488 base_flags |= (hdrlen & 0x3e0) << 5;
5492 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5493 TXD_FLAG_CPU_POST_DMA);
5495 tcp_hdr(skb)->check = 0;
5498 else if (skb->ip_summed == CHECKSUM_PARTIAL)
5499 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5500 #if TG3_VLAN_TAG_USED
5501 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5502 base_flags |= (TXD_FLAG_VLAN |
5503 (vlan_tx_tag_get(skb) << 16));
5506 len = skb_headlen(skb);
5508 /* Queue skb data, a.k.a. the main skb fragment. */
5509 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5510 if (pci_dma_mapping_error(tp->pdev, mapping)) {
5515 tnapi->tx_buffers[entry].skb = skb;
5516 pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
5518 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
5519 !mss && skb->len > ETH_DATA_LEN)
5520 base_flags |= TXD_FLAG_JMB_PKT;
5522 tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5523 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5525 entry = NEXT_TX(entry);
5527 /* Now loop through additional data fragments, and queue them. */
5528 if (skb_shinfo(skb)->nr_frags > 0) {
5529 last = skb_shinfo(skb)->nr_frags - 1;
5530 for (i = 0; i <= last; i++) {
5531 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5534 mapping = pci_map_page(tp->pdev,
5537 len, PCI_DMA_TODEVICE);
5538 if (pci_dma_mapping_error(tp->pdev, mapping))
5541 tnapi->tx_buffers[entry].skb = NULL;
5542 pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5545 tg3_set_txd(tnapi, entry, mapping, len,
5546 base_flags, (i == last) | (mss << 1));
5548 entry = NEXT_TX(entry);
5552 /* Packets are ready, update Tx producer idx local and on card. */
5553 tw32_tx_mbox(tnapi->prodmbox, entry);
5555 tnapi->tx_prod = entry;
5556 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5557 netif_tx_stop_queue(txq);
5558 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5559 netif_tx_wake_queue(txq);
5565 return NETDEV_TX_OK;
5569 entry = tnapi->tx_prod;
5570 tnapi->tx_buffers[entry].skb = NULL;
5571 pci_unmap_single(tp->pdev,
5572 pci_unmap_addr(&tnapi->tx_buffers[entry], mapping),
5575 for (i = 0; i <= last; i++) {
5576 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5577 entry = NEXT_TX(entry);
5579 pci_unmap_page(tp->pdev,
5580 pci_unmap_addr(&tnapi->tx_buffers[entry],
5582 frag->size, PCI_DMA_TODEVICE);
5586 return NETDEV_TX_OK;
5589 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *,
5590 struct net_device *);
5592 /* Use GSO to workaround a rare TSO bug that may be triggered when the
5593 * TSO header is greater than 80 bytes.
5595 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5597 struct sk_buff *segs, *nskb;
5598 u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
5600 /* Estimate the number of fragments in the worst case */
5601 if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
5602 netif_stop_queue(tp->dev);
5603 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
5604 return NETDEV_TX_BUSY;
5606 netif_wake_queue(tp->dev);
5609 segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
5611 goto tg3_tso_bug_end;
5617 tg3_start_xmit_dma_bug(nskb, tp->dev);
5623 return NETDEV_TX_OK;
5626 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5627 * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5629 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
5630 struct net_device *dev)
5632 struct tg3 *tp = netdev_priv(dev);
5633 u32 len, entry, base_flags, mss;
5634 int would_hit_hwbug;
5636 struct tg3_napi *tnapi;
5637 struct netdev_queue *txq;
5638 unsigned int i, last;
5641 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5642 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5643 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
5646 /* We are running in BH disabled context with netif_tx_lock
5647 * and TX reclaim runs via tp->napi.poll inside of a software
5648 * interrupt. Furthermore, IRQ processing runs lockless so we have
5649 * no IRQ context deadlocks to worry about either. Rejoice!
5651 if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5652 if (!netif_tx_queue_stopped(txq)) {
5653 netif_tx_stop_queue(txq);
5655 /* This is a hard error, log it. */
5656 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5657 "queue awake!\n", dev->name);
5659 return NETDEV_TX_BUSY;
5662 entry = tnapi->tx_prod;
5664 if (skb->ip_summed == CHECKSUM_PARTIAL)
5665 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5667 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5669 u32 tcp_opt_len, ip_tcp_len, hdr_len;
5671 if (skb_header_cloned(skb) &&
5672 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5677 tcp_opt_len = tcp_optlen(skb);
5678 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5680 hdr_len = ip_tcp_len + tcp_opt_len;
5681 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
5682 (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
5683 return (tg3_tso_bug(tp, skb));
5685 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5686 TXD_FLAG_CPU_POST_DMA);
5690 iph->tot_len = htons(mss + hdr_len);
5691 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
5692 tcp_hdr(skb)->check = 0;
5693 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
5695 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5700 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5701 mss |= (hdr_len & 0xc) << 12;
5703 base_flags |= 0x00000010;
5704 base_flags |= (hdr_len & 0x3e0) << 5;
5705 } else if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)
5706 mss |= hdr_len << 9;
5707 else if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_1) ||
5708 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
5709 if (tcp_opt_len || iph->ihl > 5) {
5712 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5713 mss |= (tsflags << 11);
5716 if (tcp_opt_len || iph->ihl > 5) {
5719 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5720 base_flags |= tsflags << 12;
5724 #if TG3_VLAN_TAG_USED
5725 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5726 base_flags |= (TXD_FLAG_VLAN |
5727 (vlan_tx_tag_get(skb) << 16));
5730 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
5731 !mss && skb->len > ETH_DATA_LEN)
5732 base_flags |= TXD_FLAG_JMB_PKT;
5734 len = skb_headlen(skb);
5736 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5737 if (pci_dma_mapping_error(tp->pdev, mapping)) {
5742 tnapi->tx_buffers[entry].skb = skb;
5743 pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
5745 would_hit_hwbug = 0;
5747 if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) && len <= 8)
5748 would_hit_hwbug = 1;
5750 if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5751 tg3_4g_overflow_test(mapping, len))
5752 would_hit_hwbug = 1;
5754 if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5755 tg3_40bit_overflow_test(tp, mapping, len))
5756 would_hit_hwbug = 1;
5758 if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
5759 would_hit_hwbug = 1;
5761 tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5762 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5764 entry = NEXT_TX(entry);
5766 /* Now loop through additional data fragments, and queue them. */
5767 if (skb_shinfo(skb)->nr_frags > 0) {
5768 last = skb_shinfo(skb)->nr_frags - 1;
5769 for (i = 0; i <= last; i++) {
5770 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5773 mapping = pci_map_page(tp->pdev,
5776 len, PCI_DMA_TODEVICE);
5778 tnapi->tx_buffers[entry].skb = NULL;
5779 pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5781 if (pci_dma_mapping_error(tp->pdev, mapping))
5784 if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) &&
5786 would_hit_hwbug = 1;
5788 if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5789 tg3_4g_overflow_test(mapping, len))
5790 would_hit_hwbug = 1;
5792 if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5793 tg3_40bit_overflow_test(tp, mapping, len))
5794 would_hit_hwbug = 1;
5796 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5797 tg3_set_txd(tnapi, entry, mapping, len,
5798 base_flags, (i == last)|(mss << 1));
5800 tg3_set_txd(tnapi, entry, mapping, len,
5801 base_flags, (i == last));
5803 entry = NEXT_TX(entry);
5807 if (would_hit_hwbug) {
5808 u32 last_plus_one = entry;
5811 start = entry - 1 - skb_shinfo(skb)->nr_frags;
5812 start &= (TG3_TX_RING_SIZE - 1);
5814 /* If the workaround fails due to memory/mapping
5815 * failure, silently drop this packet.
5817 if (tigon3_dma_hwbug_workaround(tnapi, skb, last_plus_one,
5818 &start, base_flags, mss))
5824 /* Packets are ready, update Tx producer idx local and on card. */
5825 tw32_tx_mbox(tnapi->prodmbox, entry);
5827 tnapi->tx_prod = entry;
5828 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5829 netif_tx_stop_queue(txq);
5830 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5831 netif_tx_wake_queue(txq);
5837 return NETDEV_TX_OK;
5841 entry = tnapi->tx_prod;
5842 tnapi->tx_buffers[entry].skb = NULL;
5843 pci_unmap_single(tp->pdev,
5844 pci_unmap_addr(&tnapi->tx_buffers[entry], mapping),
5847 for (i = 0; i <= last; i++) {
5848 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5849 entry = NEXT_TX(entry);
5851 pci_unmap_page(tp->pdev,
5852 pci_unmap_addr(&tnapi->tx_buffers[entry],
5854 frag->size, PCI_DMA_TODEVICE);
5858 return NETDEV_TX_OK;
5861 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
5866 if (new_mtu > ETH_DATA_LEN) {
5867 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
5868 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
5869 ethtool_op_set_tso(dev, 0);
5872 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
5874 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
5875 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
5876 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
5880 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
5882 struct tg3 *tp = netdev_priv(dev);
5885 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
5888 if (!netif_running(dev)) {
5889 /* We'll just catch it later when the
5892 tg3_set_mtu(dev, tp, new_mtu);
5900 tg3_full_lock(tp, 1);
5902 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5904 tg3_set_mtu(dev, tp, new_mtu);
5906 err = tg3_restart_hw(tp, 0);
5909 tg3_netif_start(tp);
5911 tg3_full_unlock(tp);
5919 static void tg3_rx_prodring_free(struct tg3 *tp,
5920 struct tg3_rx_prodring_set *tpr)
5924 if (tpr != &tp->prodring[0]) {
5925 for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx;
5926 i = (i + 1) % TG3_RX_RING_SIZE)
5927 tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
5930 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
5931 for (i = tpr->rx_jmb_cons_idx;
5932 i != tpr->rx_jmb_prod_idx;
5933 i = (i + 1) % TG3_RX_JUMBO_RING_SIZE) {
5934 tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
5942 for (i = 0; i < TG3_RX_RING_SIZE; i++)
5943 tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
5946 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
5947 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++)
5948 tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
5953 /* Initialize tx/rx rings for packet processing.
5955 * The chip has been shut down and the driver detached from
5956 * the networking, so no interrupts or new tx packets will
5957 * end up in the driver. tp->{tx,}lock are held and thus
5960 static int tg3_rx_prodring_alloc(struct tg3 *tp,
5961 struct tg3_rx_prodring_set *tpr)
5963 u32 i, rx_pkt_dma_sz;
5965 tpr->rx_std_cons_idx = 0;
5966 tpr->rx_std_prod_idx = 0;
5967 tpr->rx_jmb_cons_idx = 0;
5968 tpr->rx_jmb_prod_idx = 0;
5970 if (tpr != &tp->prodring[0]) {
5971 memset(&tpr->rx_std_buffers[0], 0, TG3_RX_STD_BUFF_RING_SIZE);
5972 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE)
5973 memset(&tpr->rx_jmb_buffers[0], 0,
5974 TG3_RX_JMB_BUFF_RING_SIZE);
5978 /* Zero out all descriptors. */
5979 memset(tpr->rx_std, 0, TG3_RX_RING_BYTES);
5981 rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
5982 if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
5983 tp->dev->mtu > ETH_DATA_LEN)
5984 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
5985 tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
5987 /* Initialize invariants of the rings, we only set this
5988 * stuff once. This works because the card does not
5989 * write into the rx buffer posting rings.
5991 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5992 struct tg3_rx_buffer_desc *rxd;
5994 rxd = &tpr->rx_std[i];
5995 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
5996 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
5997 rxd->opaque = (RXD_OPAQUE_RING_STD |
5998 (i << RXD_OPAQUE_INDEX_SHIFT));
6001 /* Now allocate fresh SKBs for each rx ring. */
6002 for (i = 0; i < tp->rx_pending; i++) {
6003 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_STD, i) < 0) {
6004 printk(KERN_WARNING PFX
6005 "%s: Using a smaller RX standard ring, "
6006 "only %d out of %d buffers were allocated "
6008 tp->dev->name, i, tp->rx_pending);
6016 if (!(tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE))
6019 memset(tpr->rx_jmb, 0, TG3_RX_JUMBO_RING_BYTES);
6021 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
6022 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
6023 struct tg3_rx_buffer_desc *rxd;
6025 rxd = &tpr->rx_jmb[i].std;
6026 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
6027 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
6029 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
6030 (i << RXD_OPAQUE_INDEX_SHIFT));
6033 for (i = 0; i < tp->rx_jumbo_pending; i++) {
6034 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_JUMBO,
6036 printk(KERN_WARNING PFX
6037 "%s: Using a smaller RX jumbo ring, "
6038 "only %d out of %d buffers were "
6039 "allocated successfully.\n",
6040 tp->dev->name, i, tp->rx_jumbo_pending);
6043 tp->rx_jumbo_pending = i;
6053 tg3_rx_prodring_free(tp, tpr);
6057 static void tg3_rx_prodring_fini(struct tg3 *tp,
6058 struct tg3_rx_prodring_set *tpr)
6060 kfree(tpr->rx_std_buffers);
6061 tpr->rx_std_buffers = NULL;
6062 kfree(tpr->rx_jmb_buffers);
6063 tpr->rx_jmb_buffers = NULL;
6065 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
6066 tpr->rx_std, tpr->rx_std_mapping);
6070 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
6071 tpr->rx_jmb, tpr->rx_jmb_mapping);
6076 static int tg3_rx_prodring_init(struct tg3 *tp,
6077 struct tg3_rx_prodring_set *tpr)
6079 tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE, GFP_KERNEL);
6080 if (!tpr->rx_std_buffers)
6083 tpr->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
6084 &tpr->rx_std_mapping);
6088 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
6089 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE,
6091 if (!tpr->rx_jmb_buffers)
6094 tpr->rx_jmb = pci_alloc_consistent(tp->pdev,
6095 TG3_RX_JUMBO_RING_BYTES,
6096 &tpr->rx_jmb_mapping);
6104 tg3_rx_prodring_fini(tp, tpr);
6108 /* Free up pending packets in all rx/tx rings.
6110 * The chip has been shut down and the driver detached from
6111 * the networking, so no interrupts or new tx packets will
6112 * end up in the driver. tp->{tx,}lock is not held and we are not
6113 * in an interrupt context and thus may sleep.
6115 static void tg3_free_rings(struct tg3 *tp)
6119 for (j = 0; j < tp->irq_cnt; j++) {
6120 struct tg3_napi *tnapi = &tp->napi[j];
6122 if (!tnapi->tx_buffers)
6125 for (i = 0; i < TG3_TX_RING_SIZE; ) {
6126 struct ring_info *txp;
6127 struct sk_buff *skb;
6130 txp = &tnapi->tx_buffers[i];
6138 pci_unmap_single(tp->pdev,
6139 pci_unmap_addr(txp, mapping),
6146 for (k = 0; k < skb_shinfo(skb)->nr_frags; k++) {
6147 txp = &tnapi->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
6148 pci_unmap_page(tp->pdev,
6149 pci_unmap_addr(txp, mapping),
6150 skb_shinfo(skb)->frags[k].size,
6155 dev_kfree_skb_any(skb);
6158 if (tp->irq_cnt == 1 || j != tp->irq_cnt - 1)
6159 tg3_rx_prodring_free(tp, &tp->prodring[j]);
6163 /* Initialize tx/rx rings for packet processing.
6165 * The chip has been shut down and the driver detached from
6166 * the networking, so no interrupts or new tx packets will
6167 * end up in the driver. tp->{tx,}lock are held and thus
6170 static int tg3_init_rings(struct tg3 *tp)
6174 /* Free up all the SKBs. */
6177 for (i = 0; i < tp->irq_cnt; i++) {
6178 struct tg3_napi *tnapi = &tp->napi[i];
6180 tnapi->last_tag = 0;
6181 tnapi->last_irq_tag = 0;
6182 tnapi->hw_status->status = 0;
6183 tnapi->hw_status->status_tag = 0;
6184 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6189 memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
6191 tnapi->rx_rcb_ptr = 0;
6193 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
6195 if ((tp->irq_cnt == 1 || i != tp->irq_cnt - 1) &&
6196 tg3_rx_prodring_alloc(tp, &tp->prodring[i]))
6204 * Must not be invoked with interrupt sources disabled and
6205 * the hardware shutdown down.
6207 static void tg3_free_consistent(struct tg3 *tp)
6211 for (i = 0; i < tp->irq_cnt; i++) {
6212 struct tg3_napi *tnapi = &tp->napi[i];
6214 if (tnapi->tx_ring) {
6215 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
6216 tnapi->tx_ring, tnapi->tx_desc_mapping);
6217 tnapi->tx_ring = NULL;
6220 kfree(tnapi->tx_buffers);
6221 tnapi->tx_buffers = NULL;
6223 if (tnapi->rx_rcb) {
6224 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
6226 tnapi->rx_rcb_mapping);
6227 tnapi->rx_rcb = NULL;
6230 if (tnapi->hw_status) {
6231 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
6233 tnapi->status_mapping);
6234 tnapi->hw_status = NULL;
6239 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
6240 tp->hw_stats, tp->stats_mapping);
6241 tp->hw_stats = NULL;
6244 for (i = 0; i < (tp->irq_cnt == 1 ? 1 : tp->irq_cnt - 1); i++)
6245 tg3_rx_prodring_fini(tp, &tp->prodring[i]);
6249 * Must not be invoked with interrupt sources disabled and
6250 * the hardware shutdown down. Can sleep.
6252 static int tg3_alloc_consistent(struct tg3 *tp)
6256 for (i = 0; i < (tp->irq_cnt == 1 ? 1 : tp->irq_cnt - 1); i++) {
6257 if (tg3_rx_prodring_init(tp, &tp->prodring[i]))
6261 tp->hw_stats = pci_alloc_consistent(tp->pdev,
6262 sizeof(struct tg3_hw_stats),
6263 &tp->stats_mapping);
6267 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6269 for (i = 0; i < tp->irq_cnt; i++) {
6270 struct tg3_napi *tnapi = &tp->napi[i];
6271 struct tg3_hw_status *sblk;
6273 tnapi->hw_status = pci_alloc_consistent(tp->pdev,
6275 &tnapi->status_mapping);
6276 if (!tnapi->hw_status)
6279 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6280 sblk = tnapi->hw_status;
6283 * When RSS is enabled, the status block format changes
6284 * slightly. The "rx_jumbo_consumer", "reserved",
6285 * and "rx_mini_consumer" members get mapped to the
6286 * other three rx return ring producer indexes.
6290 tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
6293 tnapi->rx_rcb_prod_idx = &sblk->rx_jumbo_consumer;
6296 tnapi->rx_rcb_prod_idx = &sblk->reserved;
6299 tnapi->rx_rcb_prod_idx = &sblk->rx_mini_consumer;
6303 if (tp->irq_cnt == 1)
6304 tnapi->prodring = &tp->prodring[0];
6306 tnapi->prodring = &tp->prodring[i - 1];
6309 * If multivector RSS is enabled, vector 0 does not handle
6310 * rx or tx interrupts. Don't allocate any resources for it.
6312 if (!i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS))
6315 tnapi->rx_rcb = pci_alloc_consistent(tp->pdev,
6316 TG3_RX_RCB_RING_BYTES(tp),
6317 &tnapi->rx_rcb_mapping);
6321 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
6323 tnapi->tx_buffers = kzalloc(sizeof(struct ring_info) *
6324 TG3_TX_RING_SIZE, GFP_KERNEL);
6325 if (!tnapi->tx_buffers)
6328 tnapi->tx_ring = pci_alloc_consistent(tp->pdev,
6330 &tnapi->tx_desc_mapping);
6331 if (!tnapi->tx_ring)
6338 tg3_free_consistent(tp);
6342 #define MAX_WAIT_CNT 1000
6344 /* To stop a block, clear the enable bit and poll till it
6345 * clears. tp->lock is held.
6347 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
6352 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6359 /* We can't enable/disable these bits of the
6360 * 5705/5750, just say success.
6373 for (i = 0; i < MAX_WAIT_CNT; i++) {
6376 if ((val & enable_bit) == 0)
6380 if (i == MAX_WAIT_CNT && !silent) {
6381 printk(KERN_ERR PFX "tg3_stop_block timed out, "
6382 "ofs=%lx enable_bit=%x\n",
6390 /* tp->lock is held. */
6391 static int tg3_abort_hw(struct tg3 *tp, int silent)
6395 tg3_disable_ints(tp);
6397 tp->rx_mode &= ~RX_MODE_ENABLE;
6398 tw32_f(MAC_RX_MODE, tp->rx_mode);
6401 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
6402 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
6403 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
6404 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
6405 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
6406 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
6408 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
6409 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
6410 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
6411 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
6412 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
6413 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
6414 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
6416 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
6417 tw32_f(MAC_MODE, tp->mac_mode);
6420 tp->tx_mode &= ~TX_MODE_ENABLE;
6421 tw32_f(MAC_TX_MODE, tp->tx_mode);
6423 for (i = 0; i < MAX_WAIT_CNT; i++) {
6425 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
6428 if (i >= MAX_WAIT_CNT) {
6429 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
6430 "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
6431 tp->dev->name, tr32(MAC_TX_MODE));
6435 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
6436 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
6437 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
6439 tw32(FTQ_RESET, 0xffffffff);
6440 tw32(FTQ_RESET, 0x00000000);
6442 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
6443 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
6445 for (i = 0; i < tp->irq_cnt; i++) {
6446 struct tg3_napi *tnapi = &tp->napi[i];
6447 if (tnapi->hw_status)
6448 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6451 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6456 static void tg3_ape_send_event(struct tg3 *tp, u32 event)
6461 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
6462 if (apedata != APE_SEG_SIG_MAGIC)
6465 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
6466 if (!(apedata & APE_FW_STATUS_READY))
6469 /* Wait for up to 1 millisecond for APE to service previous event. */
6470 for (i = 0; i < 10; i++) {
6471 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
6474 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
6476 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6477 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
6478 event | APE_EVENT_STATUS_EVENT_PENDING);
6480 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
6482 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6488 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6489 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
6492 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
6497 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
6501 case RESET_KIND_INIT:
6502 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
6503 APE_HOST_SEG_SIG_MAGIC);
6504 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
6505 APE_HOST_SEG_LEN_MAGIC);
6506 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
6507 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
6508 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
6509 APE_HOST_DRIVER_ID_MAGIC);
6510 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
6511 APE_HOST_BEHAV_NO_PHYLOCK);
6513 event = APE_EVENT_STATUS_STATE_START;
6515 case RESET_KIND_SHUTDOWN:
6516 /* With the interface we are currently using,
6517 * APE does not track driver state. Wiping
6518 * out the HOST SEGMENT SIGNATURE forces
6519 * the APE to assume OS absent status.
6521 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
6523 event = APE_EVENT_STATUS_STATE_UNLOAD;
6525 case RESET_KIND_SUSPEND:
6526 event = APE_EVENT_STATUS_STATE_SUSPEND;
6532 event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
6534 tg3_ape_send_event(tp, event);
6537 /* tp->lock is held. */
6538 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
6540 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
6541 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
6543 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6545 case RESET_KIND_INIT:
6546 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6550 case RESET_KIND_SHUTDOWN:
6551 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6555 case RESET_KIND_SUSPEND:
6556 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6565 if (kind == RESET_KIND_INIT ||
6566 kind == RESET_KIND_SUSPEND)
6567 tg3_ape_driver_state_change(tp, kind);
6570 /* tp->lock is held. */
6571 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
6573 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6575 case RESET_KIND_INIT:
6576 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6577 DRV_STATE_START_DONE);
6580 case RESET_KIND_SHUTDOWN:
6581 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6582 DRV_STATE_UNLOAD_DONE);
6590 if (kind == RESET_KIND_SHUTDOWN)
6591 tg3_ape_driver_state_change(tp, kind);
6594 /* tp->lock is held. */
6595 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
6597 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6599 case RESET_KIND_INIT:
6600 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6604 case RESET_KIND_SHUTDOWN:
6605 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6609 case RESET_KIND_SUSPEND:
6610 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6620 static int tg3_poll_fw(struct tg3 *tp)
6625 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6626 /* Wait up to 20ms for init done. */
6627 for (i = 0; i < 200; i++) {
6628 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
6635 /* Wait for firmware initialization to complete. */
6636 for (i = 0; i < 100000; i++) {
6637 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
6638 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
6643 /* Chip might not be fitted with firmware. Some Sun onboard
6644 * parts are configured like that. So don't signal the timeout
6645 * of the above loop as an error, but do report the lack of
6646 * running firmware once.
6649 !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
6650 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
6652 printk(KERN_INFO PFX "%s: No firmware running.\n",
6659 /* Save PCI command register before chip reset */
6660 static void tg3_save_pci_state(struct tg3 *tp)
6662 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
6665 /* Restore PCI state after chip reset */
6666 static void tg3_restore_pci_state(struct tg3 *tp)
6670 /* Re-enable indirect register accesses. */
6671 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
6672 tp->misc_host_ctrl);
6674 /* Set MAX PCI retry to zero. */
6675 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
6676 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6677 (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
6678 val |= PCISTATE_RETRY_SAME_DMA;
6679 /* Allow reads and writes to the APE register and memory space. */
6680 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
6681 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6682 PCISTATE_ALLOW_APE_SHMEM_WR;
6683 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
6685 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
6687 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
6688 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6689 pcie_set_readrq(tp->pdev, 4096);
6691 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
6692 tp->pci_cacheline_sz);
6693 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
6698 /* Make sure PCI-X relaxed ordering bit is clear. */
6699 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
6702 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6704 pcix_cmd &= ~PCI_X_CMD_ERO;
6705 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6709 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
6711 /* Chip reset on 5780 will reset MSI enable bit,
6712 * so need to restore it.
6714 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6717 pci_read_config_word(tp->pdev,
6718 tp->msi_cap + PCI_MSI_FLAGS,
6720 pci_write_config_word(tp->pdev,
6721 tp->msi_cap + PCI_MSI_FLAGS,
6722 ctrl | PCI_MSI_FLAGS_ENABLE);
6723 val = tr32(MSGINT_MODE);
6724 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
6729 static void tg3_stop_fw(struct tg3 *);
6731 /* tp->lock is held. */
6732 static int tg3_chip_reset(struct tg3 *tp)
6735 void (*write_op)(struct tg3 *, u32, u32);
6740 tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
6742 /* No matching tg3_nvram_unlock() after this because
6743 * chip reset below will undo the nvram lock.
6745 tp->nvram_lock_cnt = 0;
6747 /* GRC_MISC_CFG core clock reset will clear the memory
6748 * enable bit in PCI register 4 and the MSI enable bit
6749 * on some chips, so we save relevant registers here.
6751 tg3_save_pci_state(tp);
6753 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
6754 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
6755 tw32(GRC_FASTBOOT_PC, 0);
6758 * We must avoid the readl() that normally takes place.
6759 * It locks machines, causes machine checks, and other
6760 * fun things. So, temporarily disable the 5701
6761 * hardware workaround, while we do the reset.
6763 write_op = tp->write32;
6764 if (write_op == tg3_write_flush_reg32)
6765 tp->write32 = tg3_write32;
6767 /* Prevent the irq handler from reading or writing PCI registers
6768 * during chip reset when the memory enable bit in the PCI command
6769 * register may be cleared. The chip does not generate interrupt
6770 * at this time, but the irq handler may still be called due to irq
6771 * sharing or irqpoll.
6773 tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
6774 for (i = 0; i < tp->irq_cnt; i++) {
6775 struct tg3_napi *tnapi = &tp->napi[i];
6776 if (tnapi->hw_status) {
6777 tnapi->hw_status->status = 0;
6778 tnapi->hw_status->status_tag = 0;
6780 tnapi->last_tag = 0;
6781 tnapi->last_irq_tag = 0;
6785 for (i = 0; i < tp->irq_cnt; i++)
6786 synchronize_irq(tp->napi[i].irq_vec);
6788 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6789 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
6790 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
6794 val = GRC_MISC_CFG_CORECLK_RESET;
6796 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
6797 if (tr32(0x7e2c) == 0x60) {
6800 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
6801 tw32(GRC_MISC_CFG, (1 << 29));
6806 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6807 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
6808 tw32(GRC_VCPU_EXT_CTRL,
6809 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
6812 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6813 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
6814 tw32(GRC_MISC_CFG, val);
6816 /* restore 5701 hardware bug workaround write method */
6817 tp->write32 = write_op;
6819 /* Unfortunately, we have to delay before the PCI read back.
6820 * Some 575X chips even will not respond to a PCI cfg access
6821 * when the reset command is given to the chip.
6823 * How do these hardware designers expect things to work
6824 * properly if the PCI write is posted for a long period
6825 * of time? It is always necessary to have some method by
6826 * which a register read back can occur to push the write
6827 * out which does the reset.
6829 * For most tg3 variants the trick below was working.
6834 /* Flush PCI posted writes. The normal MMIO registers
6835 * are inaccessible at this time so this is the only
6836 * way to make this reliably (actually, this is no longer
6837 * the case, see above). I tried to use indirect
6838 * register read/write but this upset some 5701 variants.
6840 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
6844 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
6847 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
6851 /* Wait for link training to complete. */
6852 for (i = 0; i < 5000; i++)
6855 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
6856 pci_write_config_dword(tp->pdev, 0xc4,
6857 cfg_val | (1 << 15));
6860 /* Clear the "no snoop" and "relaxed ordering" bits. */
6861 pci_read_config_word(tp->pdev,
6862 tp->pcie_cap + PCI_EXP_DEVCTL,
6864 val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
6865 PCI_EXP_DEVCTL_NOSNOOP_EN);
6867 * Older PCIe devices only support the 128 byte
6868 * MPS setting. Enforce the restriction.
6870 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
6871 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784))
6872 val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
6873 pci_write_config_word(tp->pdev,
6874 tp->pcie_cap + PCI_EXP_DEVCTL,
6877 pcie_set_readrq(tp->pdev, 4096);
6879 /* Clear error status */
6880 pci_write_config_word(tp->pdev,
6881 tp->pcie_cap + PCI_EXP_DEVSTA,
6882 PCI_EXP_DEVSTA_CED |
6883 PCI_EXP_DEVSTA_NFED |
6884 PCI_EXP_DEVSTA_FED |
6885 PCI_EXP_DEVSTA_URD);
6888 tg3_restore_pci_state(tp);
6890 tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
6893 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
6894 val = tr32(MEMARB_MODE);
6895 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
6897 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
6899 tw32(0x5000, 0x400);
6902 tw32(GRC_MODE, tp->grc_mode);
6904 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
6907 tw32(0xc4, val | (1 << 15));
6910 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
6911 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6912 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
6913 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
6914 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
6915 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6918 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6919 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
6920 tw32_f(MAC_MODE, tp->mac_mode);
6921 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
6922 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
6923 tw32_f(MAC_MODE, tp->mac_mode);
6924 } else if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
6925 tp->mac_mode &= (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
6926 if (tp->mac_mode & MAC_MODE_APE_TX_EN)
6927 tp->mac_mode |= MAC_MODE_TDE_ENABLE;
6928 tw32_f(MAC_MODE, tp->mac_mode);
6930 tw32_f(MAC_MODE, 0);
6933 tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
6935 err = tg3_poll_fw(tp);
6941 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6944 phy_addr = tp->phy_addr;
6945 tp->phy_addr = TG3_PHY_PCIE_ADDR;
6947 tg3_writephy(tp, TG3_PCIEPHY_BLOCK_ADDR,
6948 TG3_PCIEPHY_TXB_BLK << TG3_PCIEPHY_BLOCK_SHIFT);
6949 val = TG3_PCIEPHY_TX0CTRL1_TXOCM | TG3_PCIEPHY_TX0CTRL1_RDCTL |
6950 TG3_PCIEPHY_TX0CTRL1_TXCMV | TG3_PCIEPHY_TX0CTRL1_TKSEL |
6951 TG3_PCIEPHY_TX0CTRL1_NB_EN;
6952 tg3_writephy(tp, TG3_PCIEPHY_TX0CTRL1, val);
6955 tg3_writephy(tp, TG3_PCIEPHY_BLOCK_ADDR,
6956 TG3_PCIEPHY_XGXS_BLK1 << TG3_PCIEPHY_BLOCK_SHIFT);
6957 val = TG3_PCIEPHY_PWRMGMT4_LOWPWR_EN |
6958 TG3_PCIEPHY_PWRMGMT4_L1PLLPD_EN;
6959 tg3_writephy(tp, TG3_PCIEPHY_PWRMGMT4, val);
6962 tp->phy_addr = phy_addr;
6965 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
6966 tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
6967 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
6968 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) {
6971 tw32(0x7c00, val | (1 << 25));
6974 /* Reprobe ASF enable state. */
6975 tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
6976 tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
6977 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
6978 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
6981 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
6982 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
6983 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
6984 tp->last_event_jiffies = jiffies;
6985 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
6986 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
6993 /* tp->lock is held. */
6994 static void tg3_stop_fw(struct tg3 *tp)
6996 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
6997 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
6998 /* Wait for RX cpu to ACK the previous event. */
6999 tg3_wait_for_event_ack(tp);
7001 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
7003 tg3_generate_fw_event(tp);
7005 /* Wait for RX cpu to ACK this event. */
7006 tg3_wait_for_event_ack(tp);
7010 /* tp->lock is held. */
7011 static int tg3_halt(struct tg3 *tp, int kind, int silent)
7017 tg3_write_sig_pre_reset(tp, kind);
7019 tg3_abort_hw(tp, silent);
7020 err = tg3_chip_reset(tp);
7022 __tg3_set_mac_addr(tp, 0);
7024 tg3_write_sig_legacy(tp, kind);
7025 tg3_write_sig_post_reset(tp, kind);
7033 #define RX_CPU_SCRATCH_BASE 0x30000
7034 #define RX_CPU_SCRATCH_SIZE 0x04000
7035 #define TX_CPU_SCRATCH_BASE 0x34000
7036 #define TX_CPU_SCRATCH_SIZE 0x04000
7038 /* tp->lock is held. */
7039 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
7043 BUG_ON(offset == TX_CPU_BASE &&
7044 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
7046 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7047 u32 val = tr32(GRC_VCPU_EXT_CTRL);
7049 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
7052 if (offset == RX_CPU_BASE) {
7053 for (i = 0; i < 10000; i++) {
7054 tw32(offset + CPU_STATE, 0xffffffff);
7055 tw32(offset + CPU_MODE, CPU_MODE_HALT);
7056 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7060 tw32(offset + CPU_STATE, 0xffffffff);
7061 tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
7064 for (i = 0; i < 10000; i++) {
7065 tw32(offset + CPU_STATE, 0xffffffff);
7066 tw32(offset + CPU_MODE, CPU_MODE_HALT);
7067 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7073 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
7076 (offset == RX_CPU_BASE ? "RX" : "TX"));
7080 /* Clear firmware's nvram arbitration. */
7081 if (tp->tg3_flags & TG3_FLAG_NVRAM)
7082 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
7087 unsigned int fw_base;
7088 unsigned int fw_len;
7089 const __be32 *fw_data;
7092 /* tp->lock is held. */
7093 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
7094 int cpu_scratch_size, struct fw_info *info)
7096 int err, lock_err, i;
7097 void (*write_op)(struct tg3 *, u32, u32);
7099 if (cpu_base == TX_CPU_BASE &&
7100 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7101 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
7102 "TX cpu firmware on %s which is 5705.\n",
7107 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7108 write_op = tg3_write_mem;
7110 write_op = tg3_write_indirect_reg32;
7112 /* It is possible that bootcode is still loading at this point.
7113 * Get the nvram lock first before halting the cpu.
7115 lock_err = tg3_nvram_lock(tp);
7116 err = tg3_halt_cpu(tp, cpu_base);
7118 tg3_nvram_unlock(tp);
7122 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
7123 write_op(tp, cpu_scratch_base + i, 0);
7124 tw32(cpu_base + CPU_STATE, 0xffffffff);
7125 tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
7126 for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
7127 write_op(tp, (cpu_scratch_base +
7128 (info->fw_base & 0xffff) +
7130 be32_to_cpu(info->fw_data[i]));
7138 /* tp->lock is held. */
7139 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
7141 struct fw_info info;
7142 const __be32 *fw_data;
7145 fw_data = (void *)tp->fw->data;
7147 /* Firmware blob starts with version numbers, followed by
7148 start address and length. We are setting complete length.
7149 length = end_address_of_bss - start_address_of_text.
7150 Remainder is the blob to be loaded contiguously
7151 from start address. */
7153 info.fw_base = be32_to_cpu(fw_data[1]);
7154 info.fw_len = tp->fw->size - 12;
7155 info.fw_data = &fw_data[3];
7157 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
7158 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
7163 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
7164 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
7169 /* Now startup only the RX cpu. */
7170 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7171 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
7173 for (i = 0; i < 5; i++) {
7174 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
7176 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7177 tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
7178 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
7182 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
7183 "to set RX CPU PC, is %08x should be %08x\n",
7184 tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
7188 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7189 tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
7194 /* 5705 needs a special version of the TSO firmware. */
7196 /* tp->lock is held. */
7197 static int tg3_load_tso_firmware(struct tg3 *tp)
7199 struct fw_info info;
7200 const __be32 *fw_data;
7201 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
7204 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7207 fw_data = (void *)tp->fw->data;
7209 /* Firmware blob starts with version numbers, followed by
7210 start address and length. We are setting complete length.
7211 length = end_address_of_bss - start_address_of_text.
7212 Remainder is the blob to be loaded contiguously
7213 from start address. */
7215 info.fw_base = be32_to_cpu(fw_data[1]);
7216 cpu_scratch_size = tp->fw_len;
7217 info.fw_len = tp->fw->size - 12;
7218 info.fw_data = &fw_data[3];
7220 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7221 cpu_base = RX_CPU_BASE;
7222 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
7224 cpu_base = TX_CPU_BASE;
7225 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
7226 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
7229 err = tg3_load_firmware_cpu(tp, cpu_base,
7230 cpu_scratch_base, cpu_scratch_size,
7235 /* Now startup the cpu. */
7236 tw32(cpu_base + CPU_STATE, 0xffffffff);
7237 tw32_f(cpu_base + CPU_PC, info.fw_base);
7239 for (i = 0; i < 5; i++) {
7240 if (tr32(cpu_base + CPU_PC) == info.fw_base)
7242 tw32(cpu_base + CPU_STATE, 0xffffffff);
7243 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
7244 tw32_f(cpu_base + CPU_PC, info.fw_base);
7248 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
7249 "to set CPU PC, is %08x should be %08x\n",
7250 tp->dev->name, tr32(cpu_base + CPU_PC),
7254 tw32(cpu_base + CPU_STATE, 0xffffffff);
7255 tw32_f(cpu_base + CPU_MODE, 0x00000000);
7260 static int tg3_set_mac_addr(struct net_device *dev, void *p)
7262 struct tg3 *tp = netdev_priv(dev);
7263 struct sockaddr *addr = p;
7264 int err = 0, skip_mac_1 = 0;
7266 if (!is_valid_ether_addr(addr->sa_data))
7269 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
7271 if (!netif_running(dev))
7274 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
7275 u32 addr0_high, addr0_low, addr1_high, addr1_low;
7277 addr0_high = tr32(MAC_ADDR_0_HIGH);
7278 addr0_low = tr32(MAC_ADDR_0_LOW);
7279 addr1_high = tr32(MAC_ADDR_1_HIGH);
7280 addr1_low = tr32(MAC_ADDR_1_LOW);
7282 /* Skip MAC addr 1 if ASF is using it. */
7283 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
7284 !(addr1_high == 0 && addr1_low == 0))
7287 spin_lock_bh(&tp->lock);
7288 __tg3_set_mac_addr(tp, skip_mac_1);
7289 spin_unlock_bh(&tp->lock);
7294 /* tp->lock is held. */
7295 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
7296 dma_addr_t mapping, u32 maxlen_flags,
7300 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
7301 ((u64) mapping >> 32));
7303 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
7304 ((u64) mapping & 0xffffffff));
7306 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
7309 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7311 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
7315 static void __tg3_set_rx_mode(struct net_device *);
7316 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
7320 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
7321 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
7322 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
7323 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
7325 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
7326 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
7327 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
7329 tw32(HOSTCC_TXCOL_TICKS, 0);
7330 tw32(HOSTCC_TXMAX_FRAMES, 0);
7331 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
7333 tw32(HOSTCC_RXCOL_TICKS, 0);
7334 tw32(HOSTCC_RXMAX_FRAMES, 0);
7335 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
7338 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7339 u32 val = ec->stats_block_coalesce_usecs;
7341 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
7342 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
7344 if (!netif_carrier_ok(tp->dev))
7347 tw32(HOSTCC_STAT_COAL_TICKS, val);
7350 for (i = 0; i < tp->irq_cnt - 1; i++) {
7353 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
7354 tw32(reg, ec->rx_coalesce_usecs);
7355 reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
7356 tw32(reg, ec->tx_coalesce_usecs);
7357 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
7358 tw32(reg, ec->rx_max_coalesced_frames);
7359 reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
7360 tw32(reg, ec->tx_max_coalesced_frames);
7361 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
7362 tw32(reg, ec->rx_max_coalesced_frames_irq);
7363 reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
7364 tw32(reg, ec->tx_max_coalesced_frames_irq);
7367 for (; i < tp->irq_max - 1; i++) {
7368 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
7369 tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
7370 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
7371 tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
7372 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7373 tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7377 /* tp->lock is held. */
7378 static void tg3_rings_reset(struct tg3 *tp)
7381 u32 stblk, txrcb, rxrcb, limit;
7382 struct tg3_napi *tnapi = &tp->napi[0];
7384 /* Disable all transmit rings but the first. */
7385 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7386 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
7388 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7390 for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7391 txrcb < limit; txrcb += TG3_BDINFO_SIZE)
7392 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
7393 BDINFO_FLAGS_DISABLED);
7396 /* Disable all receive return rings but the first. */
7397 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
7398 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
7399 else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7400 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
7401 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
7402 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
7404 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7406 for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7407 rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
7408 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
7409 BDINFO_FLAGS_DISABLED);
7411 /* Disable interrupts */
7412 tw32_mailbox_f(tp->napi[0].int_mbox, 1);
7414 /* Zero mailbox registers. */
7415 if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) {
7416 for (i = 1; i < TG3_IRQ_MAX_VECS; i++) {
7417 tp->napi[i].tx_prod = 0;
7418 tp->napi[i].tx_cons = 0;
7419 tw32_mailbox(tp->napi[i].prodmbox, 0);
7420 tw32_rx_mbox(tp->napi[i].consmbox, 0);
7421 tw32_mailbox_f(tp->napi[i].int_mbox, 1);
7424 tp->napi[0].tx_prod = 0;
7425 tp->napi[0].tx_cons = 0;
7426 tw32_mailbox(tp->napi[0].prodmbox, 0);
7427 tw32_rx_mbox(tp->napi[0].consmbox, 0);
7430 /* Make sure the NIC-based send BD rings are disabled. */
7431 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7432 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
7433 for (i = 0; i < 16; i++)
7434 tw32_tx_mbox(mbox + i * 8, 0);
7437 txrcb = NIC_SRAM_SEND_RCB;
7438 rxrcb = NIC_SRAM_RCV_RET_RCB;
7440 /* Clear status block in ram. */
7441 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7443 /* Set status block DMA address */
7444 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7445 ((u64) tnapi->status_mapping >> 32));
7446 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7447 ((u64) tnapi->status_mapping & 0xffffffff));
7449 if (tnapi->tx_ring) {
7450 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7451 (TG3_TX_RING_SIZE <<
7452 BDINFO_FLAGS_MAXLEN_SHIFT),
7453 NIC_SRAM_TX_BUFFER_DESC);
7454 txrcb += TG3_BDINFO_SIZE;
7457 if (tnapi->rx_rcb) {
7458 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7459 (TG3_RX_RCB_RING_SIZE(tp) <<
7460 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7461 rxrcb += TG3_BDINFO_SIZE;
7464 stblk = HOSTCC_STATBLCK_RING1;
7466 for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
7467 u64 mapping = (u64)tnapi->status_mapping;
7468 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
7469 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
7471 /* Clear status block in ram. */
7472 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7474 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7475 (TG3_TX_RING_SIZE <<
7476 BDINFO_FLAGS_MAXLEN_SHIFT),
7477 NIC_SRAM_TX_BUFFER_DESC);
7479 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7480 (TG3_RX_RCB_RING_SIZE(tp) <<
7481 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7484 txrcb += TG3_BDINFO_SIZE;
7485 rxrcb += TG3_BDINFO_SIZE;
7489 /* tp->lock is held. */
7490 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
7492 u32 val, rdmac_mode;
7494 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
7496 tg3_disable_ints(tp);
7500 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
7502 if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
7503 tg3_abort_hw(tp, 1);
7507 !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB))
7510 err = tg3_chip_reset(tp);
7514 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
7516 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
7517 val = tr32(TG3_CPMU_CTRL);
7518 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
7519 tw32(TG3_CPMU_CTRL, val);
7521 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7522 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7523 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7524 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7526 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
7527 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
7528 val |= CPMU_LNK_AWARE_MACCLK_6_25;
7529 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
7531 val = tr32(TG3_CPMU_HST_ACC);
7532 val &= ~CPMU_HST_ACC_MACCLK_MASK;
7533 val |= CPMU_HST_ACC_MACCLK_6_25;
7534 tw32(TG3_CPMU_HST_ACC, val);
7537 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7538 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
7539 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
7540 PCIE_PWR_MGMT_L1_THRESH_4MS;
7541 tw32(PCIE_PWR_MGMT_THRESH, val);
7543 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
7544 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
7546 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
7548 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
7549 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
7552 /* This works around an issue with Athlon chipsets on
7553 * B3 tigon3 silicon. This bit has no effect on any
7554 * other revision. But do not set this on PCI Express
7555 * chips and don't even touch the clocks if the CPMU is present.
7557 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
7558 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
7559 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
7560 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7563 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
7564 (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
7565 val = tr32(TG3PCI_PCISTATE);
7566 val |= PCISTATE_RETRY_SAME_DMA;
7567 tw32(TG3PCI_PCISTATE, val);
7570 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
7571 /* Allow reads and writes to the
7572 * APE register and memory space.
7574 val = tr32(TG3PCI_PCISTATE);
7575 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
7576 PCISTATE_ALLOW_APE_SHMEM_WR;
7577 tw32(TG3PCI_PCISTATE, val);
7580 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
7581 /* Enable some hw fixes. */
7582 val = tr32(TG3PCI_MSI_DATA);
7583 val |= (1 << 26) | (1 << 28) | (1 << 29);
7584 tw32(TG3PCI_MSI_DATA, val);
7587 /* Descriptor ring init may make accesses to the
7588 * NIC SRAM area to setup the TX descriptors, so we
7589 * can only do this after the hardware has been
7590 * successfully reset.
7592 err = tg3_init_rings(tp);
7596 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
7597 val = tr32(TG3PCI_DMA_RW_CTRL) &
7598 ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
7599 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
7600 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
7601 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
7602 /* This value is determined during the probe time DMA
7603 * engine test, tg3_test_dma.
7605 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
7608 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
7609 GRC_MODE_4X_NIC_SEND_RINGS |
7610 GRC_MODE_NO_TX_PHDR_CSUM |
7611 GRC_MODE_NO_RX_PHDR_CSUM);
7612 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
7614 /* Pseudo-header checksum is done by hardware logic and not
7615 * the offload processers, so make the chip do the pseudo-
7616 * header checksums on receive. For transmit it is more
7617 * convenient to do the pseudo-header checksum in software
7618 * as Linux does that on transmit for us in all cases.
7620 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
7624 (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
7626 /* Setup the timer prescalar register. Clock is always 66Mhz. */
7627 val = tr32(GRC_MISC_CFG);
7629 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
7630 tw32(GRC_MISC_CFG, val);
7632 /* Initialize MBUF/DESC pool. */
7633 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7635 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
7636 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
7637 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
7638 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
7640 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
7641 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
7642 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
7644 else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7647 fw_len = tp->fw_len;
7648 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
7649 tw32(BUFMGR_MB_POOL_ADDR,
7650 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
7651 tw32(BUFMGR_MB_POOL_SIZE,
7652 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
7655 if (tp->dev->mtu <= ETH_DATA_LEN) {
7656 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7657 tp->bufmgr_config.mbuf_read_dma_low_water);
7658 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7659 tp->bufmgr_config.mbuf_mac_rx_low_water);
7660 tw32(BUFMGR_MB_HIGH_WATER,
7661 tp->bufmgr_config.mbuf_high_water);
7663 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7664 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
7665 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7666 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
7667 tw32(BUFMGR_MB_HIGH_WATER,
7668 tp->bufmgr_config.mbuf_high_water_jumbo);
7670 tw32(BUFMGR_DMA_LOW_WATER,
7671 tp->bufmgr_config.dma_low_water);
7672 tw32(BUFMGR_DMA_HIGH_WATER,
7673 tp->bufmgr_config.dma_high_water);
7675 tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
7676 for (i = 0; i < 2000; i++) {
7677 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
7682 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
7687 /* Setup replenish threshold. */
7688 val = tp->rx_pending / 8;
7691 else if (val > tp->rx_std_max_post)
7692 val = tp->rx_std_max_post;
7693 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7694 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
7695 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
7697 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
7698 val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
7701 tw32(RCVBDI_STD_THRESH, val);
7703 /* Initialize TG3_BDINFO's at:
7704 * RCVDBDI_STD_BD: standard eth size rx ring
7705 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
7706 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
7709 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
7710 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
7711 * ring attribute flags
7712 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
7714 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
7715 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
7717 * The size of each ring is fixed in the firmware, but the location is
7720 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7721 ((u64) tpr->rx_std_mapping >> 32));
7722 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7723 ((u64) tpr->rx_std_mapping & 0xffffffff));
7724 if (!(tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
7725 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
7726 NIC_SRAM_RX_BUFFER_DESC);
7728 /* Disable the mini ring */
7729 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7730 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
7731 BDINFO_FLAGS_DISABLED);
7733 /* Program the jumbo buffer descriptor ring control
7734 * blocks on those devices that have them.
7736 if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
7737 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
7738 /* Setup replenish threshold. */
7739 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
7741 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
7742 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7743 ((u64) tpr->rx_jmb_mapping >> 32));
7744 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7745 ((u64) tpr->rx_jmb_mapping & 0xffffffff));
7746 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7747 (RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT) |
7748 BDINFO_FLAGS_USE_EXT_RECV);
7749 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7750 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
7751 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
7753 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7754 BDINFO_FLAGS_DISABLED);
7757 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
7758 val = (RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT) |
7759 (RX_STD_MAX_SIZE << 2);
7761 val = RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT;
7763 val = RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT;
7765 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
7767 tpr->rx_std_prod_idx = tp->rx_pending;
7768 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx);
7770 tpr->rx_jmb_prod_idx = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
7771 tp->rx_jumbo_pending : 0;
7772 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx);
7774 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
7775 tw32(STD_REPLENISH_LWM, 32);
7776 tw32(JMB_REPLENISH_LWM, 16);
7779 tg3_rings_reset(tp);
7781 /* Initialize MAC address and backoff seed. */
7782 __tg3_set_mac_addr(tp, 0);
7784 /* MTU + ethernet header + FCS + optional VLAN tag */
7785 tw32(MAC_RX_MTU_SIZE,
7786 tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
7788 /* The slot time is changed by tg3_setup_phy if we
7789 * run at gigabit with half duplex.
7791 tw32(MAC_TX_LENGTHS,
7792 (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
7793 (6 << TX_LENGTHS_IPG_SHIFT) |
7794 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
7796 /* Receive rules. */
7797 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
7798 tw32(RCVLPC_CONFIG, 0x0181);
7800 /* Calculate RDMAC_MODE setting early, we need it to determine
7801 * the RCVLPC_STATE_ENABLE mask.
7803 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
7804 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
7805 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
7806 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
7807 RDMAC_MODE_LNGREAD_ENAB);
7809 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
7810 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7811 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7812 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
7813 RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
7814 RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
7816 /* If statement applies to 5705 and 5750 PCI devices only */
7817 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7818 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7819 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
7820 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
7821 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7822 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
7823 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7824 !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
7825 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7829 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
7830 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7832 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7833 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
7835 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
7836 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7837 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7838 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
7840 /* Receive/send statistics. */
7841 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7842 val = tr32(RCVLPC_STATS_ENABLE);
7843 val &= ~RCVLPC_STATSENAB_DACK_FIX;
7844 tw32(RCVLPC_STATS_ENABLE, val);
7845 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
7846 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
7847 val = tr32(RCVLPC_STATS_ENABLE);
7848 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
7849 tw32(RCVLPC_STATS_ENABLE, val);
7851 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
7853 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
7854 tw32(SNDDATAI_STATSENAB, 0xffffff);
7855 tw32(SNDDATAI_STATSCTRL,
7856 (SNDDATAI_SCTRL_ENABLE |
7857 SNDDATAI_SCTRL_FASTUPD));
7859 /* Setup host coalescing engine. */
7860 tw32(HOSTCC_MODE, 0);
7861 for (i = 0; i < 2000; i++) {
7862 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
7867 __tg3_set_coalesce(tp, &tp->coal);
7869 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7870 /* Status/statistics block address. See tg3_timer,
7871 * the tg3_periodic_fetch_stats call there, and
7872 * tg3_get_stats to see how this works for 5705/5750 chips.
7874 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7875 ((u64) tp->stats_mapping >> 32));
7876 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7877 ((u64) tp->stats_mapping & 0xffffffff));
7878 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
7880 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
7882 /* Clear statistics and status block memory areas */
7883 for (i = NIC_SRAM_STATS_BLK;
7884 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
7886 tg3_write_mem(tp, i, 0);
7891 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
7893 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
7894 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
7895 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7896 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
7898 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
7899 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
7900 /* reset to prevent losing 1st rx packet intermittently */
7901 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7905 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7906 tp->mac_mode &= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
7909 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
7910 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
7911 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7912 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7913 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
7914 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
7915 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
7918 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
7919 * If TG3_FLG2_IS_NIC is zero, we should read the
7920 * register to preserve the GPIO settings for LOMs. The GPIOs,
7921 * whether used as inputs or outputs, are set by boot code after
7924 if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
7927 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
7928 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
7929 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
7931 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
7932 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
7933 GRC_LCLCTRL_GPIO_OUTPUT3;
7935 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
7936 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
7938 tp->grc_local_ctrl &= ~gpio_mask;
7939 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
7941 /* GPIO1 must be driven high for eeprom write protect */
7942 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
7943 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
7944 GRC_LCLCTRL_GPIO_OUTPUT1);
7946 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7949 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX) {
7950 val = tr32(MSGINT_MODE);
7951 val |= MSGINT_MODE_MULTIVEC_EN | MSGINT_MODE_ENABLE;
7952 tw32(MSGINT_MODE, val);
7955 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7956 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
7960 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
7961 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
7962 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
7963 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
7964 WDMAC_MODE_LNGREAD_ENAB);
7966 /* If statement applies to 5705 and 5750 PCI devices only */
7967 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7968 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7969 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
7970 if ((tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
7971 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
7972 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
7974 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7975 !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
7976 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
7977 val |= WDMAC_MODE_RX_ACCEL;
7981 /* Enable host coalescing bug fix */
7982 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
7983 val |= WDMAC_MODE_STATUS_TAG_FIX;
7985 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
7986 val |= WDMAC_MODE_BURST_ALL_DATA;
7988 tw32_f(WDMAC_MODE, val);
7991 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
7994 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7996 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
7997 pcix_cmd &= ~PCI_X_CMD_MAX_READ;
7998 pcix_cmd |= PCI_X_CMD_READ_2K;
7999 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
8000 pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
8001 pcix_cmd |= PCI_X_CMD_READ_2K;
8003 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8007 tw32_f(RDMAC_MODE, rdmac_mode);
8010 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
8011 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8012 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
8014 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
8016 SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
8018 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
8020 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
8021 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
8022 tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
8023 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
8024 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
8025 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
8026 val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
8027 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8028 val |= SNDBDI_MODE_MULTI_TXQ_EN;
8029 tw32(SNDBDI_MODE, val);
8030 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
8032 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8033 err = tg3_load_5701_a0_firmware_fix(tp);
8038 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
8039 err = tg3_load_tso_firmware(tp);
8044 tp->tx_mode = TX_MODE_ENABLE;
8045 tw32_f(MAC_TX_MODE, tp->tx_mode);
8048 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) {
8049 u32 reg = MAC_RSS_INDIR_TBL_0;
8050 u8 *ent = (u8 *)&val;
8052 /* Setup the indirection table */
8053 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
8054 int idx = i % sizeof(val);
8056 ent[idx] = i % (tp->irq_cnt - 1);
8057 if (idx == sizeof(val) - 1) {
8063 /* Setup the "secret" hash key. */
8064 tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
8065 tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
8066 tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
8067 tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
8068 tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
8069 tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
8070 tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
8071 tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
8072 tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
8073 tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
8076 tp->rx_mode = RX_MODE_ENABLE;
8077 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
8078 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
8080 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)
8081 tp->rx_mode |= RX_MODE_RSS_ENABLE |
8082 RX_MODE_RSS_ITBL_HASH_BITS_7 |
8083 RX_MODE_RSS_IPV6_HASH_EN |
8084 RX_MODE_RSS_TCP_IPV6_HASH_EN |
8085 RX_MODE_RSS_IPV4_HASH_EN |
8086 RX_MODE_RSS_TCP_IPV4_HASH_EN;
8088 tw32_f(MAC_RX_MODE, tp->rx_mode);
8091 tw32(MAC_LED_CTRL, tp->led_ctrl);
8093 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
8094 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
8095 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8098 tw32_f(MAC_RX_MODE, tp->rx_mode);
8101 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
8102 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
8103 !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
8104 /* Set drive transmission level to 1.2V */
8105 /* only if the signal pre-emphasis bit is not set */
8106 val = tr32(MAC_SERDES_CFG);
8109 tw32(MAC_SERDES_CFG, val);
8111 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
8112 tw32(MAC_SERDES_CFG, 0x616000);
8115 /* Prevent chip from dropping frames when flow control
8118 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
8120 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
8121 (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
8122 /* Use hardware link auto-negotiation */
8123 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
8126 if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
8127 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
8130 tmp = tr32(SERDES_RX_CTRL);
8131 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
8132 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
8133 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
8134 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8137 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
8138 if (tp->link_config.phy_is_low_power) {
8139 tp->link_config.phy_is_low_power = 0;
8140 tp->link_config.speed = tp->link_config.orig_speed;
8141 tp->link_config.duplex = tp->link_config.orig_duplex;
8142 tp->link_config.autoneg = tp->link_config.orig_autoneg;
8145 err = tg3_setup_phy(tp, 0);
8149 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
8150 !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)) {
8153 /* Clear CRC stats. */
8154 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
8155 tg3_writephy(tp, MII_TG3_TEST1,
8156 tmp | MII_TG3_TEST1_CRC_EN);
8157 tg3_readphy(tp, 0x14, &tmp);
8162 __tg3_set_rx_mode(tp->dev);
8164 /* Initialize receive rules. */
8165 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
8166 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
8167 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
8168 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
8170 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
8171 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
8175 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
8179 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
8181 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
8183 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
8185 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
8187 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
8189 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
8191 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
8193 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
8195 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
8197 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
8199 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
8201 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
8203 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
8205 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
8213 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
8214 /* Write our heartbeat update interval to APE. */
8215 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
8216 APE_HOST_HEARTBEAT_INT_DISABLE);
8218 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
8223 /* Called at device open time to get the chip ready for
8224 * packet processing. Invoked with tp->lock held.
8226 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
8228 tg3_switch_clocks(tp);
8230 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
8232 return tg3_reset_hw(tp, reset_phy);
8235 #define TG3_STAT_ADD32(PSTAT, REG) \
8236 do { u32 __val = tr32(REG); \
8237 (PSTAT)->low += __val; \
8238 if ((PSTAT)->low < __val) \
8239 (PSTAT)->high += 1; \
8242 static void tg3_periodic_fetch_stats(struct tg3 *tp)
8244 struct tg3_hw_stats *sp = tp->hw_stats;
8246 if (!netif_carrier_ok(tp->dev))
8249 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
8250 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
8251 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
8252 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
8253 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
8254 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
8255 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
8256 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
8257 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
8258 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
8259 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
8260 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
8261 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
8263 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
8264 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
8265 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
8266 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
8267 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
8268 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
8269 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
8270 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
8271 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
8272 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
8273 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
8274 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
8275 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
8276 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
8278 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
8279 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
8280 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
8283 static void tg3_timer(unsigned long __opaque)
8285 struct tg3 *tp = (struct tg3 *) __opaque;
8290 spin_lock(&tp->lock);
8292 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8293 /* All of this garbage is because when using non-tagged
8294 * IRQ status the mailbox/status_block protocol the chip
8295 * uses with the cpu is race prone.
8297 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
8298 tw32(GRC_LOCAL_CTRL,
8299 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
8301 tw32(HOSTCC_MODE, tp->coalesce_mode |
8302 HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
8305 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
8306 tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
8307 spin_unlock(&tp->lock);
8308 schedule_work(&tp->reset_task);
8313 /* This part only runs once per second. */
8314 if (!--tp->timer_counter) {
8315 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
8316 tg3_periodic_fetch_stats(tp);
8318 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
8322 mac_stat = tr32(MAC_STATUS);
8325 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
8326 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
8328 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
8332 tg3_setup_phy(tp, 0);
8333 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
8334 u32 mac_stat = tr32(MAC_STATUS);
8337 if (netif_carrier_ok(tp->dev) &&
8338 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
8341 if (! netif_carrier_ok(tp->dev) &&
8342 (mac_stat & (MAC_STATUS_PCS_SYNCED |
8343 MAC_STATUS_SIGNAL_DET))) {
8347 if (!tp->serdes_counter) {
8350 ~MAC_MODE_PORT_MODE_MASK));
8352 tw32_f(MAC_MODE, tp->mac_mode);
8355 tg3_setup_phy(tp, 0);
8357 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
8358 tg3_serdes_parallel_detect(tp);
8360 tp->timer_counter = tp->timer_multiplier;
8363 /* Heartbeat is only sent once every 2 seconds.
8365 * The heartbeat is to tell the ASF firmware that the host
8366 * driver is still alive. In the event that the OS crashes,
8367 * ASF needs to reset the hardware to free up the FIFO space
8368 * that may be filled with rx packets destined for the host.
8369 * If the FIFO is full, ASF will no longer function properly.
8371 * Unintended resets have been reported on real time kernels
8372 * where the timer doesn't run on time. Netpoll will also have
8375 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
8376 * to check the ring condition when the heartbeat is expiring
8377 * before doing the reset. This will prevent most unintended
8380 if (!--tp->asf_counter) {
8381 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
8382 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
8383 tg3_wait_for_event_ack(tp);
8385 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
8386 FWCMD_NICDRV_ALIVE3);
8387 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
8388 /* 5 seconds timeout */
8389 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
8391 tg3_generate_fw_event(tp);
8393 tp->asf_counter = tp->asf_multiplier;
8396 spin_unlock(&tp->lock);
8399 tp->timer.expires = jiffies + tp->timer_offset;
8400 add_timer(&tp->timer);
8403 static int tg3_request_irq(struct tg3 *tp, int irq_num)
8406 unsigned long flags;
8408 struct tg3_napi *tnapi = &tp->napi[irq_num];
8410 if (tp->irq_cnt == 1)
8411 name = tp->dev->name;
8413 name = &tnapi->irq_lbl[0];
8414 snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num);
8415 name[IFNAMSIZ-1] = 0;
8418 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8420 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
8422 flags = IRQF_SAMPLE_RANDOM;
8425 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8426 fn = tg3_interrupt_tagged;
8427 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
8430 return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
8433 static int tg3_test_interrupt(struct tg3 *tp)
8435 struct tg3_napi *tnapi = &tp->napi[0];
8436 struct net_device *dev = tp->dev;
8437 int err, i, intr_ok = 0;
8440 if (!netif_running(dev))
8443 tg3_disable_ints(tp);
8445 free_irq(tnapi->irq_vec, tnapi);
8448 * Turn off MSI one shot mode. Otherwise this test has no
8449 * observable way to know whether the interrupt was delivered.
8451 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
8452 (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8453 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
8454 tw32(MSGINT_MODE, val);
8457 err = request_irq(tnapi->irq_vec, tg3_test_isr,
8458 IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi);
8462 tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
8463 tg3_enable_ints(tp);
8465 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8468 for (i = 0; i < 5; i++) {
8469 u32 int_mbox, misc_host_ctrl;
8471 int_mbox = tr32_mailbox(tnapi->int_mbox);
8472 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
8474 if ((int_mbox != 0) ||
8475 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
8483 tg3_disable_ints(tp);
8485 free_irq(tnapi->irq_vec, tnapi);
8487 err = tg3_request_irq(tp, 0);
8493 /* Reenable MSI one shot mode. */
8494 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
8495 (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8496 val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
8497 tw32(MSGINT_MODE, val);
8505 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
8506 * successfully restored
8508 static int tg3_test_msi(struct tg3 *tp)
8513 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
8516 /* Turn off SERR reporting in case MSI terminates with Master
8519 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
8520 pci_write_config_word(tp->pdev, PCI_COMMAND,
8521 pci_cmd & ~PCI_COMMAND_SERR);
8523 err = tg3_test_interrupt(tp);
8525 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
8530 /* other failures */
8534 /* MSI test failed, go back to INTx mode */
8535 printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
8536 "switching to INTx mode. Please report this failure to "
8537 "the PCI maintainer and include system chipset information.\n",
8540 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8542 pci_disable_msi(tp->pdev);
8544 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8546 err = tg3_request_irq(tp, 0);
8550 /* Need to reset the chip because the MSI cycle may have terminated
8551 * with Master Abort.
8553 tg3_full_lock(tp, 1);
8555 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8556 err = tg3_init_hw(tp, 1);
8558 tg3_full_unlock(tp);
8561 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8566 static int tg3_request_firmware(struct tg3 *tp)
8568 const __be32 *fw_data;
8570 if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
8571 printk(KERN_ERR "%s: Failed to load firmware \"%s\"\n",
8572 tp->dev->name, tp->fw_needed);
8576 fw_data = (void *)tp->fw->data;
8578 /* Firmware blob starts with version numbers, followed by
8579 * start address and _full_ length including BSS sections
8580 * (which must be longer than the actual data, of course
8583 tp->fw_len = be32_to_cpu(fw_data[2]); /* includes bss */
8584 if (tp->fw_len < (tp->fw->size - 12)) {
8585 printk(KERN_ERR "%s: bogus length %d in \"%s\"\n",
8586 tp->dev->name, tp->fw_len, tp->fw_needed);
8587 release_firmware(tp->fw);
8592 /* We no longer need firmware; we have it. */
8593 tp->fw_needed = NULL;
8597 static bool tg3_enable_msix(struct tg3 *tp)
8599 int i, rc, cpus = num_online_cpus();
8600 struct msix_entry msix_ent[tp->irq_max];
8603 /* Just fallback to the simpler MSI mode. */
8607 * We want as many rx rings enabled as there are cpus.
8608 * The first MSIX vector only deals with link interrupts, etc,
8609 * so we add one to the number of vectors we are requesting.
8611 tp->irq_cnt = min_t(unsigned, cpus + 1, tp->irq_max);
8613 for (i = 0; i < tp->irq_max; i++) {
8614 msix_ent[i].entry = i;
8615 msix_ent[i].vector = 0;
8618 rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
8620 if (rc < TG3_RSS_MIN_NUM_MSIX_VECS)
8622 if (pci_enable_msix(tp->pdev, msix_ent, rc))
8625 "%s: Requested %d MSI-X vectors, received %d\n",
8626 tp->dev->name, tp->irq_cnt, rc);
8630 tp->tg3_flags3 |= TG3_FLG3_ENABLE_RSS;
8632 for (i = 0; i < tp->irq_max; i++)
8633 tp->napi[i].irq_vec = msix_ent[i].vector;
8635 tp->dev->real_num_tx_queues = tp->irq_cnt - 1;
8640 static void tg3_ints_init(struct tg3 *tp)
8642 if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI_OR_MSIX) &&
8643 !(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8644 /* All MSI supporting chips should support tagged
8645 * status. Assert that this is the case.
8647 printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
8648 "Not using MSI.\n", tp->dev->name);
8652 if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) && tg3_enable_msix(tp))
8653 tp->tg3_flags2 |= TG3_FLG2_USING_MSIX;
8654 else if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) &&
8655 pci_enable_msi(tp->pdev) == 0)
8656 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
8658 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8659 u32 msi_mode = tr32(MSGINT_MODE);
8660 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8661 msi_mode |= MSGINT_MODE_MULTIVEC_EN;
8662 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
8665 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
8667 tp->napi[0].irq_vec = tp->pdev->irq;
8668 tp->dev->real_num_tx_queues = 1;
8672 static void tg3_ints_fini(struct tg3 *tp)
8674 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8675 pci_disable_msix(tp->pdev);
8676 else if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
8677 pci_disable_msi(tp->pdev);
8678 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI_OR_MSIX;
8679 tp->tg3_flags3 &= ~TG3_FLG3_ENABLE_RSS;
8682 static int tg3_open(struct net_device *dev)
8684 struct tg3 *tp = netdev_priv(dev);
8687 if (tp->fw_needed) {
8688 err = tg3_request_firmware(tp);
8689 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8693 printk(KERN_WARNING "%s: TSO capability disabled.\n",
8695 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
8696 } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8697 printk(KERN_NOTICE "%s: TSO capability restored.\n",
8699 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
8703 netif_carrier_off(tp->dev);
8705 err = tg3_set_power_state(tp, PCI_D0);
8709 tg3_full_lock(tp, 0);
8711 tg3_disable_ints(tp);
8712 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
8714 tg3_full_unlock(tp);
8717 * Setup interrupts first so we know how
8718 * many NAPI resources to allocate
8722 /* The placement of this call is tied
8723 * to the setup and use of Host TX descriptors.
8725 err = tg3_alloc_consistent(tp);
8729 tg3_napi_enable(tp);
8731 for (i = 0; i < tp->irq_cnt; i++) {
8732 struct tg3_napi *tnapi = &tp->napi[i];
8733 err = tg3_request_irq(tp, i);
8735 for (i--; i >= 0; i--)
8736 free_irq(tnapi->irq_vec, tnapi);
8744 tg3_full_lock(tp, 0);
8746 err = tg3_init_hw(tp, 1);
8748 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8751 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8752 tp->timer_offset = HZ;
8754 tp->timer_offset = HZ / 10;
8756 BUG_ON(tp->timer_offset > HZ);
8757 tp->timer_counter = tp->timer_multiplier =
8758 (HZ / tp->timer_offset);
8759 tp->asf_counter = tp->asf_multiplier =
8760 ((HZ / tp->timer_offset) * 2);
8762 init_timer(&tp->timer);
8763 tp->timer.expires = jiffies + tp->timer_offset;
8764 tp->timer.data = (unsigned long) tp;
8765 tp->timer.function = tg3_timer;
8768 tg3_full_unlock(tp);
8773 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8774 err = tg3_test_msi(tp);
8777 tg3_full_lock(tp, 0);
8778 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8780 tg3_full_unlock(tp);
8785 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
8786 (tp->tg3_flags2 & TG3_FLG2_USING_MSI) &&
8787 (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)) {
8788 u32 val = tr32(PCIE_TRANSACTION_CFG);
8790 tw32(PCIE_TRANSACTION_CFG,
8791 val | PCIE_TRANS_CFG_1SHOT_MSI);
8797 tg3_full_lock(tp, 0);
8799 add_timer(&tp->timer);
8800 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
8801 tg3_enable_ints(tp);
8803 tg3_full_unlock(tp);
8805 netif_tx_start_all_queues(dev);
8810 for (i = tp->irq_cnt - 1; i >= 0; i--) {
8811 struct tg3_napi *tnapi = &tp->napi[i];
8812 free_irq(tnapi->irq_vec, tnapi);
8816 tg3_napi_disable(tp);
8817 tg3_free_consistent(tp);
8825 /*static*/ void tg3_dump_state(struct tg3 *tp)
8827 u32 val32, val32_2, val32_3, val32_4, val32_5;
8830 struct tg3_hw_status *sblk = tp->napi[0]->hw_status;
8832 pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
8833 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
8834 printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
8838 printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
8839 tr32(MAC_MODE), tr32(MAC_STATUS));
8840 printk(" MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
8841 tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
8842 printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
8843 tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
8844 printk(" MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
8845 tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
8847 /* Send data initiator control block */
8848 printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
8849 tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
8850 printk(" SNDDATAI_STATSCTRL[%08x]\n",
8851 tr32(SNDDATAI_STATSCTRL));
8853 /* Send data completion control block */
8854 printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
8856 /* Send BD ring selector block */
8857 printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
8858 tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
8860 /* Send BD initiator control block */
8861 printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
8862 tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
8864 /* Send BD completion control block */
8865 printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
8867 /* Receive list placement control block */
8868 printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
8869 tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
8870 printk(" RCVLPC_STATSCTRL[%08x]\n",
8871 tr32(RCVLPC_STATSCTRL));
8873 /* Receive data and receive BD initiator control block */
8874 printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
8875 tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
8877 /* Receive data completion control block */
8878 printk("DEBUG: RCVDCC_MODE[%08x]\n",
8881 /* Receive BD initiator control block */
8882 printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
8883 tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
8885 /* Receive BD completion control block */
8886 printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
8887 tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
8889 /* Receive list selector control block */
8890 printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
8891 tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
8893 /* Mbuf cluster free block */
8894 printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
8895 tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
8897 /* Host coalescing control block */
8898 printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
8899 tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
8900 printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
8901 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8902 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8903 printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
8904 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8905 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8906 printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
8907 tr32(HOSTCC_STATS_BLK_NIC_ADDR));
8908 printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
8909 tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
8911 /* Memory arbiter control block */
8912 printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
8913 tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
8915 /* Buffer manager control block */
8916 printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
8917 tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
8918 printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
8919 tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
8920 printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
8921 "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
8922 tr32(BUFMGR_DMA_DESC_POOL_ADDR),
8923 tr32(BUFMGR_DMA_DESC_POOL_SIZE));
8925 /* Read DMA control block */
8926 printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
8927 tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
8929 /* Write DMA control block */
8930 printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
8931 tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
8933 /* DMA completion block */
8934 printk("DEBUG: DMAC_MODE[%08x]\n",
8938 printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
8939 tr32(GRC_MODE), tr32(GRC_MISC_CFG));
8940 printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
8941 tr32(GRC_LOCAL_CTRL));
8944 printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
8945 tr32(RCVDBDI_JUMBO_BD + 0x0),
8946 tr32(RCVDBDI_JUMBO_BD + 0x4),
8947 tr32(RCVDBDI_JUMBO_BD + 0x8),
8948 tr32(RCVDBDI_JUMBO_BD + 0xc));
8949 printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
8950 tr32(RCVDBDI_STD_BD + 0x0),
8951 tr32(RCVDBDI_STD_BD + 0x4),
8952 tr32(RCVDBDI_STD_BD + 0x8),
8953 tr32(RCVDBDI_STD_BD + 0xc));
8954 printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
8955 tr32(RCVDBDI_MINI_BD + 0x0),
8956 tr32(RCVDBDI_MINI_BD + 0x4),
8957 tr32(RCVDBDI_MINI_BD + 0x8),
8958 tr32(RCVDBDI_MINI_BD + 0xc));
8960 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
8961 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
8962 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
8963 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
8964 printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
8965 val32, val32_2, val32_3, val32_4);
8967 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
8968 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
8969 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
8970 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
8971 printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
8972 val32, val32_2, val32_3, val32_4);
8974 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
8975 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
8976 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
8977 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
8978 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
8979 printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
8980 val32, val32_2, val32_3, val32_4, val32_5);
8982 /* SW status block */
8984 "Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
8987 sblk->rx_jumbo_consumer,
8989 sblk->rx_mini_consumer,
8990 sblk->idx[0].rx_producer,
8991 sblk->idx[0].tx_consumer);
8993 /* SW statistics block */
8994 printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
8995 ((u32 *)tp->hw_stats)[0],
8996 ((u32 *)tp->hw_stats)[1],
8997 ((u32 *)tp->hw_stats)[2],
8998 ((u32 *)tp->hw_stats)[3]);
9001 printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
9002 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
9003 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
9004 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
9005 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
9007 /* NIC side send descriptors. */
9008 for (i = 0; i < 6; i++) {
9011 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
9012 + (i * sizeof(struct tg3_tx_buffer_desc));
9013 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
9015 readl(txd + 0x0), readl(txd + 0x4),
9016 readl(txd + 0x8), readl(txd + 0xc));
9019 /* NIC side RX descriptors. */
9020 for (i = 0; i < 6; i++) {
9023 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
9024 + (i * sizeof(struct tg3_rx_buffer_desc));
9025 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
9027 readl(rxd + 0x0), readl(rxd + 0x4),
9028 readl(rxd + 0x8), readl(rxd + 0xc));
9029 rxd += (4 * sizeof(u32));
9030 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
9032 readl(rxd + 0x0), readl(rxd + 0x4),
9033 readl(rxd + 0x8), readl(rxd + 0xc));
9036 for (i = 0; i < 6; i++) {
9039 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
9040 + (i * sizeof(struct tg3_rx_buffer_desc));
9041 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
9043 readl(rxd + 0x0), readl(rxd + 0x4),
9044 readl(rxd + 0x8), readl(rxd + 0xc));
9045 rxd += (4 * sizeof(u32));
9046 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
9048 readl(rxd + 0x0), readl(rxd + 0x4),
9049 readl(rxd + 0x8), readl(rxd + 0xc));
9054 static struct net_device_stats *tg3_get_stats(struct net_device *);
9055 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
9057 static int tg3_close(struct net_device *dev)
9060 struct tg3 *tp = netdev_priv(dev);
9062 tg3_napi_disable(tp);
9063 cancel_work_sync(&tp->reset_task);
9065 netif_tx_stop_all_queues(dev);
9067 del_timer_sync(&tp->timer);
9071 tg3_full_lock(tp, 1);
9076 tg3_disable_ints(tp);
9078 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9080 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
9082 tg3_full_unlock(tp);
9084 for (i = tp->irq_cnt - 1; i >= 0; i--) {
9085 struct tg3_napi *tnapi = &tp->napi[i];
9086 free_irq(tnapi->irq_vec, tnapi);
9091 memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
9092 sizeof(tp->net_stats_prev));
9093 memcpy(&tp->estats_prev, tg3_get_estats(tp),
9094 sizeof(tp->estats_prev));
9096 tg3_free_consistent(tp);
9098 tg3_set_power_state(tp, PCI_D3hot);
9100 netif_carrier_off(tp->dev);
9105 static inline unsigned long get_stat64(tg3_stat64_t *val)
9109 #if (BITS_PER_LONG == 32)
9112 ret = ((u64)val->high << 32) | ((u64)val->low);
9117 static inline u64 get_estat64(tg3_stat64_t *val)
9119 return ((u64)val->high << 32) | ((u64)val->low);
9122 static unsigned long calc_crc_errors(struct tg3 *tp)
9124 struct tg3_hw_stats *hw_stats = tp->hw_stats;
9126 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
9127 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
9128 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
9131 spin_lock_bh(&tp->lock);
9132 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
9133 tg3_writephy(tp, MII_TG3_TEST1,
9134 val | MII_TG3_TEST1_CRC_EN);
9135 tg3_readphy(tp, 0x14, &val);
9138 spin_unlock_bh(&tp->lock);
9140 tp->phy_crc_errors += val;
9142 return tp->phy_crc_errors;
9145 return get_stat64(&hw_stats->rx_fcs_errors);
9148 #define ESTAT_ADD(member) \
9149 estats->member = old_estats->member + \
9150 get_estat64(&hw_stats->member)
9152 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
9154 struct tg3_ethtool_stats *estats = &tp->estats;
9155 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
9156 struct tg3_hw_stats *hw_stats = tp->hw_stats;
9161 ESTAT_ADD(rx_octets);
9162 ESTAT_ADD(rx_fragments);
9163 ESTAT_ADD(rx_ucast_packets);
9164 ESTAT_ADD(rx_mcast_packets);
9165 ESTAT_ADD(rx_bcast_packets);
9166 ESTAT_ADD(rx_fcs_errors);
9167 ESTAT_ADD(rx_align_errors);
9168 ESTAT_ADD(rx_xon_pause_rcvd);
9169 ESTAT_ADD(rx_xoff_pause_rcvd);
9170 ESTAT_ADD(rx_mac_ctrl_rcvd);
9171 ESTAT_ADD(rx_xoff_entered);
9172 ESTAT_ADD(rx_frame_too_long_errors);
9173 ESTAT_ADD(rx_jabbers);
9174 ESTAT_ADD(rx_undersize_packets);
9175 ESTAT_ADD(rx_in_length_errors);
9176 ESTAT_ADD(rx_out_length_errors);
9177 ESTAT_ADD(rx_64_or_less_octet_packets);
9178 ESTAT_ADD(rx_65_to_127_octet_packets);
9179 ESTAT_ADD(rx_128_to_255_octet_packets);
9180 ESTAT_ADD(rx_256_to_511_octet_packets);
9181 ESTAT_ADD(rx_512_to_1023_octet_packets);
9182 ESTAT_ADD(rx_1024_to_1522_octet_packets);
9183 ESTAT_ADD(rx_1523_to_2047_octet_packets);
9184 ESTAT_ADD(rx_2048_to_4095_octet_packets);
9185 ESTAT_ADD(rx_4096_to_8191_octet_packets);
9186 ESTAT_ADD(rx_8192_to_9022_octet_packets);
9188 ESTAT_ADD(tx_octets);
9189 ESTAT_ADD(tx_collisions);
9190 ESTAT_ADD(tx_xon_sent);
9191 ESTAT_ADD(tx_xoff_sent);
9192 ESTAT_ADD(tx_flow_control);
9193 ESTAT_ADD(tx_mac_errors);
9194 ESTAT_ADD(tx_single_collisions);
9195 ESTAT_ADD(tx_mult_collisions);
9196 ESTAT_ADD(tx_deferred);
9197 ESTAT_ADD(tx_excessive_collisions);
9198 ESTAT_ADD(tx_late_collisions);
9199 ESTAT_ADD(tx_collide_2times);
9200 ESTAT_ADD(tx_collide_3times);
9201 ESTAT_ADD(tx_collide_4times);
9202 ESTAT_ADD(tx_collide_5times);
9203 ESTAT_ADD(tx_collide_6times);
9204 ESTAT_ADD(tx_collide_7times);
9205 ESTAT_ADD(tx_collide_8times);
9206 ESTAT_ADD(tx_collide_9times);
9207 ESTAT_ADD(tx_collide_10times);
9208 ESTAT_ADD(tx_collide_11times);
9209 ESTAT_ADD(tx_collide_12times);
9210 ESTAT_ADD(tx_collide_13times);
9211 ESTAT_ADD(tx_collide_14times);
9212 ESTAT_ADD(tx_collide_15times);
9213 ESTAT_ADD(tx_ucast_packets);
9214 ESTAT_ADD(tx_mcast_packets);
9215 ESTAT_ADD(tx_bcast_packets);
9216 ESTAT_ADD(tx_carrier_sense_errors);
9217 ESTAT_ADD(tx_discards);
9218 ESTAT_ADD(tx_errors);
9220 ESTAT_ADD(dma_writeq_full);
9221 ESTAT_ADD(dma_write_prioq_full);
9222 ESTAT_ADD(rxbds_empty);
9223 ESTAT_ADD(rx_discards);
9224 ESTAT_ADD(rx_errors);
9225 ESTAT_ADD(rx_threshold_hit);
9227 ESTAT_ADD(dma_readq_full);
9228 ESTAT_ADD(dma_read_prioq_full);
9229 ESTAT_ADD(tx_comp_queue_full);
9231 ESTAT_ADD(ring_set_send_prod_index);
9232 ESTAT_ADD(ring_status_update);
9233 ESTAT_ADD(nic_irqs);
9234 ESTAT_ADD(nic_avoided_irqs);
9235 ESTAT_ADD(nic_tx_threshold_hit);
9240 static struct net_device_stats *tg3_get_stats(struct net_device *dev)
9242 struct tg3 *tp = netdev_priv(dev);
9243 struct net_device_stats *stats = &tp->net_stats;
9244 struct net_device_stats *old_stats = &tp->net_stats_prev;
9245 struct tg3_hw_stats *hw_stats = tp->hw_stats;
9250 stats->rx_packets = old_stats->rx_packets +
9251 get_stat64(&hw_stats->rx_ucast_packets) +
9252 get_stat64(&hw_stats->rx_mcast_packets) +
9253 get_stat64(&hw_stats->rx_bcast_packets);
9255 stats->tx_packets = old_stats->tx_packets +
9256 get_stat64(&hw_stats->tx_ucast_packets) +
9257 get_stat64(&hw_stats->tx_mcast_packets) +
9258 get_stat64(&hw_stats->tx_bcast_packets);
9260 stats->rx_bytes = old_stats->rx_bytes +
9261 get_stat64(&hw_stats->rx_octets);
9262 stats->tx_bytes = old_stats->tx_bytes +
9263 get_stat64(&hw_stats->tx_octets);
9265 stats->rx_errors = old_stats->rx_errors +
9266 get_stat64(&hw_stats->rx_errors);
9267 stats->tx_errors = old_stats->tx_errors +
9268 get_stat64(&hw_stats->tx_errors) +
9269 get_stat64(&hw_stats->tx_mac_errors) +
9270 get_stat64(&hw_stats->tx_carrier_sense_errors) +
9271 get_stat64(&hw_stats->tx_discards);
9273 stats->multicast = old_stats->multicast +
9274 get_stat64(&hw_stats->rx_mcast_packets);
9275 stats->collisions = old_stats->collisions +
9276 get_stat64(&hw_stats->tx_collisions);
9278 stats->rx_length_errors = old_stats->rx_length_errors +
9279 get_stat64(&hw_stats->rx_frame_too_long_errors) +
9280 get_stat64(&hw_stats->rx_undersize_packets);
9282 stats->rx_over_errors = old_stats->rx_over_errors +
9283 get_stat64(&hw_stats->rxbds_empty);
9284 stats->rx_frame_errors = old_stats->rx_frame_errors +
9285 get_stat64(&hw_stats->rx_align_errors);
9286 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
9287 get_stat64(&hw_stats->tx_discards);
9288 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
9289 get_stat64(&hw_stats->tx_carrier_sense_errors);
9291 stats->rx_crc_errors = old_stats->rx_crc_errors +
9292 calc_crc_errors(tp);
9294 stats->rx_missed_errors = old_stats->rx_missed_errors +
9295 get_stat64(&hw_stats->rx_discards);
9300 static inline u32 calc_crc(unsigned char *buf, int len)
9308 for (j = 0; j < len; j++) {
9311 for (k = 0; k < 8; k++) {
9325 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
9327 /* accept or reject all multicast frames */
9328 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
9329 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
9330 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
9331 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
9334 static void __tg3_set_rx_mode(struct net_device *dev)
9336 struct tg3 *tp = netdev_priv(dev);
9339 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
9340 RX_MODE_KEEP_VLAN_TAG);
9342 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
9345 #if TG3_VLAN_TAG_USED
9347 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9348 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9350 /* By definition, VLAN is disabled always in this
9353 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9354 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9357 if (dev->flags & IFF_PROMISC) {
9358 /* Promiscuous mode. */
9359 rx_mode |= RX_MODE_PROMISC;
9360 } else if (dev->flags & IFF_ALLMULTI) {
9361 /* Accept all multicast. */
9362 tg3_set_multi (tp, 1);
9363 } else if (dev->mc_count < 1) {
9364 /* Reject all multicast. */
9365 tg3_set_multi (tp, 0);
9367 /* Accept one or more multicast(s). */
9368 struct dev_mc_list *mclist;
9370 u32 mc_filter[4] = { 0, };
9375 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
9376 i++, mclist = mclist->next) {
9378 crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
9380 regidx = (bit & 0x60) >> 5;
9382 mc_filter[regidx] |= (1 << bit);
9385 tw32(MAC_HASH_REG_0, mc_filter[0]);
9386 tw32(MAC_HASH_REG_1, mc_filter[1]);
9387 tw32(MAC_HASH_REG_2, mc_filter[2]);
9388 tw32(MAC_HASH_REG_3, mc_filter[3]);
9391 if (rx_mode != tp->rx_mode) {
9392 tp->rx_mode = rx_mode;
9393 tw32_f(MAC_RX_MODE, rx_mode);
9398 static void tg3_set_rx_mode(struct net_device *dev)
9400 struct tg3 *tp = netdev_priv(dev);
9402 if (!netif_running(dev))
9405 tg3_full_lock(tp, 0);
9406 __tg3_set_rx_mode(dev);
9407 tg3_full_unlock(tp);
9410 #define TG3_REGDUMP_LEN (32 * 1024)
9412 static int tg3_get_regs_len(struct net_device *dev)
9414 return TG3_REGDUMP_LEN;
9417 static void tg3_get_regs(struct net_device *dev,
9418 struct ethtool_regs *regs, void *_p)
9421 struct tg3 *tp = netdev_priv(dev);
9427 memset(p, 0, TG3_REGDUMP_LEN);
9429 if (tp->link_config.phy_is_low_power)
9432 tg3_full_lock(tp, 0);
9434 #define __GET_REG32(reg) (*(p)++ = tr32(reg))
9435 #define GET_REG32_LOOP(base,len) \
9436 do { p = (u32 *)(orig_p + (base)); \
9437 for (i = 0; i < len; i += 4) \
9438 __GET_REG32((base) + i); \
9440 #define GET_REG32_1(reg) \
9441 do { p = (u32 *)(orig_p + (reg)); \
9442 __GET_REG32((reg)); \
9445 GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
9446 GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
9447 GET_REG32_LOOP(MAC_MODE, 0x4f0);
9448 GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
9449 GET_REG32_1(SNDDATAC_MODE);
9450 GET_REG32_LOOP(SNDBDS_MODE, 0x80);
9451 GET_REG32_LOOP(SNDBDI_MODE, 0x48);
9452 GET_REG32_1(SNDBDC_MODE);
9453 GET_REG32_LOOP(RCVLPC_MODE, 0x20);
9454 GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
9455 GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
9456 GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
9457 GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
9458 GET_REG32_1(RCVDCC_MODE);
9459 GET_REG32_LOOP(RCVBDI_MODE, 0x20);
9460 GET_REG32_LOOP(RCVCC_MODE, 0x14);
9461 GET_REG32_LOOP(RCVLSC_MODE, 0x08);
9462 GET_REG32_1(MBFREE_MODE);
9463 GET_REG32_LOOP(HOSTCC_MODE, 0x100);
9464 GET_REG32_LOOP(MEMARB_MODE, 0x10);
9465 GET_REG32_LOOP(BUFMGR_MODE, 0x58);
9466 GET_REG32_LOOP(RDMAC_MODE, 0x08);
9467 GET_REG32_LOOP(WDMAC_MODE, 0x08);
9468 GET_REG32_1(RX_CPU_MODE);
9469 GET_REG32_1(RX_CPU_STATE);
9470 GET_REG32_1(RX_CPU_PGMCTR);
9471 GET_REG32_1(RX_CPU_HWBKPT);
9472 GET_REG32_1(TX_CPU_MODE);
9473 GET_REG32_1(TX_CPU_STATE);
9474 GET_REG32_1(TX_CPU_PGMCTR);
9475 GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
9476 GET_REG32_LOOP(FTQ_RESET, 0x120);
9477 GET_REG32_LOOP(MSGINT_MODE, 0x0c);
9478 GET_REG32_1(DMAC_MODE);
9479 GET_REG32_LOOP(GRC_MODE, 0x4c);
9480 if (tp->tg3_flags & TG3_FLAG_NVRAM)
9481 GET_REG32_LOOP(NVRAM_CMD, 0x24);
9484 #undef GET_REG32_LOOP
9487 tg3_full_unlock(tp);
9490 static int tg3_get_eeprom_len(struct net_device *dev)
9492 struct tg3 *tp = netdev_priv(dev);
9494 return tp->nvram_size;
9497 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9499 struct tg3 *tp = netdev_priv(dev);
9502 u32 i, offset, len, b_offset, b_count;
9505 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9508 if (tp->link_config.phy_is_low_power)
9511 offset = eeprom->offset;
9515 eeprom->magic = TG3_EEPROM_MAGIC;
9518 /* adjustments to start on required 4 byte boundary */
9519 b_offset = offset & 3;
9520 b_count = 4 - b_offset;
9521 if (b_count > len) {
9522 /* i.e. offset=1 len=2 */
9525 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
9528 memcpy(data, ((char*)&val) + b_offset, b_count);
9531 eeprom->len += b_count;
9534 /* read bytes upto the last 4 byte boundary */
9535 pd = &data[eeprom->len];
9536 for (i = 0; i < (len - (len & 3)); i += 4) {
9537 ret = tg3_nvram_read_be32(tp, offset + i, &val);
9542 memcpy(pd + i, &val, 4);
9547 /* read last bytes not ending on 4 byte boundary */
9548 pd = &data[eeprom->len];
9550 b_offset = offset + len - b_count;
9551 ret = tg3_nvram_read_be32(tp, b_offset, &val);
9554 memcpy(pd, &val, b_count);
9555 eeprom->len += b_count;
9560 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
9562 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9564 struct tg3 *tp = netdev_priv(dev);
9566 u32 offset, len, b_offset, odd_len;
9570 if (tp->link_config.phy_is_low_power)
9573 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
9574 eeprom->magic != TG3_EEPROM_MAGIC)
9577 offset = eeprom->offset;
9580 if ((b_offset = (offset & 3))) {
9581 /* adjustments to start on required 4 byte boundary */
9582 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
9593 /* adjustments to end on required 4 byte boundary */
9595 len = (len + 3) & ~3;
9596 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
9602 if (b_offset || odd_len) {
9603 buf = kmalloc(len, GFP_KERNEL);
9607 memcpy(buf, &start, 4);
9609 memcpy(buf+len-4, &end, 4);
9610 memcpy(buf + b_offset, data, eeprom->len);
9613 ret = tg3_nvram_write_block(tp, offset, len, buf);
9621 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9623 struct tg3 *tp = netdev_priv(dev);
9625 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9626 struct phy_device *phydev;
9627 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9629 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9630 return phy_ethtool_gset(phydev, cmd);
9633 cmd->supported = (SUPPORTED_Autoneg);
9635 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
9636 cmd->supported |= (SUPPORTED_1000baseT_Half |
9637 SUPPORTED_1000baseT_Full);
9639 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
9640 cmd->supported |= (SUPPORTED_100baseT_Half |
9641 SUPPORTED_100baseT_Full |
9642 SUPPORTED_10baseT_Half |
9643 SUPPORTED_10baseT_Full |
9645 cmd->port = PORT_TP;
9647 cmd->supported |= SUPPORTED_FIBRE;
9648 cmd->port = PORT_FIBRE;
9651 cmd->advertising = tp->link_config.advertising;
9652 if (netif_running(dev)) {
9653 cmd->speed = tp->link_config.active_speed;
9654 cmd->duplex = tp->link_config.active_duplex;
9656 cmd->phy_address = tp->phy_addr;
9657 cmd->transceiver = XCVR_INTERNAL;
9658 cmd->autoneg = tp->link_config.autoneg;
9664 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9666 struct tg3 *tp = netdev_priv(dev);
9668 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9669 struct phy_device *phydev;
9670 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9672 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9673 return phy_ethtool_sset(phydev, cmd);
9676 if (cmd->autoneg != AUTONEG_ENABLE &&
9677 cmd->autoneg != AUTONEG_DISABLE)
9680 if (cmd->autoneg == AUTONEG_DISABLE &&
9681 cmd->duplex != DUPLEX_FULL &&
9682 cmd->duplex != DUPLEX_HALF)
9685 if (cmd->autoneg == AUTONEG_ENABLE) {
9686 u32 mask = ADVERTISED_Autoneg |
9688 ADVERTISED_Asym_Pause;
9690 if (!(tp->tg3_flags2 & TG3_FLAG_10_100_ONLY))
9691 mask |= ADVERTISED_1000baseT_Half |
9692 ADVERTISED_1000baseT_Full;
9694 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
9695 mask |= ADVERTISED_100baseT_Half |
9696 ADVERTISED_100baseT_Full |
9697 ADVERTISED_10baseT_Half |
9698 ADVERTISED_10baseT_Full |
9701 mask |= ADVERTISED_FIBRE;
9703 if (cmd->advertising & ~mask)
9706 mask &= (ADVERTISED_1000baseT_Half |
9707 ADVERTISED_1000baseT_Full |
9708 ADVERTISED_100baseT_Half |
9709 ADVERTISED_100baseT_Full |
9710 ADVERTISED_10baseT_Half |
9711 ADVERTISED_10baseT_Full);
9713 cmd->advertising &= mask;
9715 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
9716 if (cmd->speed != SPEED_1000)
9719 if (cmd->duplex != DUPLEX_FULL)
9722 if (cmd->speed != SPEED_100 &&
9723 cmd->speed != SPEED_10)
9728 tg3_full_lock(tp, 0);
9730 tp->link_config.autoneg = cmd->autoneg;
9731 if (cmd->autoneg == AUTONEG_ENABLE) {
9732 tp->link_config.advertising = (cmd->advertising |
9733 ADVERTISED_Autoneg);
9734 tp->link_config.speed = SPEED_INVALID;
9735 tp->link_config.duplex = DUPLEX_INVALID;
9737 tp->link_config.advertising = 0;
9738 tp->link_config.speed = cmd->speed;
9739 tp->link_config.duplex = cmd->duplex;
9742 tp->link_config.orig_speed = tp->link_config.speed;
9743 tp->link_config.orig_duplex = tp->link_config.duplex;
9744 tp->link_config.orig_autoneg = tp->link_config.autoneg;
9746 if (netif_running(dev))
9747 tg3_setup_phy(tp, 1);
9749 tg3_full_unlock(tp);
9754 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
9756 struct tg3 *tp = netdev_priv(dev);
9758 strcpy(info->driver, DRV_MODULE_NAME);
9759 strcpy(info->version, DRV_MODULE_VERSION);
9760 strcpy(info->fw_version, tp->fw_ver);
9761 strcpy(info->bus_info, pci_name(tp->pdev));
9764 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9766 struct tg3 *tp = netdev_priv(dev);
9768 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
9769 device_can_wakeup(&tp->pdev->dev))
9770 wol->supported = WAKE_MAGIC;
9774 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
9775 device_can_wakeup(&tp->pdev->dev))
9776 wol->wolopts = WAKE_MAGIC;
9777 memset(&wol->sopass, 0, sizeof(wol->sopass));
9780 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9782 struct tg3 *tp = netdev_priv(dev);
9783 struct device *dp = &tp->pdev->dev;
9785 if (wol->wolopts & ~WAKE_MAGIC)
9787 if ((wol->wolopts & WAKE_MAGIC) &&
9788 !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
9791 spin_lock_bh(&tp->lock);
9792 if (wol->wolopts & WAKE_MAGIC) {
9793 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
9794 device_set_wakeup_enable(dp, true);
9796 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
9797 device_set_wakeup_enable(dp, false);
9799 spin_unlock_bh(&tp->lock);
9804 static u32 tg3_get_msglevel(struct net_device *dev)
9806 struct tg3 *tp = netdev_priv(dev);
9807 return tp->msg_enable;
9810 static void tg3_set_msglevel(struct net_device *dev, u32 value)
9812 struct tg3 *tp = netdev_priv(dev);
9813 tp->msg_enable = value;
9816 static int tg3_set_tso(struct net_device *dev, u32 value)
9818 struct tg3 *tp = netdev_priv(dev);
9820 if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
9825 if ((dev->features & NETIF_F_IPV6_CSUM) &&
9826 ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
9827 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3))) {
9829 dev->features |= NETIF_F_TSO6;
9830 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
9831 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9832 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
9833 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
9834 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
9835 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
9836 dev->features |= NETIF_F_TSO_ECN;
9838 dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
9840 return ethtool_op_set_tso(dev, value);
9843 static int tg3_nway_reset(struct net_device *dev)
9845 struct tg3 *tp = netdev_priv(dev);
9848 if (!netif_running(dev))
9851 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9854 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9855 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9857 r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
9861 spin_lock_bh(&tp->lock);
9863 tg3_readphy(tp, MII_BMCR, &bmcr);
9864 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
9865 ((bmcr & BMCR_ANENABLE) ||
9866 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
9867 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
9871 spin_unlock_bh(&tp->lock);
9877 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9879 struct tg3 *tp = netdev_priv(dev);
9881 ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
9882 ering->rx_mini_max_pending = 0;
9883 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9884 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
9886 ering->rx_jumbo_max_pending = 0;
9888 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
9890 ering->rx_pending = tp->rx_pending;
9891 ering->rx_mini_pending = 0;
9892 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9893 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
9895 ering->rx_jumbo_pending = 0;
9897 ering->tx_pending = tp->napi[0].tx_pending;
9900 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9902 struct tg3 *tp = netdev_priv(dev);
9903 int i, irq_sync = 0, err = 0;
9905 if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
9906 (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
9907 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
9908 (ering->tx_pending <= MAX_SKB_FRAGS) ||
9909 ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
9910 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
9913 if (netif_running(dev)) {
9919 tg3_full_lock(tp, irq_sync);
9921 tp->rx_pending = ering->rx_pending;
9923 if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
9924 tp->rx_pending > 63)
9925 tp->rx_pending = 63;
9926 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
9928 for (i = 0; i < TG3_IRQ_MAX_VECS; i++)
9929 tp->napi[i].tx_pending = ering->tx_pending;
9931 if (netif_running(dev)) {
9932 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9933 err = tg3_restart_hw(tp, 1);
9935 tg3_netif_start(tp);
9938 tg3_full_unlock(tp);
9940 if (irq_sync && !err)
9946 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9948 struct tg3 *tp = netdev_priv(dev);
9950 epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
9952 if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
9953 epause->rx_pause = 1;
9955 epause->rx_pause = 0;
9957 if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
9958 epause->tx_pause = 1;
9960 epause->tx_pause = 0;
9963 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9965 struct tg3 *tp = netdev_priv(dev);
9968 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9969 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9972 if (epause->autoneg) {
9974 struct phy_device *phydev;
9976 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9978 if (epause->rx_pause) {
9979 if (epause->tx_pause)
9980 newadv = ADVERTISED_Pause;
9982 newadv = ADVERTISED_Pause |
9983 ADVERTISED_Asym_Pause;
9984 } else if (epause->tx_pause) {
9985 newadv = ADVERTISED_Asym_Pause;
9989 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
9990 u32 oldadv = phydev->advertising &
9992 ADVERTISED_Asym_Pause);
9993 if (oldadv != newadv) {
9994 phydev->advertising &=
9995 ~(ADVERTISED_Pause |
9996 ADVERTISED_Asym_Pause);
9997 phydev->advertising |= newadv;
9998 err = phy_start_aneg(phydev);
10001 tp->link_config.advertising &=
10002 ~(ADVERTISED_Pause |
10003 ADVERTISED_Asym_Pause);
10004 tp->link_config.advertising |= newadv;
10007 if (epause->rx_pause)
10008 tp->link_config.flowctrl |= FLOW_CTRL_RX;
10010 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
10012 if (epause->tx_pause)
10013 tp->link_config.flowctrl |= FLOW_CTRL_TX;
10015 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
10017 if (netif_running(dev))
10018 tg3_setup_flow_control(tp, 0, 0);
10023 if (netif_running(dev)) {
10024 tg3_netif_stop(tp);
10028 tg3_full_lock(tp, irq_sync);
10030 if (epause->autoneg)
10031 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
10033 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
10034 if (epause->rx_pause)
10035 tp->link_config.flowctrl |= FLOW_CTRL_RX;
10037 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
10038 if (epause->tx_pause)
10039 tp->link_config.flowctrl |= FLOW_CTRL_TX;
10041 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
10043 if (netif_running(dev)) {
10044 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10045 err = tg3_restart_hw(tp, 1);
10047 tg3_netif_start(tp);
10050 tg3_full_unlock(tp);
10056 static u32 tg3_get_rx_csum(struct net_device *dev)
10058 struct tg3 *tp = netdev_priv(dev);
10059 return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
10062 static int tg3_set_rx_csum(struct net_device *dev, u32 data)
10064 struct tg3 *tp = netdev_priv(dev);
10066 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
10072 spin_lock_bh(&tp->lock);
10074 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
10076 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
10077 spin_unlock_bh(&tp->lock);
10082 static int tg3_set_tx_csum(struct net_device *dev, u32 data)
10084 struct tg3 *tp = netdev_priv(dev);
10086 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
10092 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10093 ethtool_op_set_tx_ipv6_csum(dev, data);
10095 ethtool_op_set_tx_csum(dev, data);
10100 static int tg3_get_sset_count (struct net_device *dev, int sset)
10104 return TG3_NUM_TEST;
10106 return TG3_NUM_STATS;
10108 return -EOPNOTSUPP;
10112 static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
10114 switch (stringset) {
10116 memcpy(buf, ðtool_stats_keys, sizeof(ethtool_stats_keys));
10119 memcpy(buf, ðtool_test_keys, sizeof(ethtool_test_keys));
10122 WARN_ON(1); /* we need a WARN() */
10127 static int tg3_phys_id(struct net_device *dev, u32 data)
10129 struct tg3 *tp = netdev_priv(dev);
10132 if (!netif_running(tp->dev))
10136 data = UINT_MAX / 2;
10138 for (i = 0; i < (data * 2); i++) {
10140 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10141 LED_CTRL_1000MBPS_ON |
10142 LED_CTRL_100MBPS_ON |
10143 LED_CTRL_10MBPS_ON |
10144 LED_CTRL_TRAFFIC_OVERRIDE |
10145 LED_CTRL_TRAFFIC_BLINK |
10146 LED_CTRL_TRAFFIC_LED);
10149 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10150 LED_CTRL_TRAFFIC_OVERRIDE);
10152 if (msleep_interruptible(500))
10155 tw32(MAC_LED_CTRL, tp->led_ctrl);
10159 static void tg3_get_ethtool_stats (struct net_device *dev,
10160 struct ethtool_stats *estats, u64 *tmp_stats)
10162 struct tg3 *tp = netdev_priv(dev);
10163 memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
10166 #define NVRAM_TEST_SIZE 0x100
10167 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
10168 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
10169 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
10170 #define NVRAM_SELFBOOT_HW_SIZE 0x20
10171 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
10173 static int tg3_test_nvram(struct tg3 *tp)
10177 int i, j, k, err = 0, size;
10179 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
10182 if (tg3_nvram_read(tp, 0, &magic) != 0)
10185 if (magic == TG3_EEPROM_MAGIC)
10186 size = NVRAM_TEST_SIZE;
10187 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
10188 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
10189 TG3_EEPROM_SB_FORMAT_1) {
10190 switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
10191 case TG3_EEPROM_SB_REVISION_0:
10192 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
10194 case TG3_EEPROM_SB_REVISION_2:
10195 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
10197 case TG3_EEPROM_SB_REVISION_3:
10198 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
10205 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
10206 size = NVRAM_SELFBOOT_HW_SIZE;
10210 buf = kmalloc(size, GFP_KERNEL);
10215 for (i = 0, j = 0; i < size; i += 4, j++) {
10216 err = tg3_nvram_read_be32(tp, i, &buf[j]);
10223 /* Selfboot format */
10224 magic = be32_to_cpu(buf[0]);
10225 if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
10226 TG3_EEPROM_MAGIC_FW) {
10227 u8 *buf8 = (u8 *) buf, csum8 = 0;
10229 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
10230 TG3_EEPROM_SB_REVISION_2) {
10231 /* For rev 2, the csum doesn't include the MBA. */
10232 for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
10234 for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
10237 for (i = 0; i < size; i++)
10250 if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
10251 TG3_EEPROM_MAGIC_HW) {
10252 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
10253 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
10254 u8 *buf8 = (u8 *) buf;
10256 /* Separate the parity bits and the data bytes. */
10257 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
10258 if ((i == 0) || (i == 8)) {
10262 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
10263 parity[k++] = buf8[i] & msk;
10266 else if (i == 16) {
10270 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
10271 parity[k++] = buf8[i] & msk;
10274 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
10275 parity[k++] = buf8[i] & msk;
10278 data[j++] = buf8[i];
10282 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
10283 u8 hw8 = hweight8(data[i]);
10285 if ((hw8 & 0x1) && parity[i])
10287 else if (!(hw8 & 0x1) && !parity[i])
10294 /* Bootstrap checksum at offset 0x10 */
10295 csum = calc_crc((unsigned char *) buf, 0x10);
10296 if (csum != be32_to_cpu(buf[0x10/4]))
10299 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
10300 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
10301 if (csum != be32_to_cpu(buf[0xfc/4]))
10311 #define TG3_SERDES_TIMEOUT_SEC 2
10312 #define TG3_COPPER_TIMEOUT_SEC 6
10314 static int tg3_test_link(struct tg3 *tp)
10318 if (!netif_running(tp->dev))
10321 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
10322 max = TG3_SERDES_TIMEOUT_SEC;
10324 max = TG3_COPPER_TIMEOUT_SEC;
10326 for (i = 0; i < max; i++) {
10327 if (netif_carrier_ok(tp->dev))
10330 if (msleep_interruptible(1000))
10337 /* Only test the commonly used registers */
10338 static int tg3_test_registers(struct tg3 *tp)
10340 int i, is_5705, is_5750;
10341 u32 offset, read_mask, write_mask, val, save_val, read_val;
10345 #define TG3_FL_5705 0x1
10346 #define TG3_FL_NOT_5705 0x2
10347 #define TG3_FL_NOT_5788 0x4
10348 #define TG3_FL_NOT_5750 0x8
10352 /* MAC Control Registers */
10353 { MAC_MODE, TG3_FL_NOT_5705,
10354 0x00000000, 0x00ef6f8c },
10355 { MAC_MODE, TG3_FL_5705,
10356 0x00000000, 0x01ef6b8c },
10357 { MAC_STATUS, TG3_FL_NOT_5705,
10358 0x03800107, 0x00000000 },
10359 { MAC_STATUS, TG3_FL_5705,
10360 0x03800100, 0x00000000 },
10361 { MAC_ADDR_0_HIGH, 0x0000,
10362 0x00000000, 0x0000ffff },
10363 { MAC_ADDR_0_LOW, 0x0000,
10364 0x00000000, 0xffffffff },
10365 { MAC_RX_MTU_SIZE, 0x0000,
10366 0x00000000, 0x0000ffff },
10367 { MAC_TX_MODE, 0x0000,
10368 0x00000000, 0x00000070 },
10369 { MAC_TX_LENGTHS, 0x0000,
10370 0x00000000, 0x00003fff },
10371 { MAC_RX_MODE, TG3_FL_NOT_5705,
10372 0x00000000, 0x000007fc },
10373 { MAC_RX_MODE, TG3_FL_5705,
10374 0x00000000, 0x000007dc },
10375 { MAC_HASH_REG_0, 0x0000,
10376 0x00000000, 0xffffffff },
10377 { MAC_HASH_REG_1, 0x0000,
10378 0x00000000, 0xffffffff },
10379 { MAC_HASH_REG_2, 0x0000,
10380 0x00000000, 0xffffffff },
10381 { MAC_HASH_REG_3, 0x0000,
10382 0x00000000, 0xffffffff },
10384 /* Receive Data and Receive BD Initiator Control Registers. */
10385 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
10386 0x00000000, 0xffffffff },
10387 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
10388 0x00000000, 0xffffffff },
10389 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
10390 0x00000000, 0x00000003 },
10391 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
10392 0x00000000, 0xffffffff },
10393 { RCVDBDI_STD_BD+0, 0x0000,
10394 0x00000000, 0xffffffff },
10395 { RCVDBDI_STD_BD+4, 0x0000,
10396 0x00000000, 0xffffffff },
10397 { RCVDBDI_STD_BD+8, 0x0000,
10398 0x00000000, 0xffff0002 },
10399 { RCVDBDI_STD_BD+0xc, 0x0000,
10400 0x00000000, 0xffffffff },
10402 /* Receive BD Initiator Control Registers. */
10403 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
10404 0x00000000, 0xffffffff },
10405 { RCVBDI_STD_THRESH, TG3_FL_5705,
10406 0x00000000, 0x000003ff },
10407 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
10408 0x00000000, 0xffffffff },
10410 /* Host Coalescing Control Registers. */
10411 { HOSTCC_MODE, TG3_FL_NOT_5705,
10412 0x00000000, 0x00000004 },
10413 { HOSTCC_MODE, TG3_FL_5705,
10414 0x00000000, 0x000000f6 },
10415 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
10416 0x00000000, 0xffffffff },
10417 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
10418 0x00000000, 0x000003ff },
10419 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
10420 0x00000000, 0xffffffff },
10421 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
10422 0x00000000, 0x000003ff },
10423 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
10424 0x00000000, 0xffffffff },
10425 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10426 0x00000000, 0x000000ff },
10427 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
10428 0x00000000, 0xffffffff },
10429 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10430 0x00000000, 0x000000ff },
10431 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
10432 0x00000000, 0xffffffff },
10433 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
10434 0x00000000, 0xffffffff },
10435 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10436 0x00000000, 0xffffffff },
10437 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10438 0x00000000, 0x000000ff },
10439 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10440 0x00000000, 0xffffffff },
10441 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10442 0x00000000, 0x000000ff },
10443 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
10444 0x00000000, 0xffffffff },
10445 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
10446 0x00000000, 0xffffffff },
10447 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
10448 0x00000000, 0xffffffff },
10449 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
10450 0x00000000, 0xffffffff },
10451 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
10452 0x00000000, 0xffffffff },
10453 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
10454 0xffffffff, 0x00000000 },
10455 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
10456 0xffffffff, 0x00000000 },
10458 /* Buffer Manager Control Registers. */
10459 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
10460 0x00000000, 0x007fff80 },
10461 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
10462 0x00000000, 0x007fffff },
10463 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
10464 0x00000000, 0x0000003f },
10465 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
10466 0x00000000, 0x000001ff },
10467 { BUFMGR_MB_HIGH_WATER, 0x0000,
10468 0x00000000, 0x000001ff },
10469 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
10470 0xffffffff, 0x00000000 },
10471 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
10472 0xffffffff, 0x00000000 },
10474 /* Mailbox Registers */
10475 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
10476 0x00000000, 0x000001ff },
10477 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
10478 0x00000000, 0x000001ff },
10479 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
10480 0x00000000, 0x000007ff },
10481 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
10482 0x00000000, 0x000001ff },
10484 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
10487 is_5705 = is_5750 = 0;
10488 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
10490 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10494 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
10495 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
10498 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
10501 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
10502 (reg_tbl[i].flags & TG3_FL_NOT_5788))
10505 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
10508 offset = (u32) reg_tbl[i].offset;
10509 read_mask = reg_tbl[i].read_mask;
10510 write_mask = reg_tbl[i].write_mask;
10512 /* Save the original register content */
10513 save_val = tr32(offset);
10515 /* Determine the read-only value. */
10516 read_val = save_val & read_mask;
10518 /* Write zero to the register, then make sure the read-only bits
10519 * are not changed and the read/write bits are all zeros.
10523 val = tr32(offset);
10525 /* Test the read-only and read/write bits. */
10526 if (((val & read_mask) != read_val) || (val & write_mask))
10529 /* Write ones to all the bits defined by RdMask and WrMask, then
10530 * make sure the read-only bits are not changed and the
10531 * read/write bits are all ones.
10533 tw32(offset, read_mask | write_mask);
10535 val = tr32(offset);
10537 /* Test the read-only bits. */
10538 if ((val & read_mask) != read_val)
10541 /* Test the read/write bits. */
10542 if ((val & write_mask) != write_mask)
10545 tw32(offset, save_val);
10551 if (netif_msg_hw(tp))
10552 printk(KERN_ERR PFX "Register test failed at offset %x\n",
10554 tw32(offset, save_val);
10558 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
10560 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
10564 for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
10565 for (j = 0; j < len; j += 4) {
10568 tg3_write_mem(tp, offset + j, test_pattern[i]);
10569 tg3_read_mem(tp, offset + j, &val);
10570 if (val != test_pattern[i])
10577 static int tg3_test_memory(struct tg3 *tp)
10579 static struct mem_entry {
10582 } mem_tbl_570x[] = {
10583 { 0x00000000, 0x00b50},
10584 { 0x00002000, 0x1c000},
10585 { 0xffffffff, 0x00000}
10586 }, mem_tbl_5705[] = {
10587 { 0x00000100, 0x0000c},
10588 { 0x00000200, 0x00008},
10589 { 0x00004000, 0x00800},
10590 { 0x00006000, 0x01000},
10591 { 0x00008000, 0x02000},
10592 { 0x00010000, 0x0e000},
10593 { 0xffffffff, 0x00000}
10594 }, mem_tbl_5755[] = {
10595 { 0x00000200, 0x00008},
10596 { 0x00004000, 0x00800},
10597 { 0x00006000, 0x00800},
10598 { 0x00008000, 0x02000},
10599 { 0x00010000, 0x0c000},
10600 { 0xffffffff, 0x00000}
10601 }, mem_tbl_5906[] = {
10602 { 0x00000200, 0x00008},
10603 { 0x00004000, 0x00400},
10604 { 0x00006000, 0x00400},
10605 { 0x00008000, 0x01000},
10606 { 0x00010000, 0x01000},
10607 { 0xffffffff, 0x00000}
10609 struct mem_entry *mem_tbl;
10613 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10614 mem_tbl = mem_tbl_5755;
10615 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10616 mem_tbl = mem_tbl_5906;
10617 else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
10618 mem_tbl = mem_tbl_5705;
10620 mem_tbl = mem_tbl_570x;
10622 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
10623 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
10624 mem_tbl[i].len)) != 0)
10631 #define TG3_MAC_LOOPBACK 0
10632 #define TG3_PHY_LOOPBACK 1
10634 static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
10636 u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
10637 u32 desc_idx, coal_now;
10638 struct sk_buff *skb, *rx_skb;
10641 int num_pkts, tx_len, rx_len, i, err;
10642 struct tg3_rx_buffer_desc *desc;
10643 struct tg3_napi *tnapi, *rnapi;
10644 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
10646 if (tp->irq_cnt > 1) {
10647 tnapi = &tp->napi[1];
10648 rnapi = &tp->napi[1];
10650 tnapi = &tp->napi[0];
10651 rnapi = &tp->napi[0];
10653 coal_now = tnapi->coal_now | rnapi->coal_now;
10655 if (loopback_mode == TG3_MAC_LOOPBACK) {
10656 /* HW errata - mac loopback fails in some cases on 5780.
10657 * Normal traffic and PHY loopback are not affected by
10660 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
10663 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
10664 MAC_MODE_PORT_INT_LPBACK;
10665 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10666 mac_mode |= MAC_MODE_LINK_POLARITY;
10667 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
10668 mac_mode |= MAC_MODE_PORT_MODE_MII;
10670 mac_mode |= MAC_MODE_PORT_MODE_GMII;
10671 tw32(MAC_MODE, mac_mode);
10672 } else if (loopback_mode == TG3_PHY_LOOPBACK) {
10675 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
10676 tg3_phy_fet_toggle_apd(tp, false);
10677 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
10679 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
10681 tg3_phy_toggle_automdix(tp, 0);
10683 tg3_writephy(tp, MII_BMCR, val);
10686 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
10687 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
10688 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10689 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x1800);
10690 mac_mode |= MAC_MODE_PORT_MODE_MII;
10692 mac_mode |= MAC_MODE_PORT_MODE_GMII;
10694 /* reset to prevent losing 1st rx packet intermittently */
10695 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
10696 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10698 tw32_f(MAC_RX_MODE, tp->rx_mode);
10700 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
10701 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)
10702 mac_mode &= ~MAC_MODE_LINK_POLARITY;
10703 else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411)
10704 mac_mode |= MAC_MODE_LINK_POLARITY;
10705 tg3_writephy(tp, MII_TG3_EXT_CTRL,
10706 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
10708 tw32(MAC_MODE, mac_mode);
10716 skb = netdev_alloc_skb(tp->dev, tx_len);
10720 tx_data = skb_put(skb, tx_len);
10721 memcpy(tx_data, tp->dev->dev_addr, 6);
10722 memset(tx_data + 6, 0x0, 8);
10724 tw32(MAC_RX_MTU_SIZE, tx_len + 4);
10726 for (i = 14; i < tx_len; i++)
10727 tx_data[i] = (u8) (i & 0xff);
10729 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
10730 if (pci_dma_mapping_error(tp->pdev, map)) {
10731 dev_kfree_skb(skb);
10735 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10740 rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
10744 tg3_set_txd(tnapi, tnapi->tx_prod, map, tx_len, 0, 1);
10749 tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
10750 tr32_mailbox(tnapi->prodmbox);
10754 /* 350 usec to allow enough time on some 10/100 Mbps devices. */
10755 for (i = 0; i < 35; i++) {
10756 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10761 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
10762 rx_idx = rnapi->hw_status->idx[0].rx_producer;
10763 if ((tx_idx == tnapi->tx_prod) &&
10764 (rx_idx == (rx_start_idx + num_pkts)))
10768 pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
10769 dev_kfree_skb(skb);
10771 if (tx_idx != tnapi->tx_prod)
10774 if (rx_idx != rx_start_idx + num_pkts)
10777 desc = &rnapi->rx_rcb[rx_start_idx];
10778 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
10779 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
10780 if (opaque_key != RXD_OPAQUE_RING_STD)
10783 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
10784 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
10787 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
10788 if (rx_len != tx_len)
10791 rx_skb = tpr->rx_std_buffers[desc_idx].skb;
10793 map = pci_unmap_addr(&tpr->rx_std_buffers[desc_idx], mapping);
10794 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
10796 for (i = 14; i < tx_len; i++) {
10797 if (*(rx_skb->data + i) != (u8) (i & 0xff))
10802 /* tg3_free_rings will unmap and free the rx_skb */
10807 #define TG3_MAC_LOOPBACK_FAILED 1
10808 #define TG3_PHY_LOOPBACK_FAILED 2
10809 #define TG3_LOOPBACK_FAILED (TG3_MAC_LOOPBACK_FAILED | \
10810 TG3_PHY_LOOPBACK_FAILED)
10812 static int tg3_test_loopback(struct tg3 *tp)
10817 if (!netif_running(tp->dev))
10818 return TG3_LOOPBACK_FAILED;
10820 err = tg3_reset_hw(tp, 1);
10822 return TG3_LOOPBACK_FAILED;
10824 /* Turn off gphy autopowerdown. */
10825 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10826 tg3_phy_toggle_apd(tp, false);
10828 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
10832 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
10834 /* Wait for up to 40 microseconds to acquire lock. */
10835 for (i = 0; i < 4; i++) {
10836 status = tr32(TG3_CPMU_MUTEX_GNT);
10837 if (status == CPMU_MUTEX_GNT_DRIVER)
10842 if (status != CPMU_MUTEX_GNT_DRIVER)
10843 return TG3_LOOPBACK_FAILED;
10845 /* Turn off link-based power management. */
10846 cpmuctrl = tr32(TG3_CPMU_CTRL);
10847 tw32(TG3_CPMU_CTRL,
10848 cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
10849 CPMU_CTRL_LINK_AWARE_MODE));
10852 if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
10853 err |= TG3_MAC_LOOPBACK_FAILED;
10855 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
10856 tw32(TG3_CPMU_CTRL, cpmuctrl);
10858 /* Release the mutex */
10859 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
10862 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
10863 !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
10864 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
10865 err |= TG3_PHY_LOOPBACK_FAILED;
10868 /* Re-enable gphy autopowerdown. */
10869 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10870 tg3_phy_toggle_apd(tp, true);
10875 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
10878 struct tg3 *tp = netdev_priv(dev);
10880 if (tp->link_config.phy_is_low_power)
10881 tg3_set_power_state(tp, PCI_D0);
10883 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
10885 if (tg3_test_nvram(tp) != 0) {
10886 etest->flags |= ETH_TEST_FL_FAILED;
10889 if (tg3_test_link(tp) != 0) {
10890 etest->flags |= ETH_TEST_FL_FAILED;
10893 if (etest->flags & ETH_TEST_FL_OFFLINE) {
10894 int err, err2 = 0, irq_sync = 0;
10896 if (netif_running(dev)) {
10898 tg3_netif_stop(tp);
10902 tg3_full_lock(tp, irq_sync);
10904 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
10905 err = tg3_nvram_lock(tp);
10906 tg3_halt_cpu(tp, RX_CPU_BASE);
10907 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10908 tg3_halt_cpu(tp, TX_CPU_BASE);
10910 tg3_nvram_unlock(tp);
10912 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
10915 if (tg3_test_registers(tp) != 0) {
10916 etest->flags |= ETH_TEST_FL_FAILED;
10919 if (tg3_test_memory(tp) != 0) {
10920 etest->flags |= ETH_TEST_FL_FAILED;
10923 if ((data[4] = tg3_test_loopback(tp)) != 0)
10924 etest->flags |= ETH_TEST_FL_FAILED;
10926 tg3_full_unlock(tp);
10928 if (tg3_test_interrupt(tp) != 0) {
10929 etest->flags |= ETH_TEST_FL_FAILED;
10933 tg3_full_lock(tp, 0);
10935 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10936 if (netif_running(dev)) {
10937 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
10938 err2 = tg3_restart_hw(tp, 1);
10940 tg3_netif_start(tp);
10943 tg3_full_unlock(tp);
10945 if (irq_sync && !err2)
10948 if (tp->link_config.phy_is_low_power)
10949 tg3_set_power_state(tp, PCI_D3hot);
10953 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
10955 struct mii_ioctl_data *data = if_mii(ifr);
10956 struct tg3 *tp = netdev_priv(dev);
10959 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
10960 struct phy_device *phydev;
10961 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
10963 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
10964 return phy_mii_ioctl(phydev, data, cmd);
10969 data->phy_id = tp->phy_addr;
10972 case SIOCGMIIREG: {
10975 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10976 break; /* We have no PHY */
10978 if (tp->link_config.phy_is_low_power)
10981 spin_lock_bh(&tp->lock);
10982 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
10983 spin_unlock_bh(&tp->lock);
10985 data->val_out = mii_regval;
10991 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10992 break; /* We have no PHY */
10994 if (tp->link_config.phy_is_low_power)
10997 spin_lock_bh(&tp->lock);
10998 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
10999 spin_unlock_bh(&tp->lock);
11007 return -EOPNOTSUPP;
11010 #if TG3_VLAN_TAG_USED
11011 static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
11013 struct tg3 *tp = netdev_priv(dev);
11015 if (!netif_running(dev)) {
11020 tg3_netif_stop(tp);
11022 tg3_full_lock(tp, 0);
11026 /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
11027 __tg3_set_rx_mode(dev);
11029 tg3_netif_start(tp);
11031 tg3_full_unlock(tp);
11035 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11037 struct tg3 *tp = netdev_priv(dev);
11039 memcpy(ec, &tp->coal, sizeof(*ec));
11043 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11045 struct tg3 *tp = netdev_priv(dev);
11046 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
11047 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
11049 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
11050 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
11051 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
11052 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
11053 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
11056 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
11057 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
11058 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
11059 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
11060 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
11061 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
11062 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
11063 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
11064 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
11065 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
11068 /* No rx interrupts will be generated if both are zero */
11069 if ((ec->rx_coalesce_usecs == 0) &&
11070 (ec->rx_max_coalesced_frames == 0))
11073 /* No tx interrupts will be generated if both are zero */
11074 if ((ec->tx_coalesce_usecs == 0) &&
11075 (ec->tx_max_coalesced_frames == 0))
11078 /* Only copy relevant parameters, ignore all others. */
11079 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
11080 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
11081 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
11082 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
11083 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
11084 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
11085 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
11086 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
11087 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
11089 if (netif_running(dev)) {
11090 tg3_full_lock(tp, 0);
11091 __tg3_set_coalesce(tp, &tp->coal);
11092 tg3_full_unlock(tp);
11097 static const struct ethtool_ops tg3_ethtool_ops = {
11098 .get_settings = tg3_get_settings,
11099 .set_settings = tg3_set_settings,
11100 .get_drvinfo = tg3_get_drvinfo,
11101 .get_regs_len = tg3_get_regs_len,
11102 .get_regs = tg3_get_regs,
11103 .get_wol = tg3_get_wol,
11104 .set_wol = tg3_set_wol,
11105 .get_msglevel = tg3_get_msglevel,
11106 .set_msglevel = tg3_set_msglevel,
11107 .nway_reset = tg3_nway_reset,
11108 .get_link = ethtool_op_get_link,
11109 .get_eeprom_len = tg3_get_eeprom_len,
11110 .get_eeprom = tg3_get_eeprom,
11111 .set_eeprom = tg3_set_eeprom,
11112 .get_ringparam = tg3_get_ringparam,
11113 .set_ringparam = tg3_set_ringparam,
11114 .get_pauseparam = tg3_get_pauseparam,
11115 .set_pauseparam = tg3_set_pauseparam,
11116 .get_rx_csum = tg3_get_rx_csum,
11117 .set_rx_csum = tg3_set_rx_csum,
11118 .set_tx_csum = tg3_set_tx_csum,
11119 .set_sg = ethtool_op_set_sg,
11120 .set_tso = tg3_set_tso,
11121 .self_test = tg3_self_test,
11122 .get_strings = tg3_get_strings,
11123 .phys_id = tg3_phys_id,
11124 .get_ethtool_stats = tg3_get_ethtool_stats,
11125 .get_coalesce = tg3_get_coalesce,
11126 .set_coalesce = tg3_set_coalesce,
11127 .get_sset_count = tg3_get_sset_count,
11130 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
11132 u32 cursize, val, magic;
11134 tp->nvram_size = EEPROM_CHIP_SIZE;
11136 if (tg3_nvram_read(tp, 0, &magic) != 0)
11139 if ((magic != TG3_EEPROM_MAGIC) &&
11140 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
11141 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
11145 * Size the chip by reading offsets at increasing powers of two.
11146 * When we encounter our validation signature, we know the addressing
11147 * has wrapped around, and thus have our chip size.
11151 while (cursize < tp->nvram_size) {
11152 if (tg3_nvram_read(tp, cursize, &val) != 0)
11161 tp->nvram_size = cursize;
11164 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
11168 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
11169 tg3_nvram_read(tp, 0, &val) != 0)
11172 /* Selfboot format */
11173 if (val != TG3_EEPROM_MAGIC) {
11174 tg3_get_eeprom_size(tp);
11178 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
11180 /* This is confusing. We want to operate on the
11181 * 16-bit value at offset 0xf2. The tg3_nvram_read()
11182 * call will read from NVRAM and byteswap the data
11183 * according to the byteswapping settings for all
11184 * other register accesses. This ensures the data we
11185 * want will always reside in the lower 16-bits.
11186 * However, the data in NVRAM is in LE format, which
11187 * means the data from the NVRAM read will always be
11188 * opposite the endianness of the CPU. The 16-bit
11189 * byteswap then brings the data to CPU endianness.
11191 tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
11195 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11198 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
11202 nvcfg1 = tr32(NVRAM_CFG1);
11203 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
11204 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11206 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11207 tw32(NVRAM_CFG1, nvcfg1);
11210 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
11211 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
11212 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
11213 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
11214 tp->nvram_jedecnum = JEDEC_ATMEL;
11215 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11216 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11218 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
11219 tp->nvram_jedecnum = JEDEC_ATMEL;
11220 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
11222 case FLASH_VENDOR_ATMEL_EEPROM:
11223 tp->nvram_jedecnum = JEDEC_ATMEL;
11224 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11225 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11227 case FLASH_VENDOR_ST:
11228 tp->nvram_jedecnum = JEDEC_ST;
11229 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
11230 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11232 case FLASH_VENDOR_SAIFUN:
11233 tp->nvram_jedecnum = JEDEC_SAIFUN;
11234 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
11236 case FLASH_VENDOR_SST_SMALL:
11237 case FLASH_VENDOR_SST_LARGE:
11238 tp->nvram_jedecnum = JEDEC_SST;
11239 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
11243 tp->nvram_jedecnum = JEDEC_ATMEL;
11244 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11245 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11249 static void __devinit tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
11251 switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
11252 case FLASH_5752PAGE_SIZE_256:
11253 tp->nvram_pagesize = 256;
11255 case FLASH_5752PAGE_SIZE_512:
11256 tp->nvram_pagesize = 512;
11258 case FLASH_5752PAGE_SIZE_1K:
11259 tp->nvram_pagesize = 1024;
11261 case FLASH_5752PAGE_SIZE_2K:
11262 tp->nvram_pagesize = 2048;
11264 case FLASH_5752PAGE_SIZE_4K:
11265 tp->nvram_pagesize = 4096;
11267 case FLASH_5752PAGE_SIZE_264:
11268 tp->nvram_pagesize = 264;
11270 case FLASH_5752PAGE_SIZE_528:
11271 tp->nvram_pagesize = 528;
11276 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
11280 nvcfg1 = tr32(NVRAM_CFG1);
11282 /* NVRAM protection for TPM */
11283 if (nvcfg1 & (1 << 27))
11284 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11286 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11287 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
11288 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
11289 tp->nvram_jedecnum = JEDEC_ATMEL;
11290 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11292 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11293 tp->nvram_jedecnum = JEDEC_ATMEL;
11294 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11295 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11297 case FLASH_5752VENDOR_ST_M45PE10:
11298 case FLASH_5752VENDOR_ST_M45PE20:
11299 case FLASH_5752VENDOR_ST_M45PE40:
11300 tp->nvram_jedecnum = JEDEC_ST;
11301 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11302 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11306 if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
11307 tg3_nvram_get_pagesize(tp, nvcfg1);
11309 /* For eeprom, set pagesize to maximum eeprom size */
11310 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11312 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11313 tw32(NVRAM_CFG1, nvcfg1);
11317 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
11319 u32 nvcfg1, protect = 0;
11321 nvcfg1 = tr32(NVRAM_CFG1);
11323 /* NVRAM protection for TPM */
11324 if (nvcfg1 & (1 << 27)) {
11325 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11329 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11331 case FLASH_5755VENDOR_ATMEL_FLASH_1:
11332 case FLASH_5755VENDOR_ATMEL_FLASH_2:
11333 case FLASH_5755VENDOR_ATMEL_FLASH_3:
11334 case FLASH_5755VENDOR_ATMEL_FLASH_5:
11335 tp->nvram_jedecnum = JEDEC_ATMEL;
11336 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11337 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11338 tp->nvram_pagesize = 264;
11339 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
11340 nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
11341 tp->nvram_size = (protect ? 0x3e200 :
11342 TG3_NVRAM_SIZE_512KB);
11343 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
11344 tp->nvram_size = (protect ? 0x1f200 :
11345 TG3_NVRAM_SIZE_256KB);
11347 tp->nvram_size = (protect ? 0x1f200 :
11348 TG3_NVRAM_SIZE_128KB);
11350 case FLASH_5752VENDOR_ST_M45PE10:
11351 case FLASH_5752VENDOR_ST_M45PE20:
11352 case FLASH_5752VENDOR_ST_M45PE40:
11353 tp->nvram_jedecnum = JEDEC_ST;
11354 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11355 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11356 tp->nvram_pagesize = 256;
11357 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
11358 tp->nvram_size = (protect ?
11359 TG3_NVRAM_SIZE_64KB :
11360 TG3_NVRAM_SIZE_128KB);
11361 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
11362 tp->nvram_size = (protect ?
11363 TG3_NVRAM_SIZE_64KB :
11364 TG3_NVRAM_SIZE_256KB);
11366 tp->nvram_size = (protect ?
11367 TG3_NVRAM_SIZE_128KB :
11368 TG3_NVRAM_SIZE_512KB);
11373 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
11377 nvcfg1 = tr32(NVRAM_CFG1);
11379 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11380 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
11381 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11382 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
11383 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11384 tp->nvram_jedecnum = JEDEC_ATMEL;
11385 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11386 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11388 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11389 tw32(NVRAM_CFG1, nvcfg1);
11391 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11392 case FLASH_5755VENDOR_ATMEL_FLASH_1:
11393 case FLASH_5755VENDOR_ATMEL_FLASH_2:
11394 case FLASH_5755VENDOR_ATMEL_FLASH_3:
11395 tp->nvram_jedecnum = JEDEC_ATMEL;
11396 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11397 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11398 tp->nvram_pagesize = 264;
11400 case FLASH_5752VENDOR_ST_M45PE10:
11401 case FLASH_5752VENDOR_ST_M45PE20:
11402 case FLASH_5752VENDOR_ST_M45PE40:
11403 tp->nvram_jedecnum = JEDEC_ST;
11404 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11405 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11406 tp->nvram_pagesize = 256;
11411 static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
11413 u32 nvcfg1, protect = 0;
11415 nvcfg1 = tr32(NVRAM_CFG1);
11417 /* NVRAM protection for TPM */
11418 if (nvcfg1 & (1 << 27)) {
11419 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11423 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11425 case FLASH_5761VENDOR_ATMEL_ADB021D:
11426 case FLASH_5761VENDOR_ATMEL_ADB041D:
11427 case FLASH_5761VENDOR_ATMEL_ADB081D:
11428 case FLASH_5761VENDOR_ATMEL_ADB161D:
11429 case FLASH_5761VENDOR_ATMEL_MDB021D:
11430 case FLASH_5761VENDOR_ATMEL_MDB041D:
11431 case FLASH_5761VENDOR_ATMEL_MDB081D:
11432 case FLASH_5761VENDOR_ATMEL_MDB161D:
11433 tp->nvram_jedecnum = JEDEC_ATMEL;
11434 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11435 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11436 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11437 tp->nvram_pagesize = 256;
11439 case FLASH_5761VENDOR_ST_A_M45PE20:
11440 case FLASH_5761VENDOR_ST_A_M45PE40:
11441 case FLASH_5761VENDOR_ST_A_M45PE80:
11442 case FLASH_5761VENDOR_ST_A_M45PE16:
11443 case FLASH_5761VENDOR_ST_M_M45PE20:
11444 case FLASH_5761VENDOR_ST_M_M45PE40:
11445 case FLASH_5761VENDOR_ST_M_M45PE80:
11446 case FLASH_5761VENDOR_ST_M_M45PE16:
11447 tp->nvram_jedecnum = JEDEC_ST;
11448 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11449 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11450 tp->nvram_pagesize = 256;
11455 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
11458 case FLASH_5761VENDOR_ATMEL_ADB161D:
11459 case FLASH_5761VENDOR_ATMEL_MDB161D:
11460 case FLASH_5761VENDOR_ST_A_M45PE16:
11461 case FLASH_5761VENDOR_ST_M_M45PE16:
11462 tp->nvram_size = TG3_NVRAM_SIZE_2MB;
11464 case FLASH_5761VENDOR_ATMEL_ADB081D:
11465 case FLASH_5761VENDOR_ATMEL_MDB081D:
11466 case FLASH_5761VENDOR_ST_A_M45PE80:
11467 case FLASH_5761VENDOR_ST_M_M45PE80:
11468 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
11470 case FLASH_5761VENDOR_ATMEL_ADB041D:
11471 case FLASH_5761VENDOR_ATMEL_MDB041D:
11472 case FLASH_5761VENDOR_ST_A_M45PE40:
11473 case FLASH_5761VENDOR_ST_M_M45PE40:
11474 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11476 case FLASH_5761VENDOR_ATMEL_ADB021D:
11477 case FLASH_5761VENDOR_ATMEL_MDB021D:
11478 case FLASH_5761VENDOR_ST_A_M45PE20:
11479 case FLASH_5761VENDOR_ST_M_M45PE20:
11480 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11486 static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
11488 tp->nvram_jedecnum = JEDEC_ATMEL;
11489 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11490 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11493 static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
11497 nvcfg1 = tr32(NVRAM_CFG1);
11499 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11500 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11501 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11502 tp->nvram_jedecnum = JEDEC_ATMEL;
11503 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11504 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11506 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11507 tw32(NVRAM_CFG1, nvcfg1);
11509 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11510 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11511 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11512 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11513 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11514 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11515 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11516 tp->nvram_jedecnum = JEDEC_ATMEL;
11517 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11518 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11520 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11521 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11522 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11523 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11524 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11526 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11527 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11528 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11530 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11531 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11532 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11536 case FLASH_5752VENDOR_ST_M45PE10:
11537 case FLASH_5752VENDOR_ST_M45PE20:
11538 case FLASH_5752VENDOR_ST_M45PE40:
11539 tp->nvram_jedecnum = JEDEC_ST;
11540 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11541 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11543 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11544 case FLASH_5752VENDOR_ST_M45PE10:
11545 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11547 case FLASH_5752VENDOR_ST_M45PE20:
11548 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11550 case FLASH_5752VENDOR_ST_M45PE40:
11551 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11556 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11560 tg3_nvram_get_pagesize(tp, nvcfg1);
11561 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11562 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11566 static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp)
11570 nvcfg1 = tr32(NVRAM_CFG1);
11572 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11573 case FLASH_5717VENDOR_ATMEL_EEPROM:
11574 case FLASH_5717VENDOR_MICRO_EEPROM:
11575 tp->nvram_jedecnum = JEDEC_ATMEL;
11576 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11577 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11579 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11580 tw32(NVRAM_CFG1, nvcfg1);
11582 case FLASH_5717VENDOR_ATMEL_MDB011D:
11583 case FLASH_5717VENDOR_ATMEL_ADB011B:
11584 case FLASH_5717VENDOR_ATMEL_ADB011D:
11585 case FLASH_5717VENDOR_ATMEL_MDB021D:
11586 case FLASH_5717VENDOR_ATMEL_ADB021B:
11587 case FLASH_5717VENDOR_ATMEL_ADB021D:
11588 case FLASH_5717VENDOR_ATMEL_45USPT:
11589 tp->nvram_jedecnum = JEDEC_ATMEL;
11590 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11591 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11593 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11594 case FLASH_5717VENDOR_ATMEL_MDB021D:
11595 case FLASH_5717VENDOR_ATMEL_ADB021B:
11596 case FLASH_5717VENDOR_ATMEL_ADB021D:
11597 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11600 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11604 case FLASH_5717VENDOR_ST_M_M25PE10:
11605 case FLASH_5717VENDOR_ST_A_M25PE10:
11606 case FLASH_5717VENDOR_ST_M_M45PE10:
11607 case FLASH_5717VENDOR_ST_A_M45PE10:
11608 case FLASH_5717VENDOR_ST_M_M25PE20:
11609 case FLASH_5717VENDOR_ST_A_M25PE20:
11610 case FLASH_5717VENDOR_ST_M_M45PE20:
11611 case FLASH_5717VENDOR_ST_A_M45PE20:
11612 case FLASH_5717VENDOR_ST_25USPT:
11613 case FLASH_5717VENDOR_ST_45USPT:
11614 tp->nvram_jedecnum = JEDEC_ST;
11615 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11616 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11618 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11619 case FLASH_5717VENDOR_ST_M_M25PE20:
11620 case FLASH_5717VENDOR_ST_A_M25PE20:
11621 case FLASH_5717VENDOR_ST_M_M45PE20:
11622 case FLASH_5717VENDOR_ST_A_M45PE20:
11623 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11626 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11631 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11635 tg3_nvram_get_pagesize(tp, nvcfg1);
11636 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11637 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11640 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
11641 static void __devinit tg3_nvram_init(struct tg3 *tp)
11643 tw32_f(GRC_EEPROM_ADDR,
11644 (EEPROM_ADDR_FSM_RESET |
11645 (EEPROM_DEFAULT_CLOCK_PERIOD <<
11646 EEPROM_ADDR_CLKPERD_SHIFT)));
11650 /* Enable seeprom accesses. */
11651 tw32_f(GRC_LOCAL_CTRL,
11652 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
11655 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11656 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
11657 tp->tg3_flags |= TG3_FLAG_NVRAM;
11659 if (tg3_nvram_lock(tp)) {
11660 printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
11661 "tg3_nvram_init failed.\n", tp->dev->name);
11664 tg3_enable_nvram_access(tp);
11666 tp->nvram_size = 0;
11668 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
11669 tg3_get_5752_nvram_info(tp);
11670 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
11671 tg3_get_5755_nvram_info(tp);
11672 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
11673 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11674 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11675 tg3_get_5787_nvram_info(tp);
11676 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
11677 tg3_get_5761_nvram_info(tp);
11678 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11679 tg3_get_5906_nvram_info(tp);
11680 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
11681 tg3_get_57780_nvram_info(tp);
11682 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
11683 tg3_get_5717_nvram_info(tp);
11685 tg3_get_nvram_info(tp);
11687 if (tp->nvram_size == 0)
11688 tg3_get_nvram_size(tp);
11690 tg3_disable_nvram_access(tp);
11691 tg3_nvram_unlock(tp);
11694 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
11696 tg3_get_eeprom_size(tp);
11700 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
11701 u32 offset, u32 len, u8 *buf)
11706 for (i = 0; i < len; i += 4) {
11712 memcpy(&data, buf + i, 4);
11715 * The SEEPROM interface expects the data to always be opposite
11716 * the native endian format. We accomplish this by reversing
11717 * all the operations that would have been performed on the
11718 * data from a call to tg3_nvram_read_be32().
11720 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
11722 val = tr32(GRC_EEPROM_ADDR);
11723 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
11725 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
11727 tw32(GRC_EEPROM_ADDR, val |
11728 (0 << EEPROM_ADDR_DEVID_SHIFT) |
11729 (addr & EEPROM_ADDR_ADDR_MASK) |
11730 EEPROM_ADDR_START |
11731 EEPROM_ADDR_WRITE);
11733 for (j = 0; j < 1000; j++) {
11734 val = tr32(GRC_EEPROM_ADDR);
11736 if (val & EEPROM_ADDR_COMPLETE)
11740 if (!(val & EEPROM_ADDR_COMPLETE)) {
11749 /* offset and length are dword aligned */
11750 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
11754 u32 pagesize = tp->nvram_pagesize;
11755 u32 pagemask = pagesize - 1;
11759 tmp = kmalloc(pagesize, GFP_KERNEL);
11765 u32 phy_addr, page_off, size;
11767 phy_addr = offset & ~pagemask;
11769 for (j = 0; j < pagesize; j += 4) {
11770 ret = tg3_nvram_read_be32(tp, phy_addr + j,
11771 (__be32 *) (tmp + j));
11778 page_off = offset & pagemask;
11785 memcpy(tmp + page_off, buf, size);
11787 offset = offset + (pagesize - page_off);
11789 tg3_enable_nvram_access(tp);
11792 * Before we can erase the flash page, we need
11793 * to issue a special "write enable" command.
11795 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11797 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11800 /* Erase the target page */
11801 tw32(NVRAM_ADDR, phy_addr);
11803 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
11804 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
11806 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11809 /* Issue another write enable to start the write. */
11810 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11812 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11815 for (j = 0; j < pagesize; j += 4) {
11818 data = *((__be32 *) (tmp + j));
11820 tw32(NVRAM_WRDATA, be32_to_cpu(data));
11822 tw32(NVRAM_ADDR, phy_addr + j);
11824 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
11828 nvram_cmd |= NVRAM_CMD_FIRST;
11829 else if (j == (pagesize - 4))
11830 nvram_cmd |= NVRAM_CMD_LAST;
11832 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11839 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11840 tg3_nvram_exec_cmd(tp, nvram_cmd);
11847 /* offset and length are dword aligned */
11848 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
11853 for (i = 0; i < len; i += 4, offset += 4) {
11854 u32 page_off, phy_addr, nvram_cmd;
11857 memcpy(&data, buf + i, 4);
11858 tw32(NVRAM_WRDATA, be32_to_cpu(data));
11860 page_off = offset % tp->nvram_pagesize;
11862 phy_addr = tg3_nvram_phys_addr(tp, offset);
11864 tw32(NVRAM_ADDR, phy_addr);
11866 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
11868 if ((page_off == 0) || (i == 0))
11869 nvram_cmd |= NVRAM_CMD_FIRST;
11870 if (page_off == (tp->nvram_pagesize - 4))
11871 nvram_cmd |= NVRAM_CMD_LAST;
11873 if (i == (len - 4))
11874 nvram_cmd |= NVRAM_CMD_LAST;
11876 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
11877 !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
11878 (tp->nvram_jedecnum == JEDEC_ST) &&
11879 (nvram_cmd & NVRAM_CMD_FIRST)) {
11881 if ((ret = tg3_nvram_exec_cmd(tp,
11882 NVRAM_CMD_WREN | NVRAM_CMD_GO |
11887 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11888 /* We always do complete word writes to eeprom. */
11889 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
11892 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11898 /* offset and length are dword aligned */
11899 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
11903 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
11904 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
11905 ~GRC_LCLCTRL_GPIO_OUTPUT1);
11909 if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
11910 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
11915 ret = tg3_nvram_lock(tp);
11919 tg3_enable_nvram_access(tp);
11920 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
11921 !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM))
11922 tw32(NVRAM_WRITE1, 0x406);
11924 grc_mode = tr32(GRC_MODE);
11925 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
11927 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
11928 !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11930 ret = tg3_nvram_write_block_buffered(tp, offset, len,
11934 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
11938 grc_mode = tr32(GRC_MODE);
11939 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
11941 tg3_disable_nvram_access(tp);
11942 tg3_nvram_unlock(tp);
11945 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
11946 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
11953 struct subsys_tbl_ent {
11954 u16 subsys_vendor, subsys_devid;
11958 static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
11959 /* Broadcom boards. */
11960 { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
11961 { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
11962 { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
11963 { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 }, /* BCM95700A9 */
11964 { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
11965 { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
11966 { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 }, /* BCM95701A7 */
11967 { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
11968 { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
11969 { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
11970 { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
11973 { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
11974 { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
11975 { PCI_VENDOR_ID_3COM, 0x1004, 0 }, /* 3C996SX */
11976 { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
11977 { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
11980 { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
11981 { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
11982 { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
11983 { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
11985 /* Compaq boards. */
11986 { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
11987 { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
11988 { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 }, /* CHANGELING */
11989 { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
11990 { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
11993 { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
11996 static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
12000 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
12001 if ((subsys_id_to_phy_id[i].subsys_vendor ==
12002 tp->pdev->subsystem_vendor) &&
12003 (subsys_id_to_phy_id[i].subsys_devid ==
12004 tp->pdev->subsystem_device))
12005 return &subsys_id_to_phy_id[i];
12010 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
12015 /* On some early chips the SRAM cannot be accessed in D3hot state,
12016 * so need make sure we're in D0.
12018 pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
12019 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
12020 pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
12023 /* Make sure register accesses (indirect or otherwise)
12024 * will function correctly.
12026 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12027 tp->misc_host_ctrl);
12029 /* The memory arbiter has to be enabled in order for SRAM accesses
12030 * to succeed. Normally on powerup the tg3 chip firmware will make
12031 * sure it is enabled, but other entities such as system netboot
12032 * code might disable it.
12034 val = tr32(MEMARB_MODE);
12035 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
12037 tp->phy_id = PHY_ID_INVALID;
12038 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12040 /* Assume an onboard device and WOL capable by default. */
12041 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
12043 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12044 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
12045 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12046 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12048 val = tr32(VCPU_CFGSHDW);
12049 if (val & VCPU_CFGSHDW_ASPM_DBNC)
12050 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
12051 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
12052 (val & VCPU_CFGSHDW_WOL_MAGPKT))
12053 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12057 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
12058 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
12059 u32 nic_cfg, led_cfg;
12060 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
12061 int eeprom_phy_serdes = 0;
12063 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
12064 tp->nic_sram_data_cfg = nic_cfg;
12066 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
12067 ver >>= NIC_SRAM_DATA_VER_SHIFT;
12068 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
12069 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
12070 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
12071 (ver > 0) && (ver < 0x100))
12072 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
12074 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
12075 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
12077 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
12078 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
12079 eeprom_phy_serdes = 1;
12081 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
12082 if (nic_phy_id != 0) {
12083 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
12084 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
12086 eeprom_phy_id = (id1 >> 16) << 10;
12087 eeprom_phy_id |= (id2 & 0xfc00) << 16;
12088 eeprom_phy_id |= (id2 & 0x03ff) << 0;
12092 tp->phy_id = eeprom_phy_id;
12093 if (eeprom_phy_serdes) {
12094 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
12095 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
12097 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
12100 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
12101 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
12102 SHASTA_EXT_LED_MODE_MASK);
12104 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
12108 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
12109 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12112 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
12113 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12116 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
12117 tp->led_ctrl = LED_CTRL_MODE_MAC;
12119 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
12120 * read on some older 5700/5701 bootcode.
12122 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
12124 GET_ASIC_REV(tp->pci_chip_rev_id) ==
12126 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12130 case SHASTA_EXT_LED_SHARED:
12131 tp->led_ctrl = LED_CTRL_MODE_SHARED;
12132 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
12133 tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
12134 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12135 LED_CTRL_MODE_PHY_2);
12138 case SHASTA_EXT_LED_MAC:
12139 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
12142 case SHASTA_EXT_LED_COMBO:
12143 tp->led_ctrl = LED_CTRL_MODE_COMBO;
12144 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
12145 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12146 LED_CTRL_MODE_PHY_2);
12151 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12152 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
12153 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
12154 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12156 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
12157 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12159 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
12160 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
12161 if ((tp->pdev->subsystem_vendor ==
12162 PCI_VENDOR_ID_ARIMA) &&
12163 (tp->pdev->subsystem_device == 0x205a ||
12164 tp->pdev->subsystem_device == 0x2063))
12165 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12167 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12168 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12171 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
12172 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
12173 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
12174 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
12177 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
12178 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
12179 tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
12181 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
12182 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
12183 tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
12185 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
12186 (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
12187 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12189 if (cfg2 & (1 << 17))
12190 tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
12192 /* serdes signal pre-emphasis in register 0x590 set by */
12193 /* bootcode if bit 18 is set */
12194 if (cfg2 & (1 << 18))
12195 tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
12197 if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
12198 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
12199 (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
12200 tp->tg3_flags3 |= TG3_FLG3_PHY_ENABLE_APD;
12202 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12205 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
12206 if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
12207 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
12210 if (cfg4 & NIC_SRAM_RGMII_STD_IBND_DISABLE)
12211 tp->tg3_flags3 |= TG3_FLG3_RGMII_STD_IBND_DISABLE;
12212 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
12213 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
12214 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
12215 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
12218 device_init_wakeup(&tp->pdev->dev, tp->tg3_flags & TG3_FLAG_WOL_CAP);
12219 device_set_wakeup_enable(&tp->pdev->dev,
12220 tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
12223 static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
12228 tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
12229 tw32(OTP_CTRL, cmd);
12231 /* Wait for up to 1 ms for command to execute. */
12232 for (i = 0; i < 100; i++) {
12233 val = tr32(OTP_STATUS);
12234 if (val & OTP_STATUS_CMD_DONE)
12239 return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
12242 /* Read the gphy configuration from the OTP region of the chip. The gphy
12243 * configuration is a 32-bit value that straddles the alignment boundary.
12244 * We do two 32-bit reads and then shift and merge the results.
12246 static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
12248 u32 bhalf_otp, thalf_otp;
12250 tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
12252 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
12255 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
12257 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12260 thalf_otp = tr32(OTP_READ_DATA);
12262 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
12264 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12267 bhalf_otp = tr32(OTP_READ_DATA);
12269 return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
12272 static int __devinit tg3_phy_probe(struct tg3 *tp)
12274 u32 hw_phy_id_1, hw_phy_id_2;
12275 u32 hw_phy_id, hw_phy_id_masked;
12278 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
12279 return tg3_phy_init(tp);
12281 /* Reading the PHY ID register can conflict with ASF
12282 * firmware access to the PHY hardware.
12285 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12286 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
12287 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
12289 /* Now read the physical PHY_ID from the chip and verify
12290 * that it is sane. If it doesn't look good, we fall back
12291 * to either the hard-coded table based PHY_ID and failing
12292 * that the value found in the eeprom area.
12294 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
12295 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
12297 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
12298 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
12299 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
12301 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
12304 if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
12305 tp->phy_id = hw_phy_id;
12306 if (hw_phy_id_masked == PHY_ID_BCM8002)
12307 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
12309 tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
12311 if (tp->phy_id != PHY_ID_INVALID) {
12312 /* Do nothing, phy ID already set up in
12313 * tg3_get_eeprom_hw_cfg().
12316 struct subsys_tbl_ent *p;
12318 /* No eeprom signature? Try the hardcoded
12319 * subsys device table.
12321 p = lookup_by_subsys(tp);
12325 tp->phy_id = p->phy_id;
12327 tp->phy_id == PHY_ID_BCM8002)
12328 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
12332 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
12333 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
12334 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
12335 u32 bmsr, adv_reg, tg3_ctrl, mask;
12337 tg3_readphy(tp, MII_BMSR, &bmsr);
12338 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
12339 (bmsr & BMSR_LSTATUS))
12340 goto skip_phy_reset;
12342 err = tg3_phy_reset(tp);
12346 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
12347 ADVERTISE_100HALF | ADVERTISE_100FULL |
12348 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
12350 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
12351 tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
12352 MII_TG3_CTRL_ADV_1000_FULL);
12353 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12354 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
12355 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
12356 MII_TG3_CTRL_ENABLE_AS_MASTER);
12359 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
12360 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
12361 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
12362 if (!tg3_copper_is_advertising_all(tp, mask)) {
12363 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12365 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
12366 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12368 tg3_writephy(tp, MII_BMCR,
12369 BMCR_ANENABLE | BMCR_ANRESTART);
12371 tg3_phy_set_wirespeed(tp);
12373 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12374 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
12375 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12379 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
12380 err = tg3_init_5401phy_dsp(tp);
12385 if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
12386 err = tg3_init_5401phy_dsp(tp);
12389 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
12390 tp->link_config.advertising =
12391 (ADVERTISED_1000baseT_Half |
12392 ADVERTISED_1000baseT_Full |
12393 ADVERTISED_Autoneg |
12395 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
12396 tp->link_config.advertising &=
12397 ~(ADVERTISED_1000baseT_Half |
12398 ADVERTISED_1000baseT_Full);
12403 static void __devinit tg3_read_partno(struct tg3 *tp)
12405 unsigned char vpd_data[256]; /* in little-endian format */
12409 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
12410 tg3_nvram_read(tp, 0x0, &magic))
12411 goto out_not_found;
12413 if (magic == TG3_EEPROM_MAGIC) {
12414 for (i = 0; i < 256; i += 4) {
12417 /* The data is in little-endian format in NVRAM.
12418 * Use the big-endian read routines to preserve
12419 * the byte order as it exists in NVRAM.
12421 if (tg3_nvram_read_be32(tp, 0x100 + i, &tmp))
12422 goto out_not_found;
12424 memcpy(&vpd_data[i], &tmp, sizeof(tmp));
12429 vpd_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_VPD);
12430 for (i = 0; i < 256; i += 4) {
12435 pci_write_config_word(tp->pdev, vpd_cap + PCI_VPD_ADDR,
12437 while (j++ < 100) {
12438 pci_read_config_word(tp->pdev, vpd_cap +
12439 PCI_VPD_ADDR, &tmp16);
12440 if (tmp16 & 0x8000)
12444 if (!(tmp16 & 0x8000))
12445 goto out_not_found;
12447 pci_read_config_dword(tp->pdev, vpd_cap + PCI_VPD_DATA,
12449 v = cpu_to_le32(tmp);
12450 memcpy(&vpd_data[i], &v, sizeof(v));
12454 /* Now parse and find the part number. */
12455 for (i = 0; i < 254; ) {
12456 unsigned char val = vpd_data[i];
12457 unsigned int block_end;
12459 if (val == 0x82 || val == 0x91) {
12462 (vpd_data[i + 2] << 8)));
12467 goto out_not_found;
12469 block_end = (i + 3 +
12471 (vpd_data[i + 2] << 8)));
12474 if (block_end > 256)
12475 goto out_not_found;
12477 while (i < (block_end - 2)) {
12478 if (vpd_data[i + 0] == 'P' &&
12479 vpd_data[i + 1] == 'N') {
12480 int partno_len = vpd_data[i + 2];
12483 if (partno_len > 24 || (partno_len + i) > 256)
12484 goto out_not_found;
12486 memcpy(tp->board_part_number,
12487 &vpd_data[i], partno_len);
12492 i += 3 + vpd_data[i + 2];
12495 /* Part number not found. */
12496 goto out_not_found;
12500 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12501 strcpy(tp->board_part_number, "BCM95906");
12502 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12503 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
12504 strcpy(tp->board_part_number, "BCM57780");
12505 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12506 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
12507 strcpy(tp->board_part_number, "BCM57760");
12508 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12509 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
12510 strcpy(tp->board_part_number, "BCM57790");
12511 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12512 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
12513 strcpy(tp->board_part_number, "BCM57788");
12515 strcpy(tp->board_part_number, "none");
12518 static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
12522 if (tg3_nvram_read(tp, offset, &val) ||
12523 (val & 0xfc000000) != 0x0c000000 ||
12524 tg3_nvram_read(tp, offset + 4, &val) ||
12531 static void __devinit tg3_read_bc_ver(struct tg3 *tp)
12533 u32 val, offset, start, ver_offset;
12535 bool newver = false;
12537 if (tg3_nvram_read(tp, 0xc, &offset) ||
12538 tg3_nvram_read(tp, 0x4, &start))
12541 offset = tg3_nvram_logical_addr(tp, offset);
12543 if (tg3_nvram_read(tp, offset, &val))
12546 if ((val & 0xfc000000) == 0x0c000000) {
12547 if (tg3_nvram_read(tp, offset + 4, &val))
12555 if (tg3_nvram_read(tp, offset + 8, &ver_offset))
12558 offset = offset + ver_offset - start;
12559 for (i = 0; i < 16; i += 4) {
12561 if (tg3_nvram_read_be32(tp, offset + i, &v))
12564 memcpy(tp->fw_ver + i, &v, sizeof(v));
12569 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
12572 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
12573 TG3_NVM_BCVER_MAJSFT;
12574 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
12575 snprintf(&tp->fw_ver[0], 32, "v%d.%02d", major, minor);
12579 static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
12581 u32 val, major, minor;
12583 /* Use native endian representation */
12584 if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
12587 major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
12588 TG3_NVM_HWSB_CFG1_MAJSFT;
12589 minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
12590 TG3_NVM_HWSB_CFG1_MINSFT;
12592 snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
12595 static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
12597 u32 offset, major, minor, build;
12599 tp->fw_ver[0] = 's';
12600 tp->fw_ver[1] = 'b';
12601 tp->fw_ver[2] = '\0';
12603 if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
12606 switch (val & TG3_EEPROM_SB_REVISION_MASK) {
12607 case TG3_EEPROM_SB_REVISION_0:
12608 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
12610 case TG3_EEPROM_SB_REVISION_2:
12611 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
12613 case TG3_EEPROM_SB_REVISION_3:
12614 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
12620 if (tg3_nvram_read(tp, offset, &val))
12623 build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
12624 TG3_EEPROM_SB_EDH_BLD_SHFT;
12625 major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
12626 TG3_EEPROM_SB_EDH_MAJ_SHFT;
12627 minor = val & TG3_EEPROM_SB_EDH_MIN_MASK;
12629 if (minor > 99 || build > 26)
12632 snprintf(&tp->fw_ver[2], 30, " v%d.%02d", major, minor);
12635 tp->fw_ver[8] = 'a' + build - 1;
12636 tp->fw_ver[9] = '\0';
12640 static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
12642 u32 val, offset, start;
12645 for (offset = TG3_NVM_DIR_START;
12646 offset < TG3_NVM_DIR_END;
12647 offset += TG3_NVM_DIRENT_SIZE) {
12648 if (tg3_nvram_read(tp, offset, &val))
12651 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
12655 if (offset == TG3_NVM_DIR_END)
12658 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
12659 start = 0x08000000;
12660 else if (tg3_nvram_read(tp, offset - 4, &start))
12663 if (tg3_nvram_read(tp, offset + 4, &offset) ||
12664 !tg3_fw_img_is_valid(tp, offset) ||
12665 tg3_nvram_read(tp, offset + 8, &val))
12668 offset += val - start;
12670 vlen = strlen(tp->fw_ver);
12672 tp->fw_ver[vlen++] = ',';
12673 tp->fw_ver[vlen++] = ' ';
12675 for (i = 0; i < 4; i++) {
12677 if (tg3_nvram_read_be32(tp, offset, &v))
12680 offset += sizeof(v);
12682 if (vlen > TG3_VER_SIZE - sizeof(v)) {
12683 memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
12687 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
12692 static void __devinit tg3_read_dash_ver(struct tg3 *tp)
12697 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) ||
12698 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
12701 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
12702 if (apedata != APE_SEG_SIG_MAGIC)
12705 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
12706 if (!(apedata & APE_FW_STATUS_READY))
12709 apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
12711 vlen = strlen(tp->fw_ver);
12713 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " DASH v%d.%d.%d.%d",
12714 (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
12715 (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
12716 (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
12717 (apedata & APE_FW_VERSION_BLDMSK));
12720 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
12724 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) {
12725 tp->fw_ver[0] = 's';
12726 tp->fw_ver[1] = 'b';
12727 tp->fw_ver[2] = '\0';
12732 if (tg3_nvram_read(tp, 0, &val))
12735 if (val == TG3_EEPROM_MAGIC)
12736 tg3_read_bc_ver(tp);
12737 else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
12738 tg3_read_sb_ver(tp, val);
12739 else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
12740 tg3_read_hwsb_ver(tp);
12744 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12745 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
12748 tg3_read_mgmtfw_ver(tp);
12750 tp->fw_ver[TG3_VER_SIZE - 1] = 0;
12753 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
12755 static int __devinit tg3_get_invariants(struct tg3 *tp)
12757 static struct pci_device_id write_reorder_chipsets[] = {
12758 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12759 PCI_DEVICE_ID_AMD_FE_GATE_700C) },
12760 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12761 PCI_DEVICE_ID_AMD_8131_BRIDGE) },
12762 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
12763 PCI_DEVICE_ID_VIA_8385_0) },
12767 u32 pci_state_reg, grc_misc_cfg;
12772 /* Force memory write invalidate off. If we leave it on,
12773 * then on 5700_BX chips we have to enable a workaround.
12774 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
12775 * to match the cacheline size. The Broadcom driver have this
12776 * workaround but turns MWI off all the times so never uses
12777 * it. This seems to suggest that the workaround is insufficient.
12779 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12780 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
12781 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12783 /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
12784 * has the register indirect write enable bit set before
12785 * we try to access any of the MMIO registers. It is also
12786 * critical that the PCI-X hw workaround situation is decided
12787 * before that as well.
12789 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12792 tp->pci_chip_rev_id = (misc_ctrl_reg >>
12793 MISC_HOST_CTRL_CHIPREV_SHIFT);
12794 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
12795 u32 prod_id_asic_rev;
12797 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
12798 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
12799 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5724)
12800 pci_read_config_dword(tp->pdev,
12801 TG3PCI_GEN2_PRODID_ASICREV,
12802 &prod_id_asic_rev);
12804 pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
12805 &prod_id_asic_rev);
12807 tp->pci_chip_rev_id = prod_id_asic_rev;
12810 /* Wrong chip ID in 5752 A0. This code can be removed later
12811 * as A0 is not in production.
12813 if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
12814 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
12816 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
12817 * we need to disable memory and use config. cycles
12818 * only to access all registers. The 5702/03 chips
12819 * can mistakenly decode the special cycles from the
12820 * ICH chipsets as memory write cycles, causing corruption
12821 * of register and memory space. Only certain ICH bridges
12822 * will drive special cycles with non-zero data during the
12823 * address phase which can fall within the 5703's address
12824 * range. This is not an ICH bug as the PCI spec allows
12825 * non-zero address during special cycles. However, only
12826 * these ICH bridges are known to drive non-zero addresses
12827 * during special cycles.
12829 * Since special cycles do not cross PCI bridges, we only
12830 * enable this workaround if the 5703 is on the secondary
12831 * bus of these ICH bridges.
12833 if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
12834 (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
12835 static struct tg3_dev_id {
12839 } ich_chipsets[] = {
12840 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
12842 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
12844 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
12846 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
12850 struct tg3_dev_id *pci_id = &ich_chipsets[0];
12851 struct pci_dev *bridge = NULL;
12853 while (pci_id->vendor != 0) {
12854 bridge = pci_get_device(pci_id->vendor, pci_id->device,
12860 if (pci_id->rev != PCI_ANY_ID) {
12861 if (bridge->revision > pci_id->rev)
12864 if (bridge->subordinate &&
12865 (bridge->subordinate->number ==
12866 tp->pdev->bus->number)) {
12868 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
12869 pci_dev_put(bridge);
12875 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
12876 static struct tg3_dev_id {
12879 } bridge_chipsets[] = {
12880 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
12881 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
12884 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
12885 struct pci_dev *bridge = NULL;
12887 while (pci_id->vendor != 0) {
12888 bridge = pci_get_device(pci_id->vendor,
12895 if (bridge->subordinate &&
12896 (bridge->subordinate->number <=
12897 tp->pdev->bus->number) &&
12898 (bridge->subordinate->subordinate >=
12899 tp->pdev->bus->number)) {
12900 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
12901 pci_dev_put(bridge);
12907 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
12908 * DMA addresses > 40-bit. This bridge may have other additional
12909 * 57xx devices behind it in some 4-port NIC designs for example.
12910 * Any tg3 device found behind the bridge will also need the 40-bit
12913 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
12914 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
12915 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
12916 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
12917 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
12920 struct pci_dev *bridge = NULL;
12923 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
12924 PCI_DEVICE_ID_SERVERWORKS_EPB,
12926 if (bridge && bridge->subordinate &&
12927 (bridge->subordinate->number <=
12928 tp->pdev->bus->number) &&
12929 (bridge->subordinate->subordinate >=
12930 tp->pdev->bus->number)) {
12931 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
12932 pci_dev_put(bridge);
12938 /* Initialize misc host control in PCI block. */
12939 tp->misc_host_ctrl |= (misc_ctrl_reg &
12940 MISC_HOST_CTRL_CHIPREV);
12941 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12942 tp->misc_host_ctrl);
12944 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
12945 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
12946 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
12947 tp->pdev_peer = tg3_find_peer(tp);
12949 /* Intentionally exclude ASIC_REV_5906 */
12950 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12951 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
12952 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12953 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
12954 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12955 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
12956 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
12957 tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
12959 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
12960 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
12961 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
12962 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
12963 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
12964 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
12966 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
12967 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
12968 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
12970 /* 5700 B0 chips do not support checksumming correctly due
12971 * to hardware bugs.
12973 if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
12974 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
12976 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
12977 tp->dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
12978 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
12979 tp->dev->features |= NETIF_F_IPV6_CSUM;
12982 /* Determine TSO capabilities */
12983 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
12984 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_3;
12985 else if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
12986 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12987 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
12988 else if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
12989 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
12990 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 &&
12991 tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
12992 tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
12993 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
12994 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
12995 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
12996 tp->tg3_flags2 |= TG3_FLG2_TSO_BUG;
12997 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
12998 tp->fw_needed = FIRMWARE_TG3TSO5;
13000 tp->fw_needed = FIRMWARE_TG3TSO;
13005 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
13006 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
13007 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
13008 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
13009 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
13010 tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
13011 tp->pdev_peer == tp->pdev))
13012 tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
13014 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13015 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13016 tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
13019 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
13020 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSIX;
13021 tp->irq_max = TG3_IRQ_MAX_VECS;
13025 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13026 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13027 tp->tg3_flags3 |= TG3_FLG3_SHORT_DMA_BUG;
13028 else if (!(tp->tg3_flags3 & TG3_FLG3_5755_PLUS)) {
13029 tp->tg3_flags3 |= TG3_FLG3_4G_DMA_BNDRY_BUG;
13030 tp->tg3_flags3 |= TG3_FLG3_40BIT_DMA_LIMIT_BUG;
13033 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
13034 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
13035 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
13036 tp->tg3_flags |= TG3_FLAG_JUMBO_CAPABLE;
13038 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13041 tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
13042 if (tp->pcie_cap != 0) {
13045 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
13047 pcie_set_readrq(tp->pdev, 4096);
13049 pci_read_config_word(tp->pdev,
13050 tp->pcie_cap + PCI_EXP_LNKCTL,
13052 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
13053 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13054 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
13055 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13056 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13057 tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
13058 tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
13059 tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
13061 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
13062 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
13063 } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
13064 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13065 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
13066 if (!tp->pcix_cap) {
13067 printk(KERN_ERR PFX "Cannot find PCI-X "
13068 "capability, aborting.\n");
13072 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
13073 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
13076 /* If we have an AMD 762 or VIA K8T800 chipset, write
13077 * reordering to the mailbox registers done by the host
13078 * controller can cause major troubles. We read back from
13079 * every mailbox register write to force the writes to be
13080 * posted to the chip in order.
13082 if (pci_dev_present(write_reorder_chipsets) &&
13083 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13084 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
13086 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
13087 &tp->pci_cacheline_sz);
13088 pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13089 &tp->pci_lat_timer);
13090 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13091 tp->pci_lat_timer < 64) {
13092 tp->pci_lat_timer = 64;
13093 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13094 tp->pci_lat_timer);
13097 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
13098 /* 5700 BX chips need to have their TX producer index
13099 * mailboxes written twice to workaround a bug.
13101 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
13103 /* If we are in PCI-X mode, enable register write workaround.
13105 * The workaround is to use indirect register accesses
13106 * for all chip writes not to mailbox registers.
13108 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
13111 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13113 /* The chip can have it's power management PCI config
13114 * space registers clobbered due to this bug.
13115 * So explicitly force the chip into D0 here.
13117 pci_read_config_dword(tp->pdev,
13118 tp->pm_cap + PCI_PM_CTRL,
13120 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
13121 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
13122 pci_write_config_dword(tp->pdev,
13123 tp->pm_cap + PCI_PM_CTRL,
13126 /* Also, force SERR#/PERR# in PCI command. */
13127 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13128 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
13129 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13133 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
13134 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
13135 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
13136 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
13138 /* Chip-specific fixup from Broadcom driver */
13139 if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
13140 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
13141 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
13142 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
13145 /* Default fast path register access methods */
13146 tp->read32 = tg3_read32;
13147 tp->write32 = tg3_write32;
13148 tp->read32_mbox = tg3_read32;
13149 tp->write32_mbox = tg3_write32;
13150 tp->write32_tx_mbox = tg3_write32;
13151 tp->write32_rx_mbox = tg3_write32;
13153 /* Various workaround register access methods */
13154 if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
13155 tp->write32 = tg3_write_indirect_reg32;
13156 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
13157 ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
13158 tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
13160 * Back to back register writes can cause problems on these
13161 * chips, the workaround is to read back all reg writes
13162 * except those to mailbox regs.
13164 * See tg3_write_indirect_reg32().
13166 tp->write32 = tg3_write_flush_reg32;
13169 if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
13170 (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
13171 tp->write32_tx_mbox = tg3_write32_tx_mbox;
13172 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
13173 tp->write32_rx_mbox = tg3_write_flush_reg32;
13176 if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
13177 tp->read32 = tg3_read_indirect_reg32;
13178 tp->write32 = tg3_write_indirect_reg32;
13179 tp->read32_mbox = tg3_read_indirect_mbox;
13180 tp->write32_mbox = tg3_write_indirect_mbox;
13181 tp->write32_tx_mbox = tg3_write_indirect_mbox;
13182 tp->write32_rx_mbox = tg3_write_indirect_mbox;
13187 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13188 pci_cmd &= ~PCI_COMMAND_MEMORY;
13189 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13191 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13192 tp->read32_mbox = tg3_read32_mbox_5906;
13193 tp->write32_mbox = tg3_write32_mbox_5906;
13194 tp->write32_tx_mbox = tg3_write32_mbox_5906;
13195 tp->write32_rx_mbox = tg3_write32_mbox_5906;
13198 if (tp->write32 == tg3_write_indirect_reg32 ||
13199 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13200 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13201 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
13202 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
13204 /* Get eeprom hw config before calling tg3_set_power_state().
13205 * In particular, the TG3_FLG2_IS_NIC flag must be
13206 * determined before calling tg3_set_power_state() so that
13207 * we know whether or not to switch out of Vaux power.
13208 * When the flag is set, it means that GPIO1 is used for eeprom
13209 * write protect and also implies that it is a LOM where GPIOs
13210 * are not used to switch power.
13212 tg3_get_eeprom_hw_cfg(tp);
13214 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
13215 /* Allow reads and writes to the
13216 * APE register and memory space.
13218 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
13219 PCISTATE_ALLOW_APE_SHMEM_WR;
13220 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
13224 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13225 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13226 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13227 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13228 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
13229 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
13231 /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
13232 * GPIO1 driven high will bring 5700's external PHY out of reset.
13233 * It is also used as eeprom write protect on LOMs.
13235 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
13236 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13237 (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
13238 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
13239 GRC_LCLCTRL_GPIO_OUTPUT1);
13240 /* Unused GPIO3 must be driven as output on 5752 because there
13241 * are no pull-up resistors on unused GPIO pins.
13243 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
13244 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
13246 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13247 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
13248 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13250 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
13251 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
13252 /* Turn off the debug UART. */
13253 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13254 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
13255 /* Keep VMain power. */
13256 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
13257 GRC_LCLCTRL_GPIO_OUTPUT0;
13260 /* Force the chip into D0. */
13261 err = tg3_set_power_state(tp, PCI_D0);
13263 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
13264 pci_name(tp->pdev));
13268 /* Derive initial jumbo mode from MTU assigned in
13269 * ether_setup() via the alloc_etherdev() call
13271 if (tp->dev->mtu > ETH_DATA_LEN &&
13272 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
13273 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
13275 /* Determine WakeOnLan speed to use. */
13276 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13277 tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
13278 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
13279 tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
13280 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
13282 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
13285 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13286 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
13288 /* A few boards don't want Ethernet@WireSpeed phy feature */
13289 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13290 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
13291 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
13292 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
13293 (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) ||
13294 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
13295 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
13297 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
13298 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
13299 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
13300 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
13301 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
13303 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
13304 !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
13305 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
13306 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 &&
13307 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) {
13308 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13309 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
13310 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13311 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
13312 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
13313 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
13314 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
13315 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
13316 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
13318 tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
13321 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13322 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
13323 tp->phy_otp = tg3_read_otp_phycfg(tp);
13324 if (tp->phy_otp == 0)
13325 tp->phy_otp = TG3_OTP_DEFAULT;
13328 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
13329 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
13331 tp->mi_mode = MAC_MI_MODE_BASE;
13333 tp->coalesce_mode = 0;
13334 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
13335 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
13336 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
13338 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13339 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
13340 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
13342 err = tg3_mdio_init(tp);
13346 /* Initialize data/descriptor byte/word swapping. */
13347 val = tr32(GRC_MODE);
13348 val &= GRC_MODE_HOST_STACKUP;
13349 tw32(GRC_MODE, val | tp->grc_mode);
13351 tg3_switch_clocks(tp);
13353 /* Clear this out for sanity. */
13354 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
13356 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13358 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
13359 (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
13360 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
13362 if (chiprevid == CHIPREV_ID_5701_A0 ||
13363 chiprevid == CHIPREV_ID_5701_B0 ||
13364 chiprevid == CHIPREV_ID_5701_B2 ||
13365 chiprevid == CHIPREV_ID_5701_B5) {
13366 void __iomem *sram_base;
13368 /* Write some dummy words into the SRAM status block
13369 * area, see if it reads back correctly. If the return
13370 * value is bad, force enable the PCIX workaround.
13372 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
13374 writel(0x00000000, sram_base);
13375 writel(0x00000000, sram_base + 4);
13376 writel(0xffffffff, sram_base + 4);
13377 if (readl(sram_base) != 0x00000000)
13378 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13383 tg3_nvram_init(tp);
13385 grc_misc_cfg = tr32(GRC_MISC_CFG);
13386 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
13388 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13389 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
13390 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
13391 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
13393 if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
13394 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
13395 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
13396 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
13397 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
13398 HOSTCC_MODE_CLRTICK_TXBD);
13400 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
13401 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13402 tp->misc_host_ctrl);
13405 /* Preserve the APE MAC_MODE bits */
13406 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
13407 tp->mac_mode = tr32(MAC_MODE) |
13408 MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
13410 tp->mac_mode = TG3_DEF_MAC_MODE;
13412 /* these are limited to 10/100 only */
13413 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13414 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
13415 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13416 tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13417 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
13418 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
13419 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
13420 (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13421 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
13422 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
13423 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
13424 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
13425 (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
13426 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
13428 err = tg3_phy_probe(tp);
13430 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
13431 pci_name(tp->pdev), err);
13432 /* ... but do not return immediately ... */
13436 tg3_read_partno(tp);
13437 tg3_read_fw_ver(tp);
13439 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
13440 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
13442 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13443 tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
13445 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
13448 /* 5700 {AX,BX} chips have a broken status block link
13449 * change bit implementation, so we must use the
13450 * status register in those cases.
13452 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13453 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
13455 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
13457 /* The led_ctrl is set during tg3_phy_probe, here we might
13458 * have to force the link status polling mechanism based
13459 * upon subsystem IDs.
13461 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
13462 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13463 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
13464 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
13465 TG3_FLAG_USE_LINKCHG_REG);
13468 /* For all SERDES we poll the MAC status register. */
13469 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
13470 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
13472 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
13474 tp->rx_offset = NET_IP_ALIGN;
13475 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13476 (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
13479 tp->rx_std_max_post = TG3_RX_RING_SIZE;
13481 /* Increment the rx prod index on the rx std ring by at most
13482 * 8 for these chips to workaround hw errata.
13484 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13485 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13486 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
13487 tp->rx_std_max_post = 8;
13489 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
13490 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
13491 PCIE_PWR_MGMT_L1_THRESH_MSK;
13496 #ifdef CONFIG_SPARC
13497 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
13499 struct net_device *dev = tp->dev;
13500 struct pci_dev *pdev = tp->pdev;
13501 struct device_node *dp = pci_device_to_OF_node(pdev);
13502 const unsigned char *addr;
13505 addr = of_get_property(dp, "local-mac-address", &len);
13506 if (addr && len == 6) {
13507 memcpy(dev->dev_addr, addr, 6);
13508 memcpy(dev->perm_addr, dev->dev_addr, 6);
13514 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
13516 struct net_device *dev = tp->dev;
13518 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
13519 memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
13524 static int __devinit tg3_get_device_address(struct tg3 *tp)
13526 struct net_device *dev = tp->dev;
13527 u32 hi, lo, mac_offset;
13530 #ifdef CONFIG_SPARC
13531 if (!tg3_get_macaddr_sparc(tp))
13536 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
13537 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13538 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
13540 if (tg3_nvram_lock(tp))
13541 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
13543 tg3_nvram_unlock(tp);
13544 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
13545 if (tr32(TG3_CPMU_STATUS) & TG3_CPMU_STATUS_PCIE_FUNC)
13547 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13550 /* First try to get it from MAC address mailbox. */
13551 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
13552 if ((hi >> 16) == 0x484b) {
13553 dev->dev_addr[0] = (hi >> 8) & 0xff;
13554 dev->dev_addr[1] = (hi >> 0) & 0xff;
13556 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
13557 dev->dev_addr[2] = (lo >> 24) & 0xff;
13558 dev->dev_addr[3] = (lo >> 16) & 0xff;
13559 dev->dev_addr[4] = (lo >> 8) & 0xff;
13560 dev->dev_addr[5] = (lo >> 0) & 0xff;
13562 /* Some old bootcode may report a 0 MAC address in SRAM */
13563 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
13566 /* Next, try NVRAM. */
13567 if (!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) &&
13568 !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
13569 !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
13570 memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
13571 memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
13573 /* Finally just fetch it out of the MAC control regs. */
13575 hi = tr32(MAC_ADDR_0_HIGH);
13576 lo = tr32(MAC_ADDR_0_LOW);
13578 dev->dev_addr[5] = lo & 0xff;
13579 dev->dev_addr[4] = (lo >> 8) & 0xff;
13580 dev->dev_addr[3] = (lo >> 16) & 0xff;
13581 dev->dev_addr[2] = (lo >> 24) & 0xff;
13582 dev->dev_addr[1] = hi & 0xff;
13583 dev->dev_addr[0] = (hi >> 8) & 0xff;
13587 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
13588 #ifdef CONFIG_SPARC
13589 if (!tg3_get_default_macaddr_sparc(tp))
13594 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
13598 #define BOUNDARY_SINGLE_CACHELINE 1
13599 #define BOUNDARY_MULTI_CACHELINE 2
13601 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
13603 int cacheline_size;
13607 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
13609 cacheline_size = 1024;
13611 cacheline_size = (int) byte * 4;
13613 /* On 5703 and later chips, the boundary bits have no
13616 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13617 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13618 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13621 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
13622 goal = BOUNDARY_MULTI_CACHELINE;
13624 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
13625 goal = BOUNDARY_SINGLE_CACHELINE;
13631 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
13632 val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
13639 /* PCI controllers on most RISC systems tend to disconnect
13640 * when a device tries to burst across a cache-line boundary.
13641 * Therefore, letting tg3 do so just wastes PCI bandwidth.
13643 * Unfortunately, for PCI-E there are only limited
13644 * write-side controls for this, and thus for reads
13645 * we will still get the disconnects. We'll also waste
13646 * these PCI cycles for both read and write for chips
13647 * other than 5700 and 5701 which do not implement the
13650 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13651 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
13652 switch (cacheline_size) {
13657 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13658 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
13659 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
13661 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13662 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13667 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
13668 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
13672 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13673 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13676 } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13677 switch (cacheline_size) {
13681 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13682 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13683 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
13689 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13690 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
13694 switch (cacheline_size) {
13696 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13697 val |= (DMA_RWCTRL_READ_BNDRY_16 |
13698 DMA_RWCTRL_WRITE_BNDRY_16);
13703 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13704 val |= (DMA_RWCTRL_READ_BNDRY_32 |
13705 DMA_RWCTRL_WRITE_BNDRY_32);
13710 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13711 val |= (DMA_RWCTRL_READ_BNDRY_64 |
13712 DMA_RWCTRL_WRITE_BNDRY_64);
13717 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13718 val |= (DMA_RWCTRL_READ_BNDRY_128 |
13719 DMA_RWCTRL_WRITE_BNDRY_128);
13724 val |= (DMA_RWCTRL_READ_BNDRY_256 |
13725 DMA_RWCTRL_WRITE_BNDRY_256);
13728 val |= (DMA_RWCTRL_READ_BNDRY_512 |
13729 DMA_RWCTRL_WRITE_BNDRY_512);
13733 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
13734 DMA_RWCTRL_WRITE_BNDRY_1024);
13743 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
13745 struct tg3_internal_buffer_desc test_desc;
13746 u32 sram_dma_descs;
13749 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
13751 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
13752 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
13753 tw32(RDMAC_STATUS, 0);
13754 tw32(WDMAC_STATUS, 0);
13756 tw32(BUFMGR_MODE, 0);
13757 tw32(FTQ_RESET, 0);
13759 test_desc.addr_hi = ((u64) buf_dma) >> 32;
13760 test_desc.addr_lo = buf_dma & 0xffffffff;
13761 test_desc.nic_mbuf = 0x00002100;
13762 test_desc.len = size;
13765 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
13766 * the *second* time the tg3 driver was getting loaded after an
13769 * Broadcom tells me:
13770 * ...the DMA engine is connected to the GRC block and a DMA
13771 * reset may affect the GRC block in some unpredictable way...
13772 * The behavior of resets to individual blocks has not been tested.
13774 * Broadcom noted the GRC reset will also reset all sub-components.
13777 test_desc.cqid_sqid = (13 << 8) | 2;
13779 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
13782 test_desc.cqid_sqid = (16 << 8) | 7;
13784 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
13787 test_desc.flags = 0x00000005;
13789 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
13792 val = *(((u32 *)&test_desc) + i);
13793 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
13794 sram_dma_descs + (i * sizeof(u32)));
13795 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
13797 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
13800 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
13802 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
13806 for (i = 0; i < 40; i++) {
13810 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
13812 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
13813 if ((val & 0xffff) == sram_dma_descs) {
13824 #define TEST_BUFFER_SIZE 0x2000
13826 static int __devinit tg3_test_dma(struct tg3 *tp)
13828 dma_addr_t buf_dma;
13829 u32 *buf, saved_dma_rwctrl;
13832 buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
13838 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
13839 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
13841 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
13843 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
13846 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13847 /* DMA read watermark not used on PCIE */
13848 tp->dma_rwctrl |= 0x00180000;
13849 } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
13850 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
13851 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
13852 tp->dma_rwctrl |= 0x003f0000;
13854 tp->dma_rwctrl |= 0x003f000f;
13856 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13857 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
13858 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
13859 u32 read_water = 0x7;
13861 /* If the 5704 is behind the EPB bridge, we can
13862 * do the less restrictive ONE_DMA workaround for
13863 * better performance.
13865 if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
13866 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13867 tp->dma_rwctrl |= 0x8000;
13868 else if (ccval == 0x6 || ccval == 0x7)
13869 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
13871 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
13873 /* Set bit 23 to enable PCIX hw bug fix */
13875 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
13876 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
13878 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
13879 /* 5780 always in PCIX mode */
13880 tp->dma_rwctrl |= 0x00144000;
13881 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
13882 /* 5714 always in PCIX mode */
13883 tp->dma_rwctrl |= 0x00148000;
13885 tp->dma_rwctrl |= 0x001b000f;
13889 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13890 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13891 tp->dma_rwctrl &= 0xfffffff0;
13893 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13894 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
13895 /* Remove this if it causes problems for some boards. */
13896 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
13898 /* On 5700/5701 chips, we need to set this bit.
13899 * Otherwise the chip will issue cacheline transactions
13900 * to streamable DMA memory with not all the byte
13901 * enables turned on. This is an error on several
13902 * RISC PCI controllers, in particular sparc64.
13904 * On 5703/5704 chips, this bit has been reassigned
13905 * a different meaning. In particular, it is used
13906 * on those chips to enable a PCI-X workaround.
13908 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
13911 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13914 /* Unneeded, already done by tg3_get_invariants. */
13915 tg3_switch_clocks(tp);
13918 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13919 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
13922 /* It is best to perform DMA test with maximum write burst size
13923 * to expose the 5700/5701 write DMA bug.
13925 saved_dma_rwctrl = tp->dma_rwctrl;
13926 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
13927 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13932 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
13935 /* Send the buffer to the chip. */
13936 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
13938 printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
13943 /* validate data reached card RAM correctly. */
13944 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
13946 tg3_read_mem(tp, 0x2100 + (i*4), &val);
13947 if (le32_to_cpu(val) != p[i]) {
13948 printk(KERN_ERR " tg3_test_dma() Card buffer corrupted on write! (%d != %d)\n", val, i);
13949 /* ret = -ENODEV here? */
13954 /* Now read it back. */
13955 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
13957 printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
13963 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
13967 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
13968 DMA_RWCTRL_WRITE_BNDRY_16) {
13969 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
13970 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
13971 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13974 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
13980 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
13986 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
13987 DMA_RWCTRL_WRITE_BNDRY_16) {
13988 static struct pci_device_id dma_wait_state_chipsets[] = {
13989 { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
13990 PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
13994 /* DMA test passed without adjusting DMA boundary,
13995 * now look for chipsets that are known to expose the
13996 * DMA bug without failing the test.
13998 if (pci_dev_present(dma_wait_state_chipsets)) {
13999 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14000 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14003 /* Safe to use the calculated DMA boundary. */
14004 tp->dma_rwctrl = saved_dma_rwctrl;
14006 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14010 pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
14015 static void __devinit tg3_init_link_config(struct tg3 *tp)
14017 tp->link_config.advertising =
14018 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
14019 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
14020 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
14021 ADVERTISED_Autoneg | ADVERTISED_MII);
14022 tp->link_config.speed = SPEED_INVALID;
14023 tp->link_config.duplex = DUPLEX_INVALID;
14024 tp->link_config.autoneg = AUTONEG_ENABLE;
14025 tp->link_config.active_speed = SPEED_INVALID;
14026 tp->link_config.active_duplex = DUPLEX_INVALID;
14027 tp->link_config.phy_is_low_power = 0;
14028 tp->link_config.orig_speed = SPEED_INVALID;
14029 tp->link_config.orig_duplex = DUPLEX_INVALID;
14030 tp->link_config.orig_autoneg = AUTONEG_INVALID;
14033 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
14035 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS &&
14036 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) {
14037 tp->bufmgr_config.mbuf_read_dma_low_water =
14038 DEFAULT_MB_RDMA_LOW_WATER_5705;
14039 tp->bufmgr_config.mbuf_mac_rx_low_water =
14040 DEFAULT_MB_MACRX_LOW_WATER_5705;
14041 tp->bufmgr_config.mbuf_high_water =
14042 DEFAULT_MB_HIGH_WATER_5705;
14043 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
14044 tp->bufmgr_config.mbuf_mac_rx_low_water =
14045 DEFAULT_MB_MACRX_LOW_WATER_5906;
14046 tp->bufmgr_config.mbuf_high_water =
14047 DEFAULT_MB_HIGH_WATER_5906;
14050 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14051 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
14052 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14053 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
14054 tp->bufmgr_config.mbuf_high_water_jumbo =
14055 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
14057 tp->bufmgr_config.mbuf_read_dma_low_water =
14058 DEFAULT_MB_RDMA_LOW_WATER;
14059 tp->bufmgr_config.mbuf_mac_rx_low_water =
14060 DEFAULT_MB_MACRX_LOW_WATER;
14061 tp->bufmgr_config.mbuf_high_water =
14062 DEFAULT_MB_HIGH_WATER;
14064 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14065 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
14066 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14067 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
14068 tp->bufmgr_config.mbuf_high_water_jumbo =
14069 DEFAULT_MB_HIGH_WATER_JUMBO;
14072 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
14073 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
14076 static char * __devinit tg3_phy_string(struct tg3 *tp)
14078 switch (tp->phy_id & PHY_ID_MASK) {
14079 case PHY_ID_BCM5400: return "5400";
14080 case PHY_ID_BCM5401: return "5401";
14081 case PHY_ID_BCM5411: return "5411";
14082 case PHY_ID_BCM5701: return "5701";
14083 case PHY_ID_BCM5703: return "5703";
14084 case PHY_ID_BCM5704: return "5704";
14085 case PHY_ID_BCM5705: return "5705";
14086 case PHY_ID_BCM5750: return "5750";
14087 case PHY_ID_BCM5752: return "5752";
14088 case PHY_ID_BCM5714: return "5714";
14089 case PHY_ID_BCM5780: return "5780";
14090 case PHY_ID_BCM5755: return "5755";
14091 case PHY_ID_BCM5787: return "5787";
14092 case PHY_ID_BCM5784: return "5784";
14093 case PHY_ID_BCM5756: return "5722/5756";
14094 case PHY_ID_BCM5906: return "5906";
14095 case PHY_ID_BCM5761: return "5761";
14096 case PHY_ID_BCM5717: return "5717";
14097 case PHY_ID_BCM8002: return "8002/serdes";
14098 case 0: return "serdes";
14099 default: return "unknown";
14103 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
14105 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
14106 strcpy(str, "PCI Express");
14108 } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
14109 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
14111 strcpy(str, "PCIX:");
14113 if ((clock_ctrl == 7) ||
14114 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
14115 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
14116 strcat(str, "133MHz");
14117 else if (clock_ctrl == 0)
14118 strcat(str, "33MHz");
14119 else if (clock_ctrl == 2)
14120 strcat(str, "50MHz");
14121 else if (clock_ctrl == 4)
14122 strcat(str, "66MHz");
14123 else if (clock_ctrl == 6)
14124 strcat(str, "100MHz");
14126 strcpy(str, "PCI:");
14127 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
14128 strcat(str, "66MHz");
14130 strcat(str, "33MHz");
14132 if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
14133 strcat(str, ":32-bit");
14135 strcat(str, ":64-bit");
14139 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
14141 struct pci_dev *peer;
14142 unsigned int func, devnr = tp->pdev->devfn & ~7;
14144 for (func = 0; func < 8; func++) {
14145 peer = pci_get_slot(tp->pdev->bus, devnr | func);
14146 if (peer && peer != tp->pdev)
14150 /* 5704 can be configured in single-port mode, set peer to
14151 * tp->pdev in that case.
14159 * We don't need to keep the refcount elevated; there's no way
14160 * to remove one half of this device without removing the other
14167 static void __devinit tg3_init_coal(struct tg3 *tp)
14169 struct ethtool_coalesce *ec = &tp->coal;
14171 memset(ec, 0, sizeof(*ec));
14172 ec->cmd = ETHTOOL_GCOALESCE;
14173 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
14174 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
14175 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
14176 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
14177 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
14178 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
14179 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
14180 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
14181 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
14183 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
14184 HOSTCC_MODE_CLRTICK_TXBD)) {
14185 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
14186 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
14187 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
14188 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
14191 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
14192 ec->rx_coalesce_usecs_irq = 0;
14193 ec->tx_coalesce_usecs_irq = 0;
14194 ec->stats_block_coalesce_usecs = 0;
14198 static const struct net_device_ops tg3_netdev_ops = {
14199 .ndo_open = tg3_open,
14200 .ndo_stop = tg3_close,
14201 .ndo_start_xmit = tg3_start_xmit,
14202 .ndo_get_stats = tg3_get_stats,
14203 .ndo_validate_addr = eth_validate_addr,
14204 .ndo_set_multicast_list = tg3_set_rx_mode,
14205 .ndo_set_mac_address = tg3_set_mac_addr,
14206 .ndo_do_ioctl = tg3_ioctl,
14207 .ndo_tx_timeout = tg3_tx_timeout,
14208 .ndo_change_mtu = tg3_change_mtu,
14209 #if TG3_VLAN_TAG_USED
14210 .ndo_vlan_rx_register = tg3_vlan_rx_register,
14212 #ifdef CONFIG_NET_POLL_CONTROLLER
14213 .ndo_poll_controller = tg3_poll_controller,
14217 static const struct net_device_ops tg3_netdev_ops_dma_bug = {
14218 .ndo_open = tg3_open,
14219 .ndo_stop = tg3_close,
14220 .ndo_start_xmit = tg3_start_xmit_dma_bug,
14221 .ndo_get_stats = tg3_get_stats,
14222 .ndo_validate_addr = eth_validate_addr,
14223 .ndo_set_multicast_list = tg3_set_rx_mode,
14224 .ndo_set_mac_address = tg3_set_mac_addr,
14225 .ndo_do_ioctl = tg3_ioctl,
14226 .ndo_tx_timeout = tg3_tx_timeout,
14227 .ndo_change_mtu = tg3_change_mtu,
14228 #if TG3_VLAN_TAG_USED
14229 .ndo_vlan_rx_register = tg3_vlan_rx_register,
14231 #ifdef CONFIG_NET_POLL_CONTROLLER
14232 .ndo_poll_controller = tg3_poll_controller,
14236 static int __devinit tg3_init_one(struct pci_dev *pdev,
14237 const struct pci_device_id *ent)
14239 static int tg3_version_printed = 0;
14240 struct net_device *dev;
14242 int i, err, pm_cap;
14243 u32 sndmbx, rcvmbx, intmbx;
14245 u64 dma_mask, persist_dma_mask;
14247 if (tg3_version_printed++ == 0)
14248 printk(KERN_INFO "%s", version);
14250 err = pci_enable_device(pdev);
14252 printk(KERN_ERR PFX "Cannot enable PCI device, "
14257 err = pci_request_regions(pdev, DRV_MODULE_NAME);
14259 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
14261 goto err_out_disable_pdev;
14264 pci_set_master(pdev);
14266 /* Find power-management capability. */
14267 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
14269 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
14272 goto err_out_free_res;
14275 dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
14277 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
14279 goto err_out_free_res;
14282 SET_NETDEV_DEV(dev, &pdev->dev);
14284 #if TG3_VLAN_TAG_USED
14285 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
14288 tp = netdev_priv(dev);
14291 tp->pm_cap = pm_cap;
14292 tp->rx_mode = TG3_DEF_RX_MODE;
14293 tp->tx_mode = TG3_DEF_TX_MODE;
14296 tp->msg_enable = tg3_debug;
14298 tp->msg_enable = TG3_DEF_MSG_ENABLE;
14300 /* The word/byte swap controls here control register access byte
14301 * swapping. DMA data byte swapping is controlled in the GRC_MODE
14304 tp->misc_host_ctrl =
14305 MISC_HOST_CTRL_MASK_PCI_INT |
14306 MISC_HOST_CTRL_WORD_SWAP |
14307 MISC_HOST_CTRL_INDIR_ACCESS |
14308 MISC_HOST_CTRL_PCISTATE_RW;
14310 /* The NONFRM (non-frame) byte/word swap controls take effect
14311 * on descriptor entries, anything which isn't packet data.
14313 * The StrongARM chips on the board (one for tx, one for rx)
14314 * are running in big-endian mode.
14316 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
14317 GRC_MODE_WSWAP_NONFRM_DATA);
14318 #ifdef __BIG_ENDIAN
14319 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
14321 spin_lock_init(&tp->lock);
14322 spin_lock_init(&tp->indirect_lock);
14323 INIT_WORK(&tp->reset_task, tg3_reset_task);
14325 tp->regs = pci_ioremap_bar(pdev, BAR_0);
14327 printk(KERN_ERR PFX "Cannot map device registers, "
14330 goto err_out_free_dev;
14333 tg3_init_link_config(tp);
14335 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
14336 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
14338 dev->ethtool_ops = &tg3_ethtool_ops;
14339 dev->watchdog_timeo = TG3_TX_TIMEOUT;
14340 dev->irq = pdev->irq;
14342 err = tg3_get_invariants(tp);
14344 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
14346 goto err_out_iounmap;
14349 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
14350 tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
14351 dev->netdev_ops = &tg3_netdev_ops;
14353 dev->netdev_ops = &tg3_netdev_ops_dma_bug;
14356 /* The EPB bridge inside 5714, 5715, and 5780 and any
14357 * device behind the EPB cannot support DMA addresses > 40-bit.
14358 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
14359 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
14360 * do DMA address check in tg3_start_xmit().
14362 if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
14363 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
14364 else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
14365 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
14366 #ifdef CONFIG_HIGHMEM
14367 dma_mask = DMA_BIT_MASK(64);
14370 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
14372 /* Configure DMA attributes. */
14373 if (dma_mask > DMA_BIT_MASK(32)) {
14374 err = pci_set_dma_mask(pdev, dma_mask);
14376 dev->features |= NETIF_F_HIGHDMA;
14377 err = pci_set_consistent_dma_mask(pdev,
14380 printk(KERN_ERR PFX "Unable to obtain 64 bit "
14381 "DMA for consistent allocations\n");
14382 goto err_out_iounmap;
14386 if (err || dma_mask == DMA_BIT_MASK(32)) {
14387 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
14389 printk(KERN_ERR PFX "No usable DMA configuration, "
14391 goto err_out_iounmap;
14395 tg3_init_bufmgr_config(tp);
14397 /* Selectively allow TSO based on operating conditions */
14398 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
14399 (tp->fw_needed && !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)))
14400 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
14402 tp->tg3_flags2 &= ~(TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG);
14403 tp->fw_needed = NULL;
14406 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
14407 tp->fw_needed = FIRMWARE_TG3;
14409 /* TSO is on by default on chips that support hardware TSO.
14410 * Firmware TSO on older chips gives lower performance, so it
14411 * is off by default, but can be enabled using ethtool.
14413 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) &&
14414 (dev->features & NETIF_F_IP_CSUM))
14415 dev->features |= NETIF_F_TSO;
14417 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
14418 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3)) {
14419 if (dev->features & NETIF_F_IPV6_CSUM)
14420 dev->features |= NETIF_F_TSO6;
14421 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
14422 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
14423 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
14424 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
14425 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
14426 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
14427 dev->features |= NETIF_F_TSO_ECN;
14430 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
14431 !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
14432 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
14433 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
14434 tp->rx_pending = 63;
14437 err = tg3_get_device_address(tp);
14439 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
14444 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
14445 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
14446 if (!tp->aperegs) {
14447 printk(KERN_ERR PFX "Cannot map APE registers, "
14453 tg3_ape_lock_init(tp);
14455 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
14456 tg3_read_dash_ver(tp);
14460 * Reset chip in case UNDI or EFI driver did not shutdown
14461 * DMA self test will enable WDMAC and we'll see (spurious)
14462 * pending DMA on the PCI bus at that point.
14464 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
14465 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
14466 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
14467 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14470 err = tg3_test_dma(tp);
14472 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
14473 goto err_out_apeunmap;
14476 /* flow control autonegotiation is default behavior */
14477 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
14478 tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
14480 intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
14481 rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
14482 sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
14483 for (i = 0; i < TG3_IRQ_MAX_VECS; i++) {
14484 struct tg3_napi *tnapi = &tp->napi[i];
14487 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
14489 tnapi->int_mbox = intmbx;
14495 tnapi->consmbox = rcvmbx;
14496 tnapi->prodmbox = sndmbx;
14499 tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
14500 netif_napi_add(dev, &tnapi->napi, tg3_poll_msix, 64);
14502 tnapi->coal_now = HOSTCC_MODE_NOW;
14503 netif_napi_add(dev, &tnapi->napi, tg3_poll, 64);
14506 if (!(tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX))
14510 * If we support MSIX, we'll be using RSS. If we're using
14511 * RSS, the first vector only handles link interrupts and the
14512 * remaining vectors handle rx and tx interrupts. Reuse the
14513 * mailbox values for the next iteration. The values we setup
14514 * above are still useful for the single vectored mode.
14529 pci_set_drvdata(pdev, dev);
14531 err = register_netdev(dev);
14533 printk(KERN_ERR PFX "Cannot register net device, "
14535 goto err_out_apeunmap;
14538 printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
14540 tp->board_part_number,
14541 tp->pci_chip_rev_id,
14542 tg3_bus_string(tp, str),
14545 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
14546 struct phy_device *phydev;
14547 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
14549 "%s: attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
14550 tp->dev->name, phydev->drv->name,
14551 dev_name(&phydev->dev));
14554 "%s: attached PHY is %s (%s Ethernet) (WireSpeed[%d])\n",
14555 tp->dev->name, tg3_phy_string(tp),
14556 ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
14557 ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
14558 "10/100/1000Base-T")),
14559 (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0);
14561 printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
14563 (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
14564 (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
14565 (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
14566 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
14567 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
14568 printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
14569 dev->name, tp->dma_rwctrl,
14570 (pdev->dma_mask == DMA_BIT_MASK(32)) ? 32 :
14571 (((u64) pdev->dma_mask == DMA_BIT_MASK(40)) ? 40 : 64));
14577 iounmap(tp->aperegs);
14578 tp->aperegs = NULL;
14583 release_firmware(tp->fw);
14595 pci_release_regions(pdev);
14597 err_out_disable_pdev:
14598 pci_disable_device(pdev);
14599 pci_set_drvdata(pdev, NULL);
14603 static void __devexit tg3_remove_one(struct pci_dev *pdev)
14605 struct net_device *dev = pci_get_drvdata(pdev);
14608 struct tg3 *tp = netdev_priv(dev);
14611 release_firmware(tp->fw);
14613 flush_scheduled_work();
14615 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
14620 unregister_netdev(dev);
14622 iounmap(tp->aperegs);
14623 tp->aperegs = NULL;
14630 pci_release_regions(pdev);
14631 pci_disable_device(pdev);
14632 pci_set_drvdata(pdev, NULL);
14636 static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
14638 struct net_device *dev = pci_get_drvdata(pdev);
14639 struct tg3 *tp = netdev_priv(dev);
14640 pci_power_t target_state;
14643 /* PCI register 4 needs to be saved whether netif_running() or not.
14644 * MSI address and data need to be saved if using MSI and
14647 pci_save_state(pdev);
14649 if (!netif_running(dev))
14652 flush_scheduled_work();
14654 tg3_netif_stop(tp);
14656 del_timer_sync(&tp->timer);
14658 tg3_full_lock(tp, 1);
14659 tg3_disable_ints(tp);
14660 tg3_full_unlock(tp);
14662 netif_device_detach(dev);
14664 tg3_full_lock(tp, 0);
14665 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14666 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
14667 tg3_full_unlock(tp);
14669 target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot;
14671 err = tg3_set_power_state(tp, target_state);
14675 tg3_full_lock(tp, 0);
14677 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
14678 err2 = tg3_restart_hw(tp, 1);
14682 tp->timer.expires = jiffies + tp->timer_offset;
14683 add_timer(&tp->timer);
14685 netif_device_attach(dev);
14686 tg3_netif_start(tp);
14689 tg3_full_unlock(tp);
14698 static int tg3_resume(struct pci_dev *pdev)
14700 struct net_device *dev = pci_get_drvdata(pdev);
14701 struct tg3 *tp = netdev_priv(dev);
14704 pci_restore_state(tp->pdev);
14706 if (!netif_running(dev))
14709 err = tg3_set_power_state(tp, PCI_D0);
14713 netif_device_attach(dev);
14715 tg3_full_lock(tp, 0);
14717 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
14718 err = tg3_restart_hw(tp, 1);
14722 tp->timer.expires = jiffies + tp->timer_offset;
14723 add_timer(&tp->timer);
14725 tg3_netif_start(tp);
14728 tg3_full_unlock(tp);
14736 static struct pci_driver tg3_driver = {
14737 .name = DRV_MODULE_NAME,
14738 .id_table = tg3_pci_tbl,
14739 .probe = tg3_init_one,
14740 .remove = __devexit_p(tg3_remove_one),
14741 .suspend = tg3_suspend,
14742 .resume = tg3_resume
14745 static int __init tg3_init(void)
14747 return pci_register_driver(&tg3_driver);
14750 static void __exit tg3_cleanup(void)
14752 pci_unregister_driver(&tg3_driver);
14755 module_init(tg3_init);
14756 module_exit(tg3_cleanup);