2 * tg3.c: Broadcom Tigon3 ethernet driver.
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
7 * Copyright (C) 2005-2010 Broadcom Corporation.
10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/kernel.h>
22 #include <linux/types.h>
23 #include <linux/compiler.h>
24 #include <linux/slab.h>
25 #include <linux/delay.h>
27 #include <linux/init.h>
28 #include <linux/ioport.h>
29 #include <linux/pci.h>
30 #include <linux/netdevice.h>
31 #include <linux/etherdevice.h>
32 #include <linux/skbuff.h>
33 #include <linux/ethtool.h>
34 #include <linux/mii.h>
35 #include <linux/phy.h>
36 #include <linux/brcmphy.h>
37 #include <linux/if_vlan.h>
39 #include <linux/tcp.h>
40 #include <linux/workqueue.h>
41 #include <linux/prefetch.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/firmware.h>
45 #include <net/checksum.h>
48 #include <asm/system.h>
50 #include <asm/byteorder.h>
51 #include <asm/uaccess.h>
54 #include <asm/idprom.h>
61 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
62 #define TG3_VLAN_TAG_USED 1
64 #define TG3_VLAN_TAG_USED 0
69 #define DRV_MODULE_NAME "tg3"
70 #define PFX DRV_MODULE_NAME ": "
71 #define DRV_MODULE_VERSION "3.107"
72 #define DRV_MODULE_RELDATE "February 12, 2010"
74 #define TG3_DEF_MAC_MODE 0
75 #define TG3_DEF_RX_MODE 0
76 #define TG3_DEF_TX_MODE 0
77 #define TG3_DEF_MSG_ENABLE \
87 /* length of time before we decide the hardware is borked,
88 * and dev->tx_timeout() should be called to fix the problem
90 #define TG3_TX_TIMEOUT (5 * HZ)
92 /* hardware minimum and maximum for a single frame's data payload */
93 #define TG3_MIN_MTU 60
94 #define TG3_MAX_MTU(tp) \
95 ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
97 /* These numbers seem to be hard coded in the NIC firmware somehow.
98 * You can't change the ring sizes, but you can change where you place
99 * them in the NIC onboard memory.
101 #define TG3_RX_RING_SIZE 512
102 #define TG3_DEF_RX_RING_PENDING 200
103 #define TG3_RX_JUMBO_RING_SIZE 256
104 #define TG3_DEF_RX_JUMBO_RING_PENDING 100
105 #define TG3_RSS_INDIR_TBL_SIZE 128
107 /* Do not place this n-ring entries value into the tp struct itself,
108 * we really want to expose these constants to GCC so that modulo et
109 * al. operations are done with shifts and masks instead of with
110 * hw multiply/modulo instructions. Another solution would be to
111 * replace things like '% foo' with '& (foo - 1)'.
113 #define TG3_RX_RCB_RING_SIZE(tp) \
114 (((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) && \
115 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) ? 1024 : 512)
117 #define TG3_TX_RING_SIZE 512
118 #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
120 #define TG3_RX_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
122 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_ext_rx_buffer_desc) * \
123 TG3_RX_JUMBO_RING_SIZE)
124 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
125 TG3_RX_RCB_RING_SIZE(tp))
126 #define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
128 #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
130 #define TG3_DMA_BYTE_ENAB 64
132 #define TG3_RX_STD_DMA_SZ 1536
133 #define TG3_RX_JMB_DMA_SZ 9046
135 #define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB)
137 #define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
138 #define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
140 #define TG3_RX_STD_BUFF_RING_SIZE \
141 (sizeof(struct ring_info) * TG3_RX_RING_SIZE)
143 #define TG3_RX_JMB_BUFF_RING_SIZE \
144 (sizeof(struct ring_info) * TG3_RX_JUMBO_RING_SIZE)
146 /* minimum number of free TX descriptors required to wake up TX process */
147 #define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
149 #define TG3_RAW_IP_ALIGN 2
151 /* number of ETHTOOL_GSTATS u64's */
152 #define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
154 #define TG3_NUM_TEST 6
156 #define FIRMWARE_TG3 "tigon/tg3.bin"
157 #define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
158 #define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
160 static char version[] __devinitdata =
161 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
163 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
164 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
165 MODULE_LICENSE("GPL");
166 MODULE_VERSION(DRV_MODULE_VERSION);
167 MODULE_FIRMWARE(FIRMWARE_TG3);
168 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
169 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
171 #define TG3_RSS_MIN_NUM_MSIX_VECS 2
173 static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
174 module_param(tg3_debug, int, 0);
175 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
177 static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = {
178 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
179 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
180 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
181 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
182 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
183 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
184 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
185 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
186 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
187 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
188 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
189 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
190 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
191 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
192 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
193 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
194 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
195 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
196 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
197 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
198 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
199 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
200 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
201 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
202 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
203 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
204 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
205 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
206 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
207 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
208 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
209 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
210 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
211 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
212 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
213 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
214 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
215 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
216 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
217 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
218 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
219 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
220 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
221 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
222 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
223 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
224 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
225 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
226 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
227 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
228 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
229 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
230 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
231 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
232 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
233 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
234 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
235 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
236 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
237 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
238 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
239 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
240 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
241 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
242 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
243 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
244 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
245 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
246 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5724)},
247 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
248 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
249 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
250 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
251 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791)},
252 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795)},
253 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
254 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
255 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
256 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
257 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
258 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
259 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
263 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
265 static const struct {
266 const char string[ETH_GSTRING_LEN];
267 } ethtool_stats_keys[TG3_NUM_STATS] = {
270 { "rx_ucast_packets" },
271 { "rx_mcast_packets" },
272 { "rx_bcast_packets" },
274 { "rx_align_errors" },
275 { "rx_xon_pause_rcvd" },
276 { "rx_xoff_pause_rcvd" },
277 { "rx_mac_ctrl_rcvd" },
278 { "rx_xoff_entered" },
279 { "rx_frame_too_long_errors" },
281 { "rx_undersize_packets" },
282 { "rx_in_length_errors" },
283 { "rx_out_length_errors" },
284 { "rx_64_or_less_octet_packets" },
285 { "rx_65_to_127_octet_packets" },
286 { "rx_128_to_255_octet_packets" },
287 { "rx_256_to_511_octet_packets" },
288 { "rx_512_to_1023_octet_packets" },
289 { "rx_1024_to_1522_octet_packets" },
290 { "rx_1523_to_2047_octet_packets" },
291 { "rx_2048_to_4095_octet_packets" },
292 { "rx_4096_to_8191_octet_packets" },
293 { "rx_8192_to_9022_octet_packets" },
300 { "tx_flow_control" },
302 { "tx_single_collisions" },
303 { "tx_mult_collisions" },
305 { "tx_excessive_collisions" },
306 { "tx_late_collisions" },
307 { "tx_collide_2times" },
308 { "tx_collide_3times" },
309 { "tx_collide_4times" },
310 { "tx_collide_5times" },
311 { "tx_collide_6times" },
312 { "tx_collide_7times" },
313 { "tx_collide_8times" },
314 { "tx_collide_9times" },
315 { "tx_collide_10times" },
316 { "tx_collide_11times" },
317 { "tx_collide_12times" },
318 { "tx_collide_13times" },
319 { "tx_collide_14times" },
320 { "tx_collide_15times" },
321 { "tx_ucast_packets" },
322 { "tx_mcast_packets" },
323 { "tx_bcast_packets" },
324 { "tx_carrier_sense_errors" },
328 { "dma_writeq_full" },
329 { "dma_write_prioq_full" },
333 { "rx_threshold_hit" },
335 { "dma_readq_full" },
336 { "dma_read_prioq_full" },
337 { "tx_comp_queue_full" },
339 { "ring_set_send_prod_index" },
340 { "ring_status_update" },
342 { "nic_avoided_irqs" },
343 { "nic_tx_threshold_hit" }
346 static const struct {
347 const char string[ETH_GSTRING_LEN];
348 } ethtool_test_keys[TG3_NUM_TEST] = {
349 { "nvram test (online) " },
350 { "link test (online) " },
351 { "register test (offline)" },
352 { "memory test (offline)" },
353 { "loopback test (offline)" },
354 { "interrupt test (offline)" },
357 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
359 writel(val, tp->regs + off);
362 static u32 tg3_read32(struct tg3 *tp, u32 off)
364 return (readl(tp->regs + off));
367 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
369 writel(val, tp->aperegs + off);
372 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
374 return (readl(tp->aperegs + off));
377 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
381 spin_lock_irqsave(&tp->indirect_lock, flags);
382 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
383 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
384 spin_unlock_irqrestore(&tp->indirect_lock, flags);
387 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
389 writel(val, tp->regs + off);
390 readl(tp->regs + off);
393 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
398 spin_lock_irqsave(&tp->indirect_lock, flags);
399 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
400 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
401 spin_unlock_irqrestore(&tp->indirect_lock, flags);
405 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
409 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
410 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
411 TG3_64BIT_REG_LOW, val);
414 if (off == TG3_RX_STD_PROD_IDX_REG) {
415 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
416 TG3_64BIT_REG_LOW, val);
420 spin_lock_irqsave(&tp->indirect_lock, flags);
421 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
422 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
423 spin_unlock_irqrestore(&tp->indirect_lock, flags);
425 /* In indirect mode when disabling interrupts, we also need
426 * to clear the interrupt bit in the GRC local ctrl register.
428 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
430 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
431 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
435 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
440 spin_lock_irqsave(&tp->indirect_lock, flags);
441 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
442 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
443 spin_unlock_irqrestore(&tp->indirect_lock, flags);
447 /* usec_wait specifies the wait time in usec when writing to certain registers
448 * where it is unsafe to read back the register without some delay.
449 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
450 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
452 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
454 if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
455 (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
456 /* Non-posted methods */
457 tp->write32(tp, off, val);
460 tg3_write32(tp, off, val);
465 /* Wait again after the read for the posted method to guarantee that
466 * the wait time is met.
472 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
474 tp->write32_mbox(tp, off, val);
475 if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
476 !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
477 tp->read32_mbox(tp, off);
480 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
482 void __iomem *mbox = tp->regs + off;
484 if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
486 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
490 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
492 return (readl(tp->regs + off + GRCMBOX_BASE));
495 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
497 writel(val, tp->regs + off + GRCMBOX_BASE);
500 #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
501 #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
502 #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
503 #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
504 #define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
506 #define tw32(reg,val) tp->write32(tp, reg, val)
507 #define tw32_f(reg,val) _tw32_flush(tp,(reg),(val), 0)
508 #define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
509 #define tr32(reg) tp->read32(tp, reg)
511 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
515 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
516 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
519 spin_lock_irqsave(&tp->indirect_lock, flags);
520 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
521 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
522 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
524 /* Always leave this as zero. */
525 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
527 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
528 tw32_f(TG3PCI_MEM_WIN_DATA, val);
530 /* Always leave this as zero. */
531 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
533 spin_unlock_irqrestore(&tp->indirect_lock, flags);
536 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
540 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
541 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
546 spin_lock_irqsave(&tp->indirect_lock, flags);
547 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
548 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
549 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
551 /* Always leave this as zero. */
552 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
554 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
555 *val = tr32(TG3PCI_MEM_WIN_DATA);
557 /* Always leave this as zero. */
558 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
560 spin_unlock_irqrestore(&tp->indirect_lock, flags);
563 static void tg3_ape_lock_init(struct tg3 *tp)
567 /* Make sure the driver hasn't any stale locks. */
568 for (i = 0; i < 8; i++)
569 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + 4 * i,
570 APE_LOCK_GRANT_DRIVER);
573 static int tg3_ape_lock(struct tg3 *tp, int locknum)
579 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
583 case TG3_APE_LOCK_GRC:
584 case TG3_APE_LOCK_MEM:
592 tg3_ape_write32(tp, TG3_APE_LOCK_REQ + off, APE_LOCK_REQ_DRIVER);
594 /* Wait for up to 1 millisecond to acquire lock. */
595 for (i = 0; i < 100; i++) {
596 status = tg3_ape_read32(tp, TG3_APE_LOCK_GRANT + off);
597 if (status == APE_LOCK_GRANT_DRIVER)
602 if (status != APE_LOCK_GRANT_DRIVER) {
603 /* Revoke the lock request. */
604 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off,
605 APE_LOCK_GRANT_DRIVER);
613 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
617 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
621 case TG3_APE_LOCK_GRC:
622 case TG3_APE_LOCK_MEM:
629 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off, APE_LOCK_GRANT_DRIVER);
632 static void tg3_disable_ints(struct tg3 *tp)
636 tw32(TG3PCI_MISC_HOST_CTRL,
637 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
638 for (i = 0; i < tp->irq_max; i++)
639 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
642 static void tg3_enable_ints(struct tg3 *tp)
649 tw32(TG3PCI_MISC_HOST_CTRL,
650 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
652 tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
653 for (i = 0; i < tp->irq_cnt; i++) {
654 struct tg3_napi *tnapi = &tp->napi[i];
655 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
656 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
657 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
659 tp->coal_now |= tnapi->coal_now;
662 /* Force an initial interrupt */
663 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
664 (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
665 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
667 tw32(HOSTCC_MODE, tp->coal_now);
669 tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);
672 static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
674 struct tg3 *tp = tnapi->tp;
675 struct tg3_hw_status *sblk = tnapi->hw_status;
676 unsigned int work_exists = 0;
678 /* check for phy events */
679 if (!(tp->tg3_flags &
680 (TG3_FLAG_USE_LINKCHG_REG |
681 TG3_FLAG_POLL_SERDES))) {
682 if (sblk->status & SD_STATUS_LINK_CHG)
685 /* check for RX/TX work to do */
686 if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
687 *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
694 * similar to tg3_enable_ints, but it accurately determines whether there
695 * is new work pending and can return without flushing the PIO write
696 * which reenables interrupts
698 static void tg3_int_reenable(struct tg3_napi *tnapi)
700 struct tg3 *tp = tnapi->tp;
702 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
705 /* When doing tagged status, this work check is unnecessary.
706 * The last_tag we write above tells the chip which piece of
707 * work we've completed.
709 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
711 tw32(HOSTCC_MODE, tp->coalesce_mode |
712 HOSTCC_MODE_ENABLE | tnapi->coal_now);
715 static void tg3_napi_disable(struct tg3 *tp)
719 for (i = tp->irq_cnt - 1; i >= 0; i--)
720 napi_disable(&tp->napi[i].napi);
723 static void tg3_napi_enable(struct tg3 *tp)
727 for (i = 0; i < tp->irq_cnt; i++)
728 napi_enable(&tp->napi[i].napi);
731 static inline void tg3_netif_stop(struct tg3 *tp)
733 tp->dev->trans_start = jiffies; /* prevent tx timeout */
734 tg3_napi_disable(tp);
735 netif_tx_disable(tp->dev);
738 static inline void tg3_netif_start(struct tg3 *tp)
740 /* NOTE: unconditional netif_tx_wake_all_queues is only
741 * appropriate so long as all callers are assured to
742 * have free tx slots (such as after tg3_init_hw)
744 netif_tx_wake_all_queues(tp->dev);
747 tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
751 static void tg3_switch_clocks(struct tg3 *tp)
756 if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
757 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
760 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
762 orig_clock_ctrl = clock_ctrl;
763 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
764 CLOCK_CTRL_CLKRUN_OENABLE |
766 tp->pci_clock_ctrl = clock_ctrl;
768 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
769 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
770 tw32_wait_f(TG3PCI_CLOCK_CTRL,
771 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
773 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
774 tw32_wait_f(TG3PCI_CLOCK_CTRL,
776 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
778 tw32_wait_f(TG3PCI_CLOCK_CTRL,
779 clock_ctrl | (CLOCK_CTRL_ALTCLK),
782 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
785 #define PHY_BUSY_LOOPS 5000
787 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
793 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
795 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
801 frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
802 MI_COM_PHY_ADDR_MASK);
803 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
804 MI_COM_REG_ADDR_MASK);
805 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
807 tw32_f(MAC_MI_COM, frame_val);
809 loops = PHY_BUSY_LOOPS;
812 frame_val = tr32(MAC_MI_COM);
814 if ((frame_val & MI_COM_BUSY) == 0) {
816 frame_val = tr32(MAC_MI_COM);
824 *val = frame_val & MI_COM_DATA_MASK;
828 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
829 tw32_f(MAC_MI_MODE, tp->mi_mode);
836 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
842 if ((tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
843 (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
846 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
848 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
852 frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
853 MI_COM_PHY_ADDR_MASK);
854 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
855 MI_COM_REG_ADDR_MASK);
856 frame_val |= (val & MI_COM_DATA_MASK);
857 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
859 tw32_f(MAC_MI_COM, frame_val);
861 loops = PHY_BUSY_LOOPS;
864 frame_val = tr32(MAC_MI_COM);
865 if ((frame_val & MI_COM_BUSY) == 0) {
867 frame_val = tr32(MAC_MI_COM);
877 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
878 tw32_f(MAC_MI_MODE, tp->mi_mode);
885 static int tg3_bmcr_reset(struct tg3 *tp)
890 /* OK, reset it, and poll the BMCR_RESET bit until it
891 * clears or we time out.
893 phy_control = BMCR_RESET;
894 err = tg3_writephy(tp, MII_BMCR, phy_control);
900 err = tg3_readphy(tp, MII_BMCR, &phy_control);
904 if ((phy_control & BMCR_RESET) == 0) {
916 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
918 struct tg3 *tp = bp->priv;
921 spin_lock_bh(&tp->lock);
923 if (tg3_readphy(tp, reg, &val))
926 spin_unlock_bh(&tp->lock);
931 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
933 struct tg3 *tp = bp->priv;
936 spin_lock_bh(&tp->lock);
938 if (tg3_writephy(tp, reg, val))
941 spin_unlock_bh(&tp->lock);
946 static int tg3_mdio_reset(struct mii_bus *bp)
951 static void tg3_mdio_config_5785(struct tg3 *tp)
954 struct phy_device *phydev;
956 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
957 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
958 case TG3_PHY_ID_BCM50610:
959 case TG3_PHY_ID_BCM50610M:
960 val = MAC_PHYCFG2_50610_LED_MODES;
962 case TG3_PHY_ID_BCMAC131:
963 val = MAC_PHYCFG2_AC131_LED_MODES;
965 case TG3_PHY_ID_RTL8211C:
966 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
968 case TG3_PHY_ID_RTL8201E:
969 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
975 if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
976 tw32(MAC_PHYCFG2, val);
978 val = tr32(MAC_PHYCFG1);
979 val &= ~(MAC_PHYCFG1_RGMII_INT |
980 MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
981 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
982 tw32(MAC_PHYCFG1, val);
987 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE))
988 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
989 MAC_PHYCFG2_FMODE_MASK_MASK |
990 MAC_PHYCFG2_GMODE_MASK_MASK |
991 MAC_PHYCFG2_ACT_MASK_MASK |
992 MAC_PHYCFG2_QUAL_MASK_MASK |
993 MAC_PHYCFG2_INBAND_ENABLE;
995 tw32(MAC_PHYCFG2, val);
997 val = tr32(MAC_PHYCFG1);
998 val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
999 MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
1000 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
1001 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1002 val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
1003 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1004 val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
1006 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1007 MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1008 tw32(MAC_PHYCFG1, val);
1010 val = tr32(MAC_EXT_RGMII_MODE);
1011 val &= ~(MAC_RGMII_MODE_RX_INT_B |
1012 MAC_RGMII_MODE_RX_QUALITY |
1013 MAC_RGMII_MODE_RX_ACTIVITY |
1014 MAC_RGMII_MODE_RX_ENG_DET |
1015 MAC_RGMII_MODE_TX_ENABLE |
1016 MAC_RGMII_MODE_TX_LOWPWR |
1017 MAC_RGMII_MODE_TX_RESET);
1018 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
1019 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1020 val |= MAC_RGMII_MODE_RX_INT_B |
1021 MAC_RGMII_MODE_RX_QUALITY |
1022 MAC_RGMII_MODE_RX_ACTIVITY |
1023 MAC_RGMII_MODE_RX_ENG_DET;
1024 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1025 val |= MAC_RGMII_MODE_TX_ENABLE |
1026 MAC_RGMII_MODE_TX_LOWPWR |
1027 MAC_RGMII_MODE_TX_RESET;
1029 tw32(MAC_EXT_RGMII_MODE, val);
1032 static void tg3_mdio_start(struct tg3 *tp)
1034 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1035 tw32_f(MAC_MI_MODE, tp->mi_mode);
1038 if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
1039 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1040 tg3_mdio_config_5785(tp);
1043 static int tg3_mdio_init(struct tg3 *tp)
1047 struct phy_device *phydev;
1049 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
1050 u32 funcnum, is_serdes;
1052 funcnum = tr32(TG3_CPMU_STATUS) & TG3_CPMU_STATUS_PCIE_FUNC;
1058 if (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
1059 is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1061 is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
1062 TG3_CPMU_PHY_STRAP_IS_SERDES;
1066 tp->phy_addr = TG3_PHY_MII_ADDR;
1070 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1071 (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1074 tp->mdio_bus = mdiobus_alloc();
1075 if (tp->mdio_bus == NULL)
1078 tp->mdio_bus->name = "tg3 mdio bus";
1079 snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1080 (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1081 tp->mdio_bus->priv = tp;
1082 tp->mdio_bus->parent = &tp->pdev->dev;
1083 tp->mdio_bus->read = &tg3_mdio_read;
1084 tp->mdio_bus->write = &tg3_mdio_write;
1085 tp->mdio_bus->reset = &tg3_mdio_reset;
1086 tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
1087 tp->mdio_bus->irq = &tp->mdio_irq[0];
1089 for (i = 0; i < PHY_MAX_ADDR; i++)
1090 tp->mdio_bus->irq[i] = PHY_POLL;
1092 /* The bus registration will look for all the PHYs on the mdio bus.
1093 * Unfortunately, it does not ensure the PHY is powered up before
1094 * accessing the PHY ID registers. A chip reset is the
1095 * quickest way to bring the device back to an operational state..
1097 if (tg3_readphy(tp, MII_BMCR, ®) || (reg & BMCR_PDOWN))
1100 i = mdiobus_register(tp->mdio_bus);
1102 printk(KERN_WARNING "%s: mdiobus_reg failed (0x%x)\n",
1104 mdiobus_free(tp->mdio_bus);
1108 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1110 if (!phydev || !phydev->drv) {
1111 printk(KERN_WARNING "%s: No PHY devices\n", tp->dev->name);
1112 mdiobus_unregister(tp->mdio_bus);
1113 mdiobus_free(tp->mdio_bus);
1117 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1118 case TG3_PHY_ID_BCM57780:
1119 phydev->interface = PHY_INTERFACE_MODE_GMII;
1120 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1122 case TG3_PHY_ID_BCM50610:
1123 case TG3_PHY_ID_BCM50610M:
1124 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
1125 PHY_BRCM_RX_REFCLK_UNUSED |
1126 PHY_BRCM_DIS_TXCRXC_NOENRGY |
1127 PHY_BRCM_AUTO_PWRDWN_ENABLE;
1128 if (tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)
1129 phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1130 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1131 phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1132 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1133 phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1135 case TG3_PHY_ID_RTL8211C:
1136 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1138 case TG3_PHY_ID_RTL8201E:
1139 case TG3_PHY_ID_BCMAC131:
1140 phydev->interface = PHY_INTERFACE_MODE_MII;
1141 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1142 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
1146 tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1148 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1149 tg3_mdio_config_5785(tp);
1154 static void tg3_mdio_fini(struct tg3 *tp)
1156 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1157 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
1158 mdiobus_unregister(tp->mdio_bus);
1159 mdiobus_free(tp->mdio_bus);
1163 /* tp->lock is held. */
1164 static inline void tg3_generate_fw_event(struct tg3 *tp)
1168 val = tr32(GRC_RX_CPU_EVENT);
1169 val |= GRC_RX_CPU_DRIVER_EVENT;
1170 tw32_f(GRC_RX_CPU_EVENT, val);
1172 tp->last_event_jiffies = jiffies;
1175 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1177 /* tp->lock is held. */
1178 static void tg3_wait_for_event_ack(struct tg3 *tp)
1181 unsigned int delay_cnt;
1184 /* If enough time has passed, no wait is necessary. */
1185 time_remain = (long)(tp->last_event_jiffies + 1 +
1186 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1188 if (time_remain < 0)
1191 /* Check if we can shorten the wait time. */
1192 delay_cnt = jiffies_to_usecs(time_remain);
1193 if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1194 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1195 delay_cnt = (delay_cnt >> 3) + 1;
1197 for (i = 0; i < delay_cnt; i++) {
1198 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1204 /* tp->lock is held. */
1205 static void tg3_ump_link_report(struct tg3 *tp)
1210 if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1211 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
1214 tg3_wait_for_event_ack(tp);
1216 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1218 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1221 if (!tg3_readphy(tp, MII_BMCR, ®))
1223 if (!tg3_readphy(tp, MII_BMSR, ®))
1224 val |= (reg & 0xffff);
1225 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1228 if (!tg3_readphy(tp, MII_ADVERTISE, ®))
1230 if (!tg3_readphy(tp, MII_LPA, ®))
1231 val |= (reg & 0xffff);
1232 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1235 if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) {
1236 if (!tg3_readphy(tp, MII_CTRL1000, ®))
1238 if (!tg3_readphy(tp, MII_STAT1000, ®))
1239 val |= (reg & 0xffff);
1241 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1243 if (!tg3_readphy(tp, MII_PHYADDR, ®))
1247 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1249 tg3_generate_fw_event(tp);
1252 static void tg3_link_report(struct tg3 *tp)
1254 if (!netif_carrier_ok(tp->dev)) {
1255 if (netif_msg_link(tp))
1256 printk(KERN_INFO PFX "%s: Link is down.\n",
1258 tg3_ump_link_report(tp);
1259 } else if (netif_msg_link(tp)) {
1260 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1262 (tp->link_config.active_speed == SPEED_1000 ?
1264 (tp->link_config.active_speed == SPEED_100 ?
1266 (tp->link_config.active_duplex == DUPLEX_FULL ?
1269 printk(KERN_INFO PFX
1270 "%s: Flow control is %s for TX and %s for RX.\n",
1272 (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1274 (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1276 tg3_ump_link_report(tp);
1280 static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1284 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1285 miireg = ADVERTISE_PAUSE_CAP;
1286 else if (flow_ctrl & FLOW_CTRL_TX)
1287 miireg = ADVERTISE_PAUSE_ASYM;
1288 else if (flow_ctrl & FLOW_CTRL_RX)
1289 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1296 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1300 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1301 miireg = ADVERTISE_1000XPAUSE;
1302 else if (flow_ctrl & FLOW_CTRL_TX)
1303 miireg = ADVERTISE_1000XPSE_ASYM;
1304 else if (flow_ctrl & FLOW_CTRL_RX)
1305 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1312 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1316 if (lcladv & ADVERTISE_1000XPAUSE) {
1317 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1318 if (rmtadv & LPA_1000XPAUSE)
1319 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1320 else if (rmtadv & LPA_1000XPAUSE_ASYM)
1323 if (rmtadv & LPA_1000XPAUSE)
1324 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1326 } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1327 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1334 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1338 u32 old_rx_mode = tp->rx_mode;
1339 u32 old_tx_mode = tp->tx_mode;
1341 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
1342 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
1344 autoneg = tp->link_config.autoneg;
1346 if (autoneg == AUTONEG_ENABLE &&
1347 (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1348 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1349 flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1351 flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1353 flowctrl = tp->link_config.flowctrl;
1355 tp->link_config.active_flowctrl = flowctrl;
1357 if (flowctrl & FLOW_CTRL_RX)
1358 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1360 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1362 if (old_rx_mode != tp->rx_mode)
1363 tw32_f(MAC_RX_MODE, tp->rx_mode);
1365 if (flowctrl & FLOW_CTRL_TX)
1366 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1368 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1370 if (old_tx_mode != tp->tx_mode)
1371 tw32_f(MAC_TX_MODE, tp->tx_mode);
1374 static void tg3_adjust_link(struct net_device *dev)
1376 u8 oldflowctrl, linkmesg = 0;
1377 u32 mac_mode, lcl_adv, rmt_adv;
1378 struct tg3 *tp = netdev_priv(dev);
1379 struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1381 spin_lock_bh(&tp->lock);
1383 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1384 MAC_MODE_HALF_DUPLEX);
1386 oldflowctrl = tp->link_config.active_flowctrl;
1392 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1393 mac_mode |= MAC_MODE_PORT_MODE_MII;
1394 else if (phydev->speed == SPEED_1000 ||
1395 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
1396 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1398 mac_mode |= MAC_MODE_PORT_MODE_MII;
1400 if (phydev->duplex == DUPLEX_HALF)
1401 mac_mode |= MAC_MODE_HALF_DUPLEX;
1403 lcl_adv = tg3_advert_flowctrl_1000T(
1404 tp->link_config.flowctrl);
1407 rmt_adv = LPA_PAUSE_CAP;
1408 if (phydev->asym_pause)
1409 rmt_adv |= LPA_PAUSE_ASYM;
1412 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1414 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1416 if (mac_mode != tp->mac_mode) {
1417 tp->mac_mode = mac_mode;
1418 tw32_f(MAC_MODE, tp->mac_mode);
1422 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1423 if (phydev->speed == SPEED_10)
1425 MAC_MI_STAT_10MBPS_MODE |
1426 MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1428 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1431 if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1432 tw32(MAC_TX_LENGTHS,
1433 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1434 (6 << TX_LENGTHS_IPG_SHIFT) |
1435 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1437 tw32(MAC_TX_LENGTHS,
1438 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1439 (6 << TX_LENGTHS_IPG_SHIFT) |
1440 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1442 if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1443 (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1444 phydev->speed != tp->link_config.active_speed ||
1445 phydev->duplex != tp->link_config.active_duplex ||
1446 oldflowctrl != tp->link_config.active_flowctrl)
1449 tp->link_config.active_speed = phydev->speed;
1450 tp->link_config.active_duplex = phydev->duplex;
1452 spin_unlock_bh(&tp->lock);
1455 tg3_link_report(tp);
1458 static int tg3_phy_init(struct tg3 *tp)
1460 struct phy_device *phydev;
1462 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
1465 /* Bring the PHY back to a known state. */
1468 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1470 /* Attach the MAC to the PHY. */
1471 phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
1472 phydev->dev_flags, phydev->interface);
1473 if (IS_ERR(phydev)) {
1474 printk(KERN_ERR "%s: Could not attach to PHY\n", tp->dev->name);
1475 return PTR_ERR(phydev);
1478 /* Mask with MAC supported features. */
1479 switch (phydev->interface) {
1480 case PHY_INTERFACE_MODE_GMII:
1481 case PHY_INTERFACE_MODE_RGMII:
1482 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1483 phydev->supported &= (PHY_GBIT_FEATURES |
1485 SUPPORTED_Asym_Pause);
1489 case PHY_INTERFACE_MODE_MII:
1490 phydev->supported &= (PHY_BASIC_FEATURES |
1492 SUPPORTED_Asym_Pause);
1495 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1499 tp->tg3_flags3 |= TG3_FLG3_PHY_CONNECTED;
1501 phydev->advertising = phydev->supported;
1506 static void tg3_phy_start(struct tg3 *tp)
1508 struct phy_device *phydev;
1510 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1513 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1515 if (tp->link_config.phy_is_low_power) {
1516 tp->link_config.phy_is_low_power = 0;
1517 phydev->speed = tp->link_config.orig_speed;
1518 phydev->duplex = tp->link_config.orig_duplex;
1519 phydev->autoneg = tp->link_config.orig_autoneg;
1520 phydev->advertising = tp->link_config.orig_advertising;
1525 phy_start_aneg(phydev);
1528 static void tg3_phy_stop(struct tg3 *tp)
1530 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1533 phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1536 static void tg3_phy_fini(struct tg3 *tp)
1538 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
1539 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1540 tp->tg3_flags3 &= ~TG3_FLG3_PHY_CONNECTED;
1544 static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1546 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1547 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1550 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1554 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1557 tg3_writephy(tp, MII_TG3_FET_TEST,
1558 phytest | MII_TG3_FET_SHADOW_EN);
1559 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1561 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1563 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1564 tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1566 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1570 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1574 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1575 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
1576 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
1579 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1580 tg3_phy_fet_toggle_apd(tp, enable);
1584 reg = MII_TG3_MISC_SHDW_WREN |
1585 MII_TG3_MISC_SHDW_SCR5_SEL |
1586 MII_TG3_MISC_SHDW_SCR5_LPED |
1587 MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1588 MII_TG3_MISC_SHDW_SCR5_SDTL |
1589 MII_TG3_MISC_SHDW_SCR5_C125OE;
1590 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1591 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1593 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1596 reg = MII_TG3_MISC_SHDW_WREN |
1597 MII_TG3_MISC_SHDW_APD_SEL |
1598 MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1600 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1602 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1605 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1609 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1610 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1613 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1616 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1617 u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1619 tg3_writephy(tp, MII_TG3_FET_TEST,
1620 ephy | MII_TG3_FET_SHADOW_EN);
1621 if (!tg3_readphy(tp, reg, &phy)) {
1623 phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1625 phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1626 tg3_writephy(tp, reg, phy);
1628 tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
1631 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1632 MII_TG3_AUXCTL_SHDWSEL_MISC;
1633 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1634 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1636 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1638 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1639 phy |= MII_TG3_AUXCTL_MISC_WREN;
1640 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1645 static void tg3_phy_set_wirespeed(struct tg3 *tp)
1649 if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
1652 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1653 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1654 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1655 (val | (1 << 15) | (1 << 4)));
1658 static void tg3_phy_apply_otp(struct tg3 *tp)
1667 /* Enable SM_DSP clock and tx 6dB coding. */
1668 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1669 MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1670 MII_TG3_AUXCTL_ACTL_TX_6DB;
1671 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1673 phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1674 phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1675 tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1677 phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1678 ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1679 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1681 phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1682 phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1683 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1685 phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1686 tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1688 phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1689 tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1691 phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1692 ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1693 tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1695 /* Turn off SM_DSP clock. */
1696 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1697 MII_TG3_AUXCTL_ACTL_TX_6DB;
1698 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1701 static int tg3_wait_macro_done(struct tg3 *tp)
1708 if (!tg3_readphy(tp, 0x16, &tmp32)) {
1709 if ((tmp32 & 0x1000) == 0)
1719 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1721 static const u32 test_pat[4][6] = {
1722 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1723 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1724 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1725 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1729 for (chan = 0; chan < 4; chan++) {
1732 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1733 (chan * 0x2000) | 0x0200);
1734 tg3_writephy(tp, 0x16, 0x0002);
1736 for (i = 0; i < 6; i++)
1737 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1740 tg3_writephy(tp, 0x16, 0x0202);
1741 if (tg3_wait_macro_done(tp)) {
1746 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1747 (chan * 0x2000) | 0x0200);
1748 tg3_writephy(tp, 0x16, 0x0082);
1749 if (tg3_wait_macro_done(tp)) {
1754 tg3_writephy(tp, 0x16, 0x0802);
1755 if (tg3_wait_macro_done(tp)) {
1760 for (i = 0; i < 6; i += 2) {
1763 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1764 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1765 tg3_wait_macro_done(tp)) {
1771 if (low != test_pat[chan][i] ||
1772 high != test_pat[chan][i+1]) {
1773 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1774 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1775 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1785 static int tg3_phy_reset_chanpat(struct tg3 *tp)
1789 for (chan = 0; chan < 4; chan++) {
1792 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1793 (chan * 0x2000) | 0x0200);
1794 tg3_writephy(tp, 0x16, 0x0002);
1795 for (i = 0; i < 6; i++)
1796 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1797 tg3_writephy(tp, 0x16, 0x0202);
1798 if (tg3_wait_macro_done(tp))
1805 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1807 u32 reg32, phy9_orig;
1808 int retries, do_phy_reset, err;
1814 err = tg3_bmcr_reset(tp);
1820 /* Disable transmitter and interrupt. */
1821 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32))
1825 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1827 /* Set full-duplex, 1000 mbps. */
1828 tg3_writephy(tp, MII_BMCR,
1829 BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1831 /* Set to master mode. */
1832 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1835 tg3_writephy(tp, MII_TG3_CTRL,
1836 (MII_TG3_CTRL_AS_MASTER |
1837 MII_TG3_CTRL_ENABLE_AS_MASTER));
1839 /* Enable SM_DSP_CLOCK and 6dB. */
1840 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1842 /* Block the PHY control access. */
1843 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1844 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
1846 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1849 } while (--retries);
1851 err = tg3_phy_reset_chanpat(tp);
1855 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1856 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
1858 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1859 tg3_writephy(tp, 0x16, 0x0000);
1861 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1862 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1863 /* Set Extended packet length bit for jumbo frames */
1864 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1867 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1870 tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1872 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32)) {
1874 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1881 /* This will reset the tigon3 PHY if there is no valid
1882 * link unless the FORCE argument is non-zero.
1884 static int tg3_phy_reset(struct tg3 *tp)
1890 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1893 val = tr32(GRC_MISC_CFG);
1894 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1897 err = tg3_readphy(tp, MII_BMSR, &phy_status);
1898 err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1902 if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1903 netif_carrier_off(tp->dev);
1904 tg3_link_report(tp);
1907 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1908 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1909 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1910 err = tg3_phy_reset_5703_4_5(tp);
1917 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1918 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1919 cpmuctrl = tr32(TG3_CPMU_CTRL);
1920 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1922 cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1925 err = tg3_bmcr_reset(tp);
1929 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1932 phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1933 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy);
1935 tw32(TG3_CPMU_CTRL, cpmuctrl);
1938 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
1939 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
1942 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1943 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1944 CPMU_LSPD_1000MB_MACCLK_12_5) {
1945 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1947 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1951 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
1952 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES))
1955 tg3_phy_apply_otp(tp);
1957 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
1958 tg3_phy_toggle_apd(tp, true);
1960 tg3_phy_toggle_apd(tp, false);
1963 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1964 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1965 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1966 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1967 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1968 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
1969 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1971 if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
1972 tg3_writephy(tp, 0x1c, 0x8d68);
1973 tg3_writephy(tp, 0x1c, 0x8d68);
1975 if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1976 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1977 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1978 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1979 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1980 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1981 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1982 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1983 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1985 else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1986 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1987 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1988 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1989 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1990 tg3_writephy(tp, MII_TG3_TEST1,
1991 MII_TG3_TEST1_TRIM_EN | 0x4);
1993 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
1994 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1996 /* Set Extended packet length bit (bit 14) on all chips that */
1997 /* support jumbo frames */
1998 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1999 /* Cannot do read-modify-write on 5401 */
2000 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2001 } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2004 /* Set bit 14 with read-modify-write to preserve other bits */
2005 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
2006 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
2007 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
2010 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
2011 * jumbo frames transmission.
2013 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2016 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
2017 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2018 phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
2021 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2022 /* adjust output voltage */
2023 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
2026 tg3_phy_toggle_automdix(tp, 1);
2027 tg3_phy_set_wirespeed(tp);
2031 static void tg3_frob_aux_power(struct tg3 *tp)
2033 struct tg3 *tp_peer = tp;
2035 /* The GPIOs do something completely different on 57765. */
2036 if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0 ||
2037 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
2040 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2041 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
2042 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
2043 struct net_device *dev_peer;
2045 dev_peer = pci_get_drvdata(tp->pdev_peer);
2046 /* remove_one() may have been run on the peer. */
2050 tp_peer = netdev_priv(dev_peer);
2053 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2054 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
2055 (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2056 (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
2057 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2058 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2059 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2060 (GRC_LCLCTRL_GPIO_OE0 |
2061 GRC_LCLCTRL_GPIO_OE1 |
2062 GRC_LCLCTRL_GPIO_OE2 |
2063 GRC_LCLCTRL_GPIO_OUTPUT0 |
2064 GRC_LCLCTRL_GPIO_OUTPUT1),
2066 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2067 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2068 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2069 u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2070 GRC_LCLCTRL_GPIO_OE1 |
2071 GRC_LCLCTRL_GPIO_OE2 |
2072 GRC_LCLCTRL_GPIO_OUTPUT0 |
2073 GRC_LCLCTRL_GPIO_OUTPUT1 |
2075 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2077 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2078 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2080 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2081 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2084 u32 grc_local_ctrl = 0;
2086 if (tp_peer != tp &&
2087 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2090 /* Workaround to prevent overdrawing Amps. */
2091 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2093 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2094 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2095 grc_local_ctrl, 100);
2098 /* On 5753 and variants, GPIO2 cannot be used. */
2099 no_gpio2 = tp->nic_sram_data_cfg &
2100 NIC_SRAM_DATA_CFG_NO_GPIO2;
2102 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2103 GRC_LCLCTRL_GPIO_OE1 |
2104 GRC_LCLCTRL_GPIO_OE2 |
2105 GRC_LCLCTRL_GPIO_OUTPUT1 |
2106 GRC_LCLCTRL_GPIO_OUTPUT2;
2108 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2109 GRC_LCLCTRL_GPIO_OUTPUT2);
2111 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2112 grc_local_ctrl, 100);
2114 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2116 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2117 grc_local_ctrl, 100);
2120 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2121 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2122 grc_local_ctrl, 100);
2126 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2127 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2128 if (tp_peer != tp &&
2129 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2132 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2133 (GRC_LCLCTRL_GPIO_OE1 |
2134 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2136 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2137 GRC_LCLCTRL_GPIO_OE1, 100);
2139 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2140 (GRC_LCLCTRL_GPIO_OE1 |
2141 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2146 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2148 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2150 else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411) {
2151 if (speed != SPEED_10)
2153 } else if (speed == SPEED_10)
2159 static int tg3_setup_phy(struct tg3 *, int);
2161 #define RESET_KIND_SHUTDOWN 0
2162 #define RESET_KIND_INIT 1
2163 #define RESET_KIND_SUSPEND 2
2165 static void tg3_write_sig_post_reset(struct tg3 *, int);
2166 static int tg3_halt_cpu(struct tg3 *, u32);
2168 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2172 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2173 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2174 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2175 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2178 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2179 tw32(SG_DIG_CTRL, sg_dig_ctrl);
2180 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2185 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2187 val = tr32(GRC_MISC_CFG);
2188 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2191 } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
2193 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2196 tg3_writephy(tp, MII_ADVERTISE, 0);
2197 tg3_writephy(tp, MII_BMCR,
2198 BMCR_ANENABLE | BMCR_ANRESTART);
2200 tg3_writephy(tp, MII_TG3_FET_TEST,
2201 phytest | MII_TG3_FET_SHADOW_EN);
2202 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
2203 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
2205 MII_TG3_FET_SHDW_AUXMODE4,
2208 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2211 } else if (do_low_power) {
2212 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2213 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
2215 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2216 MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2217 MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2218 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2219 MII_TG3_AUXCTL_PCTL_VREG_11V);
2222 /* The PHY should not be powered down on some chips because
2225 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2226 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2227 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2228 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
2231 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2232 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2233 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2234 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2235 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2236 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2239 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2242 /* tp->lock is held. */
2243 static int tg3_nvram_lock(struct tg3 *tp)
2245 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2248 if (tp->nvram_lock_cnt == 0) {
2249 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2250 for (i = 0; i < 8000; i++) {
2251 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2256 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2260 tp->nvram_lock_cnt++;
2265 /* tp->lock is held. */
2266 static void tg3_nvram_unlock(struct tg3 *tp)
2268 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2269 if (tp->nvram_lock_cnt > 0)
2270 tp->nvram_lock_cnt--;
2271 if (tp->nvram_lock_cnt == 0)
2272 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2276 /* tp->lock is held. */
2277 static void tg3_enable_nvram_access(struct tg3 *tp)
2279 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2280 !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2281 u32 nvaccess = tr32(NVRAM_ACCESS);
2283 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2287 /* tp->lock is held. */
2288 static void tg3_disable_nvram_access(struct tg3 *tp)
2290 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2291 !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2292 u32 nvaccess = tr32(NVRAM_ACCESS);
2294 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2298 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2299 u32 offset, u32 *val)
2304 if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2307 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2308 EEPROM_ADDR_DEVID_MASK |
2310 tw32(GRC_EEPROM_ADDR,
2312 (0 << EEPROM_ADDR_DEVID_SHIFT) |
2313 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2314 EEPROM_ADDR_ADDR_MASK) |
2315 EEPROM_ADDR_READ | EEPROM_ADDR_START);
2317 for (i = 0; i < 1000; i++) {
2318 tmp = tr32(GRC_EEPROM_ADDR);
2320 if (tmp & EEPROM_ADDR_COMPLETE)
2324 if (!(tmp & EEPROM_ADDR_COMPLETE))
2327 tmp = tr32(GRC_EEPROM_DATA);
2330 * The data will always be opposite the native endian
2331 * format. Perform a blind byteswap to compensate.
2338 #define NVRAM_CMD_TIMEOUT 10000
2340 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2344 tw32(NVRAM_CMD, nvram_cmd);
2345 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2347 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2353 if (i == NVRAM_CMD_TIMEOUT)
2359 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2361 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2362 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2363 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2364 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2365 (tp->nvram_jedecnum == JEDEC_ATMEL))
2367 addr = ((addr / tp->nvram_pagesize) <<
2368 ATMEL_AT45DB0X1B_PAGE_POS) +
2369 (addr % tp->nvram_pagesize);
2374 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2376 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2377 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2378 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2379 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2380 (tp->nvram_jedecnum == JEDEC_ATMEL))
2382 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2383 tp->nvram_pagesize) +
2384 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2389 /* NOTE: Data read in from NVRAM is byteswapped according to
2390 * the byteswapping settings for all other register accesses.
2391 * tg3 devices are BE devices, so on a BE machine, the data
2392 * returned will be exactly as it is seen in NVRAM. On a LE
2393 * machine, the 32-bit value will be byteswapped.
2395 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2399 if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2400 return tg3_nvram_read_using_eeprom(tp, offset, val);
2402 offset = tg3_nvram_phys_addr(tp, offset);
2404 if (offset > NVRAM_ADDR_MSK)
2407 ret = tg3_nvram_lock(tp);
2411 tg3_enable_nvram_access(tp);
2413 tw32(NVRAM_ADDR, offset);
2414 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2415 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2418 *val = tr32(NVRAM_RDDATA);
2420 tg3_disable_nvram_access(tp);
2422 tg3_nvram_unlock(tp);
2427 /* Ensures NVRAM data is in bytestream format. */
2428 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
2431 int res = tg3_nvram_read(tp, offset, &v);
2433 *val = cpu_to_be32(v);
2437 /* tp->lock is held. */
2438 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2440 u32 addr_high, addr_low;
2443 addr_high = ((tp->dev->dev_addr[0] << 8) |
2444 tp->dev->dev_addr[1]);
2445 addr_low = ((tp->dev->dev_addr[2] << 24) |
2446 (tp->dev->dev_addr[3] << 16) |
2447 (tp->dev->dev_addr[4] << 8) |
2448 (tp->dev->dev_addr[5] << 0));
2449 for (i = 0; i < 4; i++) {
2450 if (i == 1 && skip_mac_1)
2452 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2453 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2456 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2457 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2458 for (i = 0; i < 12; i++) {
2459 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2460 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2464 addr_high = (tp->dev->dev_addr[0] +
2465 tp->dev->dev_addr[1] +
2466 tp->dev->dev_addr[2] +
2467 tp->dev->dev_addr[3] +
2468 tp->dev->dev_addr[4] +
2469 tp->dev->dev_addr[5]) &
2470 TX_BACKOFF_SEED_MASK;
2471 tw32(MAC_TX_BACKOFF_SEED, addr_high);
2474 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
2477 bool device_should_wake, do_low_power;
2479 /* Make sure register accesses (indirect or otherwise)
2480 * will function correctly.
2482 pci_write_config_dword(tp->pdev,
2483 TG3PCI_MISC_HOST_CTRL,
2484 tp->misc_host_ctrl);
2488 pci_enable_wake(tp->pdev, state, false);
2489 pci_set_power_state(tp->pdev, PCI_D0);
2491 /* Switch out of Vaux if it is a NIC */
2492 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
2493 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
2503 printk(KERN_ERR PFX "%s: Invalid power state (D%d) requested\n",
2504 tp->dev->name, state);
2508 /* Restore the CLKREQ setting. */
2509 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2512 pci_read_config_word(tp->pdev,
2513 tp->pcie_cap + PCI_EXP_LNKCTL,
2515 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2516 pci_write_config_word(tp->pdev,
2517 tp->pcie_cap + PCI_EXP_LNKCTL,
2521 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2522 tw32(TG3PCI_MISC_HOST_CTRL,
2523 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2525 device_should_wake = pci_pme_capable(tp->pdev, state) &&
2526 device_may_wakeup(&tp->pdev->dev) &&
2527 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2529 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
2530 do_low_power = false;
2531 if ((tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) &&
2532 !tp->link_config.phy_is_low_power) {
2533 struct phy_device *phydev;
2534 u32 phyid, advertising;
2536 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
2538 tp->link_config.phy_is_low_power = 1;
2540 tp->link_config.orig_speed = phydev->speed;
2541 tp->link_config.orig_duplex = phydev->duplex;
2542 tp->link_config.orig_autoneg = phydev->autoneg;
2543 tp->link_config.orig_advertising = phydev->advertising;
2545 advertising = ADVERTISED_TP |
2547 ADVERTISED_Autoneg |
2548 ADVERTISED_10baseT_Half;
2550 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2551 device_should_wake) {
2552 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2554 ADVERTISED_100baseT_Half |
2555 ADVERTISED_100baseT_Full |
2556 ADVERTISED_10baseT_Full;
2558 advertising |= ADVERTISED_10baseT_Full;
2561 phydev->advertising = advertising;
2563 phy_start_aneg(phydev);
2565 phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2566 if (phyid != TG3_PHY_ID_BCMAC131) {
2567 phyid &= TG3_PHY_OUI_MASK;
2568 if (phyid == TG3_PHY_OUI_1 ||
2569 phyid == TG3_PHY_OUI_2 ||
2570 phyid == TG3_PHY_OUI_3)
2571 do_low_power = true;
2575 do_low_power = true;
2577 if (tp->link_config.phy_is_low_power == 0) {
2578 tp->link_config.phy_is_low_power = 1;
2579 tp->link_config.orig_speed = tp->link_config.speed;
2580 tp->link_config.orig_duplex = tp->link_config.duplex;
2581 tp->link_config.orig_autoneg = tp->link_config.autoneg;
2584 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
2585 tp->link_config.speed = SPEED_10;
2586 tp->link_config.duplex = DUPLEX_HALF;
2587 tp->link_config.autoneg = AUTONEG_ENABLE;
2588 tg3_setup_phy(tp, 0);
2592 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2595 val = tr32(GRC_VCPU_EXT_CTRL);
2596 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2597 } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2601 for (i = 0; i < 200; i++) {
2602 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2603 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2608 if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2609 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2610 WOL_DRV_STATE_SHUTDOWN |
2614 if (device_should_wake) {
2617 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
2619 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2623 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
2624 mac_mode = MAC_MODE_PORT_MODE_GMII;
2626 mac_mode = MAC_MODE_PORT_MODE_MII;
2628 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2629 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2631 u32 speed = (tp->tg3_flags &
2632 TG3_FLAG_WOL_SPEED_100MB) ?
2633 SPEED_100 : SPEED_10;
2634 if (tg3_5700_link_polarity(tp, speed))
2635 mac_mode |= MAC_MODE_LINK_POLARITY;
2637 mac_mode &= ~MAC_MODE_LINK_POLARITY;
2640 mac_mode = MAC_MODE_PORT_MODE_TBI;
2643 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
2644 tw32(MAC_LED_CTRL, tp->led_ctrl);
2646 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2647 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2648 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2649 ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2650 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2651 mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
2653 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2654 mac_mode |= tp->mac_mode &
2655 (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
2656 if (mac_mode & MAC_MODE_APE_TX_EN)
2657 mac_mode |= MAC_MODE_TDE_ENABLE;
2660 tw32_f(MAC_MODE, mac_mode);
2663 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2667 if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2668 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2669 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2672 base_val = tp->pci_clock_ctrl;
2673 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2674 CLOCK_CTRL_TXCLK_DISABLE);
2676 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2677 CLOCK_CTRL_PWRDOWN_PLL133, 40);
2678 } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
2679 (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
2680 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
2682 } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2683 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2684 u32 newbits1, newbits2;
2686 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2687 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2688 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2689 CLOCK_CTRL_TXCLK_DISABLE |
2691 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2692 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2693 newbits1 = CLOCK_CTRL_625_CORE;
2694 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2696 newbits1 = CLOCK_CTRL_ALTCLK;
2697 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2700 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2703 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2706 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2709 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2710 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2711 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2712 CLOCK_CTRL_TXCLK_DISABLE |
2713 CLOCK_CTRL_44MHZ_CORE);
2715 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2718 tw32_wait_f(TG3PCI_CLOCK_CTRL,
2719 tp->pci_clock_ctrl | newbits3, 40);
2723 if (!(device_should_wake) &&
2724 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
2725 tg3_power_down_phy(tp, do_low_power);
2727 tg3_frob_aux_power(tp);
2729 /* Workaround for unstable PLL clock */
2730 if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2731 (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2732 u32 val = tr32(0x7d00);
2734 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2736 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2739 err = tg3_nvram_lock(tp);
2740 tg3_halt_cpu(tp, RX_CPU_BASE);
2742 tg3_nvram_unlock(tp);
2746 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2748 if (device_should_wake)
2749 pci_enable_wake(tp->pdev, state, true);
2751 /* Finally, set the new power state. */
2752 pci_set_power_state(tp->pdev, state);
2757 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2759 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2760 case MII_TG3_AUX_STAT_10HALF:
2762 *duplex = DUPLEX_HALF;
2765 case MII_TG3_AUX_STAT_10FULL:
2767 *duplex = DUPLEX_FULL;
2770 case MII_TG3_AUX_STAT_100HALF:
2772 *duplex = DUPLEX_HALF;
2775 case MII_TG3_AUX_STAT_100FULL:
2777 *duplex = DUPLEX_FULL;
2780 case MII_TG3_AUX_STAT_1000HALF:
2781 *speed = SPEED_1000;
2782 *duplex = DUPLEX_HALF;
2785 case MII_TG3_AUX_STAT_1000FULL:
2786 *speed = SPEED_1000;
2787 *duplex = DUPLEX_FULL;
2791 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
2792 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2794 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2798 *speed = SPEED_INVALID;
2799 *duplex = DUPLEX_INVALID;
2804 static void tg3_phy_copper_begin(struct tg3 *tp)
2809 if (tp->link_config.phy_is_low_power) {
2810 /* Entering low power mode. Disable gigabit and
2811 * 100baseT advertisements.
2813 tg3_writephy(tp, MII_TG3_CTRL, 0);
2815 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2816 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2817 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2818 new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2820 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2821 } else if (tp->link_config.speed == SPEED_INVALID) {
2822 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
2823 tp->link_config.advertising &=
2824 ~(ADVERTISED_1000baseT_Half |
2825 ADVERTISED_1000baseT_Full);
2827 new_adv = ADVERTISE_CSMA;
2828 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2829 new_adv |= ADVERTISE_10HALF;
2830 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2831 new_adv |= ADVERTISE_10FULL;
2832 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2833 new_adv |= ADVERTISE_100HALF;
2834 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2835 new_adv |= ADVERTISE_100FULL;
2837 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2839 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2841 if (tp->link_config.advertising &
2842 (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2844 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2845 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2846 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2847 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2848 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
2849 (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2850 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2851 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2852 MII_TG3_CTRL_ENABLE_AS_MASTER);
2853 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2855 tg3_writephy(tp, MII_TG3_CTRL, 0);
2858 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2859 new_adv |= ADVERTISE_CSMA;
2861 /* Asking for a specific link mode. */
2862 if (tp->link_config.speed == SPEED_1000) {
2863 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2865 if (tp->link_config.duplex == DUPLEX_FULL)
2866 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2868 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2869 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2870 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2871 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2872 MII_TG3_CTRL_ENABLE_AS_MASTER);
2874 if (tp->link_config.speed == SPEED_100) {
2875 if (tp->link_config.duplex == DUPLEX_FULL)
2876 new_adv |= ADVERTISE_100FULL;
2878 new_adv |= ADVERTISE_100HALF;
2880 if (tp->link_config.duplex == DUPLEX_FULL)
2881 new_adv |= ADVERTISE_10FULL;
2883 new_adv |= ADVERTISE_10HALF;
2885 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2890 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2893 if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2894 tp->link_config.speed != SPEED_INVALID) {
2895 u32 bmcr, orig_bmcr;
2897 tp->link_config.active_speed = tp->link_config.speed;
2898 tp->link_config.active_duplex = tp->link_config.duplex;
2901 switch (tp->link_config.speed) {
2907 bmcr |= BMCR_SPEED100;
2911 bmcr |= TG3_BMCR_SPEED1000;
2915 if (tp->link_config.duplex == DUPLEX_FULL)
2916 bmcr |= BMCR_FULLDPLX;
2918 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2919 (bmcr != orig_bmcr)) {
2920 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2921 for (i = 0; i < 1500; i++) {
2925 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2926 tg3_readphy(tp, MII_BMSR, &tmp))
2928 if (!(tmp & BMSR_LSTATUS)) {
2933 tg3_writephy(tp, MII_BMCR, bmcr);
2937 tg3_writephy(tp, MII_BMCR,
2938 BMCR_ANENABLE | BMCR_ANRESTART);
2942 static int tg3_init_5401phy_dsp(struct tg3 *tp)
2946 /* Turn off tap power management. */
2947 /* Set Extended packet length bit */
2948 err = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2950 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
2951 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
2953 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
2954 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
2956 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2957 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
2959 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2960 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
2962 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2963 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
2970 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
2972 u32 adv_reg, all_mask = 0;
2974 if (mask & ADVERTISED_10baseT_Half)
2975 all_mask |= ADVERTISE_10HALF;
2976 if (mask & ADVERTISED_10baseT_Full)
2977 all_mask |= ADVERTISE_10FULL;
2978 if (mask & ADVERTISED_100baseT_Half)
2979 all_mask |= ADVERTISE_100HALF;
2980 if (mask & ADVERTISED_100baseT_Full)
2981 all_mask |= ADVERTISE_100FULL;
2983 if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
2986 if ((adv_reg & all_mask) != all_mask)
2988 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
2992 if (mask & ADVERTISED_1000baseT_Half)
2993 all_mask |= ADVERTISE_1000HALF;
2994 if (mask & ADVERTISED_1000baseT_Full)
2995 all_mask |= ADVERTISE_1000FULL;
2997 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
3000 if ((tg3_ctrl & all_mask) != all_mask)
3006 static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
3010 if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
3013 curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3014 reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
3016 if (tp->link_config.active_duplex == DUPLEX_FULL) {
3017 if (curadv != reqadv)
3020 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
3021 tg3_readphy(tp, MII_LPA, rmtadv);
3023 /* Reprogram the advertisement register, even if it
3024 * does not affect the current link. If the link
3025 * gets renegotiated in the future, we can save an
3026 * additional renegotiation cycle by advertising
3027 * it correctly in the first place.
3029 if (curadv != reqadv) {
3030 *lcladv &= ~(ADVERTISE_PAUSE_CAP |
3031 ADVERTISE_PAUSE_ASYM);
3032 tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
3039 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
3041 int current_link_up;
3043 u32 lcl_adv, rmt_adv;
3051 (MAC_STATUS_SYNC_CHANGED |
3052 MAC_STATUS_CFG_CHANGED |
3053 MAC_STATUS_MI_COMPLETION |
3054 MAC_STATUS_LNKSTATE_CHANGED));
3057 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
3059 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
3063 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
3065 /* Some third-party PHYs need to be reset on link going
3068 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3069 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
3070 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
3071 netif_carrier_ok(tp->dev)) {
3072 tg3_readphy(tp, MII_BMSR, &bmsr);
3073 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3074 !(bmsr & BMSR_LSTATUS))
3080 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
3081 tg3_readphy(tp, MII_BMSR, &bmsr);
3082 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
3083 !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
3086 if (!(bmsr & BMSR_LSTATUS)) {
3087 err = tg3_init_5401phy_dsp(tp);
3091 tg3_readphy(tp, MII_BMSR, &bmsr);
3092 for (i = 0; i < 1000; i++) {
3094 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3095 (bmsr & BMSR_LSTATUS)) {
3101 if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
3102 !(bmsr & BMSR_LSTATUS) &&
3103 tp->link_config.active_speed == SPEED_1000) {
3104 err = tg3_phy_reset(tp);
3106 err = tg3_init_5401phy_dsp(tp);
3111 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3112 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3113 /* 5701 {A0,B0} CRC bug workaround */
3114 tg3_writephy(tp, 0x15, 0x0a75);
3115 tg3_writephy(tp, 0x1c, 0x8c68);
3116 tg3_writephy(tp, 0x1c, 0x8d68);
3117 tg3_writephy(tp, 0x1c, 0x8c68);
3120 /* Clear pending interrupts... */
3121 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3122 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3124 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
3125 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
3126 else if (!(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
3127 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3129 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3130 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3131 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3132 tg3_writephy(tp, MII_TG3_EXT_CTRL,
3133 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3135 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3138 current_link_up = 0;
3139 current_speed = SPEED_INVALID;
3140 current_duplex = DUPLEX_INVALID;
3142 if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
3145 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3146 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3147 if (!(val & (1 << 10))) {
3149 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3155 for (i = 0; i < 100; i++) {
3156 tg3_readphy(tp, MII_BMSR, &bmsr);
3157 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3158 (bmsr & BMSR_LSTATUS))
3163 if (bmsr & BMSR_LSTATUS) {
3166 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3167 for (i = 0; i < 2000; i++) {
3169 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3174 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3179 for (i = 0; i < 200; i++) {
3180 tg3_readphy(tp, MII_BMCR, &bmcr);
3181 if (tg3_readphy(tp, MII_BMCR, &bmcr))
3183 if (bmcr && bmcr != 0x7fff)
3191 tp->link_config.active_speed = current_speed;
3192 tp->link_config.active_duplex = current_duplex;
3194 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3195 if ((bmcr & BMCR_ANENABLE) &&
3196 tg3_copper_is_advertising_all(tp,
3197 tp->link_config.advertising)) {
3198 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3200 current_link_up = 1;
3203 if (!(bmcr & BMCR_ANENABLE) &&
3204 tp->link_config.speed == current_speed &&
3205 tp->link_config.duplex == current_duplex &&
3206 tp->link_config.flowctrl ==
3207 tp->link_config.active_flowctrl) {
3208 current_link_up = 1;
3212 if (current_link_up == 1 &&
3213 tp->link_config.active_duplex == DUPLEX_FULL)
3214 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
3218 if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
3221 tg3_phy_copper_begin(tp);
3223 tg3_readphy(tp, MII_BMSR, &tmp);
3224 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
3225 (tmp & BMSR_LSTATUS))
3226 current_link_up = 1;
3229 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3230 if (current_link_up == 1) {
3231 if (tp->link_config.active_speed == SPEED_100 ||
3232 tp->link_config.active_speed == SPEED_10)
3233 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3235 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3236 } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)
3237 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3239 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3241 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3242 if (tp->link_config.active_duplex == DUPLEX_HALF)
3243 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3245 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
3246 if (current_link_up == 1 &&
3247 tg3_5700_link_polarity(tp, tp->link_config.active_speed))
3248 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
3250 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
3253 /* ??? Without this setting Netgear GA302T PHY does not
3254 * ??? send/receive packets...
3256 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
3257 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3258 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3259 tw32_f(MAC_MI_MODE, tp->mi_mode);
3263 tw32_f(MAC_MODE, tp->mac_mode);
3266 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3267 /* Polled via timer. */
3268 tw32_f(MAC_EVENT, 0);
3270 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3274 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3275 current_link_up == 1 &&
3276 tp->link_config.active_speed == SPEED_1000 &&
3277 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3278 (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3281 (MAC_STATUS_SYNC_CHANGED |
3282 MAC_STATUS_CFG_CHANGED));
3285 NIC_SRAM_FIRMWARE_MBOX,
3286 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3289 /* Prevent send BD corruption. */
3290 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3291 u16 oldlnkctl, newlnkctl;
3293 pci_read_config_word(tp->pdev,
3294 tp->pcie_cap + PCI_EXP_LNKCTL,
3296 if (tp->link_config.active_speed == SPEED_100 ||
3297 tp->link_config.active_speed == SPEED_10)
3298 newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3300 newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3301 if (newlnkctl != oldlnkctl)
3302 pci_write_config_word(tp->pdev,
3303 tp->pcie_cap + PCI_EXP_LNKCTL,
3307 if (current_link_up != netif_carrier_ok(tp->dev)) {
3308 if (current_link_up)
3309 netif_carrier_on(tp->dev);
3311 netif_carrier_off(tp->dev);
3312 tg3_link_report(tp);
3318 struct tg3_fiber_aneginfo {
3320 #define ANEG_STATE_UNKNOWN 0
3321 #define ANEG_STATE_AN_ENABLE 1
3322 #define ANEG_STATE_RESTART_INIT 2
3323 #define ANEG_STATE_RESTART 3
3324 #define ANEG_STATE_DISABLE_LINK_OK 4
3325 #define ANEG_STATE_ABILITY_DETECT_INIT 5
3326 #define ANEG_STATE_ABILITY_DETECT 6
3327 #define ANEG_STATE_ACK_DETECT_INIT 7
3328 #define ANEG_STATE_ACK_DETECT 8
3329 #define ANEG_STATE_COMPLETE_ACK_INIT 9
3330 #define ANEG_STATE_COMPLETE_ACK 10
3331 #define ANEG_STATE_IDLE_DETECT_INIT 11
3332 #define ANEG_STATE_IDLE_DETECT 12
3333 #define ANEG_STATE_LINK_OK 13
3334 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
3335 #define ANEG_STATE_NEXT_PAGE_WAIT 15
3338 #define MR_AN_ENABLE 0x00000001
3339 #define MR_RESTART_AN 0x00000002
3340 #define MR_AN_COMPLETE 0x00000004
3341 #define MR_PAGE_RX 0x00000008
3342 #define MR_NP_LOADED 0x00000010
3343 #define MR_TOGGLE_TX 0x00000020
3344 #define MR_LP_ADV_FULL_DUPLEX 0x00000040
3345 #define MR_LP_ADV_HALF_DUPLEX 0x00000080
3346 #define MR_LP_ADV_SYM_PAUSE 0x00000100
3347 #define MR_LP_ADV_ASYM_PAUSE 0x00000200
3348 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3349 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3350 #define MR_LP_ADV_NEXT_PAGE 0x00001000
3351 #define MR_TOGGLE_RX 0x00002000
3352 #define MR_NP_RX 0x00004000
3354 #define MR_LINK_OK 0x80000000
3356 unsigned long link_time, cur_time;
3358 u32 ability_match_cfg;
3359 int ability_match_count;
3361 char ability_match, idle_match, ack_match;
3363 u32 txconfig, rxconfig;
3364 #define ANEG_CFG_NP 0x00000080
3365 #define ANEG_CFG_ACK 0x00000040
3366 #define ANEG_CFG_RF2 0x00000020
3367 #define ANEG_CFG_RF1 0x00000010
3368 #define ANEG_CFG_PS2 0x00000001
3369 #define ANEG_CFG_PS1 0x00008000
3370 #define ANEG_CFG_HD 0x00004000
3371 #define ANEG_CFG_FD 0x00002000
3372 #define ANEG_CFG_INVAL 0x00001f06
3377 #define ANEG_TIMER_ENAB 2
3378 #define ANEG_FAILED -1
3380 #define ANEG_STATE_SETTLE_TIME 10000
3382 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3383 struct tg3_fiber_aneginfo *ap)
3386 unsigned long delta;
3390 if (ap->state == ANEG_STATE_UNKNOWN) {
3394 ap->ability_match_cfg = 0;
3395 ap->ability_match_count = 0;
3396 ap->ability_match = 0;
3402 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3403 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3405 if (rx_cfg_reg != ap->ability_match_cfg) {
3406 ap->ability_match_cfg = rx_cfg_reg;
3407 ap->ability_match = 0;
3408 ap->ability_match_count = 0;
3410 if (++ap->ability_match_count > 1) {
3411 ap->ability_match = 1;
3412 ap->ability_match_cfg = rx_cfg_reg;
3415 if (rx_cfg_reg & ANEG_CFG_ACK)
3423 ap->ability_match_cfg = 0;
3424 ap->ability_match_count = 0;
3425 ap->ability_match = 0;
3431 ap->rxconfig = rx_cfg_reg;
3435 case ANEG_STATE_UNKNOWN:
3436 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3437 ap->state = ANEG_STATE_AN_ENABLE;
3440 case ANEG_STATE_AN_ENABLE:
3441 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3442 if (ap->flags & MR_AN_ENABLE) {
3445 ap->ability_match_cfg = 0;
3446 ap->ability_match_count = 0;
3447 ap->ability_match = 0;
3451 ap->state = ANEG_STATE_RESTART_INIT;
3453 ap->state = ANEG_STATE_DISABLE_LINK_OK;
3457 case ANEG_STATE_RESTART_INIT:
3458 ap->link_time = ap->cur_time;
3459 ap->flags &= ~(MR_NP_LOADED);
3461 tw32(MAC_TX_AUTO_NEG, 0);
3462 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3463 tw32_f(MAC_MODE, tp->mac_mode);
3466 ret = ANEG_TIMER_ENAB;
3467 ap->state = ANEG_STATE_RESTART;
3470 case ANEG_STATE_RESTART:
3471 delta = ap->cur_time - ap->link_time;
3472 if (delta > ANEG_STATE_SETTLE_TIME) {
3473 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3475 ret = ANEG_TIMER_ENAB;
3479 case ANEG_STATE_DISABLE_LINK_OK:
3483 case ANEG_STATE_ABILITY_DETECT_INIT:
3484 ap->flags &= ~(MR_TOGGLE_TX);
3485 ap->txconfig = ANEG_CFG_FD;
3486 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3487 if (flowctrl & ADVERTISE_1000XPAUSE)
3488 ap->txconfig |= ANEG_CFG_PS1;
3489 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3490 ap->txconfig |= ANEG_CFG_PS2;
3491 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3492 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3493 tw32_f(MAC_MODE, tp->mac_mode);
3496 ap->state = ANEG_STATE_ABILITY_DETECT;
3499 case ANEG_STATE_ABILITY_DETECT:
3500 if (ap->ability_match != 0 && ap->rxconfig != 0) {
3501 ap->state = ANEG_STATE_ACK_DETECT_INIT;
3505 case ANEG_STATE_ACK_DETECT_INIT:
3506 ap->txconfig |= ANEG_CFG_ACK;
3507 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3508 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3509 tw32_f(MAC_MODE, tp->mac_mode);
3512 ap->state = ANEG_STATE_ACK_DETECT;
3515 case ANEG_STATE_ACK_DETECT:
3516 if (ap->ack_match != 0) {
3517 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3518 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3519 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3521 ap->state = ANEG_STATE_AN_ENABLE;
3523 } else if (ap->ability_match != 0 &&
3524 ap->rxconfig == 0) {
3525 ap->state = ANEG_STATE_AN_ENABLE;
3529 case ANEG_STATE_COMPLETE_ACK_INIT:
3530 if (ap->rxconfig & ANEG_CFG_INVAL) {
3534 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3535 MR_LP_ADV_HALF_DUPLEX |
3536 MR_LP_ADV_SYM_PAUSE |
3537 MR_LP_ADV_ASYM_PAUSE |
3538 MR_LP_ADV_REMOTE_FAULT1 |
3539 MR_LP_ADV_REMOTE_FAULT2 |
3540 MR_LP_ADV_NEXT_PAGE |
3543 if (ap->rxconfig & ANEG_CFG_FD)
3544 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3545 if (ap->rxconfig & ANEG_CFG_HD)
3546 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3547 if (ap->rxconfig & ANEG_CFG_PS1)
3548 ap->flags |= MR_LP_ADV_SYM_PAUSE;
3549 if (ap->rxconfig & ANEG_CFG_PS2)
3550 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3551 if (ap->rxconfig & ANEG_CFG_RF1)
3552 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3553 if (ap->rxconfig & ANEG_CFG_RF2)
3554 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3555 if (ap->rxconfig & ANEG_CFG_NP)
3556 ap->flags |= MR_LP_ADV_NEXT_PAGE;
3558 ap->link_time = ap->cur_time;
3560 ap->flags ^= (MR_TOGGLE_TX);
3561 if (ap->rxconfig & 0x0008)
3562 ap->flags |= MR_TOGGLE_RX;
3563 if (ap->rxconfig & ANEG_CFG_NP)
3564 ap->flags |= MR_NP_RX;
3565 ap->flags |= MR_PAGE_RX;
3567 ap->state = ANEG_STATE_COMPLETE_ACK;
3568 ret = ANEG_TIMER_ENAB;
3571 case ANEG_STATE_COMPLETE_ACK:
3572 if (ap->ability_match != 0 &&
3573 ap->rxconfig == 0) {
3574 ap->state = ANEG_STATE_AN_ENABLE;
3577 delta = ap->cur_time - ap->link_time;
3578 if (delta > ANEG_STATE_SETTLE_TIME) {
3579 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3580 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3582 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3583 !(ap->flags & MR_NP_RX)) {
3584 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3592 case ANEG_STATE_IDLE_DETECT_INIT:
3593 ap->link_time = ap->cur_time;
3594 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3595 tw32_f(MAC_MODE, tp->mac_mode);
3598 ap->state = ANEG_STATE_IDLE_DETECT;
3599 ret = ANEG_TIMER_ENAB;
3602 case ANEG_STATE_IDLE_DETECT:
3603 if (ap->ability_match != 0 &&
3604 ap->rxconfig == 0) {
3605 ap->state = ANEG_STATE_AN_ENABLE;
3608 delta = ap->cur_time - ap->link_time;
3609 if (delta > ANEG_STATE_SETTLE_TIME) {
3610 /* XXX another gem from the Broadcom driver :( */
3611 ap->state = ANEG_STATE_LINK_OK;
3615 case ANEG_STATE_LINK_OK:
3616 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3620 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3621 /* ??? unimplemented */
3624 case ANEG_STATE_NEXT_PAGE_WAIT:
3625 /* ??? unimplemented */
3636 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
3639 struct tg3_fiber_aneginfo aninfo;
3640 int status = ANEG_FAILED;
3644 tw32_f(MAC_TX_AUTO_NEG, 0);
3646 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3647 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3650 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3653 memset(&aninfo, 0, sizeof(aninfo));
3654 aninfo.flags |= MR_AN_ENABLE;
3655 aninfo.state = ANEG_STATE_UNKNOWN;
3656 aninfo.cur_time = 0;
3658 while (++tick < 195000) {
3659 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3660 if (status == ANEG_DONE || status == ANEG_FAILED)
3666 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3667 tw32_f(MAC_MODE, tp->mac_mode);
3670 *txflags = aninfo.txconfig;
3671 *rxflags = aninfo.flags;
3673 if (status == ANEG_DONE &&
3674 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3675 MR_LP_ADV_FULL_DUPLEX)))
3681 static void tg3_init_bcm8002(struct tg3 *tp)
3683 u32 mac_status = tr32(MAC_STATUS);
3686 /* Reset when initting first time or we have a link. */
3687 if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3688 !(mac_status & MAC_STATUS_PCS_SYNCED))
3691 /* Set PLL lock range. */
3692 tg3_writephy(tp, 0x16, 0x8007);
3695 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3697 /* Wait for reset to complete. */
3698 /* XXX schedule_timeout() ... */
3699 for (i = 0; i < 500; i++)
3702 /* Config mode; select PMA/Ch 1 regs. */
3703 tg3_writephy(tp, 0x10, 0x8411);
3705 /* Enable auto-lock and comdet, select txclk for tx. */
3706 tg3_writephy(tp, 0x11, 0x0a10);
3708 tg3_writephy(tp, 0x18, 0x00a0);
3709 tg3_writephy(tp, 0x16, 0x41ff);
3711 /* Assert and deassert POR. */
3712 tg3_writephy(tp, 0x13, 0x0400);
3714 tg3_writephy(tp, 0x13, 0x0000);
3716 tg3_writephy(tp, 0x11, 0x0a50);
3718 tg3_writephy(tp, 0x11, 0x0a10);
3720 /* Wait for signal to stabilize */
3721 /* XXX schedule_timeout() ... */
3722 for (i = 0; i < 15000; i++)
3725 /* Deselect the channel register so we can read the PHYID
3728 tg3_writephy(tp, 0x10, 0x8011);
3731 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3734 u32 sg_dig_ctrl, sg_dig_status;
3735 u32 serdes_cfg, expected_sg_dig_ctrl;
3736 int workaround, port_a;
3737 int current_link_up;
3740 expected_sg_dig_ctrl = 0;
3743 current_link_up = 0;
3745 if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3746 tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3748 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3751 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3752 /* preserve bits 20-23 for voltage regulator */
3753 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3756 sg_dig_ctrl = tr32(SG_DIG_CTRL);
3758 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
3759 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
3761 u32 val = serdes_cfg;
3767 tw32_f(MAC_SERDES_CFG, val);
3770 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3772 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3773 tg3_setup_flow_control(tp, 0, 0);
3774 current_link_up = 1;
3779 /* Want auto-negotiation. */
3780 expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
3782 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3783 if (flowctrl & ADVERTISE_1000XPAUSE)
3784 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3785 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3786 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
3788 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3789 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
3790 tp->serdes_counter &&
3791 ((mac_status & (MAC_STATUS_PCS_SYNCED |
3792 MAC_STATUS_RCVD_CFG)) ==
3793 MAC_STATUS_PCS_SYNCED)) {
3794 tp->serdes_counter--;
3795 current_link_up = 1;
3800 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
3801 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
3803 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3805 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3806 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3807 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3808 MAC_STATUS_SIGNAL_DET)) {
3809 sg_dig_status = tr32(SG_DIG_STATUS);
3810 mac_status = tr32(MAC_STATUS);
3812 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
3813 (mac_status & MAC_STATUS_PCS_SYNCED)) {
3814 u32 local_adv = 0, remote_adv = 0;
3816 if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3817 local_adv |= ADVERTISE_1000XPAUSE;
3818 if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3819 local_adv |= ADVERTISE_1000XPSE_ASYM;
3821 if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
3822 remote_adv |= LPA_1000XPAUSE;
3823 if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
3824 remote_adv |= LPA_1000XPAUSE_ASYM;
3826 tg3_setup_flow_control(tp, local_adv, remote_adv);
3827 current_link_up = 1;
3828 tp->serdes_counter = 0;
3829 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3830 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3831 if (tp->serdes_counter)
3832 tp->serdes_counter--;
3835 u32 val = serdes_cfg;
3842 tw32_f(MAC_SERDES_CFG, val);
3845 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3848 /* Link parallel detection - link is up */
3849 /* only if we have PCS_SYNC and not */
3850 /* receiving config code words */
3851 mac_status = tr32(MAC_STATUS);
3852 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3853 !(mac_status & MAC_STATUS_RCVD_CFG)) {
3854 tg3_setup_flow_control(tp, 0, 0);
3855 current_link_up = 1;
3857 TG3_FLG2_PARALLEL_DETECT;
3858 tp->serdes_counter =
3859 SERDES_PARALLEL_DET_TIMEOUT;
3861 goto restart_autoneg;
3865 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3866 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3870 return current_link_up;
3873 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3875 int current_link_up = 0;
3877 if (!(mac_status & MAC_STATUS_PCS_SYNCED))
3880 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3881 u32 txflags, rxflags;
3884 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3885 u32 local_adv = 0, remote_adv = 0;
3887 if (txflags & ANEG_CFG_PS1)
3888 local_adv |= ADVERTISE_1000XPAUSE;
3889 if (txflags & ANEG_CFG_PS2)
3890 local_adv |= ADVERTISE_1000XPSE_ASYM;
3892 if (rxflags & MR_LP_ADV_SYM_PAUSE)
3893 remote_adv |= LPA_1000XPAUSE;
3894 if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3895 remote_adv |= LPA_1000XPAUSE_ASYM;
3897 tg3_setup_flow_control(tp, local_adv, remote_adv);
3899 current_link_up = 1;
3901 for (i = 0; i < 30; i++) {
3904 (MAC_STATUS_SYNC_CHANGED |
3905 MAC_STATUS_CFG_CHANGED));
3907 if ((tr32(MAC_STATUS) &
3908 (MAC_STATUS_SYNC_CHANGED |
3909 MAC_STATUS_CFG_CHANGED)) == 0)
3913 mac_status = tr32(MAC_STATUS);
3914 if (current_link_up == 0 &&
3915 (mac_status & MAC_STATUS_PCS_SYNCED) &&
3916 !(mac_status & MAC_STATUS_RCVD_CFG))
3917 current_link_up = 1;
3919 tg3_setup_flow_control(tp, 0, 0);
3921 /* Forcing 1000FD link up. */
3922 current_link_up = 1;
3924 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3927 tw32_f(MAC_MODE, tp->mac_mode);
3932 return current_link_up;
3935 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3938 u16 orig_active_speed;
3939 u8 orig_active_duplex;
3941 int current_link_up;
3944 orig_pause_cfg = tp->link_config.active_flowctrl;
3945 orig_active_speed = tp->link_config.active_speed;
3946 orig_active_duplex = tp->link_config.active_duplex;
3948 if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3949 netif_carrier_ok(tp->dev) &&
3950 (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3951 mac_status = tr32(MAC_STATUS);
3952 mac_status &= (MAC_STATUS_PCS_SYNCED |
3953 MAC_STATUS_SIGNAL_DET |
3954 MAC_STATUS_CFG_CHANGED |
3955 MAC_STATUS_RCVD_CFG);
3956 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3957 MAC_STATUS_SIGNAL_DET)) {
3958 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3959 MAC_STATUS_CFG_CHANGED));
3964 tw32_f(MAC_TX_AUTO_NEG, 0);
3966 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
3967 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
3968 tw32_f(MAC_MODE, tp->mac_mode);
3971 if (tp->phy_id == PHY_ID_BCM8002)
3972 tg3_init_bcm8002(tp);
3974 /* Enable link change event even when serdes polling. */
3975 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3978 current_link_up = 0;
3979 mac_status = tr32(MAC_STATUS);
3981 if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
3982 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
3984 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
3986 tp->napi[0].hw_status->status =
3987 (SD_STATUS_UPDATED |
3988 (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
3990 for (i = 0; i < 100; i++) {
3991 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3992 MAC_STATUS_CFG_CHANGED));
3994 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3995 MAC_STATUS_CFG_CHANGED |
3996 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
4000 mac_status = tr32(MAC_STATUS);
4001 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
4002 current_link_up = 0;
4003 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
4004 tp->serdes_counter == 0) {
4005 tw32_f(MAC_MODE, (tp->mac_mode |
4006 MAC_MODE_SEND_CONFIGS));
4008 tw32_f(MAC_MODE, tp->mac_mode);
4012 if (current_link_up == 1) {
4013 tp->link_config.active_speed = SPEED_1000;
4014 tp->link_config.active_duplex = DUPLEX_FULL;
4015 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4016 LED_CTRL_LNKLED_OVERRIDE |
4017 LED_CTRL_1000MBPS_ON));
4019 tp->link_config.active_speed = SPEED_INVALID;
4020 tp->link_config.active_duplex = DUPLEX_INVALID;
4021 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4022 LED_CTRL_LNKLED_OVERRIDE |
4023 LED_CTRL_TRAFFIC_OVERRIDE));
4026 if (current_link_up != netif_carrier_ok(tp->dev)) {
4027 if (current_link_up)
4028 netif_carrier_on(tp->dev);
4030 netif_carrier_off(tp->dev);
4031 tg3_link_report(tp);
4033 u32 now_pause_cfg = tp->link_config.active_flowctrl;
4034 if (orig_pause_cfg != now_pause_cfg ||
4035 orig_active_speed != tp->link_config.active_speed ||
4036 orig_active_duplex != tp->link_config.active_duplex)
4037 tg3_link_report(tp);
4043 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
4045 int current_link_up, err = 0;
4049 u32 local_adv, remote_adv;
4051 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4052 tw32_f(MAC_MODE, tp->mac_mode);
4058 (MAC_STATUS_SYNC_CHANGED |
4059 MAC_STATUS_CFG_CHANGED |
4060 MAC_STATUS_MI_COMPLETION |
4061 MAC_STATUS_LNKSTATE_CHANGED));
4067 current_link_up = 0;
4068 current_speed = SPEED_INVALID;
4069 current_duplex = DUPLEX_INVALID;
4071 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4072 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4073 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
4074 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4075 bmsr |= BMSR_LSTATUS;
4077 bmsr &= ~BMSR_LSTATUS;
4080 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
4082 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
4083 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4084 /* do nothing, just check for link up at the end */
4085 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4088 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4089 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4090 ADVERTISE_1000XPAUSE |
4091 ADVERTISE_1000XPSE_ASYM |
4094 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4096 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4097 new_adv |= ADVERTISE_1000XHALF;
4098 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4099 new_adv |= ADVERTISE_1000XFULL;
4101 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4102 tg3_writephy(tp, MII_ADVERTISE, new_adv);
4103 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4104 tg3_writephy(tp, MII_BMCR, bmcr);
4106 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4107 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
4108 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4115 bmcr &= ~BMCR_SPEED1000;
4116 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4118 if (tp->link_config.duplex == DUPLEX_FULL)
4119 new_bmcr |= BMCR_FULLDPLX;
4121 if (new_bmcr != bmcr) {
4122 /* BMCR_SPEED1000 is a reserved bit that needs
4123 * to be set on write.
4125 new_bmcr |= BMCR_SPEED1000;
4127 /* Force a linkdown */
4128 if (netif_carrier_ok(tp->dev)) {
4131 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4132 adv &= ~(ADVERTISE_1000XFULL |
4133 ADVERTISE_1000XHALF |
4135 tg3_writephy(tp, MII_ADVERTISE, adv);
4136 tg3_writephy(tp, MII_BMCR, bmcr |
4140 netif_carrier_off(tp->dev);
4142 tg3_writephy(tp, MII_BMCR, new_bmcr);
4144 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4145 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4146 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4148 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4149 bmsr |= BMSR_LSTATUS;
4151 bmsr &= ~BMSR_LSTATUS;
4153 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4157 if (bmsr & BMSR_LSTATUS) {
4158 current_speed = SPEED_1000;
4159 current_link_up = 1;
4160 if (bmcr & BMCR_FULLDPLX)
4161 current_duplex = DUPLEX_FULL;
4163 current_duplex = DUPLEX_HALF;
4168 if (bmcr & BMCR_ANENABLE) {
4171 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4172 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4173 common = local_adv & remote_adv;
4174 if (common & (ADVERTISE_1000XHALF |
4175 ADVERTISE_1000XFULL)) {
4176 if (common & ADVERTISE_1000XFULL)
4177 current_duplex = DUPLEX_FULL;
4179 current_duplex = DUPLEX_HALF;
4182 current_link_up = 0;
4186 if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4187 tg3_setup_flow_control(tp, local_adv, remote_adv);
4189 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4190 if (tp->link_config.active_duplex == DUPLEX_HALF)
4191 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4193 tw32_f(MAC_MODE, tp->mac_mode);
4196 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4198 tp->link_config.active_speed = current_speed;
4199 tp->link_config.active_duplex = current_duplex;
4201 if (current_link_up != netif_carrier_ok(tp->dev)) {
4202 if (current_link_up)
4203 netif_carrier_on(tp->dev);
4205 netif_carrier_off(tp->dev);
4206 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4208 tg3_link_report(tp);
4213 static void tg3_serdes_parallel_detect(struct tg3 *tp)
4215 if (tp->serdes_counter) {
4216 /* Give autoneg time to complete. */
4217 tp->serdes_counter--;
4220 if (!netif_carrier_ok(tp->dev) &&
4221 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4224 tg3_readphy(tp, MII_BMCR, &bmcr);
4225 if (bmcr & BMCR_ANENABLE) {
4228 /* Select shadow register 0x1f */
4229 tg3_writephy(tp, 0x1c, 0x7c00);
4230 tg3_readphy(tp, 0x1c, &phy1);
4232 /* Select expansion interrupt status register */
4233 tg3_writephy(tp, 0x17, 0x0f01);
4234 tg3_readphy(tp, 0x15, &phy2);
4235 tg3_readphy(tp, 0x15, &phy2);
4237 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4238 /* We have signal detect and not receiving
4239 * config code words, link is up by parallel
4243 bmcr &= ~BMCR_ANENABLE;
4244 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4245 tg3_writephy(tp, MII_BMCR, bmcr);
4246 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
4250 else if (netif_carrier_ok(tp->dev) &&
4251 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4252 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4255 /* Select expansion interrupt status register */
4256 tg3_writephy(tp, 0x17, 0x0f01);
4257 tg3_readphy(tp, 0x15, &phy2);
4261 /* Config code words received, turn on autoneg. */
4262 tg3_readphy(tp, MII_BMCR, &bmcr);
4263 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4265 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4271 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4275 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
4276 err = tg3_setup_fiber_phy(tp, force_reset);
4277 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
4278 err = tg3_setup_fiber_mii_phy(tp, force_reset);
4280 err = tg3_setup_copper_phy(tp, force_reset);
4283 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
4286 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4287 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4289 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4294 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4295 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4296 tw32(GRC_MISC_CFG, val);
4299 if (tp->link_config.active_speed == SPEED_1000 &&
4300 tp->link_config.active_duplex == DUPLEX_HALF)
4301 tw32(MAC_TX_LENGTHS,
4302 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4303 (6 << TX_LENGTHS_IPG_SHIFT) |
4304 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
4306 tw32(MAC_TX_LENGTHS,
4307 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4308 (6 << TX_LENGTHS_IPG_SHIFT) |
4309 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
4311 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4312 if (netif_carrier_ok(tp->dev)) {
4313 tw32(HOSTCC_STAT_COAL_TICKS,
4314 tp->coal.stats_block_coalesce_usecs);
4316 tw32(HOSTCC_STAT_COAL_TICKS, 0);
4320 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4321 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
4322 if (!netif_carrier_ok(tp->dev))
4323 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4326 val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4327 tw32(PCIE_PWR_MGMT_THRESH, val);
4333 /* This is called whenever we suspect that the system chipset is re-
4334 * ordering the sequence of MMIO to the tx send mailbox. The symptom
4335 * is bogus tx completions. We try to recover by setting the
4336 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4339 static void tg3_tx_recover(struct tg3 *tp)
4341 BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4342 tp->write32_tx_mbox == tg3_write_indirect_mbox);
4344 printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
4345 "mapped I/O cycles to the network device, attempting to "
4346 "recover. Please report the problem to the driver maintainer "
4347 "and include system chipset information.\n", tp->dev->name);
4349 spin_lock(&tp->lock);
4350 tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
4351 spin_unlock(&tp->lock);
4354 static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
4357 return tnapi->tx_pending -
4358 ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
4361 /* Tigon3 never reports partial packet sends. So we do not
4362 * need special logic to handle SKBs that have not had all
4363 * of their frags sent yet, like SunGEM does.
4365 static void tg3_tx(struct tg3_napi *tnapi)
4367 struct tg3 *tp = tnapi->tp;
4368 u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
4369 u32 sw_idx = tnapi->tx_cons;
4370 struct netdev_queue *txq;
4371 int index = tnapi - tp->napi;
4373 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
4376 txq = netdev_get_tx_queue(tp->dev, index);
4378 while (sw_idx != hw_idx) {
4379 struct ring_info *ri = &tnapi->tx_buffers[sw_idx];
4380 struct sk_buff *skb = ri->skb;
4383 if (unlikely(skb == NULL)) {
4388 pci_unmap_single(tp->pdev,
4389 pci_unmap_addr(ri, mapping),
4395 sw_idx = NEXT_TX(sw_idx);
4397 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
4398 ri = &tnapi->tx_buffers[sw_idx];
4399 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4402 pci_unmap_page(tp->pdev,
4403 pci_unmap_addr(ri, mapping),
4404 skb_shinfo(skb)->frags[i].size,
4406 sw_idx = NEXT_TX(sw_idx);
4411 if (unlikely(tx_bug)) {
4417 tnapi->tx_cons = sw_idx;
4419 /* Need to make the tx_cons update visible to tg3_start_xmit()
4420 * before checking for netif_queue_stopped(). Without the
4421 * memory barrier, there is a small possibility that tg3_start_xmit()
4422 * will miss it and cause the queue to be stopped forever.
4426 if (unlikely(netif_tx_queue_stopped(txq) &&
4427 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
4428 __netif_tx_lock(txq, smp_processor_id());
4429 if (netif_tx_queue_stopped(txq) &&
4430 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
4431 netif_tx_wake_queue(txq);
4432 __netif_tx_unlock(txq);
4436 static void tg3_rx_skb_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
4441 pci_unmap_single(tp->pdev, pci_unmap_addr(ri, mapping),
4442 map_sz, PCI_DMA_FROMDEVICE);
4443 dev_kfree_skb_any(ri->skb);
4447 /* Returns size of skb allocated or < 0 on error.
4449 * We only need to fill in the address because the other members
4450 * of the RX descriptor are invariant, see tg3_init_rings.
4452 * Note the purposeful assymetry of cpu vs. chip accesses. For
4453 * posting buffers we only dirty the first cache line of the RX
4454 * descriptor (containing the address). Whereas for the RX status
4455 * buffers the cpu only reads the last cacheline of the RX descriptor
4456 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4458 static int tg3_alloc_rx_skb(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
4459 u32 opaque_key, u32 dest_idx_unmasked)
4461 struct tg3_rx_buffer_desc *desc;
4462 struct ring_info *map, *src_map;
4463 struct sk_buff *skb;
4465 int skb_size, dest_idx;
4468 switch (opaque_key) {
4469 case RXD_OPAQUE_RING_STD:
4470 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4471 desc = &tpr->rx_std[dest_idx];
4472 map = &tpr->rx_std_buffers[dest_idx];
4473 skb_size = tp->rx_pkt_map_sz;
4476 case RXD_OPAQUE_RING_JUMBO:
4477 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4478 desc = &tpr->rx_jmb[dest_idx].std;
4479 map = &tpr->rx_jmb_buffers[dest_idx];
4480 skb_size = TG3_RX_JMB_MAP_SZ;
4487 /* Do not overwrite any of the map or rp information
4488 * until we are sure we can commit to a new buffer.
4490 * Callers depend upon this behavior and assume that
4491 * we leave everything unchanged if we fail.
4493 skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset);
4497 skb_reserve(skb, tp->rx_offset);
4499 mapping = pci_map_single(tp->pdev, skb->data, skb_size,
4500 PCI_DMA_FROMDEVICE);
4501 if (pci_dma_mapping_error(tp->pdev, mapping)) {
4507 pci_unmap_addr_set(map, mapping, mapping);
4509 desc->addr_hi = ((u64)mapping >> 32);
4510 desc->addr_lo = ((u64)mapping & 0xffffffff);
4515 /* We only need to move over in the address because the other
4516 * members of the RX descriptor are invariant. See notes above
4517 * tg3_alloc_rx_skb for full details.
4519 static void tg3_recycle_rx(struct tg3_napi *tnapi,
4520 struct tg3_rx_prodring_set *dpr,
4521 u32 opaque_key, int src_idx,
4522 u32 dest_idx_unmasked)
4524 struct tg3 *tp = tnapi->tp;
4525 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4526 struct ring_info *src_map, *dest_map;
4528 struct tg3_rx_prodring_set *spr = &tp->prodring[0];
4530 switch (opaque_key) {
4531 case RXD_OPAQUE_RING_STD:
4532 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4533 dest_desc = &dpr->rx_std[dest_idx];
4534 dest_map = &dpr->rx_std_buffers[dest_idx];
4535 src_desc = &spr->rx_std[src_idx];
4536 src_map = &spr->rx_std_buffers[src_idx];
4539 case RXD_OPAQUE_RING_JUMBO:
4540 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4541 dest_desc = &dpr->rx_jmb[dest_idx].std;
4542 dest_map = &dpr->rx_jmb_buffers[dest_idx];
4543 src_desc = &spr->rx_jmb[src_idx].std;
4544 src_map = &spr->rx_jmb_buffers[src_idx];
4551 dest_map->skb = src_map->skb;
4552 pci_unmap_addr_set(dest_map, mapping,
4553 pci_unmap_addr(src_map, mapping));
4554 dest_desc->addr_hi = src_desc->addr_hi;
4555 dest_desc->addr_lo = src_desc->addr_lo;
4557 /* Ensure that the update to the skb happens after the physical
4558 * addresses have been transferred to the new BD location.
4562 src_map->skb = NULL;
4565 /* The RX ring scheme is composed of multiple rings which post fresh
4566 * buffers to the chip, and one special ring the chip uses to report
4567 * status back to the host.
4569 * The special ring reports the status of received packets to the
4570 * host. The chip does not write into the original descriptor the
4571 * RX buffer was obtained from. The chip simply takes the original
4572 * descriptor as provided by the host, updates the status and length
4573 * field, then writes this into the next status ring entry.
4575 * Each ring the host uses to post buffers to the chip is described
4576 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
4577 * it is first placed into the on-chip ram. When the packet's length
4578 * is known, it walks down the TG3_BDINFO entries to select the ring.
4579 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4580 * which is within the range of the new packet's length is chosen.
4582 * The "separate ring for rx status" scheme may sound queer, but it makes
4583 * sense from a cache coherency perspective. If only the host writes
4584 * to the buffer post rings, and only the chip writes to the rx status
4585 * rings, then cache lines never move beyond shared-modified state.
4586 * If both the host and chip were to write into the same ring, cache line
4587 * eviction could occur since both entities want it in an exclusive state.
4589 static int tg3_rx(struct tg3_napi *tnapi, int budget)
4591 struct tg3 *tp = tnapi->tp;
4592 u32 work_mask, rx_std_posted = 0;
4593 u32 std_prod_idx, jmb_prod_idx;
4594 u32 sw_idx = tnapi->rx_rcb_ptr;
4597 struct tg3_rx_prodring_set *tpr = tnapi->prodring;
4599 hw_idx = *(tnapi->rx_rcb_prod_idx);
4601 * We need to order the read of hw_idx and the read of
4602 * the opaque cookie.
4607 std_prod_idx = tpr->rx_std_prod_idx;
4608 jmb_prod_idx = tpr->rx_jmb_prod_idx;
4609 while (sw_idx != hw_idx && budget > 0) {
4610 struct ring_info *ri;
4611 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
4613 struct sk_buff *skb;
4614 dma_addr_t dma_addr;
4615 u32 opaque_key, desc_idx, *post_ptr;
4617 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4618 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4619 if (opaque_key == RXD_OPAQUE_RING_STD) {
4620 ri = &tp->prodring[0].rx_std_buffers[desc_idx];
4621 dma_addr = pci_unmap_addr(ri, mapping);
4623 post_ptr = &std_prod_idx;
4625 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
4626 ri = &tp->prodring[0].rx_jmb_buffers[desc_idx];
4627 dma_addr = pci_unmap_addr(ri, mapping);
4629 post_ptr = &jmb_prod_idx;
4631 goto next_pkt_nopost;
4633 work_mask |= opaque_key;
4635 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4636 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4638 tg3_recycle_rx(tnapi, tpr, opaque_key,
4639 desc_idx, *post_ptr);
4641 /* Other statistics kept track of by card. */
4642 tp->net_stats.rx_dropped++;
4646 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4649 if (len > RX_COPY_THRESHOLD &&
4650 tp->rx_offset == NET_IP_ALIGN) {
4651 /* rx_offset will likely not equal NET_IP_ALIGN
4652 * if this is a 5701 card running in PCI-X mode
4653 * [see tg3_get_invariants()]
4657 skb_size = tg3_alloc_rx_skb(tp, tpr, opaque_key,
4662 pci_unmap_single(tp->pdev, dma_addr, skb_size,
4663 PCI_DMA_FROMDEVICE);
4665 /* Ensure that the update to the skb happens
4666 * after the usage of the old DMA mapping.
4674 struct sk_buff *copy_skb;
4676 tg3_recycle_rx(tnapi, tpr, opaque_key,
4677 desc_idx, *post_ptr);
4679 copy_skb = netdev_alloc_skb(tp->dev,
4680 len + TG3_RAW_IP_ALIGN);
4681 if (copy_skb == NULL)
4682 goto drop_it_no_recycle;
4684 skb_reserve(copy_skb, TG3_RAW_IP_ALIGN);
4685 skb_put(copy_skb, len);
4686 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4687 skb_copy_from_linear_data(skb, copy_skb->data, len);
4688 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4690 /* We'll reuse the original ring buffer. */
4694 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4695 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4696 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4697 >> RXD_TCPCSUM_SHIFT) == 0xffff))
4698 skb->ip_summed = CHECKSUM_UNNECESSARY;
4700 skb->ip_summed = CHECKSUM_NONE;
4702 skb->protocol = eth_type_trans(skb, tp->dev);
4704 if (len > (tp->dev->mtu + ETH_HLEN) &&
4705 skb->protocol != htons(ETH_P_8021Q)) {
4710 #if TG3_VLAN_TAG_USED
4711 if (tp->vlgrp != NULL &&
4712 desc->type_flags & RXD_FLAG_VLAN) {
4713 vlan_gro_receive(&tnapi->napi, tp->vlgrp,
4714 desc->err_vlan & RXD_VLAN_MASK, skb);
4717 napi_gro_receive(&tnapi->napi, skb);
4725 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4726 tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4727 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4728 tpr->rx_std_prod_idx);
4729 work_mask &= ~RXD_OPAQUE_RING_STD;
4734 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
4736 /* Refresh hw_idx to see if there is new work */
4737 if (sw_idx == hw_idx) {
4738 hw_idx = *(tnapi->rx_rcb_prod_idx);
4743 /* ACK the status ring. */
4744 tnapi->rx_rcb_ptr = sw_idx;
4745 tw32_rx_mbox(tnapi->consmbox, sw_idx);
4747 /* Refill RX ring(s). */
4748 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) {
4749 if (work_mask & RXD_OPAQUE_RING_STD) {
4750 tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4751 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4752 tpr->rx_std_prod_idx);
4754 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4755 tpr->rx_jmb_prod_idx = jmb_prod_idx %
4756 TG3_RX_JUMBO_RING_SIZE;
4757 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
4758 tpr->rx_jmb_prod_idx);
4761 } else if (work_mask) {
4762 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
4763 * updated before the producer indices can be updated.
4767 tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4768 tpr->rx_jmb_prod_idx = jmb_prod_idx % TG3_RX_JUMBO_RING_SIZE;
4770 if (tnapi != &tp->napi[1])
4771 napi_schedule(&tp->napi[1].napi);
4777 static void tg3_poll_link(struct tg3 *tp)
4779 /* handle link change and other phy events */
4780 if (!(tp->tg3_flags &
4781 (TG3_FLAG_USE_LINKCHG_REG |
4782 TG3_FLAG_POLL_SERDES))) {
4783 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
4785 if (sblk->status & SD_STATUS_LINK_CHG) {
4786 sblk->status = SD_STATUS_UPDATED |
4787 (sblk->status & ~SD_STATUS_LINK_CHG);
4788 spin_lock(&tp->lock);
4789 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4791 (MAC_STATUS_SYNC_CHANGED |
4792 MAC_STATUS_CFG_CHANGED |
4793 MAC_STATUS_MI_COMPLETION |
4794 MAC_STATUS_LNKSTATE_CHANGED));
4797 tg3_setup_phy(tp, 0);
4798 spin_unlock(&tp->lock);
4803 static int tg3_rx_prodring_xfer(struct tg3 *tp,
4804 struct tg3_rx_prodring_set *dpr,
4805 struct tg3_rx_prodring_set *spr)
4807 u32 si, di, cpycnt, src_prod_idx;
4811 src_prod_idx = spr->rx_std_prod_idx;
4813 /* Make sure updates to the rx_std_buffers[] entries and the
4814 * standard producer index are seen in the correct order.
4818 if (spr->rx_std_cons_idx == src_prod_idx)
4821 if (spr->rx_std_cons_idx < src_prod_idx)
4822 cpycnt = src_prod_idx - spr->rx_std_cons_idx;
4824 cpycnt = TG3_RX_RING_SIZE - spr->rx_std_cons_idx;
4826 cpycnt = min(cpycnt, TG3_RX_RING_SIZE - dpr->rx_std_prod_idx);
4828 si = spr->rx_std_cons_idx;
4829 di = dpr->rx_std_prod_idx;
4831 for (i = di; i < di + cpycnt; i++) {
4832 if (dpr->rx_std_buffers[i].skb) {
4842 /* Ensure that updates to the rx_std_buffers ring and the
4843 * shadowed hardware producer ring from tg3_recycle_skb() are
4844 * ordered correctly WRT the skb check above.
4848 memcpy(&dpr->rx_std_buffers[di],
4849 &spr->rx_std_buffers[si],
4850 cpycnt * sizeof(struct ring_info));
4852 for (i = 0; i < cpycnt; i++, di++, si++) {
4853 struct tg3_rx_buffer_desc *sbd, *dbd;
4854 sbd = &spr->rx_std[si];
4855 dbd = &dpr->rx_std[di];
4856 dbd->addr_hi = sbd->addr_hi;
4857 dbd->addr_lo = sbd->addr_lo;
4860 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) %
4862 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) %
4867 src_prod_idx = spr->rx_jmb_prod_idx;
4869 /* Make sure updates to the rx_jmb_buffers[] entries and
4870 * the jumbo producer index are seen in the correct order.
4874 if (spr->rx_jmb_cons_idx == src_prod_idx)
4877 if (spr->rx_jmb_cons_idx < src_prod_idx)
4878 cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
4880 cpycnt = TG3_RX_JUMBO_RING_SIZE - spr->rx_jmb_cons_idx;
4882 cpycnt = min(cpycnt,
4883 TG3_RX_JUMBO_RING_SIZE - dpr->rx_jmb_prod_idx);
4885 si = spr->rx_jmb_cons_idx;
4886 di = dpr->rx_jmb_prod_idx;
4888 for (i = di; i < di + cpycnt; i++) {
4889 if (dpr->rx_jmb_buffers[i].skb) {
4899 /* Ensure that updates to the rx_jmb_buffers ring and the
4900 * shadowed hardware producer ring from tg3_recycle_skb() are
4901 * ordered correctly WRT the skb check above.
4905 memcpy(&dpr->rx_jmb_buffers[di],
4906 &spr->rx_jmb_buffers[si],
4907 cpycnt * sizeof(struct ring_info));
4909 for (i = 0; i < cpycnt; i++, di++, si++) {
4910 struct tg3_rx_buffer_desc *sbd, *dbd;
4911 sbd = &spr->rx_jmb[si].std;
4912 dbd = &dpr->rx_jmb[di].std;
4913 dbd->addr_hi = sbd->addr_hi;
4914 dbd->addr_lo = sbd->addr_lo;
4917 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) %
4918 TG3_RX_JUMBO_RING_SIZE;
4919 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) %
4920 TG3_RX_JUMBO_RING_SIZE;
4926 static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
4928 struct tg3 *tp = tnapi->tp;
4930 /* run TX completion thread */
4931 if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
4933 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4937 /* run RX thread, within the bounds set by NAPI.
4938 * All RX "locking" is done by ensuring outside
4939 * code synchronizes with tg3->napi.poll()
4941 if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
4942 work_done += tg3_rx(tnapi, budget - work_done);
4944 if ((tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) && tnapi == &tp->napi[1]) {
4945 struct tg3_rx_prodring_set *dpr = &tp->prodring[0];
4947 u32 std_prod_idx = dpr->rx_std_prod_idx;
4948 u32 jmb_prod_idx = dpr->rx_jmb_prod_idx;
4950 for (i = 1; i < tp->irq_cnt; i++)
4951 err |= tg3_rx_prodring_xfer(tp, dpr,
4952 tp->napi[i].prodring);
4956 if (std_prod_idx != dpr->rx_std_prod_idx)
4957 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4958 dpr->rx_std_prod_idx);
4960 if (jmb_prod_idx != dpr->rx_jmb_prod_idx)
4961 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
4962 dpr->rx_jmb_prod_idx);
4967 tw32_f(HOSTCC_MODE, tp->coal_now);
4973 static int tg3_poll_msix(struct napi_struct *napi, int budget)
4975 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
4976 struct tg3 *tp = tnapi->tp;
4978 struct tg3_hw_status *sblk = tnapi->hw_status;
4981 work_done = tg3_poll_work(tnapi, work_done, budget);
4983 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4986 if (unlikely(work_done >= budget))
4989 /* tp->last_tag is used in tg3_restart_ints() below
4990 * to tell the hw how much work has been processed,
4991 * so we must read it before checking for more work.
4993 tnapi->last_tag = sblk->status_tag;
4994 tnapi->last_irq_tag = tnapi->last_tag;
4997 /* check for RX/TX work to do */
4998 if (sblk->idx[0].tx_consumer == tnapi->tx_cons &&
4999 *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr) {
5000 napi_complete(napi);
5001 /* Reenable interrupts. */
5002 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
5011 /* work_done is guaranteed to be less than budget. */
5012 napi_complete(napi);
5013 schedule_work(&tp->reset_task);
5017 static int tg3_poll(struct napi_struct *napi, int budget)
5019 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
5020 struct tg3 *tp = tnapi->tp;
5022 struct tg3_hw_status *sblk = tnapi->hw_status;
5027 work_done = tg3_poll_work(tnapi, work_done, budget);
5029 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5032 if (unlikely(work_done >= budget))
5035 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
5036 /* tp->last_tag is used in tg3_int_reenable() below
5037 * to tell the hw how much work has been processed,
5038 * so we must read it before checking for more work.
5040 tnapi->last_tag = sblk->status_tag;
5041 tnapi->last_irq_tag = tnapi->last_tag;
5044 sblk->status &= ~SD_STATUS_UPDATED;
5046 if (likely(!tg3_has_work(tnapi))) {
5047 napi_complete(napi);
5048 tg3_int_reenable(tnapi);
5056 /* work_done is guaranteed to be less than budget. */
5057 napi_complete(napi);
5058 schedule_work(&tp->reset_task);
5062 static void tg3_irq_quiesce(struct tg3 *tp)
5066 BUG_ON(tp->irq_sync);
5071 for (i = 0; i < tp->irq_cnt; i++)
5072 synchronize_irq(tp->napi[i].irq_vec);
5075 static inline int tg3_irq_sync(struct tg3 *tp)
5077 return tp->irq_sync;
5080 /* Fully shutdown all tg3 driver activity elsewhere in the system.
5081 * If irq_sync is non-zero, then the IRQ handler must be synchronized
5082 * with as well. Most of the time, this is not necessary except when
5083 * shutting down the device.
5085 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
5087 spin_lock_bh(&tp->lock);
5089 tg3_irq_quiesce(tp);
5092 static inline void tg3_full_unlock(struct tg3 *tp)
5094 spin_unlock_bh(&tp->lock);
5097 /* One-shot MSI handler - Chip automatically disables interrupt
5098 * after sending MSI so driver doesn't have to do it.
5100 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
5102 struct tg3_napi *tnapi = dev_id;
5103 struct tg3 *tp = tnapi->tp;
5105 prefetch(tnapi->hw_status);
5107 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5109 if (likely(!tg3_irq_sync(tp)))
5110 napi_schedule(&tnapi->napi);
5115 /* MSI ISR - No need to check for interrupt sharing and no need to
5116 * flush status block and interrupt mailbox. PCI ordering rules
5117 * guarantee that MSI will arrive after the status block.
5119 static irqreturn_t tg3_msi(int irq, void *dev_id)
5121 struct tg3_napi *tnapi = dev_id;
5122 struct tg3 *tp = tnapi->tp;
5124 prefetch(tnapi->hw_status);
5126 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5128 * Writing any value to intr-mbox-0 clears PCI INTA# and
5129 * chip-internal interrupt pending events.
5130 * Writing non-zero to intr-mbox-0 additional tells the
5131 * NIC to stop sending us irqs, engaging "in-intr-handler"
5134 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5135 if (likely(!tg3_irq_sync(tp)))
5136 napi_schedule(&tnapi->napi);
5138 return IRQ_RETVAL(1);
5141 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
5143 struct tg3_napi *tnapi = dev_id;
5144 struct tg3 *tp = tnapi->tp;
5145 struct tg3_hw_status *sblk = tnapi->hw_status;
5146 unsigned int handled = 1;
5148 /* In INTx mode, it is possible for the interrupt to arrive at
5149 * the CPU before the status block posted prior to the interrupt.
5150 * Reading the PCI State register will confirm whether the
5151 * interrupt is ours and will flush the status block.
5153 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
5154 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5155 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5162 * Writing any value to intr-mbox-0 clears PCI INTA# and
5163 * chip-internal interrupt pending events.
5164 * Writing non-zero to intr-mbox-0 additional tells the
5165 * NIC to stop sending us irqs, engaging "in-intr-handler"
5168 * Flush the mailbox to de-assert the IRQ immediately to prevent
5169 * spurious interrupts. The flush impacts performance but
5170 * excessive spurious interrupts can be worse in some cases.
5172 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5173 if (tg3_irq_sync(tp))
5175 sblk->status &= ~SD_STATUS_UPDATED;
5176 if (likely(tg3_has_work(tnapi))) {
5177 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5178 napi_schedule(&tnapi->napi);
5180 /* No work, shared interrupt perhaps? re-enable
5181 * interrupts, and flush that PCI write
5183 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
5187 return IRQ_RETVAL(handled);
5190 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
5192 struct tg3_napi *tnapi = dev_id;
5193 struct tg3 *tp = tnapi->tp;
5194 struct tg3_hw_status *sblk = tnapi->hw_status;
5195 unsigned int handled = 1;
5197 /* In INTx mode, it is possible for the interrupt to arrive at
5198 * the CPU before the status block posted prior to the interrupt.
5199 * Reading the PCI State register will confirm whether the
5200 * interrupt is ours and will flush the status block.
5202 if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
5203 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5204 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5211 * writing any value to intr-mbox-0 clears PCI INTA# and
5212 * chip-internal interrupt pending events.
5213 * writing non-zero to intr-mbox-0 additional tells the
5214 * NIC to stop sending us irqs, engaging "in-intr-handler"
5217 * Flush the mailbox to de-assert the IRQ immediately to prevent
5218 * spurious interrupts. The flush impacts performance but
5219 * excessive spurious interrupts can be worse in some cases.
5221 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5224 * In a shared interrupt configuration, sometimes other devices'
5225 * interrupts will scream. We record the current status tag here
5226 * so that the above check can report that the screaming interrupts
5227 * are unhandled. Eventually they will be silenced.
5229 tnapi->last_irq_tag = sblk->status_tag;
5231 if (tg3_irq_sync(tp))
5234 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5236 napi_schedule(&tnapi->napi);
5239 return IRQ_RETVAL(handled);
5242 /* ISR for interrupt test */
5243 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
5245 struct tg3_napi *tnapi = dev_id;
5246 struct tg3 *tp = tnapi->tp;
5247 struct tg3_hw_status *sblk = tnapi->hw_status;
5249 if ((sblk->status & SD_STATUS_UPDATED) ||
5250 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5251 tg3_disable_ints(tp);
5252 return IRQ_RETVAL(1);
5254 return IRQ_RETVAL(0);
5257 static int tg3_init_hw(struct tg3 *, int);
5258 static int tg3_halt(struct tg3 *, int, int);
5260 /* Restart hardware after configuration changes, self-test, etc.
5261 * Invoked with tp->lock held.
5263 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
5264 __releases(tp->lock)
5265 __acquires(tp->lock)
5269 err = tg3_init_hw(tp, reset_phy);
5271 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
5272 "aborting.\n", tp->dev->name);
5273 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5274 tg3_full_unlock(tp);
5275 del_timer_sync(&tp->timer);
5277 tg3_napi_enable(tp);
5279 tg3_full_lock(tp, 0);
5284 #ifdef CONFIG_NET_POLL_CONTROLLER
5285 static void tg3_poll_controller(struct net_device *dev)
5288 struct tg3 *tp = netdev_priv(dev);
5290 for (i = 0; i < tp->irq_cnt; i++)
5291 tg3_interrupt(tp->napi[i].irq_vec, dev);
5295 static void tg3_reset_task(struct work_struct *work)
5297 struct tg3 *tp = container_of(work, struct tg3, reset_task);
5299 unsigned int restart_timer;
5301 tg3_full_lock(tp, 0);
5303 if (!netif_running(tp->dev)) {
5304 tg3_full_unlock(tp);
5308 tg3_full_unlock(tp);
5314 tg3_full_lock(tp, 1);
5316 restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
5317 tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
5319 if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
5320 tp->write32_tx_mbox = tg3_write32_tx_mbox;
5321 tp->write32_rx_mbox = tg3_write_flush_reg32;
5322 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
5323 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
5326 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
5327 err = tg3_init_hw(tp, 1);
5331 tg3_netif_start(tp);
5334 mod_timer(&tp->timer, jiffies + 1);
5337 tg3_full_unlock(tp);
5343 static void tg3_dump_short_state(struct tg3 *tp)
5345 printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
5346 tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
5347 printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
5348 tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
5351 static void tg3_tx_timeout(struct net_device *dev)
5353 struct tg3 *tp = netdev_priv(dev);
5355 if (netif_msg_tx_err(tp)) {
5356 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
5358 tg3_dump_short_state(tp);
5361 schedule_work(&tp->reset_task);
5364 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5365 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
5367 u32 base = (u32) mapping & 0xffffffff;
5369 return ((base > 0xffffdcc0) &&
5370 (base + len + 8 < base));
5373 /* Test for DMA addresses > 40-bit */
5374 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
5377 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
5378 if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
5379 return (((u64) mapping + len) > DMA_BIT_MASK(40));
5386 static void tg3_set_txd(struct tg3_napi *, int, dma_addr_t, int, u32, u32);
5388 /* Workaround 4GB and 40-bit hardware DMA bugs. */
5389 static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
5390 struct sk_buff *skb, u32 last_plus_one,
5391 u32 *start, u32 base_flags, u32 mss)
5393 struct tg3 *tp = tnapi->tp;
5394 struct sk_buff *new_skb;
5395 dma_addr_t new_addr = 0;
5399 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5400 new_skb = skb_copy(skb, GFP_ATOMIC);
5402 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5404 new_skb = skb_copy_expand(skb,
5405 skb_headroom(skb) + more_headroom,
5406 skb_tailroom(skb), GFP_ATOMIC);
5412 /* New SKB is guaranteed to be linear. */
5414 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
5416 /* Make sure the mapping succeeded */
5417 if (pci_dma_mapping_error(tp->pdev, new_addr)) {
5419 dev_kfree_skb(new_skb);
5422 /* Make sure new skb does not cross any 4G boundaries.
5423 * Drop the packet if it does.
5425 } else if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5426 tg3_4g_overflow_test(new_addr, new_skb->len)) {
5427 pci_unmap_single(tp->pdev, new_addr, new_skb->len,
5430 dev_kfree_skb(new_skb);
5433 tg3_set_txd(tnapi, entry, new_addr, new_skb->len,
5434 base_flags, 1 | (mss << 1));
5435 *start = NEXT_TX(entry);
5439 /* Now clean up the sw ring entries. */
5441 while (entry != last_plus_one) {
5445 len = skb_headlen(skb);
5447 len = skb_shinfo(skb)->frags[i-1].size;
5449 pci_unmap_single(tp->pdev,
5450 pci_unmap_addr(&tnapi->tx_buffers[entry],
5452 len, PCI_DMA_TODEVICE);
5454 tnapi->tx_buffers[entry].skb = new_skb;
5455 pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5458 tnapi->tx_buffers[entry].skb = NULL;
5460 entry = NEXT_TX(entry);
5469 static void tg3_set_txd(struct tg3_napi *tnapi, int entry,
5470 dma_addr_t mapping, int len, u32 flags,
5473 struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry];
5474 int is_end = (mss_and_is_end & 0x1);
5475 u32 mss = (mss_and_is_end >> 1);
5479 flags |= TXD_FLAG_END;
5480 if (flags & TXD_FLAG_VLAN) {
5481 vlan_tag = flags >> 16;
5484 vlan_tag |= (mss << TXD_MSS_SHIFT);
5486 txd->addr_hi = ((u64) mapping >> 32);
5487 txd->addr_lo = ((u64) mapping & 0xffffffff);
5488 txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5489 txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5492 /* hard_start_xmit for devices that don't have any bugs and
5493 * support TG3_FLG2_HW_TSO_2 and TG3_FLG2_HW_TSO_3 only.
5495 static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
5496 struct net_device *dev)
5498 struct tg3 *tp = netdev_priv(dev);
5499 u32 len, entry, base_flags, mss;
5501 struct tg3_napi *tnapi;
5502 struct netdev_queue *txq;
5503 unsigned int i, last;
5506 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5507 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5508 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
5511 /* We are running in BH disabled context with netif_tx_lock
5512 * and TX reclaim runs via tp->napi.poll inside of a software
5513 * interrupt. Furthermore, IRQ processing runs lockless so we have
5514 * no IRQ context deadlocks to worry about either. Rejoice!
5516 if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5517 if (!netif_tx_queue_stopped(txq)) {
5518 netif_tx_stop_queue(txq);
5520 /* This is a hard error, log it. */
5521 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5522 "queue awake!\n", dev->name);
5524 return NETDEV_TX_BUSY;
5527 entry = tnapi->tx_prod;
5530 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5531 int tcp_opt_len, ip_tcp_len;
5534 if (skb_header_cloned(skb) &&
5535 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5540 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
5541 hdrlen = skb_headlen(skb) - ETH_HLEN;
5543 struct iphdr *iph = ip_hdr(skb);
5545 tcp_opt_len = tcp_optlen(skb);
5546 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5549 iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
5550 hdrlen = ip_tcp_len + tcp_opt_len;
5553 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5554 mss |= (hdrlen & 0xc) << 12;
5556 base_flags |= 0x00000010;
5557 base_flags |= (hdrlen & 0x3e0) << 5;
5561 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5562 TXD_FLAG_CPU_POST_DMA);
5564 tcp_hdr(skb)->check = 0;
5567 else if (skb->ip_summed == CHECKSUM_PARTIAL)
5568 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5569 #if TG3_VLAN_TAG_USED
5570 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5571 base_flags |= (TXD_FLAG_VLAN |
5572 (vlan_tx_tag_get(skb) << 16));
5575 len = skb_headlen(skb);
5577 /* Queue skb data, a.k.a. the main skb fragment. */
5578 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5579 if (pci_dma_mapping_error(tp->pdev, mapping)) {
5584 tnapi->tx_buffers[entry].skb = skb;
5585 pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
5587 if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
5588 !mss && skb->len > ETH_DATA_LEN)
5589 base_flags |= TXD_FLAG_JMB_PKT;
5591 tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5592 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5594 entry = NEXT_TX(entry);
5596 /* Now loop through additional data fragments, and queue them. */
5597 if (skb_shinfo(skb)->nr_frags > 0) {
5598 last = skb_shinfo(skb)->nr_frags - 1;
5599 for (i = 0; i <= last; i++) {
5600 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5603 mapping = pci_map_page(tp->pdev,
5606 len, PCI_DMA_TODEVICE);
5607 if (pci_dma_mapping_error(tp->pdev, mapping))
5610 tnapi->tx_buffers[entry].skb = NULL;
5611 pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5614 tg3_set_txd(tnapi, entry, mapping, len,
5615 base_flags, (i == last) | (mss << 1));
5617 entry = NEXT_TX(entry);
5621 /* Packets are ready, update Tx producer idx local and on card. */
5622 tw32_tx_mbox(tnapi->prodmbox, entry);
5624 tnapi->tx_prod = entry;
5625 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5626 netif_tx_stop_queue(txq);
5627 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5628 netif_tx_wake_queue(txq);
5634 return NETDEV_TX_OK;
5638 entry = tnapi->tx_prod;
5639 tnapi->tx_buffers[entry].skb = NULL;
5640 pci_unmap_single(tp->pdev,
5641 pci_unmap_addr(&tnapi->tx_buffers[entry], mapping),
5644 for (i = 0; i <= last; i++) {
5645 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5646 entry = NEXT_TX(entry);
5648 pci_unmap_page(tp->pdev,
5649 pci_unmap_addr(&tnapi->tx_buffers[entry],
5651 frag->size, PCI_DMA_TODEVICE);
5655 return NETDEV_TX_OK;
5658 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *,
5659 struct net_device *);
5661 /* Use GSO to workaround a rare TSO bug that may be triggered when the
5662 * TSO header is greater than 80 bytes.
5664 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5666 struct sk_buff *segs, *nskb;
5667 u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
5669 /* Estimate the number of fragments in the worst case */
5670 if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
5671 netif_stop_queue(tp->dev);
5672 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
5673 return NETDEV_TX_BUSY;
5675 netif_wake_queue(tp->dev);
5678 segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
5680 goto tg3_tso_bug_end;
5686 tg3_start_xmit_dma_bug(nskb, tp->dev);
5692 return NETDEV_TX_OK;
5695 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5696 * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5698 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
5699 struct net_device *dev)
5701 struct tg3 *tp = netdev_priv(dev);
5702 u32 len, entry, base_flags, mss;
5703 int would_hit_hwbug;
5705 struct tg3_napi *tnapi;
5706 struct netdev_queue *txq;
5707 unsigned int i, last;
5710 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5711 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5712 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
5715 /* We are running in BH disabled context with netif_tx_lock
5716 * and TX reclaim runs via tp->napi.poll inside of a software
5717 * interrupt. Furthermore, IRQ processing runs lockless so we have
5718 * no IRQ context deadlocks to worry about either. Rejoice!
5720 if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5721 if (!netif_tx_queue_stopped(txq)) {
5722 netif_tx_stop_queue(txq);
5724 /* This is a hard error, log it. */
5725 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5726 "queue awake!\n", dev->name);
5728 return NETDEV_TX_BUSY;
5731 entry = tnapi->tx_prod;
5733 if (skb->ip_summed == CHECKSUM_PARTIAL)
5734 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5736 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5738 u32 tcp_opt_len, ip_tcp_len, hdr_len;
5740 if (skb_header_cloned(skb) &&
5741 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5746 tcp_opt_len = tcp_optlen(skb);
5747 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5749 hdr_len = ip_tcp_len + tcp_opt_len;
5750 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
5751 (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
5752 return (tg3_tso_bug(tp, skb));
5754 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5755 TXD_FLAG_CPU_POST_DMA);
5759 iph->tot_len = htons(mss + hdr_len);
5760 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
5761 tcp_hdr(skb)->check = 0;
5762 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
5764 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5769 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5770 mss |= (hdr_len & 0xc) << 12;
5772 base_flags |= 0x00000010;
5773 base_flags |= (hdr_len & 0x3e0) << 5;
5774 } else if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)
5775 mss |= hdr_len << 9;
5776 else if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_1) ||
5777 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
5778 if (tcp_opt_len || iph->ihl > 5) {
5781 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5782 mss |= (tsflags << 11);
5785 if (tcp_opt_len || iph->ihl > 5) {
5788 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5789 base_flags |= tsflags << 12;
5793 #if TG3_VLAN_TAG_USED
5794 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5795 base_flags |= (TXD_FLAG_VLAN |
5796 (vlan_tx_tag_get(skb) << 16));
5799 if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
5800 !mss && skb->len > ETH_DATA_LEN)
5801 base_flags |= TXD_FLAG_JMB_PKT;
5803 len = skb_headlen(skb);
5805 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5806 if (pci_dma_mapping_error(tp->pdev, mapping)) {
5811 tnapi->tx_buffers[entry].skb = skb;
5812 pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
5814 would_hit_hwbug = 0;
5816 if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) && len <= 8)
5817 would_hit_hwbug = 1;
5819 if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5820 tg3_4g_overflow_test(mapping, len))
5821 would_hit_hwbug = 1;
5823 if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5824 tg3_40bit_overflow_test(tp, mapping, len))
5825 would_hit_hwbug = 1;
5827 if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
5828 would_hit_hwbug = 1;
5830 tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5831 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5833 entry = NEXT_TX(entry);
5835 /* Now loop through additional data fragments, and queue them. */
5836 if (skb_shinfo(skb)->nr_frags > 0) {
5837 last = skb_shinfo(skb)->nr_frags - 1;
5838 for (i = 0; i <= last; i++) {
5839 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5842 mapping = pci_map_page(tp->pdev,
5845 len, PCI_DMA_TODEVICE);
5847 tnapi->tx_buffers[entry].skb = NULL;
5848 pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5850 if (pci_dma_mapping_error(tp->pdev, mapping))
5853 if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) &&
5855 would_hit_hwbug = 1;
5857 if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5858 tg3_4g_overflow_test(mapping, len))
5859 would_hit_hwbug = 1;
5861 if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5862 tg3_40bit_overflow_test(tp, mapping, len))
5863 would_hit_hwbug = 1;
5865 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5866 tg3_set_txd(tnapi, entry, mapping, len,
5867 base_flags, (i == last)|(mss << 1));
5869 tg3_set_txd(tnapi, entry, mapping, len,
5870 base_flags, (i == last));
5872 entry = NEXT_TX(entry);
5876 if (would_hit_hwbug) {
5877 u32 last_plus_one = entry;
5880 start = entry - 1 - skb_shinfo(skb)->nr_frags;
5881 start &= (TG3_TX_RING_SIZE - 1);
5883 /* If the workaround fails due to memory/mapping
5884 * failure, silently drop this packet.
5886 if (tigon3_dma_hwbug_workaround(tnapi, skb, last_plus_one,
5887 &start, base_flags, mss))
5893 /* Packets are ready, update Tx producer idx local and on card. */
5894 tw32_tx_mbox(tnapi->prodmbox, entry);
5896 tnapi->tx_prod = entry;
5897 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5898 netif_tx_stop_queue(txq);
5899 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5900 netif_tx_wake_queue(txq);
5906 return NETDEV_TX_OK;
5910 entry = tnapi->tx_prod;
5911 tnapi->tx_buffers[entry].skb = NULL;
5912 pci_unmap_single(tp->pdev,
5913 pci_unmap_addr(&tnapi->tx_buffers[entry], mapping),
5916 for (i = 0; i <= last; i++) {
5917 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5918 entry = NEXT_TX(entry);
5920 pci_unmap_page(tp->pdev,
5921 pci_unmap_addr(&tnapi->tx_buffers[entry],
5923 frag->size, PCI_DMA_TODEVICE);
5927 return NETDEV_TX_OK;
5930 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
5935 if (new_mtu > ETH_DATA_LEN) {
5936 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
5937 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
5938 ethtool_op_set_tso(dev, 0);
5941 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
5943 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
5944 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
5945 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
5949 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
5951 struct tg3 *tp = netdev_priv(dev);
5954 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
5957 if (!netif_running(dev)) {
5958 /* We'll just catch it later when the
5961 tg3_set_mtu(dev, tp, new_mtu);
5969 tg3_full_lock(tp, 1);
5971 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5973 tg3_set_mtu(dev, tp, new_mtu);
5975 err = tg3_restart_hw(tp, 0);
5978 tg3_netif_start(tp);
5980 tg3_full_unlock(tp);
5988 static void tg3_rx_prodring_free(struct tg3 *tp,
5989 struct tg3_rx_prodring_set *tpr)
5993 if (tpr != &tp->prodring[0]) {
5994 for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx;
5995 i = (i + 1) % TG3_RX_RING_SIZE)
5996 tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
5999 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
6000 for (i = tpr->rx_jmb_cons_idx;
6001 i != tpr->rx_jmb_prod_idx;
6002 i = (i + 1) % TG3_RX_JUMBO_RING_SIZE) {
6003 tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
6011 for (i = 0; i < TG3_RX_RING_SIZE; i++)
6012 tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
6015 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
6016 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++)
6017 tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
6022 /* Initialize tx/rx rings for packet processing.
6024 * The chip has been shut down and the driver detached from
6025 * the networking, so no interrupts or new tx packets will
6026 * end up in the driver. tp->{tx,}lock are held and thus
6029 static int tg3_rx_prodring_alloc(struct tg3 *tp,
6030 struct tg3_rx_prodring_set *tpr)
6032 u32 i, rx_pkt_dma_sz;
6034 tpr->rx_std_cons_idx = 0;
6035 tpr->rx_std_prod_idx = 0;
6036 tpr->rx_jmb_cons_idx = 0;
6037 tpr->rx_jmb_prod_idx = 0;
6039 if (tpr != &tp->prodring[0]) {
6040 memset(&tpr->rx_std_buffers[0], 0, TG3_RX_STD_BUFF_RING_SIZE);
6041 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE)
6042 memset(&tpr->rx_jmb_buffers[0], 0,
6043 TG3_RX_JMB_BUFF_RING_SIZE);
6047 /* Zero out all descriptors. */
6048 memset(tpr->rx_std, 0, TG3_RX_RING_BYTES);
6050 rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
6051 if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
6052 tp->dev->mtu > ETH_DATA_LEN)
6053 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
6054 tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
6056 /* Initialize invariants of the rings, we only set this
6057 * stuff once. This works because the card does not
6058 * write into the rx buffer posting rings.
6060 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
6061 struct tg3_rx_buffer_desc *rxd;
6063 rxd = &tpr->rx_std[i];
6064 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
6065 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
6066 rxd->opaque = (RXD_OPAQUE_RING_STD |
6067 (i << RXD_OPAQUE_INDEX_SHIFT));
6070 /* Now allocate fresh SKBs for each rx ring. */
6071 for (i = 0; i < tp->rx_pending; i++) {
6072 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_STD, i) < 0) {
6073 printk(KERN_WARNING PFX
6074 "%s: Using a smaller RX standard ring, "
6075 "only %d out of %d buffers were allocated "
6077 tp->dev->name, i, tp->rx_pending);
6085 if (!(tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE))
6088 memset(tpr->rx_jmb, 0, TG3_RX_JUMBO_RING_BYTES);
6090 if (!(tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE))
6093 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
6094 struct tg3_rx_buffer_desc *rxd;
6096 rxd = &tpr->rx_jmb[i].std;
6097 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
6098 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
6100 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
6101 (i << RXD_OPAQUE_INDEX_SHIFT));
6104 for (i = 0; i < tp->rx_jumbo_pending; i++) {
6105 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_JUMBO, i) < 0) {
6106 printk(KERN_WARNING PFX
6107 "%s: Using a smaller RX jumbo ring, "
6108 "only %d out of %d buffers were "
6109 "allocated successfully.\n",
6110 tp->dev->name, i, tp->rx_jumbo_pending);
6113 tp->rx_jumbo_pending = i;
6122 tg3_rx_prodring_free(tp, tpr);
6126 static void tg3_rx_prodring_fini(struct tg3 *tp,
6127 struct tg3_rx_prodring_set *tpr)
6129 kfree(tpr->rx_std_buffers);
6130 tpr->rx_std_buffers = NULL;
6131 kfree(tpr->rx_jmb_buffers);
6132 tpr->rx_jmb_buffers = NULL;
6134 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
6135 tpr->rx_std, tpr->rx_std_mapping);
6139 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
6140 tpr->rx_jmb, tpr->rx_jmb_mapping);
6145 static int tg3_rx_prodring_init(struct tg3 *tp,
6146 struct tg3_rx_prodring_set *tpr)
6148 tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE, GFP_KERNEL);
6149 if (!tpr->rx_std_buffers)
6152 tpr->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
6153 &tpr->rx_std_mapping);
6157 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
6158 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE,
6160 if (!tpr->rx_jmb_buffers)
6163 tpr->rx_jmb = pci_alloc_consistent(tp->pdev,
6164 TG3_RX_JUMBO_RING_BYTES,
6165 &tpr->rx_jmb_mapping);
6173 tg3_rx_prodring_fini(tp, tpr);
6177 /* Free up pending packets in all rx/tx rings.
6179 * The chip has been shut down and the driver detached from
6180 * the networking, so no interrupts or new tx packets will
6181 * end up in the driver. tp->{tx,}lock is not held and we are not
6182 * in an interrupt context and thus may sleep.
6184 static void tg3_free_rings(struct tg3 *tp)
6188 for (j = 0; j < tp->irq_cnt; j++) {
6189 struct tg3_napi *tnapi = &tp->napi[j];
6191 if (!tnapi->tx_buffers)
6194 for (i = 0; i < TG3_TX_RING_SIZE; ) {
6195 struct ring_info *txp;
6196 struct sk_buff *skb;
6199 txp = &tnapi->tx_buffers[i];
6207 pci_unmap_single(tp->pdev,
6208 pci_unmap_addr(txp, mapping),
6215 for (k = 0; k < skb_shinfo(skb)->nr_frags; k++) {
6216 txp = &tnapi->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
6217 pci_unmap_page(tp->pdev,
6218 pci_unmap_addr(txp, mapping),
6219 skb_shinfo(skb)->frags[k].size,
6224 dev_kfree_skb_any(skb);
6227 tg3_rx_prodring_free(tp, &tp->prodring[j]);
6231 /* Initialize tx/rx rings for packet processing.
6233 * The chip has been shut down and the driver detached from
6234 * the networking, so no interrupts or new tx packets will
6235 * end up in the driver. tp->{tx,}lock are held and thus
6238 static int tg3_init_rings(struct tg3 *tp)
6242 /* Free up all the SKBs. */
6245 for (i = 0; i < tp->irq_cnt; i++) {
6246 struct tg3_napi *tnapi = &tp->napi[i];
6248 tnapi->last_tag = 0;
6249 tnapi->last_irq_tag = 0;
6250 tnapi->hw_status->status = 0;
6251 tnapi->hw_status->status_tag = 0;
6252 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6257 memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
6259 tnapi->rx_rcb_ptr = 0;
6261 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
6263 if (tg3_rx_prodring_alloc(tp, &tp->prodring[i])) {
6273 * Must not be invoked with interrupt sources disabled and
6274 * the hardware shutdown down.
6276 static void tg3_free_consistent(struct tg3 *tp)
6280 for (i = 0; i < tp->irq_cnt; i++) {
6281 struct tg3_napi *tnapi = &tp->napi[i];
6283 if (tnapi->tx_ring) {
6284 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
6285 tnapi->tx_ring, tnapi->tx_desc_mapping);
6286 tnapi->tx_ring = NULL;
6289 kfree(tnapi->tx_buffers);
6290 tnapi->tx_buffers = NULL;
6292 if (tnapi->rx_rcb) {
6293 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
6295 tnapi->rx_rcb_mapping);
6296 tnapi->rx_rcb = NULL;
6299 if (tnapi->hw_status) {
6300 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
6302 tnapi->status_mapping);
6303 tnapi->hw_status = NULL;
6308 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
6309 tp->hw_stats, tp->stats_mapping);
6310 tp->hw_stats = NULL;
6313 for (i = 0; i < tp->irq_cnt; i++)
6314 tg3_rx_prodring_fini(tp, &tp->prodring[i]);
6318 * Must not be invoked with interrupt sources disabled and
6319 * the hardware shutdown down. Can sleep.
6321 static int tg3_alloc_consistent(struct tg3 *tp)
6325 for (i = 0; i < tp->irq_cnt; i++) {
6326 if (tg3_rx_prodring_init(tp, &tp->prodring[i]))
6330 tp->hw_stats = pci_alloc_consistent(tp->pdev,
6331 sizeof(struct tg3_hw_stats),
6332 &tp->stats_mapping);
6336 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6338 for (i = 0; i < tp->irq_cnt; i++) {
6339 struct tg3_napi *tnapi = &tp->napi[i];
6340 struct tg3_hw_status *sblk;
6342 tnapi->hw_status = pci_alloc_consistent(tp->pdev,
6344 &tnapi->status_mapping);
6345 if (!tnapi->hw_status)
6348 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6349 sblk = tnapi->hw_status;
6351 /* If multivector TSS is enabled, vector 0 does not handle
6352 * tx interrupts. Don't allocate any resources for it.
6354 if ((!i && !(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) ||
6355 (i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))) {
6356 tnapi->tx_buffers = kzalloc(sizeof(struct ring_info) *
6359 if (!tnapi->tx_buffers)
6362 tnapi->tx_ring = pci_alloc_consistent(tp->pdev,
6364 &tnapi->tx_desc_mapping);
6365 if (!tnapi->tx_ring)
6370 * When RSS is enabled, the status block format changes
6371 * slightly. The "rx_jumbo_consumer", "reserved",
6372 * and "rx_mini_consumer" members get mapped to the
6373 * other three rx return ring producer indexes.
6377 tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
6380 tnapi->rx_rcb_prod_idx = &sblk->rx_jumbo_consumer;
6383 tnapi->rx_rcb_prod_idx = &sblk->reserved;
6386 tnapi->rx_rcb_prod_idx = &sblk->rx_mini_consumer;
6390 tnapi->prodring = &tp->prodring[i];
6393 * If multivector RSS is enabled, vector 0 does not handle
6394 * rx or tx interrupts. Don't allocate any resources for it.
6396 if (!i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS))
6399 tnapi->rx_rcb = pci_alloc_consistent(tp->pdev,
6400 TG3_RX_RCB_RING_BYTES(tp),
6401 &tnapi->rx_rcb_mapping);
6405 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
6411 tg3_free_consistent(tp);
6415 #define MAX_WAIT_CNT 1000
6417 /* To stop a block, clear the enable bit and poll till it
6418 * clears. tp->lock is held.
6420 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
6425 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6432 /* We can't enable/disable these bits of the
6433 * 5705/5750, just say success.
6446 for (i = 0; i < MAX_WAIT_CNT; i++) {
6449 if ((val & enable_bit) == 0)
6453 if (i == MAX_WAIT_CNT && !silent) {
6454 printk(KERN_ERR PFX "tg3_stop_block timed out, "
6455 "ofs=%lx enable_bit=%x\n",
6463 /* tp->lock is held. */
6464 static int tg3_abort_hw(struct tg3 *tp, int silent)
6468 tg3_disable_ints(tp);
6470 tp->rx_mode &= ~RX_MODE_ENABLE;
6471 tw32_f(MAC_RX_MODE, tp->rx_mode);
6474 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
6475 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
6476 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
6477 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
6478 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
6479 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
6481 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
6482 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
6483 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
6484 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
6485 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
6486 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
6487 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
6489 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
6490 tw32_f(MAC_MODE, tp->mac_mode);
6493 tp->tx_mode &= ~TX_MODE_ENABLE;
6494 tw32_f(MAC_TX_MODE, tp->tx_mode);
6496 for (i = 0; i < MAX_WAIT_CNT; i++) {
6498 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
6501 if (i >= MAX_WAIT_CNT) {
6502 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
6503 "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
6504 tp->dev->name, tr32(MAC_TX_MODE));
6508 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
6509 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
6510 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
6512 tw32(FTQ_RESET, 0xffffffff);
6513 tw32(FTQ_RESET, 0x00000000);
6515 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
6516 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
6518 for (i = 0; i < tp->irq_cnt; i++) {
6519 struct tg3_napi *tnapi = &tp->napi[i];
6520 if (tnapi->hw_status)
6521 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6524 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6529 static void tg3_ape_send_event(struct tg3 *tp, u32 event)
6534 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
6535 if (apedata != APE_SEG_SIG_MAGIC)
6538 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
6539 if (!(apedata & APE_FW_STATUS_READY))
6542 /* Wait for up to 1 millisecond for APE to service previous event. */
6543 for (i = 0; i < 10; i++) {
6544 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
6547 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
6549 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6550 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
6551 event | APE_EVENT_STATUS_EVENT_PENDING);
6553 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
6555 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6561 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6562 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
6565 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
6570 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
6574 case RESET_KIND_INIT:
6575 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
6576 APE_HOST_SEG_SIG_MAGIC);
6577 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
6578 APE_HOST_SEG_LEN_MAGIC);
6579 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
6580 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
6581 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
6582 APE_HOST_DRIVER_ID_MAGIC);
6583 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
6584 APE_HOST_BEHAV_NO_PHYLOCK);
6586 event = APE_EVENT_STATUS_STATE_START;
6588 case RESET_KIND_SHUTDOWN:
6589 /* With the interface we are currently using,
6590 * APE does not track driver state. Wiping
6591 * out the HOST SEGMENT SIGNATURE forces
6592 * the APE to assume OS absent status.
6594 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
6596 event = APE_EVENT_STATUS_STATE_UNLOAD;
6598 case RESET_KIND_SUSPEND:
6599 event = APE_EVENT_STATUS_STATE_SUSPEND;
6605 event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
6607 tg3_ape_send_event(tp, event);
6610 /* tp->lock is held. */
6611 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
6613 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
6614 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
6616 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6618 case RESET_KIND_INIT:
6619 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6623 case RESET_KIND_SHUTDOWN:
6624 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6628 case RESET_KIND_SUSPEND:
6629 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6638 if (kind == RESET_KIND_INIT ||
6639 kind == RESET_KIND_SUSPEND)
6640 tg3_ape_driver_state_change(tp, kind);
6643 /* tp->lock is held. */
6644 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
6646 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6648 case RESET_KIND_INIT:
6649 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6650 DRV_STATE_START_DONE);
6653 case RESET_KIND_SHUTDOWN:
6654 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6655 DRV_STATE_UNLOAD_DONE);
6663 if (kind == RESET_KIND_SHUTDOWN)
6664 tg3_ape_driver_state_change(tp, kind);
6667 /* tp->lock is held. */
6668 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
6670 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6672 case RESET_KIND_INIT:
6673 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6677 case RESET_KIND_SHUTDOWN:
6678 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6682 case RESET_KIND_SUSPEND:
6683 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6693 static int tg3_poll_fw(struct tg3 *tp)
6698 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6699 /* Wait up to 20ms for init done. */
6700 for (i = 0; i < 200; i++) {
6701 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
6708 /* Wait for firmware initialization to complete. */
6709 for (i = 0; i < 100000; i++) {
6710 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
6711 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
6716 /* Chip might not be fitted with firmware. Some Sun onboard
6717 * parts are configured like that. So don't signal the timeout
6718 * of the above loop as an error, but do report the lack of
6719 * running firmware once.
6722 !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
6723 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
6725 printk(KERN_INFO PFX "%s: No firmware running.\n",
6729 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
6730 /* The 57765 A0 needs a little more
6731 * time to do some important work.
6739 /* Save PCI command register before chip reset */
6740 static void tg3_save_pci_state(struct tg3 *tp)
6742 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
6745 /* Restore PCI state after chip reset */
6746 static void tg3_restore_pci_state(struct tg3 *tp)
6750 /* Re-enable indirect register accesses. */
6751 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
6752 tp->misc_host_ctrl);
6754 /* Set MAX PCI retry to zero. */
6755 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
6756 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6757 (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
6758 val |= PCISTATE_RETRY_SAME_DMA;
6759 /* Allow reads and writes to the APE register and memory space. */
6760 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
6761 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6762 PCISTATE_ALLOW_APE_SHMEM_WR;
6763 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
6765 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
6767 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
6768 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6769 pcie_set_readrq(tp->pdev, 4096);
6771 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
6772 tp->pci_cacheline_sz);
6773 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
6778 /* Make sure PCI-X relaxed ordering bit is clear. */
6779 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
6782 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6784 pcix_cmd &= ~PCI_X_CMD_ERO;
6785 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6789 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
6791 /* Chip reset on 5780 will reset MSI enable bit,
6792 * so need to restore it.
6794 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6797 pci_read_config_word(tp->pdev,
6798 tp->msi_cap + PCI_MSI_FLAGS,
6800 pci_write_config_word(tp->pdev,
6801 tp->msi_cap + PCI_MSI_FLAGS,
6802 ctrl | PCI_MSI_FLAGS_ENABLE);
6803 val = tr32(MSGINT_MODE);
6804 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
6809 static void tg3_stop_fw(struct tg3 *);
6811 /* tp->lock is held. */
6812 static int tg3_chip_reset(struct tg3 *tp)
6815 void (*write_op)(struct tg3 *, u32, u32);
6820 tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
6822 /* No matching tg3_nvram_unlock() after this because
6823 * chip reset below will undo the nvram lock.
6825 tp->nvram_lock_cnt = 0;
6827 /* GRC_MISC_CFG core clock reset will clear the memory
6828 * enable bit in PCI register 4 and the MSI enable bit
6829 * on some chips, so we save relevant registers here.
6831 tg3_save_pci_state(tp);
6833 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
6834 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
6835 tw32(GRC_FASTBOOT_PC, 0);
6838 * We must avoid the readl() that normally takes place.
6839 * It locks machines, causes machine checks, and other
6840 * fun things. So, temporarily disable the 5701
6841 * hardware workaround, while we do the reset.
6843 write_op = tp->write32;
6844 if (write_op == tg3_write_flush_reg32)
6845 tp->write32 = tg3_write32;
6847 /* Prevent the irq handler from reading or writing PCI registers
6848 * during chip reset when the memory enable bit in the PCI command
6849 * register may be cleared. The chip does not generate interrupt
6850 * at this time, but the irq handler may still be called due to irq
6851 * sharing or irqpoll.
6853 tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
6854 for (i = 0; i < tp->irq_cnt; i++) {
6855 struct tg3_napi *tnapi = &tp->napi[i];
6856 if (tnapi->hw_status) {
6857 tnapi->hw_status->status = 0;
6858 tnapi->hw_status->status_tag = 0;
6860 tnapi->last_tag = 0;
6861 tnapi->last_irq_tag = 0;
6865 for (i = 0; i < tp->irq_cnt; i++)
6866 synchronize_irq(tp->napi[i].irq_vec);
6868 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6869 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
6870 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
6874 val = GRC_MISC_CFG_CORECLK_RESET;
6876 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
6877 if (tr32(0x7e2c) == 0x60) {
6880 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
6881 tw32(GRC_MISC_CFG, (1 << 29));
6886 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6887 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
6888 tw32(GRC_VCPU_EXT_CTRL,
6889 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
6892 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6893 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
6894 tw32(GRC_MISC_CFG, val);
6896 /* restore 5701 hardware bug workaround write method */
6897 tp->write32 = write_op;
6899 /* Unfortunately, we have to delay before the PCI read back.
6900 * Some 575X chips even will not respond to a PCI cfg access
6901 * when the reset command is given to the chip.
6903 * How do these hardware designers expect things to work
6904 * properly if the PCI write is posted for a long period
6905 * of time? It is always necessary to have some method by
6906 * which a register read back can occur to push the write
6907 * out which does the reset.
6909 * For most tg3 variants the trick below was working.
6914 /* Flush PCI posted writes. The normal MMIO registers
6915 * are inaccessible at this time so this is the only
6916 * way to make this reliably (actually, this is no longer
6917 * the case, see above). I tried to use indirect
6918 * register read/write but this upset some 5701 variants.
6920 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
6924 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
6927 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
6931 /* Wait for link training to complete. */
6932 for (i = 0; i < 5000; i++)
6935 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
6936 pci_write_config_dword(tp->pdev, 0xc4,
6937 cfg_val | (1 << 15));
6940 /* Clear the "no snoop" and "relaxed ordering" bits. */
6941 pci_read_config_word(tp->pdev,
6942 tp->pcie_cap + PCI_EXP_DEVCTL,
6944 val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
6945 PCI_EXP_DEVCTL_NOSNOOP_EN);
6947 * Older PCIe devices only support the 128 byte
6948 * MPS setting. Enforce the restriction.
6950 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
6951 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784))
6952 val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
6953 pci_write_config_word(tp->pdev,
6954 tp->pcie_cap + PCI_EXP_DEVCTL,
6957 pcie_set_readrq(tp->pdev, 4096);
6959 /* Clear error status */
6960 pci_write_config_word(tp->pdev,
6961 tp->pcie_cap + PCI_EXP_DEVSTA,
6962 PCI_EXP_DEVSTA_CED |
6963 PCI_EXP_DEVSTA_NFED |
6964 PCI_EXP_DEVSTA_FED |
6965 PCI_EXP_DEVSTA_URD);
6968 tg3_restore_pci_state(tp);
6970 tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
6973 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
6974 val = tr32(MEMARB_MODE);
6975 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
6977 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
6979 tw32(0x5000, 0x400);
6982 tw32(GRC_MODE, tp->grc_mode);
6984 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
6987 tw32(0xc4, val | (1 << 15));
6990 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
6991 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6992 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
6993 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
6994 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
6995 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6998 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6999 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
7000 tw32_f(MAC_MODE, tp->mac_mode);
7001 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
7002 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
7003 tw32_f(MAC_MODE, tp->mac_mode);
7004 } else if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
7005 tp->mac_mode &= (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
7006 if (tp->mac_mode & MAC_MODE_APE_TX_EN)
7007 tp->mac_mode |= MAC_MODE_TDE_ENABLE;
7008 tw32_f(MAC_MODE, tp->mac_mode);
7010 tw32_f(MAC_MODE, 0);
7013 tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
7015 err = tg3_poll_fw(tp);
7021 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7024 phy_addr = tp->phy_addr;
7025 tp->phy_addr = TG3_PHY_PCIE_ADDR;
7027 tg3_writephy(tp, TG3_PCIEPHY_BLOCK_ADDR,
7028 TG3_PCIEPHY_TXB_BLK << TG3_PCIEPHY_BLOCK_SHIFT);
7029 val = TG3_PCIEPHY_TX0CTRL1_TXOCM | TG3_PCIEPHY_TX0CTRL1_RDCTL |
7030 TG3_PCIEPHY_TX0CTRL1_TXCMV | TG3_PCIEPHY_TX0CTRL1_TKSEL |
7031 TG3_PCIEPHY_TX0CTRL1_NB_EN;
7032 tg3_writephy(tp, TG3_PCIEPHY_TX0CTRL1, val);
7035 tg3_writephy(tp, TG3_PCIEPHY_BLOCK_ADDR,
7036 TG3_PCIEPHY_XGXS_BLK1 << TG3_PCIEPHY_BLOCK_SHIFT);
7037 val = TG3_PCIEPHY_PWRMGMT4_LOWPWR_EN |
7038 TG3_PCIEPHY_PWRMGMT4_L1PLLPD_EN;
7039 tg3_writephy(tp, TG3_PCIEPHY_PWRMGMT4, val);
7042 tp->phy_addr = phy_addr;
7045 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
7046 tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
7047 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
7048 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
7049 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765) {
7052 tw32(0x7c00, val | (1 << 25));
7055 /* Reprobe ASF enable state. */
7056 tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
7057 tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
7058 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
7059 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
7062 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
7063 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
7064 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
7065 tp->last_event_jiffies = jiffies;
7066 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
7067 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
7074 /* tp->lock is held. */
7075 static void tg3_stop_fw(struct tg3 *tp)
7077 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
7078 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7079 /* Wait for RX cpu to ACK the previous event. */
7080 tg3_wait_for_event_ack(tp);
7082 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
7084 tg3_generate_fw_event(tp);
7086 /* Wait for RX cpu to ACK this event. */
7087 tg3_wait_for_event_ack(tp);
7091 /* tp->lock is held. */
7092 static int tg3_halt(struct tg3 *tp, int kind, int silent)
7098 tg3_write_sig_pre_reset(tp, kind);
7100 tg3_abort_hw(tp, silent);
7101 err = tg3_chip_reset(tp);
7103 __tg3_set_mac_addr(tp, 0);
7105 tg3_write_sig_legacy(tp, kind);
7106 tg3_write_sig_post_reset(tp, kind);
7114 #define RX_CPU_SCRATCH_BASE 0x30000
7115 #define RX_CPU_SCRATCH_SIZE 0x04000
7116 #define TX_CPU_SCRATCH_BASE 0x34000
7117 #define TX_CPU_SCRATCH_SIZE 0x04000
7119 /* tp->lock is held. */
7120 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
7124 BUG_ON(offset == TX_CPU_BASE &&
7125 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
7127 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7128 u32 val = tr32(GRC_VCPU_EXT_CTRL);
7130 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
7133 if (offset == RX_CPU_BASE) {
7134 for (i = 0; i < 10000; i++) {
7135 tw32(offset + CPU_STATE, 0xffffffff);
7136 tw32(offset + CPU_MODE, CPU_MODE_HALT);
7137 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7141 tw32(offset + CPU_STATE, 0xffffffff);
7142 tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
7145 for (i = 0; i < 10000; i++) {
7146 tw32(offset + CPU_STATE, 0xffffffff);
7147 tw32(offset + CPU_MODE, CPU_MODE_HALT);
7148 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7154 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
7157 (offset == RX_CPU_BASE ? "RX" : "TX"));
7161 /* Clear firmware's nvram arbitration. */
7162 if (tp->tg3_flags & TG3_FLAG_NVRAM)
7163 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
7168 unsigned int fw_base;
7169 unsigned int fw_len;
7170 const __be32 *fw_data;
7173 /* tp->lock is held. */
7174 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
7175 int cpu_scratch_size, struct fw_info *info)
7177 int err, lock_err, i;
7178 void (*write_op)(struct tg3 *, u32, u32);
7180 if (cpu_base == TX_CPU_BASE &&
7181 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7182 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
7183 "TX cpu firmware on %s which is 5705.\n",
7188 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7189 write_op = tg3_write_mem;
7191 write_op = tg3_write_indirect_reg32;
7193 /* It is possible that bootcode is still loading at this point.
7194 * Get the nvram lock first before halting the cpu.
7196 lock_err = tg3_nvram_lock(tp);
7197 err = tg3_halt_cpu(tp, cpu_base);
7199 tg3_nvram_unlock(tp);
7203 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
7204 write_op(tp, cpu_scratch_base + i, 0);
7205 tw32(cpu_base + CPU_STATE, 0xffffffff);
7206 tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
7207 for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
7208 write_op(tp, (cpu_scratch_base +
7209 (info->fw_base & 0xffff) +
7211 be32_to_cpu(info->fw_data[i]));
7219 /* tp->lock is held. */
7220 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
7222 struct fw_info info;
7223 const __be32 *fw_data;
7226 fw_data = (void *)tp->fw->data;
7228 /* Firmware blob starts with version numbers, followed by
7229 start address and length. We are setting complete length.
7230 length = end_address_of_bss - start_address_of_text.
7231 Remainder is the blob to be loaded contiguously
7232 from start address. */
7234 info.fw_base = be32_to_cpu(fw_data[1]);
7235 info.fw_len = tp->fw->size - 12;
7236 info.fw_data = &fw_data[3];
7238 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
7239 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
7244 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
7245 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
7250 /* Now startup only the RX cpu. */
7251 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7252 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
7254 for (i = 0; i < 5; i++) {
7255 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
7257 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7258 tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
7259 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
7263 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
7264 "to set RX CPU PC, is %08x should be %08x\n",
7265 tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
7269 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7270 tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
7275 /* 5705 needs a special version of the TSO firmware. */
7277 /* tp->lock is held. */
7278 static int tg3_load_tso_firmware(struct tg3 *tp)
7280 struct fw_info info;
7281 const __be32 *fw_data;
7282 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
7285 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7288 fw_data = (void *)tp->fw->data;
7290 /* Firmware blob starts with version numbers, followed by
7291 start address and length. We are setting complete length.
7292 length = end_address_of_bss - start_address_of_text.
7293 Remainder is the blob to be loaded contiguously
7294 from start address. */
7296 info.fw_base = be32_to_cpu(fw_data[1]);
7297 cpu_scratch_size = tp->fw_len;
7298 info.fw_len = tp->fw->size - 12;
7299 info.fw_data = &fw_data[3];
7301 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7302 cpu_base = RX_CPU_BASE;
7303 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
7305 cpu_base = TX_CPU_BASE;
7306 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
7307 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
7310 err = tg3_load_firmware_cpu(tp, cpu_base,
7311 cpu_scratch_base, cpu_scratch_size,
7316 /* Now startup the cpu. */
7317 tw32(cpu_base + CPU_STATE, 0xffffffff);
7318 tw32_f(cpu_base + CPU_PC, info.fw_base);
7320 for (i = 0; i < 5; i++) {
7321 if (tr32(cpu_base + CPU_PC) == info.fw_base)
7323 tw32(cpu_base + CPU_STATE, 0xffffffff);
7324 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
7325 tw32_f(cpu_base + CPU_PC, info.fw_base);
7329 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
7330 "to set CPU PC, is %08x should be %08x\n",
7331 tp->dev->name, tr32(cpu_base + CPU_PC),
7335 tw32(cpu_base + CPU_STATE, 0xffffffff);
7336 tw32_f(cpu_base + CPU_MODE, 0x00000000);
7341 static int tg3_set_mac_addr(struct net_device *dev, void *p)
7343 struct tg3 *tp = netdev_priv(dev);
7344 struct sockaddr *addr = p;
7345 int err = 0, skip_mac_1 = 0;
7347 if (!is_valid_ether_addr(addr->sa_data))
7350 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
7352 if (!netif_running(dev))
7355 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
7356 u32 addr0_high, addr0_low, addr1_high, addr1_low;
7358 addr0_high = tr32(MAC_ADDR_0_HIGH);
7359 addr0_low = tr32(MAC_ADDR_0_LOW);
7360 addr1_high = tr32(MAC_ADDR_1_HIGH);
7361 addr1_low = tr32(MAC_ADDR_1_LOW);
7363 /* Skip MAC addr 1 if ASF is using it. */
7364 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
7365 !(addr1_high == 0 && addr1_low == 0))
7368 spin_lock_bh(&tp->lock);
7369 __tg3_set_mac_addr(tp, skip_mac_1);
7370 spin_unlock_bh(&tp->lock);
7375 /* tp->lock is held. */
7376 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
7377 dma_addr_t mapping, u32 maxlen_flags,
7381 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
7382 ((u64) mapping >> 32));
7384 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
7385 ((u64) mapping & 0xffffffff));
7387 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
7390 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7392 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
7396 static void __tg3_set_rx_mode(struct net_device *);
7397 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
7401 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) {
7402 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
7403 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
7404 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
7406 tw32(HOSTCC_TXCOL_TICKS, 0);
7407 tw32(HOSTCC_TXMAX_FRAMES, 0);
7408 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
7411 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
7412 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
7413 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
7414 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
7416 tw32(HOSTCC_RXCOL_TICKS, 0);
7417 tw32(HOSTCC_RXMAX_FRAMES, 0);
7418 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
7421 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7422 u32 val = ec->stats_block_coalesce_usecs;
7424 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
7425 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
7427 if (!netif_carrier_ok(tp->dev))
7430 tw32(HOSTCC_STAT_COAL_TICKS, val);
7433 for (i = 0; i < tp->irq_cnt - 1; i++) {
7436 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
7437 tw32(reg, ec->rx_coalesce_usecs);
7438 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
7439 tw32(reg, ec->rx_max_coalesced_frames);
7440 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
7441 tw32(reg, ec->rx_max_coalesced_frames_irq);
7443 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7444 reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
7445 tw32(reg, ec->tx_coalesce_usecs);
7446 reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
7447 tw32(reg, ec->tx_max_coalesced_frames);
7448 reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
7449 tw32(reg, ec->tx_max_coalesced_frames_irq);
7453 for (; i < tp->irq_max - 1; i++) {
7454 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
7455 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
7456 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7458 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7459 tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
7460 tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
7461 tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7466 /* tp->lock is held. */
7467 static void tg3_rings_reset(struct tg3 *tp)
7470 u32 stblk, txrcb, rxrcb, limit;
7471 struct tg3_napi *tnapi = &tp->napi[0];
7473 /* Disable all transmit rings but the first. */
7474 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7475 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
7476 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7477 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2;
7479 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7481 for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7482 txrcb < limit; txrcb += TG3_BDINFO_SIZE)
7483 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
7484 BDINFO_FLAGS_DISABLED);
7487 /* Disable all receive return rings but the first. */
7488 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
7489 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
7490 else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7491 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
7492 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
7493 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7494 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
7496 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7498 for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7499 rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
7500 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
7501 BDINFO_FLAGS_DISABLED);
7503 /* Disable interrupts */
7504 tw32_mailbox_f(tp->napi[0].int_mbox, 1);
7506 /* Zero mailbox registers. */
7507 if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) {
7508 for (i = 1; i < TG3_IRQ_MAX_VECS; i++) {
7509 tp->napi[i].tx_prod = 0;
7510 tp->napi[i].tx_cons = 0;
7511 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
7512 tw32_mailbox(tp->napi[i].prodmbox, 0);
7513 tw32_rx_mbox(tp->napi[i].consmbox, 0);
7514 tw32_mailbox_f(tp->napi[i].int_mbox, 1);
7516 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))
7517 tw32_mailbox(tp->napi[0].prodmbox, 0);
7519 tp->napi[0].tx_prod = 0;
7520 tp->napi[0].tx_cons = 0;
7521 tw32_mailbox(tp->napi[0].prodmbox, 0);
7522 tw32_rx_mbox(tp->napi[0].consmbox, 0);
7525 /* Make sure the NIC-based send BD rings are disabled. */
7526 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7527 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
7528 for (i = 0; i < 16; i++)
7529 tw32_tx_mbox(mbox + i * 8, 0);
7532 txrcb = NIC_SRAM_SEND_RCB;
7533 rxrcb = NIC_SRAM_RCV_RET_RCB;
7535 /* Clear status block in ram. */
7536 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7538 /* Set status block DMA address */
7539 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7540 ((u64) tnapi->status_mapping >> 32));
7541 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7542 ((u64) tnapi->status_mapping & 0xffffffff));
7544 if (tnapi->tx_ring) {
7545 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7546 (TG3_TX_RING_SIZE <<
7547 BDINFO_FLAGS_MAXLEN_SHIFT),
7548 NIC_SRAM_TX_BUFFER_DESC);
7549 txrcb += TG3_BDINFO_SIZE;
7552 if (tnapi->rx_rcb) {
7553 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7554 (TG3_RX_RCB_RING_SIZE(tp) <<
7555 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7556 rxrcb += TG3_BDINFO_SIZE;
7559 stblk = HOSTCC_STATBLCK_RING1;
7561 for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
7562 u64 mapping = (u64)tnapi->status_mapping;
7563 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
7564 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
7566 /* Clear status block in ram. */
7567 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7569 if (tnapi->tx_ring) {
7570 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7571 (TG3_TX_RING_SIZE <<
7572 BDINFO_FLAGS_MAXLEN_SHIFT),
7573 NIC_SRAM_TX_BUFFER_DESC);
7574 txrcb += TG3_BDINFO_SIZE;
7577 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7578 (TG3_RX_RCB_RING_SIZE(tp) <<
7579 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7582 rxrcb += TG3_BDINFO_SIZE;
7586 /* tp->lock is held. */
7587 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
7589 u32 val, rdmac_mode;
7591 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
7593 tg3_disable_ints(tp);
7597 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
7599 if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
7600 tg3_abort_hw(tp, 1);
7606 err = tg3_chip_reset(tp);
7610 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
7612 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
7613 val = tr32(TG3_CPMU_CTRL);
7614 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
7615 tw32(TG3_CPMU_CTRL, val);
7617 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7618 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7619 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7620 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7622 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
7623 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
7624 val |= CPMU_LNK_AWARE_MACCLK_6_25;
7625 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
7627 val = tr32(TG3_CPMU_HST_ACC);
7628 val &= ~CPMU_HST_ACC_MACCLK_MASK;
7629 val |= CPMU_HST_ACC_MACCLK_6_25;
7630 tw32(TG3_CPMU_HST_ACC, val);
7633 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7634 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
7635 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
7636 PCIE_PWR_MGMT_L1_THRESH_4MS;
7637 tw32(PCIE_PWR_MGMT_THRESH, val);
7639 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
7640 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
7642 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
7644 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
7645 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
7648 if (tp->tg3_flags3 & TG3_FLG3_L1PLLPD_EN) {
7649 u32 grc_mode = tr32(GRC_MODE);
7651 /* Access the lower 1K of PL PCIE block registers. */
7652 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
7653 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
7655 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1);
7656 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1,
7657 val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN);
7659 tw32(GRC_MODE, grc_mode);
7662 /* This works around an issue with Athlon chipsets on
7663 * B3 tigon3 silicon. This bit has no effect on any
7664 * other revision. But do not set this on PCI Express
7665 * chips and don't even touch the clocks if the CPMU is present.
7667 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
7668 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
7669 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
7670 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7673 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
7674 (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
7675 val = tr32(TG3PCI_PCISTATE);
7676 val |= PCISTATE_RETRY_SAME_DMA;
7677 tw32(TG3PCI_PCISTATE, val);
7680 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
7681 /* Allow reads and writes to the
7682 * APE register and memory space.
7684 val = tr32(TG3PCI_PCISTATE);
7685 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
7686 PCISTATE_ALLOW_APE_SHMEM_WR;
7687 tw32(TG3PCI_PCISTATE, val);
7690 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
7691 /* Enable some hw fixes. */
7692 val = tr32(TG3PCI_MSI_DATA);
7693 val |= (1 << 26) | (1 << 28) | (1 << 29);
7694 tw32(TG3PCI_MSI_DATA, val);
7697 /* Descriptor ring init may make accesses to the
7698 * NIC SRAM area to setup the TX descriptors, so we
7699 * can only do this after the hardware has been
7700 * successfully reset.
7702 err = tg3_init_rings(tp);
7706 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7707 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
7708 val = tr32(TG3PCI_DMA_RW_CTRL) &
7709 ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
7710 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
7711 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
7712 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
7713 /* This value is determined during the probe time DMA
7714 * engine test, tg3_test_dma.
7716 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
7719 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
7720 GRC_MODE_4X_NIC_SEND_RINGS |
7721 GRC_MODE_NO_TX_PHDR_CSUM |
7722 GRC_MODE_NO_RX_PHDR_CSUM);
7723 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
7725 /* Pseudo-header checksum is done by hardware logic and not
7726 * the offload processers, so make the chip do the pseudo-
7727 * header checksums on receive. For transmit it is more
7728 * convenient to do the pseudo-header checksum in software
7729 * as Linux does that on transmit for us in all cases.
7731 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
7735 (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
7737 /* Setup the timer prescalar register. Clock is always 66Mhz. */
7738 val = tr32(GRC_MISC_CFG);
7740 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
7741 tw32(GRC_MISC_CFG, val);
7743 /* Initialize MBUF/DESC pool. */
7744 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7746 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
7747 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
7748 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
7749 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
7751 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
7752 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
7753 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
7755 else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7758 fw_len = tp->fw_len;
7759 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
7760 tw32(BUFMGR_MB_POOL_ADDR,
7761 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
7762 tw32(BUFMGR_MB_POOL_SIZE,
7763 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
7766 if (tp->dev->mtu <= ETH_DATA_LEN) {
7767 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7768 tp->bufmgr_config.mbuf_read_dma_low_water);
7769 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7770 tp->bufmgr_config.mbuf_mac_rx_low_water);
7771 tw32(BUFMGR_MB_HIGH_WATER,
7772 tp->bufmgr_config.mbuf_high_water);
7774 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7775 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
7776 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7777 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
7778 tw32(BUFMGR_MB_HIGH_WATER,
7779 tp->bufmgr_config.mbuf_high_water_jumbo);
7781 tw32(BUFMGR_DMA_LOW_WATER,
7782 tp->bufmgr_config.dma_low_water);
7783 tw32(BUFMGR_DMA_HIGH_WATER,
7784 tp->bufmgr_config.dma_high_water);
7786 tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
7787 for (i = 0; i < 2000; i++) {
7788 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
7793 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
7798 /* Setup replenish threshold. */
7799 val = tp->rx_pending / 8;
7802 else if (val > tp->rx_std_max_post)
7803 val = tp->rx_std_max_post;
7804 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7805 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
7806 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
7808 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
7809 val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
7812 tw32(RCVBDI_STD_THRESH, val);
7814 /* Initialize TG3_BDINFO's at:
7815 * RCVDBDI_STD_BD: standard eth size rx ring
7816 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
7817 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
7820 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
7821 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
7822 * ring attribute flags
7823 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
7825 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
7826 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
7828 * The size of each ring is fixed in the firmware, but the location is
7831 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7832 ((u64) tpr->rx_std_mapping >> 32));
7833 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7834 ((u64) tpr->rx_std_mapping & 0xffffffff));
7835 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717)
7836 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
7837 NIC_SRAM_RX_BUFFER_DESC);
7839 /* Disable the mini ring */
7840 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7841 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
7842 BDINFO_FLAGS_DISABLED);
7844 /* Program the jumbo buffer descriptor ring control
7845 * blocks on those devices that have them.
7847 if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
7848 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
7849 /* Setup replenish threshold. */
7850 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
7852 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
7853 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7854 ((u64) tpr->rx_jmb_mapping >> 32));
7855 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7856 ((u64) tpr->rx_jmb_mapping & 0xffffffff));
7857 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7858 (RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT) |
7859 BDINFO_FLAGS_USE_EXT_RECV);
7860 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717)
7861 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
7862 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
7864 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7865 BDINFO_FLAGS_DISABLED);
7868 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7869 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7870 val = (RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT) |
7871 (RX_STD_MAX_SIZE << 2);
7873 val = RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT;
7875 val = RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT;
7877 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
7879 tpr->rx_std_prod_idx = tp->rx_pending;
7880 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx);
7882 tpr->rx_jmb_prod_idx = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
7883 tp->rx_jumbo_pending : 0;
7884 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx);
7886 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7887 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
7888 tw32(STD_REPLENISH_LWM, 32);
7889 tw32(JMB_REPLENISH_LWM, 16);
7892 tg3_rings_reset(tp);
7894 /* Initialize MAC address and backoff seed. */
7895 __tg3_set_mac_addr(tp, 0);
7897 /* MTU + ethernet header + FCS + optional VLAN tag */
7898 tw32(MAC_RX_MTU_SIZE,
7899 tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
7901 /* The slot time is changed by tg3_setup_phy if we
7902 * run at gigabit with half duplex.
7904 tw32(MAC_TX_LENGTHS,
7905 (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
7906 (6 << TX_LENGTHS_IPG_SHIFT) |
7907 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
7909 /* Receive rules. */
7910 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
7911 tw32(RCVLPC_CONFIG, 0x0181);
7913 /* Calculate RDMAC_MODE setting early, we need it to determine
7914 * the RCVLPC_STATE_ENABLE mask.
7916 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
7917 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
7918 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
7919 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
7920 RDMAC_MODE_LNGREAD_ENAB);
7922 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
7923 rdmac_mode |= RDMAC_MODE_MULT_DMA_RD_DIS;
7925 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
7926 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7927 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7928 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
7929 RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
7930 RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
7932 /* If statement applies to 5705 and 5750 PCI devices only */
7933 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7934 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7935 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
7936 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
7937 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7938 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
7939 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7940 !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
7941 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7945 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
7946 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7948 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7949 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
7951 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
7952 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7953 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7954 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
7956 /* Receive/send statistics. */
7957 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7958 val = tr32(RCVLPC_STATS_ENABLE);
7959 val &= ~RCVLPC_STATSENAB_DACK_FIX;
7960 tw32(RCVLPC_STATS_ENABLE, val);
7961 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
7962 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
7963 val = tr32(RCVLPC_STATS_ENABLE);
7964 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
7965 tw32(RCVLPC_STATS_ENABLE, val);
7967 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
7969 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
7970 tw32(SNDDATAI_STATSENAB, 0xffffff);
7971 tw32(SNDDATAI_STATSCTRL,
7972 (SNDDATAI_SCTRL_ENABLE |
7973 SNDDATAI_SCTRL_FASTUPD));
7975 /* Setup host coalescing engine. */
7976 tw32(HOSTCC_MODE, 0);
7977 for (i = 0; i < 2000; i++) {
7978 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
7983 __tg3_set_coalesce(tp, &tp->coal);
7985 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7986 /* Status/statistics block address. See tg3_timer,
7987 * the tg3_periodic_fetch_stats call there, and
7988 * tg3_get_stats to see how this works for 5705/5750 chips.
7990 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7991 ((u64) tp->stats_mapping >> 32));
7992 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7993 ((u64) tp->stats_mapping & 0xffffffff));
7994 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
7996 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
7998 /* Clear statistics and status block memory areas */
7999 for (i = NIC_SRAM_STATS_BLK;
8000 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
8002 tg3_write_mem(tp, i, 0);
8007 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
8009 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
8010 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
8011 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8012 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
8014 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
8015 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
8016 /* reset to prevent losing 1st rx packet intermittently */
8017 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8021 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
8022 tp->mac_mode &= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
8025 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
8026 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
8027 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
8028 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
8029 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
8030 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
8031 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
8034 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
8035 * If TG3_FLG2_IS_NIC is zero, we should read the
8036 * register to preserve the GPIO settings for LOMs. The GPIOs,
8037 * whether used as inputs or outputs, are set by boot code after
8040 if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
8043 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
8044 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
8045 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
8047 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
8048 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
8049 GRC_LCLCTRL_GPIO_OUTPUT3;
8051 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
8052 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
8054 tp->grc_local_ctrl &= ~gpio_mask;
8055 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
8057 /* GPIO1 must be driven high for eeprom write protect */
8058 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
8059 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
8060 GRC_LCLCTRL_GPIO_OUTPUT1);
8062 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8065 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX) {
8066 val = tr32(MSGINT_MODE);
8067 val |= MSGINT_MODE_MULTIVEC_EN | MSGINT_MODE_ENABLE;
8068 tw32(MSGINT_MODE, val);
8071 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
8072 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
8076 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
8077 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
8078 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
8079 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
8080 WDMAC_MODE_LNGREAD_ENAB);
8082 /* If statement applies to 5705 and 5750 PCI devices only */
8083 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
8084 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
8085 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
8086 if ((tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
8087 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
8088 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
8090 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
8091 !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
8092 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
8093 val |= WDMAC_MODE_RX_ACCEL;
8097 /* Enable host coalescing bug fix */
8098 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
8099 val |= WDMAC_MODE_STATUS_TAG_FIX;
8101 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
8102 val |= WDMAC_MODE_BURST_ALL_DATA;
8104 tw32_f(WDMAC_MODE, val);
8107 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
8110 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8112 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
8113 pcix_cmd &= ~PCI_X_CMD_MAX_READ;
8114 pcix_cmd |= PCI_X_CMD_READ_2K;
8115 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
8116 pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
8117 pcix_cmd |= PCI_X_CMD_READ_2K;
8119 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8123 tw32_f(RDMAC_MODE, rdmac_mode);
8126 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
8127 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8128 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
8130 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
8132 SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
8134 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
8136 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
8137 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
8138 tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
8139 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
8140 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
8141 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
8142 val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
8143 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
8144 val |= SNDBDI_MODE_MULTI_TXQ_EN;
8145 tw32(SNDBDI_MODE, val);
8146 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
8148 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8149 err = tg3_load_5701_a0_firmware_fix(tp);
8154 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
8155 err = tg3_load_tso_firmware(tp);
8160 tp->tx_mode = TX_MODE_ENABLE;
8161 tw32_f(MAC_TX_MODE, tp->tx_mode);
8164 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) {
8165 u32 reg = MAC_RSS_INDIR_TBL_0;
8166 u8 *ent = (u8 *)&val;
8168 /* Setup the indirection table */
8169 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
8170 int idx = i % sizeof(val);
8172 ent[idx] = i % (tp->irq_cnt - 1);
8173 if (idx == sizeof(val) - 1) {
8179 /* Setup the "secret" hash key. */
8180 tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
8181 tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
8182 tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
8183 tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
8184 tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
8185 tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
8186 tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
8187 tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
8188 tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
8189 tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
8192 tp->rx_mode = RX_MODE_ENABLE;
8193 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
8194 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
8196 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)
8197 tp->rx_mode |= RX_MODE_RSS_ENABLE |
8198 RX_MODE_RSS_ITBL_HASH_BITS_7 |
8199 RX_MODE_RSS_IPV6_HASH_EN |
8200 RX_MODE_RSS_TCP_IPV6_HASH_EN |
8201 RX_MODE_RSS_IPV4_HASH_EN |
8202 RX_MODE_RSS_TCP_IPV4_HASH_EN;
8204 tw32_f(MAC_RX_MODE, tp->rx_mode);
8207 tw32(MAC_LED_CTRL, tp->led_ctrl);
8209 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
8210 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
8211 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8214 tw32_f(MAC_RX_MODE, tp->rx_mode);
8217 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
8218 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
8219 !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
8220 /* Set drive transmission level to 1.2V */
8221 /* only if the signal pre-emphasis bit is not set */
8222 val = tr32(MAC_SERDES_CFG);
8225 tw32(MAC_SERDES_CFG, val);
8227 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
8228 tw32(MAC_SERDES_CFG, 0x616000);
8231 /* Prevent chip from dropping frames when flow control
8234 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
8238 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val);
8240 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
8241 (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
8242 /* Use hardware link auto-negotiation */
8243 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
8246 if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
8247 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
8250 tmp = tr32(SERDES_RX_CTRL);
8251 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
8252 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
8253 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
8254 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8257 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
8258 if (tp->link_config.phy_is_low_power) {
8259 tp->link_config.phy_is_low_power = 0;
8260 tp->link_config.speed = tp->link_config.orig_speed;
8261 tp->link_config.duplex = tp->link_config.orig_duplex;
8262 tp->link_config.autoneg = tp->link_config.orig_autoneg;
8265 err = tg3_setup_phy(tp, 0);
8269 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
8270 !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)) {
8273 /* Clear CRC stats. */
8274 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
8275 tg3_writephy(tp, MII_TG3_TEST1,
8276 tmp | MII_TG3_TEST1_CRC_EN);
8277 tg3_readphy(tp, 0x14, &tmp);
8282 __tg3_set_rx_mode(tp->dev);
8284 /* Initialize receive rules. */
8285 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
8286 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
8287 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
8288 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
8290 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
8291 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
8295 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
8299 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
8301 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
8303 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
8305 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
8307 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
8309 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
8311 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
8313 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
8315 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
8317 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
8319 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
8321 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
8323 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
8325 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
8333 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
8334 /* Write our heartbeat update interval to APE. */
8335 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
8336 APE_HOST_HEARTBEAT_INT_DISABLE);
8338 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
8343 /* Called at device open time to get the chip ready for
8344 * packet processing. Invoked with tp->lock held.
8346 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
8348 tg3_switch_clocks(tp);
8350 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
8352 return tg3_reset_hw(tp, reset_phy);
8355 #define TG3_STAT_ADD32(PSTAT, REG) \
8356 do { u32 __val = tr32(REG); \
8357 (PSTAT)->low += __val; \
8358 if ((PSTAT)->low < __val) \
8359 (PSTAT)->high += 1; \
8362 static void tg3_periodic_fetch_stats(struct tg3 *tp)
8364 struct tg3_hw_stats *sp = tp->hw_stats;
8366 if (!netif_carrier_ok(tp->dev))
8369 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
8370 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
8371 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
8372 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
8373 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
8374 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
8375 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
8376 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
8377 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
8378 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
8379 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
8380 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
8381 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
8383 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
8384 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
8385 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
8386 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
8387 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
8388 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
8389 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
8390 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
8391 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
8392 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
8393 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
8394 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
8395 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
8396 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
8398 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
8399 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
8400 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
8403 static void tg3_timer(unsigned long __opaque)
8405 struct tg3 *tp = (struct tg3 *) __opaque;
8410 spin_lock(&tp->lock);
8412 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8413 /* All of this garbage is because when using non-tagged
8414 * IRQ status the mailbox/status_block protocol the chip
8415 * uses with the cpu is race prone.
8417 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
8418 tw32(GRC_LOCAL_CTRL,
8419 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
8421 tw32(HOSTCC_MODE, tp->coalesce_mode |
8422 HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
8425 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
8426 tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
8427 spin_unlock(&tp->lock);
8428 schedule_work(&tp->reset_task);
8433 /* This part only runs once per second. */
8434 if (!--tp->timer_counter) {
8435 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
8436 tg3_periodic_fetch_stats(tp);
8438 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
8442 mac_stat = tr32(MAC_STATUS);
8445 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
8446 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
8448 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
8452 tg3_setup_phy(tp, 0);
8453 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
8454 u32 mac_stat = tr32(MAC_STATUS);
8457 if (netif_carrier_ok(tp->dev) &&
8458 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
8461 if (! netif_carrier_ok(tp->dev) &&
8462 (mac_stat & (MAC_STATUS_PCS_SYNCED |
8463 MAC_STATUS_SIGNAL_DET))) {
8467 if (!tp->serdes_counter) {
8470 ~MAC_MODE_PORT_MODE_MASK));
8472 tw32_f(MAC_MODE, tp->mac_mode);
8475 tg3_setup_phy(tp, 0);
8477 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
8478 tg3_serdes_parallel_detect(tp);
8480 tp->timer_counter = tp->timer_multiplier;
8483 /* Heartbeat is only sent once every 2 seconds.
8485 * The heartbeat is to tell the ASF firmware that the host
8486 * driver is still alive. In the event that the OS crashes,
8487 * ASF needs to reset the hardware to free up the FIFO space
8488 * that may be filled with rx packets destined for the host.
8489 * If the FIFO is full, ASF will no longer function properly.
8491 * Unintended resets have been reported on real time kernels
8492 * where the timer doesn't run on time. Netpoll will also have
8495 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
8496 * to check the ring condition when the heartbeat is expiring
8497 * before doing the reset. This will prevent most unintended
8500 if (!--tp->asf_counter) {
8501 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
8502 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
8503 tg3_wait_for_event_ack(tp);
8505 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
8506 FWCMD_NICDRV_ALIVE3);
8507 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
8508 /* 5 seconds timeout */
8509 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
8511 tg3_generate_fw_event(tp);
8513 tp->asf_counter = tp->asf_multiplier;
8516 spin_unlock(&tp->lock);
8519 tp->timer.expires = jiffies + tp->timer_offset;
8520 add_timer(&tp->timer);
8523 static int tg3_request_irq(struct tg3 *tp, int irq_num)
8526 unsigned long flags;
8528 struct tg3_napi *tnapi = &tp->napi[irq_num];
8530 if (tp->irq_cnt == 1)
8531 name = tp->dev->name;
8533 name = &tnapi->irq_lbl[0];
8534 snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num);
8535 name[IFNAMSIZ-1] = 0;
8538 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8540 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
8542 flags = IRQF_SAMPLE_RANDOM;
8545 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8546 fn = tg3_interrupt_tagged;
8547 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
8550 return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
8553 static int tg3_test_interrupt(struct tg3 *tp)
8555 struct tg3_napi *tnapi = &tp->napi[0];
8556 struct net_device *dev = tp->dev;
8557 int err, i, intr_ok = 0;
8560 if (!netif_running(dev))
8563 tg3_disable_ints(tp);
8565 free_irq(tnapi->irq_vec, tnapi);
8568 * Turn off MSI one shot mode. Otherwise this test has no
8569 * observable way to know whether the interrupt was delivered.
8571 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
8572 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) &&
8573 (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8574 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
8575 tw32(MSGINT_MODE, val);
8578 err = request_irq(tnapi->irq_vec, tg3_test_isr,
8579 IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi);
8583 tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
8584 tg3_enable_ints(tp);
8586 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8589 for (i = 0; i < 5; i++) {
8590 u32 int_mbox, misc_host_ctrl;
8592 int_mbox = tr32_mailbox(tnapi->int_mbox);
8593 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
8595 if ((int_mbox != 0) ||
8596 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
8604 tg3_disable_ints(tp);
8606 free_irq(tnapi->irq_vec, tnapi);
8608 err = tg3_request_irq(tp, 0);
8614 /* Reenable MSI one shot mode. */
8615 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
8616 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) &&
8617 (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8618 val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
8619 tw32(MSGINT_MODE, val);
8627 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
8628 * successfully restored
8630 static int tg3_test_msi(struct tg3 *tp)
8635 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
8638 /* Turn off SERR reporting in case MSI terminates with Master
8641 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
8642 pci_write_config_word(tp->pdev, PCI_COMMAND,
8643 pci_cmd & ~PCI_COMMAND_SERR);
8645 err = tg3_test_interrupt(tp);
8647 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
8652 /* other failures */
8656 /* MSI test failed, go back to INTx mode */
8657 printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
8658 "switching to INTx mode. Please report this failure to "
8659 "the PCI maintainer and include system chipset information.\n",
8662 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8664 pci_disable_msi(tp->pdev);
8666 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8668 err = tg3_request_irq(tp, 0);
8672 /* Need to reset the chip because the MSI cycle may have terminated
8673 * with Master Abort.
8675 tg3_full_lock(tp, 1);
8677 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8678 err = tg3_init_hw(tp, 1);
8680 tg3_full_unlock(tp);
8683 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8688 static int tg3_request_firmware(struct tg3 *tp)
8690 const __be32 *fw_data;
8692 if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
8693 printk(KERN_ERR "%s: Failed to load firmware \"%s\"\n",
8694 tp->dev->name, tp->fw_needed);
8698 fw_data = (void *)tp->fw->data;
8700 /* Firmware blob starts with version numbers, followed by
8701 * start address and _full_ length including BSS sections
8702 * (which must be longer than the actual data, of course
8705 tp->fw_len = be32_to_cpu(fw_data[2]); /* includes bss */
8706 if (tp->fw_len < (tp->fw->size - 12)) {
8707 printk(KERN_ERR "%s: bogus length %d in \"%s\"\n",
8708 tp->dev->name, tp->fw_len, tp->fw_needed);
8709 release_firmware(tp->fw);
8714 /* We no longer need firmware; we have it. */
8715 tp->fw_needed = NULL;
8719 static bool tg3_enable_msix(struct tg3 *tp)
8721 int i, rc, cpus = num_online_cpus();
8722 struct msix_entry msix_ent[tp->irq_max];
8725 /* Just fallback to the simpler MSI mode. */
8729 * We want as many rx rings enabled as there are cpus.
8730 * The first MSIX vector only deals with link interrupts, etc,
8731 * so we add one to the number of vectors we are requesting.
8733 tp->irq_cnt = min_t(unsigned, cpus + 1, tp->irq_max);
8735 for (i = 0; i < tp->irq_max; i++) {
8736 msix_ent[i].entry = i;
8737 msix_ent[i].vector = 0;
8740 rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
8742 if (rc < TG3_RSS_MIN_NUM_MSIX_VECS)
8744 if (pci_enable_msix(tp->pdev, msix_ent, rc))
8747 "%s: Requested %d MSI-X vectors, received %d\n",
8748 tp->dev->name, tp->irq_cnt, rc);
8752 tp->tg3_flags3 |= TG3_FLG3_ENABLE_RSS;
8754 for (i = 0; i < tp->irq_max; i++)
8755 tp->napi[i].irq_vec = msix_ent[i].vector;
8757 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
8758 tp->tg3_flags3 |= TG3_FLG3_ENABLE_TSS;
8759 tp->dev->real_num_tx_queues = tp->irq_cnt - 1;
8761 tp->dev->real_num_tx_queues = 1;
8766 static void tg3_ints_init(struct tg3 *tp)
8768 if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI_OR_MSIX) &&
8769 !(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8770 /* All MSI supporting chips should support tagged
8771 * status. Assert that this is the case.
8773 printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
8774 "Not using MSI.\n", tp->dev->name);
8778 if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) && tg3_enable_msix(tp))
8779 tp->tg3_flags2 |= TG3_FLG2_USING_MSIX;
8780 else if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) &&
8781 pci_enable_msi(tp->pdev) == 0)
8782 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
8784 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8785 u32 msi_mode = tr32(MSGINT_MODE);
8786 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8787 msi_mode |= MSGINT_MODE_MULTIVEC_EN;
8788 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
8791 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
8793 tp->napi[0].irq_vec = tp->pdev->irq;
8794 tp->dev->real_num_tx_queues = 1;
8798 static void tg3_ints_fini(struct tg3 *tp)
8800 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8801 pci_disable_msix(tp->pdev);
8802 else if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
8803 pci_disable_msi(tp->pdev);
8804 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI_OR_MSIX;
8805 tp->tg3_flags3 &= ~TG3_FLG3_ENABLE_RSS;
8808 static int tg3_open(struct net_device *dev)
8810 struct tg3 *tp = netdev_priv(dev);
8813 if (tp->fw_needed) {
8814 err = tg3_request_firmware(tp);
8815 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8819 printk(KERN_WARNING "%s: TSO capability disabled.\n",
8821 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
8822 } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8823 printk(KERN_NOTICE "%s: TSO capability restored.\n",
8825 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
8829 netif_carrier_off(tp->dev);
8831 err = tg3_set_power_state(tp, PCI_D0);
8835 tg3_full_lock(tp, 0);
8837 tg3_disable_ints(tp);
8838 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
8840 tg3_full_unlock(tp);
8843 * Setup interrupts first so we know how
8844 * many NAPI resources to allocate
8848 /* The placement of this call is tied
8849 * to the setup and use of Host TX descriptors.
8851 err = tg3_alloc_consistent(tp);
8855 tg3_napi_enable(tp);
8857 for (i = 0; i < tp->irq_cnt; i++) {
8858 struct tg3_napi *tnapi = &tp->napi[i];
8859 err = tg3_request_irq(tp, i);
8861 for (i--; i >= 0; i--)
8862 free_irq(tnapi->irq_vec, tnapi);
8870 tg3_full_lock(tp, 0);
8872 err = tg3_init_hw(tp, 1);
8874 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8877 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8878 tp->timer_offset = HZ;
8880 tp->timer_offset = HZ / 10;
8882 BUG_ON(tp->timer_offset > HZ);
8883 tp->timer_counter = tp->timer_multiplier =
8884 (HZ / tp->timer_offset);
8885 tp->asf_counter = tp->asf_multiplier =
8886 ((HZ / tp->timer_offset) * 2);
8888 init_timer(&tp->timer);
8889 tp->timer.expires = jiffies + tp->timer_offset;
8890 tp->timer.data = (unsigned long) tp;
8891 tp->timer.function = tg3_timer;
8894 tg3_full_unlock(tp);
8899 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8900 err = tg3_test_msi(tp);
8903 tg3_full_lock(tp, 0);
8904 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8906 tg3_full_unlock(tp);
8911 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
8912 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765 &&
8913 (tp->tg3_flags2 & TG3_FLG2_USING_MSI) &&
8914 (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)) {
8915 u32 val = tr32(PCIE_TRANSACTION_CFG);
8917 tw32(PCIE_TRANSACTION_CFG,
8918 val | PCIE_TRANS_CFG_1SHOT_MSI);
8924 tg3_full_lock(tp, 0);
8926 add_timer(&tp->timer);
8927 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
8928 tg3_enable_ints(tp);
8930 tg3_full_unlock(tp);
8932 netif_tx_start_all_queues(dev);
8937 for (i = tp->irq_cnt - 1; i >= 0; i--) {
8938 struct tg3_napi *tnapi = &tp->napi[i];
8939 free_irq(tnapi->irq_vec, tnapi);
8943 tg3_napi_disable(tp);
8944 tg3_free_consistent(tp);
8952 /*static*/ void tg3_dump_state(struct tg3 *tp)
8954 u32 val32, val32_2, val32_3, val32_4, val32_5;
8957 struct tg3_hw_status *sblk = tp->napi[0]->hw_status;
8959 pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
8960 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
8961 printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
8965 printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
8966 tr32(MAC_MODE), tr32(MAC_STATUS));
8967 printk(" MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
8968 tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
8969 printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
8970 tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
8971 printk(" MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
8972 tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
8974 /* Send data initiator control block */
8975 printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
8976 tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
8977 printk(" SNDDATAI_STATSCTRL[%08x]\n",
8978 tr32(SNDDATAI_STATSCTRL));
8980 /* Send data completion control block */
8981 printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
8983 /* Send BD ring selector block */
8984 printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
8985 tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
8987 /* Send BD initiator control block */
8988 printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
8989 tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
8991 /* Send BD completion control block */
8992 printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
8994 /* Receive list placement control block */
8995 printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
8996 tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
8997 printk(" RCVLPC_STATSCTRL[%08x]\n",
8998 tr32(RCVLPC_STATSCTRL));
9000 /* Receive data and receive BD initiator control block */
9001 printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
9002 tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
9004 /* Receive data completion control block */
9005 printk("DEBUG: RCVDCC_MODE[%08x]\n",
9008 /* Receive BD initiator control block */
9009 printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
9010 tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
9012 /* Receive BD completion control block */
9013 printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
9014 tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
9016 /* Receive list selector control block */
9017 printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
9018 tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
9020 /* Mbuf cluster free block */
9021 printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
9022 tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
9024 /* Host coalescing control block */
9025 printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
9026 tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
9027 printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
9028 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
9029 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
9030 printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
9031 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
9032 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
9033 printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
9034 tr32(HOSTCC_STATS_BLK_NIC_ADDR));
9035 printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
9036 tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
9038 /* Memory arbiter control block */
9039 printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
9040 tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
9042 /* Buffer manager control block */
9043 printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
9044 tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
9045 printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
9046 tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
9047 printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
9048 "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
9049 tr32(BUFMGR_DMA_DESC_POOL_ADDR),
9050 tr32(BUFMGR_DMA_DESC_POOL_SIZE));
9052 /* Read DMA control block */
9053 printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
9054 tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
9056 /* Write DMA control block */
9057 printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
9058 tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
9060 /* DMA completion block */
9061 printk("DEBUG: DMAC_MODE[%08x]\n",
9065 printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
9066 tr32(GRC_MODE), tr32(GRC_MISC_CFG));
9067 printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
9068 tr32(GRC_LOCAL_CTRL));
9071 printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
9072 tr32(RCVDBDI_JUMBO_BD + 0x0),
9073 tr32(RCVDBDI_JUMBO_BD + 0x4),
9074 tr32(RCVDBDI_JUMBO_BD + 0x8),
9075 tr32(RCVDBDI_JUMBO_BD + 0xc));
9076 printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
9077 tr32(RCVDBDI_STD_BD + 0x0),
9078 tr32(RCVDBDI_STD_BD + 0x4),
9079 tr32(RCVDBDI_STD_BD + 0x8),
9080 tr32(RCVDBDI_STD_BD + 0xc));
9081 printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
9082 tr32(RCVDBDI_MINI_BD + 0x0),
9083 tr32(RCVDBDI_MINI_BD + 0x4),
9084 tr32(RCVDBDI_MINI_BD + 0x8),
9085 tr32(RCVDBDI_MINI_BD + 0xc));
9087 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
9088 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
9089 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
9090 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
9091 printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
9092 val32, val32_2, val32_3, val32_4);
9094 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
9095 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
9096 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
9097 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
9098 printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
9099 val32, val32_2, val32_3, val32_4);
9101 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
9102 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
9103 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
9104 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
9105 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
9106 printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
9107 val32, val32_2, val32_3, val32_4, val32_5);
9109 /* SW status block */
9111 "Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
9114 sblk->rx_jumbo_consumer,
9116 sblk->rx_mini_consumer,
9117 sblk->idx[0].rx_producer,
9118 sblk->idx[0].tx_consumer);
9120 /* SW statistics block */
9121 printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
9122 ((u32 *)tp->hw_stats)[0],
9123 ((u32 *)tp->hw_stats)[1],
9124 ((u32 *)tp->hw_stats)[2],
9125 ((u32 *)tp->hw_stats)[3]);
9128 printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
9129 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
9130 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
9131 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
9132 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
9134 /* NIC side send descriptors. */
9135 for (i = 0; i < 6; i++) {
9138 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
9139 + (i * sizeof(struct tg3_tx_buffer_desc));
9140 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
9142 readl(txd + 0x0), readl(txd + 0x4),
9143 readl(txd + 0x8), readl(txd + 0xc));
9146 /* NIC side RX descriptors. */
9147 for (i = 0; i < 6; i++) {
9150 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
9151 + (i * sizeof(struct tg3_rx_buffer_desc));
9152 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
9154 readl(rxd + 0x0), readl(rxd + 0x4),
9155 readl(rxd + 0x8), readl(rxd + 0xc));
9156 rxd += (4 * sizeof(u32));
9157 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
9159 readl(rxd + 0x0), readl(rxd + 0x4),
9160 readl(rxd + 0x8), readl(rxd + 0xc));
9163 for (i = 0; i < 6; i++) {
9166 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
9167 + (i * sizeof(struct tg3_rx_buffer_desc));
9168 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
9170 readl(rxd + 0x0), readl(rxd + 0x4),
9171 readl(rxd + 0x8), readl(rxd + 0xc));
9172 rxd += (4 * sizeof(u32));
9173 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
9175 readl(rxd + 0x0), readl(rxd + 0x4),
9176 readl(rxd + 0x8), readl(rxd + 0xc));
9181 static struct net_device_stats *tg3_get_stats(struct net_device *);
9182 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
9184 static int tg3_close(struct net_device *dev)
9187 struct tg3 *tp = netdev_priv(dev);
9189 tg3_napi_disable(tp);
9190 cancel_work_sync(&tp->reset_task);
9192 netif_tx_stop_all_queues(dev);
9194 del_timer_sync(&tp->timer);
9198 tg3_full_lock(tp, 1);
9203 tg3_disable_ints(tp);
9205 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9207 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
9209 tg3_full_unlock(tp);
9211 for (i = tp->irq_cnt - 1; i >= 0; i--) {
9212 struct tg3_napi *tnapi = &tp->napi[i];
9213 free_irq(tnapi->irq_vec, tnapi);
9218 memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
9219 sizeof(tp->net_stats_prev));
9220 memcpy(&tp->estats_prev, tg3_get_estats(tp),
9221 sizeof(tp->estats_prev));
9223 tg3_free_consistent(tp);
9225 tg3_set_power_state(tp, PCI_D3hot);
9227 netif_carrier_off(tp->dev);
9232 static inline unsigned long get_stat64(tg3_stat64_t *val)
9236 #if (BITS_PER_LONG == 32)
9239 ret = ((u64)val->high << 32) | ((u64)val->low);
9244 static inline u64 get_estat64(tg3_stat64_t *val)
9246 return ((u64)val->high << 32) | ((u64)val->low);
9249 static unsigned long calc_crc_errors(struct tg3 *tp)
9251 struct tg3_hw_stats *hw_stats = tp->hw_stats;
9253 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
9254 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
9255 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
9258 spin_lock_bh(&tp->lock);
9259 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
9260 tg3_writephy(tp, MII_TG3_TEST1,
9261 val | MII_TG3_TEST1_CRC_EN);
9262 tg3_readphy(tp, 0x14, &val);
9265 spin_unlock_bh(&tp->lock);
9267 tp->phy_crc_errors += val;
9269 return tp->phy_crc_errors;
9272 return get_stat64(&hw_stats->rx_fcs_errors);
9275 #define ESTAT_ADD(member) \
9276 estats->member = old_estats->member + \
9277 get_estat64(&hw_stats->member)
9279 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
9281 struct tg3_ethtool_stats *estats = &tp->estats;
9282 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
9283 struct tg3_hw_stats *hw_stats = tp->hw_stats;
9288 ESTAT_ADD(rx_octets);
9289 ESTAT_ADD(rx_fragments);
9290 ESTAT_ADD(rx_ucast_packets);
9291 ESTAT_ADD(rx_mcast_packets);
9292 ESTAT_ADD(rx_bcast_packets);
9293 ESTAT_ADD(rx_fcs_errors);
9294 ESTAT_ADD(rx_align_errors);
9295 ESTAT_ADD(rx_xon_pause_rcvd);
9296 ESTAT_ADD(rx_xoff_pause_rcvd);
9297 ESTAT_ADD(rx_mac_ctrl_rcvd);
9298 ESTAT_ADD(rx_xoff_entered);
9299 ESTAT_ADD(rx_frame_too_long_errors);
9300 ESTAT_ADD(rx_jabbers);
9301 ESTAT_ADD(rx_undersize_packets);
9302 ESTAT_ADD(rx_in_length_errors);
9303 ESTAT_ADD(rx_out_length_errors);
9304 ESTAT_ADD(rx_64_or_less_octet_packets);
9305 ESTAT_ADD(rx_65_to_127_octet_packets);
9306 ESTAT_ADD(rx_128_to_255_octet_packets);
9307 ESTAT_ADD(rx_256_to_511_octet_packets);
9308 ESTAT_ADD(rx_512_to_1023_octet_packets);
9309 ESTAT_ADD(rx_1024_to_1522_octet_packets);
9310 ESTAT_ADD(rx_1523_to_2047_octet_packets);
9311 ESTAT_ADD(rx_2048_to_4095_octet_packets);
9312 ESTAT_ADD(rx_4096_to_8191_octet_packets);
9313 ESTAT_ADD(rx_8192_to_9022_octet_packets);
9315 ESTAT_ADD(tx_octets);
9316 ESTAT_ADD(tx_collisions);
9317 ESTAT_ADD(tx_xon_sent);
9318 ESTAT_ADD(tx_xoff_sent);
9319 ESTAT_ADD(tx_flow_control);
9320 ESTAT_ADD(tx_mac_errors);
9321 ESTAT_ADD(tx_single_collisions);
9322 ESTAT_ADD(tx_mult_collisions);
9323 ESTAT_ADD(tx_deferred);
9324 ESTAT_ADD(tx_excessive_collisions);
9325 ESTAT_ADD(tx_late_collisions);
9326 ESTAT_ADD(tx_collide_2times);
9327 ESTAT_ADD(tx_collide_3times);
9328 ESTAT_ADD(tx_collide_4times);
9329 ESTAT_ADD(tx_collide_5times);
9330 ESTAT_ADD(tx_collide_6times);
9331 ESTAT_ADD(tx_collide_7times);
9332 ESTAT_ADD(tx_collide_8times);
9333 ESTAT_ADD(tx_collide_9times);
9334 ESTAT_ADD(tx_collide_10times);
9335 ESTAT_ADD(tx_collide_11times);
9336 ESTAT_ADD(tx_collide_12times);
9337 ESTAT_ADD(tx_collide_13times);
9338 ESTAT_ADD(tx_collide_14times);
9339 ESTAT_ADD(tx_collide_15times);
9340 ESTAT_ADD(tx_ucast_packets);
9341 ESTAT_ADD(tx_mcast_packets);
9342 ESTAT_ADD(tx_bcast_packets);
9343 ESTAT_ADD(tx_carrier_sense_errors);
9344 ESTAT_ADD(tx_discards);
9345 ESTAT_ADD(tx_errors);
9347 ESTAT_ADD(dma_writeq_full);
9348 ESTAT_ADD(dma_write_prioq_full);
9349 ESTAT_ADD(rxbds_empty);
9350 ESTAT_ADD(rx_discards);
9351 ESTAT_ADD(rx_errors);
9352 ESTAT_ADD(rx_threshold_hit);
9354 ESTAT_ADD(dma_readq_full);
9355 ESTAT_ADD(dma_read_prioq_full);
9356 ESTAT_ADD(tx_comp_queue_full);
9358 ESTAT_ADD(ring_set_send_prod_index);
9359 ESTAT_ADD(ring_status_update);
9360 ESTAT_ADD(nic_irqs);
9361 ESTAT_ADD(nic_avoided_irqs);
9362 ESTAT_ADD(nic_tx_threshold_hit);
9367 static struct net_device_stats *tg3_get_stats(struct net_device *dev)
9369 struct tg3 *tp = netdev_priv(dev);
9370 struct net_device_stats *stats = &tp->net_stats;
9371 struct net_device_stats *old_stats = &tp->net_stats_prev;
9372 struct tg3_hw_stats *hw_stats = tp->hw_stats;
9377 stats->rx_packets = old_stats->rx_packets +
9378 get_stat64(&hw_stats->rx_ucast_packets) +
9379 get_stat64(&hw_stats->rx_mcast_packets) +
9380 get_stat64(&hw_stats->rx_bcast_packets);
9382 stats->tx_packets = old_stats->tx_packets +
9383 get_stat64(&hw_stats->tx_ucast_packets) +
9384 get_stat64(&hw_stats->tx_mcast_packets) +
9385 get_stat64(&hw_stats->tx_bcast_packets);
9387 stats->rx_bytes = old_stats->rx_bytes +
9388 get_stat64(&hw_stats->rx_octets);
9389 stats->tx_bytes = old_stats->tx_bytes +
9390 get_stat64(&hw_stats->tx_octets);
9392 stats->rx_errors = old_stats->rx_errors +
9393 get_stat64(&hw_stats->rx_errors);
9394 stats->tx_errors = old_stats->tx_errors +
9395 get_stat64(&hw_stats->tx_errors) +
9396 get_stat64(&hw_stats->tx_mac_errors) +
9397 get_stat64(&hw_stats->tx_carrier_sense_errors) +
9398 get_stat64(&hw_stats->tx_discards);
9400 stats->multicast = old_stats->multicast +
9401 get_stat64(&hw_stats->rx_mcast_packets);
9402 stats->collisions = old_stats->collisions +
9403 get_stat64(&hw_stats->tx_collisions);
9405 stats->rx_length_errors = old_stats->rx_length_errors +
9406 get_stat64(&hw_stats->rx_frame_too_long_errors) +
9407 get_stat64(&hw_stats->rx_undersize_packets);
9409 stats->rx_over_errors = old_stats->rx_over_errors +
9410 get_stat64(&hw_stats->rxbds_empty);
9411 stats->rx_frame_errors = old_stats->rx_frame_errors +
9412 get_stat64(&hw_stats->rx_align_errors);
9413 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
9414 get_stat64(&hw_stats->tx_discards);
9415 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
9416 get_stat64(&hw_stats->tx_carrier_sense_errors);
9418 stats->rx_crc_errors = old_stats->rx_crc_errors +
9419 calc_crc_errors(tp);
9421 stats->rx_missed_errors = old_stats->rx_missed_errors +
9422 get_stat64(&hw_stats->rx_discards);
9427 static inline u32 calc_crc(unsigned char *buf, int len)
9435 for (j = 0; j < len; j++) {
9438 for (k = 0; k < 8; k++) {
9452 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
9454 /* accept or reject all multicast frames */
9455 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
9456 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
9457 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
9458 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
9461 static void __tg3_set_rx_mode(struct net_device *dev)
9463 struct tg3 *tp = netdev_priv(dev);
9466 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
9467 RX_MODE_KEEP_VLAN_TAG);
9469 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
9472 #if TG3_VLAN_TAG_USED
9474 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9475 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9477 /* By definition, VLAN is disabled always in this
9480 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9481 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9484 if (dev->flags & IFF_PROMISC) {
9485 /* Promiscuous mode. */
9486 rx_mode |= RX_MODE_PROMISC;
9487 } else if (dev->flags & IFF_ALLMULTI) {
9488 /* Accept all multicast. */
9489 tg3_set_multi (tp, 1);
9490 } else if (netdev_mc_empty(dev)) {
9491 /* Reject all multicast. */
9492 tg3_set_multi (tp, 0);
9494 /* Accept one or more multicast(s). */
9495 struct dev_mc_list *mclist;
9497 u32 mc_filter[4] = { 0, };
9502 for (i = 0, mclist = dev->mc_list; mclist && i < netdev_mc_count(dev);
9503 i++, mclist = mclist->next) {
9505 crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
9507 regidx = (bit & 0x60) >> 5;
9509 mc_filter[regidx] |= (1 << bit);
9512 tw32(MAC_HASH_REG_0, mc_filter[0]);
9513 tw32(MAC_HASH_REG_1, mc_filter[1]);
9514 tw32(MAC_HASH_REG_2, mc_filter[2]);
9515 tw32(MAC_HASH_REG_3, mc_filter[3]);
9518 if (rx_mode != tp->rx_mode) {
9519 tp->rx_mode = rx_mode;
9520 tw32_f(MAC_RX_MODE, rx_mode);
9525 static void tg3_set_rx_mode(struct net_device *dev)
9527 struct tg3 *tp = netdev_priv(dev);
9529 if (!netif_running(dev))
9532 tg3_full_lock(tp, 0);
9533 __tg3_set_rx_mode(dev);
9534 tg3_full_unlock(tp);
9537 #define TG3_REGDUMP_LEN (32 * 1024)
9539 static int tg3_get_regs_len(struct net_device *dev)
9541 return TG3_REGDUMP_LEN;
9544 static void tg3_get_regs(struct net_device *dev,
9545 struct ethtool_regs *regs, void *_p)
9548 struct tg3 *tp = netdev_priv(dev);
9554 memset(p, 0, TG3_REGDUMP_LEN);
9556 if (tp->link_config.phy_is_low_power)
9559 tg3_full_lock(tp, 0);
9561 #define __GET_REG32(reg) (*(p)++ = tr32(reg))
9562 #define GET_REG32_LOOP(base,len) \
9563 do { p = (u32 *)(orig_p + (base)); \
9564 for (i = 0; i < len; i += 4) \
9565 __GET_REG32((base) + i); \
9567 #define GET_REG32_1(reg) \
9568 do { p = (u32 *)(orig_p + (reg)); \
9569 __GET_REG32((reg)); \
9572 GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
9573 GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
9574 GET_REG32_LOOP(MAC_MODE, 0x4f0);
9575 GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
9576 GET_REG32_1(SNDDATAC_MODE);
9577 GET_REG32_LOOP(SNDBDS_MODE, 0x80);
9578 GET_REG32_LOOP(SNDBDI_MODE, 0x48);
9579 GET_REG32_1(SNDBDC_MODE);
9580 GET_REG32_LOOP(RCVLPC_MODE, 0x20);
9581 GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
9582 GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
9583 GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
9584 GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
9585 GET_REG32_1(RCVDCC_MODE);
9586 GET_REG32_LOOP(RCVBDI_MODE, 0x20);
9587 GET_REG32_LOOP(RCVCC_MODE, 0x14);
9588 GET_REG32_LOOP(RCVLSC_MODE, 0x08);
9589 GET_REG32_1(MBFREE_MODE);
9590 GET_REG32_LOOP(HOSTCC_MODE, 0x100);
9591 GET_REG32_LOOP(MEMARB_MODE, 0x10);
9592 GET_REG32_LOOP(BUFMGR_MODE, 0x58);
9593 GET_REG32_LOOP(RDMAC_MODE, 0x08);
9594 GET_REG32_LOOP(WDMAC_MODE, 0x08);
9595 GET_REG32_1(RX_CPU_MODE);
9596 GET_REG32_1(RX_CPU_STATE);
9597 GET_REG32_1(RX_CPU_PGMCTR);
9598 GET_REG32_1(RX_CPU_HWBKPT);
9599 GET_REG32_1(TX_CPU_MODE);
9600 GET_REG32_1(TX_CPU_STATE);
9601 GET_REG32_1(TX_CPU_PGMCTR);
9602 GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
9603 GET_REG32_LOOP(FTQ_RESET, 0x120);
9604 GET_REG32_LOOP(MSGINT_MODE, 0x0c);
9605 GET_REG32_1(DMAC_MODE);
9606 GET_REG32_LOOP(GRC_MODE, 0x4c);
9607 if (tp->tg3_flags & TG3_FLAG_NVRAM)
9608 GET_REG32_LOOP(NVRAM_CMD, 0x24);
9611 #undef GET_REG32_LOOP
9614 tg3_full_unlock(tp);
9617 static int tg3_get_eeprom_len(struct net_device *dev)
9619 struct tg3 *tp = netdev_priv(dev);
9621 return tp->nvram_size;
9624 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9626 struct tg3 *tp = netdev_priv(dev);
9629 u32 i, offset, len, b_offset, b_count;
9632 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9635 if (tp->link_config.phy_is_low_power)
9638 offset = eeprom->offset;
9642 eeprom->magic = TG3_EEPROM_MAGIC;
9645 /* adjustments to start on required 4 byte boundary */
9646 b_offset = offset & 3;
9647 b_count = 4 - b_offset;
9648 if (b_count > len) {
9649 /* i.e. offset=1 len=2 */
9652 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
9655 memcpy(data, ((char*)&val) + b_offset, b_count);
9658 eeprom->len += b_count;
9661 /* read bytes upto the last 4 byte boundary */
9662 pd = &data[eeprom->len];
9663 for (i = 0; i < (len - (len & 3)); i += 4) {
9664 ret = tg3_nvram_read_be32(tp, offset + i, &val);
9669 memcpy(pd + i, &val, 4);
9674 /* read last bytes not ending on 4 byte boundary */
9675 pd = &data[eeprom->len];
9677 b_offset = offset + len - b_count;
9678 ret = tg3_nvram_read_be32(tp, b_offset, &val);
9681 memcpy(pd, &val, b_count);
9682 eeprom->len += b_count;
9687 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
9689 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9691 struct tg3 *tp = netdev_priv(dev);
9693 u32 offset, len, b_offset, odd_len;
9697 if (tp->link_config.phy_is_low_power)
9700 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
9701 eeprom->magic != TG3_EEPROM_MAGIC)
9704 offset = eeprom->offset;
9707 if ((b_offset = (offset & 3))) {
9708 /* adjustments to start on required 4 byte boundary */
9709 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
9720 /* adjustments to end on required 4 byte boundary */
9722 len = (len + 3) & ~3;
9723 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
9729 if (b_offset || odd_len) {
9730 buf = kmalloc(len, GFP_KERNEL);
9734 memcpy(buf, &start, 4);
9736 memcpy(buf+len-4, &end, 4);
9737 memcpy(buf + b_offset, data, eeprom->len);
9740 ret = tg3_nvram_write_block(tp, offset, len, buf);
9748 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9750 struct tg3 *tp = netdev_priv(dev);
9752 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9753 struct phy_device *phydev;
9754 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9756 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9757 return phy_ethtool_gset(phydev, cmd);
9760 cmd->supported = (SUPPORTED_Autoneg);
9762 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
9763 cmd->supported |= (SUPPORTED_1000baseT_Half |
9764 SUPPORTED_1000baseT_Full);
9766 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
9767 cmd->supported |= (SUPPORTED_100baseT_Half |
9768 SUPPORTED_100baseT_Full |
9769 SUPPORTED_10baseT_Half |
9770 SUPPORTED_10baseT_Full |
9772 cmd->port = PORT_TP;
9774 cmd->supported |= SUPPORTED_FIBRE;
9775 cmd->port = PORT_FIBRE;
9778 cmd->advertising = tp->link_config.advertising;
9779 if (netif_running(dev)) {
9780 cmd->speed = tp->link_config.active_speed;
9781 cmd->duplex = tp->link_config.active_duplex;
9783 cmd->phy_address = tp->phy_addr;
9784 cmd->transceiver = XCVR_INTERNAL;
9785 cmd->autoneg = tp->link_config.autoneg;
9791 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9793 struct tg3 *tp = netdev_priv(dev);
9795 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9796 struct phy_device *phydev;
9797 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9799 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9800 return phy_ethtool_sset(phydev, cmd);
9803 if (cmd->autoneg != AUTONEG_ENABLE &&
9804 cmd->autoneg != AUTONEG_DISABLE)
9807 if (cmd->autoneg == AUTONEG_DISABLE &&
9808 cmd->duplex != DUPLEX_FULL &&
9809 cmd->duplex != DUPLEX_HALF)
9812 if (cmd->autoneg == AUTONEG_ENABLE) {
9813 u32 mask = ADVERTISED_Autoneg |
9815 ADVERTISED_Asym_Pause;
9817 if (!(tp->tg3_flags2 & TG3_FLAG_10_100_ONLY))
9818 mask |= ADVERTISED_1000baseT_Half |
9819 ADVERTISED_1000baseT_Full;
9821 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
9822 mask |= ADVERTISED_100baseT_Half |
9823 ADVERTISED_100baseT_Full |
9824 ADVERTISED_10baseT_Half |
9825 ADVERTISED_10baseT_Full |
9828 mask |= ADVERTISED_FIBRE;
9830 if (cmd->advertising & ~mask)
9833 mask &= (ADVERTISED_1000baseT_Half |
9834 ADVERTISED_1000baseT_Full |
9835 ADVERTISED_100baseT_Half |
9836 ADVERTISED_100baseT_Full |
9837 ADVERTISED_10baseT_Half |
9838 ADVERTISED_10baseT_Full);
9840 cmd->advertising &= mask;
9842 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
9843 if (cmd->speed != SPEED_1000)
9846 if (cmd->duplex != DUPLEX_FULL)
9849 if (cmd->speed != SPEED_100 &&
9850 cmd->speed != SPEED_10)
9855 tg3_full_lock(tp, 0);
9857 tp->link_config.autoneg = cmd->autoneg;
9858 if (cmd->autoneg == AUTONEG_ENABLE) {
9859 tp->link_config.advertising = (cmd->advertising |
9860 ADVERTISED_Autoneg);
9861 tp->link_config.speed = SPEED_INVALID;
9862 tp->link_config.duplex = DUPLEX_INVALID;
9864 tp->link_config.advertising = 0;
9865 tp->link_config.speed = cmd->speed;
9866 tp->link_config.duplex = cmd->duplex;
9869 tp->link_config.orig_speed = tp->link_config.speed;
9870 tp->link_config.orig_duplex = tp->link_config.duplex;
9871 tp->link_config.orig_autoneg = tp->link_config.autoneg;
9873 if (netif_running(dev))
9874 tg3_setup_phy(tp, 1);
9876 tg3_full_unlock(tp);
9881 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
9883 struct tg3 *tp = netdev_priv(dev);
9885 strcpy(info->driver, DRV_MODULE_NAME);
9886 strcpy(info->version, DRV_MODULE_VERSION);
9887 strcpy(info->fw_version, tp->fw_ver);
9888 strcpy(info->bus_info, pci_name(tp->pdev));
9891 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9893 struct tg3 *tp = netdev_priv(dev);
9895 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
9896 device_can_wakeup(&tp->pdev->dev))
9897 wol->supported = WAKE_MAGIC;
9901 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
9902 device_can_wakeup(&tp->pdev->dev))
9903 wol->wolopts = WAKE_MAGIC;
9904 memset(&wol->sopass, 0, sizeof(wol->sopass));
9907 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9909 struct tg3 *tp = netdev_priv(dev);
9910 struct device *dp = &tp->pdev->dev;
9912 if (wol->wolopts & ~WAKE_MAGIC)
9914 if ((wol->wolopts & WAKE_MAGIC) &&
9915 !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
9918 spin_lock_bh(&tp->lock);
9919 if (wol->wolopts & WAKE_MAGIC) {
9920 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
9921 device_set_wakeup_enable(dp, true);
9923 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
9924 device_set_wakeup_enable(dp, false);
9926 spin_unlock_bh(&tp->lock);
9931 static u32 tg3_get_msglevel(struct net_device *dev)
9933 struct tg3 *tp = netdev_priv(dev);
9934 return tp->msg_enable;
9937 static void tg3_set_msglevel(struct net_device *dev, u32 value)
9939 struct tg3 *tp = netdev_priv(dev);
9940 tp->msg_enable = value;
9943 static int tg3_set_tso(struct net_device *dev, u32 value)
9945 struct tg3 *tp = netdev_priv(dev);
9947 if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
9952 if ((dev->features & NETIF_F_IPV6_CSUM) &&
9953 ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
9954 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3))) {
9956 dev->features |= NETIF_F_TSO6;
9957 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
9958 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9959 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
9960 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
9961 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
9962 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
9963 dev->features |= NETIF_F_TSO_ECN;
9965 dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
9967 return ethtool_op_set_tso(dev, value);
9970 static int tg3_nway_reset(struct net_device *dev)
9972 struct tg3 *tp = netdev_priv(dev);
9975 if (!netif_running(dev))
9978 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9981 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9982 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9984 r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
9988 spin_lock_bh(&tp->lock);
9990 tg3_readphy(tp, MII_BMCR, &bmcr);
9991 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
9992 ((bmcr & BMCR_ANENABLE) ||
9993 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
9994 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
9998 spin_unlock_bh(&tp->lock);
10004 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
10006 struct tg3 *tp = netdev_priv(dev);
10008 ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
10009 ering->rx_mini_max_pending = 0;
10010 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
10011 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
10013 ering->rx_jumbo_max_pending = 0;
10015 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
10017 ering->rx_pending = tp->rx_pending;
10018 ering->rx_mini_pending = 0;
10019 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
10020 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
10022 ering->rx_jumbo_pending = 0;
10024 ering->tx_pending = tp->napi[0].tx_pending;
10027 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
10029 struct tg3 *tp = netdev_priv(dev);
10030 int i, irq_sync = 0, err = 0;
10032 if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
10033 (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
10034 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
10035 (ering->tx_pending <= MAX_SKB_FRAGS) ||
10036 ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
10037 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
10040 if (netif_running(dev)) {
10042 tg3_netif_stop(tp);
10046 tg3_full_lock(tp, irq_sync);
10048 tp->rx_pending = ering->rx_pending;
10050 if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
10051 tp->rx_pending > 63)
10052 tp->rx_pending = 63;
10053 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
10055 for (i = 0; i < TG3_IRQ_MAX_VECS; i++)
10056 tp->napi[i].tx_pending = ering->tx_pending;
10058 if (netif_running(dev)) {
10059 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10060 err = tg3_restart_hw(tp, 1);
10062 tg3_netif_start(tp);
10065 tg3_full_unlock(tp);
10067 if (irq_sync && !err)
10073 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
10075 struct tg3 *tp = netdev_priv(dev);
10077 epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
10079 if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
10080 epause->rx_pause = 1;
10082 epause->rx_pause = 0;
10084 if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
10085 epause->tx_pause = 1;
10087 epause->tx_pause = 0;
10090 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
10092 struct tg3 *tp = netdev_priv(dev);
10095 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
10097 struct phy_device *phydev;
10099 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
10101 if (!(phydev->supported & SUPPORTED_Pause) ||
10102 (!(phydev->supported & SUPPORTED_Asym_Pause) &&
10103 ((epause->rx_pause && !epause->tx_pause) ||
10104 (!epause->rx_pause && epause->tx_pause))))
10107 tp->link_config.flowctrl = 0;
10108 if (epause->rx_pause) {
10109 tp->link_config.flowctrl |= FLOW_CTRL_RX;
10111 if (epause->tx_pause) {
10112 tp->link_config.flowctrl |= FLOW_CTRL_TX;
10113 newadv = ADVERTISED_Pause;
10115 newadv = ADVERTISED_Pause |
10116 ADVERTISED_Asym_Pause;
10117 } else if (epause->tx_pause) {
10118 tp->link_config.flowctrl |= FLOW_CTRL_TX;
10119 newadv = ADVERTISED_Asym_Pause;
10123 if (epause->autoneg)
10124 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
10126 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
10128 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
10129 u32 oldadv = phydev->advertising &
10130 (ADVERTISED_Pause | ADVERTISED_Asym_Pause);
10131 if (oldadv != newadv) {
10132 phydev->advertising &=
10133 ~(ADVERTISED_Pause |
10134 ADVERTISED_Asym_Pause);
10135 phydev->advertising |= newadv;
10136 if (phydev->autoneg) {
10138 * Always renegotiate the link to
10139 * inform our link partner of our
10140 * flow control settings, even if the
10141 * flow control is forced. Let
10142 * tg3_adjust_link() do the final
10143 * flow control setup.
10145 return phy_start_aneg(phydev);
10149 if (!epause->autoneg)
10150 tg3_setup_flow_control(tp, 0, 0);
10152 tp->link_config.orig_advertising &=
10153 ~(ADVERTISED_Pause |
10154 ADVERTISED_Asym_Pause);
10155 tp->link_config.orig_advertising |= newadv;
10160 if (netif_running(dev)) {
10161 tg3_netif_stop(tp);
10165 tg3_full_lock(tp, irq_sync);
10167 if (epause->autoneg)
10168 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
10170 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
10171 if (epause->rx_pause)
10172 tp->link_config.flowctrl |= FLOW_CTRL_RX;
10174 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
10175 if (epause->tx_pause)
10176 tp->link_config.flowctrl |= FLOW_CTRL_TX;
10178 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
10180 if (netif_running(dev)) {
10181 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10182 err = tg3_restart_hw(tp, 1);
10184 tg3_netif_start(tp);
10187 tg3_full_unlock(tp);
10193 static u32 tg3_get_rx_csum(struct net_device *dev)
10195 struct tg3 *tp = netdev_priv(dev);
10196 return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
10199 static int tg3_set_rx_csum(struct net_device *dev, u32 data)
10201 struct tg3 *tp = netdev_priv(dev);
10203 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
10209 spin_lock_bh(&tp->lock);
10211 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
10213 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
10214 spin_unlock_bh(&tp->lock);
10219 static int tg3_set_tx_csum(struct net_device *dev, u32 data)
10221 struct tg3 *tp = netdev_priv(dev);
10223 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
10229 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10230 ethtool_op_set_tx_ipv6_csum(dev, data);
10232 ethtool_op_set_tx_csum(dev, data);
10237 static int tg3_get_sset_count (struct net_device *dev, int sset)
10241 return TG3_NUM_TEST;
10243 return TG3_NUM_STATS;
10245 return -EOPNOTSUPP;
10249 static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
10251 switch (stringset) {
10253 memcpy(buf, ðtool_stats_keys, sizeof(ethtool_stats_keys));
10256 memcpy(buf, ðtool_test_keys, sizeof(ethtool_test_keys));
10259 WARN_ON(1); /* we need a WARN() */
10264 static int tg3_phys_id(struct net_device *dev, u32 data)
10266 struct tg3 *tp = netdev_priv(dev);
10269 if (!netif_running(tp->dev))
10273 data = UINT_MAX / 2;
10275 for (i = 0; i < (data * 2); i++) {
10277 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10278 LED_CTRL_1000MBPS_ON |
10279 LED_CTRL_100MBPS_ON |
10280 LED_CTRL_10MBPS_ON |
10281 LED_CTRL_TRAFFIC_OVERRIDE |
10282 LED_CTRL_TRAFFIC_BLINK |
10283 LED_CTRL_TRAFFIC_LED);
10286 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10287 LED_CTRL_TRAFFIC_OVERRIDE);
10289 if (msleep_interruptible(500))
10292 tw32(MAC_LED_CTRL, tp->led_ctrl);
10296 static void tg3_get_ethtool_stats (struct net_device *dev,
10297 struct ethtool_stats *estats, u64 *tmp_stats)
10299 struct tg3 *tp = netdev_priv(dev);
10300 memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
10303 #define NVRAM_TEST_SIZE 0x100
10304 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
10305 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
10306 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
10307 #define NVRAM_SELFBOOT_HW_SIZE 0x20
10308 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
10310 static int tg3_test_nvram(struct tg3 *tp)
10314 int i, j, k, err = 0, size;
10316 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
10319 if (tg3_nvram_read(tp, 0, &magic) != 0)
10322 if (magic == TG3_EEPROM_MAGIC)
10323 size = NVRAM_TEST_SIZE;
10324 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
10325 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
10326 TG3_EEPROM_SB_FORMAT_1) {
10327 switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
10328 case TG3_EEPROM_SB_REVISION_0:
10329 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
10331 case TG3_EEPROM_SB_REVISION_2:
10332 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
10334 case TG3_EEPROM_SB_REVISION_3:
10335 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
10342 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
10343 size = NVRAM_SELFBOOT_HW_SIZE;
10347 buf = kmalloc(size, GFP_KERNEL);
10352 for (i = 0, j = 0; i < size; i += 4, j++) {
10353 err = tg3_nvram_read_be32(tp, i, &buf[j]);
10360 /* Selfboot format */
10361 magic = be32_to_cpu(buf[0]);
10362 if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
10363 TG3_EEPROM_MAGIC_FW) {
10364 u8 *buf8 = (u8 *) buf, csum8 = 0;
10366 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
10367 TG3_EEPROM_SB_REVISION_2) {
10368 /* For rev 2, the csum doesn't include the MBA. */
10369 for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
10371 for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
10374 for (i = 0; i < size; i++)
10387 if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
10388 TG3_EEPROM_MAGIC_HW) {
10389 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
10390 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
10391 u8 *buf8 = (u8 *) buf;
10393 /* Separate the parity bits and the data bytes. */
10394 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
10395 if ((i == 0) || (i == 8)) {
10399 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
10400 parity[k++] = buf8[i] & msk;
10403 else if (i == 16) {
10407 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
10408 parity[k++] = buf8[i] & msk;
10411 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
10412 parity[k++] = buf8[i] & msk;
10415 data[j++] = buf8[i];
10419 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
10420 u8 hw8 = hweight8(data[i]);
10422 if ((hw8 & 0x1) && parity[i])
10424 else if (!(hw8 & 0x1) && !parity[i])
10431 /* Bootstrap checksum at offset 0x10 */
10432 csum = calc_crc((unsigned char *) buf, 0x10);
10433 if (csum != be32_to_cpu(buf[0x10/4]))
10436 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
10437 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
10438 if (csum != be32_to_cpu(buf[0xfc/4]))
10448 #define TG3_SERDES_TIMEOUT_SEC 2
10449 #define TG3_COPPER_TIMEOUT_SEC 6
10451 static int tg3_test_link(struct tg3 *tp)
10455 if (!netif_running(tp->dev))
10458 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
10459 max = TG3_SERDES_TIMEOUT_SEC;
10461 max = TG3_COPPER_TIMEOUT_SEC;
10463 for (i = 0; i < max; i++) {
10464 if (netif_carrier_ok(tp->dev))
10467 if (msleep_interruptible(1000))
10474 /* Only test the commonly used registers */
10475 static int tg3_test_registers(struct tg3 *tp)
10477 int i, is_5705, is_5750;
10478 u32 offset, read_mask, write_mask, val, save_val, read_val;
10482 #define TG3_FL_5705 0x1
10483 #define TG3_FL_NOT_5705 0x2
10484 #define TG3_FL_NOT_5788 0x4
10485 #define TG3_FL_NOT_5750 0x8
10489 /* MAC Control Registers */
10490 { MAC_MODE, TG3_FL_NOT_5705,
10491 0x00000000, 0x00ef6f8c },
10492 { MAC_MODE, TG3_FL_5705,
10493 0x00000000, 0x01ef6b8c },
10494 { MAC_STATUS, TG3_FL_NOT_5705,
10495 0x03800107, 0x00000000 },
10496 { MAC_STATUS, TG3_FL_5705,
10497 0x03800100, 0x00000000 },
10498 { MAC_ADDR_0_HIGH, 0x0000,
10499 0x00000000, 0x0000ffff },
10500 { MAC_ADDR_0_LOW, 0x0000,
10501 0x00000000, 0xffffffff },
10502 { MAC_RX_MTU_SIZE, 0x0000,
10503 0x00000000, 0x0000ffff },
10504 { MAC_TX_MODE, 0x0000,
10505 0x00000000, 0x00000070 },
10506 { MAC_TX_LENGTHS, 0x0000,
10507 0x00000000, 0x00003fff },
10508 { MAC_RX_MODE, TG3_FL_NOT_5705,
10509 0x00000000, 0x000007fc },
10510 { MAC_RX_MODE, TG3_FL_5705,
10511 0x00000000, 0x000007dc },
10512 { MAC_HASH_REG_0, 0x0000,
10513 0x00000000, 0xffffffff },
10514 { MAC_HASH_REG_1, 0x0000,
10515 0x00000000, 0xffffffff },
10516 { MAC_HASH_REG_2, 0x0000,
10517 0x00000000, 0xffffffff },
10518 { MAC_HASH_REG_3, 0x0000,
10519 0x00000000, 0xffffffff },
10521 /* Receive Data and Receive BD Initiator Control Registers. */
10522 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
10523 0x00000000, 0xffffffff },
10524 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
10525 0x00000000, 0xffffffff },
10526 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
10527 0x00000000, 0x00000003 },
10528 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
10529 0x00000000, 0xffffffff },
10530 { RCVDBDI_STD_BD+0, 0x0000,
10531 0x00000000, 0xffffffff },
10532 { RCVDBDI_STD_BD+4, 0x0000,
10533 0x00000000, 0xffffffff },
10534 { RCVDBDI_STD_BD+8, 0x0000,
10535 0x00000000, 0xffff0002 },
10536 { RCVDBDI_STD_BD+0xc, 0x0000,
10537 0x00000000, 0xffffffff },
10539 /* Receive BD Initiator Control Registers. */
10540 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
10541 0x00000000, 0xffffffff },
10542 { RCVBDI_STD_THRESH, TG3_FL_5705,
10543 0x00000000, 0x000003ff },
10544 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
10545 0x00000000, 0xffffffff },
10547 /* Host Coalescing Control Registers. */
10548 { HOSTCC_MODE, TG3_FL_NOT_5705,
10549 0x00000000, 0x00000004 },
10550 { HOSTCC_MODE, TG3_FL_5705,
10551 0x00000000, 0x000000f6 },
10552 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
10553 0x00000000, 0xffffffff },
10554 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
10555 0x00000000, 0x000003ff },
10556 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
10557 0x00000000, 0xffffffff },
10558 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
10559 0x00000000, 0x000003ff },
10560 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
10561 0x00000000, 0xffffffff },
10562 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10563 0x00000000, 0x000000ff },
10564 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
10565 0x00000000, 0xffffffff },
10566 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10567 0x00000000, 0x000000ff },
10568 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
10569 0x00000000, 0xffffffff },
10570 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
10571 0x00000000, 0xffffffff },
10572 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10573 0x00000000, 0xffffffff },
10574 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10575 0x00000000, 0x000000ff },
10576 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10577 0x00000000, 0xffffffff },
10578 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10579 0x00000000, 0x000000ff },
10580 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
10581 0x00000000, 0xffffffff },
10582 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
10583 0x00000000, 0xffffffff },
10584 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
10585 0x00000000, 0xffffffff },
10586 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
10587 0x00000000, 0xffffffff },
10588 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
10589 0x00000000, 0xffffffff },
10590 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
10591 0xffffffff, 0x00000000 },
10592 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
10593 0xffffffff, 0x00000000 },
10595 /* Buffer Manager Control Registers. */
10596 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
10597 0x00000000, 0x007fff80 },
10598 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
10599 0x00000000, 0x007fffff },
10600 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
10601 0x00000000, 0x0000003f },
10602 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
10603 0x00000000, 0x000001ff },
10604 { BUFMGR_MB_HIGH_WATER, 0x0000,
10605 0x00000000, 0x000001ff },
10606 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
10607 0xffffffff, 0x00000000 },
10608 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
10609 0xffffffff, 0x00000000 },
10611 /* Mailbox Registers */
10612 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
10613 0x00000000, 0x000001ff },
10614 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
10615 0x00000000, 0x000001ff },
10616 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
10617 0x00000000, 0x000007ff },
10618 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
10619 0x00000000, 0x000001ff },
10621 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
10624 is_5705 = is_5750 = 0;
10625 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
10627 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10631 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
10632 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
10635 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
10638 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
10639 (reg_tbl[i].flags & TG3_FL_NOT_5788))
10642 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
10645 offset = (u32) reg_tbl[i].offset;
10646 read_mask = reg_tbl[i].read_mask;
10647 write_mask = reg_tbl[i].write_mask;
10649 /* Save the original register content */
10650 save_val = tr32(offset);
10652 /* Determine the read-only value. */
10653 read_val = save_val & read_mask;
10655 /* Write zero to the register, then make sure the read-only bits
10656 * are not changed and the read/write bits are all zeros.
10660 val = tr32(offset);
10662 /* Test the read-only and read/write bits. */
10663 if (((val & read_mask) != read_val) || (val & write_mask))
10666 /* Write ones to all the bits defined by RdMask and WrMask, then
10667 * make sure the read-only bits are not changed and the
10668 * read/write bits are all ones.
10670 tw32(offset, read_mask | write_mask);
10672 val = tr32(offset);
10674 /* Test the read-only bits. */
10675 if ((val & read_mask) != read_val)
10678 /* Test the read/write bits. */
10679 if ((val & write_mask) != write_mask)
10682 tw32(offset, save_val);
10688 if (netif_msg_hw(tp))
10689 printk(KERN_ERR PFX "Register test failed at offset %x\n",
10691 tw32(offset, save_val);
10695 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
10697 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
10701 for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
10702 for (j = 0; j < len; j += 4) {
10705 tg3_write_mem(tp, offset + j, test_pattern[i]);
10706 tg3_read_mem(tp, offset + j, &val);
10707 if (val != test_pattern[i])
10714 static int tg3_test_memory(struct tg3 *tp)
10716 static struct mem_entry {
10719 } mem_tbl_570x[] = {
10720 { 0x00000000, 0x00b50},
10721 { 0x00002000, 0x1c000},
10722 { 0xffffffff, 0x00000}
10723 }, mem_tbl_5705[] = {
10724 { 0x00000100, 0x0000c},
10725 { 0x00000200, 0x00008},
10726 { 0x00004000, 0x00800},
10727 { 0x00006000, 0x01000},
10728 { 0x00008000, 0x02000},
10729 { 0x00010000, 0x0e000},
10730 { 0xffffffff, 0x00000}
10731 }, mem_tbl_5755[] = {
10732 { 0x00000200, 0x00008},
10733 { 0x00004000, 0x00800},
10734 { 0x00006000, 0x00800},
10735 { 0x00008000, 0x02000},
10736 { 0x00010000, 0x0c000},
10737 { 0xffffffff, 0x00000}
10738 }, mem_tbl_5906[] = {
10739 { 0x00000200, 0x00008},
10740 { 0x00004000, 0x00400},
10741 { 0x00006000, 0x00400},
10742 { 0x00008000, 0x01000},
10743 { 0x00010000, 0x01000},
10744 { 0xffffffff, 0x00000}
10745 }, mem_tbl_5717[] = {
10746 { 0x00000200, 0x00008},
10747 { 0x00010000, 0x0a000},
10748 { 0x00020000, 0x13c00},
10749 { 0xffffffff, 0x00000}
10750 }, mem_tbl_57765[] = {
10751 { 0x00000200, 0x00008},
10752 { 0x00004000, 0x00800},
10753 { 0x00006000, 0x09800},
10754 { 0x00010000, 0x0a000},
10755 { 0xffffffff, 0x00000}
10757 struct mem_entry *mem_tbl;
10761 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
10762 mem_tbl = mem_tbl_5717;
10763 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
10764 mem_tbl = mem_tbl_57765;
10765 else if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10766 mem_tbl = mem_tbl_5755;
10767 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10768 mem_tbl = mem_tbl_5906;
10769 else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
10770 mem_tbl = mem_tbl_5705;
10772 mem_tbl = mem_tbl_570x;
10774 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
10775 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
10776 mem_tbl[i].len)) != 0)
10783 #define TG3_MAC_LOOPBACK 0
10784 #define TG3_PHY_LOOPBACK 1
10786 static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
10788 u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
10789 u32 desc_idx, coal_now;
10790 struct sk_buff *skb, *rx_skb;
10793 int num_pkts, tx_len, rx_len, i, err;
10794 struct tg3_rx_buffer_desc *desc;
10795 struct tg3_napi *tnapi, *rnapi;
10796 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
10798 tnapi = &tp->napi[0];
10799 rnapi = &tp->napi[0];
10800 if (tp->irq_cnt > 1) {
10801 rnapi = &tp->napi[1];
10802 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
10803 tnapi = &tp->napi[1];
10805 coal_now = tnapi->coal_now | rnapi->coal_now;
10807 if (loopback_mode == TG3_MAC_LOOPBACK) {
10808 /* HW errata - mac loopback fails in some cases on 5780.
10809 * Normal traffic and PHY loopback are not affected by
10812 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
10815 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
10816 MAC_MODE_PORT_INT_LPBACK;
10817 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10818 mac_mode |= MAC_MODE_LINK_POLARITY;
10819 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
10820 mac_mode |= MAC_MODE_PORT_MODE_MII;
10822 mac_mode |= MAC_MODE_PORT_MODE_GMII;
10823 tw32(MAC_MODE, mac_mode);
10824 } else if (loopback_mode == TG3_PHY_LOOPBACK) {
10827 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
10828 tg3_phy_fet_toggle_apd(tp, false);
10829 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
10831 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
10833 tg3_phy_toggle_automdix(tp, 0);
10835 tg3_writephy(tp, MII_BMCR, val);
10838 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
10839 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
10840 tg3_writephy(tp, MII_TG3_FET_PTEST,
10841 MII_TG3_FET_PTEST_FRC_TX_LINK |
10842 MII_TG3_FET_PTEST_FRC_TX_LOCK);
10843 /* The write needs to be flushed for the AC131 */
10844 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
10845 tg3_readphy(tp, MII_TG3_FET_PTEST, &val);
10846 mac_mode |= MAC_MODE_PORT_MODE_MII;
10848 mac_mode |= MAC_MODE_PORT_MODE_GMII;
10850 /* reset to prevent losing 1st rx packet intermittently */
10851 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
10852 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10854 tw32_f(MAC_RX_MODE, tp->rx_mode);
10856 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
10857 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)
10858 mac_mode &= ~MAC_MODE_LINK_POLARITY;
10859 else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411)
10860 mac_mode |= MAC_MODE_LINK_POLARITY;
10861 tg3_writephy(tp, MII_TG3_EXT_CTRL,
10862 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
10864 tw32(MAC_MODE, mac_mode);
10872 skb = netdev_alloc_skb(tp->dev, tx_len);
10876 tx_data = skb_put(skb, tx_len);
10877 memcpy(tx_data, tp->dev->dev_addr, 6);
10878 memset(tx_data + 6, 0x0, 8);
10880 tw32(MAC_RX_MTU_SIZE, tx_len + 4);
10882 for (i = 14; i < tx_len; i++)
10883 tx_data[i] = (u8) (i & 0xff);
10885 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
10886 if (pci_dma_mapping_error(tp->pdev, map)) {
10887 dev_kfree_skb(skb);
10891 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10896 rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
10900 tg3_set_txd(tnapi, tnapi->tx_prod, map, tx_len, 0, 1);
10905 tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
10906 tr32_mailbox(tnapi->prodmbox);
10910 /* 350 usec to allow enough time on some 10/100 Mbps devices. */
10911 for (i = 0; i < 35; i++) {
10912 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10917 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
10918 rx_idx = rnapi->hw_status->idx[0].rx_producer;
10919 if ((tx_idx == tnapi->tx_prod) &&
10920 (rx_idx == (rx_start_idx + num_pkts)))
10924 pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
10925 dev_kfree_skb(skb);
10927 if (tx_idx != tnapi->tx_prod)
10930 if (rx_idx != rx_start_idx + num_pkts)
10933 desc = &rnapi->rx_rcb[rx_start_idx];
10934 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
10935 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
10936 if (opaque_key != RXD_OPAQUE_RING_STD)
10939 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
10940 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
10943 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
10944 if (rx_len != tx_len)
10947 rx_skb = tpr->rx_std_buffers[desc_idx].skb;
10949 map = pci_unmap_addr(&tpr->rx_std_buffers[desc_idx], mapping);
10950 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
10952 for (i = 14; i < tx_len; i++) {
10953 if (*(rx_skb->data + i) != (u8) (i & 0xff))
10958 /* tg3_free_rings will unmap and free the rx_skb */
10963 #define TG3_MAC_LOOPBACK_FAILED 1
10964 #define TG3_PHY_LOOPBACK_FAILED 2
10965 #define TG3_LOOPBACK_FAILED (TG3_MAC_LOOPBACK_FAILED | \
10966 TG3_PHY_LOOPBACK_FAILED)
10968 static int tg3_test_loopback(struct tg3 *tp)
10973 if (!netif_running(tp->dev))
10974 return TG3_LOOPBACK_FAILED;
10976 err = tg3_reset_hw(tp, 1);
10978 return TG3_LOOPBACK_FAILED;
10980 /* Turn off gphy autopowerdown. */
10981 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10982 tg3_phy_toggle_apd(tp, false);
10984 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
10988 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
10990 /* Wait for up to 40 microseconds to acquire lock. */
10991 for (i = 0; i < 4; i++) {
10992 status = tr32(TG3_CPMU_MUTEX_GNT);
10993 if (status == CPMU_MUTEX_GNT_DRIVER)
10998 if (status != CPMU_MUTEX_GNT_DRIVER)
10999 return TG3_LOOPBACK_FAILED;
11001 /* Turn off link-based power management. */
11002 cpmuctrl = tr32(TG3_CPMU_CTRL);
11003 tw32(TG3_CPMU_CTRL,
11004 cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
11005 CPMU_CTRL_LINK_AWARE_MODE));
11008 if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
11009 err |= TG3_MAC_LOOPBACK_FAILED;
11011 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
11012 tw32(TG3_CPMU_CTRL, cpmuctrl);
11014 /* Release the mutex */
11015 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
11018 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
11019 !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
11020 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
11021 err |= TG3_PHY_LOOPBACK_FAILED;
11024 /* Re-enable gphy autopowerdown. */
11025 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
11026 tg3_phy_toggle_apd(tp, true);
11031 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
11034 struct tg3 *tp = netdev_priv(dev);
11036 if (tp->link_config.phy_is_low_power)
11037 tg3_set_power_state(tp, PCI_D0);
11039 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
11041 if (tg3_test_nvram(tp) != 0) {
11042 etest->flags |= ETH_TEST_FL_FAILED;
11045 if (tg3_test_link(tp) != 0) {
11046 etest->flags |= ETH_TEST_FL_FAILED;
11049 if (etest->flags & ETH_TEST_FL_OFFLINE) {
11050 int err, err2 = 0, irq_sync = 0;
11052 if (netif_running(dev)) {
11054 tg3_netif_stop(tp);
11058 tg3_full_lock(tp, irq_sync);
11060 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
11061 err = tg3_nvram_lock(tp);
11062 tg3_halt_cpu(tp, RX_CPU_BASE);
11063 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
11064 tg3_halt_cpu(tp, TX_CPU_BASE);
11066 tg3_nvram_unlock(tp);
11068 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
11071 if (tg3_test_registers(tp) != 0) {
11072 etest->flags |= ETH_TEST_FL_FAILED;
11075 if (tg3_test_memory(tp) != 0) {
11076 etest->flags |= ETH_TEST_FL_FAILED;
11079 if ((data[4] = tg3_test_loopback(tp)) != 0)
11080 etest->flags |= ETH_TEST_FL_FAILED;
11082 tg3_full_unlock(tp);
11084 if (tg3_test_interrupt(tp) != 0) {
11085 etest->flags |= ETH_TEST_FL_FAILED;
11089 tg3_full_lock(tp, 0);
11091 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11092 if (netif_running(dev)) {
11093 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
11094 err2 = tg3_restart_hw(tp, 1);
11096 tg3_netif_start(tp);
11099 tg3_full_unlock(tp);
11101 if (irq_sync && !err2)
11104 if (tp->link_config.phy_is_low_power)
11105 tg3_set_power_state(tp, PCI_D3hot);
11109 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
11111 struct mii_ioctl_data *data = if_mii(ifr);
11112 struct tg3 *tp = netdev_priv(dev);
11115 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
11116 struct phy_device *phydev;
11117 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
11119 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
11120 return phy_mii_ioctl(phydev, data, cmd);
11125 data->phy_id = tp->phy_addr;
11128 case SIOCGMIIREG: {
11131 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
11132 break; /* We have no PHY */
11134 if (tp->link_config.phy_is_low_power)
11137 spin_lock_bh(&tp->lock);
11138 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
11139 spin_unlock_bh(&tp->lock);
11141 data->val_out = mii_regval;
11147 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
11148 break; /* We have no PHY */
11150 if (tp->link_config.phy_is_low_power)
11153 spin_lock_bh(&tp->lock);
11154 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
11155 spin_unlock_bh(&tp->lock);
11163 return -EOPNOTSUPP;
11166 #if TG3_VLAN_TAG_USED
11167 static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
11169 struct tg3 *tp = netdev_priv(dev);
11171 if (!netif_running(dev)) {
11176 tg3_netif_stop(tp);
11178 tg3_full_lock(tp, 0);
11182 /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
11183 __tg3_set_rx_mode(dev);
11185 tg3_netif_start(tp);
11187 tg3_full_unlock(tp);
11191 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11193 struct tg3 *tp = netdev_priv(dev);
11195 memcpy(ec, &tp->coal, sizeof(*ec));
11199 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11201 struct tg3 *tp = netdev_priv(dev);
11202 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
11203 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
11205 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
11206 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
11207 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
11208 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
11209 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
11212 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
11213 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
11214 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
11215 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
11216 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
11217 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
11218 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
11219 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
11220 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
11221 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
11224 /* No rx interrupts will be generated if both are zero */
11225 if ((ec->rx_coalesce_usecs == 0) &&
11226 (ec->rx_max_coalesced_frames == 0))
11229 /* No tx interrupts will be generated if both are zero */
11230 if ((ec->tx_coalesce_usecs == 0) &&
11231 (ec->tx_max_coalesced_frames == 0))
11234 /* Only copy relevant parameters, ignore all others. */
11235 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
11236 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
11237 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
11238 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
11239 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
11240 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
11241 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
11242 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
11243 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
11245 if (netif_running(dev)) {
11246 tg3_full_lock(tp, 0);
11247 __tg3_set_coalesce(tp, &tp->coal);
11248 tg3_full_unlock(tp);
11253 static const struct ethtool_ops tg3_ethtool_ops = {
11254 .get_settings = tg3_get_settings,
11255 .set_settings = tg3_set_settings,
11256 .get_drvinfo = tg3_get_drvinfo,
11257 .get_regs_len = tg3_get_regs_len,
11258 .get_regs = tg3_get_regs,
11259 .get_wol = tg3_get_wol,
11260 .set_wol = tg3_set_wol,
11261 .get_msglevel = tg3_get_msglevel,
11262 .set_msglevel = tg3_set_msglevel,
11263 .nway_reset = tg3_nway_reset,
11264 .get_link = ethtool_op_get_link,
11265 .get_eeprom_len = tg3_get_eeprom_len,
11266 .get_eeprom = tg3_get_eeprom,
11267 .set_eeprom = tg3_set_eeprom,
11268 .get_ringparam = tg3_get_ringparam,
11269 .set_ringparam = tg3_set_ringparam,
11270 .get_pauseparam = tg3_get_pauseparam,
11271 .set_pauseparam = tg3_set_pauseparam,
11272 .get_rx_csum = tg3_get_rx_csum,
11273 .set_rx_csum = tg3_set_rx_csum,
11274 .set_tx_csum = tg3_set_tx_csum,
11275 .set_sg = ethtool_op_set_sg,
11276 .set_tso = tg3_set_tso,
11277 .self_test = tg3_self_test,
11278 .get_strings = tg3_get_strings,
11279 .phys_id = tg3_phys_id,
11280 .get_ethtool_stats = tg3_get_ethtool_stats,
11281 .get_coalesce = tg3_get_coalesce,
11282 .set_coalesce = tg3_set_coalesce,
11283 .get_sset_count = tg3_get_sset_count,
11286 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
11288 u32 cursize, val, magic;
11290 tp->nvram_size = EEPROM_CHIP_SIZE;
11292 if (tg3_nvram_read(tp, 0, &magic) != 0)
11295 if ((magic != TG3_EEPROM_MAGIC) &&
11296 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
11297 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
11301 * Size the chip by reading offsets at increasing powers of two.
11302 * When we encounter our validation signature, we know the addressing
11303 * has wrapped around, and thus have our chip size.
11307 while (cursize < tp->nvram_size) {
11308 if (tg3_nvram_read(tp, cursize, &val) != 0)
11317 tp->nvram_size = cursize;
11320 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
11324 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
11325 tg3_nvram_read(tp, 0, &val) != 0)
11328 /* Selfboot format */
11329 if (val != TG3_EEPROM_MAGIC) {
11330 tg3_get_eeprom_size(tp);
11334 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
11336 /* This is confusing. We want to operate on the
11337 * 16-bit value at offset 0xf2. The tg3_nvram_read()
11338 * call will read from NVRAM and byteswap the data
11339 * according to the byteswapping settings for all
11340 * other register accesses. This ensures the data we
11341 * want will always reside in the lower 16-bits.
11342 * However, the data in NVRAM is in LE format, which
11343 * means the data from the NVRAM read will always be
11344 * opposite the endianness of the CPU. The 16-bit
11345 * byteswap then brings the data to CPU endianness.
11347 tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
11351 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11354 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
11358 nvcfg1 = tr32(NVRAM_CFG1);
11359 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
11360 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11362 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11363 tw32(NVRAM_CFG1, nvcfg1);
11366 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
11367 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
11368 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
11369 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
11370 tp->nvram_jedecnum = JEDEC_ATMEL;
11371 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11372 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11374 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
11375 tp->nvram_jedecnum = JEDEC_ATMEL;
11376 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
11378 case FLASH_VENDOR_ATMEL_EEPROM:
11379 tp->nvram_jedecnum = JEDEC_ATMEL;
11380 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11381 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11383 case FLASH_VENDOR_ST:
11384 tp->nvram_jedecnum = JEDEC_ST;
11385 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
11386 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11388 case FLASH_VENDOR_SAIFUN:
11389 tp->nvram_jedecnum = JEDEC_SAIFUN;
11390 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
11392 case FLASH_VENDOR_SST_SMALL:
11393 case FLASH_VENDOR_SST_LARGE:
11394 tp->nvram_jedecnum = JEDEC_SST;
11395 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
11399 tp->nvram_jedecnum = JEDEC_ATMEL;
11400 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11401 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11405 static void __devinit tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
11407 switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
11408 case FLASH_5752PAGE_SIZE_256:
11409 tp->nvram_pagesize = 256;
11411 case FLASH_5752PAGE_SIZE_512:
11412 tp->nvram_pagesize = 512;
11414 case FLASH_5752PAGE_SIZE_1K:
11415 tp->nvram_pagesize = 1024;
11417 case FLASH_5752PAGE_SIZE_2K:
11418 tp->nvram_pagesize = 2048;
11420 case FLASH_5752PAGE_SIZE_4K:
11421 tp->nvram_pagesize = 4096;
11423 case FLASH_5752PAGE_SIZE_264:
11424 tp->nvram_pagesize = 264;
11426 case FLASH_5752PAGE_SIZE_528:
11427 tp->nvram_pagesize = 528;
11432 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
11436 nvcfg1 = tr32(NVRAM_CFG1);
11438 /* NVRAM protection for TPM */
11439 if (nvcfg1 & (1 << 27))
11440 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11442 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11443 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
11444 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
11445 tp->nvram_jedecnum = JEDEC_ATMEL;
11446 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11448 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11449 tp->nvram_jedecnum = JEDEC_ATMEL;
11450 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11451 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11453 case FLASH_5752VENDOR_ST_M45PE10:
11454 case FLASH_5752VENDOR_ST_M45PE20:
11455 case FLASH_5752VENDOR_ST_M45PE40:
11456 tp->nvram_jedecnum = JEDEC_ST;
11457 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11458 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11462 if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
11463 tg3_nvram_get_pagesize(tp, nvcfg1);
11465 /* For eeprom, set pagesize to maximum eeprom size */
11466 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11468 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11469 tw32(NVRAM_CFG1, nvcfg1);
11473 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
11475 u32 nvcfg1, protect = 0;
11477 nvcfg1 = tr32(NVRAM_CFG1);
11479 /* NVRAM protection for TPM */
11480 if (nvcfg1 & (1 << 27)) {
11481 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11485 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11487 case FLASH_5755VENDOR_ATMEL_FLASH_1:
11488 case FLASH_5755VENDOR_ATMEL_FLASH_2:
11489 case FLASH_5755VENDOR_ATMEL_FLASH_3:
11490 case FLASH_5755VENDOR_ATMEL_FLASH_5:
11491 tp->nvram_jedecnum = JEDEC_ATMEL;
11492 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11493 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11494 tp->nvram_pagesize = 264;
11495 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
11496 nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
11497 tp->nvram_size = (protect ? 0x3e200 :
11498 TG3_NVRAM_SIZE_512KB);
11499 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
11500 tp->nvram_size = (protect ? 0x1f200 :
11501 TG3_NVRAM_SIZE_256KB);
11503 tp->nvram_size = (protect ? 0x1f200 :
11504 TG3_NVRAM_SIZE_128KB);
11506 case FLASH_5752VENDOR_ST_M45PE10:
11507 case FLASH_5752VENDOR_ST_M45PE20:
11508 case FLASH_5752VENDOR_ST_M45PE40:
11509 tp->nvram_jedecnum = JEDEC_ST;
11510 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11511 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11512 tp->nvram_pagesize = 256;
11513 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
11514 tp->nvram_size = (protect ?
11515 TG3_NVRAM_SIZE_64KB :
11516 TG3_NVRAM_SIZE_128KB);
11517 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
11518 tp->nvram_size = (protect ?
11519 TG3_NVRAM_SIZE_64KB :
11520 TG3_NVRAM_SIZE_256KB);
11522 tp->nvram_size = (protect ?
11523 TG3_NVRAM_SIZE_128KB :
11524 TG3_NVRAM_SIZE_512KB);
11529 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
11533 nvcfg1 = tr32(NVRAM_CFG1);
11535 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11536 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
11537 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11538 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
11539 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11540 tp->nvram_jedecnum = JEDEC_ATMEL;
11541 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11542 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11544 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11545 tw32(NVRAM_CFG1, nvcfg1);
11547 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11548 case FLASH_5755VENDOR_ATMEL_FLASH_1:
11549 case FLASH_5755VENDOR_ATMEL_FLASH_2:
11550 case FLASH_5755VENDOR_ATMEL_FLASH_3:
11551 tp->nvram_jedecnum = JEDEC_ATMEL;
11552 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11553 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11554 tp->nvram_pagesize = 264;
11556 case FLASH_5752VENDOR_ST_M45PE10:
11557 case FLASH_5752VENDOR_ST_M45PE20:
11558 case FLASH_5752VENDOR_ST_M45PE40:
11559 tp->nvram_jedecnum = JEDEC_ST;
11560 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11561 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11562 tp->nvram_pagesize = 256;
11567 static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
11569 u32 nvcfg1, protect = 0;
11571 nvcfg1 = tr32(NVRAM_CFG1);
11573 /* NVRAM protection for TPM */
11574 if (nvcfg1 & (1 << 27)) {
11575 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11579 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11581 case FLASH_5761VENDOR_ATMEL_ADB021D:
11582 case FLASH_5761VENDOR_ATMEL_ADB041D:
11583 case FLASH_5761VENDOR_ATMEL_ADB081D:
11584 case FLASH_5761VENDOR_ATMEL_ADB161D:
11585 case FLASH_5761VENDOR_ATMEL_MDB021D:
11586 case FLASH_5761VENDOR_ATMEL_MDB041D:
11587 case FLASH_5761VENDOR_ATMEL_MDB081D:
11588 case FLASH_5761VENDOR_ATMEL_MDB161D:
11589 tp->nvram_jedecnum = JEDEC_ATMEL;
11590 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11591 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11592 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11593 tp->nvram_pagesize = 256;
11595 case FLASH_5761VENDOR_ST_A_M45PE20:
11596 case FLASH_5761VENDOR_ST_A_M45PE40:
11597 case FLASH_5761VENDOR_ST_A_M45PE80:
11598 case FLASH_5761VENDOR_ST_A_M45PE16:
11599 case FLASH_5761VENDOR_ST_M_M45PE20:
11600 case FLASH_5761VENDOR_ST_M_M45PE40:
11601 case FLASH_5761VENDOR_ST_M_M45PE80:
11602 case FLASH_5761VENDOR_ST_M_M45PE16:
11603 tp->nvram_jedecnum = JEDEC_ST;
11604 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11605 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11606 tp->nvram_pagesize = 256;
11611 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
11614 case FLASH_5761VENDOR_ATMEL_ADB161D:
11615 case FLASH_5761VENDOR_ATMEL_MDB161D:
11616 case FLASH_5761VENDOR_ST_A_M45PE16:
11617 case FLASH_5761VENDOR_ST_M_M45PE16:
11618 tp->nvram_size = TG3_NVRAM_SIZE_2MB;
11620 case FLASH_5761VENDOR_ATMEL_ADB081D:
11621 case FLASH_5761VENDOR_ATMEL_MDB081D:
11622 case FLASH_5761VENDOR_ST_A_M45PE80:
11623 case FLASH_5761VENDOR_ST_M_M45PE80:
11624 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
11626 case FLASH_5761VENDOR_ATMEL_ADB041D:
11627 case FLASH_5761VENDOR_ATMEL_MDB041D:
11628 case FLASH_5761VENDOR_ST_A_M45PE40:
11629 case FLASH_5761VENDOR_ST_M_M45PE40:
11630 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11632 case FLASH_5761VENDOR_ATMEL_ADB021D:
11633 case FLASH_5761VENDOR_ATMEL_MDB021D:
11634 case FLASH_5761VENDOR_ST_A_M45PE20:
11635 case FLASH_5761VENDOR_ST_M_M45PE20:
11636 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11642 static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
11644 tp->nvram_jedecnum = JEDEC_ATMEL;
11645 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11646 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11649 static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
11653 nvcfg1 = tr32(NVRAM_CFG1);
11655 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11656 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11657 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11658 tp->nvram_jedecnum = JEDEC_ATMEL;
11659 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11660 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11662 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11663 tw32(NVRAM_CFG1, nvcfg1);
11665 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11666 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11667 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11668 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11669 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11670 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11671 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11672 tp->nvram_jedecnum = JEDEC_ATMEL;
11673 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11674 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11676 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11677 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11678 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11679 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11680 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11682 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11683 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11684 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11686 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11687 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11688 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11692 case FLASH_5752VENDOR_ST_M45PE10:
11693 case FLASH_5752VENDOR_ST_M45PE20:
11694 case FLASH_5752VENDOR_ST_M45PE40:
11695 tp->nvram_jedecnum = JEDEC_ST;
11696 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11697 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11699 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11700 case FLASH_5752VENDOR_ST_M45PE10:
11701 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11703 case FLASH_5752VENDOR_ST_M45PE20:
11704 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11706 case FLASH_5752VENDOR_ST_M45PE40:
11707 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11712 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11716 tg3_nvram_get_pagesize(tp, nvcfg1);
11717 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11718 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11722 static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp)
11726 nvcfg1 = tr32(NVRAM_CFG1);
11728 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11729 case FLASH_5717VENDOR_ATMEL_EEPROM:
11730 case FLASH_5717VENDOR_MICRO_EEPROM:
11731 tp->nvram_jedecnum = JEDEC_ATMEL;
11732 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11733 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11735 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11736 tw32(NVRAM_CFG1, nvcfg1);
11738 case FLASH_5717VENDOR_ATMEL_MDB011D:
11739 case FLASH_5717VENDOR_ATMEL_ADB011B:
11740 case FLASH_5717VENDOR_ATMEL_ADB011D:
11741 case FLASH_5717VENDOR_ATMEL_MDB021D:
11742 case FLASH_5717VENDOR_ATMEL_ADB021B:
11743 case FLASH_5717VENDOR_ATMEL_ADB021D:
11744 case FLASH_5717VENDOR_ATMEL_45USPT:
11745 tp->nvram_jedecnum = JEDEC_ATMEL;
11746 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11747 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11749 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11750 case FLASH_5717VENDOR_ATMEL_MDB021D:
11751 case FLASH_5717VENDOR_ATMEL_ADB021B:
11752 case FLASH_5717VENDOR_ATMEL_ADB021D:
11753 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11756 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11760 case FLASH_5717VENDOR_ST_M_M25PE10:
11761 case FLASH_5717VENDOR_ST_A_M25PE10:
11762 case FLASH_5717VENDOR_ST_M_M45PE10:
11763 case FLASH_5717VENDOR_ST_A_M45PE10:
11764 case FLASH_5717VENDOR_ST_M_M25PE20:
11765 case FLASH_5717VENDOR_ST_A_M25PE20:
11766 case FLASH_5717VENDOR_ST_M_M45PE20:
11767 case FLASH_5717VENDOR_ST_A_M45PE20:
11768 case FLASH_5717VENDOR_ST_25USPT:
11769 case FLASH_5717VENDOR_ST_45USPT:
11770 tp->nvram_jedecnum = JEDEC_ST;
11771 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11772 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11774 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11775 case FLASH_5717VENDOR_ST_M_M25PE20:
11776 case FLASH_5717VENDOR_ST_A_M25PE20:
11777 case FLASH_5717VENDOR_ST_M_M45PE20:
11778 case FLASH_5717VENDOR_ST_A_M45PE20:
11779 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11782 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11787 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11791 tg3_nvram_get_pagesize(tp, nvcfg1);
11792 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11793 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11796 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
11797 static void __devinit tg3_nvram_init(struct tg3 *tp)
11799 tw32_f(GRC_EEPROM_ADDR,
11800 (EEPROM_ADDR_FSM_RESET |
11801 (EEPROM_DEFAULT_CLOCK_PERIOD <<
11802 EEPROM_ADDR_CLKPERD_SHIFT)));
11806 /* Enable seeprom accesses. */
11807 tw32_f(GRC_LOCAL_CTRL,
11808 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
11811 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11812 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
11813 tp->tg3_flags |= TG3_FLAG_NVRAM;
11815 if (tg3_nvram_lock(tp)) {
11816 printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
11817 "tg3_nvram_init failed.\n", tp->dev->name);
11820 tg3_enable_nvram_access(tp);
11822 tp->nvram_size = 0;
11824 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
11825 tg3_get_5752_nvram_info(tp);
11826 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
11827 tg3_get_5755_nvram_info(tp);
11828 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
11829 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11830 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11831 tg3_get_5787_nvram_info(tp);
11832 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
11833 tg3_get_5761_nvram_info(tp);
11834 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11835 tg3_get_5906_nvram_info(tp);
11836 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
11837 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
11838 tg3_get_57780_nvram_info(tp);
11839 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
11840 tg3_get_5717_nvram_info(tp);
11842 tg3_get_nvram_info(tp);
11844 if (tp->nvram_size == 0)
11845 tg3_get_nvram_size(tp);
11847 tg3_disable_nvram_access(tp);
11848 tg3_nvram_unlock(tp);
11851 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
11853 tg3_get_eeprom_size(tp);
11857 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
11858 u32 offset, u32 len, u8 *buf)
11863 for (i = 0; i < len; i += 4) {
11869 memcpy(&data, buf + i, 4);
11872 * The SEEPROM interface expects the data to always be opposite
11873 * the native endian format. We accomplish this by reversing
11874 * all the operations that would have been performed on the
11875 * data from a call to tg3_nvram_read_be32().
11877 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
11879 val = tr32(GRC_EEPROM_ADDR);
11880 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
11882 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
11884 tw32(GRC_EEPROM_ADDR, val |
11885 (0 << EEPROM_ADDR_DEVID_SHIFT) |
11886 (addr & EEPROM_ADDR_ADDR_MASK) |
11887 EEPROM_ADDR_START |
11888 EEPROM_ADDR_WRITE);
11890 for (j = 0; j < 1000; j++) {
11891 val = tr32(GRC_EEPROM_ADDR);
11893 if (val & EEPROM_ADDR_COMPLETE)
11897 if (!(val & EEPROM_ADDR_COMPLETE)) {
11906 /* offset and length are dword aligned */
11907 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
11911 u32 pagesize = tp->nvram_pagesize;
11912 u32 pagemask = pagesize - 1;
11916 tmp = kmalloc(pagesize, GFP_KERNEL);
11922 u32 phy_addr, page_off, size;
11924 phy_addr = offset & ~pagemask;
11926 for (j = 0; j < pagesize; j += 4) {
11927 ret = tg3_nvram_read_be32(tp, phy_addr + j,
11928 (__be32 *) (tmp + j));
11935 page_off = offset & pagemask;
11942 memcpy(tmp + page_off, buf, size);
11944 offset = offset + (pagesize - page_off);
11946 tg3_enable_nvram_access(tp);
11949 * Before we can erase the flash page, we need
11950 * to issue a special "write enable" command.
11952 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11954 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11957 /* Erase the target page */
11958 tw32(NVRAM_ADDR, phy_addr);
11960 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
11961 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
11963 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11966 /* Issue another write enable to start the write. */
11967 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11969 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11972 for (j = 0; j < pagesize; j += 4) {
11975 data = *((__be32 *) (tmp + j));
11977 tw32(NVRAM_WRDATA, be32_to_cpu(data));
11979 tw32(NVRAM_ADDR, phy_addr + j);
11981 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
11985 nvram_cmd |= NVRAM_CMD_FIRST;
11986 else if (j == (pagesize - 4))
11987 nvram_cmd |= NVRAM_CMD_LAST;
11989 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11996 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11997 tg3_nvram_exec_cmd(tp, nvram_cmd);
12004 /* offset and length are dword aligned */
12005 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
12010 for (i = 0; i < len; i += 4, offset += 4) {
12011 u32 page_off, phy_addr, nvram_cmd;
12014 memcpy(&data, buf + i, 4);
12015 tw32(NVRAM_WRDATA, be32_to_cpu(data));
12017 page_off = offset % tp->nvram_pagesize;
12019 phy_addr = tg3_nvram_phys_addr(tp, offset);
12021 tw32(NVRAM_ADDR, phy_addr);
12023 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
12025 if ((page_off == 0) || (i == 0))
12026 nvram_cmd |= NVRAM_CMD_FIRST;
12027 if (page_off == (tp->nvram_pagesize - 4))
12028 nvram_cmd |= NVRAM_CMD_LAST;
12030 if (i == (len - 4))
12031 nvram_cmd |= NVRAM_CMD_LAST;
12033 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
12034 !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
12035 (tp->nvram_jedecnum == JEDEC_ST) &&
12036 (nvram_cmd & NVRAM_CMD_FIRST)) {
12038 if ((ret = tg3_nvram_exec_cmd(tp,
12039 NVRAM_CMD_WREN | NVRAM_CMD_GO |
12044 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
12045 /* We always do complete word writes to eeprom. */
12046 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
12049 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
12055 /* offset and length are dword aligned */
12056 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
12060 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
12061 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
12062 ~GRC_LCLCTRL_GPIO_OUTPUT1);
12066 if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
12067 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
12072 ret = tg3_nvram_lock(tp);
12076 tg3_enable_nvram_access(tp);
12077 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
12078 !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM))
12079 tw32(NVRAM_WRITE1, 0x406);
12081 grc_mode = tr32(GRC_MODE);
12082 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
12084 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
12085 !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
12087 ret = tg3_nvram_write_block_buffered(tp, offset, len,
12091 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
12095 grc_mode = tr32(GRC_MODE);
12096 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
12098 tg3_disable_nvram_access(tp);
12099 tg3_nvram_unlock(tp);
12102 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
12103 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
12110 struct subsys_tbl_ent {
12111 u16 subsys_vendor, subsys_devid;
12115 static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
12116 /* Broadcom boards. */
12117 { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
12118 { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
12119 { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
12120 { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 }, /* BCM95700A9 */
12121 { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
12122 { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
12123 { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 }, /* BCM95701A7 */
12124 { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
12125 { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
12126 { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
12127 { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
12130 { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
12131 { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
12132 { PCI_VENDOR_ID_3COM, 0x1004, 0 }, /* 3C996SX */
12133 { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
12134 { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
12137 { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
12138 { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
12139 { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
12140 { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
12142 /* Compaq boards. */
12143 { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
12144 { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
12145 { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 }, /* CHANGELING */
12146 { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
12147 { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
12150 { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
12153 static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
12157 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
12158 if ((subsys_id_to_phy_id[i].subsys_vendor ==
12159 tp->pdev->subsystem_vendor) &&
12160 (subsys_id_to_phy_id[i].subsys_devid ==
12161 tp->pdev->subsystem_device))
12162 return &subsys_id_to_phy_id[i];
12167 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
12172 /* On some early chips the SRAM cannot be accessed in D3hot state,
12173 * so need make sure we're in D0.
12175 pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
12176 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
12177 pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
12180 /* Make sure register accesses (indirect or otherwise)
12181 * will function correctly.
12183 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12184 tp->misc_host_ctrl);
12186 /* The memory arbiter has to be enabled in order for SRAM accesses
12187 * to succeed. Normally on powerup the tg3 chip firmware will make
12188 * sure it is enabled, but other entities such as system netboot
12189 * code might disable it.
12191 val = tr32(MEMARB_MODE);
12192 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
12194 tp->phy_id = PHY_ID_INVALID;
12195 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12197 /* Assume an onboard device and WOL capable by default. */
12198 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
12200 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12201 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
12202 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12203 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12205 val = tr32(VCPU_CFGSHDW);
12206 if (val & VCPU_CFGSHDW_ASPM_DBNC)
12207 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
12208 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
12209 (val & VCPU_CFGSHDW_WOL_MAGPKT))
12210 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12214 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
12215 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
12216 u32 nic_cfg, led_cfg;
12217 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
12218 int eeprom_phy_serdes = 0;
12220 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
12221 tp->nic_sram_data_cfg = nic_cfg;
12223 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
12224 ver >>= NIC_SRAM_DATA_VER_SHIFT;
12225 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
12226 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
12227 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
12228 (ver > 0) && (ver < 0x100))
12229 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
12231 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
12232 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
12234 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
12235 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
12236 eeprom_phy_serdes = 1;
12238 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
12239 if (nic_phy_id != 0) {
12240 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
12241 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
12243 eeprom_phy_id = (id1 >> 16) << 10;
12244 eeprom_phy_id |= (id2 & 0xfc00) << 16;
12245 eeprom_phy_id |= (id2 & 0x03ff) << 0;
12249 tp->phy_id = eeprom_phy_id;
12250 if (eeprom_phy_serdes) {
12251 if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
12252 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
12253 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
12255 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
12258 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
12259 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
12260 SHASTA_EXT_LED_MODE_MASK);
12262 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
12266 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
12267 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12270 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
12271 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12274 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
12275 tp->led_ctrl = LED_CTRL_MODE_MAC;
12277 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
12278 * read on some older 5700/5701 bootcode.
12280 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
12282 GET_ASIC_REV(tp->pci_chip_rev_id) ==
12284 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12288 case SHASTA_EXT_LED_SHARED:
12289 tp->led_ctrl = LED_CTRL_MODE_SHARED;
12290 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
12291 tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
12292 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12293 LED_CTRL_MODE_PHY_2);
12296 case SHASTA_EXT_LED_MAC:
12297 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
12300 case SHASTA_EXT_LED_COMBO:
12301 tp->led_ctrl = LED_CTRL_MODE_COMBO;
12302 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
12303 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12304 LED_CTRL_MODE_PHY_2);
12309 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12310 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
12311 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
12312 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12314 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
12315 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12317 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
12318 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
12319 if ((tp->pdev->subsystem_vendor ==
12320 PCI_VENDOR_ID_ARIMA) &&
12321 (tp->pdev->subsystem_device == 0x205a ||
12322 tp->pdev->subsystem_device == 0x2063))
12323 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12325 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12326 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12329 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
12330 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
12331 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
12332 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
12335 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
12336 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
12337 tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
12339 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
12340 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
12341 tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
12343 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
12344 (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
12345 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12347 if (cfg2 & (1 << 17))
12348 tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
12350 /* serdes signal pre-emphasis in register 0x590 set by */
12351 /* bootcode if bit 18 is set */
12352 if (cfg2 & (1 << 18))
12353 tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
12355 if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
12356 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
12357 (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
12358 tp->tg3_flags3 |= TG3_FLG3_PHY_ENABLE_APD;
12360 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12363 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
12364 if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
12365 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
12368 if (cfg4 & NIC_SRAM_RGMII_INBAND_DISABLE)
12369 tp->tg3_flags3 |= TG3_FLG3_RGMII_INBAND_DISABLE;
12370 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
12371 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
12372 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
12373 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
12376 device_init_wakeup(&tp->pdev->dev, tp->tg3_flags & TG3_FLAG_WOL_CAP);
12377 device_set_wakeup_enable(&tp->pdev->dev,
12378 tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
12381 static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
12386 tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
12387 tw32(OTP_CTRL, cmd);
12389 /* Wait for up to 1 ms for command to execute. */
12390 for (i = 0; i < 100; i++) {
12391 val = tr32(OTP_STATUS);
12392 if (val & OTP_STATUS_CMD_DONE)
12397 return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
12400 /* Read the gphy configuration from the OTP region of the chip. The gphy
12401 * configuration is a 32-bit value that straddles the alignment boundary.
12402 * We do two 32-bit reads and then shift and merge the results.
12404 static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
12406 u32 bhalf_otp, thalf_otp;
12408 tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
12410 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
12413 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
12415 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12418 thalf_otp = tr32(OTP_READ_DATA);
12420 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
12422 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12425 bhalf_otp = tr32(OTP_READ_DATA);
12427 return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
12430 static int __devinit tg3_phy_probe(struct tg3 *tp)
12432 u32 hw_phy_id_1, hw_phy_id_2;
12433 u32 hw_phy_id, hw_phy_id_masked;
12436 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
12437 return tg3_phy_init(tp);
12439 /* Reading the PHY ID register can conflict with ASF
12440 * firmware access to the PHY hardware.
12443 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12444 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
12445 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
12447 /* Now read the physical PHY_ID from the chip and verify
12448 * that it is sane. If it doesn't look good, we fall back
12449 * to either the hard-coded table based PHY_ID and failing
12450 * that the value found in the eeprom area.
12452 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
12453 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
12455 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
12456 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
12457 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
12459 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
12462 if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
12463 tp->phy_id = hw_phy_id;
12464 if (hw_phy_id_masked == PHY_ID_BCM8002)
12465 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
12467 tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
12469 if (tp->phy_id != PHY_ID_INVALID) {
12470 /* Do nothing, phy ID already set up in
12471 * tg3_get_eeprom_hw_cfg().
12474 struct subsys_tbl_ent *p;
12476 /* No eeprom signature? Try the hardcoded
12477 * subsys device table.
12479 p = lookup_by_subsys(tp);
12483 tp->phy_id = p->phy_id;
12485 tp->phy_id == PHY_ID_BCM8002)
12486 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
12490 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
12491 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
12492 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
12493 u32 bmsr, adv_reg, tg3_ctrl, mask;
12495 tg3_readphy(tp, MII_BMSR, &bmsr);
12496 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
12497 (bmsr & BMSR_LSTATUS))
12498 goto skip_phy_reset;
12500 err = tg3_phy_reset(tp);
12504 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
12505 ADVERTISE_100HALF | ADVERTISE_100FULL |
12506 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
12508 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
12509 tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
12510 MII_TG3_CTRL_ADV_1000_FULL);
12511 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12512 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
12513 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
12514 MII_TG3_CTRL_ENABLE_AS_MASTER);
12517 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
12518 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
12519 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
12520 if (!tg3_copper_is_advertising_all(tp, mask)) {
12521 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12523 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
12524 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12526 tg3_writephy(tp, MII_BMCR,
12527 BMCR_ANENABLE | BMCR_ANRESTART);
12529 tg3_phy_set_wirespeed(tp);
12531 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12532 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
12533 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12537 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
12538 err = tg3_init_5401phy_dsp(tp);
12543 if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
12544 err = tg3_init_5401phy_dsp(tp);
12547 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
12548 tp->link_config.advertising =
12549 (ADVERTISED_1000baseT_Half |
12550 ADVERTISED_1000baseT_Full |
12551 ADVERTISED_Autoneg |
12553 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
12554 tp->link_config.advertising &=
12555 ~(ADVERTISED_1000baseT_Half |
12556 ADVERTISED_1000baseT_Full);
12561 static void __devinit tg3_read_partno(struct tg3 *tp)
12563 unsigned char vpd_data[TG3_NVM_VPD_LEN]; /* in little-endian format */
12567 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
12568 tg3_nvram_read(tp, 0x0, &magic))
12569 goto out_not_found;
12571 if (magic == TG3_EEPROM_MAGIC) {
12572 for (i = 0; i < TG3_NVM_VPD_LEN; i += 4) {
12575 /* The data is in little-endian format in NVRAM.
12576 * Use the big-endian read routines to preserve
12577 * the byte order as it exists in NVRAM.
12579 if (tg3_nvram_read_be32(tp, TG3_NVM_VPD_OFF + i, &tmp))
12580 goto out_not_found;
12582 memcpy(&vpd_data[i], &tmp, sizeof(tmp));
12586 unsigned int pos = 0, i = 0;
12588 for (; pos < TG3_NVM_VPD_LEN && i < 3; i++, pos += cnt) {
12589 cnt = pci_read_vpd(tp->pdev, pos,
12590 TG3_NVM_VPD_LEN - pos,
12592 if (cnt == -ETIMEDOUT || -EINTR)
12595 goto out_not_found;
12597 if (pos != TG3_NVM_VPD_LEN)
12598 goto out_not_found;
12601 /* Now parse and find the part number. */
12602 for (i = 0; i < TG3_NVM_VPD_LEN - 2; ) {
12603 unsigned char val = vpd_data[i];
12604 unsigned int block_end;
12606 if (val == 0x82 || val == 0x91) {
12609 (vpd_data[i + 2] << 8)));
12614 goto out_not_found;
12616 block_end = (i + 3 +
12618 (vpd_data[i + 2] << 8)));
12621 if (block_end > TG3_NVM_VPD_LEN)
12622 goto out_not_found;
12624 while (i < (block_end - 2)) {
12625 if (vpd_data[i + 0] == 'P' &&
12626 vpd_data[i + 1] == 'N') {
12627 int partno_len = vpd_data[i + 2];
12630 if (partno_len > TG3_BPN_SIZE ||
12631 (partno_len + i) > TG3_NVM_VPD_LEN)
12632 goto out_not_found;
12634 memcpy(tp->board_part_number,
12635 &vpd_data[i], partno_len);
12640 i += 3 + vpd_data[i + 2];
12643 /* Part number not found. */
12644 goto out_not_found;
12648 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12649 strcpy(tp->board_part_number, "BCM95906");
12650 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12651 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
12652 strcpy(tp->board_part_number, "BCM57780");
12653 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12654 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
12655 strcpy(tp->board_part_number, "BCM57760");
12656 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12657 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
12658 strcpy(tp->board_part_number, "BCM57790");
12659 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12660 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
12661 strcpy(tp->board_part_number, "BCM57788");
12662 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12663 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761)
12664 strcpy(tp->board_part_number, "BCM57761");
12665 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12666 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765)
12667 strcpy(tp->board_part_number, "BCM57765");
12668 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12669 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781)
12670 strcpy(tp->board_part_number, "BCM57781");
12671 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12672 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785)
12673 strcpy(tp->board_part_number, "BCM57785");
12674 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12675 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791)
12676 strcpy(tp->board_part_number, "BCM57791");
12677 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12678 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
12679 strcpy(tp->board_part_number, "BCM57795");
12681 strcpy(tp->board_part_number, "none");
12684 static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
12688 if (tg3_nvram_read(tp, offset, &val) ||
12689 (val & 0xfc000000) != 0x0c000000 ||
12690 tg3_nvram_read(tp, offset + 4, &val) ||
12697 static void __devinit tg3_read_bc_ver(struct tg3 *tp)
12699 u32 val, offset, start, ver_offset;
12701 bool newver = false;
12703 if (tg3_nvram_read(tp, 0xc, &offset) ||
12704 tg3_nvram_read(tp, 0x4, &start))
12707 offset = tg3_nvram_logical_addr(tp, offset);
12709 if (tg3_nvram_read(tp, offset, &val))
12712 if ((val & 0xfc000000) == 0x0c000000) {
12713 if (tg3_nvram_read(tp, offset + 4, &val))
12721 if (tg3_nvram_read(tp, offset + 8, &ver_offset))
12724 offset = offset + ver_offset - start;
12725 for (i = 0; i < 16; i += 4) {
12727 if (tg3_nvram_read_be32(tp, offset + i, &v))
12730 memcpy(tp->fw_ver + i, &v, sizeof(v));
12735 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
12738 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
12739 TG3_NVM_BCVER_MAJSFT;
12740 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
12741 snprintf(&tp->fw_ver[0], 32, "v%d.%02d", major, minor);
12745 static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
12747 u32 val, major, minor;
12749 /* Use native endian representation */
12750 if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
12753 major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
12754 TG3_NVM_HWSB_CFG1_MAJSFT;
12755 minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
12756 TG3_NVM_HWSB_CFG1_MINSFT;
12758 snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
12761 static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
12763 u32 offset, major, minor, build;
12765 tp->fw_ver[0] = 's';
12766 tp->fw_ver[1] = 'b';
12767 tp->fw_ver[2] = '\0';
12769 if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
12772 switch (val & TG3_EEPROM_SB_REVISION_MASK) {
12773 case TG3_EEPROM_SB_REVISION_0:
12774 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
12776 case TG3_EEPROM_SB_REVISION_2:
12777 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
12779 case TG3_EEPROM_SB_REVISION_3:
12780 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
12782 case TG3_EEPROM_SB_REVISION_4:
12783 offset = TG3_EEPROM_SB_F1R4_EDH_OFF;
12785 case TG3_EEPROM_SB_REVISION_5:
12786 offset = TG3_EEPROM_SB_F1R5_EDH_OFF;
12792 if (tg3_nvram_read(tp, offset, &val))
12795 build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
12796 TG3_EEPROM_SB_EDH_BLD_SHFT;
12797 major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
12798 TG3_EEPROM_SB_EDH_MAJ_SHFT;
12799 minor = val & TG3_EEPROM_SB_EDH_MIN_MASK;
12801 if (minor > 99 || build > 26)
12804 snprintf(&tp->fw_ver[2], 30, " v%d.%02d", major, minor);
12807 tp->fw_ver[8] = 'a' + build - 1;
12808 tp->fw_ver[9] = '\0';
12812 static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
12814 u32 val, offset, start;
12817 for (offset = TG3_NVM_DIR_START;
12818 offset < TG3_NVM_DIR_END;
12819 offset += TG3_NVM_DIRENT_SIZE) {
12820 if (tg3_nvram_read(tp, offset, &val))
12823 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
12827 if (offset == TG3_NVM_DIR_END)
12830 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
12831 start = 0x08000000;
12832 else if (tg3_nvram_read(tp, offset - 4, &start))
12835 if (tg3_nvram_read(tp, offset + 4, &offset) ||
12836 !tg3_fw_img_is_valid(tp, offset) ||
12837 tg3_nvram_read(tp, offset + 8, &val))
12840 offset += val - start;
12842 vlen = strlen(tp->fw_ver);
12844 tp->fw_ver[vlen++] = ',';
12845 tp->fw_ver[vlen++] = ' ';
12847 for (i = 0; i < 4; i++) {
12849 if (tg3_nvram_read_be32(tp, offset, &v))
12852 offset += sizeof(v);
12854 if (vlen > TG3_VER_SIZE - sizeof(v)) {
12855 memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
12859 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
12864 static void __devinit tg3_read_dash_ver(struct tg3 *tp)
12869 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) ||
12870 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
12873 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
12874 if (apedata != APE_SEG_SIG_MAGIC)
12877 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
12878 if (!(apedata & APE_FW_STATUS_READY))
12881 apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
12883 vlen = strlen(tp->fw_ver);
12885 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " DASH v%d.%d.%d.%d",
12886 (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
12887 (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
12888 (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
12889 (apedata & APE_FW_VERSION_BLDMSK));
12892 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
12896 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) {
12897 tp->fw_ver[0] = 's';
12898 tp->fw_ver[1] = 'b';
12899 tp->fw_ver[2] = '\0';
12904 if (tg3_nvram_read(tp, 0, &val))
12907 if (val == TG3_EEPROM_MAGIC)
12908 tg3_read_bc_ver(tp);
12909 else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
12910 tg3_read_sb_ver(tp, val);
12911 else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
12912 tg3_read_hwsb_ver(tp);
12916 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12917 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
12920 tg3_read_mgmtfw_ver(tp);
12922 tp->fw_ver[TG3_VER_SIZE - 1] = 0;
12925 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
12927 static int __devinit tg3_get_invariants(struct tg3 *tp)
12929 static struct pci_device_id write_reorder_chipsets[] = {
12930 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12931 PCI_DEVICE_ID_AMD_FE_GATE_700C) },
12932 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12933 PCI_DEVICE_ID_AMD_8131_BRIDGE) },
12934 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
12935 PCI_DEVICE_ID_VIA_8385_0) },
12939 u32 pci_state_reg, grc_misc_cfg;
12944 /* Force memory write invalidate off. If we leave it on,
12945 * then on 5700_BX chips we have to enable a workaround.
12946 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
12947 * to match the cacheline size. The Broadcom driver have this
12948 * workaround but turns MWI off all the times so never uses
12949 * it. This seems to suggest that the workaround is insufficient.
12951 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12952 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
12953 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12955 /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
12956 * has the register indirect write enable bit set before
12957 * we try to access any of the MMIO registers. It is also
12958 * critical that the PCI-X hw workaround situation is decided
12959 * before that as well.
12961 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12964 tp->pci_chip_rev_id = (misc_ctrl_reg >>
12965 MISC_HOST_CTRL_CHIPREV_SHIFT);
12966 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
12967 u32 prod_id_asic_rev;
12969 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
12970 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
12971 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5724)
12972 pci_read_config_dword(tp->pdev,
12973 TG3PCI_GEN2_PRODID_ASICREV,
12974 &prod_id_asic_rev);
12975 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 ||
12976 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 ||
12977 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 ||
12978 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 ||
12979 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
12980 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
12981 pci_read_config_dword(tp->pdev,
12982 TG3PCI_GEN15_PRODID_ASICREV,
12983 &prod_id_asic_rev);
12985 pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
12986 &prod_id_asic_rev);
12988 tp->pci_chip_rev_id = prod_id_asic_rev;
12991 /* Wrong chip ID in 5752 A0. This code can be removed later
12992 * as A0 is not in production.
12994 if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
12995 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
12997 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
12998 * we need to disable memory and use config. cycles
12999 * only to access all registers. The 5702/03 chips
13000 * can mistakenly decode the special cycles from the
13001 * ICH chipsets as memory write cycles, causing corruption
13002 * of register and memory space. Only certain ICH bridges
13003 * will drive special cycles with non-zero data during the
13004 * address phase which can fall within the 5703's address
13005 * range. This is not an ICH bug as the PCI spec allows
13006 * non-zero address during special cycles. However, only
13007 * these ICH bridges are known to drive non-zero addresses
13008 * during special cycles.
13010 * Since special cycles do not cross PCI bridges, we only
13011 * enable this workaround if the 5703 is on the secondary
13012 * bus of these ICH bridges.
13014 if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
13015 (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
13016 static struct tg3_dev_id {
13020 } ich_chipsets[] = {
13021 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
13023 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
13025 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
13027 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
13031 struct tg3_dev_id *pci_id = &ich_chipsets[0];
13032 struct pci_dev *bridge = NULL;
13034 while (pci_id->vendor != 0) {
13035 bridge = pci_get_device(pci_id->vendor, pci_id->device,
13041 if (pci_id->rev != PCI_ANY_ID) {
13042 if (bridge->revision > pci_id->rev)
13045 if (bridge->subordinate &&
13046 (bridge->subordinate->number ==
13047 tp->pdev->bus->number)) {
13049 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
13050 pci_dev_put(bridge);
13056 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
13057 static struct tg3_dev_id {
13060 } bridge_chipsets[] = {
13061 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
13062 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
13065 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
13066 struct pci_dev *bridge = NULL;
13068 while (pci_id->vendor != 0) {
13069 bridge = pci_get_device(pci_id->vendor,
13076 if (bridge->subordinate &&
13077 (bridge->subordinate->number <=
13078 tp->pdev->bus->number) &&
13079 (bridge->subordinate->subordinate >=
13080 tp->pdev->bus->number)) {
13081 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
13082 pci_dev_put(bridge);
13088 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
13089 * DMA addresses > 40-bit. This bridge may have other additional
13090 * 57xx devices behind it in some 4-port NIC designs for example.
13091 * Any tg3 device found behind the bridge will also need the 40-bit
13094 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
13095 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
13096 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
13097 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
13098 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
13101 struct pci_dev *bridge = NULL;
13104 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
13105 PCI_DEVICE_ID_SERVERWORKS_EPB,
13107 if (bridge && bridge->subordinate &&
13108 (bridge->subordinate->number <=
13109 tp->pdev->bus->number) &&
13110 (bridge->subordinate->subordinate >=
13111 tp->pdev->bus->number)) {
13112 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
13113 pci_dev_put(bridge);
13119 /* Initialize misc host control in PCI block. */
13120 tp->misc_host_ctrl |= (misc_ctrl_reg &
13121 MISC_HOST_CTRL_CHIPREV);
13122 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13123 tp->misc_host_ctrl);
13125 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
13126 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
13127 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
13128 tp->pdev_peer = tg3_find_peer(tp);
13130 /* Intentionally exclude ASIC_REV_5906 */
13131 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13132 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
13133 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13134 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13135 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13136 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13137 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13138 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13139 tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
13141 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13142 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13143 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
13144 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13145 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
13146 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
13148 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
13149 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
13150 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
13152 /* 5700 B0 chips do not support checksumming correctly due
13153 * to hardware bugs.
13155 if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
13156 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
13158 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
13159 tp->dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
13160 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
13161 tp->dev->features |= NETIF_F_IPV6_CSUM;
13164 /* Determine TSO capabilities */
13165 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13166 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13167 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_3;
13168 else if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13169 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13170 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
13171 else if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
13172 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
13173 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 &&
13174 tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
13175 tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
13176 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13177 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13178 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
13179 tp->tg3_flags2 |= TG3_FLG2_TSO_BUG;
13180 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
13181 tp->fw_needed = FIRMWARE_TG3TSO5;
13183 tp->fw_needed = FIRMWARE_TG3TSO;
13188 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
13189 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
13190 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
13191 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
13192 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
13193 tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
13194 tp->pdev_peer == tp->pdev))
13195 tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
13197 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13198 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13199 tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
13202 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13203 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
13204 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSIX;
13205 tp->irq_max = TG3_IRQ_MAX_VECS;
13209 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13210 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13211 tp->tg3_flags3 |= TG3_FLG3_SHORT_DMA_BUG;
13212 else if (!(tp->tg3_flags3 & TG3_FLG3_5755_PLUS)) {
13213 tp->tg3_flags3 |= TG3_FLG3_4G_DMA_BNDRY_BUG;
13214 tp->tg3_flags3 |= TG3_FLG3_40BIT_DMA_LIMIT_BUG;
13217 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13218 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13219 tp->tg3_flags3 |= TG3_FLG3_USE_JUMBO_BDFLAG;
13221 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
13222 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
13223 (tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG))
13224 tp->tg3_flags |= TG3_FLAG_JUMBO_CAPABLE;
13226 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13229 tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
13230 if (tp->pcie_cap != 0) {
13233 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
13235 pcie_set_readrq(tp->pdev, 4096);
13237 pci_read_config_word(tp->pdev,
13238 tp->pcie_cap + PCI_EXP_LNKCTL,
13240 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
13241 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13242 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
13243 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13244 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13245 tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
13246 tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
13247 tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
13248 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5717_A0) {
13249 tp->tg3_flags3 |= TG3_FLG3_L1PLLPD_EN;
13251 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
13252 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
13253 } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
13254 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13255 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
13256 if (!tp->pcix_cap) {
13257 printk(KERN_ERR PFX "Cannot find PCI-X "
13258 "capability, aborting.\n");
13262 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
13263 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
13266 /* If we have an AMD 762 or VIA K8T800 chipset, write
13267 * reordering to the mailbox registers done by the host
13268 * controller can cause major troubles. We read back from
13269 * every mailbox register write to force the writes to be
13270 * posted to the chip in order.
13272 if (pci_dev_present(write_reorder_chipsets) &&
13273 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13274 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
13276 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
13277 &tp->pci_cacheline_sz);
13278 pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13279 &tp->pci_lat_timer);
13280 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13281 tp->pci_lat_timer < 64) {
13282 tp->pci_lat_timer = 64;
13283 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13284 tp->pci_lat_timer);
13287 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
13288 /* 5700 BX chips need to have their TX producer index
13289 * mailboxes written twice to workaround a bug.
13291 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
13293 /* If we are in PCI-X mode, enable register write workaround.
13295 * The workaround is to use indirect register accesses
13296 * for all chip writes not to mailbox registers.
13298 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
13301 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13303 /* The chip can have it's power management PCI config
13304 * space registers clobbered due to this bug.
13305 * So explicitly force the chip into D0 here.
13307 pci_read_config_dword(tp->pdev,
13308 tp->pm_cap + PCI_PM_CTRL,
13310 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
13311 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
13312 pci_write_config_dword(tp->pdev,
13313 tp->pm_cap + PCI_PM_CTRL,
13316 /* Also, force SERR#/PERR# in PCI command. */
13317 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13318 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
13319 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13323 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
13324 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
13325 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
13326 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
13328 /* Chip-specific fixup from Broadcom driver */
13329 if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
13330 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
13331 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
13332 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
13335 /* Default fast path register access methods */
13336 tp->read32 = tg3_read32;
13337 tp->write32 = tg3_write32;
13338 tp->read32_mbox = tg3_read32;
13339 tp->write32_mbox = tg3_write32;
13340 tp->write32_tx_mbox = tg3_write32;
13341 tp->write32_rx_mbox = tg3_write32;
13343 /* Various workaround register access methods */
13344 if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
13345 tp->write32 = tg3_write_indirect_reg32;
13346 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
13347 ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
13348 tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
13350 * Back to back register writes can cause problems on these
13351 * chips, the workaround is to read back all reg writes
13352 * except those to mailbox regs.
13354 * See tg3_write_indirect_reg32().
13356 tp->write32 = tg3_write_flush_reg32;
13359 if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
13360 (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
13361 tp->write32_tx_mbox = tg3_write32_tx_mbox;
13362 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
13363 tp->write32_rx_mbox = tg3_write_flush_reg32;
13366 if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
13367 tp->read32 = tg3_read_indirect_reg32;
13368 tp->write32 = tg3_write_indirect_reg32;
13369 tp->read32_mbox = tg3_read_indirect_mbox;
13370 tp->write32_mbox = tg3_write_indirect_mbox;
13371 tp->write32_tx_mbox = tg3_write_indirect_mbox;
13372 tp->write32_rx_mbox = tg3_write_indirect_mbox;
13377 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13378 pci_cmd &= ~PCI_COMMAND_MEMORY;
13379 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13381 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13382 tp->read32_mbox = tg3_read32_mbox_5906;
13383 tp->write32_mbox = tg3_write32_mbox_5906;
13384 tp->write32_tx_mbox = tg3_write32_mbox_5906;
13385 tp->write32_rx_mbox = tg3_write32_mbox_5906;
13388 if (tp->write32 == tg3_write_indirect_reg32 ||
13389 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13390 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13391 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
13392 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
13394 /* Get eeprom hw config before calling tg3_set_power_state().
13395 * In particular, the TG3_FLG2_IS_NIC flag must be
13396 * determined before calling tg3_set_power_state() so that
13397 * we know whether or not to switch out of Vaux power.
13398 * When the flag is set, it means that GPIO1 is used for eeprom
13399 * write protect and also implies that it is a LOM where GPIOs
13400 * are not used to switch power.
13402 tg3_get_eeprom_hw_cfg(tp);
13404 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
13405 /* Allow reads and writes to the
13406 * APE register and memory space.
13408 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
13409 PCISTATE_ALLOW_APE_SHMEM_WR;
13410 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
13414 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13415 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13416 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13417 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13418 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13419 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13420 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
13422 /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
13423 * GPIO1 driven high will bring 5700's external PHY out of reset.
13424 * It is also used as eeprom write protect on LOMs.
13426 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
13427 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13428 (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
13429 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
13430 GRC_LCLCTRL_GPIO_OUTPUT1);
13431 /* Unused GPIO3 must be driven as output on 5752 because there
13432 * are no pull-up resistors on unused GPIO pins.
13434 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
13435 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
13437 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13438 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13439 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13440 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13442 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
13443 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
13444 /* Turn off the debug UART. */
13445 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13446 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
13447 /* Keep VMain power. */
13448 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
13449 GRC_LCLCTRL_GPIO_OUTPUT0;
13452 /* Force the chip into D0. */
13453 err = tg3_set_power_state(tp, PCI_D0);
13455 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
13456 pci_name(tp->pdev));
13460 /* Derive initial jumbo mode from MTU assigned in
13461 * ether_setup() via the alloc_etherdev() call
13463 if (tp->dev->mtu > ETH_DATA_LEN &&
13464 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
13465 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
13467 /* Determine WakeOnLan speed to use. */
13468 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13469 tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
13470 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
13471 tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
13472 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
13474 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
13477 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13478 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
13480 /* A few boards don't want Ethernet@WireSpeed phy feature */
13481 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13482 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
13483 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
13484 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
13485 (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) ||
13486 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
13487 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
13489 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
13490 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
13491 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
13492 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
13493 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
13495 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
13496 !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
13497 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
13498 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 &&
13499 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
13500 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765) {
13501 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13502 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
13503 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13504 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
13505 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
13506 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
13507 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
13508 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
13509 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
13511 tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
13514 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13515 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
13516 tp->phy_otp = tg3_read_otp_phycfg(tp);
13517 if (tp->phy_otp == 0)
13518 tp->phy_otp = TG3_OTP_DEFAULT;
13521 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
13522 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
13524 tp->mi_mode = MAC_MI_MODE_BASE;
13526 tp->coalesce_mode = 0;
13527 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
13528 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
13529 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
13531 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13532 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
13533 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
13535 err = tg3_mdio_init(tp);
13539 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
13540 (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0 ||
13541 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
13544 /* Initialize data/descriptor byte/word swapping. */
13545 val = tr32(GRC_MODE);
13546 val &= GRC_MODE_HOST_STACKUP;
13547 tw32(GRC_MODE, val | tp->grc_mode);
13549 tg3_switch_clocks(tp);
13551 /* Clear this out for sanity. */
13552 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
13554 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13556 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
13557 (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
13558 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
13560 if (chiprevid == CHIPREV_ID_5701_A0 ||
13561 chiprevid == CHIPREV_ID_5701_B0 ||
13562 chiprevid == CHIPREV_ID_5701_B2 ||
13563 chiprevid == CHIPREV_ID_5701_B5) {
13564 void __iomem *sram_base;
13566 /* Write some dummy words into the SRAM status block
13567 * area, see if it reads back correctly. If the return
13568 * value is bad, force enable the PCIX workaround.
13570 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
13572 writel(0x00000000, sram_base);
13573 writel(0x00000000, sram_base + 4);
13574 writel(0xffffffff, sram_base + 4);
13575 if (readl(sram_base) != 0x00000000)
13576 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13581 tg3_nvram_init(tp);
13583 grc_misc_cfg = tr32(GRC_MISC_CFG);
13584 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
13586 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13587 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
13588 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
13589 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
13591 if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
13592 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
13593 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
13594 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
13595 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
13596 HOSTCC_MODE_CLRTICK_TXBD);
13598 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
13599 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13600 tp->misc_host_ctrl);
13603 /* Preserve the APE MAC_MODE bits */
13604 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
13605 tp->mac_mode = tr32(MAC_MODE) |
13606 MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
13608 tp->mac_mode = TG3_DEF_MAC_MODE;
13610 /* these are limited to 10/100 only */
13611 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13612 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
13613 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13614 tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13615 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
13616 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
13617 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
13618 (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13619 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
13620 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
13621 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
13622 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
13623 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
13624 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 ||
13625 (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
13626 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
13628 err = tg3_phy_probe(tp);
13630 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
13631 pci_name(tp->pdev), err);
13632 /* ... but do not return immediately ... */
13636 tg3_read_partno(tp);
13637 tg3_read_fw_ver(tp);
13639 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
13640 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
13642 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13643 tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
13645 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
13648 /* 5700 {AX,BX} chips have a broken status block link
13649 * change bit implementation, so we must use the
13650 * status register in those cases.
13652 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13653 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
13655 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
13657 /* The led_ctrl is set during tg3_phy_probe, here we might
13658 * have to force the link status polling mechanism based
13659 * upon subsystem IDs.
13661 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
13662 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13663 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
13664 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
13665 TG3_FLAG_USE_LINKCHG_REG);
13668 /* For all SERDES we poll the MAC status register. */
13669 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
13670 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
13672 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
13674 tp->rx_offset = NET_IP_ALIGN;
13675 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13676 (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
13679 tp->rx_std_max_post = TG3_RX_RING_SIZE;
13681 /* Increment the rx prod index on the rx std ring by at most
13682 * 8 for these chips to workaround hw errata.
13684 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13685 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13686 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
13687 tp->rx_std_max_post = 8;
13689 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
13690 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
13691 PCIE_PWR_MGMT_L1_THRESH_MSK;
13696 #ifdef CONFIG_SPARC
13697 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
13699 struct net_device *dev = tp->dev;
13700 struct pci_dev *pdev = tp->pdev;
13701 struct device_node *dp = pci_device_to_OF_node(pdev);
13702 const unsigned char *addr;
13705 addr = of_get_property(dp, "local-mac-address", &len);
13706 if (addr && len == 6) {
13707 memcpy(dev->dev_addr, addr, 6);
13708 memcpy(dev->perm_addr, dev->dev_addr, 6);
13714 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
13716 struct net_device *dev = tp->dev;
13718 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
13719 memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
13724 static int __devinit tg3_get_device_address(struct tg3 *tp)
13726 struct net_device *dev = tp->dev;
13727 u32 hi, lo, mac_offset;
13730 #ifdef CONFIG_SPARC
13731 if (!tg3_get_macaddr_sparc(tp))
13736 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
13737 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13738 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
13740 if (tg3_nvram_lock(tp))
13741 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
13743 tg3_nvram_unlock(tp);
13744 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
13745 if (tr32(TG3_CPMU_STATUS) & TG3_CPMU_STATUS_PCIE_FUNC)
13747 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13750 /* First try to get it from MAC address mailbox. */
13751 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
13752 if ((hi >> 16) == 0x484b) {
13753 dev->dev_addr[0] = (hi >> 8) & 0xff;
13754 dev->dev_addr[1] = (hi >> 0) & 0xff;
13756 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
13757 dev->dev_addr[2] = (lo >> 24) & 0xff;
13758 dev->dev_addr[3] = (lo >> 16) & 0xff;
13759 dev->dev_addr[4] = (lo >> 8) & 0xff;
13760 dev->dev_addr[5] = (lo >> 0) & 0xff;
13762 /* Some old bootcode may report a 0 MAC address in SRAM */
13763 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
13766 /* Next, try NVRAM. */
13767 if (!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) &&
13768 !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
13769 !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
13770 memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
13771 memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
13773 /* Finally just fetch it out of the MAC control regs. */
13775 hi = tr32(MAC_ADDR_0_HIGH);
13776 lo = tr32(MAC_ADDR_0_LOW);
13778 dev->dev_addr[5] = lo & 0xff;
13779 dev->dev_addr[4] = (lo >> 8) & 0xff;
13780 dev->dev_addr[3] = (lo >> 16) & 0xff;
13781 dev->dev_addr[2] = (lo >> 24) & 0xff;
13782 dev->dev_addr[1] = hi & 0xff;
13783 dev->dev_addr[0] = (hi >> 8) & 0xff;
13787 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
13788 #ifdef CONFIG_SPARC
13789 if (!tg3_get_default_macaddr_sparc(tp))
13794 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
13798 #define BOUNDARY_SINGLE_CACHELINE 1
13799 #define BOUNDARY_MULTI_CACHELINE 2
13801 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
13803 int cacheline_size;
13807 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
13809 cacheline_size = 1024;
13811 cacheline_size = (int) byte * 4;
13813 /* On 5703 and later chips, the boundary bits have no
13816 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13817 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13818 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13821 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
13822 goal = BOUNDARY_MULTI_CACHELINE;
13824 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
13825 goal = BOUNDARY_SINGLE_CACHELINE;
13831 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13832 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
13833 val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
13840 /* PCI controllers on most RISC systems tend to disconnect
13841 * when a device tries to burst across a cache-line boundary.
13842 * Therefore, letting tg3 do so just wastes PCI bandwidth.
13844 * Unfortunately, for PCI-E there are only limited
13845 * write-side controls for this, and thus for reads
13846 * we will still get the disconnects. We'll also waste
13847 * these PCI cycles for both read and write for chips
13848 * other than 5700 and 5701 which do not implement the
13851 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13852 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
13853 switch (cacheline_size) {
13858 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13859 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
13860 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
13862 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13863 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13868 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
13869 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
13873 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13874 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13877 } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13878 switch (cacheline_size) {
13882 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13883 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13884 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
13890 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13891 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
13895 switch (cacheline_size) {
13897 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13898 val |= (DMA_RWCTRL_READ_BNDRY_16 |
13899 DMA_RWCTRL_WRITE_BNDRY_16);
13904 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13905 val |= (DMA_RWCTRL_READ_BNDRY_32 |
13906 DMA_RWCTRL_WRITE_BNDRY_32);
13911 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13912 val |= (DMA_RWCTRL_READ_BNDRY_64 |
13913 DMA_RWCTRL_WRITE_BNDRY_64);
13918 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13919 val |= (DMA_RWCTRL_READ_BNDRY_128 |
13920 DMA_RWCTRL_WRITE_BNDRY_128);
13925 val |= (DMA_RWCTRL_READ_BNDRY_256 |
13926 DMA_RWCTRL_WRITE_BNDRY_256);
13929 val |= (DMA_RWCTRL_READ_BNDRY_512 |
13930 DMA_RWCTRL_WRITE_BNDRY_512);
13934 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
13935 DMA_RWCTRL_WRITE_BNDRY_1024);
13944 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
13946 struct tg3_internal_buffer_desc test_desc;
13947 u32 sram_dma_descs;
13950 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
13952 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
13953 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
13954 tw32(RDMAC_STATUS, 0);
13955 tw32(WDMAC_STATUS, 0);
13957 tw32(BUFMGR_MODE, 0);
13958 tw32(FTQ_RESET, 0);
13960 test_desc.addr_hi = ((u64) buf_dma) >> 32;
13961 test_desc.addr_lo = buf_dma & 0xffffffff;
13962 test_desc.nic_mbuf = 0x00002100;
13963 test_desc.len = size;
13966 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
13967 * the *second* time the tg3 driver was getting loaded after an
13970 * Broadcom tells me:
13971 * ...the DMA engine is connected to the GRC block and a DMA
13972 * reset may affect the GRC block in some unpredictable way...
13973 * The behavior of resets to individual blocks has not been tested.
13975 * Broadcom noted the GRC reset will also reset all sub-components.
13978 test_desc.cqid_sqid = (13 << 8) | 2;
13980 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
13983 test_desc.cqid_sqid = (16 << 8) | 7;
13985 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
13988 test_desc.flags = 0x00000005;
13990 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
13993 val = *(((u32 *)&test_desc) + i);
13994 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
13995 sram_dma_descs + (i * sizeof(u32)));
13996 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
13998 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
14001 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
14003 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
14007 for (i = 0; i < 40; i++) {
14011 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
14013 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
14014 if ((val & 0xffff) == sram_dma_descs) {
14025 #define TEST_BUFFER_SIZE 0x2000
14027 static int __devinit tg3_test_dma(struct tg3 *tp)
14029 dma_addr_t buf_dma;
14030 u32 *buf, saved_dma_rwctrl;
14033 buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
14039 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
14040 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
14042 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
14044 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
14045 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
14048 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
14049 /* DMA read watermark not used on PCIE */
14050 tp->dma_rwctrl |= 0x00180000;
14051 } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
14052 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
14053 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
14054 tp->dma_rwctrl |= 0x003f0000;
14056 tp->dma_rwctrl |= 0x003f000f;
14058 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
14059 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
14060 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
14061 u32 read_water = 0x7;
14063 /* If the 5704 is behind the EPB bridge, we can
14064 * do the less restrictive ONE_DMA workaround for
14065 * better performance.
14067 if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
14068 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
14069 tp->dma_rwctrl |= 0x8000;
14070 else if (ccval == 0x6 || ccval == 0x7)
14071 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
14073 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
14075 /* Set bit 23 to enable PCIX hw bug fix */
14077 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
14078 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
14080 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
14081 /* 5780 always in PCIX mode */
14082 tp->dma_rwctrl |= 0x00144000;
14083 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
14084 /* 5714 always in PCIX mode */
14085 tp->dma_rwctrl |= 0x00148000;
14087 tp->dma_rwctrl |= 0x001b000f;
14091 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
14092 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
14093 tp->dma_rwctrl &= 0xfffffff0;
14095 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
14096 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
14097 /* Remove this if it causes problems for some boards. */
14098 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
14100 /* On 5700/5701 chips, we need to set this bit.
14101 * Otherwise the chip will issue cacheline transactions
14102 * to streamable DMA memory with not all the byte
14103 * enables turned on. This is an error on several
14104 * RISC PCI controllers, in particular sparc64.
14106 * On 5703/5704 chips, this bit has been reassigned
14107 * a different meaning. In particular, it is used
14108 * on those chips to enable a PCI-X workaround.
14110 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
14113 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14116 /* Unneeded, already done by tg3_get_invariants. */
14117 tg3_switch_clocks(tp);
14120 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
14121 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
14124 /* It is best to perform DMA test with maximum write burst size
14125 * to expose the 5700/5701 write DMA bug.
14127 saved_dma_rwctrl = tp->dma_rwctrl;
14128 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14129 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14134 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
14137 /* Send the buffer to the chip. */
14138 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
14140 printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
14145 /* validate data reached card RAM correctly. */
14146 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
14148 tg3_read_mem(tp, 0x2100 + (i*4), &val);
14149 if (le32_to_cpu(val) != p[i]) {
14150 printk(KERN_ERR " tg3_test_dma() Card buffer corrupted on write! (%d != %d)\n", val, i);
14151 /* ret = -ENODEV here? */
14156 /* Now read it back. */
14157 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
14159 printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
14165 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
14169 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
14170 DMA_RWCTRL_WRITE_BNDRY_16) {
14171 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14172 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14173 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14176 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
14182 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
14188 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
14189 DMA_RWCTRL_WRITE_BNDRY_16) {
14190 static struct pci_device_id dma_wait_state_chipsets[] = {
14191 { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
14192 PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
14196 /* DMA test passed without adjusting DMA boundary,
14197 * now look for chipsets that are known to expose the
14198 * DMA bug without failing the test.
14200 if (pci_dev_present(dma_wait_state_chipsets)) {
14201 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14202 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14205 /* Safe to use the calculated DMA boundary. */
14206 tp->dma_rwctrl = saved_dma_rwctrl;
14208 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14212 pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
14217 static void __devinit tg3_init_link_config(struct tg3 *tp)
14219 tp->link_config.advertising =
14220 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
14221 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
14222 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
14223 ADVERTISED_Autoneg | ADVERTISED_MII);
14224 tp->link_config.speed = SPEED_INVALID;
14225 tp->link_config.duplex = DUPLEX_INVALID;
14226 tp->link_config.autoneg = AUTONEG_ENABLE;
14227 tp->link_config.active_speed = SPEED_INVALID;
14228 tp->link_config.active_duplex = DUPLEX_INVALID;
14229 tp->link_config.phy_is_low_power = 0;
14230 tp->link_config.orig_speed = SPEED_INVALID;
14231 tp->link_config.orig_duplex = DUPLEX_INVALID;
14232 tp->link_config.orig_autoneg = AUTONEG_INVALID;
14235 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
14237 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
14238 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
14239 tp->bufmgr_config.mbuf_read_dma_low_water =
14240 DEFAULT_MB_RDMA_LOW_WATER_5705;
14241 tp->bufmgr_config.mbuf_mac_rx_low_water =
14242 DEFAULT_MB_MACRX_LOW_WATER_57765;
14243 tp->bufmgr_config.mbuf_high_water =
14244 DEFAULT_MB_HIGH_WATER_57765;
14246 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14247 DEFAULT_MB_RDMA_LOW_WATER_5705;
14248 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14249 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765;
14250 tp->bufmgr_config.mbuf_high_water_jumbo =
14251 DEFAULT_MB_HIGH_WATER_JUMBO_57765;
14252 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
14253 tp->bufmgr_config.mbuf_read_dma_low_water =
14254 DEFAULT_MB_RDMA_LOW_WATER_5705;
14255 tp->bufmgr_config.mbuf_mac_rx_low_water =
14256 DEFAULT_MB_MACRX_LOW_WATER_5705;
14257 tp->bufmgr_config.mbuf_high_water =
14258 DEFAULT_MB_HIGH_WATER_5705;
14259 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
14260 tp->bufmgr_config.mbuf_mac_rx_low_water =
14261 DEFAULT_MB_MACRX_LOW_WATER_5906;
14262 tp->bufmgr_config.mbuf_high_water =
14263 DEFAULT_MB_HIGH_WATER_5906;
14266 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14267 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
14268 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14269 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
14270 tp->bufmgr_config.mbuf_high_water_jumbo =
14271 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
14273 tp->bufmgr_config.mbuf_read_dma_low_water =
14274 DEFAULT_MB_RDMA_LOW_WATER;
14275 tp->bufmgr_config.mbuf_mac_rx_low_water =
14276 DEFAULT_MB_MACRX_LOW_WATER;
14277 tp->bufmgr_config.mbuf_high_water =
14278 DEFAULT_MB_HIGH_WATER;
14280 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14281 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
14282 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14283 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
14284 tp->bufmgr_config.mbuf_high_water_jumbo =
14285 DEFAULT_MB_HIGH_WATER_JUMBO;
14288 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
14289 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
14292 static char * __devinit tg3_phy_string(struct tg3 *tp)
14294 switch (tp->phy_id & PHY_ID_MASK) {
14295 case PHY_ID_BCM5400: return "5400";
14296 case PHY_ID_BCM5401: return "5401";
14297 case PHY_ID_BCM5411: return "5411";
14298 case PHY_ID_BCM5701: return "5701";
14299 case PHY_ID_BCM5703: return "5703";
14300 case PHY_ID_BCM5704: return "5704";
14301 case PHY_ID_BCM5705: return "5705";
14302 case PHY_ID_BCM5750: return "5750";
14303 case PHY_ID_BCM5752: return "5752";
14304 case PHY_ID_BCM5714: return "5714";
14305 case PHY_ID_BCM5780: return "5780";
14306 case PHY_ID_BCM5755: return "5755";
14307 case PHY_ID_BCM5787: return "5787";
14308 case PHY_ID_BCM5784: return "5784";
14309 case PHY_ID_BCM5756: return "5722/5756";
14310 case PHY_ID_BCM5906: return "5906";
14311 case PHY_ID_BCM5761: return "5761";
14312 case PHY_ID_BCM5718C: return "5718C";
14313 case PHY_ID_BCM5718S: return "5718S";
14314 case PHY_ID_BCM57765: return "57765";
14315 case PHY_ID_BCM8002: return "8002/serdes";
14316 case 0: return "serdes";
14317 default: return "unknown";
14321 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
14323 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
14324 strcpy(str, "PCI Express");
14326 } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
14327 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
14329 strcpy(str, "PCIX:");
14331 if ((clock_ctrl == 7) ||
14332 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
14333 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
14334 strcat(str, "133MHz");
14335 else if (clock_ctrl == 0)
14336 strcat(str, "33MHz");
14337 else if (clock_ctrl == 2)
14338 strcat(str, "50MHz");
14339 else if (clock_ctrl == 4)
14340 strcat(str, "66MHz");
14341 else if (clock_ctrl == 6)
14342 strcat(str, "100MHz");
14344 strcpy(str, "PCI:");
14345 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
14346 strcat(str, "66MHz");
14348 strcat(str, "33MHz");
14350 if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
14351 strcat(str, ":32-bit");
14353 strcat(str, ":64-bit");
14357 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
14359 struct pci_dev *peer;
14360 unsigned int func, devnr = tp->pdev->devfn & ~7;
14362 for (func = 0; func < 8; func++) {
14363 peer = pci_get_slot(tp->pdev->bus, devnr | func);
14364 if (peer && peer != tp->pdev)
14368 /* 5704 can be configured in single-port mode, set peer to
14369 * tp->pdev in that case.
14377 * We don't need to keep the refcount elevated; there's no way
14378 * to remove one half of this device without removing the other
14385 static void __devinit tg3_init_coal(struct tg3 *tp)
14387 struct ethtool_coalesce *ec = &tp->coal;
14389 memset(ec, 0, sizeof(*ec));
14390 ec->cmd = ETHTOOL_GCOALESCE;
14391 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
14392 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
14393 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
14394 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
14395 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
14396 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
14397 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
14398 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
14399 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
14401 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
14402 HOSTCC_MODE_CLRTICK_TXBD)) {
14403 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
14404 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
14405 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
14406 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
14409 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
14410 ec->rx_coalesce_usecs_irq = 0;
14411 ec->tx_coalesce_usecs_irq = 0;
14412 ec->stats_block_coalesce_usecs = 0;
14416 static const struct net_device_ops tg3_netdev_ops = {
14417 .ndo_open = tg3_open,
14418 .ndo_stop = tg3_close,
14419 .ndo_start_xmit = tg3_start_xmit,
14420 .ndo_get_stats = tg3_get_stats,
14421 .ndo_validate_addr = eth_validate_addr,
14422 .ndo_set_multicast_list = tg3_set_rx_mode,
14423 .ndo_set_mac_address = tg3_set_mac_addr,
14424 .ndo_do_ioctl = tg3_ioctl,
14425 .ndo_tx_timeout = tg3_tx_timeout,
14426 .ndo_change_mtu = tg3_change_mtu,
14427 #if TG3_VLAN_TAG_USED
14428 .ndo_vlan_rx_register = tg3_vlan_rx_register,
14430 #ifdef CONFIG_NET_POLL_CONTROLLER
14431 .ndo_poll_controller = tg3_poll_controller,
14435 static const struct net_device_ops tg3_netdev_ops_dma_bug = {
14436 .ndo_open = tg3_open,
14437 .ndo_stop = tg3_close,
14438 .ndo_start_xmit = tg3_start_xmit_dma_bug,
14439 .ndo_get_stats = tg3_get_stats,
14440 .ndo_validate_addr = eth_validate_addr,
14441 .ndo_set_multicast_list = tg3_set_rx_mode,
14442 .ndo_set_mac_address = tg3_set_mac_addr,
14443 .ndo_do_ioctl = tg3_ioctl,
14444 .ndo_tx_timeout = tg3_tx_timeout,
14445 .ndo_change_mtu = tg3_change_mtu,
14446 #if TG3_VLAN_TAG_USED
14447 .ndo_vlan_rx_register = tg3_vlan_rx_register,
14449 #ifdef CONFIG_NET_POLL_CONTROLLER
14450 .ndo_poll_controller = tg3_poll_controller,
14454 static int __devinit tg3_init_one(struct pci_dev *pdev,
14455 const struct pci_device_id *ent)
14457 static int tg3_version_printed = 0;
14458 struct net_device *dev;
14460 int i, err, pm_cap;
14461 u32 sndmbx, rcvmbx, intmbx;
14463 u64 dma_mask, persist_dma_mask;
14465 if (tg3_version_printed++ == 0)
14466 printk(KERN_INFO "%s", version);
14468 err = pci_enable_device(pdev);
14470 printk(KERN_ERR PFX "Cannot enable PCI device, "
14475 err = pci_request_regions(pdev, DRV_MODULE_NAME);
14477 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
14479 goto err_out_disable_pdev;
14482 pci_set_master(pdev);
14484 /* Find power-management capability. */
14485 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
14487 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
14490 goto err_out_free_res;
14493 dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
14495 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
14497 goto err_out_free_res;
14500 SET_NETDEV_DEV(dev, &pdev->dev);
14502 #if TG3_VLAN_TAG_USED
14503 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
14506 tp = netdev_priv(dev);
14509 tp->pm_cap = pm_cap;
14510 tp->rx_mode = TG3_DEF_RX_MODE;
14511 tp->tx_mode = TG3_DEF_TX_MODE;
14514 tp->msg_enable = tg3_debug;
14516 tp->msg_enable = TG3_DEF_MSG_ENABLE;
14518 /* The word/byte swap controls here control register access byte
14519 * swapping. DMA data byte swapping is controlled in the GRC_MODE
14522 tp->misc_host_ctrl =
14523 MISC_HOST_CTRL_MASK_PCI_INT |
14524 MISC_HOST_CTRL_WORD_SWAP |
14525 MISC_HOST_CTRL_INDIR_ACCESS |
14526 MISC_HOST_CTRL_PCISTATE_RW;
14528 /* The NONFRM (non-frame) byte/word swap controls take effect
14529 * on descriptor entries, anything which isn't packet data.
14531 * The StrongARM chips on the board (one for tx, one for rx)
14532 * are running in big-endian mode.
14534 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
14535 GRC_MODE_WSWAP_NONFRM_DATA);
14536 #ifdef __BIG_ENDIAN
14537 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
14539 spin_lock_init(&tp->lock);
14540 spin_lock_init(&tp->indirect_lock);
14541 INIT_WORK(&tp->reset_task, tg3_reset_task);
14543 tp->regs = pci_ioremap_bar(pdev, BAR_0);
14545 printk(KERN_ERR PFX "Cannot map device registers, "
14548 goto err_out_free_dev;
14551 tg3_init_link_config(tp);
14553 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
14554 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
14556 dev->ethtool_ops = &tg3_ethtool_ops;
14557 dev->watchdog_timeo = TG3_TX_TIMEOUT;
14558 dev->irq = pdev->irq;
14560 err = tg3_get_invariants(tp);
14562 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
14564 goto err_out_iounmap;
14567 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
14568 tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
14569 dev->netdev_ops = &tg3_netdev_ops;
14571 dev->netdev_ops = &tg3_netdev_ops_dma_bug;
14574 /* The EPB bridge inside 5714, 5715, and 5780 and any
14575 * device behind the EPB cannot support DMA addresses > 40-bit.
14576 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
14577 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
14578 * do DMA address check in tg3_start_xmit().
14580 if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
14581 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
14582 else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
14583 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
14584 #ifdef CONFIG_HIGHMEM
14585 dma_mask = DMA_BIT_MASK(64);
14588 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
14590 /* Configure DMA attributes. */
14591 if (dma_mask > DMA_BIT_MASK(32)) {
14592 err = pci_set_dma_mask(pdev, dma_mask);
14594 dev->features |= NETIF_F_HIGHDMA;
14595 err = pci_set_consistent_dma_mask(pdev,
14598 printk(KERN_ERR PFX "Unable to obtain 64 bit "
14599 "DMA for consistent allocations\n");
14600 goto err_out_iounmap;
14604 if (err || dma_mask == DMA_BIT_MASK(32)) {
14605 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
14607 printk(KERN_ERR PFX "No usable DMA configuration, "
14609 goto err_out_iounmap;
14613 tg3_init_bufmgr_config(tp);
14615 /* Selectively allow TSO based on operating conditions */
14616 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
14617 (tp->fw_needed && !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)))
14618 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
14620 tp->tg3_flags2 &= ~(TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG);
14621 tp->fw_needed = NULL;
14624 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
14625 tp->fw_needed = FIRMWARE_TG3;
14627 /* TSO is on by default on chips that support hardware TSO.
14628 * Firmware TSO on older chips gives lower performance, so it
14629 * is off by default, but can be enabled using ethtool.
14631 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) &&
14632 (dev->features & NETIF_F_IP_CSUM))
14633 dev->features |= NETIF_F_TSO;
14635 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
14636 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3)) {
14637 if (dev->features & NETIF_F_IPV6_CSUM)
14638 dev->features |= NETIF_F_TSO6;
14639 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
14640 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
14641 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
14642 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
14643 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
14644 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
14645 dev->features |= NETIF_F_TSO_ECN;
14648 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
14649 !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
14650 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
14651 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
14652 tp->rx_pending = 63;
14655 err = tg3_get_device_address(tp);
14657 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
14659 goto err_out_iounmap;
14662 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
14663 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
14664 if (!tp->aperegs) {
14665 printk(KERN_ERR PFX "Cannot map APE registers, "
14668 goto err_out_iounmap;
14671 tg3_ape_lock_init(tp);
14673 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
14674 tg3_read_dash_ver(tp);
14678 * Reset chip in case UNDI or EFI driver did not shutdown
14679 * DMA self test will enable WDMAC and we'll see (spurious)
14680 * pending DMA on the PCI bus at that point.
14682 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
14683 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
14684 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
14685 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14688 err = tg3_test_dma(tp);
14690 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
14691 goto err_out_apeunmap;
14694 /* flow control autonegotiation is default behavior */
14695 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
14696 tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
14698 intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
14699 rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
14700 sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
14701 for (i = 0; i < TG3_IRQ_MAX_VECS; i++) {
14702 struct tg3_napi *tnapi = &tp->napi[i];
14705 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
14707 tnapi->int_mbox = intmbx;
14713 tnapi->consmbox = rcvmbx;
14714 tnapi->prodmbox = sndmbx;
14717 tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
14718 netif_napi_add(dev, &tnapi->napi, tg3_poll_msix, 64);
14720 tnapi->coal_now = HOSTCC_MODE_NOW;
14721 netif_napi_add(dev, &tnapi->napi, tg3_poll, 64);
14724 if (!(tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX))
14728 * If we support MSIX, we'll be using RSS. If we're using
14729 * RSS, the first vector only handles link interrupts and the
14730 * remaining vectors handle rx and tx interrupts. Reuse the
14731 * mailbox values for the next iteration. The values we setup
14732 * above are still useful for the single vectored mode.
14747 pci_set_drvdata(pdev, dev);
14749 err = register_netdev(dev);
14751 printk(KERN_ERR PFX "Cannot register net device, "
14753 goto err_out_apeunmap;
14756 printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
14758 tp->board_part_number,
14759 tp->pci_chip_rev_id,
14760 tg3_bus_string(tp, str),
14763 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
14764 struct phy_device *phydev;
14765 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
14767 "%s: attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
14768 tp->dev->name, phydev->drv->name,
14769 dev_name(&phydev->dev));
14772 "%s: attached PHY is %s (%s Ethernet) (WireSpeed[%d])\n",
14773 tp->dev->name, tg3_phy_string(tp),
14774 ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
14775 ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
14776 "10/100/1000Base-T")),
14777 (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0);
14779 printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
14781 (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
14782 (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
14783 (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
14784 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
14785 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
14786 printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
14787 dev->name, tp->dma_rwctrl,
14788 (pdev->dma_mask == DMA_BIT_MASK(32)) ? 32 :
14789 (((u64) pdev->dma_mask == DMA_BIT_MASK(40)) ? 40 : 64));
14795 iounmap(tp->aperegs);
14796 tp->aperegs = NULL;
14809 pci_release_regions(pdev);
14811 err_out_disable_pdev:
14812 pci_disable_device(pdev);
14813 pci_set_drvdata(pdev, NULL);
14817 static void __devexit tg3_remove_one(struct pci_dev *pdev)
14819 struct net_device *dev = pci_get_drvdata(pdev);
14822 struct tg3 *tp = netdev_priv(dev);
14825 release_firmware(tp->fw);
14827 flush_scheduled_work();
14829 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
14834 unregister_netdev(dev);
14836 iounmap(tp->aperegs);
14837 tp->aperegs = NULL;
14844 pci_release_regions(pdev);
14845 pci_disable_device(pdev);
14846 pci_set_drvdata(pdev, NULL);
14850 static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
14852 struct net_device *dev = pci_get_drvdata(pdev);
14853 struct tg3 *tp = netdev_priv(dev);
14854 pci_power_t target_state;
14857 /* PCI register 4 needs to be saved whether netif_running() or not.
14858 * MSI address and data need to be saved if using MSI and
14861 pci_save_state(pdev);
14863 if (!netif_running(dev))
14866 flush_scheduled_work();
14868 tg3_netif_stop(tp);
14870 del_timer_sync(&tp->timer);
14872 tg3_full_lock(tp, 1);
14873 tg3_disable_ints(tp);
14874 tg3_full_unlock(tp);
14876 netif_device_detach(dev);
14878 tg3_full_lock(tp, 0);
14879 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14880 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
14881 tg3_full_unlock(tp);
14883 target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot;
14885 err = tg3_set_power_state(tp, target_state);
14889 tg3_full_lock(tp, 0);
14891 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
14892 err2 = tg3_restart_hw(tp, 1);
14896 tp->timer.expires = jiffies + tp->timer_offset;
14897 add_timer(&tp->timer);
14899 netif_device_attach(dev);
14900 tg3_netif_start(tp);
14903 tg3_full_unlock(tp);
14912 static int tg3_resume(struct pci_dev *pdev)
14914 struct net_device *dev = pci_get_drvdata(pdev);
14915 struct tg3 *tp = netdev_priv(dev);
14918 pci_restore_state(tp->pdev);
14920 if (!netif_running(dev))
14923 err = tg3_set_power_state(tp, PCI_D0);
14927 netif_device_attach(dev);
14929 tg3_full_lock(tp, 0);
14931 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
14932 err = tg3_restart_hw(tp, 1);
14936 tp->timer.expires = jiffies + tp->timer_offset;
14937 add_timer(&tp->timer);
14939 tg3_netif_start(tp);
14942 tg3_full_unlock(tp);
14950 static struct pci_driver tg3_driver = {
14951 .name = DRV_MODULE_NAME,
14952 .id_table = tg3_pci_tbl,
14953 .probe = tg3_init_one,
14954 .remove = __devexit_p(tg3_remove_one),
14955 .suspend = tg3_suspend,
14956 .resume = tg3_resume
14959 static int __init tg3_init(void)
14961 return pci_register_driver(&tg3_driver);
14964 static void __exit tg3_cleanup(void)
14966 pci_unregister_driver(&tg3_driver);
14969 module_init(tg3_init);
14970 module_exit(tg3_cleanup);