drivers/net/tg3.c

   1 /*
   2  * tg3.c: Broadcom Tigon3 ethernet driver.
   3  *
   4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
   5  * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
   6  * Copyright (C) 2004 Sun Microsystems Inc.
   7  * Copyright (C) 2005-2009 Broadcom Corporation.
   8  *
   9  * Firmware is:
  10  *      Derived from proprietary unpublished source code,
  11  *      Copyright (C) 2000-2003 Broadcom Corporation.
  12  *
  13  *      Permission is hereby granted for the distribution of this firmware
  14  *      data in hexadecimal or equivalent format, provided this copyright
  15  *      notice is accompanying it.
  16  */
  17
  18
  19 #include <linux/module.h>
  20 #include <linux/moduleparam.h>
  21 #include <linux/kernel.h>
  22 #include <linux/types.h>
  23 #include <linux/compiler.h>
  24 #include <linux/slab.h>
  25 #include <linux/delay.h>
  26 #include <linux/in.h>
  27 #include <linux/init.h>
  28 #include <linux/ioport.h>
  29 #include <linux/pci.h>
  30 #include <linux/netdevice.h>
  31 #include <linux/etherdevice.h>
  32 #include <linux/skbuff.h>
  33 #include <linux/ethtool.h>
  34 #include <linux/mii.h>
  35 #include <linux/phy.h>
  36 #include <linux/brcmphy.h>
  37 #include <linux/if_vlan.h>
  38 #include <linux/ip.h>
  39 #include <linux/tcp.h>
  40 #include <linux/workqueue.h>
  41 #include <linux/prefetch.h>
  42 #include <linux/dma-mapping.h>
  43 #include <linux/firmware.h>
  44
  45 #include <net/checksum.h>
  46 #include <net/ip.h>
  47
  48 #include <asm/system.h>
  49 #include <asm/io.h>
  50 #include <asm/byteorder.h>
  51 #include <asm/uaccess.h>
  52
  53 #ifdef CONFIG_SPARC
  54 #include <asm/idprom.h>
  55 #include <asm/prom.h>
  56 #endif
  57
  58 #define BAR_0   0
  59 #define BAR_2   2
  60
  61 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  62 #define TG3_VLAN_TAG_USED 1
  63 #else
  64 #define TG3_VLAN_TAG_USED 0
  65 #endif
  66
  67 #include "tg3.h"
  68
  69 #define DRV_MODULE_NAME         "tg3"
  70 #define PFX DRV_MODULE_NAME     ": "
  71 #define DRV_MODULE_VERSION      "3.103"
  72 #define DRV_MODULE_RELDATE      "November 2, 2009"
  73
  74 #define TG3_DEF_MAC_MODE        0
  75 #define TG3_DEF_RX_MODE         0
  76 #define TG3_DEF_TX_MODE         0
  77 #define TG3_DEF_MSG_ENABLE        \
  78         (NETIF_MSG_DRV          | \
  79          NETIF_MSG_PROBE        | \
  80          NETIF_MSG_LINK         | \
  81          NETIF_MSG_TIMER        | \
  82          NETIF_MSG_IFDOWN       | \
  83          NETIF_MSG_IFUP         | \
  84          NETIF_MSG_RX_ERR       | \
  85          NETIF_MSG_TX_ERR)
  86
  87 /* length of time before we decide the hardware is borked,
  88  * and dev->tx_timeout() should be called to fix the problem
  89  */
  90 #define TG3_TX_TIMEOUT                  (5 * HZ)
  91
  92 /* hardware minimum and maximum for a single frame's data payload */
  93 #define TG3_MIN_MTU                     60
  94 #define TG3_MAX_MTU(tp) \
  95         ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
  96
  97 /* These numbers seem to be hard coded in the NIC firmware somehow.
  98  * You can't change the ring sizes, but you can change where you place
  99  * them in the NIC onboard memory.
 100  */
 101 #define TG3_RX_RING_SIZE                512
 102 #define TG3_DEF_RX_RING_PENDING         200
 103 #define TG3_RX_JUMBO_RING_SIZE          256
 104 #define TG3_DEF_RX_JUMBO_RING_PENDING   100
 105 #define TG3_RSS_INDIR_TBL_SIZE 128
 106
 107 /* Do not place this n-ring entries value into the tp struct itself,
 108  * we really want to expose these constants to GCC so that modulo et
 109  * al.  operations are done with shifts and masks instead of with
 110  * hw multiply/modulo instructions.  Another solution would be to
 111  * replace things like '% foo' with '& (foo - 1)'.
 112  */
 113 #define TG3_RX_RCB_RING_SIZE(tp)        \
 114         (((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) && \
 115           !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) ? 1024 : 512)
 116
 117 #define TG3_TX_RING_SIZE                512
 118 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
 119
 120 #define TG3_RX_RING_BYTES       (sizeof(struct tg3_rx_buffer_desc) * \
 121                                  TG3_RX_RING_SIZE)
 122 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_ext_rx_buffer_desc) * \
 123                                  TG3_RX_JUMBO_RING_SIZE)
 124 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
 125                                  TG3_RX_RCB_RING_SIZE(tp))
 126 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * \
 127                                  TG3_TX_RING_SIZE)
 128 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
 129
 130 #define TG3_DMA_BYTE_ENAB               64
 131
 132 #define TG3_RX_STD_DMA_SZ               1536
 133 #define TG3_RX_JMB_DMA_SZ               9046
 134
 135 #define TG3_RX_DMA_TO_MAP_SZ(x)         ((x) + TG3_DMA_BYTE_ENAB)
 136
 137 #define TG3_RX_STD_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
 138 #define TG3_RX_JMB_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
 139
 140 /* minimum number of free TX descriptors required to wake up TX process */
 141 #define TG3_TX_WAKEUP_THRESH(tnapi)             ((tnapi)->tx_pending / 4)
 142
 143 #define TG3_RAW_IP_ALIGN 2
 144
 145 /* number of ETHTOOL_GSTATS u64's */
 146 #define TG3_NUM_STATS           (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
 147
 148 #define TG3_NUM_TEST            6
 149
 150 #define FIRMWARE_TG3            "tigon/tg3.bin"
 151 #define FIRMWARE_TG3TSO         "tigon/tg3_tso.bin"
 152 #define FIRMWARE_TG3TSO5        "tigon/tg3_tso5.bin"
 153
 154 static char version[] __devinitdata =
 155         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
 156
 157 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
 158 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
 159 MODULE_LICENSE("GPL");
 160 MODULE_VERSION(DRV_MODULE_VERSION);
 161 MODULE_FIRMWARE(FIRMWARE_TG3);
 162 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
 163 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
 164
 165 #define TG3_RSS_MIN_NUM_MSIX_VECS       2
 166
 167 static int tg3_debug = -1;      /* -1 == use TG3_DEF_MSG_ENABLE as value */
 168 module_param(tg3_debug, int, 0);
 169 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
 170
 171 static struct pci_device_id tg3_pci_tbl[] = {
 172         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
 173         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
 174         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
 175         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
 176         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
 177         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
 178         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
 179         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
 180         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
 181         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
 182         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
 183         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
 184         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
 185         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
 186         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
 187         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
 188         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
 189         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
 190         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
 191         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
 192         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
 193         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
 194         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
 195         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
 196         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
 197         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
 198         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
 199         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
 200         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
 201         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
 202         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
 203         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
 204         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
 205         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
 206         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
 207         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
 208         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
 209         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
 210         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
 211         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
 212         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
 213         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
 214         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
 215         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
 216         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
 217         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
 218         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
 219         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
 220         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
 221         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
 222         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
 223         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
 224         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
 225         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
 226         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
 227         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
 228         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
 229         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
 230         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
 231         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
 232         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
 233         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
 234         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
 235         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
 236         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
 237         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
 238         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
 239         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
 240         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
 241         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
 242         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
 243         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
 244         {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
 245         {}
 246 };
 247
 248 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
 249
 250 static const struct {
 251         const char string[ETH_GSTRING_LEN];
 252 } ethtool_stats_keys[TG3_NUM_STATS] = {
 253         { "rx_octets" },
 254         { "rx_fragments" },
 255         { "rx_ucast_packets" },
 256         { "rx_mcast_packets" },
 257         { "rx_bcast_packets" },
 258         { "rx_fcs_errors" },
 259         { "rx_align_errors" },
 260         { "rx_xon_pause_rcvd" },
 261         { "rx_xoff_pause_rcvd" },
 262         { "rx_mac_ctrl_rcvd" },
 263         { "rx_xoff_entered" },
 264         { "rx_frame_too_long_errors" },
 265         { "rx_jabbers" },
 266         { "rx_undersize_packets" },
 267         { "rx_in_length_errors" },
 268         { "rx_out_length_errors" },
 269         { "rx_64_or_less_octet_packets" },
 270         { "rx_65_to_127_octet_packets" },
 271         { "rx_128_to_255_octet_packets" },
 272         { "rx_256_to_511_octet_packets" },
 273         { "rx_512_to_1023_octet_packets" },
 274         { "rx_1024_to_1522_octet_packets" },
 275         { "rx_1523_to_2047_octet_packets" },
 276         { "rx_2048_to_4095_octet_packets" },
 277         { "rx_4096_to_8191_octet_packets" },
 278         { "rx_8192_to_9022_octet_packets" },
 279
 280         { "tx_octets" },
 281         { "tx_collisions" },
 282
 283         { "tx_xon_sent" },
 284         { "tx_xoff_sent" },
 285         { "tx_flow_control" },
 286         { "tx_mac_errors" },
 287         { "tx_single_collisions" },
 288         { "tx_mult_collisions" },
 289         { "tx_deferred" },
 290         { "tx_excessive_collisions" },
 291         { "tx_late_collisions" },
 292         { "tx_collide_2times" },
 293         { "tx_collide_3times" },
 294         { "tx_collide_4times" },
 295         { "tx_collide_5times" },
 296         { "tx_collide_6times" },
 297         { "tx_collide_7times" },
 298         { "tx_collide_8times" },
 299         { "tx_collide_9times" },
 300         { "tx_collide_10times" },
 301         { "tx_collide_11times" },
 302         { "tx_collide_12times" },
 303         { "tx_collide_13times" },
 304         { "tx_collide_14times" },
 305         { "tx_collide_15times" },
 306         { "tx_ucast_packets" },
 307         { "tx_mcast_packets" },
 308         { "tx_bcast_packets" },
 309         { "tx_carrier_sense_errors" },
 310         { "tx_discards" },
 311         { "tx_errors" },
 312
 313         { "dma_writeq_full" },
 314         { "dma_write_prioq_full" },
 315         { "rxbds_empty" },
 316         { "rx_discards" },
 317         { "rx_errors" },
 318         { "rx_threshold_hit" },
 319
 320         { "dma_readq_full" },
 321         { "dma_read_prioq_full" },
 322         { "tx_comp_queue_full" },
 323
 324         { "ring_set_send_prod_index" },
 325         { "ring_status_update" },
 326         { "nic_irqs" },
 327         { "nic_avoided_irqs" },
 328         { "nic_tx_threshold_hit" }
 329 };
 330
 331 static const struct {
 332         const char string[ETH_GSTRING_LEN];
 333 } ethtool_test_keys[TG3_NUM_TEST] = {
 334         { "nvram test     (online) " },
 335         { "link test      (online) " },
 336         { "register test  (offline)" },
 337         { "memory test    (offline)" },
 338         { "loopback test  (offline)" },
 339         { "interrupt test (offline)" },
 340 };
 341
 342 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
 343 {
 344         writel(val, tp->regs + off);
 345 }
 346
 347 static u32 tg3_read32(struct tg3 *tp, u32 off)
 348 {
 349         return (readl(tp->regs + off));
 350 }
 351
 352 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
 353 {
 354         writel(val, tp->aperegs + off);
 355 }
 356
 357 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
 358 {
 359         return (readl(tp->aperegs + off));
 360 }
 361
 362 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
 363 {
 364         unsigned long flags;
 365
 366         spin_lock_irqsave(&tp->indirect_lock, flags);
 367         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 368         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 369         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 370 }
 371
 372 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
 373 {
 374         writel(val, tp->regs + off);
 375         readl(tp->regs + off);
 376 }
 377
 378 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
 379 {
 380         unsigned long flags;
 381         u32 val;
 382
 383         spin_lock_irqsave(&tp->indirect_lock, flags);
 384         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 385         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 386         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 387         return val;
 388 }
 389
 390 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
 391 {
 392         unsigned long flags;
 393
 394         if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
 395                 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
 396                                        TG3_64BIT_REG_LOW, val);
 397                 return;
 398         }
 399         if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
 400                 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
 401                                        TG3_64BIT_REG_LOW, val);
 402                 return;
 403         }
 404
 405         spin_lock_irqsave(&tp->indirect_lock, flags);
 406         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 407         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 408         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 409
 410         /* In indirect mode when disabling interrupts, we also need
 411          * to clear the interrupt bit in the GRC local ctrl register.
 412          */
 413         if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
 414             (val == 0x1)) {
 415                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
 416                                        tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
 417         }
 418 }
 419
 420 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
 421 {
 422         unsigned long flags;
 423         u32 val;
 424
 425         spin_lock_irqsave(&tp->indirect_lock, flags);
 426         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 427         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 428         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 429         return val;
 430 }
 431
 432 /* usec_wait specifies the wait time in usec when writing to certain registers
 433  * where it is unsafe to read back the register without some delay.
 434  * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
 435  * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
 436  */
 437 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
 438 {
 439         if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
 440             (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 441                 /* Non-posted methods */
 442                 tp->write32(tp, off, val);
 443         else {
 444                 /* Posted method */
 445                 tg3_write32(tp, off, val);
 446                 if (usec_wait)
 447                         udelay(usec_wait);
 448                 tp->read32(tp, off);
 449         }
 450         /* Wait again after the read for the posted method to guarantee that
 451          * the wait time is met.
 452          */
 453         if (usec_wait)
 454                 udelay(usec_wait);
 455 }
 456
 457 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
 458 {
 459         tp->write32_mbox(tp, off, val);
 460         if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
 461             !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 462                 tp->read32_mbox(tp, off);
 463 }
 464
 465 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
 466 {
 467         void __iomem *mbox = tp->regs + off;
 468         writel(val, mbox);
 469         if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
 470                 writel(val, mbox);
 471         if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
 472                 readl(mbox);
 473 }
 474
 475 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
 476 {
 477         return (readl(tp->regs + off + GRCMBOX_BASE));
 478 }
 479
 480 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
 481 {
 482         writel(val, tp->regs + off + GRCMBOX_BASE);
 483 }
 484
 485 #define tw32_mailbox(reg, val)  tp->write32_mbox(tp, reg, val)
 486 #define tw32_mailbox_f(reg, val)        tw32_mailbox_flush(tp, (reg), (val))
 487 #define tw32_rx_mbox(reg, val)  tp->write32_rx_mbox(tp, reg, val)
 488 #define tw32_tx_mbox(reg, val)  tp->write32_tx_mbox(tp, reg, val)
 489 #define tr32_mailbox(reg)       tp->read32_mbox(tp, reg)
 490
 491 #define tw32(reg,val)           tp->write32(tp, reg, val)
 492 #define tw32_f(reg,val)         _tw32_flush(tp,(reg),(val), 0)
 493 #define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
 494 #define tr32(reg)               tp->read32(tp, reg)
 495
 496 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
 497 {
 498         unsigned long flags;
 499
 500         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 501             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
 502                 return;
 503
 504         spin_lock_irqsave(&tp->indirect_lock, flags);
 505         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 506                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 507                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 508
 509                 /* Always leave this as zero. */
 510                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 511         } else {
 512                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 513                 tw32_f(TG3PCI_MEM_WIN_DATA, val);
 514
 515                 /* Always leave this as zero. */
 516                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 517         }
 518         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 519 }
 520
 521 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
 522 {
 523         unsigned long flags;
 524
 525         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 526             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
 527                 *val = 0;
 528                 return;
 529         }
 530
 531         spin_lock_irqsave(&tp->indirect_lock, flags);
 532         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 533                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 534                 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 535
 536                 /* Always leave this as zero. */
 537                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 538         } else {
 539                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 540                 *val = tr32(TG3PCI_MEM_WIN_DATA);
 541
 542                 /* Always leave this as zero. */
 543                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 544         }
 545         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 546 }
 547
 548 static void tg3_ape_lock_init(struct tg3 *tp)
 549 {
 550         int i;
 551
 552         /* Make sure the driver hasn't any stale locks. */
 553         for (i = 0; i < 8; i++)
 554                 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + 4 * i,
 555                                 APE_LOCK_GRANT_DRIVER);
 556 }
 557
 558 static int tg3_ape_lock(struct tg3 *tp, int locknum)
 559 {
 560         int i, off;
 561         int ret = 0;
 562         u32 status;
 563
 564         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
 565                 return 0;
 566
 567         switch (locknum) {
 568                 case TG3_APE_LOCK_GRC:
 569                 case TG3_APE_LOCK_MEM:
 570                         break;
 571                 default:
 572                         return -EINVAL;
 573         }
 574
 575         off = 4 * locknum;
 576
 577         tg3_ape_write32(tp, TG3_APE_LOCK_REQ + off, APE_LOCK_REQ_DRIVER);
 578
 579         /* Wait for up to 1 millisecond to acquire lock. */
 580         for (i = 0; i < 100; i++) {
 581                 status = tg3_ape_read32(tp, TG3_APE_LOCK_GRANT + off);
 582                 if (status == APE_LOCK_GRANT_DRIVER)
 583                         break;
 584                 udelay(10);
 585         }
 586
 587         if (status != APE_LOCK_GRANT_DRIVER) {
 588                 /* Revoke the lock request. */
 589                 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off,
 590                                 APE_LOCK_GRANT_DRIVER);
 591
 592                 ret = -EBUSY;
 593         }
 594
 595         return ret;
 596 }
 597
 598 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
 599 {
 600         int off;
 601
 602         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
 603                 return;
 604
 605         switch (locknum) {
 606                 case TG3_APE_LOCK_GRC:
 607                 case TG3_APE_LOCK_MEM:
 608                         break;
 609                 default:
 610                         return;
 611         }
 612
 613         off = 4 * locknum;
 614         tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off, APE_LOCK_GRANT_DRIVER);
 615 }
 616
 617 static void tg3_disable_ints(struct tg3 *tp)
 618 {
 619         int i;
 620
 621         tw32(TG3PCI_MISC_HOST_CTRL,
 622              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
 623         for (i = 0; i < tp->irq_max; i++)
 624                 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
 625 }
 626
 627 static void tg3_enable_ints(struct tg3 *tp)
 628 {
 629         int i;
 630         u32 coal_now = 0;
 631
 632         tp->irq_sync = 0;
 633         wmb();
 634
 635         tw32(TG3PCI_MISC_HOST_CTRL,
 636              (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
 637
 638         for (i = 0; i < tp->irq_cnt; i++) {
 639                 struct tg3_napi *tnapi = &tp->napi[i];
 640                 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
 641                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
 642                         tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
 643
 644                 coal_now |= tnapi->coal_now;
 645         }
 646
 647         /* Force an initial interrupt */
 648         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 649             (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
 650                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
 651         else
 652                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 653                      HOSTCC_MODE_ENABLE | coal_now);
 654 }
 655
 656 static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
 657 {
 658         struct tg3 *tp = tnapi->tp;
 659         struct tg3_hw_status *sblk = tnapi->hw_status;
 660         unsigned int work_exists = 0;
 661
 662         /* check for phy events */
 663         if (!(tp->tg3_flags &
 664               (TG3_FLAG_USE_LINKCHG_REG |
 665                TG3_FLAG_POLL_SERDES))) {
 666                 if (sblk->status & SD_STATUS_LINK_CHG)
 667                         work_exists = 1;
 668         }
 669         /* check for RX/TX work to do */
 670         if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
 671             *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
 672                 work_exists = 1;
 673
 674         return work_exists;
 675 }
 676
 677 /* tg3_int_reenable
 678  *  similar to tg3_enable_ints, but it accurately determines whether there
 679  *  is new work pending and can return without flushing the PIO write
 680  *  which reenables interrupts
 681  */
 682 static void tg3_int_reenable(struct tg3_napi *tnapi)
 683 {
 684         struct tg3 *tp = tnapi->tp;
 685
 686         tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
 687         mmiowb();
 688
 689         /* When doing tagged status, this work check is unnecessary.
 690          * The last_tag we write above tells the chip which piece of
 691          * work we've completed.
 692          */
 693         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 694             tg3_has_work(tnapi))
 695                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 696                      HOSTCC_MODE_ENABLE | tnapi->coal_now);
 697 }
 698
 699 static void tg3_napi_disable(struct tg3 *tp)
 700 {
 701         int i;
 702
 703         for (i = tp->irq_cnt - 1; i >= 0; i--)
 704                 napi_disable(&tp->napi[i].napi);
 705 }
 706
 707 static void tg3_napi_enable(struct tg3 *tp)
 708 {
 709         int i;
 710
 711         for (i = 0; i < tp->irq_cnt; i++)
 712                 napi_enable(&tp->napi[i].napi);
 713 }
 714
 715 static inline void tg3_netif_stop(struct tg3 *tp)
 716 {
 717         tp->dev->trans_start = jiffies; /* prevent tx timeout */
 718         tg3_napi_disable(tp);
 719         netif_tx_disable(tp->dev);
 720 }
 721
 722 static inline void tg3_netif_start(struct tg3 *tp)
 723 {
 724         /* NOTE: unconditional netif_tx_wake_all_queues is only
 725          * appropriate so long as all callers are assured to
 726          * have free tx slots (such as after tg3_init_hw)
 727          */
 728         netif_tx_wake_all_queues(tp->dev);
 729
 730         tg3_napi_enable(tp);
 731         tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
 732         tg3_enable_ints(tp);
 733 }
 734
 735 static void tg3_switch_clocks(struct tg3 *tp)
 736 {
 737         u32 clock_ctrl;
 738         u32 orig_clock_ctrl;
 739
 740         if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
 741             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
 742                 return;
 743
 744         clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
 745
 746         orig_clock_ctrl = clock_ctrl;
 747         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
 748                        CLOCK_CTRL_CLKRUN_OENABLE |
 749                        0x1f);
 750         tp->pci_clock_ctrl = clock_ctrl;
 751
 752         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
 753                 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
 754                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
 755                                     clock_ctrl | CLOCK_CTRL_625_CORE, 40);
 756                 }
 757         } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
 758                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 759                             clock_ctrl |
 760                             (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
 761                             40);
 762                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 763                             clock_ctrl | (CLOCK_CTRL_ALTCLK),
 764                             40);
 765         }
 766         tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
 767 }
 768
 769 #define PHY_BUSY_LOOPS  5000
 770
 771 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
 772 {
 773         u32 frame_val;
 774         unsigned int loops;
 775         int ret;
 776
 777         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 778                 tw32_f(MAC_MI_MODE,
 779                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 780                 udelay(80);
 781         }
 782
 783         *val = 0x0;
 784
 785         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
 786                       MI_COM_PHY_ADDR_MASK);
 787         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 788                       MI_COM_REG_ADDR_MASK);
 789         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
 790
 791         tw32_f(MAC_MI_COM, frame_val);
 792
 793         loops = PHY_BUSY_LOOPS;
 794         while (loops != 0) {
 795                 udelay(10);
 796                 frame_val = tr32(MAC_MI_COM);
 797
 798                 if ((frame_val & MI_COM_BUSY) == 0) {
 799                         udelay(5);
 800                         frame_val = tr32(MAC_MI_COM);
 801                         break;
 802                 }
 803                 loops -= 1;
 804         }
 805
 806         ret = -EBUSY;
 807         if (loops != 0) {
 808                 *val = frame_val & MI_COM_DATA_MASK;
 809                 ret = 0;
 810         }
 811
 812         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 813                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 814                 udelay(80);
 815         }
 816
 817         return ret;
 818 }
 819
 820 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
 821 {
 822         u32 frame_val;
 823         unsigned int loops;
 824         int ret;
 825
 826         if ((tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
 827             (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
 828                 return 0;
 829
 830         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 831                 tw32_f(MAC_MI_MODE,
 832                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 833                 udelay(80);
 834         }
 835
 836         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
 837                       MI_COM_PHY_ADDR_MASK);
 838         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 839                       MI_COM_REG_ADDR_MASK);
 840         frame_val |= (val & MI_COM_DATA_MASK);
 841         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
 842
 843         tw32_f(MAC_MI_COM, frame_val);
 844
 845         loops = PHY_BUSY_LOOPS;
 846         while (loops != 0) {
 847                 udelay(10);
 848                 frame_val = tr32(MAC_MI_COM);
 849                 if ((frame_val & MI_COM_BUSY) == 0) {
 850                         udelay(5);
 851                         frame_val = tr32(MAC_MI_COM);
 852                         break;
 853                 }
 854                 loops -= 1;
 855         }
 856
 857         ret = -EBUSY;
 858         if (loops != 0)
 859                 ret = 0;
 860
 861         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 862                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 863                 udelay(80);
 864         }
 865
 866         return ret;
 867 }
 868
 869 static int tg3_bmcr_reset(struct tg3 *tp)
 870 {
 871         u32 phy_control;
 872         int limit, err;
 873
 874         /* OK, reset it, and poll the BMCR_RESET bit until it
 875          * clears or we time out.
 876          */
 877         phy_control = BMCR_RESET;
 878         err = tg3_writephy(tp, MII_BMCR, phy_control);
 879         if (err != 0)
 880                 return -EBUSY;
 881
 882         limit = 5000;
 883         while (limit--) {
 884                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
 885                 if (err != 0)
 886                         return -EBUSY;
 887
 888                 if ((phy_control & BMCR_RESET) == 0) {
 889                         udelay(40);
 890                         break;
 891                 }
 892                 udelay(10);
 893         }
 894         if (limit < 0)
 895                 return -EBUSY;
 896
 897         return 0;
 898 }
 899
 900 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
 901 {
 902         struct tg3 *tp = bp->priv;
 903         u32 val;
 904
 905         spin_lock_bh(&tp->lock);
 906
 907         if (tg3_readphy(tp, reg, &val))
 908                 val = -EIO;
 909
 910         spin_unlock_bh(&tp->lock);
 911
 912         return val;
 913 }
 914
 915 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
 916 {
 917         struct tg3 *tp = bp->priv;
 918         u32 ret = 0;
 919
 920         spin_lock_bh(&tp->lock);
 921
 922         if (tg3_writephy(tp, reg, val))
 923                 ret = -EIO;
 924
 925         spin_unlock_bh(&tp->lock);
 926
 927         return ret;
 928 }
 929
 930 static int tg3_mdio_reset(struct mii_bus *bp)
 931 {
 932         return 0;
 933 }
 934
 935 static void tg3_mdio_config_5785(struct tg3 *tp)
 936 {
 937         u32 val;
 938         struct phy_device *phydev;
 939
 940         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
 941         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
 942         case TG3_PHY_ID_BCM50610:
 943         case TG3_PHY_ID_BCM50610M:
 944                 val = MAC_PHYCFG2_50610_LED_MODES;
 945                 break;
 946         case TG3_PHY_ID_BCMAC131:
 947                 val = MAC_PHYCFG2_AC131_LED_MODES;
 948                 break;
 949         case TG3_PHY_ID_RTL8211C:
 950                 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
 951                 break;
 952         case TG3_PHY_ID_RTL8201E:
 953                 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
 954                 break;
 955         default:
 956                 return;
 957         }
 958
 959         if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
 960                 tw32(MAC_PHYCFG2, val);
 961
 962                 val = tr32(MAC_PHYCFG1);
 963                 val &= ~(MAC_PHYCFG1_RGMII_INT |
 964                          MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
 965                 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
 966                 tw32(MAC_PHYCFG1, val);
 967
 968                 return;
 969         }
 970
 971         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE))
 972                 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
 973                        MAC_PHYCFG2_FMODE_MASK_MASK |
 974                        MAC_PHYCFG2_GMODE_MASK_MASK |
 975                        MAC_PHYCFG2_ACT_MASK_MASK   |
 976                        MAC_PHYCFG2_QUAL_MASK_MASK |
 977                        MAC_PHYCFG2_INBAND_ENABLE;
 978
 979         tw32(MAC_PHYCFG2, val);
 980
 981         val = tr32(MAC_PHYCFG1);
 982         val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
 983                  MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
 984         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
 985                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
 986                         val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
 987                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
 988                         val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
 989         }
 990         val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
 991                MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
 992         tw32(MAC_PHYCFG1, val);
 993
 994         val = tr32(MAC_EXT_RGMII_MODE);
 995         val &= ~(MAC_RGMII_MODE_RX_INT_B |
 996                  MAC_RGMII_MODE_RX_QUALITY |
 997                  MAC_RGMII_MODE_RX_ACTIVITY |
 998                  MAC_RGMII_MODE_RX_ENG_DET |
 999                  MAC_RGMII_MODE_TX_ENABLE |
1000                  MAC_RGMII_MODE_TX_LOWPWR |
1001                  MAC_RGMII_MODE_TX_RESET);
1002         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
1003                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1004                         val |= MAC_RGMII_MODE_RX_INT_B |
1005                                MAC_RGMII_MODE_RX_QUALITY |
1006                                MAC_RGMII_MODE_RX_ACTIVITY |
1007                                MAC_RGMII_MODE_RX_ENG_DET;
1008                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1009                         val |= MAC_RGMII_MODE_TX_ENABLE |
1010                                MAC_RGMII_MODE_TX_LOWPWR |
1011                                MAC_RGMII_MODE_TX_RESET;
1012         }
1013         tw32(MAC_EXT_RGMII_MODE, val);
1014 }
1015
1016 static void tg3_mdio_start(struct tg3 *tp)
1017 {
1018         tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1019         tw32_f(MAC_MI_MODE, tp->mi_mode);
1020         udelay(80);
1021
1022         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
1023                 u32 funcnum, is_serdes;
1024
1025                 funcnum = tr32(TG3_CPMU_STATUS) & TG3_CPMU_STATUS_PCIE_FUNC;
1026                 if (funcnum)
1027                         tp->phy_addr = 2;
1028                 else
1029                         tp->phy_addr = 1;
1030
1031                 is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1032                 if (is_serdes)
1033                         tp->phy_addr += 7;
1034         } else
1035                 tp->phy_addr = TG3_PHY_MII_ADDR;
1036
1037         if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
1038             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1039                 tg3_mdio_config_5785(tp);
1040 }
1041
1042 static int tg3_mdio_init(struct tg3 *tp)
1043 {
1044         int i;
1045         u32 reg;
1046         struct phy_device *phydev;
1047
1048         tg3_mdio_start(tp);
1049
1050         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1051             (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1052                 return 0;
1053
1054         tp->mdio_bus = mdiobus_alloc();
1055         if (tp->mdio_bus == NULL)
1056                 return -ENOMEM;
1057
1058         tp->mdio_bus->name     = "tg3 mdio bus";
1059         snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1060                  (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1061         tp->mdio_bus->priv     = tp;
1062         tp->mdio_bus->parent   = &tp->pdev->dev;
1063         tp->mdio_bus->read     = &tg3_mdio_read;
1064         tp->mdio_bus->write    = &tg3_mdio_write;
1065         tp->mdio_bus->reset    = &tg3_mdio_reset;
1066         tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
1067         tp->mdio_bus->irq      = &tp->mdio_irq[0];
1068
1069         for (i = 0; i < PHY_MAX_ADDR; i++)
1070                 tp->mdio_bus->irq[i] = PHY_POLL;
1071
1072         /* The bus registration will look for all the PHYs on the mdio bus.
1073          * Unfortunately, it does not ensure the PHY is powered up before
1074          * accessing the PHY ID registers.  A chip reset is the
1075          * quickest way to bring the device back to an operational state..
1076          */
1077         if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1078                 tg3_bmcr_reset(tp);
1079
1080         i = mdiobus_register(tp->mdio_bus);
1081         if (i) {
1082                 printk(KERN_WARNING "%s: mdiobus_reg failed (0x%x)\n",
1083                         tp->dev->name, i);
1084                 mdiobus_free(tp->mdio_bus);
1085                 return i;
1086         }
1087
1088         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1089
1090         if (!phydev || !phydev->drv) {
1091                 printk(KERN_WARNING "%s: No PHY devices\n", tp->dev->name);
1092                 mdiobus_unregister(tp->mdio_bus);
1093                 mdiobus_free(tp->mdio_bus);
1094                 return -ENODEV;
1095         }
1096
1097         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1098         case TG3_PHY_ID_BCM57780:
1099                 phydev->interface = PHY_INTERFACE_MODE_GMII;
1100                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1101                 break;
1102         case TG3_PHY_ID_BCM50610:
1103         case TG3_PHY_ID_BCM50610M:
1104                 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
1105                                      PHY_BRCM_RX_REFCLK_UNUSED |
1106                                      PHY_BRCM_DIS_TXCRXC_NOENRGY |
1107                                      PHY_BRCM_AUTO_PWRDWN_ENABLE;
1108                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)
1109                         phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1110                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1111                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1112                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1113                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1114                 /* fallthru */
1115         case TG3_PHY_ID_RTL8211C:
1116                 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1117                 break;
1118         case TG3_PHY_ID_RTL8201E:
1119         case TG3_PHY_ID_BCMAC131:
1120                 phydev->interface = PHY_INTERFACE_MODE_MII;
1121                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1122                 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
1123                 break;
1124         }
1125
1126         tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1127
1128         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1129                 tg3_mdio_config_5785(tp);
1130
1131         return 0;
1132 }
1133
1134 static void tg3_mdio_fini(struct tg3 *tp)
1135 {
1136         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1137                 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
1138                 mdiobus_unregister(tp->mdio_bus);
1139                 mdiobus_free(tp->mdio_bus);
1140         }
1141 }
1142
1143 /* tp->lock is held. */
1144 static inline void tg3_generate_fw_event(struct tg3 *tp)
1145 {
1146         u32 val;
1147
1148         val = tr32(GRC_RX_CPU_EVENT);
1149         val |= GRC_RX_CPU_DRIVER_EVENT;
1150         tw32_f(GRC_RX_CPU_EVENT, val);
1151
1152         tp->last_event_jiffies = jiffies;
1153 }
1154
1155 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1156
1157 /* tp->lock is held. */
1158 static void tg3_wait_for_event_ack(struct tg3 *tp)
1159 {
1160         int i;
1161         unsigned int delay_cnt;
1162         long time_remain;
1163
1164         /* If enough time has passed, no wait is necessary. */
1165         time_remain = (long)(tp->last_event_jiffies + 1 +
1166                       usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1167                       (long)jiffies;
1168         if (time_remain < 0)
1169                 return;
1170
1171         /* Check if we can shorten the wait time. */
1172         delay_cnt = jiffies_to_usecs(time_remain);
1173         if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1174                 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1175         delay_cnt = (delay_cnt >> 3) + 1;
1176
1177         for (i = 0; i < delay_cnt; i++) {
1178                 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1179                         break;
1180                 udelay(8);
1181         }
1182 }
1183
1184 /* tp->lock is held. */
1185 static void tg3_ump_link_report(struct tg3 *tp)
1186 {
1187         u32 reg;
1188         u32 val;
1189
1190         if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1191             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
1192                 return;
1193
1194         tg3_wait_for_event_ack(tp);
1195
1196         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1197
1198         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1199
1200         val = 0;
1201         if (!tg3_readphy(tp, MII_BMCR, &reg))
1202                 val = reg << 16;
1203         if (!tg3_readphy(tp, MII_BMSR, &reg))
1204                 val |= (reg & 0xffff);
1205         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1206
1207         val = 0;
1208         if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1209                 val = reg << 16;
1210         if (!tg3_readphy(tp, MII_LPA, &reg))
1211                 val |= (reg & 0xffff);
1212         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1213
1214         val = 0;
1215         if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) {
1216                 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1217                         val = reg << 16;
1218                 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1219                         val |= (reg & 0xffff);
1220         }
1221         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1222
1223         if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1224                 val = reg << 16;
1225         else
1226                 val = 0;
1227         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1228
1229         tg3_generate_fw_event(tp);
1230 }
1231
1232 static void tg3_link_report(struct tg3 *tp)
1233 {
1234         if (!netif_carrier_ok(tp->dev)) {
1235                 if (netif_msg_link(tp))
1236                         printk(KERN_INFO PFX "%s: Link is down.\n",
1237                                tp->dev->name);
1238                 tg3_ump_link_report(tp);
1239         } else if (netif_msg_link(tp)) {
1240                 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1241                        tp->dev->name,
1242                        (tp->link_config.active_speed == SPEED_1000 ?
1243                         1000 :
1244                         (tp->link_config.active_speed == SPEED_100 ?
1245                          100 : 10)),
1246                        (tp->link_config.active_duplex == DUPLEX_FULL ?
1247                         "full" : "half"));
1248
1249                 printk(KERN_INFO PFX
1250                        "%s: Flow control is %s for TX and %s for RX.\n",
1251                        tp->dev->name,
1252                        (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1253                        "on" : "off",
1254                        (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1255                        "on" : "off");
1256                 tg3_ump_link_report(tp);
1257         }
1258 }
1259
1260 static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1261 {
1262         u16 miireg;
1263
1264         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1265                 miireg = ADVERTISE_PAUSE_CAP;
1266         else if (flow_ctrl & FLOW_CTRL_TX)
1267                 miireg = ADVERTISE_PAUSE_ASYM;
1268         else if (flow_ctrl & FLOW_CTRL_RX)
1269                 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1270         else
1271                 miireg = 0;
1272
1273         return miireg;
1274 }
1275
1276 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1277 {
1278         u16 miireg;
1279
1280         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1281                 miireg = ADVERTISE_1000XPAUSE;
1282         else if (flow_ctrl & FLOW_CTRL_TX)
1283                 miireg = ADVERTISE_1000XPSE_ASYM;
1284         else if (flow_ctrl & FLOW_CTRL_RX)
1285                 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1286         else
1287                 miireg = 0;
1288
1289         return miireg;
1290 }
1291
1292 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1293 {
1294         u8 cap = 0;
1295
1296         if (lcladv & ADVERTISE_1000XPAUSE) {
1297                 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1298                         if (rmtadv & LPA_1000XPAUSE)
1299                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1300                         else if (rmtadv & LPA_1000XPAUSE_ASYM)
1301                                 cap = FLOW_CTRL_RX;
1302                 } else {
1303                         if (rmtadv & LPA_1000XPAUSE)
1304                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1305                 }
1306         } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1307                 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1308                         cap = FLOW_CTRL_TX;
1309         }
1310
1311         return cap;
1312 }
1313
1314 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1315 {
1316         u8 autoneg;
1317         u8 flowctrl = 0;
1318         u32 old_rx_mode = tp->rx_mode;
1319         u32 old_tx_mode = tp->tx_mode;
1320
1321         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
1322                 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
1323         else
1324                 autoneg = tp->link_config.autoneg;
1325
1326         if (autoneg == AUTONEG_ENABLE &&
1327             (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1328                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1329                         flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1330                 else
1331                         flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1332         } else
1333                 flowctrl = tp->link_config.flowctrl;
1334
1335         tp->link_config.active_flowctrl = flowctrl;
1336
1337         if (flowctrl & FLOW_CTRL_RX)
1338                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1339         else
1340                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1341
1342         if (old_rx_mode != tp->rx_mode)
1343                 tw32_f(MAC_RX_MODE, tp->rx_mode);
1344
1345         if (flowctrl & FLOW_CTRL_TX)
1346                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1347         else
1348                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1349
1350         if (old_tx_mode != tp->tx_mode)
1351                 tw32_f(MAC_TX_MODE, tp->tx_mode);
1352 }
1353
1354 static void tg3_adjust_link(struct net_device *dev)
1355 {
1356         u8 oldflowctrl, linkmesg = 0;
1357         u32 mac_mode, lcl_adv, rmt_adv;
1358         struct tg3 *tp = netdev_priv(dev);
1359         struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1360
1361         spin_lock_bh(&tp->lock);
1362
1363         mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1364                                     MAC_MODE_HALF_DUPLEX);
1365
1366         oldflowctrl = tp->link_config.active_flowctrl;
1367
1368         if (phydev->link) {
1369                 lcl_adv = 0;
1370                 rmt_adv = 0;
1371
1372                 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1373                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1374                 else if (phydev->speed == SPEED_1000 ||
1375                          GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
1376                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
1377                 else
1378                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1379
1380                 if (phydev->duplex == DUPLEX_HALF)
1381                         mac_mode |= MAC_MODE_HALF_DUPLEX;
1382                 else {
1383                         lcl_adv = tg3_advert_flowctrl_1000T(
1384                                   tp->link_config.flowctrl);
1385
1386                         if (phydev->pause)
1387                                 rmt_adv = LPA_PAUSE_CAP;
1388                         if (phydev->asym_pause)
1389                                 rmt_adv |= LPA_PAUSE_ASYM;
1390                 }
1391
1392                 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1393         } else
1394                 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1395
1396         if (mac_mode != tp->mac_mode) {
1397                 tp->mac_mode = mac_mode;
1398                 tw32_f(MAC_MODE, tp->mac_mode);
1399                 udelay(40);
1400         }
1401
1402         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1403                 if (phydev->speed == SPEED_10)
1404                         tw32(MAC_MI_STAT,
1405                              MAC_MI_STAT_10MBPS_MODE |
1406                              MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1407                 else
1408                         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1409         }
1410
1411         if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1412                 tw32(MAC_TX_LENGTHS,
1413                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1414                       (6 << TX_LENGTHS_IPG_SHIFT) |
1415                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1416         else
1417                 tw32(MAC_TX_LENGTHS,
1418                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1419                       (6 << TX_LENGTHS_IPG_SHIFT) |
1420                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1421
1422         if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1423             (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1424             phydev->speed != tp->link_config.active_speed ||
1425             phydev->duplex != tp->link_config.active_duplex ||
1426             oldflowctrl != tp->link_config.active_flowctrl)
1427             linkmesg = 1;
1428
1429         tp->link_config.active_speed = phydev->speed;
1430         tp->link_config.active_duplex = phydev->duplex;
1431
1432         spin_unlock_bh(&tp->lock);
1433
1434         if (linkmesg)
1435                 tg3_link_report(tp);
1436 }
1437
1438 static int tg3_phy_init(struct tg3 *tp)
1439 {
1440         struct phy_device *phydev;
1441
1442         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
1443                 return 0;
1444
1445         /* Bring the PHY back to a known state. */
1446         tg3_bmcr_reset(tp);
1447
1448         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1449
1450         /* Attach the MAC to the PHY. */
1451         phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
1452                              phydev->dev_flags, phydev->interface);
1453         if (IS_ERR(phydev)) {
1454                 printk(KERN_ERR "%s: Could not attach to PHY\n", tp->dev->name);
1455                 return PTR_ERR(phydev);
1456         }
1457
1458         /* Mask with MAC supported features. */
1459         switch (phydev->interface) {
1460         case PHY_INTERFACE_MODE_GMII:
1461         case PHY_INTERFACE_MODE_RGMII:
1462                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1463                         phydev->supported &= (PHY_GBIT_FEATURES |
1464                                               SUPPORTED_Pause |
1465                                               SUPPORTED_Asym_Pause);
1466                         break;
1467                 }
1468                 /* fallthru */
1469         case PHY_INTERFACE_MODE_MII:
1470                 phydev->supported &= (PHY_BASIC_FEATURES |
1471                                       SUPPORTED_Pause |
1472                                       SUPPORTED_Asym_Pause);
1473                 break;
1474         default:
1475                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1476                 return -EINVAL;
1477         }
1478
1479         tp->tg3_flags3 |= TG3_FLG3_PHY_CONNECTED;
1480
1481         phydev->advertising = phydev->supported;
1482
1483         return 0;
1484 }
1485
1486 static void tg3_phy_start(struct tg3 *tp)
1487 {
1488         struct phy_device *phydev;
1489
1490         if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1491                 return;
1492
1493         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1494
1495         if (tp->link_config.phy_is_low_power) {
1496                 tp->link_config.phy_is_low_power = 0;
1497                 phydev->speed = tp->link_config.orig_speed;
1498                 phydev->duplex = tp->link_config.orig_duplex;
1499                 phydev->autoneg = tp->link_config.orig_autoneg;
1500                 phydev->advertising = tp->link_config.orig_advertising;
1501         }
1502
1503         phy_start(phydev);
1504
1505         phy_start_aneg(phydev);
1506 }
1507
1508 static void tg3_phy_stop(struct tg3 *tp)
1509 {
1510         if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1511                 return;
1512
1513         phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1514 }
1515
1516 static void tg3_phy_fini(struct tg3 *tp)
1517 {
1518         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
1519                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1520                 tp->tg3_flags3 &= ~TG3_FLG3_PHY_CONNECTED;
1521         }
1522 }
1523
1524 static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1525 {
1526         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1527         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1528 }
1529
1530 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1531 {
1532         u32 phytest;
1533
1534         if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1535                 u32 phy;
1536
1537                 tg3_writephy(tp, MII_TG3_FET_TEST,
1538                              phytest | MII_TG3_FET_SHADOW_EN);
1539                 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1540                         if (enable)
1541                                 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1542                         else
1543                                 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1544                         tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1545                 }
1546                 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1547         }
1548 }
1549
1550 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1551 {
1552         u32 reg;
1553
1554         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
1555                 return;
1556
1557         if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1558                 tg3_phy_fet_toggle_apd(tp, enable);
1559                 return;
1560         }
1561
1562         reg = MII_TG3_MISC_SHDW_WREN |
1563               MII_TG3_MISC_SHDW_SCR5_SEL |
1564               MII_TG3_MISC_SHDW_SCR5_LPED |
1565               MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1566               MII_TG3_MISC_SHDW_SCR5_SDTL |
1567               MII_TG3_MISC_SHDW_SCR5_C125OE;
1568         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1569                 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1570
1571         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1572
1573
1574         reg = MII_TG3_MISC_SHDW_WREN |
1575               MII_TG3_MISC_SHDW_APD_SEL |
1576               MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1577         if (enable)
1578                 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1579
1580         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1581 }
1582
1583 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1584 {
1585         u32 phy;
1586
1587         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1588             (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1589                 return;
1590
1591         if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1592                 u32 ephy;
1593
1594                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1595                         u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1596
1597                         tg3_writephy(tp, MII_TG3_FET_TEST,
1598                                      ephy | MII_TG3_FET_SHADOW_EN);
1599                         if (!tg3_readphy(tp, reg, &phy)) {
1600                                 if (enable)
1601                                         phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1602                                 else
1603                                         phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1604                                 tg3_writephy(tp, reg, phy);
1605                         }
1606                         tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
1607                 }
1608         } else {
1609                 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1610                       MII_TG3_AUXCTL_SHDWSEL_MISC;
1611                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1612                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1613                         if (enable)
1614                                 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1615                         else
1616                                 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1617                         phy |= MII_TG3_AUXCTL_MISC_WREN;
1618                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1619                 }
1620         }
1621 }
1622
1623 static void tg3_phy_set_wirespeed(struct tg3 *tp)
1624 {
1625         u32 val;
1626
1627         if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
1628                 return;
1629
1630         if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1631             !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1632                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1633                              (val | (1 << 15) | (1 << 4)));
1634 }
1635
1636 static void tg3_phy_apply_otp(struct tg3 *tp)
1637 {
1638         u32 otp, phy;
1639
1640         if (!tp->phy_otp)
1641                 return;
1642
1643         otp = tp->phy_otp;
1644
1645         /* Enable SM_DSP clock and tx 6dB coding. */
1646         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1647               MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1648               MII_TG3_AUXCTL_ACTL_TX_6DB;
1649         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1650
1651         phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1652         phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1653         tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1654
1655         phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1656               ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1657         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1658
1659         phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1660         phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1661         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1662
1663         phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1664         tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1665
1666         phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1667         tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1668
1669         phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1670               ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1671         tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1672
1673         /* Turn off SM_DSP clock. */
1674         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1675               MII_TG3_AUXCTL_ACTL_TX_6DB;
1676         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1677 }
1678
1679 static int tg3_wait_macro_done(struct tg3 *tp)
1680 {
1681         int limit = 100;
1682
1683         while (limit--) {
1684                 u32 tmp32;
1685
1686                 if (!tg3_readphy(tp, 0x16, &tmp32)) {
1687                         if ((tmp32 & 0x1000) == 0)
1688                                 break;
1689                 }
1690         }
1691         if (limit < 0)
1692                 return -EBUSY;
1693
1694         return 0;
1695 }
1696
1697 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1698 {
1699         static const u32 test_pat[4][6] = {
1700         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1701         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1702         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1703         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1704         };
1705         int chan;
1706
1707         for (chan = 0; chan < 4; chan++) {
1708                 int i;
1709
1710                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1711                              (chan * 0x2000) | 0x0200);
1712                 tg3_writephy(tp, 0x16, 0x0002);
1713
1714                 for (i = 0; i < 6; i++)
1715                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1716                                      test_pat[chan][i]);
1717
1718                 tg3_writephy(tp, 0x16, 0x0202);
1719                 if (tg3_wait_macro_done(tp)) {
1720                         *resetp = 1;
1721                         return -EBUSY;
1722                 }
1723
1724                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1725                              (chan * 0x2000) | 0x0200);
1726                 tg3_writephy(tp, 0x16, 0x0082);
1727                 if (tg3_wait_macro_done(tp)) {
1728                         *resetp = 1;
1729                         return -EBUSY;
1730                 }
1731
1732                 tg3_writephy(tp, 0x16, 0x0802);
1733                 if (tg3_wait_macro_done(tp)) {
1734                         *resetp = 1;
1735                         return -EBUSY;
1736                 }
1737
1738                 for (i = 0; i < 6; i += 2) {
1739                         u32 low, high;
1740
1741                         if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1742                             tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1743                             tg3_wait_macro_done(tp)) {
1744                                 *resetp = 1;
1745                                 return -EBUSY;
1746                         }
1747                         low &= 0x7fff;
1748                         high &= 0x000f;
1749                         if (low != test_pat[chan][i] ||
1750                             high != test_pat[chan][i+1]) {
1751                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1752                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1753                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1754
1755                                 return -EBUSY;
1756                         }
1757                 }
1758         }
1759
1760         return 0;
1761 }
1762
1763 static int tg3_phy_reset_chanpat(struct tg3 *tp)
1764 {
1765         int chan;
1766
1767         for (chan = 0; chan < 4; chan++) {
1768                 int i;
1769
1770                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1771                              (chan * 0x2000) | 0x0200);
1772                 tg3_writephy(tp, 0x16, 0x0002);
1773                 for (i = 0; i < 6; i++)
1774                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1775                 tg3_writephy(tp, 0x16, 0x0202);
1776                 if (tg3_wait_macro_done(tp))
1777                         return -EBUSY;
1778         }
1779
1780         return 0;
1781 }
1782
1783 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1784 {
1785         u32 reg32, phy9_orig;
1786         int retries, do_phy_reset, err;
1787
1788         retries = 10;
1789         do_phy_reset = 1;
1790         do {
1791                 if (do_phy_reset) {
1792                         err = tg3_bmcr_reset(tp);
1793                         if (err)
1794                                 return err;
1795                         do_phy_reset = 0;
1796                 }
1797
1798                 /* Disable transmitter and interrupt.  */
1799                 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1800                         continue;
1801
1802                 reg32 |= 0x3000;
1803                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1804
1805                 /* Set full-duplex, 1000 mbps.  */
1806                 tg3_writephy(tp, MII_BMCR,
1807                              BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1808
1809                 /* Set to master mode.  */
1810                 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1811                         continue;
1812
1813                 tg3_writephy(tp, MII_TG3_CTRL,
1814                              (MII_TG3_CTRL_AS_MASTER |
1815                               MII_TG3_CTRL_ENABLE_AS_MASTER));
1816
1817                 /* Enable SM_DSP_CLOCK and 6dB.  */
1818                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1819
1820                 /* Block the PHY control access.  */
1821                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1822                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
1823
1824                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1825                 if (!err)
1826                         break;
1827         } while (--retries);
1828
1829         err = tg3_phy_reset_chanpat(tp);
1830         if (err)
1831                 return err;
1832
1833         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1834         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
1835
1836         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1837         tg3_writephy(tp, 0x16, 0x0000);
1838
1839         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1840             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1841                 /* Set Extended packet length bit for jumbo frames */
1842                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1843         }
1844         else {
1845                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1846         }
1847
1848         tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1849
1850         if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1851                 reg32 &= ~0x3000;
1852                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1853         } else if (!err)
1854                 err = -EBUSY;
1855
1856         return err;
1857 }
1858
1859 /* This will reset the tigon3 PHY if there is no valid
1860  * link unless the FORCE argument is non-zero.
1861  */
1862 static int tg3_phy_reset(struct tg3 *tp)
1863 {
1864         u32 cpmuctrl;
1865         u32 phy_status;
1866         int err;
1867
1868         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1869                 u32 val;
1870
1871                 val = tr32(GRC_MISC_CFG);
1872                 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1873                 udelay(40);
1874         }
1875         err  = tg3_readphy(tp, MII_BMSR, &phy_status);
1876         err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1877         if (err != 0)
1878                 return -EBUSY;
1879
1880         if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1881                 netif_carrier_off(tp->dev);
1882                 tg3_link_report(tp);
1883         }
1884
1885         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1886             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1887             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1888                 err = tg3_phy_reset_5703_4_5(tp);
1889                 if (err)
1890                         return err;
1891                 goto out;
1892         }
1893
1894         cpmuctrl = 0;
1895         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1896             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1897                 cpmuctrl = tr32(TG3_CPMU_CTRL);
1898                 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1899                         tw32(TG3_CPMU_CTRL,
1900                              cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1901         }
1902
1903         err = tg3_bmcr_reset(tp);
1904         if (err)
1905                 return err;
1906
1907         if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1908                 u32 phy;
1909
1910                 phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1911                 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy);
1912
1913                 tw32(TG3_CPMU_CTRL, cpmuctrl);
1914         }
1915
1916         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
1917             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
1918                 u32 val;
1919
1920                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1921                 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1922                     CPMU_LSPD_1000MB_MACCLK_12_5) {
1923                         val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1924                         udelay(40);
1925                         tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1926                 }
1927         }
1928
1929         tg3_phy_apply_otp(tp);
1930
1931         if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
1932                 tg3_phy_toggle_apd(tp, true);
1933         else
1934                 tg3_phy_toggle_apd(tp, false);
1935
1936 out:
1937         if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1938                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1939                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1940                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1941                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1942                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
1943                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1944         }
1945         if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
1946                 tg3_writephy(tp, 0x1c, 0x8d68);
1947                 tg3_writephy(tp, 0x1c, 0x8d68);
1948         }
1949         if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1950                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1951                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1952                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1953                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1954                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1955                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1956                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1957                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1958         }
1959         else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1960                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1961                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1962                 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1963                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1964                         tg3_writephy(tp, MII_TG3_TEST1,
1965                                      MII_TG3_TEST1_TRIM_EN | 0x4);
1966                 } else
1967                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
1968                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1969         }
1970         /* Set Extended packet length bit (bit 14) on all chips that */
1971         /* support jumbo frames */
1972         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1973                 /* Cannot do read-modify-write on 5401 */
1974                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1975         } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1976                 u32 phy_reg;
1977
1978                 /* Set bit 14 with read-modify-write to preserve other bits */
1979                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1980                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1981                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1982         }
1983
1984         /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1985          * jumbo frames transmission.
1986          */
1987         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1988                 u32 phy_reg;
1989
1990                 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
1991                     tg3_writephy(tp, MII_TG3_EXT_CTRL,
1992                                  phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1993         }
1994
1995         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1996                 /* adjust output voltage */
1997                 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
1998         }
1999
2000         tg3_phy_toggle_automdix(tp, 1);
2001         tg3_phy_set_wirespeed(tp);
2002         return 0;
2003 }
2004
2005 static void tg3_frob_aux_power(struct tg3 *tp)
2006 {
2007         struct tg3 *tp_peer = tp;
2008
2009         if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
2010                 return;
2011
2012         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2013             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
2014             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
2015                 struct net_device *dev_peer;
2016
2017                 dev_peer = pci_get_drvdata(tp->pdev_peer);
2018                 /* remove_one() may have been run on the peer. */
2019                 if (!dev_peer)
2020                         tp_peer = tp;
2021                 else
2022                         tp_peer = netdev_priv(dev_peer);
2023         }
2024
2025         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2026             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
2027             (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2028             (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
2029                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2030                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2031                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2032                                     (GRC_LCLCTRL_GPIO_OE0 |
2033                                      GRC_LCLCTRL_GPIO_OE1 |
2034                                      GRC_LCLCTRL_GPIO_OE2 |
2035                                      GRC_LCLCTRL_GPIO_OUTPUT0 |
2036                                      GRC_LCLCTRL_GPIO_OUTPUT1),
2037                                     100);
2038                 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2039                            tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2040                         /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2041                         u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2042                                              GRC_LCLCTRL_GPIO_OE1 |
2043                                              GRC_LCLCTRL_GPIO_OE2 |
2044                                              GRC_LCLCTRL_GPIO_OUTPUT0 |
2045                                              GRC_LCLCTRL_GPIO_OUTPUT1 |
2046                                              tp->grc_local_ctrl;
2047                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2048
2049                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2050                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2051
2052                         grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2053                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2054                 } else {
2055                         u32 no_gpio2;
2056                         u32 grc_local_ctrl = 0;
2057
2058                         if (tp_peer != tp &&
2059                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2060                                 return;
2061
2062                         /* Workaround to prevent overdrawing Amps. */
2063                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2064                             ASIC_REV_5714) {
2065                                 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2066                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2067                                             grc_local_ctrl, 100);
2068                         }
2069
2070                         /* On 5753 and variants, GPIO2 cannot be used. */
2071                         no_gpio2 = tp->nic_sram_data_cfg &
2072                                     NIC_SRAM_DATA_CFG_NO_GPIO2;
2073
2074                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2075                                          GRC_LCLCTRL_GPIO_OE1 |
2076                                          GRC_LCLCTRL_GPIO_OE2 |
2077                                          GRC_LCLCTRL_GPIO_OUTPUT1 |
2078                                          GRC_LCLCTRL_GPIO_OUTPUT2;
2079                         if (no_gpio2) {
2080                                 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2081                                                     GRC_LCLCTRL_GPIO_OUTPUT2);
2082                         }
2083                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2084                                                     grc_local_ctrl, 100);
2085
2086                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2087
2088                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2089                                                     grc_local_ctrl, 100);
2090
2091                         if (!no_gpio2) {
2092                                 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2093                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2094                                             grc_local_ctrl, 100);
2095                         }
2096                 }
2097         } else {
2098                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2099                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2100                         if (tp_peer != tp &&
2101                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2102                                 return;
2103
2104                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2105                                     (GRC_LCLCTRL_GPIO_OE1 |
2106                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2107
2108                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2109                                     GRC_LCLCTRL_GPIO_OE1, 100);
2110
2111                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2112                                     (GRC_LCLCTRL_GPIO_OE1 |
2113                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2114                 }
2115         }
2116 }
2117
2118 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2119 {
2120         if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2121                 return 1;
2122         else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411) {
2123                 if (speed != SPEED_10)
2124                         return 1;
2125         } else if (speed == SPEED_10)
2126                 return 1;
2127
2128         return 0;
2129 }
2130
2131 static int tg3_setup_phy(struct tg3 *, int);
2132
2133 #define RESET_KIND_SHUTDOWN     0
2134 #define RESET_KIND_INIT         1
2135 #define RESET_KIND_SUSPEND      2
2136
2137 static void tg3_write_sig_post_reset(struct tg3 *, int);
2138 static int tg3_halt_cpu(struct tg3 *, u32);
2139
2140 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2141 {
2142         u32 val;
2143
2144         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2145                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2146                         u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2147                         u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2148
2149                         sg_dig_ctrl |=
2150                                 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2151                         tw32(SG_DIG_CTRL, sg_dig_ctrl);
2152                         tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2153                 }
2154                 return;
2155         }
2156
2157         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2158                 tg3_bmcr_reset(tp);
2159                 val = tr32(GRC_MISC_CFG);
2160                 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2161                 udelay(40);
2162                 return;
2163         } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
2164                 u32 phytest;
2165                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2166                         u32 phy;
2167
2168                         tg3_writephy(tp, MII_ADVERTISE, 0);
2169                         tg3_writephy(tp, MII_BMCR,
2170                                      BMCR_ANENABLE | BMCR_ANRESTART);
2171
2172                         tg3_writephy(tp, MII_TG3_FET_TEST,
2173                                      phytest | MII_TG3_FET_SHADOW_EN);
2174                         if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
2175                                 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
2176                                 tg3_writephy(tp,
2177                                              MII_TG3_FET_SHDW_AUXMODE4,
2178                                              phy);
2179                         }
2180                         tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2181                 }
2182                 return;
2183         } else if (do_low_power) {
2184                 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2185                              MII_TG3_EXT_CTRL_FORCE_LED_OFF);
2186
2187                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2188                              MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2189                              MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2190                              MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2191                              MII_TG3_AUXCTL_PCTL_VREG_11V);
2192         }
2193
2194         /* The PHY should not be powered down on some chips because
2195          * of bugs.
2196          */
2197         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2198             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2199             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2200              (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
2201                 return;
2202
2203         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2204             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2205                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2206                 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2207                 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2208                 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2209         }
2210
2211         tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2212 }
2213
2214 /* tp->lock is held. */
2215 static int tg3_nvram_lock(struct tg3 *tp)
2216 {
2217         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2218                 int i;
2219
2220                 if (tp->nvram_lock_cnt == 0) {
2221                         tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2222                         for (i = 0; i < 8000; i++) {
2223                                 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2224                                         break;
2225                                 udelay(20);
2226                         }
2227                         if (i == 8000) {
2228                                 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2229                                 return -ENODEV;
2230                         }
2231                 }
2232                 tp->nvram_lock_cnt++;
2233         }
2234         return 0;
2235 }
2236
2237 /* tp->lock is held. */
2238 static void tg3_nvram_unlock(struct tg3 *tp)
2239 {
2240         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2241                 if (tp->nvram_lock_cnt > 0)
2242                         tp->nvram_lock_cnt--;
2243                 if (tp->nvram_lock_cnt == 0)
2244                         tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2245         }
2246 }
2247
2248 /* tp->lock is held. */
2249 static void tg3_enable_nvram_access(struct tg3 *tp)
2250 {
2251         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2252             !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2253                 u32 nvaccess = tr32(NVRAM_ACCESS);
2254
2255                 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2256         }
2257 }
2258
2259 /* tp->lock is held. */
2260 static void tg3_disable_nvram_access(struct tg3 *tp)
2261 {
2262         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2263             !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2264                 u32 nvaccess = tr32(NVRAM_ACCESS);
2265
2266                 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2267         }
2268 }
2269
2270 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2271                                         u32 offset, u32 *val)
2272 {
2273         u32 tmp;
2274         int i;
2275
2276         if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2277                 return -EINVAL;
2278
2279         tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2280                                         EEPROM_ADDR_DEVID_MASK |
2281                                         EEPROM_ADDR_READ);
2282         tw32(GRC_EEPROM_ADDR,
2283              tmp |
2284              (0 << EEPROM_ADDR_DEVID_SHIFT) |
2285              ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2286               EEPROM_ADDR_ADDR_MASK) |
2287              EEPROM_ADDR_READ | EEPROM_ADDR_START);
2288
2289         for (i = 0; i < 1000; i++) {
2290                 tmp = tr32(GRC_EEPROM_ADDR);
2291
2292                 if (tmp & EEPROM_ADDR_COMPLETE)
2293                         break;
2294                 msleep(1);
2295         }
2296         if (!(tmp & EEPROM_ADDR_COMPLETE))
2297                 return -EBUSY;
2298
2299         tmp = tr32(GRC_EEPROM_DATA);
2300
2301         /*
2302          * The data will always be opposite the native endian
2303          * format.  Perform a blind byteswap to compensate.
2304          */
2305         *val = swab32(tmp);
2306
2307         return 0;
2308 }
2309
2310 #define NVRAM_CMD_TIMEOUT 10000
2311
2312 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2313 {
2314         int i;
2315
2316         tw32(NVRAM_CMD, nvram_cmd);
2317         for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2318                 udelay(10);
2319                 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2320                         udelay(10);
2321                         break;
2322                 }
2323         }
2324
2325         if (i == NVRAM_CMD_TIMEOUT)
2326                 return -EBUSY;
2327
2328         return 0;
2329 }
2330
2331 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2332 {
2333         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2334             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2335             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2336            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2337             (tp->nvram_jedecnum == JEDEC_ATMEL))
2338
2339                 addr = ((addr / tp->nvram_pagesize) <<
2340                         ATMEL_AT45DB0X1B_PAGE_POS) +
2341                        (addr % tp->nvram_pagesize);
2342
2343         return addr;
2344 }
2345
2346 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2347 {
2348         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2349             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2350             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2351            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2352             (tp->nvram_jedecnum == JEDEC_ATMEL))
2353
2354                 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2355                         tp->nvram_pagesize) +
2356                        (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2357
2358         return addr;
2359 }
2360
2361 /* NOTE: Data read in from NVRAM is byteswapped according to
2362  * the byteswapping settings for all other register accesses.
2363  * tg3 devices are BE devices, so on a BE machine, the data
2364  * returned will be exactly as it is seen in NVRAM.  On a LE
2365  * machine, the 32-bit value will be byteswapped.
2366  */
2367 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2368 {
2369         int ret;
2370
2371         if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2372                 return tg3_nvram_read_using_eeprom(tp, offset, val);
2373
2374         offset = tg3_nvram_phys_addr(tp, offset);
2375
2376         if (offset > NVRAM_ADDR_MSK)
2377                 return -EINVAL;
2378
2379         ret = tg3_nvram_lock(tp);
2380         if (ret)
2381                 return ret;
2382
2383         tg3_enable_nvram_access(tp);
2384
2385         tw32(NVRAM_ADDR, offset);
2386         ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2387                 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2388
2389         if (ret == 0)
2390                 *val = tr32(NVRAM_RDDATA);
2391
2392         tg3_disable_nvram_access(tp);
2393
2394         tg3_nvram_unlock(tp);
2395
2396         return ret;
2397 }
2398
2399 /* Ensures NVRAM data is in bytestream format. */
2400 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
2401 {
2402         u32 v;
2403         int res = tg3_nvram_read(tp, offset, &v);
2404         if (!res)
2405                 *val = cpu_to_be32(v);
2406         return res;
2407 }
2408
2409 /* tp->lock is held. */
2410 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2411 {
2412         u32 addr_high, addr_low;
2413         int i;
2414
2415         addr_high = ((tp->dev->dev_addr[0] << 8) |
2416                      tp->dev->dev_addr[1]);
2417         addr_low = ((tp->dev->dev_addr[2] << 24) |
2418                     (tp->dev->dev_addr[3] << 16) |
2419                     (tp->dev->dev_addr[4] <<  8) |
2420                     (tp->dev->dev_addr[5] <<  0));
2421         for (i = 0; i < 4; i++) {
2422                 if (i == 1 && skip_mac_1)
2423                         continue;
2424                 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2425                 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2426         }
2427
2428         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2429             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2430                 for (i = 0; i < 12; i++) {
2431                         tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2432                         tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2433                 }
2434         }
2435
2436         addr_high = (tp->dev->dev_addr[0] +
2437                      tp->dev->dev_addr[1] +
2438                      tp->dev->dev_addr[2] +
2439                      tp->dev->dev_addr[3] +
2440                      tp->dev->dev_addr[4] +
2441                      tp->dev->dev_addr[5]) &
2442                 TX_BACKOFF_SEED_MASK;
2443         tw32(MAC_TX_BACKOFF_SEED, addr_high);
2444 }
2445
2446 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
2447 {
2448         u32 misc_host_ctrl;
2449         bool device_should_wake, do_low_power;
2450
2451         /* Make sure register accesses (indirect or otherwise)
2452          * will function correctly.
2453          */
2454         pci_write_config_dword(tp->pdev,
2455                                TG3PCI_MISC_HOST_CTRL,
2456                                tp->misc_host_ctrl);
2457
2458         switch (state) {
2459         case PCI_D0:
2460                 pci_enable_wake(tp->pdev, state, false);
2461                 pci_set_power_state(tp->pdev, PCI_D0);
2462
2463                 /* Switch out of Vaux if it is a NIC */
2464                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
2465                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
2466
2467                 return 0;
2468
2469         case PCI_D1:
2470         case PCI_D2:
2471         case PCI_D3hot:
2472                 break;
2473
2474         default:
2475                 printk(KERN_ERR PFX "%s: Invalid power state (D%d) requested\n",
2476                         tp->dev->name, state);
2477                 return -EINVAL;
2478         }
2479
2480         /* Restore the CLKREQ setting. */
2481         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2482                 u16 lnkctl;
2483
2484                 pci_read_config_word(tp->pdev,
2485                                      tp->pcie_cap + PCI_EXP_LNKCTL,
2486                                      &lnkctl);
2487                 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2488                 pci_write_config_word(tp->pdev,
2489                                       tp->pcie_cap + PCI_EXP_LNKCTL,
2490                                       lnkctl);
2491         }
2492
2493         misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2494         tw32(TG3PCI_MISC_HOST_CTRL,
2495              misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2496
2497         device_should_wake = pci_pme_capable(tp->pdev, state) &&
2498                              device_may_wakeup(&tp->pdev->dev) &&
2499                              (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2500
2501         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
2502                 do_low_power = false;
2503                 if ((tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) &&
2504                     !tp->link_config.phy_is_low_power) {
2505                         struct phy_device *phydev;
2506                         u32 phyid, advertising;
2507
2508                         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
2509
2510                         tp->link_config.phy_is_low_power = 1;
2511
2512                         tp->link_config.orig_speed = phydev->speed;
2513                         tp->link_config.orig_duplex = phydev->duplex;
2514                         tp->link_config.orig_autoneg = phydev->autoneg;
2515                         tp->link_config.orig_advertising = phydev->advertising;
2516
2517                         advertising = ADVERTISED_TP |
2518                                       ADVERTISED_Pause |
2519                                       ADVERTISED_Autoneg |
2520                                       ADVERTISED_10baseT_Half;
2521
2522                         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2523                             device_should_wake) {
2524                                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2525                                         advertising |=
2526                                                 ADVERTISED_100baseT_Half |
2527                                                 ADVERTISED_100baseT_Full |
2528                                                 ADVERTISED_10baseT_Full;
2529                                 else
2530                                         advertising |= ADVERTISED_10baseT_Full;
2531                         }
2532
2533                         phydev->advertising = advertising;
2534
2535                         phy_start_aneg(phydev);
2536
2537                         phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2538                         if (phyid != TG3_PHY_ID_BCMAC131) {
2539                                 phyid &= TG3_PHY_OUI_MASK;
2540                                 if (phyid == TG3_PHY_OUI_1 ||
2541                                     phyid == TG3_PHY_OUI_2 ||
2542                                     phyid == TG3_PHY_OUI_3)
2543                                         do_low_power = true;
2544                         }
2545                 }
2546         } else {
2547                 do_low_power = true;
2548
2549                 if (tp->link_config.phy_is_low_power == 0) {
2550                         tp->link_config.phy_is_low_power = 1;
2551                         tp->link_config.orig_speed = tp->link_config.speed;
2552                         tp->link_config.orig_duplex = tp->link_config.duplex;
2553                         tp->link_config.orig_autoneg = tp->link_config.autoneg;
2554                 }
2555
2556                 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
2557                         tp->link_config.speed = SPEED_10;
2558                         tp->link_config.duplex = DUPLEX_HALF;
2559                         tp->link_config.autoneg = AUTONEG_ENABLE;
2560                         tg3_setup_phy(tp, 0);
2561                 }
2562         }
2563
2564         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2565                 u32 val;
2566
2567                 val = tr32(GRC_VCPU_EXT_CTRL);
2568                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2569         } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2570                 int i;
2571                 u32 val;
2572
2573                 for (i = 0; i < 200; i++) {
2574                         tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2575                         if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2576                                 break;
2577                         msleep(1);
2578                 }
2579         }
2580         if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2581                 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2582                                                      WOL_DRV_STATE_SHUTDOWN |
2583                                                      WOL_DRV_WOL |
2584                                                      WOL_SET_MAGIC_PKT);
2585
2586         if (device_should_wake) {
2587                 u32 mac_mode;
2588
2589                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
2590                         if (do_low_power) {
2591                                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2592                                 udelay(40);
2593                         }
2594
2595                         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
2596                                 mac_mode = MAC_MODE_PORT_MODE_GMII;
2597                         else
2598                                 mac_mode = MAC_MODE_PORT_MODE_MII;
2599
2600                         mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2601                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2602                             ASIC_REV_5700) {
2603                                 u32 speed = (tp->tg3_flags &
2604                                              TG3_FLAG_WOL_SPEED_100MB) ?
2605                                              SPEED_100 : SPEED_10;
2606                                 if (tg3_5700_link_polarity(tp, speed))
2607                                         mac_mode |= MAC_MODE_LINK_POLARITY;
2608                                 else
2609                                         mac_mode &= ~MAC_MODE_LINK_POLARITY;
2610                         }
2611                 } else {
2612                         mac_mode = MAC_MODE_PORT_MODE_TBI;
2613                 }
2614
2615                 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
2616                         tw32(MAC_LED_CTRL, tp->led_ctrl);
2617
2618                 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2619                 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2620                     !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2621                     ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2622                      (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2623                         mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
2624
2625                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2626                         mac_mode |= tp->mac_mode &
2627                                     (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
2628                         if (mac_mode & MAC_MODE_APE_TX_EN)
2629                                 mac_mode |= MAC_MODE_TDE_ENABLE;
2630                 }
2631
2632                 tw32_f(MAC_MODE, mac_mode);
2633                 udelay(100);
2634
2635                 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2636                 udelay(10);
2637         }
2638
2639         if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2640             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2641              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2642                 u32 base_val;
2643
2644                 base_val = tp->pci_clock_ctrl;
2645                 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2646                              CLOCK_CTRL_TXCLK_DISABLE);
2647
2648                 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2649                             CLOCK_CTRL_PWRDOWN_PLL133, 40);
2650         } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
2651                    (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
2652                    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
2653                 /* do nothing */
2654         } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2655                      (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2656                 u32 newbits1, newbits2;
2657
2658                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2659                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2660                         newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2661                                     CLOCK_CTRL_TXCLK_DISABLE |
2662                                     CLOCK_CTRL_ALTCLK);
2663                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2664                 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2665                         newbits1 = CLOCK_CTRL_625_CORE;
2666                         newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2667                 } else {
2668                         newbits1 = CLOCK_CTRL_ALTCLK;
2669                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2670                 }
2671
2672                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2673                             40);
2674
2675                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2676                             40);
2677
2678                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2679                         u32 newbits3;
2680
2681                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2682                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2683                                 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2684                                             CLOCK_CTRL_TXCLK_DISABLE |
2685                                             CLOCK_CTRL_44MHZ_CORE);
2686                         } else {
2687                                 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2688                         }
2689
2690                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
2691                                     tp->pci_clock_ctrl | newbits3, 40);
2692                 }
2693         }
2694
2695         if (!(device_should_wake) &&
2696             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
2697                 tg3_power_down_phy(tp, do_low_power);
2698
2699         tg3_frob_aux_power(tp);
2700
2701         /* Workaround for unstable PLL clock */
2702         if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2703             (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2704                 u32 val = tr32(0x7d00);
2705
2706                 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2707                 tw32(0x7d00, val);
2708                 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2709                         int err;
2710
2711                         err = tg3_nvram_lock(tp);
2712                         tg3_halt_cpu(tp, RX_CPU_BASE);
2713                         if (!err)
2714                                 tg3_nvram_unlock(tp);
2715                 }
2716         }
2717
2718         tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2719
2720         if (device_should_wake)
2721                 pci_enable_wake(tp->pdev, state, true);
2722
2723         /* Finally, set the new power state. */
2724         pci_set_power_state(tp->pdev, state);
2725
2726         return 0;
2727 }
2728
2729 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2730 {
2731         switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2732         case MII_TG3_AUX_STAT_10HALF:
2733                 *speed = SPEED_10;
2734                 *duplex = DUPLEX_HALF;
2735                 break;
2736
2737         case MII_TG3_AUX_STAT_10FULL:
2738                 *speed = SPEED_10;
2739                 *duplex = DUPLEX_FULL;
2740                 break;
2741
2742         case MII_TG3_AUX_STAT_100HALF:
2743                 *speed = SPEED_100;
2744                 *duplex = DUPLEX_HALF;
2745                 break;
2746
2747         case MII_TG3_AUX_STAT_100FULL:
2748                 *speed = SPEED_100;
2749                 *duplex = DUPLEX_FULL;
2750                 break;
2751
2752         case MII_TG3_AUX_STAT_1000HALF:
2753                 *speed = SPEED_1000;
2754                 *duplex = DUPLEX_HALF;
2755                 break;
2756
2757         case MII_TG3_AUX_STAT_1000FULL:
2758                 *speed = SPEED_1000;
2759                 *duplex = DUPLEX_FULL;
2760                 break;
2761
2762         default:
2763                 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
2764                         *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2765                                  SPEED_10;
2766                         *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2767                                   DUPLEX_HALF;
2768                         break;
2769                 }
2770                 *speed = SPEED_INVALID;
2771                 *duplex = DUPLEX_INVALID;
2772                 break;
2773         }
2774 }
2775
2776 static void tg3_phy_copper_begin(struct tg3 *tp)
2777 {
2778         u32 new_adv;
2779         int i;
2780
2781         if (tp->link_config.phy_is_low_power) {
2782                 /* Entering low power mode.  Disable gigabit and
2783                  * 100baseT advertisements.
2784                  */
2785                 tg3_writephy(tp, MII_TG3_CTRL, 0);
2786
2787                 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2788                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2789                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2790                         new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2791
2792                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2793         } else if (tp->link_config.speed == SPEED_INVALID) {
2794                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
2795                         tp->link_config.advertising &=
2796                                 ~(ADVERTISED_1000baseT_Half |
2797                                   ADVERTISED_1000baseT_Full);
2798
2799                 new_adv = ADVERTISE_CSMA;
2800                 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2801                         new_adv |= ADVERTISE_10HALF;
2802                 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2803                         new_adv |= ADVERTISE_10FULL;
2804                 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2805                         new_adv |= ADVERTISE_100HALF;
2806                 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2807                         new_adv |= ADVERTISE_100FULL;
2808
2809                 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2810
2811                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2812
2813                 if (tp->link_config.advertising &
2814                     (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2815                         new_adv = 0;
2816                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2817                                 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2818                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2819                                 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2820                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
2821                             (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2822                              tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2823                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2824                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2825                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2826                 } else {
2827                         tg3_writephy(tp, MII_TG3_CTRL, 0);
2828                 }
2829         } else {
2830                 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2831                 new_adv |= ADVERTISE_CSMA;
2832
2833                 /* Asking for a specific link mode. */
2834                 if (tp->link_config.speed == SPEED_1000) {
2835                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2836
2837                         if (tp->link_config.duplex == DUPLEX_FULL)
2838                                 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2839                         else
2840                                 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2841                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2842                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2843                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2844                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2845                 } else {
2846                         if (tp->link_config.speed == SPEED_100) {
2847                                 if (tp->link_config.duplex == DUPLEX_FULL)
2848                                         new_adv |= ADVERTISE_100FULL;
2849                                 else
2850                                         new_adv |= ADVERTISE_100HALF;
2851                         } else {
2852                                 if (tp->link_config.duplex == DUPLEX_FULL)
2853                                         new_adv |= ADVERTISE_10FULL;
2854                                 else
2855                                         new_adv |= ADVERTISE_10HALF;
2856                         }
2857                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2858
2859                         new_adv = 0;
2860                 }
2861
2862                 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2863         }
2864
2865         if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2866             tp->link_config.speed != SPEED_INVALID) {
2867                 u32 bmcr, orig_bmcr;
2868
2869                 tp->link_config.active_speed = tp->link_config.speed;
2870                 tp->link_config.active_duplex = tp->link_config.duplex;
2871
2872                 bmcr = 0;
2873                 switch (tp->link_config.speed) {
2874                 default:
2875                 case SPEED_10:
2876                         break;
2877
2878                 case SPEED_100:
2879                         bmcr |= BMCR_SPEED100;
2880                         break;
2881
2882                 case SPEED_1000:
2883                         bmcr |= TG3_BMCR_SPEED1000;
2884                         break;
2885                 }
2886
2887                 if (tp->link_config.duplex == DUPLEX_FULL)
2888                         bmcr |= BMCR_FULLDPLX;
2889
2890                 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2891                     (bmcr != orig_bmcr)) {
2892                         tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2893                         for (i = 0; i < 1500; i++) {
2894                                 u32 tmp;
2895
2896                                 udelay(10);
2897                                 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2898                                     tg3_readphy(tp, MII_BMSR, &tmp))
2899                                         continue;
2900                                 if (!(tmp & BMSR_LSTATUS)) {
2901                                         udelay(40);
2902                                         break;
2903                                 }
2904                         }
2905                         tg3_writephy(tp, MII_BMCR, bmcr);
2906                         udelay(40);
2907                 }
2908         } else {
2909                 tg3_writephy(tp, MII_BMCR,
2910                              BMCR_ANENABLE | BMCR_ANRESTART);
2911         }
2912 }
2913
2914 static int tg3_init_5401phy_dsp(struct tg3 *tp)
2915 {
2916         int err;
2917
2918         /* Turn off tap power management. */
2919         /* Set Extended packet length bit */
2920         err  = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2921
2922         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
2923         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
2924
2925         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
2926         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
2927
2928         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2929         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
2930
2931         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2932         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
2933
2934         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2935         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
2936
2937         udelay(40);
2938
2939         return err;
2940 }
2941
2942 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
2943 {
2944         u32 adv_reg, all_mask = 0;
2945
2946         if (mask & ADVERTISED_10baseT_Half)
2947                 all_mask |= ADVERTISE_10HALF;
2948         if (mask & ADVERTISED_10baseT_Full)
2949                 all_mask |= ADVERTISE_10FULL;
2950         if (mask & ADVERTISED_100baseT_Half)
2951                 all_mask |= ADVERTISE_100HALF;
2952         if (mask & ADVERTISED_100baseT_Full)
2953                 all_mask |= ADVERTISE_100FULL;
2954
2955         if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
2956                 return 0;
2957
2958         if ((adv_reg & all_mask) != all_mask)
2959                 return 0;
2960         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
2961                 u32 tg3_ctrl;
2962
2963                 all_mask = 0;
2964                 if (mask & ADVERTISED_1000baseT_Half)
2965                         all_mask |= ADVERTISE_1000HALF;
2966                 if (mask & ADVERTISED_1000baseT_Full)
2967                         all_mask |= ADVERTISE_1000FULL;
2968
2969                 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
2970                         return 0;
2971
2972                 if ((tg3_ctrl & all_mask) != all_mask)
2973                         return 0;
2974         }
2975         return 1;
2976 }
2977
2978 static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
2979 {
2980         u32 curadv, reqadv;
2981
2982         if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
2983                 return 1;
2984
2985         curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2986         reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2987
2988         if (tp->link_config.active_duplex == DUPLEX_FULL) {
2989                 if (curadv != reqadv)
2990                         return 0;
2991
2992                 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
2993                         tg3_readphy(tp, MII_LPA, rmtadv);
2994         } else {
2995                 /* Reprogram the advertisement register, even if it
2996                  * does not affect the current link.  If the link
2997                  * gets renegotiated in the future, we can save an
2998                  * additional renegotiation cycle by advertising
2999                  * it correctly in the first place.
3000                  */
3001                 if (curadv != reqadv) {
3002                         *lcladv &= ~(ADVERTISE_PAUSE_CAP |
3003                                      ADVERTISE_PAUSE_ASYM);
3004                         tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
3005                 }
3006         }
3007
3008         return 1;
3009 }
3010
3011 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
3012 {
3013         int current_link_up;
3014         u32 bmsr, dummy;
3015         u32 lcl_adv, rmt_adv;
3016         u16 current_speed;
3017         u8 current_duplex;
3018         int i, err;
3019
3020         tw32(MAC_EVENT, 0);
3021
3022         tw32_f(MAC_STATUS,
3023              (MAC_STATUS_SYNC_CHANGED |
3024               MAC_STATUS_CFG_CHANGED |
3025               MAC_STATUS_MI_COMPLETION |
3026               MAC_STATUS_LNKSTATE_CHANGED));
3027         udelay(40);
3028
3029         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
3030                 tw32_f(MAC_MI_MODE,
3031                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
3032                 udelay(80);
3033         }
3034
3035         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
3036
3037         /* Some third-party PHYs need to be reset on link going
3038          * down.
3039          */
3040         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3041              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
3042              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
3043             netif_carrier_ok(tp->dev)) {
3044                 tg3_readphy(tp, MII_BMSR, &bmsr);
3045                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3046                     !(bmsr & BMSR_LSTATUS))
3047                         force_reset = 1;
3048         }
3049         if (force_reset)
3050                 tg3_phy_reset(tp);
3051
3052         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
3053                 tg3_readphy(tp, MII_BMSR, &bmsr);
3054                 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
3055                     !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
3056                         bmsr = 0;
3057
3058                 if (!(bmsr & BMSR_LSTATUS)) {
3059                         err = tg3_init_5401phy_dsp(tp);
3060                         if (err)
3061                                 return err;
3062
3063                         tg3_readphy(tp, MII_BMSR, &bmsr);
3064                         for (i = 0; i < 1000; i++) {
3065                                 udelay(10);
3066                                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3067                                     (bmsr & BMSR_LSTATUS)) {
3068                                         udelay(40);
3069                                         break;
3070                                 }
3071                         }
3072
3073                         if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
3074                             !(bmsr & BMSR_LSTATUS) &&
3075                             tp->link_config.active_speed == SPEED_1000) {
3076                                 err = tg3_phy_reset(tp);
3077                                 if (!err)
3078                                         err = tg3_init_5401phy_dsp(tp);
3079                                 if (err)
3080                                         return err;
3081                         }
3082                 }
3083         } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3084                    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3085                 /* 5701 {A0,B0} CRC bug workaround */
3086                 tg3_writephy(tp, 0x15, 0x0a75);
3087                 tg3_writephy(tp, 0x1c, 0x8c68);
3088                 tg3_writephy(tp, 0x1c, 0x8d68);
3089                 tg3_writephy(tp, 0x1c, 0x8c68);
3090         }
3091
3092         /* Clear pending interrupts... */
3093         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3094         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3095
3096         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
3097                 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
3098         else if (!(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
3099                 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3100
3101         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3102             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3103                 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3104                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
3105                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3106                 else
3107                         tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3108         }
3109
3110         current_link_up = 0;
3111         current_speed = SPEED_INVALID;
3112         current_duplex = DUPLEX_INVALID;
3113
3114         if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
3115                 u32 val;
3116
3117                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3118                 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3119                 if (!(val & (1 << 10))) {
3120                         val |= (1 << 10);
3121                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3122                         goto relink;
3123                 }
3124         }
3125
3126         bmsr = 0;
3127         for (i = 0; i < 100; i++) {
3128                 tg3_readphy(tp, MII_BMSR, &bmsr);
3129                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3130                     (bmsr & BMSR_LSTATUS))
3131                         break;
3132                 udelay(40);
3133         }
3134
3135         if (bmsr & BMSR_LSTATUS) {
3136                 u32 aux_stat, bmcr;
3137
3138                 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3139                 for (i = 0; i < 2000; i++) {
3140                         udelay(10);
3141                         if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3142                             aux_stat)
3143                                 break;
3144                 }
3145
3146                 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3147                                              &current_speed,
3148                                              &current_duplex);
3149
3150                 bmcr = 0;
3151                 for (i = 0; i < 200; i++) {
3152                         tg3_readphy(tp, MII_BMCR, &bmcr);
3153                         if (tg3_readphy(tp, MII_BMCR, &bmcr))
3154                                 continue;
3155                         if (bmcr && bmcr != 0x7fff)
3156                                 break;
3157                         udelay(10);
3158                 }
3159
3160                 lcl_adv = 0;
3161                 rmt_adv = 0;
3162
3163                 tp->link_config.active_speed = current_speed;
3164                 tp->link_config.active_duplex = current_duplex;
3165
3166                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3167                         if ((bmcr & BMCR_ANENABLE) &&
3168                             tg3_copper_is_advertising_all(tp,
3169                                                 tp->link_config.advertising)) {
3170                                 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3171                                                                   &rmt_adv))
3172                                         current_link_up = 1;
3173                         }
3174                 } else {
3175                         if (!(bmcr & BMCR_ANENABLE) &&
3176                             tp->link_config.speed == current_speed &&
3177                             tp->link_config.duplex == current_duplex &&
3178                             tp->link_config.flowctrl ==
3179                             tp->link_config.active_flowctrl) {
3180                                 current_link_up = 1;
3181                         }
3182                 }
3183
3184                 if (current_link_up == 1 &&
3185                     tp->link_config.active_duplex == DUPLEX_FULL)
3186                         tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
3187         }
3188
3189 relink:
3190         if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
3191                 u32 tmp;
3192
3193                 tg3_phy_copper_begin(tp);
3194
3195                 tg3_readphy(tp, MII_BMSR, &tmp);
3196                 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
3197                     (tmp & BMSR_LSTATUS))
3198                         current_link_up = 1;
3199         }
3200
3201         tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3202         if (current_link_up == 1) {
3203                 if (tp->link_config.active_speed == SPEED_100 ||
3204                     tp->link_config.active_speed == SPEED_10)
3205                         tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3206                 else
3207                         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3208         } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)
3209                 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3210         else
3211                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3212
3213         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3214         if (tp->link_config.active_duplex == DUPLEX_HALF)
3215                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3216
3217         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
3218                 if (current_link_up == 1 &&
3219                     tg3_5700_link_polarity(tp, tp->link_config.active_speed))
3220                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
3221                 else
3222                         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
3223         }
3224
3225         /* ??? Without this setting Netgear GA302T PHY does not
3226          * ??? send/receive packets...
3227          */
3228         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
3229             tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3230                 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3231                 tw32_f(MAC_MI_MODE, tp->mi_mode);
3232                 udelay(80);
3233         }
3234
3235         tw32_f(MAC_MODE, tp->mac_mode);
3236         udelay(40);
3237
3238         if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3239                 /* Polled via timer. */
3240                 tw32_f(MAC_EVENT, 0);
3241         } else {
3242                 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3243         }
3244         udelay(40);
3245
3246         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3247             current_link_up == 1 &&
3248             tp->link_config.active_speed == SPEED_1000 &&
3249             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3250              (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3251                 udelay(120);
3252                 tw32_f(MAC_STATUS,
3253                      (MAC_STATUS_SYNC_CHANGED |
3254                       MAC_STATUS_CFG_CHANGED));
3255                 udelay(40);
3256                 tg3_write_mem(tp,
3257                               NIC_SRAM_FIRMWARE_MBOX,
3258                               NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3259         }
3260
3261         /* Prevent send BD corruption. */
3262         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3263                 u16 oldlnkctl, newlnkctl;
3264
3265                 pci_read_config_word(tp->pdev,
3266                                      tp->pcie_cap + PCI_EXP_LNKCTL,
3267                                      &oldlnkctl);
3268                 if (tp->link_config.active_speed == SPEED_100 ||
3269                     tp->link_config.active_speed == SPEED_10)
3270                         newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3271                 else
3272                         newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3273                 if (newlnkctl != oldlnkctl)
3274                         pci_write_config_word(tp->pdev,
3275                                               tp->pcie_cap + PCI_EXP_LNKCTL,
3276                                               newlnkctl);
3277         }
3278
3279         if (current_link_up != netif_carrier_ok(tp->dev)) {
3280                 if (current_link_up)
3281                         netif_carrier_on(tp->dev);
3282                 else
3283                         netif_carrier_off(tp->dev);
3284                 tg3_link_report(tp);
3285         }
3286
3287         return 0;
3288 }
3289
3290 struct tg3_fiber_aneginfo {
3291         int state;
3292 #define ANEG_STATE_UNKNOWN              0
3293 #define ANEG_STATE_AN_ENABLE            1
3294 #define ANEG_STATE_RESTART_INIT         2
3295 #define ANEG_STATE_RESTART              3
3296 #define ANEG_STATE_DISABLE_LINK_OK      4
3297 #define ANEG_STATE_ABILITY_DETECT_INIT  5
3298 #define ANEG_STATE_ABILITY_DETECT       6
3299 #define ANEG_STATE_ACK_DETECT_INIT      7
3300 #define ANEG_STATE_ACK_DETECT           8
3301 #define ANEG_STATE_COMPLETE_ACK_INIT    9
3302 #define ANEG_STATE_COMPLETE_ACK         10
3303 #define ANEG_STATE_IDLE_DETECT_INIT     11
3304 #define ANEG_STATE_IDLE_DETECT          12
3305 #define ANEG_STATE_LINK_OK              13
3306 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT  14
3307 #define ANEG_STATE_NEXT_PAGE_WAIT       15
3308
3309         u32 flags;
3310 #define MR_AN_ENABLE            0x00000001
3311 #define MR_RESTART_AN           0x00000002
3312 #define MR_AN_COMPLETE          0x00000004
3313 #define MR_PAGE_RX              0x00000008
3314 #define MR_NP_LOADED            0x00000010
3315 #define MR_TOGGLE_TX            0x00000020
3316 #define MR_LP_ADV_FULL_DUPLEX   0x00000040
3317 #define MR_LP_ADV_HALF_DUPLEX   0x00000080
3318 #define MR_LP_ADV_SYM_PAUSE     0x00000100
3319 #define MR_LP_ADV_ASYM_PAUSE    0x00000200
3320 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3321 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3322 #define MR_LP_ADV_NEXT_PAGE     0x00001000
3323 #define MR_TOGGLE_RX            0x00002000
3324 #define MR_NP_RX                0x00004000
3325
3326 #define MR_LINK_OK              0x80000000
3327
3328         unsigned long link_time, cur_time;
3329
3330         u32 ability_match_cfg;
3331         int ability_match_count;
3332
3333         char ability_match, idle_match, ack_match;
3334
3335         u32 txconfig, rxconfig;
3336 #define ANEG_CFG_NP             0x00000080
3337 #define ANEG_CFG_ACK            0x00000040
3338 #define ANEG_CFG_RF2            0x00000020
3339 #define ANEG_CFG_RF1            0x00000010
3340 #define ANEG_CFG_PS2            0x00000001
3341 #define ANEG_CFG_PS1            0x00008000
3342 #define ANEG_CFG_HD             0x00004000
3343 #define ANEG_CFG_FD             0x00002000
3344 #define ANEG_CFG_INVAL          0x00001f06
3345
3346 };
3347 #define ANEG_OK         0
3348 #define ANEG_DONE       1
3349 #define ANEG_TIMER_ENAB 2
3350 #define ANEG_FAILED     -1
3351
3352 #define ANEG_STATE_SETTLE_TIME  10000
3353
3354 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3355                                    struct tg3_fiber_aneginfo *ap)
3356 {
3357         u16 flowctrl;
3358         unsigned long delta;
3359         u32 rx_cfg_reg;
3360         int ret;
3361
3362         if (ap->state == ANEG_STATE_UNKNOWN) {
3363                 ap->rxconfig = 0;
3364                 ap->link_time = 0;
3365                 ap->cur_time = 0;
3366                 ap->ability_match_cfg = 0;
3367                 ap->ability_match_count = 0;
3368                 ap->ability_match = 0;
3369                 ap->idle_match = 0;
3370                 ap->ack_match = 0;
3371         }
3372         ap->cur_time++;
3373
3374         if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3375                 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3376
3377                 if (rx_cfg_reg != ap->ability_match_cfg) {
3378                         ap->ability_match_cfg = rx_cfg_reg;
3379                         ap->ability_match = 0;
3380                         ap->ability_match_count = 0;
3381                 } else {
3382                         if (++ap->ability_match_count > 1) {
3383                                 ap->ability_match = 1;
3384                                 ap->ability_match_cfg = rx_cfg_reg;
3385                         }
3386                 }
3387                 if (rx_cfg_reg & ANEG_CFG_ACK)
3388                         ap->ack_match = 1;
3389                 else
3390                         ap->ack_match = 0;
3391
3392                 ap->idle_match = 0;
3393         } else {
3394                 ap->idle_match = 1;
3395                 ap->ability_match_cfg = 0;
3396                 ap->ability_match_count = 0;
3397                 ap->ability_match = 0;
3398                 ap->ack_match = 0;
3399
3400                 rx_cfg_reg = 0;
3401         }
3402
3403         ap->rxconfig = rx_cfg_reg;
3404         ret = ANEG_OK;
3405
3406         switch(ap->state) {
3407         case ANEG_STATE_UNKNOWN:
3408                 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3409                         ap->state = ANEG_STATE_AN_ENABLE;
3410
3411                 /* fallthru */
3412         case ANEG_STATE_AN_ENABLE:
3413                 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3414                 if (ap->flags & MR_AN_ENABLE) {
3415                         ap->link_time = 0;
3416                         ap->cur_time = 0;
3417                         ap->ability_match_cfg = 0;
3418                         ap->ability_match_count = 0;
3419                         ap->ability_match = 0;
3420                         ap->idle_match = 0;
3421                         ap->ack_match = 0;
3422
3423                         ap->state = ANEG_STATE_RESTART_INIT;
3424                 } else {
3425                         ap->state = ANEG_STATE_DISABLE_LINK_OK;
3426                 }
3427                 break;
3428
3429         case ANEG_STATE_RESTART_INIT:
3430                 ap->link_time = ap->cur_time;
3431                 ap->flags &= ~(MR_NP_LOADED);
3432                 ap->txconfig = 0;
3433                 tw32(MAC_TX_AUTO_NEG, 0);
3434                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3435                 tw32_f(MAC_MODE, tp->mac_mode);
3436                 udelay(40);
3437
3438                 ret = ANEG_TIMER_ENAB;
3439                 ap->state = ANEG_STATE_RESTART;
3440
3441                 /* fallthru */
3442         case ANEG_STATE_RESTART:
3443                 delta = ap->cur_time - ap->link_time;
3444                 if (delta > ANEG_STATE_SETTLE_TIME) {
3445                         ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3446                 } else {
3447                         ret = ANEG_TIMER_ENAB;
3448                 }
3449                 break;
3450
3451         case ANEG_STATE_DISABLE_LINK_OK:
3452                 ret = ANEG_DONE;
3453                 break;
3454
3455         case ANEG_STATE_ABILITY_DETECT_INIT:
3456                 ap->flags &= ~(MR_TOGGLE_TX);
3457                 ap->txconfig = ANEG_CFG_FD;
3458                 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3459                 if (flowctrl & ADVERTISE_1000XPAUSE)
3460                         ap->txconfig |= ANEG_CFG_PS1;
3461                 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3462                         ap->txconfig |= ANEG_CFG_PS2;
3463                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3464                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3465                 tw32_f(MAC_MODE, tp->mac_mode);
3466                 udelay(40);
3467
3468                 ap->state = ANEG_STATE_ABILITY_DETECT;
3469                 break;
3470
3471         case ANEG_STATE_ABILITY_DETECT:
3472                 if (ap->ability_match != 0 && ap->rxconfig != 0) {
3473                         ap->state = ANEG_STATE_ACK_DETECT_INIT;
3474                 }
3475                 break;
3476
3477         case ANEG_STATE_ACK_DETECT_INIT:
3478                 ap->txconfig |= ANEG_CFG_ACK;
3479                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3480                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3481                 tw32_f(MAC_MODE, tp->mac_mode);
3482                 udelay(40);
3483
3484                 ap->state = ANEG_STATE_ACK_DETECT;
3485
3486                 /* fallthru */
3487         case ANEG_STATE_ACK_DETECT:
3488                 if (ap->ack_match != 0) {
3489                         if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3490                             (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3491                                 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3492                         } else {
3493                                 ap->state = ANEG_STATE_AN_ENABLE;
3494                         }
3495                 } else if (ap->ability_match != 0 &&
3496                            ap->rxconfig == 0) {
3497                         ap->state = ANEG_STATE_AN_ENABLE;
3498                 }
3499                 break;
3500
3501         case ANEG_STATE_COMPLETE_ACK_INIT:
3502                 if (ap->rxconfig & ANEG_CFG_INVAL) {
3503                         ret = ANEG_FAILED;
3504                         break;
3505                 }
3506                 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3507                                MR_LP_ADV_HALF_DUPLEX |
3508                                MR_LP_ADV_SYM_PAUSE |
3509                                MR_LP_ADV_ASYM_PAUSE |
3510                                MR_LP_ADV_REMOTE_FAULT1 |
3511                                MR_LP_ADV_REMOTE_FAULT2 |
3512                                MR_LP_ADV_NEXT_PAGE |
3513                                MR_TOGGLE_RX |
3514                                MR_NP_RX);
3515                 if (ap->rxconfig & ANEG_CFG_FD)
3516                         ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3517                 if (ap->rxconfig & ANEG_CFG_HD)
3518                         ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3519                 if (ap->rxconfig & ANEG_CFG_PS1)
3520                         ap->flags |= MR_LP_ADV_SYM_PAUSE;
3521                 if (ap->rxconfig & ANEG_CFG_PS2)
3522                         ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3523                 if (ap->rxconfig & ANEG_CFG_RF1)
3524                         ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3525                 if (ap->rxconfig & ANEG_CFG_RF2)
3526                         ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3527                 if (ap->rxconfig & ANEG_CFG_NP)
3528                         ap->flags |= MR_LP_ADV_NEXT_PAGE;
3529
3530                 ap->link_time = ap->cur_time;
3531
3532                 ap->flags ^= (MR_TOGGLE_TX);
3533                 if (ap->rxconfig & 0x0008)
3534                         ap->flags |= MR_TOGGLE_RX;
3535                 if (ap->rxconfig & ANEG_CFG_NP)
3536                         ap->flags |= MR_NP_RX;
3537                 ap->flags |= MR_PAGE_RX;
3538
3539                 ap->state = ANEG_STATE_COMPLETE_ACK;
3540                 ret = ANEG_TIMER_ENAB;
3541                 break;
3542
3543         case ANEG_STATE_COMPLETE_ACK:
3544                 if (ap->ability_match != 0 &&
3545                     ap->rxconfig == 0) {
3546                         ap->state = ANEG_STATE_AN_ENABLE;
3547                         break;
3548                 }
3549                 delta = ap->cur_time - ap->link_time;
3550                 if (delta > ANEG_STATE_SETTLE_TIME) {
3551                         if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3552                                 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3553                         } else {
3554                                 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3555                                     !(ap->flags & MR_NP_RX)) {
3556                                         ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3557                                 } else {
3558                                         ret = ANEG_FAILED;
3559                                 }
3560                         }
3561                 }
3562                 break;
3563
3564         case ANEG_STATE_IDLE_DETECT_INIT:
3565                 ap->link_time = ap->cur_time;
3566                 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3567                 tw32_f(MAC_MODE, tp->mac_mode);
3568                 udelay(40);
3569
3570                 ap->state = ANEG_STATE_IDLE_DETECT;
3571                 ret = ANEG_TIMER_ENAB;
3572                 break;
3573
3574         case ANEG_STATE_IDLE_DETECT:
3575                 if (ap->ability_match != 0 &&
3576                     ap->rxconfig == 0) {
3577                         ap->state = ANEG_STATE_AN_ENABLE;
3578                         break;
3579                 }
3580                 delta = ap->cur_time - ap->link_time;
3581                 if (delta > ANEG_STATE_SETTLE_TIME) {
3582                         /* XXX another gem from the Broadcom driver :( */
3583                         ap->state = ANEG_STATE_LINK_OK;
3584                 }
3585                 break;
3586
3587         case ANEG_STATE_LINK_OK:
3588                 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3589                 ret = ANEG_DONE;
3590                 break;
3591
3592         case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3593                 /* ??? unimplemented */
3594                 break;
3595
3596         case ANEG_STATE_NEXT_PAGE_WAIT:
3597                 /* ??? unimplemented */
3598                 break;
3599
3600         default:
3601                 ret = ANEG_FAILED;
3602                 break;
3603         }
3604
3605         return ret;
3606 }
3607
3608 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
3609 {
3610         int res = 0;
3611         struct tg3_fiber_aneginfo aninfo;
3612         int status = ANEG_FAILED;
3613         unsigned int tick;
3614         u32 tmp;
3615
3616         tw32_f(MAC_TX_AUTO_NEG, 0);
3617
3618         tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3619         tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3620         udelay(40);
3621
3622         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3623         udelay(40);
3624
3625         memset(&aninfo, 0, sizeof(aninfo));
3626         aninfo.flags |= MR_AN_ENABLE;
3627         aninfo.state = ANEG_STATE_UNKNOWN;
3628         aninfo.cur_time = 0;
3629         tick = 0;
3630         while (++tick < 195000) {
3631                 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3632                 if (status == ANEG_DONE || status == ANEG_FAILED)
3633                         break;
3634
3635                 udelay(1);
3636         }
3637
3638         tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3639         tw32_f(MAC_MODE, tp->mac_mode);
3640         udelay(40);
3641
3642         *txflags = aninfo.txconfig;
3643         *rxflags = aninfo.flags;
3644
3645         if (status == ANEG_DONE &&
3646             (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3647                              MR_LP_ADV_FULL_DUPLEX)))
3648                 res = 1;
3649
3650         return res;
3651 }
3652
3653 static void tg3_init_bcm8002(struct tg3 *tp)
3654 {
3655         u32 mac_status = tr32(MAC_STATUS);
3656         int i;
3657
3658         /* Reset when initting first time or we have a link. */
3659         if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3660             !(mac_status & MAC_STATUS_PCS_SYNCED))
3661                 return;
3662
3663         /* Set PLL lock range. */
3664         tg3_writephy(tp, 0x16, 0x8007);
3665
3666         /* SW reset */
3667         tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3668
3669         /* Wait for reset to complete. */
3670         /* XXX schedule_timeout() ... */
3671         for (i = 0; i < 500; i++)
3672                 udelay(10);
3673
3674         /* Config mode; select PMA/Ch 1 regs. */
3675         tg3_writephy(tp, 0x10, 0x8411);
3676
3677         /* Enable auto-lock and comdet, select txclk for tx. */
3678         tg3_writephy(tp, 0x11, 0x0a10);
3679
3680         tg3_writephy(tp, 0x18, 0x00a0);
3681         tg3_writephy(tp, 0x16, 0x41ff);
3682
3683         /* Assert and deassert POR. */
3684         tg3_writephy(tp, 0x13, 0x0400);
3685         udelay(40);
3686         tg3_writephy(tp, 0x13, 0x0000);
3687
3688         tg3_writephy(tp, 0x11, 0x0a50);
3689         udelay(40);
3690         tg3_writephy(tp, 0x11, 0x0a10);
3691
3692         /* Wait for signal to stabilize */
3693         /* XXX schedule_timeout() ... */
3694         for (i = 0; i < 15000; i++)
3695                 udelay(10);
3696
3697         /* Deselect the channel register so we can read the PHYID
3698          * later.
3699          */
3700         tg3_writephy(tp, 0x10, 0x8011);
3701 }
3702
3703 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3704 {
3705         u16 flowctrl;
3706         u32 sg_dig_ctrl, sg_dig_status;
3707         u32 serdes_cfg, expected_sg_dig_ctrl;
3708         int workaround, port_a;
3709         int current_link_up;
3710
3711         serdes_cfg = 0;
3712         expected_sg_dig_ctrl = 0;
3713         workaround = 0;
3714         port_a = 1;
3715         current_link_up = 0;
3716
3717         if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3718             tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3719                 workaround = 1;
3720                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3721                         port_a = 0;
3722
3723                 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3724                 /* preserve bits 20-23 for voltage regulator */
3725                 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3726         }
3727
3728         sg_dig_ctrl = tr32(SG_DIG_CTRL);
3729
3730         if (tp->link_config.autoneg != AUTONEG_ENABLE) {
3731                 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
3732                         if (workaround) {
3733                                 u32 val = serdes_cfg;
3734
3735                                 if (port_a)
3736                                         val |= 0xc010000;
3737                                 else
3738                                         val |= 0x4010000;
3739                                 tw32_f(MAC_SERDES_CFG, val);
3740                         }
3741
3742                         tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3743                 }
3744                 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3745                         tg3_setup_flow_control(tp, 0, 0);
3746                         current_link_up = 1;
3747                 }
3748                 goto out;
3749         }
3750
3751         /* Want auto-negotiation.  */
3752         expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
3753
3754         flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3755         if (flowctrl & ADVERTISE_1000XPAUSE)
3756                 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3757         if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3758                 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
3759
3760         if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3761                 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
3762                     tp->serdes_counter &&
3763                     ((mac_status & (MAC_STATUS_PCS_SYNCED |
3764                                     MAC_STATUS_RCVD_CFG)) ==
3765                      MAC_STATUS_PCS_SYNCED)) {
3766                         tp->serdes_counter--;
3767                         current_link_up = 1;
3768                         goto out;
3769                 }
3770 restart_autoneg:
3771                 if (workaround)
3772                         tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
3773                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
3774                 udelay(5);
3775                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3776
3777                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3778                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3779         } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3780                                  MAC_STATUS_SIGNAL_DET)) {
3781                 sg_dig_status = tr32(SG_DIG_STATUS);
3782                 mac_status = tr32(MAC_STATUS);
3783
3784                 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
3785                     (mac_status & MAC_STATUS_PCS_SYNCED)) {
3786                         u32 local_adv = 0, remote_adv = 0;
3787
3788                         if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3789                                 local_adv |= ADVERTISE_1000XPAUSE;
3790                         if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3791                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3792
3793                         if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
3794                                 remote_adv |= LPA_1000XPAUSE;
3795                         if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
3796                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3797
3798                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3799                         current_link_up = 1;
3800                         tp->serdes_counter = 0;
3801                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3802                 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3803                         if (tp->serdes_counter)
3804                                 tp->serdes_counter--;
3805                         else {
3806                                 if (workaround) {
3807                                         u32 val = serdes_cfg;
3808
3809                                         if (port_a)
3810                                                 val |= 0xc010000;
3811                                         else
3812                                                 val |= 0x4010000;
3813
3814                                         tw32_f(MAC_SERDES_CFG, val);
3815                                 }
3816
3817                                 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3818                                 udelay(40);
3819
3820                                 /* Link parallel detection - link is up */
3821                                 /* only if we have PCS_SYNC and not */
3822                                 /* receiving config code words */
3823                                 mac_status = tr32(MAC_STATUS);
3824                                 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3825                                     !(mac_status & MAC_STATUS_RCVD_CFG)) {
3826                                         tg3_setup_flow_control(tp, 0, 0);
3827                                         current_link_up = 1;
3828                                         tp->tg3_flags2 |=
3829                                                 TG3_FLG2_PARALLEL_DETECT;
3830                                         tp->serdes_counter =
3831                                                 SERDES_PARALLEL_DET_TIMEOUT;
3832                                 } else
3833                                         goto restart_autoneg;
3834                         }
3835                 }
3836         } else {
3837                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3838                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3839         }
3840
3841 out:
3842         return current_link_up;
3843 }
3844
3845 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3846 {
3847         int current_link_up = 0;
3848
3849         if (!(mac_status & MAC_STATUS_PCS_SYNCED))
3850                 goto out;
3851
3852         if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3853                 u32 txflags, rxflags;
3854                 int i;
3855
3856                 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3857                         u32 local_adv = 0, remote_adv = 0;
3858
3859                         if (txflags & ANEG_CFG_PS1)
3860                                 local_adv |= ADVERTISE_1000XPAUSE;
3861                         if (txflags & ANEG_CFG_PS2)
3862                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3863
3864                         if (rxflags & MR_LP_ADV_SYM_PAUSE)
3865                                 remote_adv |= LPA_1000XPAUSE;
3866                         if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3867                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3868
3869                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3870
3871                         current_link_up = 1;
3872                 }
3873                 for (i = 0; i < 30; i++) {
3874                         udelay(20);
3875                         tw32_f(MAC_STATUS,
3876                                (MAC_STATUS_SYNC_CHANGED |
3877                                 MAC_STATUS_CFG_CHANGED));
3878                         udelay(40);
3879                         if ((tr32(MAC_STATUS) &
3880                              (MAC_STATUS_SYNC_CHANGED |
3881                               MAC_STATUS_CFG_CHANGED)) == 0)
3882                                 break;
3883                 }
3884
3885                 mac_status = tr32(MAC_STATUS);
3886                 if (current_link_up == 0 &&
3887                     (mac_status & MAC_STATUS_PCS_SYNCED) &&
3888                     !(mac_status & MAC_STATUS_RCVD_CFG))
3889                         current_link_up = 1;
3890         } else {
3891                 tg3_setup_flow_control(tp, 0, 0);
3892
3893                 /* Forcing 1000FD link up. */
3894                 current_link_up = 1;
3895
3896                 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3897                 udelay(40);
3898
3899                 tw32_f(MAC_MODE, tp->mac_mode);
3900                 udelay(40);
3901         }
3902
3903 out:
3904         return current_link_up;
3905 }
3906
3907 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3908 {
3909         u32 orig_pause_cfg;
3910         u16 orig_active_speed;
3911         u8 orig_active_duplex;
3912         u32 mac_status;
3913         int current_link_up;
3914         int i;
3915
3916         orig_pause_cfg = tp->link_config.active_flowctrl;
3917         orig_active_speed = tp->link_config.active_speed;
3918         orig_active_duplex = tp->link_config.active_duplex;
3919
3920         if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3921             netif_carrier_ok(tp->dev) &&
3922             (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3923                 mac_status = tr32(MAC_STATUS);
3924                 mac_status &= (MAC_STATUS_PCS_SYNCED |
3925                                MAC_STATUS_SIGNAL_DET |
3926                                MAC_STATUS_CFG_CHANGED |
3927                                MAC_STATUS_RCVD_CFG);
3928                 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3929                                    MAC_STATUS_SIGNAL_DET)) {
3930                         tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3931                                             MAC_STATUS_CFG_CHANGED));
3932                         return 0;
3933                 }
3934         }
3935
3936         tw32_f(MAC_TX_AUTO_NEG, 0);
3937
3938         tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
3939         tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
3940         tw32_f(MAC_MODE, tp->mac_mode);
3941         udelay(40);
3942
3943         if (tp->phy_id == PHY_ID_BCM8002)
3944                 tg3_init_bcm8002(tp);
3945
3946         /* Enable link change event even when serdes polling.  */
3947         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3948         udelay(40);
3949
3950         current_link_up = 0;
3951         mac_status = tr32(MAC_STATUS);
3952
3953         if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
3954                 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
3955         else
3956                 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
3957
3958         tp->napi[0].hw_status->status =
3959                 (SD_STATUS_UPDATED |
3960                  (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
3961
3962         for (i = 0; i < 100; i++) {
3963                 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3964                                     MAC_STATUS_CFG_CHANGED));
3965                 udelay(5);
3966                 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3967                                          MAC_STATUS_CFG_CHANGED |
3968                                          MAC_STATUS_LNKSTATE_CHANGED)) == 0)
3969                         break;
3970         }
3971
3972         mac_status = tr32(MAC_STATUS);
3973         if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
3974                 current_link_up = 0;
3975                 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
3976                     tp->serdes_counter == 0) {
3977                         tw32_f(MAC_MODE, (tp->mac_mode |
3978                                           MAC_MODE_SEND_CONFIGS));
3979                         udelay(1);
3980                         tw32_f(MAC_MODE, tp->mac_mode);
3981                 }
3982         }
3983
3984         if (current_link_up == 1) {
3985                 tp->link_config.active_speed = SPEED_1000;
3986                 tp->link_config.active_duplex = DUPLEX_FULL;
3987                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3988                                     LED_CTRL_LNKLED_OVERRIDE |
3989                                     LED_CTRL_1000MBPS_ON));
3990         } else {
3991                 tp->link_config.active_speed = SPEED_INVALID;
3992                 tp->link_config.active_duplex = DUPLEX_INVALID;
3993                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3994                                     LED_CTRL_LNKLED_OVERRIDE |
3995                                     LED_CTRL_TRAFFIC_OVERRIDE));
3996         }
3997
3998         if (current_link_up != netif_carrier_ok(tp->dev)) {
3999                 if (current_link_up)
4000                         netif_carrier_on(tp->dev);
4001                 else
4002                         netif_carrier_off(tp->dev);
4003                 tg3_link_report(tp);
4004         } else {
4005                 u32 now_pause_cfg = tp->link_config.active_flowctrl;
4006                 if (orig_pause_cfg != now_pause_cfg ||
4007                     orig_active_speed != tp->link_config.active_speed ||
4008                     orig_active_duplex != tp->link_config.active_duplex)
4009                         tg3_link_report(tp);
4010         }
4011
4012         return 0;
4013 }
4014
4015 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
4016 {
4017         int current_link_up, err = 0;
4018         u32 bmsr, bmcr;
4019         u16 current_speed;
4020         u8 current_duplex;
4021         u32 local_adv, remote_adv;
4022
4023         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4024         tw32_f(MAC_MODE, tp->mac_mode);
4025         udelay(40);
4026
4027         tw32(MAC_EVENT, 0);
4028
4029         tw32_f(MAC_STATUS,
4030              (MAC_STATUS_SYNC_CHANGED |
4031               MAC_STATUS_CFG_CHANGED |
4032               MAC_STATUS_MI_COMPLETION |
4033               MAC_STATUS_LNKSTATE_CHANGED));
4034         udelay(40);
4035
4036         if (force_reset)
4037                 tg3_phy_reset(tp);
4038
4039         current_link_up = 0;
4040         current_speed = SPEED_INVALID;
4041         current_duplex = DUPLEX_INVALID;
4042
4043         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4044         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4045         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
4046                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4047                         bmsr |= BMSR_LSTATUS;
4048                 else
4049                         bmsr &= ~BMSR_LSTATUS;
4050         }
4051
4052         err |= tg3_readphy(tp, MII_BMCR, &bmcr);
4053
4054         if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
4055             (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4056                 /* do nothing, just check for link up at the end */
4057         } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4058                 u32 adv, new_adv;
4059
4060                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4061                 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4062                                   ADVERTISE_1000XPAUSE |
4063                                   ADVERTISE_1000XPSE_ASYM |
4064                                   ADVERTISE_SLCT);
4065
4066                 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4067
4068                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4069                         new_adv |= ADVERTISE_1000XHALF;
4070                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4071                         new_adv |= ADVERTISE_1000XFULL;
4072
4073                 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4074                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
4075                         bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4076                         tg3_writephy(tp, MII_BMCR, bmcr);
4077
4078                         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4079                         tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
4080                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4081
4082                         return err;
4083                 }
4084         } else {
4085                 u32 new_bmcr;
4086
4087                 bmcr &= ~BMCR_SPEED1000;
4088                 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4089
4090                 if (tp->link_config.duplex == DUPLEX_FULL)
4091                         new_bmcr |= BMCR_FULLDPLX;
4092
4093                 if (new_bmcr != bmcr) {
4094                         /* BMCR_SPEED1000 is a reserved bit that needs
4095                          * to be set on write.
4096                          */
4097                         new_bmcr |= BMCR_SPEED1000;
4098
4099                         /* Force a linkdown */
4100                         if (netif_carrier_ok(tp->dev)) {
4101                                 u32 adv;
4102
4103                                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4104                                 adv &= ~(ADVERTISE_1000XFULL |
4105                                          ADVERTISE_1000XHALF |
4106                                          ADVERTISE_SLCT);
4107                                 tg3_writephy(tp, MII_ADVERTISE, adv);
4108                                 tg3_writephy(tp, MII_BMCR, bmcr |
4109                                                            BMCR_ANRESTART |
4110                                                            BMCR_ANENABLE);
4111                                 udelay(10);
4112                                 netif_carrier_off(tp->dev);
4113                         }
4114                         tg3_writephy(tp, MII_BMCR, new_bmcr);
4115                         bmcr = new_bmcr;
4116                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4117                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4118                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4119                             ASIC_REV_5714) {
4120                                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4121                                         bmsr |= BMSR_LSTATUS;
4122                                 else
4123                                         bmsr &= ~BMSR_LSTATUS;
4124                         }
4125                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4126                 }
4127         }
4128
4129         if (bmsr & BMSR_LSTATUS) {
4130                 current_speed = SPEED_1000;
4131                 current_link_up = 1;
4132                 if (bmcr & BMCR_FULLDPLX)
4133                         current_duplex = DUPLEX_FULL;
4134                 else
4135                         current_duplex = DUPLEX_HALF;
4136
4137                 local_adv = 0;
4138                 remote_adv = 0;
4139
4140                 if (bmcr & BMCR_ANENABLE) {
4141                         u32 common;
4142
4143                         err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4144                         err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4145                         common = local_adv & remote_adv;
4146                         if (common & (ADVERTISE_1000XHALF |
4147                                       ADVERTISE_1000XFULL)) {
4148                                 if (common & ADVERTISE_1000XFULL)
4149                                         current_duplex = DUPLEX_FULL;
4150                                 else
4151                                         current_duplex = DUPLEX_HALF;
4152                         }
4153                         else
4154                                 current_link_up = 0;
4155                 }
4156         }
4157
4158         if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4159                 tg3_setup_flow_control(tp, local_adv, remote_adv);
4160
4161         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4162         if (tp->link_config.active_duplex == DUPLEX_HALF)
4163                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4164
4165         tw32_f(MAC_MODE, tp->mac_mode);
4166         udelay(40);
4167
4168         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4169
4170         tp->link_config.active_speed = current_speed;
4171         tp->link_config.active_duplex = current_duplex;
4172
4173         if (current_link_up != netif_carrier_ok(tp->dev)) {
4174                 if (current_link_up)
4175                         netif_carrier_on(tp->dev);
4176                 else {
4177                         netif_carrier_off(tp->dev);
4178                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4179                 }
4180                 tg3_link_report(tp);
4181         }
4182         return err;
4183 }
4184
4185 static void tg3_serdes_parallel_detect(struct tg3 *tp)
4186 {
4187         if (tp->serdes_counter) {
4188                 /* Give autoneg time to complete. */
4189                 tp->serdes_counter--;
4190                 return;
4191         }
4192         if (!netif_carrier_ok(tp->dev) &&
4193             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4194                 u32 bmcr;
4195
4196                 tg3_readphy(tp, MII_BMCR, &bmcr);
4197                 if (bmcr & BMCR_ANENABLE) {
4198                         u32 phy1, phy2;
4199
4200                         /* Select shadow register 0x1f */
4201                         tg3_writephy(tp, 0x1c, 0x7c00);
4202                         tg3_readphy(tp, 0x1c, &phy1);
4203
4204                         /* Select expansion interrupt status register */
4205                         tg3_writephy(tp, 0x17, 0x0f01);
4206                         tg3_readphy(tp, 0x15, &phy2);
4207                         tg3_readphy(tp, 0x15, &phy2);
4208
4209                         if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4210                                 /* We have signal detect and not receiving
4211                                  * config code words, link is up by parallel
4212                                  * detection.
4213                                  */
4214
4215                                 bmcr &= ~BMCR_ANENABLE;
4216                                 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4217                                 tg3_writephy(tp, MII_BMCR, bmcr);
4218                                 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
4219                         }
4220                 }
4221         }
4222         else if (netif_carrier_ok(tp->dev) &&
4223                  (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4224                  (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4225                 u32 phy2;
4226
4227                 /* Select expansion interrupt status register */
4228                 tg3_writephy(tp, 0x17, 0x0f01);
4229                 tg3_readphy(tp, 0x15, &phy2);
4230                 if (phy2 & 0x20) {
4231                         u32 bmcr;
4232
4233                         /* Config code words received, turn on autoneg. */
4234                         tg3_readphy(tp, MII_BMCR, &bmcr);
4235                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4236
4237                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4238
4239                 }
4240         }
4241 }
4242
4243 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4244 {
4245         int err;
4246
4247         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
4248                 err = tg3_setup_fiber_phy(tp, force_reset);
4249         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
4250                 err = tg3_setup_fiber_mii_phy(tp, force_reset);
4251         } else {
4252                 err = tg3_setup_copper_phy(tp, force_reset);
4253         }
4254
4255         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
4256                 u32 val, scale;
4257
4258                 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4259                 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4260                         scale = 65;
4261                 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4262                         scale = 6;
4263                 else
4264                         scale = 12;
4265
4266                 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4267                 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4268                 tw32(GRC_MISC_CFG, val);
4269         }
4270
4271         if (tp->link_config.active_speed == SPEED_1000 &&
4272             tp->link_config.active_duplex == DUPLEX_HALF)
4273                 tw32(MAC_TX_LENGTHS,
4274                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4275                       (6 << TX_LENGTHS_IPG_SHIFT) |
4276                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
4277         else
4278                 tw32(MAC_TX_LENGTHS,
4279                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4280                       (6 << TX_LENGTHS_IPG_SHIFT) |
4281                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
4282
4283         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4284                 if (netif_carrier_ok(tp->dev)) {
4285                         tw32(HOSTCC_STAT_COAL_TICKS,
4286                              tp->coal.stats_block_coalesce_usecs);
4287                 } else {
4288                         tw32(HOSTCC_STAT_COAL_TICKS, 0);
4289                 }
4290         }
4291
4292         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4293                 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
4294                 if (!netif_carrier_ok(tp->dev))
4295                         val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4296                               tp->pwrmgmt_thresh;
4297                 else
4298                         val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4299                 tw32(PCIE_PWR_MGMT_THRESH, val);
4300         }
4301
4302         return err;
4303 }
4304
4305 /* This is called whenever we suspect that the system chipset is re-
4306  * ordering the sequence of MMIO to the tx send mailbox. The symptom
4307  * is bogus tx completions. We try to recover by setting the
4308  * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4309  * in the workqueue.
4310  */
4311 static void tg3_tx_recover(struct tg3 *tp)
4312 {
4313         BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4314                tp->write32_tx_mbox == tg3_write_indirect_mbox);
4315
4316         printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
4317                "mapped I/O cycles to the network device, attempting to "
4318                "recover. Please report the problem to the driver maintainer "
4319                "and include system chipset information.\n", tp->dev->name);
4320
4321         spin_lock(&tp->lock);
4322         tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
4323         spin_unlock(&tp->lock);
4324 }
4325
4326 static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
4327 {
4328         smp_mb();
4329         return tnapi->tx_pending -
4330                ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
4331 }
4332
4333 /* Tigon3 never reports partial packet sends.  So we do not
4334  * need special logic to handle SKBs that have not had all
4335  * of their frags sent yet, like SunGEM does.
4336  */
4337 static void tg3_tx(struct tg3_napi *tnapi)
4338 {
4339         struct tg3 *tp = tnapi->tp;
4340         u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
4341         u32 sw_idx = tnapi->tx_cons;
4342         struct netdev_queue *txq;
4343         int index = tnapi - tp->napi;
4344
4345         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
4346                 index--;
4347
4348         txq = netdev_get_tx_queue(tp->dev, index);
4349
4350         while (sw_idx != hw_idx) {
4351                 struct tx_ring_info *ri = &tnapi->tx_buffers[sw_idx];
4352                 struct sk_buff *skb = ri->skb;
4353                 int i, tx_bug = 0;
4354
4355                 if (unlikely(skb == NULL)) {
4356                         tg3_tx_recover(tp);
4357                         return;
4358                 }
4359
4360                 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
4361
4362                 ri->skb = NULL;
4363
4364                 sw_idx = NEXT_TX(sw_idx);
4365
4366                 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
4367                         ri = &tnapi->tx_buffers[sw_idx];
4368                         if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4369                                 tx_bug = 1;
4370                         sw_idx = NEXT_TX(sw_idx);
4371                 }
4372
4373                 dev_kfree_skb(skb);
4374
4375                 if (unlikely(tx_bug)) {
4376                         tg3_tx_recover(tp);
4377                         return;
4378                 }
4379         }
4380
4381         tnapi->tx_cons = sw_idx;
4382
4383         /* Need to make the tx_cons update visible to tg3_start_xmit()
4384          * before checking for netif_queue_stopped().  Without the
4385          * memory barrier, there is a small possibility that tg3_start_xmit()
4386          * will miss it and cause the queue to be stopped forever.
4387          */
4388         smp_mb();
4389
4390         if (unlikely(netif_tx_queue_stopped(txq) &&
4391                      (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
4392                 __netif_tx_lock(txq, smp_processor_id());
4393                 if (netif_tx_queue_stopped(txq) &&
4394                     (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
4395                         netif_tx_wake_queue(txq);
4396                 __netif_tx_unlock(txq);
4397         }
4398 }
4399
4400 /* Returns size of skb allocated or < 0 on error.
4401  *
4402  * We only need to fill in the address because the other members
4403  * of the RX descriptor are invariant, see tg3_init_rings.
4404  *
4405  * Note the purposeful assymetry of cpu vs. chip accesses.  For
4406  * posting buffers we only dirty the first cache line of the RX
4407  * descriptor (containing the address).  Whereas for the RX status
4408  * buffers the cpu only reads the last cacheline of the RX descriptor
4409  * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4410  */
4411 static int tg3_alloc_rx_skb(struct tg3_napi *tnapi, u32 opaque_key,
4412                             int src_idx, u32 dest_idx_unmasked)
4413 {
4414         struct tg3 *tp = tnapi->tp;
4415         struct tg3_rx_buffer_desc *desc;
4416         struct ring_info *map, *src_map;
4417         struct sk_buff *skb;
4418         dma_addr_t mapping;
4419         int skb_size, dest_idx;
4420         struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
4421
4422         src_map = NULL;
4423         switch (opaque_key) {
4424         case RXD_OPAQUE_RING_STD:
4425                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4426                 desc = &tpr->rx_std[dest_idx];
4427                 map = &tpr->rx_std_buffers[dest_idx];
4428                 if (src_idx >= 0)
4429                         src_map = &tpr->rx_std_buffers[src_idx];
4430                 skb_size = tp->rx_pkt_map_sz;
4431                 break;
4432
4433         case RXD_OPAQUE_RING_JUMBO:
4434                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4435                 desc = &tpr->rx_jmb[dest_idx].std;
4436                 map = &tpr->rx_jmb_buffers[dest_idx];
4437                 if (src_idx >= 0)
4438                         src_map = &tpr->rx_jmb_buffers[src_idx];
4439                 skb_size = TG3_RX_JMB_MAP_SZ;
4440                 break;
4441
4442         default:
4443                 return -EINVAL;
4444         }
4445
4446         /* Do not overwrite any of the map or rp information
4447          * until we are sure we can commit to a new buffer.
4448          *
4449          * Callers depend upon this behavior and assume that
4450          * we leave everything unchanged if we fail.
4451          */
4452         skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset);
4453         if (skb == NULL)
4454                 return -ENOMEM;
4455
4456         skb_reserve(skb, tp->rx_offset);
4457
4458         mapping = pci_map_single(tp->pdev, skb->data, skb_size,
4459                                  PCI_DMA_FROMDEVICE);
4460         if (pci_dma_mapping_error(tp->pdev, mapping)) {
4461                 dev_kfree_skb(skb);
4462                 return -EIO;
4463         }
4464
4465         map->skb = skb;
4466         pci_unmap_addr_set(map, mapping, mapping);
4467
4468         if (src_map != NULL)
4469                 src_map->skb = NULL;
4470
4471         desc->addr_hi = ((u64)mapping >> 32);
4472         desc->addr_lo = ((u64)mapping & 0xffffffff);
4473
4474         return skb_size;
4475 }
4476
4477 /* We only need to move over in the address because the other
4478  * members of the RX descriptor are invariant.  See notes above
4479  * tg3_alloc_rx_skb for full details.
4480  */
4481 static void tg3_recycle_rx(struct tg3_napi *tnapi, u32 opaque_key,
4482                            int src_idx, u32 dest_idx_unmasked)
4483 {
4484         struct tg3 *tp = tnapi->tp;
4485         struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4486         struct ring_info *src_map, *dest_map;
4487         int dest_idx;
4488         struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
4489
4490         switch (opaque_key) {
4491         case RXD_OPAQUE_RING_STD:
4492                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4493                 dest_desc = &tpr->rx_std[dest_idx];
4494                 dest_map = &tpr->rx_std_buffers[dest_idx];
4495                 src_desc = &tpr->rx_std[src_idx];
4496                 src_map = &tpr->rx_std_buffers[src_idx];
4497                 break;
4498
4499         case RXD_OPAQUE_RING_JUMBO:
4500                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4501                 dest_desc = &tpr->rx_jmb[dest_idx].std;
4502                 dest_map = &tpr->rx_jmb_buffers[dest_idx];
4503                 src_desc = &tpr->rx_jmb[src_idx].std;
4504                 src_map = &tpr->rx_jmb_buffers[src_idx];
4505                 break;
4506
4507         default:
4508                 return;
4509         }
4510
4511         dest_map->skb = src_map->skb;
4512         pci_unmap_addr_set(dest_map, mapping,
4513                            pci_unmap_addr(src_map, mapping));
4514         dest_desc->addr_hi = src_desc->addr_hi;
4515         dest_desc->addr_lo = src_desc->addr_lo;
4516
4517         src_map->skb = NULL;
4518 }
4519
4520 /* The RX ring scheme is composed of multiple rings which post fresh
4521  * buffers to the chip, and one special ring the chip uses to report
4522  * status back to the host.
4523  *
4524  * The special ring reports the status of received packets to the
4525  * host.  The chip does not write into the original descriptor the
4526  * RX buffer was obtained from.  The chip simply takes the original
4527  * descriptor as provided by the host, updates the status and length
4528  * field, then writes this into the next status ring entry.
4529  *
4530  * Each ring the host uses to post buffers to the chip is described
4531  * by a TG3_BDINFO entry in the chips SRAM area.  When a packet arrives,
4532  * it is first placed into the on-chip ram.  When the packet's length
4533  * is known, it walks down the TG3_BDINFO entries to select the ring.
4534  * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4535  * which is within the range of the new packet's length is chosen.
4536  *
4537  * The "separate ring for rx status" scheme may sound queer, but it makes
4538  * sense from a cache coherency perspective.  If only the host writes
4539  * to the buffer post rings, and only the chip writes to the rx status
4540  * rings, then cache lines never move beyond shared-modified state.
4541  * If both the host and chip were to write into the same ring, cache line
4542  * eviction could occur since both entities want it in an exclusive state.
4543  */
4544 static int tg3_rx(struct tg3_napi *tnapi, int budget)
4545 {
4546         struct tg3 *tp = tnapi->tp;
4547         u32 work_mask, rx_std_posted = 0;
4548         u32 sw_idx = tnapi->rx_rcb_ptr;
4549         u16 hw_idx;
4550         int received;
4551         struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
4552
4553         hw_idx = *(tnapi->rx_rcb_prod_idx);
4554         /*
4555          * We need to order the read of hw_idx and the read of
4556          * the opaque cookie.
4557          */
4558         rmb();
4559         work_mask = 0;
4560         received = 0;
4561         while (sw_idx != hw_idx && budget > 0) {
4562                 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
4563                 unsigned int len;
4564                 struct sk_buff *skb;
4565                 dma_addr_t dma_addr;
4566                 u32 opaque_key, desc_idx, *post_ptr;
4567
4568                 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4569                 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4570                 if (opaque_key == RXD_OPAQUE_RING_STD) {
4571                         struct ring_info *ri = &tpr->rx_std_buffers[desc_idx];
4572                         dma_addr = pci_unmap_addr(ri, mapping);
4573                         skb = ri->skb;
4574                         post_ptr = &tpr->rx_std_ptr;
4575                         rx_std_posted++;
4576                 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
4577                         struct ring_info *ri = &tpr->rx_jmb_buffers[desc_idx];
4578                         dma_addr = pci_unmap_addr(ri, mapping);
4579                         skb = ri->skb;
4580                         post_ptr = &tpr->rx_jmb_ptr;
4581                 } else
4582                         goto next_pkt_nopost;
4583
4584                 work_mask |= opaque_key;
4585
4586                 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4587                     (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4588                 drop_it:
4589                         tg3_recycle_rx(tnapi, opaque_key,
4590                                        desc_idx, *post_ptr);
4591                 drop_it_no_recycle:
4592                         /* Other statistics kept track of by card. */
4593                         tp->net_stats.rx_dropped++;
4594                         goto next_pkt;
4595                 }
4596
4597                 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4598                       ETH_FCS_LEN;
4599
4600                 if (len > RX_COPY_THRESHOLD
4601                         && tp->rx_offset == NET_IP_ALIGN
4602                         /* rx_offset will likely not equal NET_IP_ALIGN
4603                          * if this is a 5701 card running in PCI-X mode
4604                          * [see tg3_get_invariants()]
4605                          */
4606                 ) {
4607                         int skb_size;
4608
4609                         skb_size = tg3_alloc_rx_skb(tnapi, opaque_key,
4610                                                     desc_idx, *post_ptr);
4611                         if (skb_size < 0)
4612                                 goto drop_it;
4613
4614                         pci_unmap_single(tp->pdev, dma_addr, skb_size,
4615                                          PCI_DMA_FROMDEVICE);
4616
4617                         skb_put(skb, len);
4618                 } else {
4619                         struct sk_buff *copy_skb;
4620
4621                         tg3_recycle_rx(tnapi, opaque_key,
4622                                        desc_idx, *post_ptr);
4623
4624                         copy_skb = netdev_alloc_skb(tp->dev,
4625                                                     len + TG3_RAW_IP_ALIGN);
4626                         if (copy_skb == NULL)
4627                                 goto drop_it_no_recycle;
4628
4629                         skb_reserve(copy_skb, TG3_RAW_IP_ALIGN);
4630                         skb_put(copy_skb, len);
4631                         pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4632                         skb_copy_from_linear_data(skb, copy_skb->data, len);
4633                         pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4634
4635                         /* We'll reuse the original ring buffer. */
4636                         skb = copy_skb;
4637                 }
4638
4639                 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4640                     (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4641                     (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4642                       >> RXD_TCPCSUM_SHIFT) == 0xffff))
4643                         skb->ip_summed = CHECKSUM_UNNECESSARY;
4644                 else
4645                         skb->ip_summed = CHECKSUM_NONE;
4646
4647                 skb->protocol = eth_type_trans(skb, tp->dev);
4648
4649                 if (len > (tp->dev->mtu + ETH_HLEN) &&
4650                     skb->protocol != htons(ETH_P_8021Q)) {
4651                         dev_kfree_skb(skb);
4652                         goto next_pkt;
4653                 }
4654
4655 #if TG3_VLAN_TAG_USED
4656                 if (tp->vlgrp != NULL &&
4657                     desc->type_flags & RXD_FLAG_VLAN) {
4658                         vlan_gro_receive(&tnapi->napi, tp->vlgrp,
4659                                          desc->err_vlan & RXD_VLAN_MASK, skb);
4660                 } else
4661 #endif
4662                         napi_gro_receive(&tnapi->napi, skb);
4663
4664                 received++;
4665                 budget--;
4666
4667 next_pkt:
4668                 (*post_ptr)++;
4669
4670                 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4671                         u32 idx = *post_ptr % TG3_RX_RING_SIZE;
4672
4673                         tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX +
4674                                      TG3_64BIT_REG_LOW, idx);
4675                         work_mask &= ~RXD_OPAQUE_RING_STD;
4676                         rx_std_posted = 0;
4677                 }
4678 next_pkt_nopost:
4679                 sw_idx++;
4680                 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
4681
4682                 /* Refresh hw_idx to see if there is new work */
4683                 if (sw_idx == hw_idx) {
4684                         hw_idx = *(tnapi->rx_rcb_prod_idx);
4685                         rmb();
4686                 }
4687         }
4688
4689         /* ACK the status ring. */
4690         tnapi->rx_rcb_ptr = sw_idx;
4691         tw32_rx_mbox(tnapi->consmbox, sw_idx);
4692
4693         /* Refill RX ring(s). */
4694         if (work_mask & RXD_OPAQUE_RING_STD) {
4695                 sw_idx = tpr->rx_std_ptr % TG3_RX_RING_SIZE;
4696                 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
4697                              sw_idx);
4698         }
4699         if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4700                 sw_idx = tpr->rx_jmb_ptr % TG3_RX_JUMBO_RING_SIZE;
4701                 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
4702                              sw_idx);
4703         }
4704         mmiowb();
4705
4706         return received;
4707 }
4708
4709 static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
4710 {
4711         struct tg3 *tp = tnapi->tp;
4712         struct tg3_hw_status *sblk = tnapi->hw_status;
4713
4714         /* handle link change and other phy events */
4715         if (!(tp->tg3_flags &
4716               (TG3_FLAG_USE_LINKCHG_REG |
4717                TG3_FLAG_POLL_SERDES))) {
4718                 if (sblk->status & SD_STATUS_LINK_CHG) {
4719                         sblk->status = SD_STATUS_UPDATED |
4720                                 (sblk->status & ~SD_STATUS_LINK_CHG);
4721                         spin_lock(&tp->lock);
4722                         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4723                                 tw32_f(MAC_STATUS,
4724                                      (MAC_STATUS_SYNC_CHANGED |
4725                                       MAC_STATUS_CFG_CHANGED |
4726                                       MAC_STATUS_MI_COMPLETION |
4727                                       MAC_STATUS_LNKSTATE_CHANGED));
4728                                 udelay(40);
4729                         } else
4730                                 tg3_setup_phy(tp, 0);
4731                         spin_unlock(&tp->lock);
4732                 }
4733         }
4734
4735         /* run TX completion thread */
4736         if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
4737                 tg3_tx(tnapi);
4738                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4739                         return work_done;
4740         }
4741
4742         /* run RX thread, within the bounds set by NAPI.
4743          * All RX "locking" is done by ensuring outside
4744          * code synchronizes with tg3->napi.poll()
4745          */
4746         if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
4747                 work_done += tg3_rx(tnapi, budget - work_done);
4748
4749         return work_done;
4750 }
4751
4752 static int tg3_poll(struct napi_struct *napi, int budget)
4753 {
4754         struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
4755         struct tg3 *tp = tnapi->tp;
4756         int work_done = 0;
4757         struct tg3_hw_status *sblk = tnapi->hw_status;
4758
4759         while (1) {
4760                 work_done = tg3_poll_work(tnapi, work_done, budget);
4761
4762                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4763                         goto tx_recovery;
4764
4765                 if (unlikely(work_done >= budget))
4766                         break;
4767
4768                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
4769                         /* tp->last_tag is used in tg3_int_reenable() below
4770                          * to tell the hw how much work has been processed,
4771                          * so we must read it before checking for more work.
4772                          */
4773                         tnapi->last_tag = sblk->status_tag;
4774                         tnapi->last_irq_tag = tnapi->last_tag;
4775                         rmb();
4776                 } else
4777                         sblk->status &= ~SD_STATUS_UPDATED;
4778
4779                 if (likely(!tg3_has_work(tnapi))) {
4780                         napi_complete(napi);
4781                         tg3_int_reenable(tnapi);
4782                         break;
4783                 }
4784         }
4785
4786         return work_done;
4787
4788 tx_recovery:
4789         /* work_done is guaranteed to be less than budget. */
4790         napi_complete(napi);
4791         schedule_work(&tp->reset_task);
4792         return work_done;
4793 }
4794
4795 static void tg3_irq_quiesce(struct tg3 *tp)
4796 {
4797         int i;
4798
4799         BUG_ON(tp->irq_sync);
4800
4801         tp->irq_sync = 1;
4802         smp_mb();
4803
4804         for (i = 0; i < tp->irq_cnt; i++)
4805                 synchronize_irq(tp->napi[i].irq_vec);
4806 }
4807
4808 static inline int tg3_irq_sync(struct tg3 *tp)
4809 {
4810         return tp->irq_sync;
4811 }
4812
4813 /* Fully shutdown all tg3 driver activity elsewhere in the system.
4814  * If irq_sync is non-zero, then the IRQ handler must be synchronized
4815  * with as well.  Most of the time, this is not necessary except when
4816  * shutting down the device.
4817  */
4818 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
4819 {
4820         spin_lock_bh(&tp->lock);
4821         if (irq_sync)
4822                 tg3_irq_quiesce(tp);
4823 }
4824
4825 static inline void tg3_full_unlock(struct tg3 *tp)
4826 {
4827         spin_unlock_bh(&tp->lock);
4828 }
4829
4830 /* One-shot MSI handler - Chip automatically disables interrupt
4831  * after sending MSI so driver doesn't have to do it.
4832  */
4833 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
4834 {
4835         struct tg3_napi *tnapi = dev_id;
4836         struct tg3 *tp = tnapi->tp;
4837
4838         prefetch(tnapi->hw_status);
4839         if (tnapi->rx_rcb)
4840                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
4841
4842         if (likely(!tg3_irq_sync(tp)))
4843                 napi_schedule(&tnapi->napi);
4844
4845         return IRQ_HANDLED;
4846 }
4847
4848 /* MSI ISR - No need to check for interrupt sharing and no need to
4849  * flush status block and interrupt mailbox. PCI ordering rules
4850  * guarantee that MSI will arrive after the status block.
4851  */
4852 static irqreturn_t tg3_msi(int irq, void *dev_id)
4853 {
4854         struct tg3_napi *tnapi = dev_id;
4855         struct tg3 *tp = tnapi->tp;
4856
4857         prefetch(tnapi->hw_status);
4858         if (tnapi->rx_rcb)
4859                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
4860         /*
4861          * Writing any value to intr-mbox-0 clears PCI INTA# and
4862          * chip-internal interrupt pending events.
4863          * Writing non-zero to intr-mbox-0 additional tells the
4864          * NIC to stop sending us irqs, engaging "in-intr-handler"
4865          * event coalescing.
4866          */
4867         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4868         if (likely(!tg3_irq_sync(tp)))
4869                 napi_schedule(&tnapi->napi);
4870
4871         return IRQ_RETVAL(1);
4872 }
4873
4874 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
4875 {
4876         struct tg3_napi *tnapi = dev_id;
4877         struct tg3 *tp = tnapi->tp;
4878         struct tg3_hw_status *sblk = tnapi->hw_status;
4879         unsigned int handled = 1;
4880
4881         /* In INTx mode, it is possible for the interrupt to arrive at
4882          * the CPU before the status block posted prior to the interrupt.
4883          * Reading the PCI State register will confirm whether the
4884          * interrupt is ours and will flush the status block.
4885          */
4886         if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
4887                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4888                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4889                         handled = 0;
4890                         goto out;
4891                 }
4892         }
4893
4894         /*
4895          * Writing any value to intr-mbox-0 clears PCI INTA# and
4896          * chip-internal interrupt pending events.
4897          * Writing non-zero to intr-mbox-0 additional tells the
4898          * NIC to stop sending us irqs, engaging "in-intr-handler"
4899          * event coalescing.
4900          *
4901          * Flush the mailbox to de-assert the IRQ immediately to prevent
4902          * spurious interrupts.  The flush impacts performance but
4903          * excessive spurious interrupts can be worse in some cases.
4904          */
4905         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4906         if (tg3_irq_sync(tp))
4907                 goto out;
4908         sblk->status &= ~SD_STATUS_UPDATED;
4909         if (likely(tg3_has_work(tnapi))) {
4910                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
4911                 napi_schedule(&tnapi->napi);
4912         } else {
4913                 /* No work, shared interrupt perhaps?  re-enable
4914                  * interrupts, and flush that PCI write
4915                  */
4916                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
4917                                0x00000000);
4918         }
4919 out:
4920         return IRQ_RETVAL(handled);
4921 }
4922
4923 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
4924 {
4925         struct tg3_napi *tnapi = dev_id;
4926         struct tg3 *tp = tnapi->tp;
4927         struct tg3_hw_status *sblk = tnapi->hw_status;
4928         unsigned int handled = 1;
4929
4930         /* In INTx mode, it is possible for the interrupt to arrive at
4931          * the CPU before the status block posted prior to the interrupt.
4932          * Reading the PCI State register will confirm whether the
4933          * interrupt is ours and will flush the status block.
4934          */
4935         if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
4936                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4937                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4938                         handled = 0;
4939                         goto out;
4940                 }
4941         }
4942
4943         /*
4944          * writing any value to intr-mbox-0 clears PCI INTA# and
4945          * chip-internal interrupt pending events.
4946          * writing non-zero to intr-mbox-0 additional tells the
4947          * NIC to stop sending us irqs, engaging "in-intr-handler"
4948          * event coalescing.
4949          *
4950          * Flush the mailbox to de-assert the IRQ immediately to prevent
4951          * spurious interrupts.  The flush impacts performance but
4952          * excessive spurious interrupts can be worse in some cases.
4953          */
4954         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4955
4956         /*
4957          * In a shared interrupt configuration, sometimes other devices'
4958          * interrupts will scream.  We record the current status tag here
4959          * so that the above check can report that the screaming interrupts
4960          * are unhandled.  Eventually they will be silenced.
4961          */
4962         tnapi->last_irq_tag = sblk->status_tag;
4963
4964         if (tg3_irq_sync(tp))
4965                 goto out;
4966
4967         prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
4968
4969         napi_schedule(&tnapi->napi);
4970
4971 out:
4972         return IRQ_RETVAL(handled);
4973 }
4974
4975 /* ISR for interrupt test */
4976 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
4977 {
4978         struct tg3_napi *tnapi = dev_id;
4979         struct tg3 *tp = tnapi->tp;
4980         struct tg3_hw_status *sblk = tnapi->hw_status;
4981
4982         if ((sblk->status & SD_STATUS_UPDATED) ||
4983             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4984                 tg3_disable_ints(tp);
4985                 return IRQ_RETVAL(1);
4986         }
4987         return IRQ_RETVAL(0);
4988 }
4989
4990 static int tg3_init_hw(struct tg3 *, int);
4991 static int tg3_halt(struct tg3 *, int, int);
4992
4993 /* Restart hardware after configuration changes, self-test, etc.
4994  * Invoked with tp->lock held.
4995  */
4996 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
4997         __releases(tp->lock)
4998         __acquires(tp->lock)
4999 {
5000         int err;
5001
5002         err = tg3_init_hw(tp, reset_phy);
5003         if (err) {
5004                 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
5005                        "aborting.\n", tp->dev->name);
5006                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5007                 tg3_full_unlock(tp);
5008                 del_timer_sync(&tp->timer);
5009                 tp->irq_sync = 0;
5010                 tg3_napi_enable(tp);
5011                 dev_close(tp->dev);
5012                 tg3_full_lock(tp, 0);
5013         }
5014         return err;
5015 }
5016
5017 #ifdef CONFIG_NET_POLL_CONTROLLER
5018 static void tg3_poll_controller(struct net_device *dev)
5019 {
5020         int i;
5021         struct tg3 *tp = netdev_priv(dev);
5022
5023         for (i = 0; i < tp->irq_cnt; i++)
5024                 tg3_interrupt(tp->napi[i].irq_vec, dev);
5025 }
5026 #endif
5027
5028 static void tg3_reset_task(struct work_struct *work)
5029 {
5030         struct tg3 *tp = container_of(work, struct tg3, reset_task);
5031         int err;
5032         unsigned int restart_timer;
5033
5034         tg3_full_lock(tp, 0);
5035
5036         if (!netif_running(tp->dev)) {
5037                 tg3_full_unlock(tp);
5038                 return;
5039         }
5040
5041         tg3_full_unlock(tp);
5042
5043         tg3_phy_stop(tp);
5044
5045         tg3_netif_stop(tp);
5046
5047         tg3_full_lock(tp, 1);
5048
5049         restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
5050         tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
5051
5052         if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
5053                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
5054                 tp->write32_rx_mbox = tg3_write_flush_reg32;
5055                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
5056                 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
5057         }
5058
5059         tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
5060         err = tg3_init_hw(tp, 1);
5061         if (err)
5062                 goto out;
5063
5064         tg3_netif_start(tp);
5065
5066         if (restart_timer)
5067                 mod_timer(&tp->timer, jiffies + 1);
5068
5069 out:
5070         tg3_full_unlock(tp);
5071
5072         if (!err)
5073                 tg3_phy_start(tp);
5074 }
5075
5076 static void tg3_dump_short_state(struct tg3 *tp)
5077 {
5078         printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
5079                tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
5080         printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
5081                tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
5082 }
5083
5084 static void tg3_tx_timeout(struct net_device *dev)
5085 {
5086         struct tg3 *tp = netdev_priv(dev);
5087
5088         if (netif_msg_tx_err(tp)) {
5089                 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
5090                        dev->name);
5091                 tg3_dump_short_state(tp);
5092         }
5093
5094         schedule_work(&tp->reset_task);
5095 }
5096
5097 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5098 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
5099 {
5100         u32 base = (u32) mapping & 0xffffffff;
5101
5102         return ((base > 0xffffdcc0) &&
5103                 (base + len + 8 < base));
5104 }
5105
5106 /* Test for DMA addresses > 40-bit */
5107 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
5108                                           int len)
5109 {
5110 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
5111         if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
5112                 return (((u64) mapping + len) > DMA_BIT_MASK(40));
5113         return 0;
5114 #else
5115         return 0;
5116 #endif
5117 }
5118
5119 static void tg3_set_txd(struct tg3_napi *, int, dma_addr_t, int, u32, u32);
5120
5121 /* Workaround 4GB and 40-bit hardware DMA bugs. */
5122 static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
5123                                        struct sk_buff *skb, u32 last_plus_one,
5124                                        u32 *start, u32 base_flags, u32 mss)
5125 {
5126         struct tg3 *tp = tnapi->tp;
5127         struct sk_buff *new_skb;
5128         dma_addr_t new_addr = 0;
5129         u32 entry = *start;
5130         int i, ret = 0;
5131
5132         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5133                 new_skb = skb_copy(skb, GFP_ATOMIC);
5134         else {
5135                 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5136
5137                 new_skb = skb_copy_expand(skb,
5138                                           skb_headroom(skb) + more_headroom,
5139                                           skb_tailroom(skb), GFP_ATOMIC);
5140         }
5141
5142         if (!new_skb) {
5143                 ret = -1;
5144         } else {
5145                 /* New SKB is guaranteed to be linear. */
5146                 entry = *start;
5147                 ret = skb_dma_map(&tp->pdev->dev, new_skb, DMA_TO_DEVICE);
5148                 new_addr = skb_shinfo(new_skb)->dma_head;
5149
5150                 /* Make sure new skb does not cross any 4G boundaries.
5151                  * Drop the packet if it does.
5152                  */
5153                 if (ret || ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5154                             tg3_4g_overflow_test(new_addr, new_skb->len))) {
5155                         if (!ret)
5156                                 skb_dma_unmap(&tp->pdev->dev, new_skb,
5157                                               DMA_TO_DEVICE);
5158                         ret = -1;
5159                         dev_kfree_skb(new_skb);
5160                         new_skb = NULL;
5161                 } else {
5162                         tg3_set_txd(tnapi, entry, new_addr, new_skb->len,
5163                                     base_flags, 1 | (mss << 1));
5164                         *start = NEXT_TX(entry);
5165                 }
5166         }
5167
5168         /* Now clean up the sw ring entries. */
5169         i = 0;
5170         while (entry != last_plus_one) {
5171                 if (i == 0)
5172                         tnapi->tx_buffers[entry].skb = new_skb;
5173                 else
5174                         tnapi->tx_buffers[entry].skb = NULL;
5175                 entry = NEXT_TX(entry);
5176                 i++;
5177         }
5178
5179         skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
5180         dev_kfree_skb(skb);
5181
5182         return ret;
5183 }
5184
5185 static void tg3_set_txd(struct tg3_napi *tnapi, int entry,
5186                         dma_addr_t mapping, int len, u32 flags,
5187                         u32 mss_and_is_end)
5188 {
5189         struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry];
5190         int is_end = (mss_and_is_end & 0x1);
5191         u32 mss = (mss_and_is_end >> 1);
5192         u32 vlan_tag = 0;
5193
5194         if (is_end)
5195                 flags |= TXD_FLAG_END;
5196         if (flags & TXD_FLAG_VLAN) {
5197                 vlan_tag = flags >> 16;
5198                 flags &= 0xffff;
5199         }
5200         vlan_tag |= (mss << TXD_MSS_SHIFT);
5201
5202         txd->addr_hi = ((u64) mapping >> 32);
5203         txd->addr_lo = ((u64) mapping & 0xffffffff);
5204         txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5205         txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5206 }
5207
5208 /* hard_start_xmit for devices that don't have any bugs and
5209  * support TG3_FLG2_HW_TSO_2 and TG3_FLG2_HW_TSO_3 only.
5210  */
5211 static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
5212                                   struct net_device *dev)
5213 {
5214         struct tg3 *tp = netdev_priv(dev);
5215         u32 len, entry, base_flags, mss;
5216         struct skb_shared_info *sp;
5217         dma_addr_t mapping;
5218         struct tg3_napi *tnapi;
5219         struct netdev_queue *txq;
5220
5221         txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5222         tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5223         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
5224                 tnapi++;
5225
5226         /* We are running in BH disabled context with netif_tx_lock
5227          * and TX reclaim runs via tp->napi.poll inside of a software
5228          * interrupt.  Furthermore, IRQ processing runs lockless so we have
5229          * no IRQ context deadlocks to worry about either.  Rejoice!
5230          */
5231         if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5232                 if (!netif_tx_queue_stopped(txq)) {
5233                         netif_tx_stop_queue(txq);
5234
5235                         /* This is a hard error, log it. */
5236                         printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5237                                "queue awake!\n", dev->name);
5238                 }
5239                 return NETDEV_TX_BUSY;
5240         }
5241
5242         entry = tnapi->tx_prod;
5243         base_flags = 0;
5244         mss = 0;
5245         if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5246                 int tcp_opt_len, ip_tcp_len;
5247                 u32 hdrlen;
5248
5249                 if (skb_header_cloned(skb) &&
5250                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5251                         dev_kfree_skb(skb);
5252                         goto out_unlock;
5253                 }
5254
5255                 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
5256                         hdrlen = skb_headlen(skb) - ETH_HLEN;
5257                 else {
5258                         struct iphdr *iph = ip_hdr(skb);
5259
5260                         tcp_opt_len = tcp_optlen(skb);
5261                         ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5262
5263                         iph->check = 0;
5264                         iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
5265                         hdrlen = ip_tcp_len + tcp_opt_len;
5266                 }
5267
5268                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5269                         mss |= (hdrlen & 0xc) << 12;
5270                         if (hdrlen & 0x10)
5271                                 base_flags |= 0x00000010;
5272                         base_flags |= (hdrlen & 0x3e0) << 5;
5273                 } else
5274                         mss |= hdrlen << 9;
5275
5276                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5277                                TXD_FLAG_CPU_POST_DMA);
5278
5279                 tcp_hdr(skb)->check = 0;
5280
5281         }
5282         else if (skb->ip_summed == CHECKSUM_PARTIAL)
5283                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5284 #if TG3_VLAN_TAG_USED
5285         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5286                 base_flags |= (TXD_FLAG_VLAN |
5287                                (vlan_tx_tag_get(skb) << 16));
5288 #endif
5289
5290         if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
5291                 dev_kfree_skb(skb);
5292                 goto out_unlock;
5293         }
5294
5295         sp = skb_shinfo(skb);
5296
5297         mapping = sp->dma_head;
5298
5299         tnapi->tx_buffers[entry].skb = skb;
5300
5301         len = skb_headlen(skb);
5302
5303         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
5304             !mss && skb->len > ETH_DATA_LEN)
5305                 base_flags |= TXD_FLAG_JMB_PKT;
5306
5307         tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5308                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5309
5310         entry = NEXT_TX(entry);
5311
5312         /* Now loop through additional data fragments, and queue them. */
5313         if (skb_shinfo(skb)->nr_frags > 0) {
5314                 unsigned int i, last;
5315
5316                 last = skb_shinfo(skb)->nr_frags - 1;
5317                 for (i = 0; i <= last; i++) {
5318                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5319
5320                         len = frag->size;
5321                         mapping = sp->dma_maps[i];
5322                         tnapi->tx_buffers[entry].skb = NULL;
5323
5324                         tg3_set_txd(tnapi, entry, mapping, len,
5325                                     base_flags, (i == last) | (mss << 1));
5326
5327                         entry = NEXT_TX(entry);
5328                 }
5329         }
5330
5331         /* Packets are ready, update Tx producer idx local and on card. */
5332         tw32_tx_mbox(tnapi->prodmbox, entry);
5333
5334         tnapi->tx_prod = entry;
5335         if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5336                 netif_tx_stop_queue(txq);
5337                 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5338                         netif_tx_wake_queue(txq);
5339         }
5340
5341 out_unlock:
5342         mmiowb();
5343
5344         return NETDEV_TX_OK;
5345 }
5346
5347 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *,
5348                                           struct net_device *);
5349
5350 /* Use GSO to workaround a rare TSO bug that may be triggered when the
5351  * TSO header is greater than 80 bytes.
5352  */
5353 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5354 {
5355         struct sk_buff *segs, *nskb;
5356         u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
5357
5358         /* Estimate the number of fragments in the worst case */
5359         if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
5360                 netif_stop_queue(tp->dev);
5361                 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
5362                         return NETDEV_TX_BUSY;
5363
5364                 netif_wake_queue(tp->dev);
5365         }
5366
5367         segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
5368         if (IS_ERR(segs))
5369                 goto tg3_tso_bug_end;
5370
5371         do {
5372                 nskb = segs;
5373                 segs = segs->next;
5374                 nskb->next = NULL;
5375                 tg3_start_xmit_dma_bug(nskb, tp->dev);
5376         } while (segs);
5377
5378 tg3_tso_bug_end:
5379         dev_kfree_skb(skb);
5380
5381         return NETDEV_TX_OK;
5382 }
5383
5384 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5385  * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5386  */
5387 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
5388                                           struct net_device *dev)
5389 {
5390         struct tg3 *tp = netdev_priv(dev);
5391         u32 len, entry, base_flags, mss;
5392         struct skb_shared_info *sp;
5393         int would_hit_hwbug;
5394         dma_addr_t mapping;
5395         struct tg3_napi *tnapi;
5396         struct netdev_queue *txq;
5397
5398         txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5399         tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5400         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
5401                 tnapi++;
5402
5403         /* We are running in BH disabled context with netif_tx_lock
5404          * and TX reclaim runs via tp->napi.poll inside of a software
5405          * interrupt.  Furthermore, IRQ processing runs lockless so we have
5406          * no IRQ context deadlocks to worry about either.  Rejoice!
5407          */
5408         if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5409                 if (!netif_tx_queue_stopped(txq)) {
5410                         netif_tx_stop_queue(txq);
5411
5412                         /* This is a hard error, log it. */
5413                         printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5414                                "queue awake!\n", dev->name);
5415                 }
5416                 return NETDEV_TX_BUSY;
5417         }
5418
5419         entry = tnapi->tx_prod;
5420         base_flags = 0;
5421         if (skb->ip_summed == CHECKSUM_PARTIAL)
5422                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5423
5424         if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5425                 struct iphdr *iph;
5426                 u32 tcp_opt_len, ip_tcp_len, hdr_len;
5427
5428                 if (skb_header_cloned(skb) &&
5429                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5430                         dev_kfree_skb(skb);
5431                         goto out_unlock;
5432                 }
5433
5434                 tcp_opt_len = tcp_optlen(skb);
5435                 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5436
5437                 hdr_len = ip_tcp_len + tcp_opt_len;
5438                 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
5439                              (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
5440                         return (tg3_tso_bug(tp, skb));
5441
5442                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5443                                TXD_FLAG_CPU_POST_DMA);
5444
5445                 iph = ip_hdr(skb);
5446                 iph->check = 0;
5447                 iph->tot_len = htons(mss + hdr_len);
5448                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
5449                         tcp_hdr(skb)->check = 0;
5450                         base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
5451                 } else
5452                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5453                                                                  iph->daddr, 0,
5454                                                                  IPPROTO_TCP,
5455                                                                  0);
5456
5457                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)
5458                         mss |= hdr_len << 9;
5459                 else if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_1) ||
5460                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
5461                         if (tcp_opt_len || iph->ihl > 5) {
5462                                 int tsflags;
5463
5464                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5465                                 mss |= (tsflags << 11);
5466                         }
5467                 } else {
5468                         if (tcp_opt_len || iph->ihl > 5) {
5469                                 int tsflags;
5470
5471                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5472                                 base_flags |= tsflags << 12;
5473                         }
5474                 }
5475         }
5476 #if TG3_VLAN_TAG_USED
5477         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5478                 base_flags |= (TXD_FLAG_VLAN |
5479                                (vlan_tx_tag_get(skb) << 16));
5480 #endif
5481
5482         if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
5483                 dev_kfree_skb(skb);
5484                 goto out_unlock;
5485         }
5486
5487         sp = skb_shinfo(skb);
5488
5489         mapping = sp->dma_head;
5490
5491         tnapi->tx_buffers[entry].skb = skb;
5492
5493         would_hit_hwbug = 0;
5494
5495         len = skb_headlen(skb);
5496
5497         if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) && len <= 8)
5498                 would_hit_hwbug = 1;
5499
5500         if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5501             tg3_4g_overflow_test(mapping, len))
5502                 would_hit_hwbug = 1;
5503
5504         if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5505             tg3_40bit_overflow_test(tp, mapping, len))
5506                 would_hit_hwbug = 1;
5507
5508         if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
5509                 would_hit_hwbug = 1;
5510
5511         tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5512                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5513
5514         entry = NEXT_TX(entry);
5515
5516         /* Now loop through additional data fragments, and queue them. */
5517         if (skb_shinfo(skb)->nr_frags > 0) {
5518                 unsigned int i, last;
5519
5520                 last = skb_shinfo(skb)->nr_frags - 1;
5521                 for (i = 0; i <= last; i++) {
5522                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5523
5524                         len = frag->size;
5525                         mapping = sp->dma_maps[i];
5526
5527                         tnapi->tx_buffers[entry].skb = NULL;
5528
5529                         if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) &&
5530                             len <= 8)
5531                                 would_hit_hwbug = 1;
5532
5533                         if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5534                             tg3_4g_overflow_test(mapping, len))
5535                                 would_hit_hwbug = 1;
5536
5537                         if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5538                             tg3_40bit_overflow_test(tp, mapping, len))
5539                                 would_hit_hwbug = 1;
5540
5541                         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5542                                 tg3_set_txd(tnapi, entry, mapping, len,
5543                                             base_flags, (i == last)|(mss << 1));
5544                         else
5545                                 tg3_set_txd(tnapi, entry, mapping, len,
5546                                             base_flags, (i == last));
5547
5548                         entry = NEXT_TX(entry);
5549                 }
5550         }
5551
5552         if (would_hit_hwbug) {
5553                 u32 last_plus_one = entry;
5554                 u32 start;
5555
5556                 start = entry - 1 - skb_shinfo(skb)->nr_frags;
5557                 start &= (TG3_TX_RING_SIZE - 1);
5558
5559                 /* If the workaround fails due to memory/mapping
5560                  * failure, silently drop this packet.
5561                  */
5562                 if (tigon3_dma_hwbug_workaround(tnapi, skb, last_plus_one,
5563                                                 &start, base_flags, mss))
5564                         goto out_unlock;
5565
5566                 entry = start;
5567         }
5568
5569         /* Packets are ready, update Tx producer idx local and on card. */
5570         tw32_tx_mbox(tnapi->prodmbox, entry);
5571
5572         tnapi->tx_prod = entry;
5573         if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5574                 netif_tx_stop_queue(txq);
5575                 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5576                         netif_tx_wake_queue(txq);
5577         }
5578
5579 out_unlock:
5580         mmiowb();
5581
5582         return NETDEV_TX_OK;
5583 }
5584
5585 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
5586                                int new_mtu)
5587 {
5588         dev->mtu = new_mtu;
5589
5590         if (new_mtu > ETH_DATA_LEN) {
5591                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
5592                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
5593                         ethtool_op_set_tso(dev, 0);
5594                 }
5595                 else
5596                         tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
5597         } else {
5598                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
5599                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
5600                 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
5601         }
5602 }
5603
5604 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
5605 {
5606         struct tg3 *tp = netdev_priv(dev);
5607         int err;
5608
5609         if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
5610                 return -EINVAL;
5611
5612         if (!netif_running(dev)) {
5613                 /* We'll just catch it later when the
5614                  * device is up'd.
5615                  */
5616                 tg3_set_mtu(dev, tp, new_mtu);
5617                 return 0;
5618         }
5619
5620         tg3_phy_stop(tp);
5621
5622         tg3_netif_stop(tp);
5623
5624         tg3_full_lock(tp, 1);
5625
5626         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5627
5628         tg3_set_mtu(dev, tp, new_mtu);
5629
5630         err = tg3_restart_hw(tp, 0);
5631
5632         if (!err)
5633                 tg3_netif_start(tp);
5634
5635         tg3_full_unlock(tp);
5636
5637         if (!err)
5638                 tg3_phy_start(tp);
5639
5640         return err;
5641 }
5642
5643 static void tg3_rx_prodring_free(struct tg3 *tp,
5644                                  struct tg3_rx_prodring_set *tpr)
5645 {
5646         int i;
5647         struct ring_info *rxp;
5648
5649         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5650                 rxp = &tpr->rx_std_buffers[i];
5651
5652                 if (rxp->skb == NULL)
5653                         continue;
5654
5655                 pci_unmap_single(tp->pdev,
5656                                  pci_unmap_addr(rxp, mapping),
5657                                  tp->rx_pkt_map_sz,
5658                                  PCI_DMA_FROMDEVICE);
5659                 dev_kfree_skb_any(rxp->skb);
5660                 rxp->skb = NULL;
5661         }
5662
5663         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
5664                 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
5665                         rxp = &tpr->rx_jmb_buffers[i];
5666
5667                         if (rxp->skb == NULL)
5668                                 continue;
5669
5670                         pci_unmap_single(tp->pdev,
5671                                          pci_unmap_addr(rxp, mapping),
5672                                          TG3_RX_JMB_MAP_SZ,
5673                                          PCI_DMA_FROMDEVICE);
5674                         dev_kfree_skb_any(rxp->skb);
5675                         rxp->skb = NULL;
5676                 }
5677         }
5678 }
5679
5680 /* Initialize tx/rx rings for packet processing.
5681  *
5682  * The chip has been shut down and the driver detached from
5683  * the networking, so no interrupts or new tx packets will
5684  * end up in the driver.  tp->{tx,}lock are held and thus
5685  * we may not sleep.
5686  */
5687 static int tg3_rx_prodring_alloc(struct tg3 *tp,
5688                                  struct tg3_rx_prodring_set *tpr)
5689 {
5690         u32 i, rx_pkt_dma_sz;
5691         struct tg3_napi *tnapi = &tp->napi[0];
5692
5693         /* Zero out all descriptors. */
5694         memset(tpr->rx_std, 0, TG3_RX_RING_BYTES);
5695
5696         rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
5697         if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
5698             tp->dev->mtu > ETH_DATA_LEN)
5699                 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
5700         tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
5701
5702         /* Initialize invariants of the rings, we only set this
5703          * stuff once.  This works because the card does not
5704          * write into the rx buffer posting rings.
5705          */
5706         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5707                 struct tg3_rx_buffer_desc *rxd;
5708
5709                 rxd = &tpr->rx_std[i];
5710                 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
5711                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
5712                 rxd->opaque = (RXD_OPAQUE_RING_STD |
5713                                (i << RXD_OPAQUE_INDEX_SHIFT));
5714         }
5715
5716         /* Now allocate fresh SKBs for each rx ring. */
5717         for (i = 0; i < tp->rx_pending; i++) {
5718                 if (tg3_alloc_rx_skb(tnapi, RXD_OPAQUE_RING_STD, -1, i) < 0) {
5719                         printk(KERN_WARNING PFX
5720                                "%s: Using a smaller RX standard ring, "
5721                                "only %d out of %d buffers were allocated "
5722                                "successfully.\n",
5723                                tp->dev->name, i, tp->rx_pending);
5724                         if (i == 0)
5725                                 goto initfail;
5726                         tp->rx_pending = i;
5727                         break;
5728                 }
5729         }
5730
5731         if (!(tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE))
5732                 goto done;
5733
5734         memset(tpr->rx_jmb, 0, TG3_RX_JUMBO_RING_BYTES);
5735
5736         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
5737                 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
5738                         struct tg3_rx_buffer_desc *rxd;
5739
5740                         rxd = &tpr->rx_jmb[i].std;
5741                         rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
5742                         rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
5743                                 RXD_FLAG_JUMBO;
5744                         rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
5745                                (i << RXD_OPAQUE_INDEX_SHIFT));
5746                 }
5747
5748                 for (i = 0; i < tp->rx_jumbo_pending; i++) {
5749                         if (tg3_alloc_rx_skb(tnapi, RXD_OPAQUE_RING_JUMBO,
5750                                              -1, i) < 0) {
5751                                 printk(KERN_WARNING PFX
5752                                        "%s: Using a smaller RX jumbo ring, "
5753                                        "only %d out of %d buffers were "
5754                                        "allocated successfully.\n",
5755                                        tp->dev->name, i, tp->rx_jumbo_pending);
5756                                 if (i == 0)
5757                                         goto initfail;
5758                                 tp->rx_jumbo_pending = i;
5759                                 break;
5760                         }
5761                 }
5762         }
5763
5764 done:
5765         return 0;
5766
5767 initfail:
5768         tg3_rx_prodring_free(tp, tpr);
5769         return -ENOMEM;
5770 }
5771
5772 static void tg3_rx_prodring_fini(struct tg3 *tp,
5773                                  struct tg3_rx_prodring_set *tpr)
5774 {
5775         kfree(tpr->rx_std_buffers);
5776         tpr->rx_std_buffers = NULL;
5777         kfree(tpr->rx_jmb_buffers);
5778         tpr->rx_jmb_buffers = NULL;
5779         if (tpr->rx_std) {
5780                 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
5781                                     tpr->rx_std, tpr->rx_std_mapping);
5782                 tpr->rx_std = NULL;
5783         }
5784         if (tpr->rx_jmb) {
5785                 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
5786                                     tpr->rx_jmb, tpr->rx_jmb_mapping);
5787                 tpr->rx_jmb = NULL;
5788         }
5789 }
5790
5791 static int tg3_rx_prodring_init(struct tg3 *tp,
5792                                 struct tg3_rx_prodring_set *tpr)
5793 {
5794         tpr->rx_std_buffers = kzalloc(sizeof(struct ring_info) *
5795                                       TG3_RX_RING_SIZE, GFP_KERNEL);
5796         if (!tpr->rx_std_buffers)
5797                 return -ENOMEM;
5798
5799         tpr->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
5800                                            &tpr->rx_std_mapping);
5801         if (!tpr->rx_std)
5802                 goto err_out;
5803
5804         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
5805                 tpr->rx_jmb_buffers = kzalloc(sizeof(struct ring_info) *
5806                                               TG3_RX_JUMBO_RING_SIZE,
5807                                               GFP_KERNEL);
5808                 if (!tpr->rx_jmb_buffers)
5809                         goto err_out;
5810
5811                 tpr->rx_jmb = pci_alloc_consistent(tp->pdev,
5812                                                    TG3_RX_JUMBO_RING_BYTES,
5813                                                    &tpr->rx_jmb_mapping);
5814                 if (!tpr->rx_jmb)
5815                         goto err_out;
5816         }
5817
5818         return 0;
5819
5820 err_out:
5821         tg3_rx_prodring_fini(tp, tpr);
5822         return -ENOMEM;
5823 }
5824
5825 /* Free up pending packets in all rx/tx rings.
5826  *
5827  * The chip has been shut down and the driver detached from
5828  * the networking, so no interrupts or new tx packets will
5829  * end up in the driver.  tp->{tx,}lock is not held and we are not
5830  * in an interrupt context and thus may sleep.
5831  */
5832 static void tg3_free_rings(struct tg3 *tp)
5833 {
5834         int i, j;
5835
5836         for (j = 0; j < tp->irq_cnt; j++) {
5837                 struct tg3_napi *tnapi = &tp->napi[j];
5838
5839                 if (!tnapi->tx_buffers)
5840                         continue;
5841
5842                 for (i = 0; i < TG3_TX_RING_SIZE; ) {
5843                         struct tx_ring_info *txp;
5844                         struct sk_buff *skb;
5845
5846                         txp = &tnapi->tx_buffers[i];
5847                         skb = txp->skb;
5848
5849                         if (skb == NULL) {
5850                                 i++;
5851                                 continue;
5852                         }
5853
5854                         skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
5855
5856                         txp->skb = NULL;
5857
5858                         i += skb_shinfo(skb)->nr_frags + 1;
5859
5860                         dev_kfree_skb_any(skb);
5861                 }
5862         }
5863
5864         tg3_rx_prodring_free(tp, &tp->prodring[0]);
5865 }
5866
5867 /* Initialize tx/rx rings for packet processing.
5868  *
5869  * The chip has been shut down and the driver detached from
5870  * the networking, so no interrupts or new tx packets will
5871  * end up in the driver.  tp->{tx,}lock are held and thus
5872  * we may not sleep.
5873  */
5874 static int tg3_init_rings(struct tg3 *tp)
5875 {
5876         int i;
5877
5878         /* Free up all the SKBs. */
5879         tg3_free_rings(tp);
5880
5881         for (i = 0; i < tp->irq_cnt; i++) {
5882                 struct tg3_napi *tnapi = &tp->napi[i];
5883
5884                 tnapi->last_tag = 0;
5885                 tnapi->last_irq_tag = 0;
5886                 tnapi->hw_status->status = 0;
5887                 tnapi->hw_status->status_tag = 0;
5888                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
5889
5890                 tnapi->tx_prod = 0;
5891                 tnapi->tx_cons = 0;
5892                 if (tnapi->tx_ring)
5893                         memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
5894
5895                 tnapi->rx_rcb_ptr = 0;
5896                 if (tnapi->rx_rcb)
5897                         memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
5898         }
5899
5900         return tg3_rx_prodring_alloc(tp, &tp->prodring[0]);
5901 }
5902
5903 /*
5904  * Must not be invoked with interrupt sources disabled and
5905  * the hardware shutdown down.
5906  */
5907 static void tg3_free_consistent(struct tg3 *tp)
5908 {
5909         int i;
5910
5911         for (i = 0; i < tp->irq_cnt; i++) {
5912                 struct tg3_napi *tnapi = &tp->napi[i];
5913
5914                 if (tnapi->tx_ring) {
5915                         pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
5916                                 tnapi->tx_ring, tnapi->tx_desc_mapping);
5917                         tnapi->tx_ring = NULL;
5918                 }
5919
5920                 kfree(tnapi->tx_buffers);
5921                 tnapi->tx_buffers = NULL;
5922
5923                 if (tnapi->rx_rcb) {
5924                         pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
5925                                             tnapi->rx_rcb,
5926                                             tnapi->rx_rcb_mapping);
5927                         tnapi->rx_rcb = NULL;
5928                 }
5929
5930                 if (tnapi->hw_status) {
5931                         pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
5932                                             tnapi->hw_status,
5933                                             tnapi->status_mapping);
5934                         tnapi->hw_status = NULL;
5935                 }
5936         }
5937
5938         if (tp->hw_stats) {
5939                 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
5940                                     tp->hw_stats, tp->stats_mapping);
5941                 tp->hw_stats = NULL;
5942         }
5943
5944         tg3_rx_prodring_fini(tp, &tp->prodring[0]);
5945 }
5946
5947 /*
5948  * Must not be invoked with interrupt sources disabled and
5949  * the hardware shutdown down.  Can sleep.
5950  */
5951 static int tg3_alloc_consistent(struct tg3 *tp)
5952 {
5953         int i;
5954
5955         if (tg3_rx_prodring_init(tp, &tp->prodring[0]))
5956                 return -ENOMEM;
5957
5958         tp->hw_stats = pci_alloc_consistent(tp->pdev,
5959                                             sizeof(struct tg3_hw_stats),
5960                                             &tp->stats_mapping);
5961         if (!tp->hw_stats)
5962                 goto err_out;
5963
5964         memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
5965
5966         for (i = 0; i < tp->irq_cnt; i++) {
5967                 struct tg3_napi *tnapi = &tp->napi[i];
5968                 struct tg3_hw_status *sblk;
5969
5970                 tnapi->hw_status = pci_alloc_consistent(tp->pdev,
5971                                                         TG3_HW_STATUS_SIZE,
5972                                                         &tnapi->status_mapping);
5973                 if (!tnapi->hw_status)
5974                         goto err_out;
5975
5976                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
5977                 sblk = tnapi->hw_status;
5978
5979                 /*
5980                  * When RSS is enabled, the status block format changes
5981                  * slightly.  The "rx_jumbo_consumer", "reserved",
5982                  * and "rx_mini_consumer" members get mapped to the
5983                  * other three rx return ring producer indexes.
5984                  */
5985                 switch (i) {
5986                 default:
5987                         tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
5988                         break;
5989                 case 2:
5990                         tnapi->rx_rcb_prod_idx = &sblk->rx_jumbo_consumer;
5991                         break;
5992                 case 3:
5993                         tnapi->rx_rcb_prod_idx = &sblk->reserved;
5994                         break;
5995                 case 4:
5996                         tnapi->rx_rcb_prod_idx = &sblk->rx_mini_consumer;
5997                         break;
5998                 }
5999
6000                 /*
6001                  * If multivector RSS is enabled, vector 0 does not handle
6002                  * rx or tx interrupts.  Don't allocate any resources for it.
6003                  */
6004                 if (!i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS))
6005                         continue;
6006
6007                 tnapi->rx_rcb = pci_alloc_consistent(tp->pdev,
6008                                                      TG3_RX_RCB_RING_BYTES(tp),
6009                                                      &tnapi->rx_rcb_mapping);
6010                 if (!tnapi->rx_rcb)
6011                         goto err_out;
6012
6013                 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
6014
6015                 tnapi->tx_buffers = kzalloc(sizeof(struct tx_ring_info) *
6016                                             TG3_TX_RING_SIZE, GFP_KERNEL);
6017                 if (!tnapi->tx_buffers)
6018                         goto err_out;
6019
6020                 tnapi->tx_ring = pci_alloc_consistent(tp->pdev,
6021                                                       TG3_TX_RING_BYTES,
6022                                                       &tnapi->tx_desc_mapping);
6023                 if (!tnapi->tx_ring)
6024                         goto err_out;
6025         }
6026
6027         return 0;
6028
6029 err_out:
6030         tg3_free_consistent(tp);
6031         return -ENOMEM;
6032 }
6033
6034 #define MAX_WAIT_CNT 1000
6035
6036 /* To stop a block, clear the enable bit and poll till it
6037  * clears.  tp->lock is held.
6038  */
6039 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
6040 {
6041         unsigned int i;
6042         u32 val;
6043
6044         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6045                 switch (ofs) {
6046                 case RCVLSC_MODE:
6047                 case DMAC_MODE:
6048                 case MBFREE_MODE:
6049                 case BUFMGR_MODE:
6050                 case MEMARB_MODE:
6051                         /* We can't enable/disable these bits of the
6052                          * 5705/5750, just say success.
6053                          */
6054                         return 0;
6055
6056                 default:
6057                         break;
6058                 }
6059         }
6060
6061         val = tr32(ofs);
6062         val &= ~enable_bit;
6063         tw32_f(ofs, val);
6064
6065         for (i = 0; i < MAX_WAIT_CNT; i++) {
6066                 udelay(100);
6067                 val = tr32(ofs);
6068                 if ((val & enable_bit) == 0)
6069                         break;
6070         }
6071
6072         if (i == MAX_WAIT_CNT && !silent) {
6073                 printk(KERN_ERR PFX "tg3_stop_block timed out, "
6074                        "ofs=%lx enable_bit=%x\n",
6075                        ofs, enable_bit);
6076                 return -ENODEV;
6077         }
6078
6079         return 0;
6080 }
6081
6082 /* tp->lock is held. */
6083 static int tg3_abort_hw(struct tg3 *tp, int silent)
6084 {
6085         int i, err;
6086
6087         tg3_disable_ints(tp);
6088
6089         tp->rx_mode &= ~RX_MODE_ENABLE;
6090         tw32_f(MAC_RX_MODE, tp->rx_mode);
6091         udelay(10);
6092
6093         err  = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
6094         err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
6095         err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
6096         err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
6097         err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
6098         err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
6099
6100         err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
6101         err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
6102         err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
6103         err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
6104         err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
6105         err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
6106         err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
6107
6108         tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
6109         tw32_f(MAC_MODE, tp->mac_mode);
6110         udelay(40);
6111
6112         tp->tx_mode &= ~TX_MODE_ENABLE;
6113         tw32_f(MAC_TX_MODE, tp->tx_mode);
6114
6115         for (i = 0; i < MAX_WAIT_CNT; i++) {
6116                 udelay(100);
6117                 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
6118                         break;
6119         }
6120         if (i >= MAX_WAIT_CNT) {
6121                 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
6122                        "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
6123                        tp->dev->name, tr32(MAC_TX_MODE));
6124                 err |= -ENODEV;
6125         }
6126
6127         err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
6128         err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
6129         err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
6130
6131         tw32(FTQ_RESET, 0xffffffff);
6132         tw32(FTQ_RESET, 0x00000000);
6133
6134         err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
6135         err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
6136
6137         for (i = 0; i < tp->irq_cnt; i++) {
6138                 struct tg3_napi *tnapi = &tp->napi[i];
6139                 if (tnapi->hw_status)
6140                         memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6141         }
6142         if (tp->hw_stats)
6143                 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6144
6145         return err;
6146 }
6147
6148 static void tg3_ape_send_event(struct tg3 *tp, u32 event)
6149 {
6150         int i;
6151         u32 apedata;
6152
6153         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
6154         if (apedata != APE_SEG_SIG_MAGIC)
6155                 return;
6156
6157         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
6158         if (!(apedata & APE_FW_STATUS_READY))
6159                 return;
6160
6161         /* Wait for up to 1 millisecond for APE to service previous event. */
6162         for (i = 0; i < 10; i++) {
6163                 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
6164                         return;
6165
6166                 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
6167
6168                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6169                         tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
6170                                         event | APE_EVENT_STATUS_EVENT_PENDING);
6171
6172                 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
6173
6174                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6175                         break;
6176
6177                 udelay(100);
6178         }
6179
6180         if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6181                 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
6182 }
6183
6184 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
6185 {
6186         u32 event;
6187         u32 apedata;
6188
6189         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
6190                 return;
6191
6192         switch (kind) {
6193                 case RESET_KIND_INIT:
6194                         tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
6195                                         APE_HOST_SEG_SIG_MAGIC);
6196                         tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
6197                                         APE_HOST_SEG_LEN_MAGIC);
6198                         apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
6199                         tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
6200                         tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
6201                                         APE_HOST_DRIVER_ID_MAGIC);
6202                         tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
6203                                         APE_HOST_BEHAV_NO_PHYLOCK);
6204
6205                         event = APE_EVENT_STATUS_STATE_START;
6206                         break;
6207                 case RESET_KIND_SHUTDOWN:
6208                         /* With the interface we are currently using,
6209                          * APE does not track driver state.  Wiping
6210                          * out the HOST SEGMENT SIGNATURE forces
6211                          * the APE to assume OS absent status.
6212                          */
6213                         tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
6214
6215                         event = APE_EVENT_STATUS_STATE_UNLOAD;
6216                         break;
6217                 case RESET_KIND_SUSPEND:
6218                         event = APE_EVENT_STATUS_STATE_SUSPEND;
6219                         break;
6220                 default:
6221                         return;
6222         }
6223
6224         event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
6225
6226         tg3_ape_send_event(tp, event);
6227 }
6228
6229 /* tp->lock is held. */
6230 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
6231 {
6232         tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
6233                       NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
6234
6235         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6236                 switch (kind) {
6237                 case RESET_KIND_INIT:
6238                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6239                                       DRV_STATE_START);
6240                         break;
6241
6242                 case RESET_KIND_SHUTDOWN:
6243                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6244                                       DRV_STATE_UNLOAD);
6245                         break;
6246
6247                 case RESET_KIND_SUSPEND:
6248                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6249                                       DRV_STATE_SUSPEND);
6250                         break;
6251
6252                 default:
6253                         break;
6254                 }
6255         }
6256
6257         if (kind == RESET_KIND_INIT ||
6258             kind == RESET_KIND_SUSPEND)
6259                 tg3_ape_driver_state_change(tp, kind);
6260 }
6261
6262 /* tp->lock is held. */
6263 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
6264 {
6265         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6266                 switch (kind) {
6267                 case RESET_KIND_INIT:
6268                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6269                                       DRV_STATE_START_DONE);
6270                         break;
6271
6272                 case RESET_KIND_SHUTDOWN:
6273                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6274                                       DRV_STATE_UNLOAD_DONE);
6275                         break;
6276
6277                 default:
6278                         break;
6279                 }
6280         }
6281
6282         if (kind == RESET_KIND_SHUTDOWN)
6283                 tg3_ape_driver_state_change(tp, kind);
6284 }
6285
6286 /* tp->lock is held. */
6287 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
6288 {
6289         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6290                 switch (kind) {
6291                 case RESET_KIND_INIT:
6292                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6293                                       DRV_STATE_START);
6294                         break;
6295
6296                 case RESET_KIND_SHUTDOWN:
6297                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6298                                       DRV_STATE_UNLOAD);
6299                         break;
6300
6301                 case RESET_KIND_SUSPEND:
6302                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6303                                       DRV_STATE_SUSPEND);
6304                         break;
6305
6306                 default:
6307                         break;
6308                 }
6309         }
6310 }
6311
6312 static int tg3_poll_fw(struct tg3 *tp)
6313 {
6314         int i;
6315         u32 val;
6316
6317         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6318                 /* Wait up to 20ms for init done. */
6319                 for (i = 0; i < 200; i++) {
6320                         if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
6321                                 return 0;
6322                         udelay(100);
6323                 }
6324                 return -ENODEV;
6325         }
6326
6327         /* Wait for firmware initialization to complete. */
6328         for (i = 0; i < 100000; i++) {
6329                 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
6330                 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
6331                         break;
6332                 udelay(10);
6333         }
6334
6335         /* Chip might not be fitted with firmware.  Some Sun onboard
6336          * parts are configured like that.  So don't signal the timeout
6337          * of the above loop as an error, but do report the lack of
6338          * running firmware once.
6339          */
6340         if (i >= 100000 &&
6341             !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
6342                 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
6343
6344                 printk(KERN_INFO PFX "%s: No firmware running.\n",
6345                        tp->dev->name);
6346         }
6347
6348         return 0;
6349 }
6350
6351 /* Save PCI command register before chip reset */
6352 static void tg3_save_pci_state(struct tg3 *tp)
6353 {
6354         pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
6355 }
6356
6357 /* Restore PCI state after chip reset */
6358 static void tg3_restore_pci_state(struct tg3 *tp)
6359 {
6360         u32 val;
6361
6362         /* Re-enable indirect register accesses. */
6363         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
6364                                tp->misc_host_ctrl);
6365
6366         /* Set MAX PCI retry to zero. */
6367         val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
6368         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6369             (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
6370                 val |= PCISTATE_RETRY_SAME_DMA;
6371         /* Allow reads and writes to the APE register and memory space. */
6372         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
6373                 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6374                        PCISTATE_ALLOW_APE_SHMEM_WR;
6375         pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
6376
6377         pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
6378
6379         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
6380                 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6381                         pcie_set_readrq(tp->pdev, 4096);
6382                 else {
6383                         pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
6384                                               tp->pci_cacheline_sz);
6385                         pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
6386                                               tp->pci_lat_timer);
6387                 }
6388         }
6389
6390         /* Make sure PCI-X relaxed ordering bit is clear. */
6391         if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
6392                 u16 pcix_cmd;
6393
6394                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6395                                      &pcix_cmd);
6396                 pcix_cmd &= ~PCI_X_CMD_ERO;
6397                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6398                                       pcix_cmd);
6399         }
6400
6401         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
6402
6403                 /* Chip reset on 5780 will reset MSI enable bit,
6404                  * so need to restore it.
6405                  */
6406                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6407                         u16 ctrl;
6408
6409                         pci_read_config_word(tp->pdev,
6410                                              tp->msi_cap + PCI_MSI_FLAGS,
6411                                              &ctrl);
6412                         pci_write_config_word(tp->pdev,
6413                                               tp->msi_cap + PCI_MSI_FLAGS,
6414                                               ctrl | PCI_MSI_FLAGS_ENABLE);
6415                         val = tr32(MSGINT_MODE);
6416                         tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
6417                 }
6418         }
6419 }
6420
6421 static void tg3_stop_fw(struct tg3 *);
6422
6423 /* tp->lock is held. */
6424 static int tg3_chip_reset(struct tg3 *tp)
6425 {
6426         u32 val;
6427         void (*write_op)(struct tg3 *, u32, u32);
6428         int i, err;
6429
6430         tg3_nvram_lock(tp);
6431
6432         tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
6433
6434         /* No matching tg3_nvram_unlock() after this because
6435          * chip reset below will undo the nvram lock.
6436          */
6437         tp->nvram_lock_cnt = 0;
6438
6439         /* GRC_MISC_CFG core clock reset will clear the memory
6440          * enable bit in PCI register 4 and the MSI enable bit
6441          * on some chips, so we save relevant registers here.
6442          */
6443         tg3_save_pci_state(tp);
6444
6445         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
6446             (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
6447                 tw32(GRC_FASTBOOT_PC, 0);
6448
6449         /*
6450          * We must avoid the readl() that normally takes place.
6451          * It locks machines, causes machine checks, and other
6452          * fun things.  So, temporarily disable the 5701
6453          * hardware workaround, while we do the reset.
6454          */
6455         write_op = tp->write32;
6456         if (write_op == tg3_write_flush_reg32)
6457                 tp->write32 = tg3_write32;
6458
6459         /* Prevent the irq handler from reading or writing PCI registers
6460          * during chip reset when the memory enable bit in the PCI command
6461          * register may be cleared.  The chip does not generate interrupt
6462          * at this time, but the irq handler may still be called due to irq
6463          * sharing or irqpoll.
6464          */
6465         tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
6466         for (i = 0; i < tp->irq_cnt; i++) {
6467                 struct tg3_napi *tnapi = &tp->napi[i];
6468                 if (tnapi->hw_status) {
6469                         tnapi->hw_status->status = 0;
6470                         tnapi->hw_status->status_tag = 0;
6471                 }
6472                 tnapi->last_tag = 0;
6473                 tnapi->last_irq_tag = 0;
6474         }
6475         smp_mb();
6476
6477         for (i = 0; i < tp->irq_cnt; i++)
6478                 synchronize_irq(tp->napi[i].irq_vec);
6479
6480         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6481                 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
6482                 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
6483         }
6484
6485         /* do the reset */
6486         val = GRC_MISC_CFG_CORECLK_RESET;
6487
6488         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
6489                 if (tr32(0x7e2c) == 0x60) {
6490                         tw32(0x7e2c, 0x20);
6491                 }
6492                 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
6493                         tw32(GRC_MISC_CFG, (1 << 29));
6494                         val |= (1 << 29);
6495                 }
6496         }
6497
6498         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6499                 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
6500                 tw32(GRC_VCPU_EXT_CTRL,
6501                      tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
6502         }
6503
6504         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6505                 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
6506         tw32(GRC_MISC_CFG, val);
6507
6508         /* restore 5701 hardware bug workaround write method */
6509         tp->write32 = write_op;
6510
6511         /* Unfortunately, we have to delay before the PCI read back.
6512          * Some 575X chips even will not respond to a PCI cfg access
6513          * when the reset command is given to the chip.
6514          *
6515          * How do these hardware designers expect things to work
6516          * properly if the PCI write is posted for a long period
6517          * of time?  It is always necessary to have some method by
6518          * which a register read back can occur to push the write
6519          * out which does the reset.
6520          *
6521          * For most tg3 variants the trick below was working.
6522          * Ho hum...
6523          */
6524         udelay(120);
6525
6526         /* Flush PCI posted writes.  The normal MMIO registers
6527          * are inaccessible at this time so this is the only
6528          * way to make this reliably (actually, this is no longer
6529          * the case, see above).  I tried to use indirect
6530          * register read/write but this upset some 5701 variants.
6531          */
6532         pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
6533
6534         udelay(120);
6535
6536         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
6537                 u16 val16;
6538
6539                 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
6540                         int i;
6541                         u32 cfg_val;
6542
6543                         /* Wait for link training to complete.  */
6544                         for (i = 0; i < 5000; i++)
6545                                 udelay(100);
6546
6547                         pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
6548                         pci_write_config_dword(tp->pdev, 0xc4,
6549                                                cfg_val | (1 << 15));
6550                 }
6551
6552                 /* Clear the "no snoop" and "relaxed ordering" bits. */
6553                 pci_read_config_word(tp->pdev,
6554                                      tp->pcie_cap + PCI_EXP_DEVCTL,
6555                                      &val16);
6556                 val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
6557                            PCI_EXP_DEVCTL_NOSNOOP_EN);
6558                 /*
6559                  * Older PCIe devices only support the 128 byte
6560                  * MPS setting.  Enforce the restriction.
6561                  */
6562                 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
6563                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784))
6564                         val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
6565                 pci_write_config_word(tp->pdev,
6566                                       tp->pcie_cap + PCI_EXP_DEVCTL,
6567                                       val16);
6568
6569                 pcie_set_readrq(tp->pdev, 4096);
6570
6571                 /* Clear error status */
6572                 pci_write_config_word(tp->pdev,
6573                                       tp->pcie_cap + PCI_EXP_DEVSTA,
6574                                       PCI_EXP_DEVSTA_CED |
6575                                       PCI_EXP_DEVSTA_NFED |
6576                                       PCI_EXP_DEVSTA_FED |
6577                                       PCI_EXP_DEVSTA_URD);
6578         }
6579
6580         tg3_restore_pci_state(tp);
6581
6582         tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
6583
6584         val = 0;
6585         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
6586                 val = tr32(MEMARB_MODE);
6587         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
6588
6589         if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
6590                 tg3_stop_fw(tp);
6591                 tw32(0x5000, 0x400);
6592         }
6593
6594         tw32(GRC_MODE, tp->grc_mode);
6595
6596         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
6597                 val = tr32(0xc4);
6598
6599                 tw32(0xc4, val | (1 << 15));
6600         }
6601
6602         if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
6603             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6604                 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
6605                 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
6606                         tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
6607                 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6608         }
6609
6610         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6611                 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
6612                 tw32_f(MAC_MODE, tp->mac_mode);
6613         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
6614                 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
6615                 tw32_f(MAC_MODE, tp->mac_mode);
6616         } else if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
6617                 tp->mac_mode &= (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
6618                 if (tp->mac_mode & MAC_MODE_APE_TX_EN)
6619                         tp->mac_mode |= MAC_MODE_TDE_ENABLE;
6620                 tw32_f(MAC_MODE, tp->mac_mode);
6621         } else
6622                 tw32_f(MAC_MODE, 0);
6623         udelay(40);
6624
6625         tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
6626
6627         err = tg3_poll_fw(tp);
6628         if (err)
6629                 return err;
6630
6631         tg3_mdio_start(tp);
6632
6633         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6634                 u8 phy_addr;
6635
6636                 phy_addr = tp->phy_addr;
6637                 tp->phy_addr = TG3_PHY_PCIE_ADDR;
6638
6639                 tg3_writephy(tp, TG3_PCIEPHY_BLOCK_ADDR,
6640                              TG3_PCIEPHY_TXB_BLK << TG3_PCIEPHY_BLOCK_SHIFT);
6641                 val = TG3_PCIEPHY_TX0CTRL1_TXOCM | TG3_PCIEPHY_TX0CTRL1_RDCTL |
6642                       TG3_PCIEPHY_TX0CTRL1_TXCMV | TG3_PCIEPHY_TX0CTRL1_TKSEL |
6643                       TG3_PCIEPHY_TX0CTRL1_NB_EN;
6644                 tg3_writephy(tp, TG3_PCIEPHY_TX0CTRL1, val);
6645                 udelay(10);
6646
6647                 tg3_writephy(tp, TG3_PCIEPHY_BLOCK_ADDR,
6648                              TG3_PCIEPHY_XGXS_BLK1 << TG3_PCIEPHY_BLOCK_SHIFT);
6649                 val = TG3_PCIEPHY_PWRMGMT4_LOWPWR_EN |
6650                       TG3_PCIEPHY_PWRMGMT4_L1PLLPD_EN;
6651                 tg3_writephy(tp, TG3_PCIEPHY_PWRMGMT4, val);
6652                 udelay(10);
6653
6654                 tp->phy_addr = phy_addr;
6655         }
6656
6657         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
6658             tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
6659             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
6660             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) {
6661                 val = tr32(0x7c00);
6662
6663                 tw32(0x7c00, val | (1 << 25));
6664         }
6665
6666         /* Reprobe ASF enable state.  */
6667         tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
6668         tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
6669         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
6670         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
6671                 u32 nic_cfg;
6672
6673                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
6674                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
6675                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
6676                         tp->last_event_jiffies = jiffies;
6677                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
6678                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
6679                 }
6680         }
6681
6682         return 0;
6683 }
6684
6685 /* tp->lock is held. */
6686 static void tg3_stop_fw(struct tg3 *tp)
6687 {
6688         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
6689            !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
6690                 /* Wait for RX cpu to ACK the previous event. */
6691                 tg3_wait_for_event_ack(tp);
6692
6693                 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
6694
6695                 tg3_generate_fw_event(tp);
6696
6697                 /* Wait for RX cpu to ACK this event. */
6698                 tg3_wait_for_event_ack(tp);
6699         }
6700 }
6701
6702 /* tp->lock is held. */
6703 static int tg3_halt(struct tg3 *tp, int kind, int silent)
6704 {
6705         int err;
6706
6707         tg3_stop_fw(tp);
6708
6709         tg3_write_sig_pre_reset(tp, kind);
6710
6711         tg3_abort_hw(tp, silent);
6712         err = tg3_chip_reset(tp);
6713
6714         __tg3_set_mac_addr(tp, 0);
6715
6716         tg3_write_sig_legacy(tp, kind);
6717         tg3_write_sig_post_reset(tp, kind);
6718
6719         if (err)
6720                 return err;
6721
6722         return 0;
6723 }
6724
6725 #define RX_CPU_SCRATCH_BASE     0x30000
6726 #define RX_CPU_SCRATCH_SIZE     0x04000
6727 #define TX_CPU_SCRATCH_BASE     0x34000
6728 #define TX_CPU_SCRATCH_SIZE     0x04000
6729
6730 /* tp->lock is held. */
6731 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
6732 {
6733         int i;
6734
6735         BUG_ON(offset == TX_CPU_BASE &&
6736             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
6737
6738         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6739                 u32 val = tr32(GRC_VCPU_EXT_CTRL);
6740
6741                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
6742                 return 0;
6743         }
6744         if (offset == RX_CPU_BASE) {
6745                 for (i = 0; i < 10000; i++) {
6746                         tw32(offset + CPU_STATE, 0xffffffff);
6747                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
6748                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
6749                                 break;
6750                 }
6751
6752                 tw32(offset + CPU_STATE, 0xffffffff);
6753                 tw32_f(offset + CPU_MODE,  CPU_MODE_HALT);
6754                 udelay(10);
6755         } else {
6756                 for (i = 0; i < 10000; i++) {
6757                         tw32(offset + CPU_STATE, 0xffffffff);
6758                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
6759                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
6760                                 break;
6761                 }
6762         }
6763
6764         if (i >= 10000) {
6765                 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
6766                        "and %s CPU\n",
6767                        tp->dev->name,
6768                        (offset == RX_CPU_BASE ? "RX" : "TX"));
6769                 return -ENODEV;
6770         }
6771
6772         /* Clear firmware's nvram arbitration. */
6773         if (tp->tg3_flags & TG3_FLAG_NVRAM)
6774                 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
6775         return 0;
6776 }
6777
6778 struct fw_info {
6779         unsigned int fw_base;
6780         unsigned int fw_len;
6781         const __be32 *fw_data;
6782 };
6783
6784 /* tp->lock is held. */
6785 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
6786                                  int cpu_scratch_size, struct fw_info *info)
6787 {
6788         int err, lock_err, i;
6789         void (*write_op)(struct tg3 *, u32, u32);
6790
6791         if (cpu_base == TX_CPU_BASE &&
6792             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6793                 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
6794                        "TX cpu firmware on %s which is 5705.\n",
6795                        tp->dev->name);
6796                 return -EINVAL;
6797         }
6798
6799         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6800                 write_op = tg3_write_mem;
6801         else
6802                 write_op = tg3_write_indirect_reg32;
6803
6804         /* It is possible that bootcode is still loading at this point.
6805          * Get the nvram lock first before halting the cpu.
6806          */
6807         lock_err = tg3_nvram_lock(tp);
6808         err = tg3_halt_cpu(tp, cpu_base);
6809         if (!lock_err)
6810                 tg3_nvram_unlock(tp);
6811         if (err)
6812                 goto out;
6813
6814         for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
6815                 write_op(tp, cpu_scratch_base + i, 0);
6816         tw32(cpu_base + CPU_STATE, 0xffffffff);
6817         tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
6818         for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
6819                 write_op(tp, (cpu_scratch_base +
6820                               (info->fw_base & 0xffff) +
6821                               (i * sizeof(u32))),
6822                               be32_to_cpu(info->fw_data[i]));
6823
6824         err = 0;
6825
6826 out:
6827         return err;
6828 }
6829
6830 /* tp->lock is held. */
6831 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
6832 {
6833         struct fw_info info;
6834         const __be32 *fw_data;
6835         int err, i;
6836
6837         fw_data = (void *)tp->fw->data;
6838
6839         /* Firmware blob starts with version numbers, followed by
6840            start address and length. We are setting complete length.
6841            length = end_address_of_bss - start_address_of_text.
6842            Remainder is the blob to be loaded contiguously
6843            from start address. */
6844
6845         info.fw_base = be32_to_cpu(fw_data[1]);
6846         info.fw_len = tp->fw->size - 12;
6847         info.fw_data = &fw_data[3];
6848
6849         err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
6850                                     RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
6851                                     &info);
6852         if (err)
6853                 return err;
6854
6855         err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
6856                                     TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
6857                                     &info);
6858         if (err)
6859                 return err;
6860
6861         /* Now startup only the RX cpu. */
6862         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6863         tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
6864
6865         for (i = 0; i < 5; i++) {
6866                 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
6867                         break;
6868                 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6869                 tw32(RX_CPU_BASE + CPU_MODE,  CPU_MODE_HALT);
6870                 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
6871                 udelay(1000);
6872         }
6873         if (i >= 5) {
6874                 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
6875                        "to set RX CPU PC, is %08x should be %08x\n",
6876                        tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
6877                        info.fw_base);
6878                 return -ENODEV;
6879         }
6880         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6881         tw32_f(RX_CPU_BASE + CPU_MODE,  0x00000000);
6882
6883         return 0;
6884 }
6885
6886 /* 5705 needs a special version of the TSO firmware.  */
6887
6888 /* tp->lock is held. */
6889 static int tg3_load_tso_firmware(struct tg3 *tp)
6890 {
6891         struct fw_info info;
6892         const __be32 *fw_data;
6893         unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
6894         int err, i;
6895
6896         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6897                 return 0;
6898
6899         fw_data = (void *)tp->fw->data;
6900
6901         /* Firmware blob starts with version numbers, followed by
6902            start address and length. We are setting complete length.
6903            length = end_address_of_bss - start_address_of_text.
6904            Remainder is the blob to be loaded contiguously
6905            from start address. */
6906
6907         info.fw_base = be32_to_cpu(fw_data[1]);
6908         cpu_scratch_size = tp->fw_len;
6909         info.fw_len = tp->fw->size - 12;
6910         info.fw_data = &fw_data[3];
6911
6912         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6913                 cpu_base = RX_CPU_BASE;
6914                 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
6915         } else {
6916                 cpu_base = TX_CPU_BASE;
6917                 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
6918                 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
6919         }
6920
6921         err = tg3_load_firmware_cpu(tp, cpu_base,
6922                                     cpu_scratch_base, cpu_scratch_size,
6923                                     &info);
6924         if (err)
6925                 return err;
6926
6927         /* Now startup the cpu. */
6928         tw32(cpu_base + CPU_STATE, 0xffffffff);
6929         tw32_f(cpu_base + CPU_PC, info.fw_base);
6930
6931         for (i = 0; i < 5; i++) {
6932                 if (tr32(cpu_base + CPU_PC) == info.fw_base)
6933                         break;
6934                 tw32(cpu_base + CPU_STATE, 0xffffffff);
6935                 tw32(cpu_base + CPU_MODE,  CPU_MODE_HALT);
6936                 tw32_f(cpu_base + CPU_PC, info.fw_base);
6937                 udelay(1000);
6938         }
6939         if (i >= 5) {
6940                 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
6941                        "to set CPU PC, is %08x should be %08x\n",
6942                        tp->dev->name, tr32(cpu_base + CPU_PC),
6943                        info.fw_base);
6944                 return -ENODEV;
6945         }
6946         tw32(cpu_base + CPU_STATE, 0xffffffff);
6947         tw32_f(cpu_base + CPU_MODE,  0x00000000);
6948         return 0;
6949 }
6950
6951
6952 static int tg3_set_mac_addr(struct net_device *dev, void *p)
6953 {
6954         struct tg3 *tp = netdev_priv(dev);
6955         struct sockaddr *addr = p;
6956         int err = 0, skip_mac_1 = 0;
6957
6958         if (!is_valid_ether_addr(addr->sa_data))
6959                 return -EINVAL;
6960
6961         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
6962
6963         if (!netif_running(dev))
6964                 return 0;
6965
6966         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6967                 u32 addr0_high, addr0_low, addr1_high, addr1_low;
6968
6969                 addr0_high = tr32(MAC_ADDR_0_HIGH);
6970                 addr0_low = tr32(MAC_ADDR_0_LOW);
6971                 addr1_high = tr32(MAC_ADDR_1_HIGH);
6972                 addr1_low = tr32(MAC_ADDR_1_LOW);
6973
6974                 /* Skip MAC addr 1 if ASF is using it. */
6975                 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
6976                     !(addr1_high == 0 && addr1_low == 0))
6977                         skip_mac_1 = 1;
6978         }
6979         spin_lock_bh(&tp->lock);
6980         __tg3_set_mac_addr(tp, skip_mac_1);
6981         spin_unlock_bh(&tp->lock);
6982
6983         return err;
6984 }
6985
6986 /* tp->lock is held. */
6987 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
6988                            dma_addr_t mapping, u32 maxlen_flags,
6989                            u32 nic_addr)
6990 {
6991         tg3_write_mem(tp,
6992                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
6993                       ((u64) mapping >> 32));
6994         tg3_write_mem(tp,
6995                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
6996                       ((u64) mapping & 0xffffffff));
6997         tg3_write_mem(tp,
6998                       (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
6999                        maxlen_flags);
7000
7001         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7002                 tg3_write_mem(tp,
7003                               (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
7004                               nic_addr);
7005 }
7006
7007 static void __tg3_set_rx_mode(struct net_device *);
7008 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
7009 {
7010         int i;
7011
7012         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
7013                 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
7014                 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
7015                 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
7016
7017                 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
7018                 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
7019                 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
7020         } else {
7021                 tw32(HOSTCC_TXCOL_TICKS, 0);
7022                 tw32(HOSTCC_TXMAX_FRAMES, 0);
7023                 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
7024
7025                 tw32(HOSTCC_RXCOL_TICKS, 0);
7026                 tw32(HOSTCC_RXMAX_FRAMES, 0);
7027                 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
7028         }
7029
7030         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7031                 u32 val = ec->stats_block_coalesce_usecs;
7032
7033                 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
7034                 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
7035
7036                 if (!netif_carrier_ok(tp->dev))
7037                         val = 0;
7038
7039                 tw32(HOSTCC_STAT_COAL_TICKS, val);
7040         }
7041
7042         for (i = 0; i < tp->irq_cnt - 1; i++) {
7043                 u32 reg;
7044
7045                 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
7046                 tw32(reg, ec->rx_coalesce_usecs);
7047                 reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
7048                 tw32(reg, ec->tx_coalesce_usecs);
7049                 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
7050                 tw32(reg, ec->rx_max_coalesced_frames);
7051                 reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
7052                 tw32(reg, ec->tx_max_coalesced_frames);
7053                 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
7054                 tw32(reg, ec->rx_max_coalesced_frames_irq);
7055                 reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
7056                 tw32(reg, ec->tx_max_coalesced_frames_irq);
7057         }
7058
7059         for (; i < tp->irq_max - 1; i++) {
7060                 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
7061                 tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
7062                 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
7063                 tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
7064                 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7065                 tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7066         }
7067 }
7068
7069 /* tp->lock is held. */
7070 static void tg3_rings_reset(struct tg3 *tp)
7071 {
7072         int i;
7073         u32 stblk, txrcb, rxrcb, limit;
7074         struct tg3_napi *tnapi = &tp->napi[0];
7075
7076         /* Disable all transmit rings but the first. */
7077         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7078                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
7079         else
7080                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7081
7082         for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7083              txrcb < limit; txrcb += TG3_BDINFO_SIZE)
7084                 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
7085                               BDINFO_FLAGS_DISABLED);
7086
7087
7088         /* Disable all receive return rings but the first. */
7089         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
7090                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
7091         else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7092                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
7093         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
7094                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
7095         else
7096                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7097
7098         for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7099              rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
7100                 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
7101                               BDINFO_FLAGS_DISABLED);
7102
7103         /* Disable interrupts */
7104         tw32_mailbox_f(tp->napi[0].int_mbox, 1);
7105
7106         /* Zero mailbox registers. */
7107         if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) {
7108                 for (i = 1; i < TG3_IRQ_MAX_VECS; i++) {
7109                         tp->napi[i].tx_prod = 0;
7110                         tp->napi[i].tx_cons = 0;
7111                         tw32_mailbox(tp->napi[i].prodmbox, 0);
7112                         tw32_rx_mbox(tp->napi[i].consmbox, 0);
7113                         tw32_mailbox_f(tp->napi[i].int_mbox, 1);
7114                 }
7115         } else {
7116                 tp->napi[0].tx_prod = 0;
7117                 tp->napi[0].tx_cons = 0;
7118                 tw32_mailbox(tp->napi[0].prodmbox, 0);
7119                 tw32_rx_mbox(tp->napi[0].consmbox, 0);
7120         }
7121
7122         /* Make sure the NIC-based send BD rings are disabled. */
7123         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7124                 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
7125                 for (i = 0; i < 16; i++)
7126                         tw32_tx_mbox(mbox + i * 8, 0);
7127         }
7128
7129         txrcb = NIC_SRAM_SEND_RCB;
7130         rxrcb = NIC_SRAM_RCV_RET_RCB;
7131
7132         /* Clear status block in ram. */
7133         memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7134
7135         /* Set status block DMA address */
7136         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7137              ((u64) tnapi->status_mapping >> 32));
7138         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7139              ((u64) tnapi->status_mapping & 0xffffffff));
7140
7141         if (tnapi->tx_ring) {
7142                 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7143                                (TG3_TX_RING_SIZE <<
7144                                 BDINFO_FLAGS_MAXLEN_SHIFT),
7145                                NIC_SRAM_TX_BUFFER_DESC);
7146                 txrcb += TG3_BDINFO_SIZE;
7147         }
7148
7149         if (tnapi->rx_rcb) {
7150                 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7151                                (TG3_RX_RCB_RING_SIZE(tp) <<
7152                                 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7153                 rxrcb += TG3_BDINFO_SIZE;
7154         }
7155
7156         stblk = HOSTCC_STATBLCK_RING1;
7157
7158         for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
7159                 u64 mapping = (u64)tnapi->status_mapping;
7160                 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
7161                 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
7162
7163                 /* Clear status block in ram. */
7164                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7165
7166                 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7167                                (TG3_TX_RING_SIZE <<
7168                                 BDINFO_FLAGS_MAXLEN_SHIFT),
7169                                NIC_SRAM_TX_BUFFER_DESC);
7170
7171                 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7172                                (TG3_RX_RCB_RING_SIZE(tp) <<
7173                                 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7174
7175                 stblk += 8;
7176                 txrcb += TG3_BDINFO_SIZE;
7177                 rxrcb += TG3_BDINFO_SIZE;
7178         }
7179 }
7180
7181 /* tp->lock is held. */
7182 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
7183 {
7184         u32 val, rdmac_mode;
7185         int i, err, limit;
7186         struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
7187
7188         tg3_disable_ints(tp);
7189
7190         tg3_stop_fw(tp);
7191
7192         tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
7193
7194         if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
7195                 tg3_abort_hw(tp, 1);
7196         }
7197
7198         if (reset_phy &&
7199             !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB))
7200                 tg3_phy_reset(tp);
7201
7202         err = tg3_chip_reset(tp);
7203         if (err)
7204                 return err;
7205
7206         tg3_write_sig_legacy(tp, RESET_KIND_INIT);
7207
7208         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
7209                 val = tr32(TG3_CPMU_CTRL);
7210                 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
7211                 tw32(TG3_CPMU_CTRL, val);
7212
7213                 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7214                 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7215                 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7216                 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7217
7218                 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
7219                 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
7220                 val |= CPMU_LNK_AWARE_MACCLK_6_25;
7221                 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
7222
7223                 val = tr32(TG3_CPMU_HST_ACC);
7224                 val &= ~CPMU_HST_ACC_MACCLK_MASK;
7225                 val |= CPMU_HST_ACC_MACCLK_6_25;
7226                 tw32(TG3_CPMU_HST_ACC, val);
7227         }
7228
7229         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7230                 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
7231                 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
7232                        PCIE_PWR_MGMT_L1_THRESH_4MS;
7233                 tw32(PCIE_PWR_MGMT_THRESH, val);
7234
7235                 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
7236                 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
7237
7238                 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
7239
7240                 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
7241                 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
7242         }
7243
7244         /* This works around an issue with Athlon chipsets on
7245          * B3 tigon3 silicon.  This bit has no effect on any
7246          * other revision.  But do not set this on PCI Express
7247          * chips and don't even touch the clocks if the CPMU is present.
7248          */
7249         if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
7250                 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
7251                         tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
7252                 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7253         }
7254
7255         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
7256             (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
7257                 val = tr32(TG3PCI_PCISTATE);
7258                 val |= PCISTATE_RETRY_SAME_DMA;
7259                 tw32(TG3PCI_PCISTATE, val);
7260         }
7261
7262         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
7263                 /* Allow reads and writes to the
7264                  * APE register and memory space.
7265                  */
7266                 val = tr32(TG3PCI_PCISTATE);
7267                 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
7268                        PCISTATE_ALLOW_APE_SHMEM_WR;
7269                 tw32(TG3PCI_PCISTATE, val);
7270         }
7271
7272         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
7273                 /* Enable some hw fixes.  */
7274                 val = tr32(TG3PCI_MSI_DATA);
7275                 val |= (1 << 26) | (1 << 28) | (1 << 29);
7276                 tw32(TG3PCI_MSI_DATA, val);
7277         }
7278
7279         /* Descriptor ring init may make accesses to the
7280          * NIC SRAM area to setup the TX descriptors, so we
7281          * can only do this after the hardware has been
7282          * successfully reset.
7283          */
7284         err = tg3_init_rings(tp);
7285         if (err)
7286                 return err;
7287
7288         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
7289             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761 &&
7290             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) {
7291                 /* This value is determined during the probe time DMA
7292                  * engine test, tg3_test_dma.
7293                  */
7294                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
7295         }
7296
7297         tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
7298                           GRC_MODE_4X_NIC_SEND_RINGS |
7299                           GRC_MODE_NO_TX_PHDR_CSUM |
7300                           GRC_MODE_NO_RX_PHDR_CSUM);
7301         tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
7302
7303         /* Pseudo-header checksum is done by hardware logic and not
7304          * the offload processers, so make the chip do the pseudo-
7305          * header checksums on receive.  For transmit it is more
7306          * convenient to do the pseudo-header checksum in software
7307          * as Linux does that on transmit for us in all cases.
7308          */
7309         tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
7310
7311         tw32(GRC_MODE,
7312              tp->grc_mode |
7313              (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
7314
7315         /* Setup the timer prescalar register.  Clock is always 66Mhz. */
7316         val = tr32(GRC_MISC_CFG);
7317         val &= ~0xff;
7318         val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
7319         tw32(GRC_MISC_CFG, val);
7320
7321         /* Initialize MBUF/DESC pool. */
7322         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7323                 /* Do nothing.  */
7324         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
7325                 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
7326                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
7327                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
7328                 else
7329                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
7330                 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
7331                 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
7332         }
7333         else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7334                 int fw_len;
7335
7336                 fw_len = tp->fw_len;
7337                 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
7338                 tw32(BUFMGR_MB_POOL_ADDR,
7339                      NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
7340                 tw32(BUFMGR_MB_POOL_SIZE,
7341                      NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
7342         }
7343
7344         if (tp->dev->mtu <= ETH_DATA_LEN) {
7345                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7346                      tp->bufmgr_config.mbuf_read_dma_low_water);
7347                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7348                      tp->bufmgr_config.mbuf_mac_rx_low_water);
7349                 tw32(BUFMGR_MB_HIGH_WATER,
7350                      tp->bufmgr_config.mbuf_high_water);
7351         } else {
7352                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7353                      tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
7354                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7355                      tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
7356                 tw32(BUFMGR_MB_HIGH_WATER,
7357                      tp->bufmgr_config.mbuf_high_water_jumbo);
7358         }
7359         tw32(BUFMGR_DMA_LOW_WATER,
7360              tp->bufmgr_config.dma_low_water);
7361         tw32(BUFMGR_DMA_HIGH_WATER,
7362              tp->bufmgr_config.dma_high_water);
7363
7364         tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
7365         for (i = 0; i < 2000; i++) {
7366                 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
7367                         break;
7368                 udelay(10);
7369         }
7370         if (i >= 2000) {
7371                 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
7372                        tp->dev->name);
7373                 return -ENODEV;
7374         }
7375
7376         /* Setup replenish threshold. */
7377         val = tp->rx_pending / 8;
7378         if (val == 0)
7379                 val = 1;
7380         else if (val > tp->rx_std_max_post)
7381                 val = tp->rx_std_max_post;
7382         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7383                 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
7384                         tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
7385
7386                 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
7387                         val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
7388         }
7389
7390         tw32(RCVBDI_STD_THRESH, val);
7391
7392         /* Initialize TG3_BDINFO's at:
7393          *  RCVDBDI_STD_BD:     standard eth size rx ring
7394          *  RCVDBDI_JUMBO_BD:   jumbo frame rx ring
7395          *  RCVDBDI_MINI_BD:    small frame rx ring (??? does not work)
7396          *
7397          * like so:
7398          *  TG3_BDINFO_HOST_ADDR:       high/low parts of DMA address of ring
7399          *  TG3_BDINFO_MAXLEN_FLAGS:    (rx max buffer size << 16) |
7400          *                              ring attribute flags
7401          *  TG3_BDINFO_NIC_ADDR:        location of descriptors in nic SRAM
7402          *
7403          * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
7404          * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
7405          *
7406          * The size of each ring is fixed in the firmware, but the location is
7407          * configurable.
7408          */
7409         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7410              ((u64) tpr->rx_std_mapping >> 32));
7411         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7412              ((u64) tpr->rx_std_mapping & 0xffffffff));
7413         if (!(tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
7414                 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
7415                      NIC_SRAM_RX_BUFFER_DESC);
7416
7417         /* Disable the mini ring */
7418         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7419                 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
7420                      BDINFO_FLAGS_DISABLED);
7421
7422         /* Program the jumbo buffer descriptor ring control
7423          * blocks on those devices that have them.
7424          */
7425         if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
7426             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
7427                 /* Setup replenish threshold. */
7428                 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
7429
7430                 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
7431                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7432                              ((u64) tpr->rx_jmb_mapping >> 32));
7433                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7434                              ((u64) tpr->rx_jmb_mapping & 0xffffffff));
7435                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7436                              (RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT) |
7437                              BDINFO_FLAGS_USE_EXT_RECV);
7438                         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7439                                 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
7440                                      NIC_SRAM_RX_JUMBO_BUFFER_DESC);
7441                 } else {
7442                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7443                              BDINFO_FLAGS_DISABLED);
7444                 }
7445
7446                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
7447                         val = (RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT) |
7448                               (RX_STD_MAX_SIZE << 2);
7449                 else
7450                         val = RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT;
7451         } else
7452                 val = RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT;
7453
7454         tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
7455
7456         tpr->rx_std_ptr = tp->rx_pending;
7457         tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
7458                      tpr->rx_std_ptr);
7459
7460         tpr->rx_jmb_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
7461                           tp->rx_jumbo_pending : 0;
7462         tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
7463                      tpr->rx_jmb_ptr);
7464
7465         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
7466                 tw32(STD_REPLENISH_LWM, 32);
7467                 tw32(JMB_REPLENISH_LWM, 16);
7468         }
7469
7470         tg3_rings_reset(tp);
7471
7472         /* Initialize MAC address and backoff seed. */
7473         __tg3_set_mac_addr(tp, 0);
7474
7475         /* MTU + ethernet header + FCS + optional VLAN tag */
7476         tw32(MAC_RX_MTU_SIZE,
7477              tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
7478
7479         /* The slot time is changed by tg3_setup_phy if we
7480          * run at gigabit with half duplex.
7481          */
7482         tw32(MAC_TX_LENGTHS,
7483              (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
7484              (6 << TX_LENGTHS_IPG_SHIFT) |
7485              (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
7486
7487         /* Receive rules. */
7488         tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
7489         tw32(RCVLPC_CONFIG, 0x0181);
7490
7491         /* Calculate RDMAC_MODE setting early, we need it to determine
7492          * the RCVLPC_STATE_ENABLE mask.
7493          */
7494         rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
7495                       RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
7496                       RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
7497                       RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
7498                       RDMAC_MODE_LNGREAD_ENAB);
7499
7500         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
7501             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7502             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7503                 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
7504                               RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
7505                               RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
7506
7507         /* If statement applies to 5705 and 5750 PCI devices only */
7508         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7509              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7510             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
7511                 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
7512                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7513                         rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
7514                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7515                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
7516                         rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7517                 }
7518         }
7519
7520         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
7521                 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7522
7523         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7524                 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
7525
7526         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
7527             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7528             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7529                 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
7530
7531         /* Receive/send statistics. */
7532         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7533                 val = tr32(RCVLPC_STATS_ENABLE);
7534                 val &= ~RCVLPC_STATSENAB_DACK_FIX;
7535                 tw32(RCVLPC_STATS_ENABLE, val);
7536         } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
7537                    (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
7538                 val = tr32(RCVLPC_STATS_ENABLE);
7539                 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
7540                 tw32(RCVLPC_STATS_ENABLE, val);
7541         } else {
7542                 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
7543         }
7544         tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
7545         tw32(SNDDATAI_STATSENAB, 0xffffff);
7546         tw32(SNDDATAI_STATSCTRL,
7547              (SNDDATAI_SCTRL_ENABLE |
7548               SNDDATAI_SCTRL_FASTUPD));
7549
7550         /* Setup host coalescing engine. */
7551         tw32(HOSTCC_MODE, 0);
7552         for (i = 0; i < 2000; i++) {
7553                 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
7554                         break;
7555                 udelay(10);
7556         }
7557
7558         __tg3_set_coalesce(tp, &tp->coal);
7559
7560         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7561                 /* Status/statistics block address.  See tg3_timer,
7562                  * the tg3_periodic_fetch_stats call there, and
7563                  * tg3_get_stats to see how this works for 5705/5750 chips.
7564                  */
7565                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7566                      ((u64) tp->stats_mapping >> 32));
7567                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7568                      ((u64) tp->stats_mapping & 0xffffffff));
7569                 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
7570
7571                 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
7572
7573                 /* Clear statistics and status block memory areas */
7574                 for (i = NIC_SRAM_STATS_BLK;
7575                      i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
7576                      i += sizeof(u32)) {
7577                         tg3_write_mem(tp, i, 0);
7578                         udelay(40);
7579                 }
7580         }
7581
7582         tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
7583
7584         tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
7585         tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
7586         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7587                 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
7588
7589         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
7590                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
7591                 /* reset to prevent losing 1st rx packet intermittently */
7592                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7593                 udelay(10);
7594         }
7595
7596         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7597                 tp->mac_mode &= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
7598         else
7599                 tp->mac_mode = 0;
7600         tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
7601                 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
7602         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7603             !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7604             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
7605                 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
7606         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
7607         udelay(40);
7608
7609         /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
7610          * If TG3_FLG2_IS_NIC is zero, we should read the
7611          * register to preserve the GPIO settings for LOMs. The GPIOs,
7612          * whether used as inputs or outputs, are set by boot code after
7613          * reset.
7614          */
7615         if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
7616                 u32 gpio_mask;
7617
7618                 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
7619                             GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
7620                             GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
7621
7622                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
7623                         gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
7624                                      GRC_LCLCTRL_GPIO_OUTPUT3;
7625
7626                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
7627                         gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
7628
7629                 tp->grc_local_ctrl &= ~gpio_mask;
7630                 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
7631
7632                 /* GPIO1 must be driven high for eeprom write protect */
7633                 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
7634                         tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
7635                                                GRC_LCLCTRL_GPIO_OUTPUT1);
7636         }
7637         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7638         udelay(100);
7639
7640         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX) {
7641                 val = tr32(MSGINT_MODE);
7642                 val |= MSGINT_MODE_MULTIVEC_EN | MSGINT_MODE_ENABLE;
7643                 tw32(MSGINT_MODE, val);
7644         }
7645
7646         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7647                 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
7648                 udelay(40);
7649         }
7650
7651         val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
7652                WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
7653                WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
7654                WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
7655                WDMAC_MODE_LNGREAD_ENAB);
7656
7657         /* If statement applies to 5705 and 5750 PCI devices only */
7658         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7659              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7660             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
7661                 if ((tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
7662                     (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
7663                      tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
7664                         /* nothing */
7665                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7666                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
7667                            !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
7668                         val |= WDMAC_MODE_RX_ACCEL;
7669                 }
7670         }
7671
7672         /* Enable host coalescing bug fix */
7673         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
7674                 val |= WDMAC_MODE_STATUS_TAG_FIX;
7675
7676         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
7677                 val |= WDMAC_MODE_BURST_ALL_DATA;
7678
7679         tw32_f(WDMAC_MODE, val);
7680         udelay(40);
7681
7682         if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
7683                 u16 pcix_cmd;
7684
7685                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7686                                      &pcix_cmd);
7687                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
7688                         pcix_cmd &= ~PCI_X_CMD_MAX_READ;
7689                         pcix_cmd |= PCI_X_CMD_READ_2K;
7690                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
7691                         pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
7692                         pcix_cmd |= PCI_X_CMD_READ_2K;
7693                 }
7694                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7695                                       pcix_cmd);
7696         }
7697
7698         tw32_f(RDMAC_MODE, rdmac_mode);
7699         udelay(40);
7700
7701         tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
7702         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7703                 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
7704
7705         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
7706                 tw32(SNDDATAC_MODE,
7707                      SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
7708         else
7709                 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
7710
7711         tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
7712         tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
7713         tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
7714         tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
7715         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7716                 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
7717         val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
7718         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
7719                 val |= SNDBDI_MODE_MULTI_TXQ_EN;
7720         tw32(SNDBDI_MODE, val);
7721         tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
7722
7723         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
7724                 err = tg3_load_5701_a0_firmware_fix(tp);
7725                 if (err)
7726                         return err;
7727         }
7728
7729         if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7730                 err = tg3_load_tso_firmware(tp);
7731                 if (err)
7732                         return err;
7733         }
7734
7735         tp->tx_mode = TX_MODE_ENABLE;
7736         tw32_f(MAC_TX_MODE, tp->tx_mode);
7737         udelay(100);
7738
7739         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) {
7740                 u32 reg = MAC_RSS_INDIR_TBL_0;
7741                 u8 *ent = (u8 *)&val;
7742
7743                 /* Setup the indirection table */
7744                 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
7745                         int idx = i % sizeof(val);
7746
7747                         ent[idx] = i % (tp->irq_cnt - 1);
7748                         if (idx == sizeof(val) - 1) {
7749                                 tw32(reg, val);
7750                                 reg += 4;
7751                         }
7752                 }
7753
7754                 /* Setup the "secret" hash key. */
7755                 tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
7756                 tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
7757                 tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
7758                 tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
7759                 tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
7760                 tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
7761                 tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
7762                 tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
7763                 tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
7764                 tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
7765         }
7766
7767         tp->rx_mode = RX_MODE_ENABLE;
7768         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
7769                 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
7770
7771         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)
7772                 tp->rx_mode |= RX_MODE_RSS_ENABLE |
7773                                RX_MODE_RSS_ITBL_HASH_BITS_7 |
7774                                RX_MODE_RSS_IPV6_HASH_EN |
7775                                RX_MODE_RSS_TCP_IPV6_HASH_EN |
7776                                RX_MODE_RSS_IPV4_HASH_EN |
7777                                RX_MODE_RSS_TCP_IPV4_HASH_EN;
7778
7779         tw32_f(MAC_RX_MODE, tp->rx_mode);
7780         udelay(10);
7781
7782         tw32(MAC_LED_CTRL, tp->led_ctrl);
7783
7784         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
7785         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
7786                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7787                 udelay(10);
7788         }
7789         tw32_f(MAC_RX_MODE, tp->rx_mode);
7790         udelay(10);
7791
7792         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
7793                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
7794                         !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
7795                         /* Set drive transmission level to 1.2V  */
7796                         /* only if the signal pre-emphasis bit is not set  */
7797                         val = tr32(MAC_SERDES_CFG);
7798                         val &= 0xfffff000;
7799                         val |= 0x880;
7800                         tw32(MAC_SERDES_CFG, val);
7801                 }
7802                 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
7803                         tw32(MAC_SERDES_CFG, 0x616000);
7804         }
7805
7806         /* Prevent chip from dropping frames when flow control
7807          * is enabled.
7808          */
7809         tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
7810
7811         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
7812             (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
7813                 /* Use hardware link auto-negotiation */
7814                 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
7815         }
7816
7817         if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
7818             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
7819                 u32 tmp;
7820
7821                 tmp = tr32(SERDES_RX_CTRL);
7822                 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
7823                 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
7824                 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
7825                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7826         }
7827
7828         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
7829                 if (tp->link_config.phy_is_low_power) {
7830                         tp->link_config.phy_is_low_power = 0;
7831                         tp->link_config.speed = tp->link_config.orig_speed;
7832                         tp->link_config.duplex = tp->link_config.orig_duplex;
7833                         tp->link_config.autoneg = tp->link_config.orig_autoneg;
7834                 }
7835
7836                 err = tg3_setup_phy(tp, 0);
7837                 if (err)
7838                         return err;
7839
7840                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7841                     !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)) {
7842                         u32 tmp;
7843
7844                         /* Clear CRC stats. */
7845                         if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
7846                                 tg3_writephy(tp, MII_TG3_TEST1,
7847                                              tmp | MII_TG3_TEST1_CRC_EN);
7848                                 tg3_readphy(tp, 0x14, &tmp);
7849                         }
7850                 }
7851         }
7852
7853         __tg3_set_rx_mode(tp->dev);
7854
7855         /* Initialize receive rules. */
7856         tw32(MAC_RCV_RULE_0,  0xc2000000 & RCV_RULE_DISABLE_MASK);
7857         tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
7858         tw32(MAC_RCV_RULE_1,  0x86000004 & RCV_RULE_DISABLE_MASK);
7859         tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
7860
7861         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7862             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
7863                 limit = 8;
7864         else
7865                 limit = 16;
7866         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
7867                 limit -= 4;
7868         switch (limit) {
7869         case 16:
7870                 tw32(MAC_RCV_RULE_15,  0); tw32(MAC_RCV_VALUE_15,  0);
7871         case 15:
7872                 tw32(MAC_RCV_RULE_14,  0); tw32(MAC_RCV_VALUE_14,  0);
7873         case 14:
7874                 tw32(MAC_RCV_RULE_13,  0); tw32(MAC_RCV_VALUE_13,  0);
7875         case 13:
7876                 tw32(MAC_RCV_RULE_12,  0); tw32(MAC_RCV_VALUE_12,  0);
7877         case 12:
7878                 tw32(MAC_RCV_RULE_11,  0); tw32(MAC_RCV_VALUE_11,  0);
7879         case 11:
7880                 tw32(MAC_RCV_RULE_10,  0); tw32(MAC_RCV_VALUE_10,  0);
7881         case 10:
7882                 tw32(MAC_RCV_RULE_9,  0); tw32(MAC_RCV_VALUE_9,  0);
7883         case 9:
7884                 tw32(MAC_RCV_RULE_8,  0); tw32(MAC_RCV_VALUE_8,  0);
7885         case 8:
7886                 tw32(MAC_RCV_RULE_7,  0); tw32(MAC_RCV_VALUE_7,  0);
7887         case 7:
7888                 tw32(MAC_RCV_RULE_6,  0); tw32(MAC_RCV_VALUE_6,  0);
7889         case 6:
7890                 tw32(MAC_RCV_RULE_5,  0); tw32(MAC_RCV_VALUE_5,  0);
7891         case 5:
7892                 tw32(MAC_RCV_RULE_4,  0); tw32(MAC_RCV_VALUE_4,  0);
7893         case 4:
7894                 /* tw32(MAC_RCV_RULE_3,  0); tw32(MAC_RCV_VALUE_3,  0); */
7895         case 3:
7896                 /* tw32(MAC_RCV_RULE_2,  0); tw32(MAC_RCV_VALUE_2,  0); */
7897         case 2:
7898         case 1:
7899
7900         default:
7901                 break;
7902         }
7903
7904         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7905                 /* Write our heartbeat update interval to APE. */
7906                 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
7907                                 APE_HOST_HEARTBEAT_INT_DISABLE);
7908
7909         tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
7910
7911         return 0;
7912 }
7913
7914 /* Called at device open time to get the chip ready for
7915  * packet processing.  Invoked with tp->lock held.
7916  */
7917 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
7918 {
7919         tg3_switch_clocks(tp);
7920
7921         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
7922
7923         return tg3_reset_hw(tp, reset_phy);
7924 }
7925
7926 #define TG3_STAT_ADD32(PSTAT, REG) \
7927 do {    u32 __val = tr32(REG); \
7928         (PSTAT)->low += __val; \
7929         if ((PSTAT)->low < __val) \
7930                 (PSTAT)->high += 1; \
7931 } while (0)
7932
7933 static void tg3_periodic_fetch_stats(struct tg3 *tp)
7934 {
7935         struct tg3_hw_stats *sp = tp->hw_stats;
7936
7937         if (!netif_carrier_ok(tp->dev))
7938                 return;
7939
7940         TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
7941         TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
7942         TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
7943         TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
7944         TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
7945         TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
7946         TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
7947         TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
7948         TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
7949         TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
7950         TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
7951         TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
7952         TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
7953
7954         TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
7955         TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
7956         TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
7957         TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
7958         TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
7959         TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
7960         TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
7961         TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
7962         TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
7963         TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
7964         TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
7965         TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
7966         TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
7967         TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
7968
7969         TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
7970         TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
7971         TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
7972 }
7973
7974 static void tg3_timer(unsigned long __opaque)
7975 {
7976         struct tg3 *tp = (struct tg3 *) __opaque;
7977
7978         if (tp->irq_sync)
7979                 goto restart_timer;
7980
7981         spin_lock(&tp->lock);
7982
7983         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
7984                 /* All of this garbage is because when using non-tagged
7985                  * IRQ status the mailbox/status_block protocol the chip
7986                  * uses with the cpu is race prone.
7987                  */
7988                 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
7989                         tw32(GRC_LOCAL_CTRL,
7990                              tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
7991                 } else {
7992                         tw32(HOSTCC_MODE, tp->coalesce_mode |
7993                              HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
7994                 }
7995
7996                 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
7997                         tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
7998                         spin_unlock(&tp->lock);
7999                         schedule_work(&tp->reset_task);
8000                         return;
8001                 }
8002         }
8003
8004         /* This part only runs once per second. */
8005         if (!--tp->timer_counter) {
8006                 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
8007                         tg3_periodic_fetch_stats(tp);
8008
8009                 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
8010                         u32 mac_stat;
8011                         int phy_event;
8012
8013                         mac_stat = tr32(MAC_STATUS);
8014
8015                         phy_event = 0;
8016                         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
8017                                 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
8018                                         phy_event = 1;
8019                         } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
8020                                 phy_event = 1;
8021
8022                         if (phy_event)
8023                                 tg3_setup_phy(tp, 0);
8024                 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
8025                         u32 mac_stat = tr32(MAC_STATUS);
8026                         int need_setup = 0;
8027
8028                         if (netif_carrier_ok(tp->dev) &&
8029                             (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
8030                                 need_setup = 1;
8031                         }
8032                         if (! netif_carrier_ok(tp->dev) &&
8033                             (mac_stat & (MAC_STATUS_PCS_SYNCED |
8034                                          MAC_STATUS_SIGNAL_DET))) {
8035                                 need_setup = 1;
8036                         }
8037                         if (need_setup) {
8038                                 if (!tp->serdes_counter) {
8039                                         tw32_f(MAC_MODE,
8040                                              (tp->mac_mode &
8041                                               ~MAC_MODE_PORT_MODE_MASK));
8042                                         udelay(40);
8043                                         tw32_f(MAC_MODE, tp->mac_mode);
8044                                         udelay(40);
8045                                 }
8046                                 tg3_setup_phy(tp, 0);
8047                         }
8048                 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
8049                         tg3_serdes_parallel_detect(tp);
8050
8051                 tp->timer_counter = tp->timer_multiplier;
8052         }
8053
8054         /* Heartbeat is only sent once every 2 seconds.
8055          *
8056          * The heartbeat is to tell the ASF firmware that the host
8057          * driver is still alive.  In the event that the OS crashes,
8058          * ASF needs to reset the hardware to free up the FIFO space
8059          * that may be filled with rx packets destined for the host.
8060          * If the FIFO is full, ASF will no longer function properly.
8061          *
8062          * Unintended resets have been reported on real time kernels
8063          * where the timer doesn't run on time.  Netpoll will also have
8064          * same problem.
8065          *
8066          * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
8067          * to check the ring condition when the heartbeat is expiring
8068          * before doing the reset.  This will prevent most unintended
8069          * resets.
8070          */
8071         if (!--tp->asf_counter) {
8072                 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
8073                     !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
8074                         tg3_wait_for_event_ack(tp);
8075
8076                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
8077                                       FWCMD_NICDRV_ALIVE3);
8078                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
8079                         /* 5 seconds timeout */
8080                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
8081
8082                         tg3_generate_fw_event(tp);
8083                 }
8084                 tp->asf_counter = tp->asf_multiplier;
8085         }
8086
8087         spin_unlock(&tp->lock);
8088
8089 restart_timer:
8090         tp->timer.expires = jiffies + tp->timer_offset;
8091         add_timer(&tp->timer);
8092 }
8093
8094 static int tg3_request_irq(struct tg3 *tp, int irq_num)
8095 {
8096         irq_handler_t fn;
8097         unsigned long flags;
8098         char *name;
8099         struct tg3_napi *tnapi = &tp->napi[irq_num];
8100
8101         if (tp->irq_cnt == 1)
8102                 name = tp->dev->name;
8103         else {
8104                 name = &tnapi->irq_lbl[0];
8105                 snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num);
8106                 name[IFNAMSIZ-1] = 0;
8107         }
8108
8109         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8110                 fn = tg3_msi;
8111                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
8112                         fn = tg3_msi_1shot;
8113                 flags = IRQF_SAMPLE_RANDOM;
8114         } else {
8115                 fn = tg3_interrupt;
8116                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8117                         fn = tg3_interrupt_tagged;
8118                 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
8119         }
8120
8121         return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
8122 }
8123
8124 static int tg3_test_interrupt(struct tg3 *tp)
8125 {
8126         struct tg3_napi *tnapi = &tp->napi[0];
8127         struct net_device *dev = tp->dev;
8128         int err, i, intr_ok = 0;
8129         u32 val;
8130
8131         if (!netif_running(dev))
8132                 return -ENODEV;
8133
8134         tg3_disable_ints(tp);
8135
8136         free_irq(tnapi->irq_vec, tnapi);
8137
8138         /*
8139          * Turn off MSI one shot mode.  Otherwise this test has no
8140          * observable way to know whether the interrupt was delivered.
8141          */
8142         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
8143             (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8144                 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
8145                 tw32(MSGINT_MODE, val);
8146         }
8147
8148         err = request_irq(tnapi->irq_vec, tg3_test_isr,
8149                           IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi);
8150         if (err)
8151                 return err;
8152
8153         tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
8154         tg3_enable_ints(tp);
8155
8156         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8157                tnapi->coal_now);
8158
8159         for (i = 0; i < 5; i++) {
8160                 u32 int_mbox, misc_host_ctrl;
8161
8162                 int_mbox = tr32_mailbox(tnapi->int_mbox);
8163                 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
8164
8165                 if ((int_mbox != 0) ||
8166                     (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
8167                         intr_ok = 1;
8168                         break;
8169                 }
8170
8171                 msleep(10);
8172         }
8173
8174         tg3_disable_ints(tp);
8175
8176         free_irq(tnapi->irq_vec, tnapi);
8177
8178         err = tg3_request_irq(tp, 0);
8179
8180         if (err)
8181                 return err;
8182
8183         if (intr_ok) {
8184                 /* Reenable MSI one shot mode. */
8185                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
8186                     (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8187                         val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
8188                         tw32(MSGINT_MODE, val);
8189                 }
8190                 return 0;
8191         }
8192
8193         return -EIO;
8194 }
8195
8196 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
8197  * successfully restored
8198  */
8199 static int tg3_test_msi(struct tg3 *tp)
8200 {
8201         int err;
8202         u16 pci_cmd;
8203
8204         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
8205                 return 0;
8206
8207         /* Turn off SERR reporting in case MSI terminates with Master
8208          * Abort.
8209          */
8210         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
8211         pci_write_config_word(tp->pdev, PCI_COMMAND,
8212                               pci_cmd & ~PCI_COMMAND_SERR);
8213
8214         err = tg3_test_interrupt(tp);
8215
8216         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
8217
8218         if (!err)
8219                 return 0;
8220
8221         /* other failures */
8222         if (err != -EIO)
8223                 return err;
8224
8225         /* MSI test failed, go back to INTx mode */
8226         printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
8227                "switching to INTx mode. Please report this failure to "
8228                "the PCI maintainer and include system chipset information.\n",
8229                        tp->dev->name);
8230
8231         free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8232
8233         pci_disable_msi(tp->pdev);
8234
8235         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8236
8237         err = tg3_request_irq(tp, 0);
8238         if (err)
8239                 return err;
8240
8241         /* Need to reset the chip because the MSI cycle may have terminated
8242          * with Master Abort.
8243          */
8244         tg3_full_lock(tp, 1);
8245
8246         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8247         err = tg3_init_hw(tp, 1);
8248
8249         tg3_full_unlock(tp);
8250
8251         if (err)
8252                 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8253
8254         return err;
8255 }
8256
8257 static int tg3_request_firmware(struct tg3 *tp)
8258 {
8259         const __be32 *fw_data;
8260
8261         if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
8262                 printk(KERN_ERR "%s: Failed to load firmware \"%s\"\n",
8263                        tp->dev->name, tp->fw_needed);
8264                 return -ENOENT;
8265         }
8266
8267         fw_data = (void *)tp->fw->data;
8268
8269         /* Firmware blob starts with version numbers, followed by
8270          * start address and _full_ length including BSS sections
8271          * (which must be longer than the actual data, of course
8272          */
8273
8274         tp->fw_len = be32_to_cpu(fw_data[2]);   /* includes bss */
8275         if (tp->fw_len < (tp->fw->size - 12)) {
8276                 printk(KERN_ERR "%s: bogus length %d in \"%s\"\n",
8277                        tp->dev->name, tp->fw_len, tp->fw_needed);
8278                 release_firmware(tp->fw);
8279                 tp->fw = NULL;
8280                 return -EINVAL;
8281         }
8282
8283         /* We no longer need firmware; we have it. */
8284         tp->fw_needed = NULL;
8285         return 0;
8286 }
8287
8288 static bool tg3_enable_msix(struct tg3 *tp)
8289 {
8290         int i, rc, cpus = num_online_cpus();
8291         struct msix_entry msix_ent[tp->irq_max];
8292
8293         if (cpus == 1)
8294                 /* Just fallback to the simpler MSI mode. */
8295                 return false;
8296
8297         /*
8298          * We want as many rx rings enabled as there are cpus.
8299          * The first MSIX vector only deals with link interrupts, etc,
8300          * so we add one to the number of vectors we are requesting.
8301          */
8302         tp->irq_cnt = min_t(unsigned, cpus + 1, tp->irq_max);
8303
8304         for (i = 0; i < tp->irq_max; i++) {
8305                 msix_ent[i].entry  = i;
8306                 msix_ent[i].vector = 0;
8307         }
8308
8309         rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
8310         if (rc != 0) {
8311                 if (rc < TG3_RSS_MIN_NUM_MSIX_VECS)
8312                         return false;
8313                 if (pci_enable_msix(tp->pdev, msix_ent, rc))
8314                         return false;
8315                 printk(KERN_NOTICE
8316                        "%s: Requested %d MSI-X vectors, received %d\n",
8317                        tp->dev->name, tp->irq_cnt, rc);
8318                 tp->irq_cnt = rc;
8319         }
8320
8321         tp->tg3_flags3 |= TG3_FLG3_ENABLE_RSS;
8322
8323         for (i = 0; i < tp->irq_max; i++)
8324                 tp->napi[i].irq_vec = msix_ent[i].vector;
8325
8326         tp->dev->real_num_tx_queues = tp->irq_cnt - 1;
8327
8328         return true;
8329 }
8330
8331 static void tg3_ints_init(struct tg3 *tp)
8332 {
8333         if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI_OR_MSIX) &&
8334             !(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8335                 /* All MSI supporting chips should support tagged
8336                  * status.  Assert that this is the case.
8337                  */
8338                 printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
8339                        "Not using MSI.\n", tp->dev->name);
8340                 goto defcfg;
8341         }
8342
8343         if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) && tg3_enable_msix(tp))
8344                 tp->tg3_flags2 |= TG3_FLG2_USING_MSIX;
8345         else if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) &&
8346                  pci_enable_msi(tp->pdev) == 0)
8347                 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
8348
8349         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8350                 u32 msi_mode = tr32(MSGINT_MODE);
8351                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8352                         msi_mode |= MSGINT_MODE_MULTIVEC_EN;
8353                 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
8354         }
8355 defcfg:
8356         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
8357                 tp->irq_cnt = 1;
8358                 tp->napi[0].irq_vec = tp->pdev->irq;
8359                 tp->dev->real_num_tx_queues = 1;
8360         }
8361 }
8362
8363 static void tg3_ints_fini(struct tg3 *tp)
8364 {
8365         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8366                 pci_disable_msix(tp->pdev);
8367         else if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
8368                 pci_disable_msi(tp->pdev);
8369         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI_OR_MSIX;
8370         tp->tg3_flags3 &= ~TG3_FLG3_ENABLE_RSS;
8371 }
8372
8373 static int tg3_open(struct net_device *dev)
8374 {
8375         struct tg3 *tp = netdev_priv(dev);
8376         int i, err;
8377
8378         if (tp->fw_needed) {
8379                 err = tg3_request_firmware(tp);
8380                 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8381                         if (err)
8382                                 return err;
8383                 } else if (err) {
8384                         printk(KERN_WARNING "%s: TSO capability disabled.\n",
8385                                tp->dev->name);
8386                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
8387                 } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8388                         printk(KERN_NOTICE "%s: TSO capability restored.\n",
8389                                tp->dev->name);
8390                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
8391                 }
8392         }
8393
8394         netif_carrier_off(tp->dev);
8395
8396         err = tg3_set_power_state(tp, PCI_D0);
8397         if (err)
8398                 return err;
8399
8400         tg3_full_lock(tp, 0);
8401
8402         tg3_disable_ints(tp);
8403         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
8404
8405         tg3_full_unlock(tp);
8406
8407         /*
8408          * Setup interrupts first so we know how
8409          * many NAPI resources to allocate
8410          */
8411         tg3_ints_init(tp);
8412
8413         /* The placement of this call is tied
8414          * to the setup and use of Host TX descriptors.
8415          */
8416         err = tg3_alloc_consistent(tp);
8417         if (err)
8418                 goto err_out1;
8419
8420         tg3_napi_enable(tp);
8421
8422         for (i = 0; i < tp->irq_cnt; i++) {
8423                 struct tg3_napi *tnapi = &tp->napi[i];
8424                 err = tg3_request_irq(tp, i);
8425                 if (err) {
8426                         for (i--; i >= 0; i--)
8427                                 free_irq(tnapi->irq_vec, tnapi);
8428                         break;
8429                 }
8430         }
8431
8432         if (err)
8433                 goto err_out2;
8434
8435         tg3_full_lock(tp, 0);
8436
8437         err = tg3_init_hw(tp, 1);
8438         if (err) {
8439                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8440                 tg3_free_rings(tp);
8441         } else {
8442                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8443                         tp->timer_offset = HZ;
8444                 else
8445                         tp->timer_offset = HZ / 10;
8446
8447                 BUG_ON(tp->timer_offset > HZ);
8448                 tp->timer_counter = tp->timer_multiplier =
8449                         (HZ / tp->timer_offset);
8450                 tp->asf_counter = tp->asf_multiplier =
8451                         ((HZ / tp->timer_offset) * 2);
8452
8453                 init_timer(&tp->timer);
8454                 tp->timer.expires = jiffies + tp->timer_offset;
8455                 tp->timer.data = (unsigned long) tp;
8456                 tp->timer.function = tg3_timer;
8457         }
8458
8459         tg3_full_unlock(tp);
8460
8461         if (err)
8462                 goto err_out3;
8463
8464         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8465                 err = tg3_test_msi(tp);
8466
8467                 if (err) {
8468                         tg3_full_lock(tp, 0);
8469                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8470                         tg3_free_rings(tp);
8471                         tg3_full_unlock(tp);
8472
8473                         goto err_out2;
8474                 }
8475
8476                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
8477                     (tp->tg3_flags2 & TG3_FLG2_USING_MSI) &&
8478                     (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)) {
8479                         u32 val = tr32(PCIE_TRANSACTION_CFG);
8480
8481                         tw32(PCIE_TRANSACTION_CFG,
8482                              val | PCIE_TRANS_CFG_1SHOT_MSI);
8483                 }
8484         }
8485
8486         tg3_phy_start(tp);
8487
8488         tg3_full_lock(tp, 0);
8489
8490         add_timer(&tp->timer);
8491         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
8492         tg3_enable_ints(tp);
8493
8494         tg3_full_unlock(tp);
8495
8496         netif_tx_start_all_queues(dev);
8497
8498         return 0;
8499
8500 err_out3:
8501         for (i = tp->irq_cnt - 1; i >= 0; i--) {
8502                 struct tg3_napi *tnapi = &tp->napi[i];
8503                 free_irq(tnapi->irq_vec, tnapi);
8504         }
8505
8506 err_out2:
8507         tg3_napi_disable(tp);
8508         tg3_free_consistent(tp);
8509
8510 err_out1:
8511         tg3_ints_fini(tp);
8512         return err;
8513 }
8514
8515 #if 0
8516 /*static*/ void tg3_dump_state(struct tg3 *tp)
8517 {
8518         u32 val32, val32_2, val32_3, val32_4, val32_5;
8519         u16 val16;
8520         int i;
8521         struct tg3_hw_status *sblk = tp->napi[0]->hw_status;
8522
8523         pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
8524         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
8525         printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
8526                val16, val32);
8527
8528         /* MAC block */
8529         printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
8530                tr32(MAC_MODE), tr32(MAC_STATUS));
8531         printk("       MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
8532                tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
8533         printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
8534                tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
8535         printk("       MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
8536                tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
8537
8538         /* Send data initiator control block */
8539         printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
8540                tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
8541         printk("       SNDDATAI_STATSCTRL[%08x]\n",
8542                tr32(SNDDATAI_STATSCTRL));
8543
8544         /* Send data completion control block */
8545         printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
8546
8547         /* Send BD ring selector block */
8548         printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
8549                tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
8550
8551         /* Send BD initiator control block */
8552         printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
8553                tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
8554
8555         /* Send BD completion control block */
8556         printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
8557
8558         /* Receive list placement control block */
8559         printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
8560                tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
8561         printk("       RCVLPC_STATSCTRL[%08x]\n",
8562                tr32(RCVLPC_STATSCTRL));
8563
8564         /* Receive data and receive BD initiator control block */
8565         printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
8566                tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
8567
8568         /* Receive data completion control block */
8569         printk("DEBUG: RCVDCC_MODE[%08x]\n",
8570                tr32(RCVDCC_MODE));
8571
8572         /* Receive BD initiator control block */
8573         printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
8574                tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
8575
8576         /* Receive BD completion control block */
8577         printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
8578                tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
8579
8580         /* Receive list selector control block */
8581         printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
8582                tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
8583
8584         /* Mbuf cluster free block */
8585         printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
8586                tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
8587
8588         /* Host coalescing control block */
8589         printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
8590                tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
8591         printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
8592                tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8593                tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8594         printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
8595                tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8596                tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8597         printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
8598                tr32(HOSTCC_STATS_BLK_NIC_ADDR));
8599         printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
8600                tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
8601
8602         /* Memory arbiter control block */
8603         printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
8604                tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
8605
8606         /* Buffer manager control block */
8607         printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
8608                tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
8609         printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
8610                tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
8611         printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
8612                "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
8613                tr32(BUFMGR_DMA_DESC_POOL_ADDR),
8614                tr32(BUFMGR_DMA_DESC_POOL_SIZE));
8615
8616         /* Read DMA control block */
8617         printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
8618                tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
8619
8620         /* Write DMA control block */
8621         printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
8622                tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
8623
8624         /* DMA completion block */
8625         printk("DEBUG: DMAC_MODE[%08x]\n",
8626                tr32(DMAC_MODE));
8627
8628         /* GRC block */
8629         printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
8630                tr32(GRC_MODE), tr32(GRC_MISC_CFG));
8631         printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
8632                tr32(GRC_LOCAL_CTRL));
8633
8634         /* TG3_BDINFOs */
8635         printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
8636                tr32(RCVDBDI_JUMBO_BD + 0x0),
8637                tr32(RCVDBDI_JUMBO_BD + 0x4),
8638                tr32(RCVDBDI_JUMBO_BD + 0x8),
8639                tr32(RCVDBDI_JUMBO_BD + 0xc));
8640         printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
8641                tr32(RCVDBDI_STD_BD + 0x0),
8642                tr32(RCVDBDI_STD_BD + 0x4),
8643                tr32(RCVDBDI_STD_BD + 0x8),
8644                tr32(RCVDBDI_STD_BD + 0xc));
8645         printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
8646                tr32(RCVDBDI_MINI_BD + 0x0),
8647                tr32(RCVDBDI_MINI_BD + 0x4),
8648                tr32(RCVDBDI_MINI_BD + 0x8),
8649                tr32(RCVDBDI_MINI_BD + 0xc));
8650
8651         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
8652         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
8653         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
8654         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
8655         printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
8656                val32, val32_2, val32_3, val32_4);
8657
8658         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
8659         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
8660         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
8661         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
8662         printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
8663                val32, val32_2, val32_3, val32_4);
8664
8665         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
8666         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
8667         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
8668         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
8669         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
8670         printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
8671                val32, val32_2, val32_3, val32_4, val32_5);
8672
8673         /* SW status block */
8674         printk(KERN_DEBUG
8675          "Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
8676                sblk->status,
8677                sblk->status_tag,
8678                sblk->rx_jumbo_consumer,
8679                sblk->rx_consumer,
8680                sblk->rx_mini_consumer,
8681                sblk->idx[0].rx_producer,
8682                sblk->idx[0].tx_consumer);
8683
8684         /* SW statistics block */
8685         printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
8686                ((u32 *)tp->hw_stats)[0],
8687                ((u32 *)tp->hw_stats)[1],
8688                ((u32 *)tp->hw_stats)[2],
8689                ((u32 *)tp->hw_stats)[3]);
8690
8691         /* Mailboxes */
8692         printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
8693                tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
8694                tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
8695                tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
8696                tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
8697
8698         /* NIC side send descriptors. */
8699         for (i = 0; i < 6; i++) {
8700                 unsigned long txd;
8701
8702                 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
8703                         + (i * sizeof(struct tg3_tx_buffer_desc));
8704                 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
8705                        i,
8706                        readl(txd + 0x0), readl(txd + 0x4),
8707                        readl(txd + 0x8), readl(txd + 0xc));
8708         }
8709
8710         /* NIC side RX descriptors. */
8711         for (i = 0; i < 6; i++) {
8712                 unsigned long rxd;
8713
8714                 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
8715                         + (i * sizeof(struct tg3_rx_buffer_desc));
8716                 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
8717                        i,
8718                        readl(rxd + 0x0), readl(rxd + 0x4),
8719                        readl(rxd + 0x8), readl(rxd + 0xc));
8720                 rxd += (4 * sizeof(u32));
8721                 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
8722                        i,
8723                        readl(rxd + 0x0), readl(rxd + 0x4),
8724                        readl(rxd + 0x8), readl(rxd + 0xc));
8725         }
8726
8727         for (i = 0; i < 6; i++) {
8728                 unsigned long rxd;
8729
8730                 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
8731                         + (i * sizeof(struct tg3_rx_buffer_desc));
8732                 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
8733                        i,
8734                        readl(rxd + 0x0), readl(rxd + 0x4),
8735                        readl(rxd + 0x8), readl(rxd + 0xc));
8736                 rxd += (4 * sizeof(u32));
8737                 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
8738                        i,
8739                        readl(rxd + 0x0), readl(rxd + 0x4),
8740                        readl(rxd + 0x8), readl(rxd + 0xc));
8741         }
8742 }
8743 #endif
8744
8745 static struct net_device_stats *tg3_get_stats(struct net_device *);
8746 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
8747
8748 static int tg3_close(struct net_device *dev)
8749 {
8750         int i;
8751         struct tg3 *tp = netdev_priv(dev);
8752
8753         tg3_napi_disable(tp);
8754         cancel_work_sync(&tp->reset_task);
8755
8756         netif_tx_stop_all_queues(dev);
8757
8758         del_timer_sync(&tp->timer);
8759
8760         tg3_phy_stop(tp);
8761
8762         tg3_full_lock(tp, 1);
8763 #if 0
8764         tg3_dump_state(tp);
8765 #endif
8766
8767         tg3_disable_ints(tp);
8768
8769         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8770         tg3_free_rings(tp);
8771         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
8772
8773         tg3_full_unlock(tp);
8774
8775         for (i = tp->irq_cnt - 1; i >= 0; i--) {
8776                 struct tg3_napi *tnapi = &tp->napi[i];
8777                 free_irq(tnapi->irq_vec, tnapi);
8778         }
8779
8780         tg3_ints_fini(tp);
8781
8782         memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
8783                sizeof(tp->net_stats_prev));
8784         memcpy(&tp->estats_prev, tg3_get_estats(tp),
8785                sizeof(tp->estats_prev));
8786
8787         tg3_free_consistent(tp);
8788
8789         tg3_set_power_state(tp, PCI_D3hot);
8790
8791         netif_carrier_off(tp->dev);
8792
8793         return 0;
8794 }
8795
8796 static inline unsigned long get_stat64(tg3_stat64_t *val)
8797 {
8798         unsigned long ret;
8799
8800 #if (BITS_PER_LONG == 32)
8801         ret = val->low;
8802 #else
8803         ret = ((u64)val->high << 32) | ((u64)val->low);
8804 #endif
8805         return ret;
8806 }
8807
8808 static inline u64 get_estat64(tg3_stat64_t *val)
8809 {
8810        return ((u64)val->high << 32) | ((u64)val->low);
8811 }
8812
8813 static unsigned long calc_crc_errors(struct tg3 *tp)
8814 {
8815         struct tg3_hw_stats *hw_stats = tp->hw_stats;
8816
8817         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
8818             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
8819              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
8820                 u32 val;
8821
8822                 spin_lock_bh(&tp->lock);
8823                 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
8824                         tg3_writephy(tp, MII_TG3_TEST1,
8825                                      val | MII_TG3_TEST1_CRC_EN);
8826                         tg3_readphy(tp, 0x14, &val);
8827                 } else
8828                         val = 0;
8829                 spin_unlock_bh(&tp->lock);
8830
8831                 tp->phy_crc_errors += val;
8832
8833                 return tp->phy_crc_errors;
8834         }
8835
8836         return get_stat64(&hw_stats->rx_fcs_errors);
8837 }
8838
8839 #define ESTAT_ADD(member) \
8840         estats->member =        old_estats->member + \
8841                                 get_estat64(&hw_stats->member)
8842
8843 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
8844 {
8845         struct tg3_ethtool_stats *estats = &tp->estats;
8846         struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
8847         struct tg3_hw_stats *hw_stats = tp->hw_stats;
8848
8849         if (!hw_stats)
8850                 return old_estats;
8851
8852         ESTAT_ADD(rx_octets);
8853         ESTAT_ADD(rx_fragments);
8854         ESTAT_ADD(rx_ucast_packets);
8855         ESTAT_ADD(rx_mcast_packets);
8856         ESTAT_ADD(rx_bcast_packets);
8857         ESTAT_ADD(rx_fcs_errors);
8858         ESTAT_ADD(rx_align_errors);
8859         ESTAT_ADD(rx_xon_pause_rcvd);
8860         ESTAT_ADD(rx_xoff_pause_rcvd);
8861         ESTAT_ADD(rx_mac_ctrl_rcvd);
8862         ESTAT_ADD(rx_xoff_entered);
8863         ESTAT_ADD(rx_frame_too_long_errors);
8864         ESTAT_ADD(rx_jabbers);
8865         ESTAT_ADD(rx_undersize_packets);
8866         ESTAT_ADD(rx_in_length_errors);
8867         ESTAT_ADD(rx_out_length_errors);
8868         ESTAT_ADD(rx_64_or_less_octet_packets);
8869         ESTAT_ADD(rx_65_to_127_octet_packets);
8870         ESTAT_ADD(rx_128_to_255_octet_packets);
8871         ESTAT_ADD(rx_256_to_511_octet_packets);
8872         ESTAT_ADD(rx_512_to_1023_octet_packets);
8873         ESTAT_ADD(rx_1024_to_1522_octet_packets);
8874         ESTAT_ADD(rx_1523_to_2047_octet_packets);
8875         ESTAT_ADD(rx_2048_to_4095_octet_packets);
8876         ESTAT_ADD(rx_4096_to_8191_octet_packets);
8877         ESTAT_ADD(rx_8192_to_9022_octet_packets);
8878
8879         ESTAT_ADD(tx_octets);
8880         ESTAT_ADD(tx_collisions);
8881         ESTAT_ADD(tx_xon_sent);
8882         ESTAT_ADD(tx_xoff_sent);
8883         ESTAT_ADD(tx_flow_control);
8884         ESTAT_ADD(tx_mac_errors);
8885         ESTAT_ADD(tx_single_collisions);
8886         ESTAT_ADD(tx_mult_collisions);
8887         ESTAT_ADD(tx_deferred);
8888         ESTAT_ADD(tx_excessive_collisions);
8889         ESTAT_ADD(tx_late_collisions);
8890         ESTAT_ADD(tx_collide_2times);
8891         ESTAT_ADD(tx_collide_3times);
8892         ESTAT_ADD(tx_collide_4times);
8893         ESTAT_ADD(tx_collide_5times);
8894         ESTAT_ADD(tx_collide_6times);
8895         ESTAT_ADD(tx_collide_7times);
8896         ESTAT_ADD(tx_collide_8times);
8897         ESTAT_ADD(tx_collide_9times);
8898         ESTAT_ADD(tx_collide_10times);
8899         ESTAT_ADD(tx_collide_11times);
8900         ESTAT_ADD(tx_collide_12times);
8901         ESTAT_ADD(tx_collide_13times);
8902         ESTAT_ADD(tx_collide_14times);
8903         ESTAT_ADD(tx_collide_15times);
8904         ESTAT_ADD(tx_ucast_packets);
8905         ESTAT_ADD(tx_mcast_packets);
8906         ESTAT_ADD(tx_bcast_packets);
8907         ESTAT_ADD(tx_carrier_sense_errors);
8908         ESTAT_ADD(tx_discards);
8909         ESTAT_ADD(tx_errors);
8910
8911         ESTAT_ADD(dma_writeq_full);
8912         ESTAT_ADD(dma_write_prioq_full);
8913         ESTAT_ADD(rxbds_empty);
8914         ESTAT_ADD(rx_discards);
8915         ESTAT_ADD(rx_errors);
8916         ESTAT_ADD(rx_threshold_hit);
8917
8918         ESTAT_ADD(dma_readq_full);
8919         ESTAT_ADD(dma_read_prioq_full);
8920         ESTAT_ADD(tx_comp_queue_full);
8921
8922         ESTAT_ADD(ring_set_send_prod_index);
8923         ESTAT_ADD(ring_status_update);
8924         ESTAT_ADD(nic_irqs);
8925         ESTAT_ADD(nic_avoided_irqs);
8926         ESTAT_ADD(nic_tx_threshold_hit);
8927
8928         return estats;
8929 }
8930
8931 static struct net_device_stats *tg3_get_stats(struct net_device *dev)
8932 {
8933         struct tg3 *tp = netdev_priv(dev);
8934         struct net_device_stats *stats = &tp->net_stats;
8935         struct net_device_stats *old_stats = &tp->net_stats_prev;
8936         struct tg3_hw_stats *hw_stats = tp->hw_stats;
8937
8938         if (!hw_stats)
8939                 return old_stats;
8940
8941         stats->rx_packets = old_stats->rx_packets +
8942                 get_stat64(&hw_stats->rx_ucast_packets) +
8943                 get_stat64(&hw_stats->rx_mcast_packets) +
8944                 get_stat64(&hw_stats->rx_bcast_packets);
8945
8946         stats->tx_packets = old_stats->tx_packets +
8947                 get_stat64(&hw_stats->tx_ucast_packets) +
8948                 get_stat64(&hw_stats->tx_mcast_packets) +
8949                 get_stat64(&hw_stats->tx_bcast_packets);
8950
8951         stats->rx_bytes = old_stats->rx_bytes +
8952                 get_stat64(&hw_stats->rx_octets);
8953         stats->tx_bytes = old_stats->tx_bytes +
8954                 get_stat64(&hw_stats->tx_octets);
8955
8956         stats->rx_errors = old_stats->rx_errors +
8957                 get_stat64(&hw_stats->rx_errors);
8958         stats->tx_errors = old_stats->tx_errors +
8959                 get_stat64(&hw_stats->tx_errors) +
8960                 get_stat64(&hw_stats->tx_mac_errors) +
8961                 get_stat64(&hw_stats->tx_carrier_sense_errors) +
8962                 get_stat64(&hw_stats->tx_discards);
8963
8964         stats->multicast = old_stats->multicast +
8965                 get_stat64(&hw_stats->rx_mcast_packets);
8966         stats->collisions = old_stats->collisions +
8967                 get_stat64(&hw_stats->tx_collisions);
8968
8969         stats->rx_length_errors = old_stats->rx_length_errors +
8970                 get_stat64(&hw_stats->rx_frame_too_long_errors) +
8971                 get_stat64(&hw_stats->rx_undersize_packets);
8972
8973         stats->rx_over_errors = old_stats->rx_over_errors +
8974                 get_stat64(&hw_stats->rxbds_empty);
8975         stats->rx_frame_errors = old_stats->rx_frame_errors +
8976                 get_stat64(&hw_stats->rx_align_errors);
8977         stats->tx_aborted_errors = old_stats->tx_aborted_errors +
8978                 get_stat64(&hw_stats->tx_discards);
8979         stats->tx_carrier_errors = old_stats->tx_carrier_errors +
8980                 get_stat64(&hw_stats->tx_carrier_sense_errors);
8981
8982         stats->rx_crc_errors = old_stats->rx_crc_errors +
8983                 calc_crc_errors(tp);
8984
8985         stats->rx_missed_errors = old_stats->rx_missed_errors +
8986                 get_stat64(&hw_stats->rx_discards);
8987
8988         return stats;
8989 }
8990
8991 static inline u32 calc_crc(unsigned char *buf, int len)
8992 {
8993         u32 reg;
8994         u32 tmp;
8995         int j, k;
8996
8997         reg = 0xffffffff;
8998
8999         for (j = 0; j < len; j++) {
9000                 reg ^= buf[j];
9001
9002                 for (k = 0; k < 8; k++) {
9003                         tmp = reg & 0x01;
9004
9005                         reg >>= 1;
9006
9007                         if (tmp) {
9008                                 reg ^= 0xedb88320;
9009                         }
9010                 }
9011         }
9012
9013         return ~reg;
9014 }
9015
9016 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
9017 {
9018         /* accept or reject all multicast frames */
9019         tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
9020         tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
9021         tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
9022         tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
9023 }
9024
9025 static void __tg3_set_rx_mode(struct net_device *dev)
9026 {
9027         struct tg3 *tp = netdev_priv(dev);
9028         u32 rx_mode;
9029
9030         rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
9031                                   RX_MODE_KEEP_VLAN_TAG);
9032
9033         /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
9034          * flag clear.
9035          */
9036 #if TG3_VLAN_TAG_USED
9037         if (!tp->vlgrp &&
9038             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9039                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9040 #else
9041         /* By definition, VLAN is disabled always in this
9042          * case.
9043          */
9044         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9045                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9046 #endif
9047
9048         if (dev->flags & IFF_PROMISC) {
9049                 /* Promiscuous mode. */
9050                 rx_mode |= RX_MODE_PROMISC;
9051         } else if (dev->flags & IFF_ALLMULTI) {
9052                 /* Accept all multicast. */
9053                 tg3_set_multi (tp, 1);
9054         } else if (dev->mc_count < 1) {
9055                 /* Reject all multicast. */
9056                 tg3_set_multi (tp, 0);
9057         } else {
9058                 /* Accept one or more multicast(s). */
9059                 struct dev_mc_list *mclist;
9060                 unsigned int i;
9061                 u32 mc_filter[4] = { 0, };
9062                 u32 regidx;
9063                 u32 bit;
9064                 u32 crc;
9065
9066                 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
9067                      i++, mclist = mclist->next) {
9068
9069                         crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
9070                         bit = ~crc & 0x7f;
9071                         regidx = (bit & 0x60) >> 5;
9072                         bit &= 0x1f;
9073                         mc_filter[regidx] |= (1 << bit);
9074                 }
9075
9076                 tw32(MAC_HASH_REG_0, mc_filter[0]);
9077                 tw32(MAC_HASH_REG_1, mc_filter[1]);
9078                 tw32(MAC_HASH_REG_2, mc_filter[2]);
9079                 tw32(MAC_HASH_REG_3, mc_filter[3]);
9080         }
9081
9082         if (rx_mode != tp->rx_mode) {
9083                 tp->rx_mode = rx_mode;
9084                 tw32_f(MAC_RX_MODE, rx_mode);
9085                 udelay(10);
9086         }
9087 }
9088
9089 static void tg3_set_rx_mode(struct net_device *dev)
9090 {
9091         struct tg3 *tp = netdev_priv(dev);
9092
9093         if (!netif_running(dev))
9094                 return;
9095
9096         tg3_full_lock(tp, 0);
9097         __tg3_set_rx_mode(dev);
9098         tg3_full_unlock(tp);
9099 }
9100
9101 #define TG3_REGDUMP_LEN         (32 * 1024)
9102
9103 static int tg3_get_regs_len(struct net_device *dev)
9104 {
9105         return TG3_REGDUMP_LEN;
9106 }
9107
9108 static void tg3_get_regs(struct net_device *dev,
9109                 struct ethtool_regs *regs, void *_p)
9110 {
9111         u32 *p = _p;
9112         struct tg3 *tp = netdev_priv(dev);
9113         u8 *orig_p = _p;
9114         int i;
9115
9116         regs->version = 0;
9117
9118         memset(p, 0, TG3_REGDUMP_LEN);
9119
9120         if (tp->link_config.phy_is_low_power)
9121                 return;
9122
9123         tg3_full_lock(tp, 0);
9124
9125 #define __GET_REG32(reg)        (*(p)++ = tr32(reg))
9126 #define GET_REG32_LOOP(base,len)                \
9127 do {    p = (u32 *)(orig_p + (base));           \
9128         for (i = 0; i < len; i += 4)            \
9129                 __GET_REG32((base) + i);        \
9130 } while (0)
9131 #define GET_REG32_1(reg)                        \
9132 do {    p = (u32 *)(orig_p + (reg));            \
9133         __GET_REG32((reg));                     \
9134 } while (0)
9135
9136         GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
9137         GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
9138         GET_REG32_LOOP(MAC_MODE, 0x4f0);
9139         GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
9140         GET_REG32_1(SNDDATAC_MODE);
9141         GET_REG32_LOOP(SNDBDS_MODE, 0x80);
9142         GET_REG32_LOOP(SNDBDI_MODE, 0x48);
9143         GET_REG32_1(SNDBDC_MODE);
9144         GET_REG32_LOOP(RCVLPC_MODE, 0x20);
9145         GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
9146         GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
9147         GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
9148         GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
9149         GET_REG32_1(RCVDCC_MODE);
9150         GET_REG32_LOOP(RCVBDI_MODE, 0x20);
9151         GET_REG32_LOOP(RCVCC_MODE, 0x14);
9152         GET_REG32_LOOP(RCVLSC_MODE, 0x08);
9153         GET_REG32_1(MBFREE_MODE);
9154         GET_REG32_LOOP(HOSTCC_MODE, 0x100);
9155         GET_REG32_LOOP(MEMARB_MODE, 0x10);
9156         GET_REG32_LOOP(BUFMGR_MODE, 0x58);
9157         GET_REG32_LOOP(RDMAC_MODE, 0x08);
9158         GET_REG32_LOOP(WDMAC_MODE, 0x08);
9159         GET_REG32_1(RX_CPU_MODE);
9160         GET_REG32_1(RX_CPU_STATE);
9161         GET_REG32_1(RX_CPU_PGMCTR);
9162         GET_REG32_1(RX_CPU_HWBKPT);
9163         GET_REG32_1(TX_CPU_MODE);
9164         GET_REG32_1(TX_CPU_STATE);
9165         GET_REG32_1(TX_CPU_PGMCTR);
9166         GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
9167         GET_REG32_LOOP(FTQ_RESET, 0x120);
9168         GET_REG32_LOOP(MSGINT_MODE, 0x0c);
9169         GET_REG32_1(DMAC_MODE);
9170         GET_REG32_LOOP(GRC_MODE, 0x4c);
9171         if (tp->tg3_flags & TG3_FLAG_NVRAM)
9172                 GET_REG32_LOOP(NVRAM_CMD, 0x24);
9173
9174 #undef __GET_REG32
9175 #undef GET_REG32_LOOP
9176 #undef GET_REG32_1
9177
9178         tg3_full_unlock(tp);
9179 }
9180
9181 static int tg3_get_eeprom_len(struct net_device *dev)
9182 {
9183         struct tg3 *tp = netdev_priv(dev);
9184
9185         return tp->nvram_size;
9186 }
9187
9188 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9189 {
9190         struct tg3 *tp = netdev_priv(dev);
9191         int ret;
9192         u8  *pd;
9193         u32 i, offset, len, b_offset, b_count;
9194         __be32 val;
9195
9196         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9197                 return -EINVAL;
9198
9199         if (tp->link_config.phy_is_low_power)
9200                 return -EAGAIN;
9201
9202         offset = eeprom->offset;
9203         len = eeprom->len;
9204         eeprom->len = 0;
9205
9206         eeprom->magic = TG3_EEPROM_MAGIC;
9207
9208         if (offset & 3) {
9209                 /* adjustments to start on required 4 byte boundary */
9210                 b_offset = offset & 3;
9211                 b_count = 4 - b_offset;
9212                 if (b_count > len) {
9213                         /* i.e. offset=1 len=2 */
9214                         b_count = len;
9215                 }
9216                 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
9217                 if (ret)
9218                         return ret;
9219                 memcpy(data, ((char*)&val) + b_offset, b_count);
9220                 len -= b_count;
9221                 offset += b_count;
9222                 eeprom->len += b_count;
9223         }
9224
9225         /* read bytes upto the last 4 byte boundary */
9226         pd = &data[eeprom->len];
9227         for (i = 0; i < (len - (len & 3)); i += 4) {
9228                 ret = tg3_nvram_read_be32(tp, offset + i, &val);
9229                 if (ret) {
9230                         eeprom->len += i;
9231                         return ret;
9232                 }
9233                 memcpy(pd + i, &val, 4);
9234         }
9235         eeprom->len += i;
9236
9237         if (len & 3) {
9238                 /* read last bytes not ending on 4 byte boundary */
9239                 pd = &data[eeprom->len];
9240                 b_count = len & 3;
9241                 b_offset = offset + len - b_count;
9242                 ret = tg3_nvram_read_be32(tp, b_offset, &val);
9243                 if (ret)
9244                         return ret;
9245                 memcpy(pd, &val, b_count);
9246                 eeprom->len += b_count;
9247         }
9248         return 0;
9249 }
9250
9251 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
9252
9253 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9254 {
9255         struct tg3 *tp = netdev_priv(dev);
9256         int ret;
9257         u32 offset, len, b_offset, odd_len;
9258         u8 *buf;
9259         __be32 start, end;
9260
9261         if (tp->link_config.phy_is_low_power)
9262                 return -EAGAIN;
9263
9264         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
9265             eeprom->magic != TG3_EEPROM_MAGIC)
9266                 return -EINVAL;
9267
9268         offset = eeprom->offset;
9269         len = eeprom->len;
9270
9271         if ((b_offset = (offset & 3))) {
9272                 /* adjustments to start on required 4 byte boundary */
9273                 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
9274                 if (ret)
9275                         return ret;
9276                 len += b_offset;
9277                 offset &= ~3;
9278                 if (len < 4)
9279                         len = 4;
9280         }
9281
9282         odd_len = 0;
9283         if (len & 3) {
9284                 /* adjustments to end on required 4 byte boundary */
9285                 odd_len = 1;
9286                 len = (len + 3) & ~3;
9287                 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
9288                 if (ret)
9289                         return ret;
9290         }
9291
9292         buf = data;
9293         if (b_offset || odd_len) {
9294                 buf = kmalloc(len, GFP_KERNEL);
9295                 if (!buf)
9296                         return -ENOMEM;
9297                 if (b_offset)
9298                         memcpy(buf, &start, 4);
9299                 if (odd_len)
9300                         memcpy(buf+len-4, &end, 4);
9301                 memcpy(buf + b_offset, data, eeprom->len);
9302         }
9303
9304         ret = tg3_nvram_write_block(tp, offset, len, buf);
9305
9306         if (buf != data)
9307                 kfree(buf);
9308
9309         return ret;
9310 }
9311
9312 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9313 {
9314         struct tg3 *tp = netdev_priv(dev);
9315
9316         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9317                 struct phy_device *phydev;
9318                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9319                         return -EAGAIN;
9320                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9321                 return phy_ethtool_gset(phydev, cmd);
9322         }
9323
9324         cmd->supported = (SUPPORTED_Autoneg);
9325
9326         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
9327                 cmd->supported |= (SUPPORTED_1000baseT_Half |
9328                                    SUPPORTED_1000baseT_Full);
9329
9330         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
9331                 cmd->supported |= (SUPPORTED_100baseT_Half |
9332                                   SUPPORTED_100baseT_Full |
9333                                   SUPPORTED_10baseT_Half |
9334                                   SUPPORTED_10baseT_Full |
9335                                   SUPPORTED_TP);
9336                 cmd->port = PORT_TP;
9337         } else {
9338                 cmd->supported |= SUPPORTED_FIBRE;
9339                 cmd->port = PORT_FIBRE;
9340         }
9341
9342         cmd->advertising = tp->link_config.advertising;
9343         if (netif_running(dev)) {
9344                 cmd->speed = tp->link_config.active_speed;
9345                 cmd->duplex = tp->link_config.active_duplex;
9346         }
9347         cmd->phy_address = tp->phy_addr;
9348         cmd->transceiver = XCVR_INTERNAL;
9349         cmd->autoneg = tp->link_config.autoneg;
9350         cmd->maxtxpkt = 0;
9351         cmd->maxrxpkt = 0;
9352         return 0;
9353 }
9354
9355 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9356 {
9357         struct tg3 *tp = netdev_priv(dev);
9358
9359         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9360                 struct phy_device *phydev;
9361                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9362                         return -EAGAIN;
9363                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9364                 return phy_ethtool_sset(phydev, cmd);
9365         }
9366
9367         if (cmd->autoneg != AUTONEG_ENABLE &&
9368             cmd->autoneg != AUTONEG_DISABLE)
9369                 return -EINVAL;
9370
9371         if (cmd->autoneg == AUTONEG_DISABLE &&
9372             cmd->duplex != DUPLEX_FULL &&
9373             cmd->duplex != DUPLEX_HALF)
9374                 return -EINVAL;
9375
9376         if (cmd->autoneg == AUTONEG_ENABLE) {
9377                 u32 mask = ADVERTISED_Autoneg |
9378                            ADVERTISED_Pause |
9379                            ADVERTISED_Asym_Pause;
9380
9381                 if (!(tp->tg3_flags2 & TG3_FLAG_10_100_ONLY))
9382                         mask |= ADVERTISED_1000baseT_Half |
9383                                 ADVERTISED_1000baseT_Full;
9384
9385                 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
9386                         mask |= ADVERTISED_100baseT_Half |
9387                                 ADVERTISED_100baseT_Full |
9388                                 ADVERTISED_10baseT_Half |
9389                                 ADVERTISED_10baseT_Full |
9390                                 ADVERTISED_TP;
9391                 else
9392                         mask |= ADVERTISED_FIBRE;
9393
9394                 if (cmd->advertising & ~mask)
9395                         return -EINVAL;
9396
9397                 mask &= (ADVERTISED_1000baseT_Half |
9398                          ADVERTISED_1000baseT_Full |
9399                          ADVERTISED_100baseT_Half |
9400                          ADVERTISED_100baseT_Full |
9401                          ADVERTISED_10baseT_Half |
9402                          ADVERTISED_10baseT_Full);
9403
9404                 cmd->advertising &= mask;
9405         } else {
9406                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
9407                         if (cmd->speed != SPEED_1000)
9408                                 return -EINVAL;
9409
9410                         if (cmd->duplex != DUPLEX_FULL)
9411                                 return -EINVAL;
9412                 } else {
9413                         if (cmd->speed != SPEED_100 &&
9414                             cmd->speed != SPEED_10)
9415                                 return -EINVAL;
9416                 }
9417         }
9418
9419         tg3_full_lock(tp, 0);
9420
9421         tp->link_config.autoneg = cmd->autoneg;
9422         if (cmd->autoneg == AUTONEG_ENABLE) {
9423                 tp->link_config.advertising = (cmd->advertising |
9424                                               ADVERTISED_Autoneg);
9425                 tp->link_config.speed = SPEED_INVALID;
9426                 tp->link_config.duplex = DUPLEX_INVALID;
9427         } else {
9428                 tp->link_config.advertising = 0;
9429                 tp->link_config.speed = cmd->speed;
9430                 tp->link_config.duplex = cmd->duplex;
9431         }
9432
9433         tp->link_config.orig_speed = tp->link_config.speed;
9434         tp->link_config.orig_duplex = tp->link_config.duplex;
9435         tp->link_config.orig_autoneg = tp->link_config.autoneg;
9436
9437         if (netif_running(dev))
9438                 tg3_setup_phy(tp, 1);
9439
9440         tg3_full_unlock(tp);
9441
9442         return 0;
9443 }
9444
9445 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
9446 {
9447         struct tg3 *tp = netdev_priv(dev);
9448
9449         strcpy(info->driver, DRV_MODULE_NAME);
9450         strcpy(info->version, DRV_MODULE_VERSION);
9451         strcpy(info->fw_version, tp->fw_ver);
9452         strcpy(info->bus_info, pci_name(tp->pdev));
9453 }
9454
9455 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9456 {
9457         struct tg3 *tp = netdev_priv(dev);
9458
9459         if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
9460             device_can_wakeup(&tp->pdev->dev))
9461                 wol->supported = WAKE_MAGIC;
9462         else
9463                 wol->supported = 0;
9464         wol->wolopts = 0;
9465         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
9466             device_can_wakeup(&tp->pdev->dev))
9467                 wol->wolopts = WAKE_MAGIC;
9468         memset(&wol->sopass, 0, sizeof(wol->sopass));
9469 }
9470
9471 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9472 {
9473         struct tg3 *tp = netdev_priv(dev);
9474         struct device *dp = &tp->pdev->dev;
9475
9476         if (wol->wolopts & ~WAKE_MAGIC)
9477                 return -EINVAL;
9478         if ((wol->wolopts & WAKE_MAGIC) &&
9479             !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
9480                 return -EINVAL;
9481
9482         spin_lock_bh(&tp->lock);
9483         if (wol->wolopts & WAKE_MAGIC) {
9484                 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
9485                 device_set_wakeup_enable(dp, true);
9486         } else {
9487                 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
9488                 device_set_wakeup_enable(dp, false);
9489         }
9490         spin_unlock_bh(&tp->lock);
9491
9492         return 0;
9493 }
9494
9495 static u32 tg3_get_msglevel(struct net_device *dev)
9496 {
9497         struct tg3 *tp = netdev_priv(dev);
9498         return tp->msg_enable;
9499 }
9500
9501 static void tg3_set_msglevel(struct net_device *dev, u32 value)
9502 {
9503         struct tg3 *tp = netdev_priv(dev);
9504         tp->msg_enable = value;
9505 }
9506
9507 static int tg3_set_tso(struct net_device *dev, u32 value)
9508 {
9509         struct tg3 *tp = netdev_priv(dev);
9510
9511         if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
9512                 if (value)
9513                         return -EINVAL;
9514                 return 0;
9515         }
9516         if ((dev->features & NETIF_F_IPV6_CSUM) &&
9517             ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
9518              (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3))) {
9519                 if (value) {
9520                         dev->features |= NETIF_F_TSO6;
9521                         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
9522                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9523                             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
9524                              GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
9525                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
9526                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
9527                                 dev->features |= NETIF_F_TSO_ECN;
9528                 } else
9529                         dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
9530         }
9531         return ethtool_op_set_tso(dev, value);
9532 }
9533
9534 static int tg3_nway_reset(struct net_device *dev)
9535 {
9536         struct tg3 *tp = netdev_priv(dev);
9537         int r;
9538
9539         if (!netif_running(dev))
9540                 return -EAGAIN;
9541
9542         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9543                 return -EINVAL;
9544
9545         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9546                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9547                         return -EAGAIN;
9548                 r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
9549         } else {
9550                 u32 bmcr;
9551
9552                 spin_lock_bh(&tp->lock);
9553                 r = -EINVAL;
9554                 tg3_readphy(tp, MII_BMCR, &bmcr);
9555                 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
9556                     ((bmcr & BMCR_ANENABLE) ||
9557                      (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
9558                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
9559                                                    BMCR_ANENABLE);
9560                         r = 0;
9561                 }
9562                 spin_unlock_bh(&tp->lock);
9563         }
9564
9565         return r;
9566 }
9567
9568 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9569 {
9570         struct tg3 *tp = netdev_priv(dev);
9571
9572         ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
9573         ering->rx_mini_max_pending = 0;
9574         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9575                 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
9576         else
9577                 ering->rx_jumbo_max_pending = 0;
9578
9579         ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
9580
9581         ering->rx_pending = tp->rx_pending;
9582         ering->rx_mini_pending = 0;
9583         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9584                 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
9585         else
9586                 ering->rx_jumbo_pending = 0;
9587
9588         ering->tx_pending = tp->napi[0].tx_pending;
9589 }
9590
9591 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9592 {
9593         struct tg3 *tp = netdev_priv(dev);
9594         int i, irq_sync = 0, err = 0;
9595
9596         if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
9597             (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
9598             (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
9599             (ering->tx_pending <= MAX_SKB_FRAGS) ||
9600             ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
9601              (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
9602                 return -EINVAL;
9603
9604         if (netif_running(dev)) {
9605                 tg3_phy_stop(tp);
9606                 tg3_netif_stop(tp);
9607                 irq_sync = 1;
9608         }
9609
9610         tg3_full_lock(tp, irq_sync);
9611
9612         tp->rx_pending = ering->rx_pending;
9613
9614         if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
9615             tp->rx_pending > 63)
9616                 tp->rx_pending = 63;
9617         tp->rx_jumbo_pending = ering->rx_jumbo_pending;
9618
9619         for (i = 0; i < TG3_IRQ_MAX_VECS; i++)
9620                 tp->napi[i].tx_pending = ering->tx_pending;
9621
9622         if (netif_running(dev)) {
9623                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9624                 err = tg3_restart_hw(tp, 1);
9625                 if (!err)
9626                         tg3_netif_start(tp);
9627         }
9628
9629         tg3_full_unlock(tp);
9630
9631         if (irq_sync && !err)
9632                 tg3_phy_start(tp);
9633
9634         return err;
9635 }
9636
9637 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9638 {
9639         struct tg3 *tp = netdev_priv(dev);
9640
9641         epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
9642
9643         if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
9644                 epause->rx_pause = 1;
9645         else
9646                 epause->rx_pause = 0;
9647
9648         if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
9649                 epause->tx_pause = 1;
9650         else
9651                 epause->tx_pause = 0;
9652 }
9653
9654 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9655 {
9656         struct tg3 *tp = netdev_priv(dev);
9657         int err = 0;
9658
9659         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9660                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9661                         return -EAGAIN;
9662
9663                 if (epause->autoneg) {
9664                         u32 newadv;
9665                         struct phy_device *phydev;
9666
9667                         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9668
9669                         if (epause->rx_pause) {
9670                                 if (epause->tx_pause)
9671                                         newadv = ADVERTISED_Pause;
9672                                 else
9673                                         newadv = ADVERTISED_Pause |
9674                                                  ADVERTISED_Asym_Pause;
9675                         } else if (epause->tx_pause) {
9676                                 newadv = ADVERTISED_Asym_Pause;
9677                         } else
9678                                 newadv = 0;
9679
9680                         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
9681                                 u32 oldadv = phydev->advertising &
9682                                              (ADVERTISED_Pause |
9683                                               ADVERTISED_Asym_Pause);
9684                                 if (oldadv != newadv) {
9685                                         phydev->advertising &=
9686                                                 ~(ADVERTISED_Pause |
9687                                                   ADVERTISED_Asym_Pause);
9688                                         phydev->advertising |= newadv;
9689                                         err = phy_start_aneg(phydev);
9690                                 }
9691                         } else {
9692                                 tp->link_config.advertising &=
9693                                                 ~(ADVERTISED_Pause |
9694                                                   ADVERTISED_Asym_Pause);
9695                                 tp->link_config.advertising |= newadv;
9696                         }
9697                 } else {
9698                         if (epause->rx_pause)
9699                                 tp->link_config.flowctrl |= FLOW_CTRL_RX;
9700                         else
9701                                 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
9702
9703                         if (epause->tx_pause)
9704                                 tp->link_config.flowctrl |= FLOW_CTRL_TX;
9705                         else
9706                                 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
9707
9708                         if (netif_running(dev))
9709                                 tg3_setup_flow_control(tp, 0, 0);
9710                 }
9711         } else {
9712                 int irq_sync = 0;
9713
9714                 if (netif_running(dev)) {
9715                         tg3_netif_stop(tp);
9716                         irq_sync = 1;
9717                 }
9718
9719                 tg3_full_lock(tp, irq_sync);
9720
9721                 if (epause->autoneg)
9722                         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
9723                 else
9724                         tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
9725                 if (epause->rx_pause)
9726                         tp->link_config.flowctrl |= FLOW_CTRL_RX;
9727                 else
9728                         tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
9729                 if (epause->tx_pause)
9730                         tp->link_config.flowctrl |= FLOW_CTRL_TX;
9731                 else
9732                         tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
9733
9734                 if (netif_running(dev)) {
9735                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9736                         err = tg3_restart_hw(tp, 1);
9737                         if (!err)
9738                                 tg3_netif_start(tp);
9739                 }
9740
9741                 tg3_full_unlock(tp);
9742         }
9743
9744         return err;
9745 }
9746
9747 static u32 tg3_get_rx_csum(struct net_device *dev)
9748 {
9749         struct tg3 *tp = netdev_priv(dev);
9750         return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
9751 }
9752
9753 static int tg3_set_rx_csum(struct net_device *dev, u32 data)
9754 {
9755         struct tg3 *tp = netdev_priv(dev);
9756
9757         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
9758                 if (data != 0)
9759                         return -EINVAL;
9760                 return 0;
9761         }
9762
9763         spin_lock_bh(&tp->lock);
9764         if (data)
9765                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
9766         else
9767                 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
9768         spin_unlock_bh(&tp->lock);
9769
9770         return 0;
9771 }
9772
9773 static int tg3_set_tx_csum(struct net_device *dev, u32 data)
9774 {
9775         struct tg3 *tp = netdev_priv(dev);
9776
9777         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
9778                 if (data != 0)
9779                         return -EINVAL;
9780                 return 0;
9781         }
9782
9783         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
9784                 ethtool_op_set_tx_ipv6_csum(dev, data);
9785         else
9786                 ethtool_op_set_tx_csum(dev, data);
9787
9788         return 0;
9789 }
9790
9791 static int tg3_get_sset_count (struct net_device *dev, int sset)
9792 {
9793         switch (sset) {
9794         case ETH_SS_TEST:
9795                 return TG3_NUM_TEST;
9796         case ETH_SS_STATS:
9797                 return TG3_NUM_STATS;
9798         default:
9799                 return -EOPNOTSUPP;
9800         }
9801 }
9802
9803 static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
9804 {
9805         switch (stringset) {
9806         case ETH_SS_STATS:
9807                 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
9808                 break;
9809         case ETH_SS_TEST:
9810                 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
9811                 break;
9812         default:
9813                 WARN_ON(1);     /* we need a WARN() */
9814                 break;
9815         }
9816 }
9817
9818 static int tg3_phys_id(struct net_device *dev, u32 data)
9819 {
9820         struct tg3 *tp = netdev_priv(dev);
9821         int i;
9822
9823         if (!netif_running(tp->dev))
9824                 return -EAGAIN;
9825
9826         if (data == 0)
9827                 data = UINT_MAX / 2;
9828
9829         for (i = 0; i < (data * 2); i++) {
9830                 if ((i % 2) == 0)
9831                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
9832                                            LED_CTRL_1000MBPS_ON |
9833                                            LED_CTRL_100MBPS_ON |
9834                                            LED_CTRL_10MBPS_ON |
9835                                            LED_CTRL_TRAFFIC_OVERRIDE |
9836                                            LED_CTRL_TRAFFIC_BLINK |
9837                                            LED_CTRL_TRAFFIC_LED);
9838
9839                 else
9840                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
9841                                            LED_CTRL_TRAFFIC_OVERRIDE);
9842
9843                 if (msleep_interruptible(500))
9844                         break;
9845         }
9846         tw32(MAC_LED_CTRL, tp->led_ctrl);
9847         return 0;
9848 }
9849
9850 static void tg3_get_ethtool_stats (struct net_device *dev,
9851                                    struct ethtool_stats *estats, u64 *tmp_stats)
9852 {
9853         struct tg3 *tp = netdev_priv(dev);
9854         memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
9855 }
9856
9857 #define NVRAM_TEST_SIZE 0x100
9858 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE   0x14
9859 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE   0x18
9860 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE   0x1c
9861 #define NVRAM_SELFBOOT_HW_SIZE 0x20
9862 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
9863
9864 static int tg3_test_nvram(struct tg3 *tp)
9865 {
9866         u32 csum, magic;
9867         __be32 *buf;
9868         int i, j, k, err = 0, size;
9869
9870         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9871                 return 0;
9872
9873         if (tg3_nvram_read(tp, 0, &magic) != 0)
9874                 return -EIO;
9875
9876         if (magic == TG3_EEPROM_MAGIC)
9877                 size = NVRAM_TEST_SIZE;
9878         else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
9879                 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
9880                     TG3_EEPROM_SB_FORMAT_1) {
9881                         switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
9882                         case TG3_EEPROM_SB_REVISION_0:
9883                                 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
9884                                 break;
9885                         case TG3_EEPROM_SB_REVISION_2:
9886                                 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
9887                                 break;
9888                         case TG3_EEPROM_SB_REVISION_3:
9889                                 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
9890                                 break;
9891                         default:
9892                                 return 0;
9893                         }
9894                 } else
9895                         return 0;
9896         } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
9897                 size = NVRAM_SELFBOOT_HW_SIZE;
9898         else
9899                 return -EIO;
9900
9901         buf = kmalloc(size, GFP_KERNEL);
9902         if (buf == NULL)
9903                 return -ENOMEM;
9904
9905         err = -EIO;
9906         for (i = 0, j = 0; i < size; i += 4, j++) {
9907                 err = tg3_nvram_read_be32(tp, i, &buf[j]);
9908                 if (err)
9909                         break;
9910         }
9911         if (i < size)
9912                 goto out;
9913
9914         /* Selfboot format */
9915         magic = be32_to_cpu(buf[0]);
9916         if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
9917             TG3_EEPROM_MAGIC_FW) {
9918                 u8 *buf8 = (u8 *) buf, csum8 = 0;
9919
9920                 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
9921                     TG3_EEPROM_SB_REVISION_2) {
9922                         /* For rev 2, the csum doesn't include the MBA. */
9923                         for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
9924                                 csum8 += buf8[i];
9925                         for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
9926                                 csum8 += buf8[i];
9927                 } else {
9928                         for (i = 0; i < size; i++)
9929                                 csum8 += buf8[i];
9930                 }
9931
9932                 if (csum8 == 0) {
9933                         err = 0;
9934                         goto out;
9935                 }
9936
9937                 err = -EIO;
9938                 goto out;
9939         }
9940
9941         if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
9942             TG3_EEPROM_MAGIC_HW) {
9943                 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
9944                 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
9945                 u8 *buf8 = (u8 *) buf;
9946
9947                 /* Separate the parity bits and the data bytes.  */
9948                 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
9949                         if ((i == 0) || (i == 8)) {
9950                                 int l;
9951                                 u8 msk;
9952
9953                                 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
9954                                         parity[k++] = buf8[i] & msk;
9955                                 i++;
9956                         }
9957                         else if (i == 16) {
9958                                 int l;
9959                                 u8 msk;
9960
9961                                 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
9962                                         parity[k++] = buf8[i] & msk;
9963                                 i++;
9964
9965                                 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
9966                                         parity[k++] = buf8[i] & msk;
9967                                 i++;
9968                         }
9969                         data[j++] = buf8[i];
9970                 }
9971
9972                 err = -EIO;
9973                 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
9974                         u8 hw8 = hweight8(data[i]);
9975
9976                         if ((hw8 & 0x1) && parity[i])
9977                                 goto out;
9978                         else if (!(hw8 & 0x1) && !parity[i])
9979                                 goto out;
9980                 }
9981                 err = 0;
9982                 goto out;
9983         }
9984
9985         /* Bootstrap checksum at offset 0x10 */
9986         csum = calc_crc((unsigned char *) buf, 0x10);
9987         if (csum != be32_to_cpu(buf[0x10/4]))
9988                 goto out;
9989
9990         /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
9991         csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
9992         if (csum != be32_to_cpu(buf[0xfc/4]))
9993                 goto out;
9994
9995         err = 0;
9996
9997 out:
9998         kfree(buf);
9999         return err;
10000 }
10001
10002 #define TG3_SERDES_TIMEOUT_SEC  2
10003 #define TG3_COPPER_TIMEOUT_SEC  6
10004
10005 static int tg3_test_link(struct tg3 *tp)
10006 {
10007         int i, max;
10008
10009         if (!netif_running(tp->dev))
10010                 return -ENODEV;
10011
10012         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
10013                 max = TG3_SERDES_TIMEOUT_SEC;
10014         else
10015                 max = TG3_COPPER_TIMEOUT_SEC;
10016
10017         for (i = 0; i < max; i++) {
10018                 if (netif_carrier_ok(tp->dev))
10019                         return 0;
10020
10021                 if (msleep_interruptible(1000))
10022                         break;
10023         }
10024
10025         return -EIO;
10026 }
10027
10028 /* Only test the commonly used registers */
10029 static int tg3_test_registers(struct tg3 *tp)
10030 {
10031         int i, is_5705, is_5750;
10032         u32 offset, read_mask, write_mask, val, save_val, read_val;
10033         static struct {
10034                 u16 offset;
10035                 u16 flags;
10036 #define TG3_FL_5705     0x1
10037 #define TG3_FL_NOT_5705 0x2
10038 #define TG3_FL_NOT_5788 0x4
10039 #define TG3_FL_NOT_5750 0x8
10040                 u32 read_mask;
10041                 u32 write_mask;
10042         } reg_tbl[] = {
10043                 /* MAC Control Registers */
10044                 { MAC_MODE, TG3_FL_NOT_5705,
10045                         0x00000000, 0x00ef6f8c },
10046                 { MAC_MODE, TG3_FL_5705,
10047                         0x00000000, 0x01ef6b8c },
10048                 { MAC_STATUS, TG3_FL_NOT_5705,
10049                         0x03800107, 0x00000000 },
10050                 { MAC_STATUS, TG3_FL_5705,
10051                         0x03800100, 0x00000000 },
10052                 { MAC_ADDR_0_HIGH, 0x0000,
10053                         0x00000000, 0x0000ffff },
10054                 { MAC_ADDR_0_LOW, 0x0000,
10055                         0x00000000, 0xffffffff },
10056                 { MAC_RX_MTU_SIZE, 0x0000,
10057                         0x00000000, 0x0000ffff },
10058                 { MAC_TX_MODE, 0x0000,
10059                         0x00000000, 0x00000070 },
10060                 { MAC_TX_LENGTHS, 0x0000,
10061                         0x00000000, 0x00003fff },
10062                 { MAC_RX_MODE, TG3_FL_NOT_5705,
10063                         0x00000000, 0x000007fc },
10064                 { MAC_RX_MODE, TG3_FL_5705,
10065                         0x00000000, 0x000007dc },
10066                 { MAC_HASH_REG_0, 0x0000,
10067                         0x00000000, 0xffffffff },
10068                 { MAC_HASH_REG_1, 0x0000,
10069                         0x00000000, 0xffffffff },
10070                 { MAC_HASH_REG_2, 0x0000,
10071                         0x00000000, 0xffffffff },
10072                 { MAC_HASH_REG_3, 0x0000,
10073                         0x00000000, 0xffffffff },
10074
10075                 /* Receive Data and Receive BD Initiator Control Registers. */
10076                 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
10077                         0x00000000, 0xffffffff },
10078                 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
10079                         0x00000000, 0xffffffff },
10080                 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
10081                         0x00000000, 0x00000003 },
10082                 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
10083                         0x00000000, 0xffffffff },
10084                 { RCVDBDI_STD_BD+0, 0x0000,
10085                         0x00000000, 0xffffffff },
10086                 { RCVDBDI_STD_BD+4, 0x0000,
10087                         0x00000000, 0xffffffff },
10088                 { RCVDBDI_STD_BD+8, 0x0000,
10089                         0x00000000, 0xffff0002 },
10090                 { RCVDBDI_STD_BD+0xc, 0x0000,
10091                         0x00000000, 0xffffffff },
10092
10093                 /* Receive BD Initiator Control Registers. */
10094                 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
10095                         0x00000000, 0xffffffff },
10096                 { RCVBDI_STD_THRESH, TG3_FL_5705,
10097                         0x00000000, 0x000003ff },
10098                 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
10099                         0x00000000, 0xffffffff },
10100
10101                 /* Host Coalescing Control Registers. */
10102                 { HOSTCC_MODE, TG3_FL_NOT_5705,
10103                         0x00000000, 0x00000004 },
10104                 { HOSTCC_MODE, TG3_FL_5705,
10105                         0x00000000, 0x000000f6 },
10106                 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
10107                         0x00000000, 0xffffffff },
10108                 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
10109                         0x00000000, 0x000003ff },
10110                 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
10111                         0x00000000, 0xffffffff },
10112                 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
10113                         0x00000000, 0x000003ff },
10114                 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
10115                         0x00000000, 0xffffffff },
10116                 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10117                         0x00000000, 0x000000ff },
10118                 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
10119                         0x00000000, 0xffffffff },
10120                 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10121                         0x00000000, 0x000000ff },
10122                 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
10123                         0x00000000, 0xffffffff },
10124                 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
10125                         0x00000000, 0xffffffff },
10126                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10127                         0x00000000, 0xffffffff },
10128                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10129                         0x00000000, 0x000000ff },
10130                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10131                         0x00000000, 0xffffffff },
10132                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10133                         0x00000000, 0x000000ff },
10134                 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
10135                         0x00000000, 0xffffffff },
10136                 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
10137                         0x00000000, 0xffffffff },
10138                 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
10139                         0x00000000, 0xffffffff },
10140                 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
10141                         0x00000000, 0xffffffff },
10142                 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
10143                         0x00000000, 0xffffffff },
10144                 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
10145                         0xffffffff, 0x00000000 },
10146                 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
10147                         0xffffffff, 0x00000000 },
10148
10149                 /* Buffer Manager Control Registers. */
10150                 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
10151                         0x00000000, 0x007fff80 },
10152                 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
10153                         0x00000000, 0x007fffff },
10154                 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
10155                         0x00000000, 0x0000003f },
10156                 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
10157                         0x00000000, 0x000001ff },
10158                 { BUFMGR_MB_HIGH_WATER, 0x0000,
10159                         0x00000000, 0x000001ff },
10160                 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
10161                         0xffffffff, 0x00000000 },
10162                 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
10163                         0xffffffff, 0x00000000 },
10164
10165                 /* Mailbox Registers */
10166                 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
10167                         0x00000000, 0x000001ff },
10168                 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
10169                         0x00000000, 0x000001ff },
10170                 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
10171                         0x00000000, 0x000007ff },
10172                 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
10173                         0x00000000, 0x000001ff },
10174
10175                 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
10176         };
10177
10178         is_5705 = is_5750 = 0;
10179         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
10180                 is_5705 = 1;
10181                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10182                         is_5750 = 1;
10183         }
10184
10185         for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
10186                 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
10187                         continue;
10188
10189                 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
10190                         continue;
10191
10192                 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
10193                     (reg_tbl[i].flags & TG3_FL_NOT_5788))
10194                         continue;
10195
10196                 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
10197                         continue;
10198
10199                 offset = (u32) reg_tbl[i].offset;
10200                 read_mask = reg_tbl[i].read_mask;
10201                 write_mask = reg_tbl[i].write_mask;
10202
10203                 /* Save the original register content */
10204                 save_val = tr32(offset);
10205
10206                 /* Determine the read-only value. */
10207                 read_val = save_val & read_mask;
10208
10209                 /* Write zero to the register, then make sure the read-only bits
10210                  * are not changed and the read/write bits are all zeros.
10211                  */
10212                 tw32(offset, 0);
10213
10214                 val = tr32(offset);
10215
10216                 /* Test the read-only and read/write bits. */
10217                 if (((val & read_mask) != read_val) || (val & write_mask))
10218                         goto out;
10219
10220                 /* Write ones to all the bits defined by RdMask and WrMask, then
10221                  * make sure the read-only bits are not changed and the
10222                  * read/write bits are all ones.
10223                  */
10224                 tw32(offset, read_mask | write_mask);
10225
10226                 val = tr32(offset);
10227
10228                 /* Test the read-only bits. */
10229                 if ((val & read_mask) != read_val)
10230                         goto out;
10231
10232                 /* Test the read/write bits. */
10233                 if ((val & write_mask) != write_mask)
10234                         goto out;
10235
10236                 tw32(offset, save_val);
10237         }
10238
10239         return 0;
10240
10241 out:
10242         if (netif_msg_hw(tp))
10243                 printk(KERN_ERR PFX "Register test failed at offset %x\n",
10244                        offset);
10245         tw32(offset, save_val);
10246         return -EIO;
10247 }
10248
10249 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
10250 {
10251         static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
10252         int i;
10253         u32 j;
10254
10255         for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
10256                 for (j = 0; j < len; j += 4) {
10257                         u32 val;
10258
10259                         tg3_write_mem(tp, offset + j, test_pattern[i]);
10260                         tg3_read_mem(tp, offset + j, &val);
10261                         if (val != test_pattern[i])
10262                                 return -EIO;
10263                 }
10264         }
10265         return 0;
10266 }
10267
10268 static int tg3_test_memory(struct tg3 *tp)
10269 {
10270         static struct mem_entry {
10271                 u32 offset;
10272                 u32 len;
10273         } mem_tbl_570x[] = {
10274                 { 0x00000000, 0x00b50},
10275                 { 0x00002000, 0x1c000},
10276                 { 0xffffffff, 0x00000}
10277         }, mem_tbl_5705[] = {
10278                 { 0x00000100, 0x0000c},
10279                 { 0x00000200, 0x00008},
10280                 { 0x00004000, 0x00800},
10281                 { 0x00006000, 0x01000},
10282                 { 0x00008000, 0x02000},
10283                 { 0x00010000, 0x0e000},
10284                 { 0xffffffff, 0x00000}
10285         }, mem_tbl_5755[] = {
10286                 { 0x00000200, 0x00008},
10287                 { 0x00004000, 0x00800},
10288                 { 0x00006000, 0x00800},
10289                 { 0x00008000, 0x02000},
10290                 { 0x00010000, 0x0c000},
10291                 { 0xffffffff, 0x00000}
10292         }, mem_tbl_5906[] = {
10293                 { 0x00000200, 0x00008},
10294                 { 0x00004000, 0x00400},
10295                 { 0x00006000, 0x00400},
10296                 { 0x00008000, 0x01000},
10297                 { 0x00010000, 0x01000},
10298                 { 0xffffffff, 0x00000}
10299         };
10300         struct mem_entry *mem_tbl;
10301         int err = 0;
10302         int i;
10303
10304         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10305                 mem_tbl = mem_tbl_5755;
10306         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10307                 mem_tbl = mem_tbl_5906;
10308         else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
10309                 mem_tbl = mem_tbl_5705;
10310         else
10311                 mem_tbl = mem_tbl_570x;
10312
10313         for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
10314                 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
10315                     mem_tbl[i].len)) != 0)
10316                         break;
10317         }
10318
10319         return err;
10320 }
10321
10322 #define TG3_MAC_LOOPBACK        0
10323 #define TG3_PHY_LOOPBACK        1
10324
10325 static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
10326 {
10327         u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
10328         u32 desc_idx, coal_now;
10329         struct sk_buff *skb, *rx_skb;
10330         u8 *tx_data;
10331         dma_addr_t map;
10332         int num_pkts, tx_len, rx_len, i, err;
10333         struct tg3_rx_buffer_desc *desc;
10334         struct tg3_napi *tnapi, *rnapi;
10335         struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
10336
10337         if (tp->irq_cnt > 1) {
10338                 tnapi = &tp->napi[1];
10339                 rnapi = &tp->napi[1];
10340         } else {
10341                 tnapi = &tp->napi[0];
10342                 rnapi = &tp->napi[0];
10343         }
10344         coal_now = tnapi->coal_now | rnapi->coal_now;
10345
10346         if (loopback_mode == TG3_MAC_LOOPBACK) {
10347                 /* HW errata - mac loopback fails in some cases on 5780.
10348                  * Normal traffic and PHY loopback are not affected by
10349                  * errata.
10350                  */
10351                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
10352                         return 0;
10353
10354                 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
10355                            MAC_MODE_PORT_INT_LPBACK;
10356                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10357                         mac_mode |= MAC_MODE_LINK_POLARITY;
10358                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
10359                         mac_mode |= MAC_MODE_PORT_MODE_MII;
10360                 else
10361                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
10362                 tw32(MAC_MODE, mac_mode);
10363         } else if (loopback_mode == TG3_PHY_LOOPBACK) {
10364                 u32 val;
10365
10366                 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
10367                         tg3_phy_fet_toggle_apd(tp, false);
10368                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
10369                 } else
10370                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
10371
10372                 tg3_phy_toggle_automdix(tp, 0);
10373
10374                 tg3_writephy(tp, MII_BMCR, val);
10375                 udelay(40);
10376
10377                 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
10378                 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
10379                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10380                                 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x1800);
10381                         mac_mode |= MAC_MODE_PORT_MODE_MII;
10382                 } else
10383                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
10384
10385                 /* reset to prevent losing 1st rx packet intermittently */
10386                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
10387                         tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10388                         udelay(10);
10389                         tw32_f(MAC_RX_MODE, tp->rx_mode);
10390                 }
10391                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
10392                         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)
10393                                 mac_mode &= ~MAC_MODE_LINK_POLARITY;
10394                         else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411)
10395                                 mac_mode |= MAC_MODE_LINK_POLARITY;
10396                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
10397                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
10398                 }
10399                 tw32(MAC_MODE, mac_mode);
10400         }
10401         else
10402                 return -EINVAL;
10403
10404         err = -EIO;
10405
10406         tx_len = 1514;
10407         skb = netdev_alloc_skb(tp->dev, tx_len);
10408         if (!skb)
10409                 return -ENOMEM;
10410
10411         tx_data = skb_put(skb, tx_len);
10412         memcpy(tx_data, tp->dev->dev_addr, 6);
10413         memset(tx_data + 6, 0x0, 8);
10414
10415         tw32(MAC_RX_MTU_SIZE, tx_len + 4);
10416
10417         for (i = 14; i < tx_len; i++)
10418                 tx_data[i] = (u8) (i & 0xff);
10419
10420         if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
10421                 dev_kfree_skb(skb);
10422                 return -EIO;
10423         }
10424
10425         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10426                rnapi->coal_now);
10427
10428         udelay(10);
10429
10430         rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
10431
10432         num_pkts = 0;
10433
10434         tg3_set_txd(tnapi, tnapi->tx_prod,
10435                     skb_shinfo(skb)->dma_head, tx_len, 0, 1);
10436
10437         tnapi->tx_prod++;
10438         num_pkts++;
10439
10440         tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
10441         tr32_mailbox(tnapi->prodmbox);
10442
10443         udelay(10);
10444
10445         /* 350 usec to allow enough time on some 10/100 Mbps devices.  */
10446         for (i = 0; i < 35; i++) {
10447                 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10448                        coal_now);
10449
10450                 udelay(10);
10451
10452                 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
10453                 rx_idx = rnapi->hw_status->idx[0].rx_producer;
10454                 if ((tx_idx == tnapi->tx_prod) &&
10455                     (rx_idx == (rx_start_idx + num_pkts)))
10456                         break;
10457         }
10458
10459         skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
10460         dev_kfree_skb(skb);
10461
10462         if (tx_idx != tnapi->tx_prod)
10463                 goto out;
10464
10465         if (rx_idx != rx_start_idx + num_pkts)
10466                 goto out;
10467
10468         desc = &rnapi->rx_rcb[rx_start_idx];
10469         desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
10470         opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
10471         if (opaque_key != RXD_OPAQUE_RING_STD)
10472                 goto out;
10473
10474         if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
10475             (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
10476                 goto out;
10477
10478         rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
10479         if (rx_len != tx_len)
10480                 goto out;
10481
10482         rx_skb = tpr->rx_std_buffers[desc_idx].skb;
10483
10484         map = pci_unmap_addr(&tpr->rx_std_buffers[desc_idx], mapping);
10485         pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
10486
10487         for (i = 14; i < tx_len; i++) {
10488                 if (*(rx_skb->data + i) != (u8) (i & 0xff))
10489                         goto out;
10490         }
10491         err = 0;
10492
10493         /* tg3_free_rings will unmap and free the rx_skb */
10494 out:
10495         return err;
10496 }
10497
10498 #define TG3_MAC_LOOPBACK_FAILED         1
10499 #define TG3_PHY_LOOPBACK_FAILED         2
10500 #define TG3_LOOPBACK_FAILED             (TG3_MAC_LOOPBACK_FAILED |      \
10501                                          TG3_PHY_LOOPBACK_FAILED)
10502
10503 static int tg3_test_loopback(struct tg3 *tp)
10504 {
10505         int err = 0;
10506         u32 cpmuctrl = 0;
10507
10508         if (!netif_running(tp->dev))
10509                 return TG3_LOOPBACK_FAILED;
10510
10511         err = tg3_reset_hw(tp, 1);
10512         if (err)
10513                 return TG3_LOOPBACK_FAILED;
10514
10515         /* Turn off gphy autopowerdown. */
10516         if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10517                 tg3_phy_toggle_apd(tp, false);
10518
10519         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
10520                 int i;
10521                 u32 status;
10522
10523                 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
10524
10525                 /* Wait for up to 40 microseconds to acquire lock. */
10526                 for (i = 0; i < 4; i++) {
10527                         status = tr32(TG3_CPMU_MUTEX_GNT);
10528                         if (status == CPMU_MUTEX_GNT_DRIVER)
10529                                 break;
10530                         udelay(10);
10531                 }
10532
10533                 if (status != CPMU_MUTEX_GNT_DRIVER)
10534                         return TG3_LOOPBACK_FAILED;
10535
10536                 /* Turn off link-based power management. */
10537                 cpmuctrl = tr32(TG3_CPMU_CTRL);
10538                 tw32(TG3_CPMU_CTRL,
10539                      cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
10540                                   CPMU_CTRL_LINK_AWARE_MODE));
10541         }
10542
10543         if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
10544                 err |= TG3_MAC_LOOPBACK_FAILED;
10545
10546         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
10547                 tw32(TG3_CPMU_CTRL, cpmuctrl);
10548
10549                 /* Release the mutex */
10550                 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
10551         }
10552
10553         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
10554             !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
10555                 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
10556                         err |= TG3_PHY_LOOPBACK_FAILED;
10557         }
10558
10559         /* Re-enable gphy autopowerdown. */
10560         if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10561                 tg3_phy_toggle_apd(tp, true);
10562
10563         return err;
10564 }
10565
10566 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
10567                           u64 *data)
10568 {
10569         struct tg3 *tp = netdev_priv(dev);
10570
10571         if (tp->link_config.phy_is_low_power)
10572                 tg3_set_power_state(tp, PCI_D0);
10573
10574         memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
10575
10576         if (tg3_test_nvram(tp) != 0) {
10577                 etest->flags |= ETH_TEST_FL_FAILED;
10578                 data[0] = 1;
10579         }
10580         if (tg3_test_link(tp) != 0) {
10581                 etest->flags |= ETH_TEST_FL_FAILED;
10582                 data[1] = 1;
10583         }
10584         if (etest->flags & ETH_TEST_FL_OFFLINE) {
10585                 int err, err2 = 0, irq_sync = 0;
10586
10587                 if (netif_running(dev)) {
10588                         tg3_phy_stop(tp);
10589                         tg3_netif_stop(tp);
10590                         irq_sync = 1;
10591                 }
10592
10593                 tg3_full_lock(tp, irq_sync);
10594
10595                 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
10596                 err = tg3_nvram_lock(tp);
10597                 tg3_halt_cpu(tp, RX_CPU_BASE);
10598                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10599                         tg3_halt_cpu(tp, TX_CPU_BASE);
10600                 if (!err)
10601                         tg3_nvram_unlock(tp);
10602
10603                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
10604                         tg3_phy_reset(tp);
10605
10606                 if (tg3_test_registers(tp) != 0) {
10607                         etest->flags |= ETH_TEST_FL_FAILED;
10608                         data[2] = 1;
10609                 }
10610                 if (tg3_test_memory(tp) != 0) {
10611                         etest->flags |= ETH_TEST_FL_FAILED;
10612                         data[3] = 1;
10613                 }
10614                 if ((data[4] = tg3_test_loopback(tp)) != 0)
10615                         etest->flags |= ETH_TEST_FL_FAILED;
10616
10617                 tg3_full_unlock(tp);
10618
10619                 if (tg3_test_interrupt(tp) != 0) {
10620                         etest->flags |= ETH_TEST_FL_FAILED;
10621                         data[5] = 1;
10622                 }
10623
10624                 tg3_full_lock(tp, 0);
10625
10626                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10627                 if (netif_running(dev)) {
10628                         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
10629                         err2 = tg3_restart_hw(tp, 1);
10630                         if (!err2)
10631                                 tg3_netif_start(tp);
10632                 }
10633
10634                 tg3_full_unlock(tp);
10635
10636                 if (irq_sync && !err2)
10637                         tg3_phy_start(tp);
10638         }
10639         if (tp->link_config.phy_is_low_power)
10640                 tg3_set_power_state(tp, PCI_D3hot);
10641
10642 }
10643
10644 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
10645 {
10646         struct mii_ioctl_data *data = if_mii(ifr);
10647         struct tg3 *tp = netdev_priv(dev);
10648         int err;
10649
10650         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
10651                 struct phy_device *phydev;
10652                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
10653                         return -EAGAIN;
10654                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
10655                 return phy_mii_ioctl(phydev, data, cmd);
10656         }
10657
10658         switch(cmd) {
10659         case SIOCGMIIPHY:
10660                 data->phy_id = tp->phy_addr;
10661
10662                 /* fallthru */
10663         case SIOCGMIIREG: {
10664                 u32 mii_regval;
10665
10666                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10667                         break;                  /* We have no PHY */
10668
10669                 if (tp->link_config.phy_is_low_power)
10670                         return -EAGAIN;
10671
10672                 spin_lock_bh(&tp->lock);
10673                 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
10674                 spin_unlock_bh(&tp->lock);
10675
10676                 data->val_out = mii_regval;
10677
10678                 return err;
10679         }
10680
10681         case SIOCSMIIREG:
10682                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10683                         break;                  /* We have no PHY */
10684
10685                 if (tp->link_config.phy_is_low_power)
10686                         return -EAGAIN;
10687
10688                 spin_lock_bh(&tp->lock);
10689                 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
10690                 spin_unlock_bh(&tp->lock);
10691
10692                 return err;
10693
10694         default:
10695                 /* do nothing */
10696                 break;
10697         }
10698         return -EOPNOTSUPP;
10699 }
10700
10701 #if TG3_VLAN_TAG_USED
10702 static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
10703 {
10704         struct tg3 *tp = netdev_priv(dev);
10705
10706         if (!netif_running(dev)) {
10707                 tp->vlgrp = grp;
10708                 return;
10709         }
10710
10711         tg3_netif_stop(tp);
10712
10713         tg3_full_lock(tp, 0);
10714
10715         tp->vlgrp = grp;
10716
10717         /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
10718         __tg3_set_rx_mode(dev);
10719
10720         tg3_netif_start(tp);
10721
10722         tg3_full_unlock(tp);
10723 }
10724 #endif
10725
10726 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10727 {
10728         struct tg3 *tp = netdev_priv(dev);
10729
10730         memcpy(ec, &tp->coal, sizeof(*ec));
10731         return 0;
10732 }
10733
10734 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10735 {
10736         struct tg3 *tp = netdev_priv(dev);
10737         u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
10738         u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
10739
10740         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
10741                 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
10742                 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
10743                 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
10744                 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
10745         }
10746
10747         if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
10748             (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
10749             (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
10750             (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
10751             (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
10752             (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
10753             (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
10754             (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
10755             (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
10756             (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
10757                 return -EINVAL;
10758
10759         /* No rx interrupts will be generated if both are zero */
10760         if ((ec->rx_coalesce_usecs == 0) &&
10761             (ec->rx_max_coalesced_frames == 0))
10762                 return -EINVAL;
10763
10764         /* No tx interrupts will be generated if both are zero */
10765         if ((ec->tx_coalesce_usecs == 0) &&
10766             (ec->tx_max_coalesced_frames == 0))
10767                 return -EINVAL;
10768
10769         /* Only copy relevant parameters, ignore all others. */
10770         tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
10771         tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
10772         tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
10773         tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
10774         tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
10775         tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
10776         tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
10777         tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
10778         tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
10779
10780         if (netif_running(dev)) {
10781                 tg3_full_lock(tp, 0);
10782                 __tg3_set_coalesce(tp, &tp->coal);
10783                 tg3_full_unlock(tp);
10784         }
10785         return 0;
10786 }
10787
10788 static const struct ethtool_ops tg3_ethtool_ops = {
10789         .get_settings           = tg3_get_settings,
10790         .set_settings           = tg3_set_settings,
10791         .get_drvinfo            = tg3_get_drvinfo,
10792         .get_regs_len           = tg3_get_regs_len,
10793         .get_regs               = tg3_get_regs,
10794         .get_wol                = tg3_get_wol,
10795         .set_wol                = tg3_set_wol,
10796         .get_msglevel           = tg3_get_msglevel,
10797         .set_msglevel           = tg3_set_msglevel,
10798         .nway_reset             = tg3_nway_reset,
10799         .get_link               = ethtool_op_get_link,
10800         .get_eeprom_len         = tg3_get_eeprom_len,
10801         .get_eeprom             = tg3_get_eeprom,
10802         .set_eeprom             = tg3_set_eeprom,
10803         .get_ringparam          = tg3_get_ringparam,
10804         .set_ringparam          = tg3_set_ringparam,
10805         .get_pauseparam         = tg3_get_pauseparam,
10806         .set_pauseparam         = tg3_set_pauseparam,
10807         .get_rx_csum            = tg3_get_rx_csum,
10808         .set_rx_csum            = tg3_set_rx_csum,
10809         .set_tx_csum            = tg3_set_tx_csum,
10810         .set_sg                 = ethtool_op_set_sg,
10811         .set_tso                = tg3_set_tso,
10812         .self_test              = tg3_self_test,
10813         .get_strings            = tg3_get_strings,
10814         .phys_id                = tg3_phys_id,
10815         .get_ethtool_stats      = tg3_get_ethtool_stats,
10816         .get_coalesce           = tg3_get_coalesce,
10817         .set_coalesce           = tg3_set_coalesce,
10818         .get_sset_count         = tg3_get_sset_count,
10819 };
10820
10821 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
10822 {
10823         u32 cursize, val, magic;
10824
10825         tp->nvram_size = EEPROM_CHIP_SIZE;
10826
10827         if (tg3_nvram_read(tp, 0, &magic) != 0)
10828                 return;
10829
10830         if ((magic != TG3_EEPROM_MAGIC) &&
10831             ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
10832             ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
10833                 return;
10834
10835         /*
10836          * Size the chip by reading offsets at increasing powers of two.
10837          * When we encounter our validation signature, we know the addressing
10838          * has wrapped around, and thus have our chip size.
10839          */
10840         cursize = 0x10;
10841
10842         while (cursize < tp->nvram_size) {
10843                 if (tg3_nvram_read(tp, cursize, &val) != 0)
10844                         return;
10845
10846                 if (val == magic)
10847                         break;
10848
10849                 cursize <<= 1;
10850         }
10851
10852         tp->nvram_size = cursize;
10853 }
10854
10855 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
10856 {
10857         u32 val;
10858
10859         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
10860             tg3_nvram_read(tp, 0, &val) != 0)
10861                 return;
10862
10863         /* Selfboot format */
10864         if (val != TG3_EEPROM_MAGIC) {
10865                 tg3_get_eeprom_size(tp);
10866                 return;
10867         }
10868
10869         if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
10870                 if (val != 0) {
10871                         /* This is confusing.  We want to operate on the
10872                          * 16-bit value at offset 0xf2.  The tg3_nvram_read()
10873                          * call will read from NVRAM and byteswap the data
10874                          * according to the byteswapping settings for all
10875                          * other register accesses.  This ensures the data we
10876                          * want will always reside in the lower 16-bits.
10877                          * However, the data in NVRAM is in LE format, which
10878                          * means the data from the NVRAM read will always be
10879                          * opposite the endianness of the CPU.  The 16-bit
10880                          * byteswap then brings the data to CPU endianness.
10881                          */
10882                         tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
10883                         return;
10884                 }
10885         }
10886         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10887 }
10888
10889 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
10890 {
10891         u32 nvcfg1;
10892
10893         nvcfg1 = tr32(NVRAM_CFG1);
10894         if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
10895                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10896         } else {
10897                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10898                 tw32(NVRAM_CFG1, nvcfg1);
10899         }
10900
10901         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
10902             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
10903                 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
10904                 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
10905                         tp->nvram_jedecnum = JEDEC_ATMEL;
10906                         tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
10907                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10908                         break;
10909                 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
10910                         tp->nvram_jedecnum = JEDEC_ATMEL;
10911                         tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
10912                         break;
10913                 case FLASH_VENDOR_ATMEL_EEPROM:
10914                         tp->nvram_jedecnum = JEDEC_ATMEL;
10915                         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10916                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10917                         break;
10918                 case FLASH_VENDOR_ST:
10919                         tp->nvram_jedecnum = JEDEC_ST;
10920                         tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
10921                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10922                         break;
10923                 case FLASH_VENDOR_SAIFUN:
10924                         tp->nvram_jedecnum = JEDEC_SAIFUN;
10925                         tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
10926                         break;
10927                 case FLASH_VENDOR_SST_SMALL:
10928                 case FLASH_VENDOR_SST_LARGE:
10929                         tp->nvram_jedecnum = JEDEC_SST;
10930                         tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
10931                         break;
10932                 }
10933         } else {
10934                 tp->nvram_jedecnum = JEDEC_ATMEL;
10935                 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
10936                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10937         }
10938 }
10939
10940 static void __devinit tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
10941 {
10942         switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
10943         case FLASH_5752PAGE_SIZE_256:
10944                 tp->nvram_pagesize = 256;
10945                 break;
10946         case FLASH_5752PAGE_SIZE_512:
10947                 tp->nvram_pagesize = 512;
10948                 break;
10949         case FLASH_5752PAGE_SIZE_1K:
10950                 tp->nvram_pagesize = 1024;
10951                 break;
10952         case FLASH_5752PAGE_SIZE_2K:
10953                 tp->nvram_pagesize = 2048;
10954                 break;
10955         case FLASH_5752PAGE_SIZE_4K:
10956                 tp->nvram_pagesize = 4096;
10957                 break;
10958         case FLASH_5752PAGE_SIZE_264:
10959                 tp->nvram_pagesize = 264;
10960                 break;
10961         case FLASH_5752PAGE_SIZE_528:
10962                 tp->nvram_pagesize = 528;
10963                 break;
10964         }
10965 }
10966
10967 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
10968 {
10969         u32 nvcfg1;
10970
10971         nvcfg1 = tr32(NVRAM_CFG1);
10972
10973         /* NVRAM protection for TPM */
10974         if (nvcfg1 & (1 << 27))
10975                 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
10976
10977         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10978         case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
10979         case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
10980                 tp->nvram_jedecnum = JEDEC_ATMEL;
10981                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10982                 break;
10983         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10984                 tp->nvram_jedecnum = JEDEC_ATMEL;
10985                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10986                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10987                 break;
10988         case FLASH_5752VENDOR_ST_M45PE10:
10989         case FLASH_5752VENDOR_ST_M45PE20:
10990         case FLASH_5752VENDOR_ST_M45PE40:
10991                 tp->nvram_jedecnum = JEDEC_ST;
10992                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10993                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10994                 break;
10995         }
10996
10997         if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
10998                 tg3_nvram_get_pagesize(tp, nvcfg1);
10999         } else {
11000                 /* For eeprom, set pagesize to maximum eeprom size */
11001                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11002
11003                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11004                 tw32(NVRAM_CFG1, nvcfg1);
11005         }
11006 }
11007
11008 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
11009 {
11010         u32 nvcfg1, protect = 0;
11011
11012         nvcfg1 = tr32(NVRAM_CFG1);
11013
11014         /* NVRAM protection for TPM */
11015         if (nvcfg1 & (1 << 27)) {
11016                 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11017                 protect = 1;
11018         }
11019
11020         nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11021         switch (nvcfg1) {
11022         case FLASH_5755VENDOR_ATMEL_FLASH_1:
11023         case FLASH_5755VENDOR_ATMEL_FLASH_2:
11024         case FLASH_5755VENDOR_ATMEL_FLASH_3:
11025         case FLASH_5755VENDOR_ATMEL_FLASH_5:
11026                 tp->nvram_jedecnum = JEDEC_ATMEL;
11027                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11028                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11029                 tp->nvram_pagesize = 264;
11030                 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
11031                     nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
11032                         tp->nvram_size = (protect ? 0x3e200 :
11033                                           TG3_NVRAM_SIZE_512KB);
11034                 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
11035                         tp->nvram_size = (protect ? 0x1f200 :
11036                                           TG3_NVRAM_SIZE_256KB);
11037                 else
11038                         tp->nvram_size = (protect ? 0x1f200 :
11039                                           TG3_NVRAM_SIZE_128KB);
11040                 break;
11041         case FLASH_5752VENDOR_ST_M45PE10:
11042         case FLASH_5752VENDOR_ST_M45PE20:
11043         case FLASH_5752VENDOR_ST_M45PE40:
11044                 tp->nvram_jedecnum = JEDEC_ST;
11045                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11046                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11047                 tp->nvram_pagesize = 256;
11048                 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
11049                         tp->nvram_size = (protect ?
11050                                           TG3_NVRAM_SIZE_64KB :
11051                                           TG3_NVRAM_SIZE_128KB);
11052                 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
11053                         tp->nvram_size = (protect ?
11054                                           TG3_NVRAM_SIZE_64KB :
11055                                           TG3_NVRAM_SIZE_256KB);
11056                 else
11057                         tp->nvram_size = (protect ?
11058                                           TG3_NVRAM_SIZE_128KB :
11059                                           TG3_NVRAM_SIZE_512KB);
11060                 break;
11061         }
11062 }
11063
11064 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
11065 {
11066         u32 nvcfg1;
11067
11068         nvcfg1 = tr32(NVRAM_CFG1);
11069
11070         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11071         case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
11072         case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11073         case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
11074         case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11075                 tp->nvram_jedecnum = JEDEC_ATMEL;
11076                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11077                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11078
11079                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11080                 tw32(NVRAM_CFG1, nvcfg1);
11081                 break;
11082         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11083         case FLASH_5755VENDOR_ATMEL_FLASH_1:
11084         case FLASH_5755VENDOR_ATMEL_FLASH_2:
11085         case FLASH_5755VENDOR_ATMEL_FLASH_3:
11086                 tp->nvram_jedecnum = JEDEC_ATMEL;
11087                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11088                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11089                 tp->nvram_pagesize = 264;
11090                 break;
11091         case FLASH_5752VENDOR_ST_M45PE10:
11092         case FLASH_5752VENDOR_ST_M45PE20:
11093         case FLASH_5752VENDOR_ST_M45PE40:
11094                 tp->nvram_jedecnum = JEDEC_ST;
11095                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11096                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11097                 tp->nvram_pagesize = 256;
11098                 break;
11099         }
11100 }
11101
11102 static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
11103 {
11104         u32 nvcfg1, protect = 0;
11105
11106         nvcfg1 = tr32(NVRAM_CFG1);
11107
11108         /* NVRAM protection for TPM */
11109         if (nvcfg1 & (1 << 27)) {
11110                 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11111                 protect = 1;
11112         }
11113
11114         nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11115         switch (nvcfg1) {
11116         case FLASH_5761VENDOR_ATMEL_ADB021D:
11117         case FLASH_5761VENDOR_ATMEL_ADB041D:
11118         case FLASH_5761VENDOR_ATMEL_ADB081D:
11119         case FLASH_5761VENDOR_ATMEL_ADB161D:
11120         case FLASH_5761VENDOR_ATMEL_MDB021D:
11121         case FLASH_5761VENDOR_ATMEL_MDB041D:
11122         case FLASH_5761VENDOR_ATMEL_MDB081D:
11123         case FLASH_5761VENDOR_ATMEL_MDB161D:
11124                 tp->nvram_jedecnum = JEDEC_ATMEL;
11125                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11126                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11127                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11128                 tp->nvram_pagesize = 256;
11129                 break;
11130         case FLASH_5761VENDOR_ST_A_M45PE20:
11131         case FLASH_5761VENDOR_ST_A_M45PE40:
11132         case FLASH_5761VENDOR_ST_A_M45PE80:
11133         case FLASH_5761VENDOR_ST_A_M45PE16:
11134         case FLASH_5761VENDOR_ST_M_M45PE20:
11135         case FLASH_5761VENDOR_ST_M_M45PE40:
11136         case FLASH_5761VENDOR_ST_M_M45PE80:
11137         case FLASH_5761VENDOR_ST_M_M45PE16:
11138                 tp->nvram_jedecnum = JEDEC_ST;
11139                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11140                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11141                 tp->nvram_pagesize = 256;
11142                 break;
11143         }
11144
11145         if (protect) {
11146                 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
11147         } else {
11148                 switch (nvcfg1) {
11149                 case FLASH_5761VENDOR_ATMEL_ADB161D:
11150                 case FLASH_5761VENDOR_ATMEL_MDB161D:
11151                 case FLASH_5761VENDOR_ST_A_M45PE16:
11152                 case FLASH_5761VENDOR_ST_M_M45PE16:
11153                         tp->nvram_size = TG3_NVRAM_SIZE_2MB;
11154                         break;
11155                 case FLASH_5761VENDOR_ATMEL_ADB081D:
11156                 case FLASH_5761VENDOR_ATMEL_MDB081D:
11157                 case FLASH_5761VENDOR_ST_A_M45PE80:
11158                 case FLASH_5761VENDOR_ST_M_M45PE80:
11159                         tp->nvram_size = TG3_NVRAM_SIZE_1MB;
11160                         break;
11161                 case FLASH_5761VENDOR_ATMEL_ADB041D:
11162                 case FLASH_5761VENDOR_ATMEL_MDB041D:
11163                 case FLASH_5761VENDOR_ST_A_M45PE40:
11164                 case FLASH_5761VENDOR_ST_M_M45PE40:
11165                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11166                         break;
11167                 case FLASH_5761VENDOR_ATMEL_ADB021D:
11168                 case FLASH_5761VENDOR_ATMEL_MDB021D:
11169                 case FLASH_5761VENDOR_ST_A_M45PE20:
11170                 case FLASH_5761VENDOR_ST_M_M45PE20:
11171                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11172                         break;
11173                 }
11174         }
11175 }
11176
11177 static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
11178 {
11179         tp->nvram_jedecnum = JEDEC_ATMEL;
11180         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11181         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11182 }
11183
11184 static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
11185 {
11186         u32 nvcfg1;
11187
11188         nvcfg1 = tr32(NVRAM_CFG1);
11189
11190         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11191         case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11192         case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11193                 tp->nvram_jedecnum = JEDEC_ATMEL;
11194                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11195                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11196
11197                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11198                 tw32(NVRAM_CFG1, nvcfg1);
11199                 return;
11200         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11201         case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11202         case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11203         case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11204         case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11205         case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11206         case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11207                 tp->nvram_jedecnum = JEDEC_ATMEL;
11208                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11209                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11210
11211                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11212                 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11213                 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11214                 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11215                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11216                         break;
11217                 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11218                 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11219                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11220                         break;
11221                 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11222                 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11223                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11224                         break;
11225                 }
11226                 break;
11227         case FLASH_5752VENDOR_ST_M45PE10:
11228         case FLASH_5752VENDOR_ST_M45PE20:
11229         case FLASH_5752VENDOR_ST_M45PE40:
11230                 tp->nvram_jedecnum = JEDEC_ST;
11231                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11232                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11233
11234                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11235                 case FLASH_5752VENDOR_ST_M45PE10:
11236                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11237                         break;
11238                 case FLASH_5752VENDOR_ST_M45PE20:
11239                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11240                         break;
11241                 case FLASH_5752VENDOR_ST_M45PE40:
11242                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11243                         break;
11244                 }
11245                 break;
11246         default:
11247                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11248                 return;
11249         }
11250
11251         tg3_nvram_get_pagesize(tp, nvcfg1);
11252         if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11253                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11254 }
11255
11256
11257 static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp)
11258 {
11259         u32 nvcfg1;
11260
11261         nvcfg1 = tr32(NVRAM_CFG1);
11262
11263         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11264         case FLASH_5717VENDOR_ATMEL_EEPROM:
11265         case FLASH_5717VENDOR_MICRO_EEPROM:
11266                 tp->nvram_jedecnum = JEDEC_ATMEL;
11267                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11268                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11269
11270                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11271                 tw32(NVRAM_CFG1, nvcfg1);
11272                 return;
11273         case FLASH_5717VENDOR_ATMEL_MDB011D:
11274         case FLASH_5717VENDOR_ATMEL_ADB011B:
11275         case FLASH_5717VENDOR_ATMEL_ADB011D:
11276         case FLASH_5717VENDOR_ATMEL_MDB021D:
11277         case FLASH_5717VENDOR_ATMEL_ADB021B:
11278         case FLASH_5717VENDOR_ATMEL_ADB021D:
11279         case FLASH_5717VENDOR_ATMEL_45USPT:
11280                 tp->nvram_jedecnum = JEDEC_ATMEL;
11281                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11282                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11283
11284                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11285                 case FLASH_5717VENDOR_ATMEL_MDB021D:
11286                 case FLASH_5717VENDOR_ATMEL_ADB021B:
11287                 case FLASH_5717VENDOR_ATMEL_ADB021D:
11288                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11289                         break;
11290                 default:
11291                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11292                         break;
11293                 }
11294                 break;
11295         case FLASH_5717VENDOR_ST_M_M25PE10:
11296         case FLASH_5717VENDOR_ST_A_M25PE10:
11297         case FLASH_5717VENDOR_ST_M_M45PE10:
11298         case FLASH_5717VENDOR_ST_A_M45PE10:
11299         case FLASH_5717VENDOR_ST_M_M25PE20:
11300         case FLASH_5717VENDOR_ST_A_M25PE20:
11301         case FLASH_5717VENDOR_ST_M_M45PE20:
11302         case FLASH_5717VENDOR_ST_A_M45PE20:
11303         case FLASH_5717VENDOR_ST_25USPT:
11304         case FLASH_5717VENDOR_ST_45USPT:
11305                 tp->nvram_jedecnum = JEDEC_ST;
11306                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11307                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11308
11309                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11310                 case FLASH_5717VENDOR_ST_M_M25PE20:
11311                 case FLASH_5717VENDOR_ST_A_M25PE20:
11312                 case FLASH_5717VENDOR_ST_M_M45PE20:
11313                 case FLASH_5717VENDOR_ST_A_M45PE20:
11314                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11315                         break;
11316                 default:
11317                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11318                         break;
11319                 }
11320                 break;
11321         default:
11322                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11323                 return;
11324         }
11325
11326         tg3_nvram_get_pagesize(tp, nvcfg1);
11327         if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11328                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11329 }
11330
11331 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
11332 static void __devinit tg3_nvram_init(struct tg3 *tp)
11333 {
11334         tw32_f(GRC_EEPROM_ADDR,
11335              (EEPROM_ADDR_FSM_RESET |
11336               (EEPROM_DEFAULT_CLOCK_PERIOD <<
11337                EEPROM_ADDR_CLKPERD_SHIFT)));
11338
11339         msleep(1);
11340
11341         /* Enable seeprom accesses. */
11342         tw32_f(GRC_LOCAL_CTRL,
11343              tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
11344         udelay(100);
11345
11346         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11347             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
11348                 tp->tg3_flags |= TG3_FLAG_NVRAM;
11349
11350                 if (tg3_nvram_lock(tp)) {
11351                         printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
11352                                "tg3_nvram_init failed.\n", tp->dev->name);
11353                         return;
11354                 }
11355                 tg3_enable_nvram_access(tp);
11356
11357                 tp->nvram_size = 0;
11358
11359                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
11360                         tg3_get_5752_nvram_info(tp);
11361                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
11362                         tg3_get_5755_nvram_info(tp);
11363                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
11364                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11365                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11366                         tg3_get_5787_nvram_info(tp);
11367                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
11368                         tg3_get_5761_nvram_info(tp);
11369                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11370                         tg3_get_5906_nvram_info(tp);
11371                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
11372                         tg3_get_57780_nvram_info(tp);
11373                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
11374                         tg3_get_5717_nvram_info(tp);
11375                 else
11376                         tg3_get_nvram_info(tp);
11377
11378                 if (tp->nvram_size == 0)
11379                         tg3_get_nvram_size(tp);
11380
11381                 tg3_disable_nvram_access(tp);
11382                 tg3_nvram_unlock(tp);
11383
11384         } else {
11385                 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
11386
11387                 tg3_get_eeprom_size(tp);
11388         }
11389 }
11390
11391 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
11392                                     u32 offset, u32 len, u8 *buf)
11393 {
11394         int i, j, rc = 0;
11395         u32 val;
11396
11397         for (i = 0; i < len; i += 4) {
11398                 u32 addr;
11399                 __be32 data;
11400
11401                 addr = offset + i;
11402
11403                 memcpy(&data, buf + i, 4);
11404
11405                 /*
11406                  * The SEEPROM interface expects the data to always be opposite
11407                  * the native endian format.  We accomplish this by reversing
11408                  * all the operations that would have been performed on the
11409                  * data from a call to tg3_nvram_read_be32().
11410                  */
11411                 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
11412
11413                 val = tr32(GRC_EEPROM_ADDR);
11414                 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
11415
11416                 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
11417                         EEPROM_ADDR_READ);
11418                 tw32(GRC_EEPROM_ADDR, val |
11419                         (0 << EEPROM_ADDR_DEVID_SHIFT) |
11420                         (addr & EEPROM_ADDR_ADDR_MASK) |
11421                         EEPROM_ADDR_START |
11422                         EEPROM_ADDR_WRITE);
11423
11424                 for (j = 0; j < 1000; j++) {
11425                         val = tr32(GRC_EEPROM_ADDR);
11426
11427                         if (val & EEPROM_ADDR_COMPLETE)
11428                                 break;
11429                         msleep(1);
11430                 }
11431                 if (!(val & EEPROM_ADDR_COMPLETE)) {
11432                         rc = -EBUSY;
11433                         break;
11434                 }
11435         }
11436
11437         return rc;
11438 }
11439
11440 /* offset and length are dword aligned */
11441 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
11442                 u8 *buf)
11443 {
11444         int ret = 0;
11445         u32 pagesize = tp->nvram_pagesize;
11446         u32 pagemask = pagesize - 1;
11447         u32 nvram_cmd;
11448         u8 *tmp;
11449
11450         tmp = kmalloc(pagesize, GFP_KERNEL);
11451         if (tmp == NULL)
11452                 return -ENOMEM;
11453
11454         while (len) {
11455                 int j;
11456                 u32 phy_addr, page_off, size;
11457
11458                 phy_addr = offset & ~pagemask;
11459
11460                 for (j = 0; j < pagesize; j += 4) {
11461                         ret = tg3_nvram_read_be32(tp, phy_addr + j,
11462                                                   (__be32 *) (tmp + j));
11463                         if (ret)
11464                                 break;
11465                 }
11466                 if (ret)
11467                         break;
11468
11469                 page_off = offset & pagemask;
11470                 size = pagesize;
11471                 if (len < size)
11472                         size = len;
11473
11474                 len -= size;
11475
11476                 memcpy(tmp + page_off, buf, size);
11477
11478                 offset = offset + (pagesize - page_off);
11479
11480                 tg3_enable_nvram_access(tp);
11481
11482                 /*
11483                  * Before we can erase the flash page, we need
11484                  * to issue a special "write enable" command.
11485                  */
11486                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11487
11488                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11489                         break;
11490
11491                 /* Erase the target page */
11492                 tw32(NVRAM_ADDR, phy_addr);
11493
11494                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
11495                         NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
11496
11497                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11498                         break;
11499
11500                 /* Issue another write enable to start the write. */
11501                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11502
11503                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11504                         break;
11505
11506                 for (j = 0; j < pagesize; j += 4) {
11507                         __be32 data;
11508
11509                         data = *((__be32 *) (tmp + j));
11510
11511                         tw32(NVRAM_WRDATA, be32_to_cpu(data));
11512
11513                         tw32(NVRAM_ADDR, phy_addr + j);
11514
11515                         nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
11516                                 NVRAM_CMD_WR;
11517
11518                         if (j == 0)
11519                                 nvram_cmd |= NVRAM_CMD_FIRST;
11520                         else if (j == (pagesize - 4))
11521                                 nvram_cmd |= NVRAM_CMD_LAST;
11522
11523                         if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11524                                 break;
11525                 }
11526                 if (ret)
11527                         break;
11528         }
11529
11530         nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11531         tg3_nvram_exec_cmd(tp, nvram_cmd);
11532
11533         kfree(tmp);
11534
11535         return ret;
11536 }
11537
11538 /* offset and length are dword aligned */
11539 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
11540                 u8 *buf)
11541 {
11542         int i, ret = 0;
11543
11544         for (i = 0; i < len; i += 4, offset += 4) {
11545                 u32 page_off, phy_addr, nvram_cmd;
11546                 __be32 data;
11547
11548                 memcpy(&data, buf + i, 4);
11549                 tw32(NVRAM_WRDATA, be32_to_cpu(data));
11550
11551                 page_off = offset % tp->nvram_pagesize;
11552
11553                 phy_addr = tg3_nvram_phys_addr(tp, offset);
11554
11555                 tw32(NVRAM_ADDR, phy_addr);
11556
11557                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
11558
11559                 if ((page_off == 0) || (i == 0))
11560                         nvram_cmd |= NVRAM_CMD_FIRST;
11561                 if (page_off == (tp->nvram_pagesize - 4))
11562                         nvram_cmd |= NVRAM_CMD_LAST;
11563
11564                 if (i == (len - 4))
11565                         nvram_cmd |= NVRAM_CMD_LAST;
11566
11567                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
11568                     !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
11569                     (tp->nvram_jedecnum == JEDEC_ST) &&
11570                     (nvram_cmd & NVRAM_CMD_FIRST)) {
11571
11572                         if ((ret = tg3_nvram_exec_cmd(tp,
11573                                 NVRAM_CMD_WREN | NVRAM_CMD_GO |
11574                                 NVRAM_CMD_DONE)))
11575
11576                                 break;
11577                 }
11578                 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11579                         /* We always do complete word writes to eeprom. */
11580                         nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
11581                 }
11582
11583                 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11584                         break;
11585         }
11586         return ret;
11587 }
11588
11589 /* offset and length are dword aligned */
11590 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
11591 {
11592         int ret;
11593
11594         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
11595                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
11596                        ~GRC_LCLCTRL_GPIO_OUTPUT1);
11597                 udelay(40);
11598         }
11599
11600         if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
11601                 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
11602         }
11603         else {
11604                 u32 grc_mode;
11605
11606                 ret = tg3_nvram_lock(tp);
11607                 if (ret)
11608                         return ret;
11609
11610                 tg3_enable_nvram_access(tp);
11611                 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
11612                     !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM))
11613                         tw32(NVRAM_WRITE1, 0x406);
11614
11615                 grc_mode = tr32(GRC_MODE);
11616                 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
11617
11618                 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
11619                         !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11620
11621                         ret = tg3_nvram_write_block_buffered(tp, offset, len,
11622                                 buf);
11623                 }
11624                 else {
11625                         ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
11626                                 buf);
11627                 }
11628
11629                 grc_mode = tr32(GRC_MODE);
11630                 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
11631
11632                 tg3_disable_nvram_access(tp);
11633                 tg3_nvram_unlock(tp);
11634         }
11635
11636         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
11637                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
11638                 udelay(40);
11639         }
11640
11641         return ret;
11642 }
11643
11644 struct subsys_tbl_ent {
11645         u16 subsys_vendor, subsys_devid;
11646         u32 phy_id;
11647 };
11648
11649 static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
11650         /* Broadcom boards. */
11651         { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
11652         { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
11653         { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
11654         { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 },              /* BCM95700A9 */
11655         { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
11656         { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
11657         { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 },              /* BCM95701A7 */
11658         { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
11659         { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
11660         { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
11661         { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
11662
11663         /* 3com boards. */
11664         { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
11665         { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
11666         { PCI_VENDOR_ID_3COM, 0x1004, 0 },              /* 3C996SX */
11667         { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
11668         { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
11669
11670         /* DELL boards. */
11671         { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
11672         { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
11673         { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
11674         { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
11675
11676         /* Compaq boards. */
11677         { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
11678         { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
11679         { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 },              /* CHANGELING */
11680         { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
11681         { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
11682
11683         /* IBM boards. */
11684         { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
11685 };
11686
11687 static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
11688 {
11689         int i;
11690
11691         for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
11692                 if ((subsys_id_to_phy_id[i].subsys_vendor ==
11693                      tp->pdev->subsystem_vendor) &&
11694                     (subsys_id_to_phy_id[i].subsys_devid ==
11695                      tp->pdev->subsystem_device))
11696                         return &subsys_id_to_phy_id[i];
11697         }
11698         return NULL;
11699 }
11700
11701 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
11702 {
11703         u32 val;
11704         u16 pmcsr;
11705
11706         /* On some early chips the SRAM cannot be accessed in D3hot state,
11707          * so need make sure we're in D0.
11708          */
11709         pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
11710         pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
11711         pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
11712         msleep(1);
11713
11714         /* Make sure register accesses (indirect or otherwise)
11715          * will function correctly.
11716          */
11717         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11718                                tp->misc_host_ctrl);
11719
11720         /* The memory arbiter has to be enabled in order for SRAM accesses
11721          * to succeed.  Normally on powerup the tg3 chip firmware will make
11722          * sure it is enabled, but other entities such as system netboot
11723          * code might disable it.
11724          */
11725         val = tr32(MEMARB_MODE);
11726         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
11727
11728         tp->phy_id = PHY_ID_INVALID;
11729         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11730
11731         /* Assume an onboard device and WOL capable by default.  */
11732         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
11733
11734         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
11735                 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
11736                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11737                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
11738                 }
11739                 val = tr32(VCPU_CFGSHDW);
11740                 if (val & VCPU_CFGSHDW_ASPM_DBNC)
11741                         tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
11742                 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
11743                     (val & VCPU_CFGSHDW_WOL_MAGPKT))
11744                         tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
11745                 goto done;
11746         }
11747
11748         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
11749         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
11750                 u32 nic_cfg, led_cfg;
11751                 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
11752                 int eeprom_phy_serdes = 0;
11753
11754                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
11755                 tp->nic_sram_data_cfg = nic_cfg;
11756
11757                 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
11758                 ver >>= NIC_SRAM_DATA_VER_SHIFT;
11759                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
11760                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
11761                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
11762                     (ver > 0) && (ver < 0x100))
11763                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
11764
11765                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11766                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
11767
11768                 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
11769                     NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
11770                         eeprom_phy_serdes = 1;
11771
11772                 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
11773                 if (nic_phy_id != 0) {
11774                         u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
11775                         u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
11776
11777                         eeprom_phy_id  = (id1 >> 16) << 10;
11778                         eeprom_phy_id |= (id2 & 0xfc00) << 16;
11779                         eeprom_phy_id |= (id2 & 0x03ff) <<  0;
11780                 } else
11781                         eeprom_phy_id = 0;
11782
11783                 tp->phy_id = eeprom_phy_id;
11784                 if (eeprom_phy_serdes) {
11785                         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
11786                                 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
11787                         else
11788                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11789                 }
11790
11791                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
11792                         led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
11793                                     SHASTA_EXT_LED_MODE_MASK);
11794                 else
11795                         led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
11796
11797                 switch (led_cfg) {
11798                 default:
11799                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
11800                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11801                         break;
11802
11803                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
11804                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
11805                         break;
11806
11807                 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
11808                         tp->led_ctrl = LED_CTRL_MODE_MAC;
11809
11810                         /* Default to PHY_1_MODE if 0 (MAC_MODE) is
11811                          * read on some older 5700/5701 bootcode.
11812                          */
11813                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
11814                             ASIC_REV_5700 ||
11815                             GET_ASIC_REV(tp->pci_chip_rev_id) ==
11816                             ASIC_REV_5701)
11817                                 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11818
11819                         break;
11820
11821                 case SHASTA_EXT_LED_SHARED:
11822                         tp->led_ctrl = LED_CTRL_MODE_SHARED;
11823                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
11824                             tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
11825                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
11826                                                  LED_CTRL_MODE_PHY_2);
11827                         break;
11828
11829                 case SHASTA_EXT_LED_MAC:
11830                         tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
11831                         break;
11832
11833                 case SHASTA_EXT_LED_COMBO:
11834                         tp->led_ctrl = LED_CTRL_MODE_COMBO;
11835                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
11836                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
11837                                                  LED_CTRL_MODE_PHY_2);
11838                         break;
11839
11840                 }
11841
11842                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11843                      GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
11844                     tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
11845                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
11846
11847                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
11848                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11849
11850                 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
11851                         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
11852                         if ((tp->pdev->subsystem_vendor ==
11853                              PCI_VENDOR_ID_ARIMA) &&
11854                             (tp->pdev->subsystem_device == 0x205a ||
11855                              tp->pdev->subsystem_device == 0x2063))
11856                                 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11857                 } else {
11858                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11859                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
11860                 }
11861
11862                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
11863                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
11864                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
11865                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
11866                 }
11867
11868                 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
11869                         (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
11870                         tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
11871
11872                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
11873                     !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
11874                         tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
11875
11876                 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
11877                     (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
11878                         tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
11879
11880                 if (cfg2 & (1 << 17))
11881                         tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
11882
11883                 /* serdes signal pre-emphasis in register 0x590 set by */
11884                 /* bootcode if bit 18 is set */
11885                 if (cfg2 & (1 << 18))
11886                         tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
11887
11888                 if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
11889                       GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
11890                     (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
11891                         tp->tg3_flags3 |= TG3_FLG3_PHY_ENABLE_APD;
11892
11893                 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11894                         u32 cfg3;
11895
11896                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
11897                         if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
11898                                 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
11899                 }
11900
11901                 if (cfg4 & NIC_SRAM_RGMII_STD_IBND_DISABLE)
11902                         tp->tg3_flags3 |= TG3_FLG3_RGMII_STD_IBND_DISABLE;
11903                 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
11904                         tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
11905                 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
11906                         tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
11907         }
11908 done:
11909         device_init_wakeup(&tp->pdev->dev, tp->tg3_flags & TG3_FLAG_WOL_CAP);
11910         device_set_wakeup_enable(&tp->pdev->dev,
11911                                  tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
11912 }
11913
11914 static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
11915 {
11916         int i;
11917         u32 val;
11918
11919         tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
11920         tw32(OTP_CTRL, cmd);
11921
11922         /* Wait for up to 1 ms for command to execute. */
11923         for (i = 0; i < 100; i++) {
11924                 val = tr32(OTP_STATUS);
11925                 if (val & OTP_STATUS_CMD_DONE)
11926                         break;
11927                 udelay(10);
11928         }
11929
11930         return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
11931 }
11932
11933 /* Read the gphy configuration from the OTP region of the chip.  The gphy
11934  * configuration is a 32-bit value that straddles the alignment boundary.
11935  * We do two 32-bit reads and then shift and merge the results.
11936  */
11937 static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
11938 {
11939         u32 bhalf_otp, thalf_otp;
11940
11941         tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
11942
11943         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
11944                 return 0;
11945
11946         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
11947
11948         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
11949                 return 0;
11950
11951         thalf_otp = tr32(OTP_READ_DATA);
11952
11953         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
11954
11955         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
11956                 return 0;
11957
11958         bhalf_otp = tr32(OTP_READ_DATA);
11959
11960         return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
11961 }
11962
11963 static int __devinit tg3_phy_probe(struct tg3 *tp)
11964 {
11965         u32 hw_phy_id_1, hw_phy_id_2;
11966         u32 hw_phy_id, hw_phy_id_masked;
11967         int err;
11968
11969         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
11970                 return tg3_phy_init(tp);
11971
11972         /* Reading the PHY ID register can conflict with ASF
11973          * firmware access to the PHY hardware.
11974          */
11975         err = 0;
11976         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
11977             (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
11978                 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
11979         } else {
11980                 /* Now read the physical PHY_ID from the chip and verify
11981                  * that it is sane.  If it doesn't look good, we fall back
11982                  * to either the hard-coded table based PHY_ID and failing
11983                  * that the value found in the eeprom area.
11984                  */
11985                 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
11986                 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
11987
11988                 hw_phy_id  = (hw_phy_id_1 & 0xffff) << 10;
11989                 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
11990                 hw_phy_id |= (hw_phy_id_2 & 0x03ff) <<  0;
11991
11992                 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
11993         }
11994
11995         if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
11996                 tp->phy_id = hw_phy_id;
11997                 if (hw_phy_id_masked == PHY_ID_BCM8002)
11998                         tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11999                 else
12000                         tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
12001         } else {
12002                 if (tp->phy_id != PHY_ID_INVALID) {
12003                         /* Do nothing, phy ID already set up in
12004                          * tg3_get_eeprom_hw_cfg().
12005                          */
12006                 } else {
12007                         struct subsys_tbl_ent *p;
12008
12009                         /* No eeprom signature?  Try the hardcoded
12010                          * subsys device table.
12011                          */
12012                         p = lookup_by_subsys(tp);
12013                         if (!p)
12014                                 return -ENODEV;
12015
12016                         tp->phy_id = p->phy_id;
12017                         if (!tp->phy_id ||
12018                             tp->phy_id == PHY_ID_BCM8002)
12019                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
12020                 }
12021         }
12022
12023         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
12024             !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
12025             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
12026                 u32 bmsr, adv_reg, tg3_ctrl, mask;
12027
12028                 tg3_readphy(tp, MII_BMSR, &bmsr);
12029                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
12030                     (bmsr & BMSR_LSTATUS))
12031                         goto skip_phy_reset;
12032
12033                 err = tg3_phy_reset(tp);
12034                 if (err)
12035                         return err;
12036
12037                 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
12038                            ADVERTISE_100HALF | ADVERTISE_100FULL |
12039                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
12040                 tg3_ctrl = 0;
12041                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
12042                         tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
12043                                     MII_TG3_CTRL_ADV_1000_FULL);
12044                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12045                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
12046                                 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
12047                                              MII_TG3_CTRL_ENABLE_AS_MASTER);
12048                 }
12049
12050                 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
12051                         ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
12052                         ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
12053                 if (!tg3_copper_is_advertising_all(tp, mask)) {
12054                         tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12055
12056                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
12057                                 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12058
12059                         tg3_writephy(tp, MII_BMCR,
12060                                      BMCR_ANENABLE | BMCR_ANRESTART);
12061                 }
12062                 tg3_phy_set_wirespeed(tp);
12063
12064                 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12065                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
12066                         tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12067         }
12068
12069 skip_phy_reset:
12070         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
12071                 err = tg3_init_5401phy_dsp(tp);
12072                 if (err)
12073                         return err;
12074         }
12075
12076         if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
12077                 err = tg3_init_5401phy_dsp(tp);
12078         }
12079
12080         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
12081                 tp->link_config.advertising =
12082                         (ADVERTISED_1000baseT_Half |
12083                          ADVERTISED_1000baseT_Full |
12084                          ADVERTISED_Autoneg |
12085                          ADVERTISED_FIBRE);
12086         if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
12087                 tp->link_config.advertising &=
12088                         ~(ADVERTISED_1000baseT_Half |
12089                           ADVERTISED_1000baseT_Full);
12090
12091         return err;
12092 }
12093
12094 static void __devinit tg3_read_partno(struct tg3 *tp)
12095 {
12096         unsigned char vpd_data[256];   /* in little-endian format */
12097         unsigned int i;
12098         u32 magic;
12099
12100         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
12101             tg3_nvram_read(tp, 0x0, &magic))
12102                 goto out_not_found;
12103
12104         if (magic == TG3_EEPROM_MAGIC) {
12105                 for (i = 0; i < 256; i += 4) {
12106                         u32 tmp;
12107
12108                         /* The data is in little-endian format in NVRAM.
12109                          * Use the big-endian read routines to preserve
12110                          * the byte order as it exists in NVRAM.
12111                          */
12112                         if (tg3_nvram_read_be32(tp, 0x100 + i, &tmp))
12113                                 goto out_not_found;
12114
12115                         memcpy(&vpd_data[i], &tmp, sizeof(tmp));
12116                 }
12117         } else {
12118                 int vpd_cap;
12119
12120                 vpd_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_VPD);
12121                 for (i = 0; i < 256; i += 4) {
12122                         u32 tmp, j = 0;
12123                         __le32 v;
12124                         u16 tmp16;
12125
12126                         pci_write_config_word(tp->pdev, vpd_cap + PCI_VPD_ADDR,
12127                                               i);
12128                         while (j++ < 100) {
12129                                 pci_read_config_word(tp->pdev, vpd_cap +
12130                                                      PCI_VPD_ADDR, &tmp16);
12131                                 if (tmp16 & 0x8000)
12132                                         break;
12133                                 msleep(1);
12134                         }
12135                         if (!(tmp16 & 0x8000))
12136                                 goto out_not_found;
12137
12138                         pci_read_config_dword(tp->pdev, vpd_cap + PCI_VPD_DATA,
12139                                               &tmp);
12140                         v = cpu_to_le32(tmp);
12141                         memcpy(&vpd_data[i], &v, sizeof(v));
12142                 }
12143         }
12144
12145         /* Now parse and find the part number. */
12146         for (i = 0; i < 254; ) {
12147                 unsigned char val = vpd_data[i];
12148                 unsigned int block_end;
12149
12150                 if (val == 0x82 || val == 0x91) {
12151                         i = (i + 3 +
12152                              (vpd_data[i + 1] +
12153                               (vpd_data[i + 2] << 8)));
12154                         continue;
12155                 }
12156
12157                 if (val != 0x90)
12158                         goto out_not_found;
12159
12160                 block_end = (i + 3 +
12161                              (vpd_data[i + 1] +
12162                               (vpd_data[i + 2] << 8)));
12163                 i += 3;
12164
12165                 if (block_end > 256)
12166                         goto out_not_found;
12167
12168                 while (i < (block_end - 2)) {
12169                         if (vpd_data[i + 0] == 'P' &&
12170                             vpd_data[i + 1] == 'N') {
12171                                 int partno_len = vpd_data[i + 2];
12172
12173                                 i += 3;
12174                                 if (partno_len > 24 || (partno_len + i) > 256)
12175                                         goto out_not_found;
12176
12177                                 memcpy(tp->board_part_number,
12178                                        &vpd_data[i], partno_len);
12179
12180                                 /* Success. */
12181                                 return;
12182                         }
12183                         i += 3 + vpd_data[i + 2];
12184                 }
12185
12186                 /* Part number not found. */
12187                 goto out_not_found;
12188         }
12189
12190 out_not_found:
12191         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12192                 strcpy(tp->board_part_number, "BCM95906");
12193         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12194                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
12195                 strcpy(tp->board_part_number, "BCM57780");
12196         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12197                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
12198                 strcpy(tp->board_part_number, "BCM57760");
12199         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12200                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
12201                 strcpy(tp->board_part_number, "BCM57790");
12202         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12203                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
12204                 strcpy(tp->board_part_number, "BCM57788");
12205         else
12206                 strcpy(tp->board_part_number, "none");
12207 }
12208
12209 static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
12210 {
12211         u32 val;
12212
12213         if (tg3_nvram_read(tp, offset, &val) ||
12214             (val & 0xfc000000) != 0x0c000000 ||
12215             tg3_nvram_read(tp, offset + 4, &val) ||
12216             val != 0)
12217                 return 0;
12218
12219         return 1;
12220 }
12221
12222 static void __devinit tg3_read_bc_ver(struct tg3 *tp)
12223 {
12224         u32 val, offset, start, ver_offset;
12225         int i;
12226         bool newver = false;
12227
12228         if (tg3_nvram_read(tp, 0xc, &offset) ||
12229             tg3_nvram_read(tp, 0x4, &start))
12230                 return;
12231
12232         offset = tg3_nvram_logical_addr(tp, offset);
12233
12234         if (tg3_nvram_read(tp, offset, &val))
12235                 return;
12236
12237         if ((val & 0xfc000000) == 0x0c000000) {
12238                 if (tg3_nvram_read(tp, offset + 4, &val))
12239                         return;
12240
12241                 if (val == 0)
12242                         newver = true;
12243         }
12244
12245         if (newver) {
12246                 if (tg3_nvram_read(tp, offset + 8, &ver_offset))
12247                         return;
12248
12249                 offset = offset + ver_offset - start;
12250                 for (i = 0; i < 16; i += 4) {
12251                         __be32 v;
12252                         if (tg3_nvram_read_be32(tp, offset + i, &v))
12253                                 return;
12254
12255                         memcpy(tp->fw_ver + i, &v, sizeof(v));
12256                 }
12257         } else {
12258                 u32 major, minor;
12259
12260                 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
12261                         return;
12262
12263                 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
12264                         TG3_NVM_BCVER_MAJSFT;
12265                 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
12266                 snprintf(&tp->fw_ver[0], 32, "v%d.%02d", major, minor);
12267         }
12268 }
12269
12270 static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
12271 {
12272         u32 val, major, minor;
12273
12274         /* Use native endian representation */
12275         if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
12276                 return;
12277
12278         major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
12279                 TG3_NVM_HWSB_CFG1_MAJSFT;
12280         minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
12281                 TG3_NVM_HWSB_CFG1_MINSFT;
12282
12283         snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
12284 }
12285
12286 static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
12287 {
12288         u32 offset, major, minor, build;
12289
12290         tp->fw_ver[0] = 's';
12291         tp->fw_ver[1] = 'b';
12292         tp->fw_ver[2] = '\0';
12293
12294         if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
12295                 return;
12296
12297         switch (val & TG3_EEPROM_SB_REVISION_MASK) {
12298         case TG3_EEPROM_SB_REVISION_0:
12299                 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
12300                 break;
12301         case TG3_EEPROM_SB_REVISION_2:
12302                 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
12303                 break;
12304         case TG3_EEPROM_SB_REVISION_3:
12305                 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
12306                 break;
12307         default:
12308                 return;
12309         }
12310
12311         if (tg3_nvram_read(tp, offset, &val))
12312                 return;
12313
12314         build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
12315                 TG3_EEPROM_SB_EDH_BLD_SHFT;
12316         major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
12317                 TG3_EEPROM_SB_EDH_MAJ_SHFT;
12318         minor =  val & TG3_EEPROM_SB_EDH_MIN_MASK;
12319
12320         if (minor > 99 || build > 26)
12321                 return;
12322
12323         snprintf(&tp->fw_ver[2], 30, " v%d.%02d", major, minor);
12324
12325         if (build > 0) {
12326                 tp->fw_ver[8] = 'a' + build - 1;
12327                 tp->fw_ver[9] = '\0';
12328         }
12329 }
12330
12331 static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
12332 {
12333         u32 val, offset, start;
12334         int i, vlen;
12335
12336         for (offset = TG3_NVM_DIR_START;
12337              offset < TG3_NVM_DIR_END;
12338              offset += TG3_NVM_DIRENT_SIZE) {
12339                 if (tg3_nvram_read(tp, offset, &val))
12340                         return;
12341
12342                 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
12343                         break;
12344         }
12345
12346         if (offset == TG3_NVM_DIR_END)
12347                 return;
12348
12349         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
12350                 start = 0x08000000;
12351         else if (tg3_nvram_read(tp, offset - 4, &start))
12352                 return;
12353
12354         if (tg3_nvram_read(tp, offset + 4, &offset) ||
12355             !tg3_fw_img_is_valid(tp, offset) ||
12356             tg3_nvram_read(tp, offset + 8, &val))
12357                 return;
12358
12359         offset += val - start;
12360
12361         vlen = strlen(tp->fw_ver);
12362
12363         tp->fw_ver[vlen++] = ',';
12364         tp->fw_ver[vlen++] = ' ';
12365
12366         for (i = 0; i < 4; i++) {
12367                 __be32 v;
12368                 if (tg3_nvram_read_be32(tp, offset, &v))
12369                         return;
12370
12371                 offset += sizeof(v);
12372
12373                 if (vlen > TG3_VER_SIZE - sizeof(v)) {
12374                         memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
12375                         break;
12376                 }
12377
12378                 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
12379                 vlen += sizeof(v);
12380         }
12381 }
12382
12383 static void __devinit tg3_read_dash_ver(struct tg3 *tp)
12384 {
12385         int vlen;
12386         u32 apedata;
12387
12388         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) ||
12389             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
12390                 return;
12391
12392         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
12393         if (apedata != APE_SEG_SIG_MAGIC)
12394                 return;
12395
12396         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
12397         if (!(apedata & APE_FW_STATUS_READY))
12398                 return;
12399
12400         apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
12401
12402         vlen = strlen(tp->fw_ver);
12403
12404         snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " DASH v%d.%d.%d.%d",
12405                  (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
12406                  (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
12407                  (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
12408                  (apedata & APE_FW_VERSION_BLDMSK));
12409 }
12410
12411 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
12412 {
12413         u32 val;
12414
12415         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) {
12416                 tp->fw_ver[0] = 's';
12417                 tp->fw_ver[1] = 'b';
12418                 tp->fw_ver[2] = '\0';
12419
12420                 return;
12421         }
12422
12423         if (tg3_nvram_read(tp, 0, &val))
12424                 return;
12425
12426         if (val == TG3_EEPROM_MAGIC)
12427                 tg3_read_bc_ver(tp);
12428         else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
12429                 tg3_read_sb_ver(tp, val);
12430         else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
12431                 tg3_read_hwsb_ver(tp);
12432         else
12433                 return;
12434
12435         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12436              (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
12437                 return;
12438
12439         tg3_read_mgmtfw_ver(tp);
12440
12441         tp->fw_ver[TG3_VER_SIZE - 1] = 0;
12442 }
12443
12444 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
12445
12446 static int __devinit tg3_get_invariants(struct tg3 *tp)
12447 {
12448         static struct pci_device_id write_reorder_chipsets[] = {
12449                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12450                              PCI_DEVICE_ID_AMD_FE_GATE_700C) },
12451                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12452                              PCI_DEVICE_ID_AMD_8131_BRIDGE) },
12453                 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
12454                              PCI_DEVICE_ID_VIA_8385_0) },
12455                 { },
12456         };
12457         u32 misc_ctrl_reg;
12458         u32 pci_state_reg, grc_misc_cfg;
12459         u32 val;
12460         u16 pci_cmd;
12461         int err;
12462
12463         /* Force memory write invalidate off.  If we leave it on,
12464          * then on 5700_BX chips we have to enable a workaround.
12465          * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
12466          * to match the cacheline size.  The Broadcom driver have this
12467          * workaround but turns MWI off all the times so never uses
12468          * it.  This seems to suggest that the workaround is insufficient.
12469          */
12470         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12471         pci_cmd &= ~PCI_COMMAND_INVALIDATE;
12472         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12473
12474         /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
12475          * has the register indirect write enable bit set before
12476          * we try to access any of the MMIO registers.  It is also
12477          * critical that the PCI-X hw workaround situation is decided
12478          * before that as well.
12479          */
12480         pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12481                               &misc_ctrl_reg);
12482
12483         tp->pci_chip_rev_id = (misc_ctrl_reg >>
12484                                MISC_HOST_CTRL_CHIPREV_SHIFT);
12485         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
12486                 u32 prod_id_asic_rev;
12487
12488                 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717C ||
12489                     tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717S ||
12490                     tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718C ||
12491                     tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718S)
12492                         pci_read_config_dword(tp->pdev,
12493                                               TG3PCI_GEN2_PRODID_ASICREV,
12494                                               &prod_id_asic_rev);
12495                 else
12496                         pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
12497                                               &prod_id_asic_rev);
12498
12499                 tp->pci_chip_rev_id = prod_id_asic_rev;
12500         }
12501
12502         /* Wrong chip ID in 5752 A0. This code can be removed later
12503          * as A0 is not in production.
12504          */
12505         if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
12506                 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
12507
12508         /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
12509          * we need to disable memory and use config. cycles
12510          * only to access all registers. The 5702/03 chips
12511          * can mistakenly decode the special cycles from the
12512          * ICH chipsets as memory write cycles, causing corruption
12513          * of register and memory space. Only certain ICH bridges
12514          * will drive special cycles with non-zero data during the
12515          * address phase which can fall within the 5703's address
12516          * range. This is not an ICH bug as the PCI spec allows
12517          * non-zero address during special cycles. However, only
12518          * these ICH bridges are known to drive non-zero addresses
12519          * during special cycles.
12520          *
12521          * Since special cycles do not cross PCI bridges, we only
12522          * enable this workaround if the 5703 is on the secondary
12523          * bus of these ICH bridges.
12524          */
12525         if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
12526             (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
12527                 static struct tg3_dev_id {
12528                         u32     vendor;
12529                         u32     device;
12530                         u32     rev;
12531                 } ich_chipsets[] = {
12532                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
12533                           PCI_ANY_ID },
12534                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
12535                           PCI_ANY_ID },
12536                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
12537                           0xa },
12538                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
12539                           PCI_ANY_ID },
12540                         { },
12541                 };
12542                 struct tg3_dev_id *pci_id = &ich_chipsets[0];
12543                 struct pci_dev *bridge = NULL;
12544
12545                 while (pci_id->vendor != 0) {
12546                         bridge = pci_get_device(pci_id->vendor, pci_id->device,
12547                                                 bridge);
12548                         if (!bridge) {
12549                                 pci_id++;
12550                                 continue;
12551                         }
12552                         if (pci_id->rev != PCI_ANY_ID) {
12553                                 if (bridge->revision > pci_id->rev)
12554                                         continue;
12555                         }
12556                         if (bridge->subordinate &&
12557                             (bridge->subordinate->number ==
12558                              tp->pdev->bus->number)) {
12559
12560                                 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
12561                                 pci_dev_put(bridge);
12562                                 break;
12563                         }
12564                 }
12565         }
12566
12567         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
12568                 static struct tg3_dev_id {
12569                         u32     vendor;
12570                         u32     device;
12571                 } bridge_chipsets[] = {
12572                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
12573                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
12574                         { },
12575                 };
12576                 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
12577                 struct pci_dev *bridge = NULL;
12578
12579                 while (pci_id->vendor != 0) {
12580                         bridge = pci_get_device(pci_id->vendor,
12581                                                 pci_id->device,
12582                                                 bridge);
12583                         if (!bridge) {
12584                                 pci_id++;
12585                                 continue;
12586                         }
12587                         if (bridge->subordinate &&
12588                             (bridge->subordinate->number <=
12589                              tp->pdev->bus->number) &&
12590                             (bridge->subordinate->subordinate >=
12591                              tp->pdev->bus->number)) {
12592                                 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
12593                                 pci_dev_put(bridge);
12594                                 break;
12595                         }
12596                 }
12597         }
12598
12599         /* The EPB bridge inside 5714, 5715, and 5780 cannot support
12600          * DMA addresses > 40-bit. This bridge may have other additional
12601          * 57xx devices behind it in some 4-port NIC designs for example.
12602          * Any tg3 device found behind the bridge will also need the 40-bit
12603          * DMA workaround.
12604          */
12605         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
12606             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
12607                 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
12608                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
12609                 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
12610         }
12611         else {
12612                 struct pci_dev *bridge = NULL;
12613
12614                 do {
12615                         bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
12616                                                 PCI_DEVICE_ID_SERVERWORKS_EPB,
12617                                                 bridge);
12618                         if (bridge && bridge->subordinate &&
12619                             (bridge->subordinate->number <=
12620                              tp->pdev->bus->number) &&
12621                             (bridge->subordinate->subordinate >=
12622                              tp->pdev->bus->number)) {
12623                                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
12624                                 pci_dev_put(bridge);
12625                                 break;
12626                         }
12627                 } while (bridge);
12628         }
12629
12630         /* Initialize misc host control in PCI block. */
12631         tp->misc_host_ctrl |= (misc_ctrl_reg &
12632                                MISC_HOST_CTRL_CHIPREV);
12633         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12634                                tp->misc_host_ctrl);
12635
12636         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
12637             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
12638             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
12639                 tp->pdev_peer = tg3_find_peer(tp);
12640
12641         /* Intentionally exclude ASIC_REV_5906 */
12642         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12643             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
12644             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12645             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
12646             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12647             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
12648             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
12649                 tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
12650
12651         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
12652             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
12653             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
12654             (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
12655             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
12656                 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
12657
12658         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
12659             (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
12660                 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
12661
12662         /* 5700 B0 chips do not support checksumming correctly due
12663          * to hardware bugs.
12664          */
12665         if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
12666                 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
12667         else {
12668                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
12669                 tp->dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
12670                 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
12671                         tp->dev->features |= NETIF_F_IPV6_CSUM;
12672         }
12673
12674         /* Determine TSO capabilities */
12675         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
12676                 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_3;
12677         else if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
12678                  GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12679                 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
12680         else if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
12681                 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
12682                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 &&
12683                     tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
12684                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
12685         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
12686                    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
12687                    tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
12688                 tp->tg3_flags2 |= TG3_FLG2_TSO_BUG;
12689                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
12690                         tp->fw_needed = FIRMWARE_TG3TSO5;
12691                 else
12692                         tp->fw_needed = FIRMWARE_TG3TSO;
12693         }
12694
12695         tp->irq_max = 1;
12696
12697         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
12698                 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
12699                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
12700                     GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
12701                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
12702                      tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
12703                      tp->pdev_peer == tp->pdev))
12704                         tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
12705
12706                 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
12707                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12708                         tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
12709                 }
12710
12711                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
12712                         tp->tg3_flags |= TG3_FLAG_SUPPORT_MSIX;
12713                         tp->irq_max = TG3_IRQ_MAX_VECS;
12714                 }
12715         }
12716
12717         if (!(tp->tg3_flags3 & TG3_FLG3_5755_PLUS)) {
12718                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12719                         tp->tg3_flags3 |= TG3_FLG3_SHORT_DMA_BUG;
12720                 else {
12721                         tp->tg3_flags3 |= TG3_FLG3_4G_DMA_BNDRY_BUG;
12722                         tp->tg3_flags3 |= TG3_FLG3_40BIT_DMA_LIMIT_BUG;
12723                 }
12724         }
12725
12726         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
12727              (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
12728             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
12729                 tp->tg3_flags |= TG3_FLAG_JUMBO_CAPABLE;
12730
12731         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
12732                               &pci_state_reg);
12733
12734         tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
12735         if (tp->pcie_cap != 0) {
12736                 u16 lnkctl;
12737
12738                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
12739
12740                 pcie_set_readrq(tp->pdev, 4096);
12741
12742                 pci_read_config_word(tp->pdev,
12743                                      tp->pcie_cap + PCI_EXP_LNKCTL,
12744                                      &lnkctl);
12745                 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
12746                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12747                                 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
12748                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12749                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
12750                             tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
12751                             tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
12752                                 tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
12753                 }
12754         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
12755                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
12756         } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
12757                    (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
12758                 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
12759                 if (!tp->pcix_cap) {
12760                         printk(KERN_ERR PFX "Cannot find PCI-X "
12761                                             "capability, aborting.\n");
12762                         return -EIO;
12763                 }
12764
12765                 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
12766                         tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
12767         }
12768
12769         /* If we have an AMD 762 or VIA K8T800 chipset, write
12770          * reordering to the mailbox registers done by the host
12771          * controller can cause major troubles.  We read back from
12772          * every mailbox register write to force the writes to be
12773          * posted to the chip in order.
12774          */
12775         if (pci_dev_present(write_reorder_chipsets) &&
12776             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
12777                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
12778
12779         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
12780                              &tp->pci_cacheline_sz);
12781         pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
12782                              &tp->pci_lat_timer);
12783         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
12784             tp->pci_lat_timer < 64) {
12785                 tp->pci_lat_timer = 64;
12786                 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
12787                                       tp->pci_lat_timer);
12788         }
12789
12790         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
12791                 /* 5700 BX chips need to have their TX producer index
12792                  * mailboxes written twice to workaround a bug.
12793                  */
12794                 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
12795
12796                 /* If we are in PCI-X mode, enable register write workaround.
12797                  *
12798                  * The workaround is to use indirect register accesses
12799                  * for all chip writes not to mailbox registers.
12800                  */
12801                 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
12802                         u32 pm_reg;
12803
12804                         tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
12805
12806                         /* The chip can have it's power management PCI config
12807                          * space registers clobbered due to this bug.
12808                          * So explicitly force the chip into D0 here.
12809                          */
12810                         pci_read_config_dword(tp->pdev,
12811                                               tp->pm_cap + PCI_PM_CTRL,
12812                                               &pm_reg);
12813                         pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
12814                         pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
12815                         pci_write_config_dword(tp->pdev,
12816                                                tp->pm_cap + PCI_PM_CTRL,
12817                                                pm_reg);
12818
12819                         /* Also, force SERR#/PERR# in PCI command. */
12820                         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12821                         pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
12822                         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12823                 }
12824         }
12825
12826         if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
12827                 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
12828         if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
12829                 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
12830
12831         /* Chip-specific fixup from Broadcom driver */
12832         if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
12833             (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
12834                 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
12835                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
12836         }
12837
12838         /* Default fast path register access methods */
12839         tp->read32 = tg3_read32;
12840         tp->write32 = tg3_write32;
12841         tp->read32_mbox = tg3_read32;
12842         tp->write32_mbox = tg3_write32;
12843         tp->write32_tx_mbox = tg3_write32;
12844         tp->write32_rx_mbox = tg3_write32;
12845
12846         /* Various workaround register access methods */
12847         if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
12848                 tp->write32 = tg3_write_indirect_reg32;
12849         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
12850                  ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
12851                   tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
12852                 /*
12853                  * Back to back register writes can cause problems on these
12854                  * chips, the workaround is to read back all reg writes
12855                  * except those to mailbox regs.
12856                  *
12857                  * See tg3_write_indirect_reg32().
12858                  */
12859                 tp->write32 = tg3_write_flush_reg32;
12860         }
12861
12862         if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
12863             (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
12864                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
12865                 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
12866                         tp->write32_rx_mbox = tg3_write_flush_reg32;
12867         }
12868
12869         if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
12870                 tp->read32 = tg3_read_indirect_reg32;
12871                 tp->write32 = tg3_write_indirect_reg32;
12872                 tp->read32_mbox = tg3_read_indirect_mbox;
12873                 tp->write32_mbox = tg3_write_indirect_mbox;
12874                 tp->write32_tx_mbox = tg3_write_indirect_mbox;
12875                 tp->write32_rx_mbox = tg3_write_indirect_mbox;
12876
12877                 iounmap(tp->regs);
12878                 tp->regs = NULL;
12879
12880                 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12881                 pci_cmd &= ~PCI_COMMAND_MEMORY;
12882                 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12883         }
12884         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12885                 tp->read32_mbox = tg3_read32_mbox_5906;
12886                 tp->write32_mbox = tg3_write32_mbox_5906;
12887                 tp->write32_tx_mbox = tg3_write32_mbox_5906;
12888                 tp->write32_rx_mbox = tg3_write32_mbox_5906;
12889         }
12890
12891         if (tp->write32 == tg3_write_indirect_reg32 ||
12892             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
12893              (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12894               GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
12895                 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
12896
12897         /* Get eeprom hw config before calling tg3_set_power_state().
12898          * In particular, the TG3_FLG2_IS_NIC flag must be
12899          * determined before calling tg3_set_power_state() so that
12900          * we know whether or not to switch out of Vaux power.
12901          * When the flag is set, it means that GPIO1 is used for eeprom
12902          * write protect and also implies that it is a LOM where GPIOs
12903          * are not used to switch power.
12904          */
12905         tg3_get_eeprom_hw_cfg(tp);
12906
12907         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
12908                 /* Allow reads and writes to the
12909                  * APE register and memory space.
12910                  */
12911                 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
12912                                  PCISTATE_ALLOW_APE_SHMEM_WR;
12913                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
12914                                        pci_state_reg);
12915         }
12916
12917         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12918             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
12919             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12920             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
12921             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
12922                 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
12923
12924         /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
12925          * GPIO1 driven high will bring 5700's external PHY out of reset.
12926          * It is also used as eeprom write protect on LOMs.
12927          */
12928         tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
12929         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
12930             (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
12931                 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
12932                                        GRC_LCLCTRL_GPIO_OUTPUT1);
12933         /* Unused GPIO3 must be driven as output on 5752 because there
12934          * are no pull-up resistors on unused GPIO pins.
12935          */
12936         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
12937                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
12938
12939         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12940             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
12941                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
12942
12943         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
12944             tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
12945                 /* Turn off the debug UART. */
12946                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
12947                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
12948                         /* Keep VMain power. */
12949                         tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
12950                                               GRC_LCLCTRL_GPIO_OUTPUT0;
12951         }
12952
12953         /* Force the chip into D0. */
12954         err = tg3_set_power_state(tp, PCI_D0);
12955         if (err) {
12956                 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
12957                        pci_name(tp->pdev));
12958                 return err;
12959         }
12960
12961         /* Derive initial jumbo mode from MTU assigned in
12962          * ether_setup() via the alloc_etherdev() call
12963          */
12964         if (tp->dev->mtu > ETH_DATA_LEN &&
12965             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
12966                 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
12967
12968         /* Determine WakeOnLan speed to use. */
12969         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12970             tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12971             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
12972             tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
12973                 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
12974         } else {
12975                 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
12976         }
12977
12978         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12979                 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
12980
12981         /* A few boards don't want Ethernet@WireSpeed phy feature */
12982         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
12983             ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
12984              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
12985              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
12986             (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) ||
12987             (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
12988                 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
12989
12990         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
12991             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
12992                 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
12993         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
12994                 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
12995
12996         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
12997             !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
12998             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
12999             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 &&
13000             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) {
13001                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13002                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
13003                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13004                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
13005                         if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
13006                             tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
13007                                 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
13008                         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
13009                                 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
13010                 } else
13011                         tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
13012         }
13013
13014         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13015             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
13016                 tp->phy_otp = tg3_read_otp_phycfg(tp);
13017                 if (tp->phy_otp == 0)
13018                         tp->phy_otp = TG3_OTP_DEFAULT;
13019         }
13020
13021         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
13022                 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
13023         else
13024                 tp->mi_mode = MAC_MI_MODE_BASE;
13025
13026         tp->coalesce_mode = 0;
13027         if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
13028             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
13029                 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
13030
13031         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13032             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
13033                 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
13034
13035         err = tg3_mdio_init(tp);
13036         if (err)
13037                 return err;
13038
13039         /* Initialize data/descriptor byte/word swapping. */
13040         val = tr32(GRC_MODE);
13041         val &= GRC_MODE_HOST_STACKUP;
13042         tw32(GRC_MODE, val | tp->grc_mode);
13043
13044         tg3_switch_clocks(tp);
13045
13046         /* Clear this out for sanity. */
13047         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
13048
13049         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13050                               &pci_state_reg);
13051         if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
13052             (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
13053                 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
13054
13055                 if (chiprevid == CHIPREV_ID_5701_A0 ||
13056                     chiprevid == CHIPREV_ID_5701_B0 ||
13057                     chiprevid == CHIPREV_ID_5701_B2 ||
13058                     chiprevid == CHIPREV_ID_5701_B5) {
13059                         void __iomem *sram_base;
13060
13061                         /* Write some dummy words into the SRAM status block
13062                          * area, see if it reads back correctly.  If the return
13063                          * value is bad, force enable the PCIX workaround.
13064                          */
13065                         sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
13066
13067                         writel(0x00000000, sram_base);
13068                         writel(0x00000000, sram_base + 4);
13069                         writel(0xffffffff, sram_base + 4);
13070                         if (readl(sram_base) != 0x00000000)
13071                                 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13072                 }
13073         }
13074
13075         udelay(50);
13076         tg3_nvram_init(tp);
13077
13078         grc_misc_cfg = tr32(GRC_MISC_CFG);
13079         grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
13080
13081         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13082             (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
13083              grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
13084                 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
13085
13086         if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
13087             (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
13088                 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
13089         if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
13090                 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
13091                                       HOSTCC_MODE_CLRTICK_TXBD);
13092
13093                 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
13094                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13095                                        tp->misc_host_ctrl);
13096         }
13097
13098         /* Preserve the APE MAC_MODE bits */
13099         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
13100                 tp->mac_mode = tr32(MAC_MODE) |
13101                                MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
13102         else
13103                 tp->mac_mode = TG3_DEF_MAC_MODE;
13104
13105         /* these are limited to 10/100 only */
13106         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13107              (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
13108             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13109              tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13110              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
13111               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
13112               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
13113             (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13114              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
13115               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
13116               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
13117             tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
13118             (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
13119                 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
13120
13121         err = tg3_phy_probe(tp);
13122         if (err) {
13123                 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
13124                        pci_name(tp->pdev), err);
13125                 /* ... but do not return immediately ... */
13126                 tg3_mdio_fini(tp);
13127         }
13128
13129         tg3_read_partno(tp);
13130         tg3_read_fw_ver(tp);
13131
13132         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
13133                 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
13134         } else {
13135                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13136                         tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
13137                 else
13138                         tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
13139         }
13140
13141         /* 5700 {AX,BX} chips have a broken status block link
13142          * change bit implementation, so we must use the
13143          * status register in those cases.
13144          */
13145         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13146                 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
13147         else
13148                 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
13149
13150         /* The led_ctrl is set during tg3_phy_probe, here we might
13151          * have to force the link status polling mechanism based
13152          * upon subsystem IDs.
13153          */
13154         if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
13155             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13156             !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
13157                 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
13158                                   TG3_FLAG_USE_LINKCHG_REG);
13159         }
13160
13161         /* For all SERDES we poll the MAC status register. */
13162         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
13163                 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
13164         else
13165                 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
13166
13167         tp->rx_offset = NET_IP_ALIGN;
13168         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13169             (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
13170                 tp->rx_offset = 0;
13171
13172         tp->rx_std_max_post = TG3_RX_RING_SIZE;
13173
13174         /* Increment the rx prod index on the rx std ring by at most
13175          * 8 for these chips to workaround hw errata.
13176          */
13177         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13178             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13179             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
13180                 tp->rx_std_max_post = 8;
13181
13182         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
13183                 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
13184                                      PCIE_PWR_MGMT_L1_THRESH_MSK;
13185
13186         return err;
13187 }
13188
13189 #ifdef CONFIG_SPARC
13190 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
13191 {
13192         struct net_device *dev = tp->dev;
13193         struct pci_dev *pdev = tp->pdev;
13194         struct device_node *dp = pci_device_to_OF_node(pdev);
13195         const unsigned char *addr;
13196         int len;
13197
13198         addr = of_get_property(dp, "local-mac-address", &len);
13199         if (addr && len == 6) {
13200                 memcpy(dev->dev_addr, addr, 6);
13201                 memcpy(dev->perm_addr, dev->dev_addr, 6);
13202                 return 0;
13203         }
13204         return -ENODEV;
13205 }
13206
13207 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
13208 {
13209         struct net_device *dev = tp->dev;
13210
13211         memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
13212         memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
13213         return 0;
13214 }
13215 #endif
13216
13217 static int __devinit tg3_get_device_address(struct tg3 *tp)
13218 {
13219         struct net_device *dev = tp->dev;
13220         u32 hi, lo, mac_offset;
13221         int addr_ok = 0;
13222
13223 #ifdef CONFIG_SPARC
13224         if (!tg3_get_macaddr_sparc(tp))
13225                 return 0;
13226 #endif
13227
13228         mac_offset = 0x7c;
13229         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
13230             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13231                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
13232                         mac_offset = 0xcc;
13233                 if (tg3_nvram_lock(tp))
13234                         tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
13235                 else
13236                         tg3_nvram_unlock(tp);
13237         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
13238                 if (tr32(TG3_CPMU_STATUS) & TG3_CPMU_STATUS_PCIE_FUNC)
13239                         mac_offset = 0xcc;
13240         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13241                 mac_offset = 0x10;
13242
13243         /* First try to get it from MAC address mailbox. */
13244         tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
13245         if ((hi >> 16) == 0x484b) {
13246                 dev->dev_addr[0] = (hi >>  8) & 0xff;
13247                 dev->dev_addr[1] = (hi >>  0) & 0xff;
13248
13249                 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
13250                 dev->dev_addr[2] = (lo >> 24) & 0xff;
13251                 dev->dev_addr[3] = (lo >> 16) & 0xff;
13252                 dev->dev_addr[4] = (lo >>  8) & 0xff;
13253                 dev->dev_addr[5] = (lo >>  0) & 0xff;
13254
13255                 /* Some old bootcode may report a 0 MAC address in SRAM */
13256                 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
13257         }
13258         if (!addr_ok) {
13259                 /* Next, try NVRAM. */
13260                 if (!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) &&
13261                     !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
13262                     !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
13263                         memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
13264                         memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
13265                 }
13266                 /* Finally just fetch it out of the MAC control regs. */
13267                 else {
13268                         hi = tr32(MAC_ADDR_0_HIGH);
13269                         lo = tr32(MAC_ADDR_0_LOW);
13270
13271                         dev->dev_addr[5] = lo & 0xff;
13272                         dev->dev_addr[4] = (lo >> 8) & 0xff;
13273                         dev->dev_addr[3] = (lo >> 16) & 0xff;
13274                         dev->dev_addr[2] = (lo >> 24) & 0xff;
13275                         dev->dev_addr[1] = hi & 0xff;
13276                         dev->dev_addr[0] = (hi >> 8) & 0xff;
13277                 }
13278         }
13279
13280         if (!is_valid_ether_addr(&dev->dev_addr[0])) {
13281 #ifdef CONFIG_SPARC
13282                 if (!tg3_get_default_macaddr_sparc(tp))
13283                         return 0;
13284 #endif
13285                 return -EINVAL;
13286         }
13287         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
13288         return 0;
13289 }
13290
13291 #define BOUNDARY_SINGLE_CACHELINE       1
13292 #define BOUNDARY_MULTI_CACHELINE        2
13293
13294 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
13295 {
13296         int cacheline_size;
13297         u8 byte;
13298         int goal;
13299
13300         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
13301         if (byte == 0)
13302                 cacheline_size = 1024;
13303         else
13304                 cacheline_size = (int) byte * 4;
13305
13306         /* On 5703 and later chips, the boundary bits have no
13307          * effect.
13308          */
13309         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13310             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13311             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13312                 goto out;
13313
13314 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
13315         goal = BOUNDARY_MULTI_CACHELINE;
13316 #else
13317 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
13318         goal = BOUNDARY_SINGLE_CACHELINE;
13319 #else
13320         goal = 0;
13321 #endif
13322 #endif
13323
13324         if (!goal)
13325                 goto out;
13326
13327         /* PCI controllers on most RISC systems tend to disconnect
13328          * when a device tries to burst across a cache-line boundary.
13329          * Therefore, letting tg3 do so just wastes PCI bandwidth.
13330          *
13331          * Unfortunately, for PCI-E there are only limited
13332          * write-side controls for this, and thus for reads
13333          * we will still get the disconnects.  We'll also waste
13334          * these PCI cycles for both read and write for chips
13335          * other than 5700 and 5701 which do not implement the
13336          * boundary bits.
13337          */
13338         if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13339             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
13340                 switch (cacheline_size) {
13341                 case 16:
13342                 case 32:
13343                 case 64:
13344                 case 128:
13345                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13346                                 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
13347                                         DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
13348                         } else {
13349                                 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13350                                         DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13351                         }
13352                         break;
13353
13354                 case 256:
13355                         val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
13356                                 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
13357                         break;
13358
13359                 default:
13360                         val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13361                                 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13362                         break;
13363                 }
13364         } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13365                 switch (cacheline_size) {
13366                 case 16:
13367                 case 32:
13368                 case 64:
13369                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13370                                 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13371                                 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
13372                                 break;
13373                         }
13374                         /* fallthrough */
13375                 case 128:
13376                 default:
13377                         val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13378                         val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
13379                         break;
13380                 }
13381         } else {
13382                 switch (cacheline_size) {
13383                 case 16:
13384                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13385                                 val |= (DMA_RWCTRL_READ_BNDRY_16 |
13386                                         DMA_RWCTRL_WRITE_BNDRY_16);
13387                                 break;
13388                         }
13389                         /* fallthrough */
13390                 case 32:
13391                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13392                                 val |= (DMA_RWCTRL_READ_BNDRY_32 |
13393                                         DMA_RWCTRL_WRITE_BNDRY_32);
13394                                 break;
13395                         }
13396                         /* fallthrough */
13397                 case 64:
13398                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13399                                 val |= (DMA_RWCTRL_READ_BNDRY_64 |
13400                                         DMA_RWCTRL_WRITE_BNDRY_64);
13401                                 break;
13402                         }
13403                         /* fallthrough */
13404                 case 128:
13405                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13406                                 val |= (DMA_RWCTRL_READ_BNDRY_128 |
13407                                         DMA_RWCTRL_WRITE_BNDRY_128);
13408                                 break;
13409                         }
13410                         /* fallthrough */
13411                 case 256:
13412                         val |= (DMA_RWCTRL_READ_BNDRY_256 |
13413                                 DMA_RWCTRL_WRITE_BNDRY_256);
13414                         break;
13415                 case 512:
13416                         val |= (DMA_RWCTRL_READ_BNDRY_512 |
13417                                 DMA_RWCTRL_WRITE_BNDRY_512);
13418                         break;
13419                 case 1024:
13420                 default:
13421                         val |= (DMA_RWCTRL_READ_BNDRY_1024 |
13422                                 DMA_RWCTRL_WRITE_BNDRY_1024);
13423                         break;
13424                 }
13425         }
13426
13427 out:
13428         return val;
13429 }
13430
13431 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
13432 {
13433         struct tg3_internal_buffer_desc test_desc;
13434         u32 sram_dma_descs;
13435         int i, ret;
13436
13437         sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
13438
13439         tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
13440         tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
13441         tw32(RDMAC_STATUS, 0);
13442         tw32(WDMAC_STATUS, 0);
13443
13444         tw32(BUFMGR_MODE, 0);
13445         tw32(FTQ_RESET, 0);
13446
13447         test_desc.addr_hi = ((u64) buf_dma) >> 32;
13448         test_desc.addr_lo = buf_dma & 0xffffffff;
13449         test_desc.nic_mbuf = 0x00002100;
13450         test_desc.len = size;
13451
13452         /*
13453          * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
13454          * the *second* time the tg3 driver was getting loaded after an
13455          * initial scan.
13456          *
13457          * Broadcom tells me:
13458          *   ...the DMA engine is connected to the GRC block and a DMA
13459          *   reset may affect the GRC block in some unpredictable way...
13460          *   The behavior of resets to individual blocks has not been tested.
13461          *
13462          * Broadcom noted the GRC reset will also reset all sub-components.
13463          */
13464         if (to_device) {
13465                 test_desc.cqid_sqid = (13 << 8) | 2;
13466
13467                 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
13468                 udelay(40);
13469         } else {
13470                 test_desc.cqid_sqid = (16 << 8) | 7;
13471
13472                 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
13473                 udelay(40);
13474         }
13475         test_desc.flags = 0x00000005;
13476
13477         for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
13478                 u32 val;
13479
13480                 val = *(((u32 *)&test_desc) + i);
13481                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
13482                                        sram_dma_descs + (i * sizeof(u32)));
13483                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
13484         }
13485         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
13486
13487         if (to_device) {
13488                 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
13489         } else {
13490                 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
13491         }
13492
13493         ret = -ENODEV;
13494         for (i = 0; i < 40; i++) {
13495                 u32 val;
13496
13497                 if (to_device)
13498                         val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
13499                 else
13500                         val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
13501                 if ((val & 0xffff) == sram_dma_descs) {
13502                         ret = 0;
13503                         break;
13504                 }
13505
13506                 udelay(100);
13507         }
13508
13509         return ret;
13510 }
13511
13512 #define TEST_BUFFER_SIZE        0x2000
13513
13514 static int __devinit tg3_test_dma(struct tg3 *tp)
13515 {
13516         dma_addr_t buf_dma;
13517         u32 *buf, saved_dma_rwctrl;
13518         int ret;
13519
13520         buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
13521         if (!buf) {
13522                 ret = -ENOMEM;
13523                 goto out_nofree;
13524         }
13525
13526         tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
13527                           (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
13528
13529         tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
13530
13531         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13532                 /* DMA read watermark not used on PCIE */
13533                 tp->dma_rwctrl |= 0x00180000;
13534         } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
13535                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
13536                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
13537                         tp->dma_rwctrl |= 0x003f0000;
13538                 else
13539                         tp->dma_rwctrl |= 0x003f000f;
13540         } else {
13541                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13542                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
13543                         u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
13544                         u32 read_water = 0x7;
13545
13546                         /* If the 5704 is behind the EPB bridge, we can
13547                          * do the less restrictive ONE_DMA workaround for
13548                          * better performance.
13549                          */
13550                         if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
13551                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13552                                 tp->dma_rwctrl |= 0x8000;
13553                         else if (ccval == 0x6 || ccval == 0x7)
13554                                 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
13555
13556                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
13557                                 read_water = 4;
13558                         /* Set bit 23 to enable PCIX hw bug fix */
13559                         tp->dma_rwctrl |=
13560                                 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
13561                                 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
13562                                 (1 << 23);
13563                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
13564                         /* 5780 always in PCIX mode */
13565                         tp->dma_rwctrl |= 0x00144000;
13566                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
13567                         /* 5714 always in PCIX mode */
13568                         tp->dma_rwctrl |= 0x00148000;
13569                 } else {
13570                         tp->dma_rwctrl |= 0x001b000f;
13571                 }
13572         }
13573
13574         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13575             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13576                 tp->dma_rwctrl &= 0xfffffff0;
13577
13578         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13579             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
13580                 /* Remove this if it causes problems for some boards. */
13581                 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
13582
13583                 /* On 5700/5701 chips, we need to set this bit.
13584                  * Otherwise the chip will issue cacheline transactions
13585                  * to streamable DMA memory with not all the byte
13586                  * enables turned on.  This is an error on several
13587                  * RISC PCI controllers, in particular sparc64.
13588                  *
13589                  * On 5703/5704 chips, this bit has been reassigned
13590                  * a different meaning.  In particular, it is used
13591                  * on those chips to enable a PCI-X workaround.
13592                  */
13593                 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
13594         }
13595
13596         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13597
13598 #if 0
13599         /* Unneeded, already done by tg3_get_invariants.  */
13600         tg3_switch_clocks(tp);
13601 #endif
13602
13603         ret = 0;
13604         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13605             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
13606                 goto out;
13607
13608         /* It is best to perform DMA test with maximum write burst size
13609          * to expose the 5700/5701 write DMA bug.
13610          */
13611         saved_dma_rwctrl = tp->dma_rwctrl;
13612         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
13613         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13614
13615         while (1) {
13616                 u32 *p = buf, i;
13617
13618                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
13619                         p[i] = i;
13620
13621                 /* Send the buffer to the chip. */
13622                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
13623                 if (ret) {
13624                         printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
13625                         break;
13626                 }
13627
13628 #if 0
13629                 /* validate data reached card RAM correctly. */
13630                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
13631                         u32 val;
13632                         tg3_read_mem(tp, 0x2100 + (i*4), &val);
13633                         if (le32_to_cpu(val) != p[i]) {
13634                                 printk(KERN_ERR "  tg3_test_dma()  Card buffer corrupted on write! (%d != %d)\n", val, i);
13635                                 /* ret = -ENODEV here? */
13636                         }
13637                         p[i] = 0;
13638                 }
13639 #endif
13640                 /* Now read it back. */
13641                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
13642                 if (ret) {
13643                         printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
13644
13645                         break;
13646                 }
13647
13648                 /* Verify it. */
13649                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
13650                         if (p[i] == i)
13651                                 continue;
13652
13653                         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
13654                             DMA_RWCTRL_WRITE_BNDRY_16) {
13655                                 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
13656                                 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
13657                                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13658                                 break;
13659                         } else {
13660                                 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
13661                                 ret = -ENODEV;
13662                                 goto out;
13663                         }
13664                 }
13665
13666                 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
13667                         /* Success. */
13668                         ret = 0;
13669                         break;
13670                 }
13671         }
13672         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
13673             DMA_RWCTRL_WRITE_BNDRY_16) {
13674                 static struct pci_device_id dma_wait_state_chipsets[] = {
13675                         { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
13676                                      PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
13677                         { },
13678                 };
13679
13680                 /* DMA test passed without adjusting DMA boundary,
13681                  * now look for chipsets that are known to expose the
13682                  * DMA bug without failing the test.
13683                  */
13684                 if (pci_dev_present(dma_wait_state_chipsets)) {
13685                         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
13686                         tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
13687                 }
13688                 else
13689                         /* Safe to use the calculated DMA boundary. */
13690                         tp->dma_rwctrl = saved_dma_rwctrl;
13691
13692                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13693         }
13694
13695 out:
13696         pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
13697 out_nofree:
13698         return ret;
13699 }
13700
13701 static void __devinit tg3_init_link_config(struct tg3 *tp)
13702 {
13703         tp->link_config.advertising =
13704                 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
13705                  ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
13706                  ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
13707                  ADVERTISED_Autoneg | ADVERTISED_MII);
13708         tp->link_config.speed = SPEED_INVALID;
13709         tp->link_config.duplex = DUPLEX_INVALID;
13710         tp->link_config.autoneg = AUTONEG_ENABLE;
13711         tp->link_config.active_speed = SPEED_INVALID;
13712         tp->link_config.active_duplex = DUPLEX_INVALID;
13713         tp->link_config.phy_is_low_power = 0;
13714         tp->link_config.orig_speed = SPEED_INVALID;
13715         tp->link_config.orig_duplex = DUPLEX_INVALID;
13716         tp->link_config.orig_autoneg = AUTONEG_INVALID;
13717 }
13718
13719 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
13720 {
13721         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS &&
13722             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) {
13723                 tp->bufmgr_config.mbuf_read_dma_low_water =
13724                         DEFAULT_MB_RDMA_LOW_WATER_5705;
13725                 tp->bufmgr_config.mbuf_mac_rx_low_water =
13726                         DEFAULT_MB_MACRX_LOW_WATER_5705;
13727                 tp->bufmgr_config.mbuf_high_water =
13728                         DEFAULT_MB_HIGH_WATER_5705;
13729                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13730                         tp->bufmgr_config.mbuf_mac_rx_low_water =
13731                                 DEFAULT_MB_MACRX_LOW_WATER_5906;
13732                         tp->bufmgr_config.mbuf_high_water =
13733                                 DEFAULT_MB_HIGH_WATER_5906;
13734                 }
13735
13736                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
13737                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
13738                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
13739                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
13740                 tp->bufmgr_config.mbuf_high_water_jumbo =
13741                         DEFAULT_MB_HIGH_WATER_JUMBO_5780;
13742         } else {
13743                 tp->bufmgr_config.mbuf_read_dma_low_water =
13744                         DEFAULT_MB_RDMA_LOW_WATER;
13745                 tp->bufmgr_config.mbuf_mac_rx_low_water =
13746                         DEFAULT_MB_MACRX_LOW_WATER;
13747                 tp->bufmgr_config.mbuf_high_water =
13748                         DEFAULT_MB_HIGH_WATER;
13749
13750                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
13751                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
13752                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
13753                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
13754                 tp->bufmgr_config.mbuf_high_water_jumbo =
13755                         DEFAULT_MB_HIGH_WATER_JUMBO;
13756         }
13757
13758         tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
13759         tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
13760 }
13761
13762 static char * __devinit tg3_phy_string(struct tg3 *tp)
13763 {
13764         switch (tp->phy_id & PHY_ID_MASK) {
13765         case PHY_ID_BCM5400:    return "5400";
13766         case PHY_ID_BCM5401:    return "5401";
13767         case PHY_ID_BCM5411:    return "5411";
13768         case PHY_ID_BCM5701:    return "5701";
13769         case PHY_ID_BCM5703:    return "5703";
13770         case PHY_ID_BCM5704:    return "5704";
13771         case PHY_ID_BCM5705:    return "5705";
13772         case PHY_ID_BCM5750:    return "5750";
13773         case PHY_ID_BCM5752:    return "5752";
13774         case PHY_ID_BCM5714:    return "5714";
13775         case PHY_ID_BCM5780:    return "5780";
13776         case PHY_ID_BCM5755:    return "5755";
13777         case PHY_ID_BCM5787:    return "5787";
13778         case PHY_ID_BCM5784:    return "5784";
13779         case PHY_ID_BCM5756:    return "5722/5756";
13780         case PHY_ID_BCM5906:    return "5906";
13781         case PHY_ID_BCM5761:    return "5761";
13782         case PHY_ID_BCM5717:    return "5717";
13783         case PHY_ID_BCM8002:    return "8002/serdes";
13784         case 0:                 return "serdes";
13785         default:                return "unknown";
13786         }
13787 }
13788
13789 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
13790 {
13791         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13792                 strcpy(str, "PCI Express");
13793                 return str;
13794         } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
13795                 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
13796
13797                 strcpy(str, "PCIX:");
13798
13799                 if ((clock_ctrl == 7) ||
13800                     ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
13801                      GRC_MISC_CFG_BOARD_ID_5704CIOBE))
13802                         strcat(str, "133MHz");
13803                 else if (clock_ctrl == 0)
13804                         strcat(str, "33MHz");
13805                 else if (clock_ctrl == 2)
13806                         strcat(str, "50MHz");
13807                 else if (clock_ctrl == 4)
13808                         strcat(str, "66MHz");
13809                 else if (clock_ctrl == 6)
13810                         strcat(str, "100MHz");
13811         } else {
13812                 strcpy(str, "PCI:");
13813                 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
13814                         strcat(str, "66MHz");
13815                 else
13816                         strcat(str, "33MHz");
13817         }
13818         if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
13819                 strcat(str, ":32-bit");
13820         else
13821                 strcat(str, ":64-bit");
13822         return str;
13823 }
13824
13825 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
13826 {
13827         struct pci_dev *peer;
13828         unsigned int func, devnr = tp->pdev->devfn & ~7;
13829
13830         for (func = 0; func < 8; func++) {
13831                 peer = pci_get_slot(tp->pdev->bus, devnr | func);
13832                 if (peer && peer != tp->pdev)
13833                         break;
13834                 pci_dev_put(peer);
13835         }
13836         /* 5704 can be configured in single-port mode, set peer to
13837          * tp->pdev in that case.
13838          */
13839         if (!peer) {
13840                 peer = tp->pdev;
13841                 return peer;
13842         }
13843
13844         /*
13845          * We don't need to keep the refcount elevated; there's no way
13846          * to remove one half of this device without removing the other
13847          */
13848         pci_dev_put(peer);
13849
13850         return peer;
13851 }
13852
13853 static void __devinit tg3_init_coal(struct tg3 *tp)
13854 {
13855         struct ethtool_coalesce *ec = &tp->coal;
13856
13857         memset(ec, 0, sizeof(*ec));
13858         ec->cmd = ETHTOOL_GCOALESCE;
13859         ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
13860         ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
13861         ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
13862         ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
13863         ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
13864         ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
13865         ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
13866         ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
13867         ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
13868
13869         if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
13870                                  HOSTCC_MODE_CLRTICK_TXBD)) {
13871                 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
13872                 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
13873                 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
13874                 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
13875         }
13876
13877         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
13878                 ec->rx_coalesce_usecs_irq = 0;
13879                 ec->tx_coalesce_usecs_irq = 0;
13880                 ec->stats_block_coalesce_usecs = 0;
13881         }
13882 }
13883
13884 static const struct net_device_ops tg3_netdev_ops = {
13885         .ndo_open               = tg3_open,
13886         .ndo_stop               = tg3_close,
13887         .ndo_start_xmit         = tg3_start_xmit,
13888         .ndo_get_stats          = tg3_get_stats,
13889         .ndo_validate_addr      = eth_validate_addr,
13890         .ndo_set_multicast_list = tg3_set_rx_mode,
13891         .ndo_set_mac_address    = tg3_set_mac_addr,
13892         .ndo_do_ioctl           = tg3_ioctl,
13893         .ndo_tx_timeout         = tg3_tx_timeout,
13894         .ndo_change_mtu         = tg3_change_mtu,
13895 #if TG3_VLAN_TAG_USED
13896         .ndo_vlan_rx_register   = tg3_vlan_rx_register,
13897 #endif
13898 #ifdef CONFIG_NET_POLL_CONTROLLER
13899         .ndo_poll_controller    = tg3_poll_controller,
13900 #endif
13901 };
13902
13903 static const struct net_device_ops tg3_netdev_ops_dma_bug = {
13904         .ndo_open               = tg3_open,
13905         .ndo_stop               = tg3_close,
13906         .ndo_start_xmit         = tg3_start_xmit_dma_bug,
13907         .ndo_get_stats          = tg3_get_stats,
13908         .ndo_validate_addr      = eth_validate_addr,
13909         .ndo_set_multicast_list = tg3_set_rx_mode,
13910         .ndo_set_mac_address    = tg3_set_mac_addr,
13911         .ndo_do_ioctl           = tg3_ioctl,
13912         .ndo_tx_timeout         = tg3_tx_timeout,
13913         .ndo_change_mtu         = tg3_change_mtu,
13914 #if TG3_VLAN_TAG_USED
13915         .ndo_vlan_rx_register   = tg3_vlan_rx_register,
13916 #endif
13917 #ifdef CONFIG_NET_POLL_CONTROLLER
13918         .ndo_poll_controller    = tg3_poll_controller,
13919 #endif
13920 };
13921
13922 static int __devinit tg3_init_one(struct pci_dev *pdev,
13923                                   const struct pci_device_id *ent)
13924 {
13925         static int tg3_version_printed = 0;
13926         struct net_device *dev;
13927         struct tg3 *tp;
13928         int i, err, pm_cap;
13929         u32 sndmbx, rcvmbx, intmbx;
13930         char str[40];
13931         u64 dma_mask, persist_dma_mask;
13932
13933         if (tg3_version_printed++ == 0)
13934                 printk(KERN_INFO "%s", version);
13935
13936         err = pci_enable_device(pdev);
13937         if (err) {
13938                 printk(KERN_ERR PFX "Cannot enable PCI device, "
13939                        "aborting.\n");
13940                 return err;
13941         }
13942
13943         err = pci_request_regions(pdev, DRV_MODULE_NAME);
13944         if (err) {
13945                 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
13946                        "aborting.\n");
13947                 goto err_out_disable_pdev;
13948         }
13949
13950         pci_set_master(pdev);
13951
13952         /* Find power-management capability. */
13953         pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
13954         if (pm_cap == 0) {
13955                 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
13956                        "aborting.\n");
13957                 err = -EIO;
13958                 goto err_out_free_res;
13959         }
13960
13961         dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
13962         if (!dev) {
13963                 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
13964                 err = -ENOMEM;
13965                 goto err_out_free_res;
13966         }
13967
13968         SET_NETDEV_DEV(dev, &pdev->dev);
13969
13970 #if TG3_VLAN_TAG_USED
13971         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
13972 #endif
13973
13974         tp = netdev_priv(dev);
13975         tp->pdev = pdev;
13976         tp->dev = dev;
13977         tp->pm_cap = pm_cap;
13978         tp->rx_mode = TG3_DEF_RX_MODE;
13979         tp->tx_mode = TG3_DEF_TX_MODE;
13980
13981         if (tg3_debug > 0)
13982                 tp->msg_enable = tg3_debug;
13983         else
13984                 tp->msg_enable = TG3_DEF_MSG_ENABLE;
13985
13986         /* The word/byte swap controls here control register access byte
13987          * swapping.  DMA data byte swapping is controlled in the GRC_MODE
13988          * setting below.
13989          */
13990         tp->misc_host_ctrl =
13991                 MISC_HOST_CTRL_MASK_PCI_INT |
13992                 MISC_HOST_CTRL_WORD_SWAP |
13993                 MISC_HOST_CTRL_INDIR_ACCESS |
13994                 MISC_HOST_CTRL_PCISTATE_RW;
13995
13996         /* The NONFRM (non-frame) byte/word swap controls take effect
13997          * on descriptor entries, anything which isn't packet data.
13998          *
13999          * The StrongARM chips on the board (one for tx, one for rx)
14000          * are running in big-endian mode.
14001          */
14002         tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
14003                         GRC_MODE_WSWAP_NONFRM_DATA);
14004 #ifdef __BIG_ENDIAN
14005         tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
14006 #endif
14007         spin_lock_init(&tp->lock);
14008         spin_lock_init(&tp->indirect_lock);
14009         INIT_WORK(&tp->reset_task, tg3_reset_task);
14010
14011         tp->regs = pci_ioremap_bar(pdev, BAR_0);
14012         if (!tp->regs) {
14013                 printk(KERN_ERR PFX "Cannot map device registers, "
14014                        "aborting.\n");
14015                 err = -ENOMEM;
14016                 goto err_out_free_dev;
14017         }
14018
14019         tg3_init_link_config(tp);
14020
14021         tp->rx_pending = TG3_DEF_RX_RING_PENDING;
14022         tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
14023
14024         intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
14025         rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
14026         sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
14027         for (i = 0; i < TG3_IRQ_MAX_VECS; i++) {
14028                 struct tg3_napi *tnapi = &tp->napi[i];
14029
14030                 tnapi->tp = tp;
14031                 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
14032
14033                 tnapi->int_mbox = intmbx;
14034                 if (i < 4)
14035                         intmbx += 0x8;
14036                 else
14037                         intmbx += 0x4;
14038
14039                 tnapi->consmbox = rcvmbx;
14040                 tnapi->prodmbox = sndmbx;
14041
14042                 if (i)
14043                         tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
14044                 else
14045                         tnapi->coal_now = HOSTCC_MODE_NOW;
14046
14047                 if (!(tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX))
14048                         break;
14049
14050                 /*
14051                  * If we support MSIX, we'll be using RSS.  If we're using
14052                  * RSS, the first vector only handles link interrupts and the
14053                  * remaining vectors handle rx and tx interrupts.  Reuse the
14054                  * mailbox values for the next iteration.  The values we setup
14055                  * above are still useful for the single vectored mode.
14056                  */
14057                 if (!i)
14058                         continue;
14059
14060                 rcvmbx += 0x8;
14061
14062                 if (sndmbx & 0x4)
14063                         sndmbx -= 0x4;
14064                 else
14065                         sndmbx += 0xc;
14066         }
14067
14068         netif_napi_add(dev, &tp->napi[0].napi, tg3_poll, 64);
14069         dev->ethtool_ops = &tg3_ethtool_ops;
14070         dev->watchdog_timeo = TG3_TX_TIMEOUT;
14071         dev->irq = pdev->irq;
14072
14073         err = tg3_get_invariants(tp);
14074         if (err) {
14075                 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
14076                        "aborting.\n");
14077                 goto err_out_iounmap;
14078         }
14079
14080         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
14081                 dev->netdev_ops = &tg3_netdev_ops;
14082         else
14083                 dev->netdev_ops = &tg3_netdev_ops_dma_bug;
14084
14085
14086         /* The EPB bridge inside 5714, 5715, and 5780 and any
14087          * device behind the EPB cannot support DMA addresses > 40-bit.
14088          * On 64-bit systems with IOMMU, use 40-bit dma_mask.
14089          * On 64-bit systems without IOMMU, use 64-bit dma_mask and
14090          * do DMA address check in tg3_start_xmit().
14091          */
14092         if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
14093                 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
14094         else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
14095                 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
14096 #ifdef CONFIG_HIGHMEM
14097                 dma_mask = DMA_BIT_MASK(64);
14098 #endif
14099         } else
14100                 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
14101
14102         /* Configure DMA attributes. */
14103         if (dma_mask > DMA_BIT_MASK(32)) {
14104                 err = pci_set_dma_mask(pdev, dma_mask);
14105                 if (!err) {
14106                         dev->features |= NETIF_F_HIGHDMA;
14107                         err = pci_set_consistent_dma_mask(pdev,
14108                                                           persist_dma_mask);
14109                         if (err < 0) {
14110                                 printk(KERN_ERR PFX "Unable to obtain 64 bit "
14111                                        "DMA for consistent allocations\n");
14112                                 goto err_out_iounmap;
14113                         }
14114                 }
14115         }
14116         if (err || dma_mask == DMA_BIT_MASK(32)) {
14117                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
14118                 if (err) {
14119                         printk(KERN_ERR PFX "No usable DMA configuration, "
14120                                "aborting.\n");
14121                         goto err_out_iounmap;
14122                 }
14123         }
14124
14125         tg3_init_bufmgr_config(tp);
14126
14127         /* Selectively allow TSO based on operating conditions */
14128         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
14129             (tp->fw_needed && !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)))
14130                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
14131         else {
14132                 tp->tg3_flags2 &= ~(TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG);
14133                 tp->fw_needed = NULL;
14134         }
14135
14136         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
14137                 tp->fw_needed = FIRMWARE_TG3;
14138
14139         /* TSO is on by default on chips that support hardware TSO.
14140          * Firmware TSO on older chips gives lower performance, so it
14141          * is off by default, but can be enabled using ethtool.
14142          */
14143         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) &&
14144             (dev->features & NETIF_F_IP_CSUM))
14145                 dev->features |= NETIF_F_TSO;
14146
14147         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
14148             (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3)) {
14149                 if (dev->features & NETIF_F_IPV6_CSUM)
14150                         dev->features |= NETIF_F_TSO6;
14151                 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
14152                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
14153                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
14154                      GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
14155                         GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
14156                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
14157                         dev->features |= NETIF_F_TSO_ECN;
14158         }
14159
14160         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
14161             !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
14162             !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
14163                 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
14164                 tp->rx_pending = 63;
14165         }
14166
14167         err = tg3_get_device_address(tp);
14168         if (err) {
14169                 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
14170                        "aborting.\n");
14171                 goto err_out_fw;
14172         }
14173
14174         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
14175                 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
14176                 if (!tp->aperegs) {
14177                         printk(KERN_ERR PFX "Cannot map APE registers, "
14178                                "aborting.\n");
14179                         err = -ENOMEM;
14180                         goto err_out_fw;
14181                 }
14182
14183                 tg3_ape_lock_init(tp);
14184
14185                 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
14186                         tg3_read_dash_ver(tp);
14187         }
14188
14189         /*
14190          * Reset chip in case UNDI or EFI driver did not shutdown
14191          * DMA self test will enable WDMAC and we'll see (spurious)
14192          * pending DMA on the PCI bus at that point.
14193          */
14194         if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
14195             (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
14196                 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
14197                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14198         }
14199
14200         err = tg3_test_dma(tp);
14201         if (err) {
14202                 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
14203                 goto err_out_apeunmap;
14204         }
14205
14206         /* flow control autonegotiation is default behavior */
14207         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
14208         tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
14209
14210         tg3_init_coal(tp);
14211
14212         pci_set_drvdata(pdev, dev);
14213
14214         err = register_netdev(dev);
14215         if (err) {
14216                 printk(KERN_ERR PFX "Cannot register net device, "
14217                        "aborting.\n");
14218                 goto err_out_apeunmap;
14219         }
14220
14221         printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
14222                dev->name,
14223                tp->board_part_number,
14224                tp->pci_chip_rev_id,
14225                tg3_bus_string(tp, str),
14226                dev->dev_addr);
14227
14228         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
14229                 struct phy_device *phydev;
14230                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
14231                 printk(KERN_INFO
14232                        "%s: attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
14233                        tp->dev->name, phydev->drv->name,
14234                        dev_name(&phydev->dev));
14235         } else
14236                 printk(KERN_INFO
14237                        "%s: attached PHY is %s (%s Ethernet) (WireSpeed[%d])\n",
14238                        tp->dev->name, tg3_phy_string(tp),
14239                        ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
14240                         ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
14241                          "10/100/1000Base-T")),
14242                        (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0);
14243
14244         printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
14245                dev->name,
14246                (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
14247                (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
14248                (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
14249                (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
14250                (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
14251         printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
14252                dev->name, tp->dma_rwctrl,
14253                (pdev->dma_mask == DMA_BIT_MASK(32)) ? 32 :
14254                 (((u64) pdev->dma_mask == DMA_BIT_MASK(40)) ? 40 : 64));
14255
14256         return 0;
14257
14258 err_out_apeunmap:
14259         if (tp->aperegs) {
14260                 iounmap(tp->aperegs);
14261                 tp->aperegs = NULL;
14262         }
14263
14264 err_out_fw:
14265         if (tp->fw)
14266                 release_firmware(tp->fw);
14267
14268 err_out_iounmap:
14269         if (tp->regs) {
14270                 iounmap(tp->regs);
14271                 tp->regs = NULL;
14272         }
14273
14274 err_out_free_dev:
14275         free_netdev(dev);
14276
14277 err_out_free_res:
14278         pci_release_regions(pdev);
14279
14280 err_out_disable_pdev:
14281         pci_disable_device(pdev);
14282         pci_set_drvdata(pdev, NULL);
14283         return err;
14284 }
14285
14286 static void __devexit tg3_remove_one(struct pci_dev *pdev)
14287 {
14288         struct net_device *dev = pci_get_drvdata(pdev);
14289
14290         if (dev) {
14291                 struct tg3 *tp = netdev_priv(dev);
14292
14293                 if (tp->fw)
14294                         release_firmware(tp->fw);
14295
14296                 flush_scheduled_work();
14297
14298                 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
14299                         tg3_phy_fini(tp);
14300                         tg3_mdio_fini(tp);
14301                 }
14302
14303                 unregister_netdev(dev);
14304                 if (tp->aperegs) {
14305                         iounmap(tp->aperegs);
14306                         tp->aperegs = NULL;
14307                 }
14308                 if (tp->regs) {
14309                         iounmap(tp->regs);
14310                         tp->regs = NULL;
14311                 }
14312                 free_netdev(dev);
14313                 pci_release_regions(pdev);
14314                 pci_disable_device(pdev);
14315                 pci_set_drvdata(pdev, NULL);
14316         }
14317 }
14318
14319 static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
14320 {
14321         struct net_device *dev = pci_get_drvdata(pdev);
14322         struct tg3 *tp = netdev_priv(dev);
14323         pci_power_t target_state;
14324         int err;
14325
14326         /* PCI register 4 needs to be saved whether netif_running() or not.
14327          * MSI address and data need to be saved if using MSI and
14328          * netif_running().
14329          */
14330         pci_save_state(pdev);
14331
14332         if (!netif_running(dev))
14333                 return 0;
14334
14335         flush_scheduled_work();
14336         tg3_phy_stop(tp);
14337         tg3_netif_stop(tp);
14338
14339         del_timer_sync(&tp->timer);
14340
14341         tg3_full_lock(tp, 1);
14342         tg3_disable_ints(tp);
14343         tg3_full_unlock(tp);
14344
14345         netif_device_detach(dev);
14346
14347         tg3_full_lock(tp, 0);
14348         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14349         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
14350         tg3_full_unlock(tp);
14351
14352         target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot;
14353
14354         err = tg3_set_power_state(tp, target_state);
14355         if (err) {
14356                 int err2;
14357
14358                 tg3_full_lock(tp, 0);
14359
14360                 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
14361                 err2 = tg3_restart_hw(tp, 1);
14362                 if (err2)
14363                         goto out;
14364
14365                 tp->timer.expires = jiffies + tp->timer_offset;
14366                 add_timer(&tp->timer);
14367
14368                 netif_device_attach(dev);
14369                 tg3_netif_start(tp);
14370
14371 out:
14372                 tg3_full_unlock(tp);
14373
14374                 if (!err2)
14375                         tg3_phy_start(tp);
14376         }
14377
14378         return err;
14379 }
14380
14381 static int tg3_resume(struct pci_dev *pdev)
14382 {
14383         struct net_device *dev = pci_get_drvdata(pdev);
14384         struct tg3 *tp = netdev_priv(dev);
14385         int err;
14386
14387         pci_restore_state(tp->pdev);
14388
14389         if (!netif_running(dev))
14390                 return 0;
14391
14392         err = tg3_set_power_state(tp, PCI_D0);
14393         if (err)
14394                 return err;
14395
14396         netif_device_attach(dev);
14397
14398         tg3_full_lock(tp, 0);
14399
14400         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
14401         err = tg3_restart_hw(tp, 1);
14402         if (err)
14403                 goto out;
14404
14405         tp->timer.expires = jiffies + tp->timer_offset;
14406         add_timer(&tp->timer);
14407
14408         tg3_netif_start(tp);
14409
14410 out:
14411         tg3_full_unlock(tp);
14412
14413         if (!err)
14414                 tg3_phy_start(tp);
14415
14416         return err;
14417 }
14418
14419 static struct pci_driver tg3_driver = {
14420         .name           = DRV_MODULE_NAME,
14421         .id_table       = tg3_pci_tbl,
14422         .probe          = tg3_init_one,
14423         .remove         = __devexit_p(tg3_remove_one),
14424         .suspend        = tg3_suspend,
14425         .resume         = tg3_resume
14426 };
14427
14428 static int __init tg3_init(void)
14429 {
14430         return pci_register_driver(&tg3_driver);
14431 }
14432
14433 static void __exit tg3_cleanup(void)
14434 {
14435         pci_unregister_driver(&tg3_driver);
14436 }
14437
14438 module_init(tg3_init);
14439 module_exit(tg3_cleanup);