drivers/net/tg3.c

   1 /*
   2  * tg3.c: Broadcom Tigon3 ethernet driver.
   3  *
   4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
   5  * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
   6  * Copyright (C) 2004 Sun Microsystems Inc.
   7  * Copyright (C) 2005-2009 Broadcom Corporation.
   8  *
   9  * Firmware is:
  10  *      Derived from proprietary unpublished source code,
  11  *      Copyright (C) 2000-2003 Broadcom Corporation.
  12  *
  13  *      Permission is hereby granted for the distribution of this firmware
  14  *      data in hexadecimal or equivalent format, provided this copyright
  15  *      notice is accompanying it.
  16  */
  17
  18
  19 #include <linux/module.h>
  20 #include <linux/moduleparam.h>
  21 #include <linux/kernel.h>
  22 #include <linux/types.h>
  23 #include <linux/compiler.h>
  24 #include <linux/slab.h>
  25 #include <linux/delay.h>
  26 #include <linux/in.h>
  27 #include <linux/init.h>
  28 #include <linux/ioport.h>
  29 #include <linux/pci.h>
  30 #include <linux/netdevice.h>
  31 #include <linux/etherdevice.h>
  32 #include <linux/skbuff.h>
  33 #include <linux/ethtool.h>
  34 #include <linux/mii.h>
  35 #include <linux/phy.h>
  36 #include <linux/brcmphy.h>
  37 #include <linux/if_vlan.h>
  38 #include <linux/ip.h>
  39 #include <linux/tcp.h>
  40 #include <linux/workqueue.h>
  41 #include <linux/prefetch.h>
  42 #include <linux/dma-mapping.h>
  43 #include <linux/firmware.h>
  44
  45 #include <net/checksum.h>
  46 #include <net/ip.h>
  47
  48 #include <asm/system.h>
  49 #include <asm/io.h>
  50 #include <asm/byteorder.h>
  51 #include <asm/uaccess.h>
  52
  53 #ifdef CONFIG_SPARC
  54 #include <asm/idprom.h>
  55 #include <asm/prom.h>
  56 #endif
  57
  58 #define BAR_0   0
  59 #define BAR_2   2
  60
  61 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  62 #define TG3_VLAN_TAG_USED 1
  63 #else
  64 #define TG3_VLAN_TAG_USED 0
  65 #endif
  66
  67 #include "tg3.h"
  68
  69 #define DRV_MODULE_NAME         "tg3"
  70 #define PFX DRV_MODULE_NAME     ": "
  71 #define DRV_MODULE_VERSION      "3.104"
  72 #define DRV_MODULE_RELDATE      "November 13, 2009"
  73
  74 #define TG3_DEF_MAC_MODE        0
  75 #define TG3_DEF_RX_MODE         0
  76 #define TG3_DEF_TX_MODE         0
  77 #define TG3_DEF_MSG_ENABLE        \
  78         (NETIF_MSG_DRV          | \
  79          NETIF_MSG_PROBE        | \
  80          NETIF_MSG_LINK         | \
  81          NETIF_MSG_TIMER        | \
  82          NETIF_MSG_IFDOWN       | \
  83          NETIF_MSG_IFUP         | \
  84          NETIF_MSG_RX_ERR       | \
  85          NETIF_MSG_TX_ERR)
  86
  87 /* length of time before we decide the hardware is borked,
  88  * and dev->tx_timeout() should be called to fix the problem
  89  */
  90 #define TG3_TX_TIMEOUT                  (5 * HZ)
  91
  92 /* hardware minimum and maximum for a single frame's data payload */
  93 #define TG3_MIN_MTU                     60
  94 #define TG3_MAX_MTU(tp) \
  95         ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
  96
  97 /* These numbers seem to be hard coded in the NIC firmware somehow.
  98  * You can't change the ring sizes, but you can change where you place
  99  * them in the NIC onboard memory.
 100  */
 101 #define TG3_RX_RING_SIZE                512
 102 #define TG3_DEF_RX_RING_PENDING         200
 103 #define TG3_RX_JUMBO_RING_SIZE          256
 104 #define TG3_DEF_RX_JUMBO_RING_PENDING   100
 105 #define TG3_RSS_INDIR_TBL_SIZE 128
 106
 107 /* Do not place this n-ring entries value into the tp struct itself,
 108  * we really want to expose these constants to GCC so that modulo et
 109  * al.  operations are done with shifts and masks instead of with
 110  * hw multiply/modulo instructions.  Another solution would be to
 111  * replace things like '% foo' with '& (foo - 1)'.
 112  */
 113 #define TG3_RX_RCB_RING_SIZE(tp)        \
 114         (((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) && \
 115           !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) ? 1024 : 512)
 116
 117 #define TG3_TX_RING_SIZE                512
 118 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
 119
 120 #define TG3_RX_RING_BYTES       (sizeof(struct tg3_rx_buffer_desc) * \
 121                                  TG3_RX_RING_SIZE)
 122 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_ext_rx_buffer_desc) * \
 123                                  TG3_RX_JUMBO_RING_SIZE)
 124 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
 125                                  TG3_RX_RCB_RING_SIZE(tp))
 126 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * \
 127                                  TG3_TX_RING_SIZE)
 128 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
 129
 130 #define TG3_DMA_BYTE_ENAB               64
 131
 132 #define TG3_RX_STD_DMA_SZ               1536
 133 #define TG3_RX_JMB_DMA_SZ               9046
 134
 135 #define TG3_RX_DMA_TO_MAP_SZ(x)         ((x) + TG3_DMA_BYTE_ENAB)
 136
 137 #define TG3_RX_STD_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
 138 #define TG3_RX_JMB_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
 139
 140 #define TG3_RX_STD_BUFF_RING_SIZE \
 141         (sizeof(struct ring_info) * TG3_RX_RING_SIZE)
 142
 143 #define TG3_RX_JMB_BUFF_RING_SIZE \
 144         (sizeof(struct ring_info) * TG3_RX_JUMBO_RING_SIZE)
 145
 146 /* minimum number of free TX descriptors required to wake up TX process */
 147 #define TG3_TX_WAKEUP_THRESH(tnapi)             ((tnapi)->tx_pending / 4)
 148
 149 #define TG3_RAW_IP_ALIGN 2
 150
 151 /* number of ETHTOOL_GSTATS u64's */
 152 #define TG3_NUM_STATS           (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
 153
 154 #define TG3_NUM_TEST            6
 155
 156 #define FIRMWARE_TG3            "tigon/tg3.bin"
 157 #define FIRMWARE_TG3TSO         "tigon/tg3_tso.bin"
 158 #define FIRMWARE_TG3TSO5        "tigon/tg3_tso5.bin"
 159
 160 static char version[] __devinitdata =
 161         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
 162
 163 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
 164 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
 165 MODULE_LICENSE("GPL");
 166 MODULE_VERSION(DRV_MODULE_VERSION);
 167 MODULE_FIRMWARE(FIRMWARE_TG3);
 168 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
 169 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
 170
 171 #define TG3_RSS_MIN_NUM_MSIX_VECS       2
 172
 173 static int tg3_debug = -1;      /* -1 == use TG3_DEF_MSG_ENABLE as value */
 174 module_param(tg3_debug, int, 0);
 175 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
 176
 177 static struct pci_device_id tg3_pci_tbl[] = {
 178         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
 179         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
 180         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
 181         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
 182         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
 183         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
 184         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
 185         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
 186         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
 187         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
 188         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
 189         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
 190         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
 191         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
 192         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
 193         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
 194         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
 195         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
 196         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
 197         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
 198         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
 199         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
 200         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
 201         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
 202         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
 203         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
 204         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
 205         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
 206         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
 207         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
 208         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
 209         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
 210         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
 211         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
 212         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
 213         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
 214         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
 215         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
 216         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
 217         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
 218         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
 219         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
 220         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
 221         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
 222         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
 223         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
 224         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
 225         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
 226         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
 227         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
 228         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
 229         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
 230         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
 231         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
 232         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
 233         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
 234         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
 235         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
 236         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
 237         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
 238         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
 239         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
 240         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
 241         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
 242         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
 243         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
 244         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
 245         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
 246         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5724)},
 247         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
 248         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
 249         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
 250         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
 251         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
 252         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
 253         {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
 254         {}
 255 };
 256
 257 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
 258
 259 static const struct {
 260         const char string[ETH_GSTRING_LEN];
 261 } ethtool_stats_keys[TG3_NUM_STATS] = {
 262         { "rx_octets" },
 263         { "rx_fragments" },
 264         { "rx_ucast_packets" },
 265         { "rx_mcast_packets" },
 266         { "rx_bcast_packets" },
 267         { "rx_fcs_errors" },
 268         { "rx_align_errors" },
 269         { "rx_xon_pause_rcvd" },
 270         { "rx_xoff_pause_rcvd" },
 271         { "rx_mac_ctrl_rcvd" },
 272         { "rx_xoff_entered" },
 273         { "rx_frame_too_long_errors" },
 274         { "rx_jabbers" },
 275         { "rx_undersize_packets" },
 276         { "rx_in_length_errors" },
 277         { "rx_out_length_errors" },
 278         { "rx_64_or_less_octet_packets" },
 279         { "rx_65_to_127_octet_packets" },
 280         { "rx_128_to_255_octet_packets" },
 281         { "rx_256_to_511_octet_packets" },
 282         { "rx_512_to_1023_octet_packets" },
 283         { "rx_1024_to_1522_octet_packets" },
 284         { "rx_1523_to_2047_octet_packets" },
 285         { "rx_2048_to_4095_octet_packets" },
 286         { "rx_4096_to_8191_octet_packets" },
 287         { "rx_8192_to_9022_octet_packets" },
 288
 289         { "tx_octets" },
 290         { "tx_collisions" },
 291
 292         { "tx_xon_sent" },
 293         { "tx_xoff_sent" },
 294         { "tx_flow_control" },
 295         { "tx_mac_errors" },
 296         { "tx_single_collisions" },
 297         { "tx_mult_collisions" },
 298         { "tx_deferred" },
 299         { "tx_excessive_collisions" },
 300         { "tx_late_collisions" },
 301         { "tx_collide_2times" },
 302         { "tx_collide_3times" },
 303         { "tx_collide_4times" },
 304         { "tx_collide_5times" },
 305         { "tx_collide_6times" },
 306         { "tx_collide_7times" },
 307         { "tx_collide_8times" },
 308         { "tx_collide_9times" },
 309         { "tx_collide_10times" },
 310         { "tx_collide_11times" },
 311         { "tx_collide_12times" },
 312         { "tx_collide_13times" },
 313         { "tx_collide_14times" },
 314         { "tx_collide_15times" },
 315         { "tx_ucast_packets" },
 316         { "tx_mcast_packets" },
 317         { "tx_bcast_packets" },
 318         { "tx_carrier_sense_errors" },
 319         { "tx_discards" },
 320         { "tx_errors" },
 321
 322         { "dma_writeq_full" },
 323         { "dma_write_prioq_full" },
 324         { "rxbds_empty" },
 325         { "rx_discards" },
 326         { "rx_errors" },
 327         { "rx_threshold_hit" },
 328
 329         { "dma_readq_full" },
 330         { "dma_read_prioq_full" },
 331         { "tx_comp_queue_full" },
 332
 333         { "ring_set_send_prod_index" },
 334         { "ring_status_update" },
 335         { "nic_irqs" },
 336         { "nic_avoided_irqs" },
 337         { "nic_tx_threshold_hit" }
 338 };
 339
 340 static const struct {
 341         const char string[ETH_GSTRING_LEN];
 342 } ethtool_test_keys[TG3_NUM_TEST] = {
 343         { "nvram test     (online) " },
 344         { "link test      (online) " },
 345         { "register test  (offline)" },
 346         { "memory test    (offline)" },
 347         { "loopback test  (offline)" },
 348         { "interrupt test (offline)" },
 349 };
 350
 351 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
 352 {
 353         writel(val, tp->regs + off);
 354 }
 355
 356 static u32 tg3_read32(struct tg3 *tp, u32 off)
 357 {
 358         return (readl(tp->regs + off));
 359 }
 360
 361 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
 362 {
 363         writel(val, tp->aperegs + off);
 364 }
 365
 366 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
 367 {
 368         return (readl(tp->aperegs + off));
 369 }
 370
 371 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
 372 {
 373         unsigned long flags;
 374
 375         spin_lock_irqsave(&tp->indirect_lock, flags);
 376         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 377         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 378         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 379 }
 380
 381 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
 382 {
 383         writel(val, tp->regs + off);
 384         readl(tp->regs + off);
 385 }
 386
 387 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
 388 {
 389         unsigned long flags;
 390         u32 val;
 391
 392         spin_lock_irqsave(&tp->indirect_lock, flags);
 393         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 394         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 395         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 396         return val;
 397 }
 398
 399 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
 400 {
 401         unsigned long flags;
 402
 403         if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
 404                 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
 405                                        TG3_64BIT_REG_LOW, val);
 406                 return;
 407         }
 408         if (off == TG3_RX_STD_PROD_IDX_REG) {
 409                 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
 410                                        TG3_64BIT_REG_LOW, val);
 411                 return;
 412         }
 413
 414         spin_lock_irqsave(&tp->indirect_lock, flags);
 415         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 416         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 417         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 418
 419         /* In indirect mode when disabling interrupts, we also need
 420          * to clear the interrupt bit in the GRC local ctrl register.
 421          */
 422         if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
 423             (val == 0x1)) {
 424                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
 425                                        tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
 426         }
 427 }
 428
 429 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
 430 {
 431         unsigned long flags;
 432         u32 val;
 433
 434         spin_lock_irqsave(&tp->indirect_lock, flags);
 435         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 436         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 437         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 438         return val;
 439 }
 440
 441 /* usec_wait specifies the wait time in usec when writing to certain registers
 442  * where it is unsafe to read back the register without some delay.
 443  * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
 444  * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
 445  */
 446 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
 447 {
 448         if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
 449             (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 450                 /* Non-posted methods */
 451                 tp->write32(tp, off, val);
 452         else {
 453                 /* Posted method */
 454                 tg3_write32(tp, off, val);
 455                 if (usec_wait)
 456                         udelay(usec_wait);
 457                 tp->read32(tp, off);
 458         }
 459         /* Wait again after the read for the posted method to guarantee that
 460          * the wait time is met.
 461          */
 462         if (usec_wait)
 463                 udelay(usec_wait);
 464 }
 465
 466 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
 467 {
 468         tp->write32_mbox(tp, off, val);
 469         if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
 470             !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 471                 tp->read32_mbox(tp, off);
 472 }
 473
 474 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
 475 {
 476         void __iomem *mbox = tp->regs + off;
 477         writel(val, mbox);
 478         if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
 479                 writel(val, mbox);
 480         if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
 481                 readl(mbox);
 482 }
 483
 484 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
 485 {
 486         return (readl(tp->regs + off + GRCMBOX_BASE));
 487 }
 488
 489 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
 490 {
 491         writel(val, tp->regs + off + GRCMBOX_BASE);
 492 }
 493
 494 #define tw32_mailbox(reg, val)  tp->write32_mbox(tp, reg, val)
 495 #define tw32_mailbox_f(reg, val)        tw32_mailbox_flush(tp, (reg), (val))
 496 #define tw32_rx_mbox(reg, val)  tp->write32_rx_mbox(tp, reg, val)
 497 #define tw32_tx_mbox(reg, val)  tp->write32_tx_mbox(tp, reg, val)
 498 #define tr32_mailbox(reg)       tp->read32_mbox(tp, reg)
 499
 500 #define tw32(reg,val)           tp->write32(tp, reg, val)
 501 #define tw32_f(reg,val)         _tw32_flush(tp,(reg),(val), 0)
 502 #define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
 503 #define tr32(reg)               tp->read32(tp, reg)
 504
 505 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
 506 {
 507         unsigned long flags;
 508
 509         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 510             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
 511                 return;
 512
 513         spin_lock_irqsave(&tp->indirect_lock, flags);
 514         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 515                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 516                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 517
 518                 /* Always leave this as zero. */
 519                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 520         } else {
 521                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 522                 tw32_f(TG3PCI_MEM_WIN_DATA, val);
 523
 524                 /* Always leave this as zero. */
 525                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 526         }
 527         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 528 }
 529
 530 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
 531 {
 532         unsigned long flags;
 533
 534         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 535             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
 536                 *val = 0;
 537                 return;
 538         }
 539
 540         spin_lock_irqsave(&tp->indirect_lock, flags);
 541         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 542                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 543                 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 544
 545                 /* Always leave this as zero. */
 546                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 547         } else {
 548                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 549                 *val = tr32(TG3PCI_MEM_WIN_DATA);
 550
 551                 /* Always leave this as zero. */
 552                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 553         }
 554         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 555 }
 556
 557 static void tg3_ape_lock_init(struct tg3 *tp)
 558 {
 559         int i;
 560
 561         /* Make sure the driver hasn't any stale locks. */
 562         for (i = 0; i < 8; i++)
 563                 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + 4 * i,
 564                                 APE_LOCK_GRANT_DRIVER);
 565 }
 566
 567 static int tg3_ape_lock(struct tg3 *tp, int locknum)
 568 {
 569         int i, off;
 570         int ret = 0;
 571         u32 status;
 572
 573         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
 574                 return 0;
 575
 576         switch (locknum) {
 577                 case TG3_APE_LOCK_GRC:
 578                 case TG3_APE_LOCK_MEM:
 579                         break;
 580                 default:
 581                         return -EINVAL;
 582         }
 583
 584         off = 4 * locknum;
 585
 586         tg3_ape_write32(tp, TG3_APE_LOCK_REQ + off, APE_LOCK_REQ_DRIVER);
 587
 588         /* Wait for up to 1 millisecond to acquire lock. */
 589         for (i = 0; i < 100; i++) {
 590                 status = tg3_ape_read32(tp, TG3_APE_LOCK_GRANT + off);
 591                 if (status == APE_LOCK_GRANT_DRIVER)
 592                         break;
 593                 udelay(10);
 594         }
 595
 596         if (status != APE_LOCK_GRANT_DRIVER) {
 597                 /* Revoke the lock request. */
 598                 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off,
 599                                 APE_LOCK_GRANT_DRIVER);
 600
 601                 ret = -EBUSY;
 602         }
 603
 604         return ret;
 605 }
 606
 607 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
 608 {
 609         int off;
 610
 611         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
 612                 return;
 613
 614         switch (locknum) {
 615                 case TG3_APE_LOCK_GRC:
 616                 case TG3_APE_LOCK_MEM:
 617                         break;
 618                 default:
 619                         return;
 620         }
 621
 622         off = 4 * locknum;
 623         tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off, APE_LOCK_GRANT_DRIVER);
 624 }
 625
 626 static void tg3_disable_ints(struct tg3 *tp)
 627 {
 628         int i;
 629
 630         tw32(TG3PCI_MISC_HOST_CTRL,
 631              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
 632         for (i = 0; i < tp->irq_max; i++)
 633                 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
 634 }
 635
 636 static void tg3_enable_ints(struct tg3 *tp)
 637 {
 638         int i;
 639         u32 coal_now = 0;
 640
 641         tp->irq_sync = 0;
 642         wmb();
 643
 644         tw32(TG3PCI_MISC_HOST_CTRL,
 645              (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
 646
 647         for (i = 0; i < tp->irq_cnt; i++) {
 648                 struct tg3_napi *tnapi = &tp->napi[i];
 649                 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
 650                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
 651                         tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
 652
 653                 coal_now |= tnapi->coal_now;
 654         }
 655
 656         /* Force an initial interrupt */
 657         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 658             (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
 659                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
 660         else
 661                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 662                      HOSTCC_MODE_ENABLE | coal_now);
 663 }
 664
 665 static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
 666 {
 667         struct tg3 *tp = tnapi->tp;
 668         struct tg3_hw_status *sblk = tnapi->hw_status;
 669         unsigned int work_exists = 0;
 670
 671         /* check for phy events */
 672         if (!(tp->tg3_flags &
 673               (TG3_FLAG_USE_LINKCHG_REG |
 674                TG3_FLAG_POLL_SERDES))) {
 675                 if (sblk->status & SD_STATUS_LINK_CHG)
 676                         work_exists = 1;
 677         }
 678         /* check for RX/TX work to do */
 679         if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
 680             *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
 681                 work_exists = 1;
 682
 683         return work_exists;
 684 }
 685
 686 /* tg3_int_reenable
 687  *  similar to tg3_enable_ints, but it accurately determines whether there
 688  *  is new work pending and can return without flushing the PIO write
 689  *  which reenables interrupts
 690  */
 691 static void tg3_int_reenable(struct tg3_napi *tnapi)
 692 {
 693         struct tg3 *tp = tnapi->tp;
 694
 695         tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
 696         mmiowb();
 697
 698         /* When doing tagged status, this work check is unnecessary.
 699          * The last_tag we write above tells the chip which piece of
 700          * work we've completed.
 701          */
 702         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 703             tg3_has_work(tnapi))
 704                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 705                      HOSTCC_MODE_ENABLE | tnapi->coal_now);
 706 }
 707
 708 static void tg3_napi_disable(struct tg3 *tp)
 709 {
 710         int i;
 711
 712         for (i = tp->irq_cnt - 1; i >= 0; i--)
 713                 napi_disable(&tp->napi[i].napi);
 714 }
 715
 716 static void tg3_napi_enable(struct tg3 *tp)
 717 {
 718         int i;
 719
 720         for (i = 0; i < tp->irq_cnt; i++)
 721                 napi_enable(&tp->napi[i].napi);
 722 }
 723
 724 static inline void tg3_netif_stop(struct tg3 *tp)
 725 {
 726         tp->dev->trans_start = jiffies; /* prevent tx timeout */
 727         tg3_napi_disable(tp);
 728         netif_tx_disable(tp->dev);
 729 }
 730
 731 static inline void tg3_netif_start(struct tg3 *tp)
 732 {
 733         /* NOTE: unconditional netif_tx_wake_all_queues is only
 734          * appropriate so long as all callers are assured to
 735          * have free tx slots (such as after tg3_init_hw)
 736          */
 737         netif_tx_wake_all_queues(tp->dev);
 738
 739         tg3_napi_enable(tp);
 740         tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
 741         tg3_enable_ints(tp);
 742 }
 743
 744 static void tg3_switch_clocks(struct tg3 *tp)
 745 {
 746         u32 clock_ctrl;
 747         u32 orig_clock_ctrl;
 748
 749         if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
 750             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
 751                 return;
 752
 753         clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
 754
 755         orig_clock_ctrl = clock_ctrl;
 756         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
 757                        CLOCK_CTRL_CLKRUN_OENABLE |
 758                        0x1f);
 759         tp->pci_clock_ctrl = clock_ctrl;
 760
 761         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
 762                 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
 763                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
 764                                     clock_ctrl | CLOCK_CTRL_625_CORE, 40);
 765                 }
 766         } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
 767                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 768                             clock_ctrl |
 769                             (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
 770                             40);
 771                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 772                             clock_ctrl | (CLOCK_CTRL_ALTCLK),
 773                             40);
 774         }
 775         tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
 776 }
 777
 778 #define PHY_BUSY_LOOPS  5000
 779
 780 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
 781 {
 782         u32 frame_val;
 783         unsigned int loops;
 784         int ret;
 785
 786         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 787                 tw32_f(MAC_MI_MODE,
 788                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 789                 udelay(80);
 790         }
 791
 792         *val = 0x0;
 793
 794         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
 795                       MI_COM_PHY_ADDR_MASK);
 796         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 797                       MI_COM_REG_ADDR_MASK);
 798         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
 799
 800         tw32_f(MAC_MI_COM, frame_val);
 801
 802         loops = PHY_BUSY_LOOPS;
 803         while (loops != 0) {
 804                 udelay(10);
 805                 frame_val = tr32(MAC_MI_COM);
 806
 807                 if ((frame_val & MI_COM_BUSY) == 0) {
 808                         udelay(5);
 809                         frame_val = tr32(MAC_MI_COM);
 810                         break;
 811                 }
 812                 loops -= 1;
 813         }
 814
 815         ret = -EBUSY;
 816         if (loops != 0) {
 817                 *val = frame_val & MI_COM_DATA_MASK;
 818                 ret = 0;
 819         }
 820
 821         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 822                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 823                 udelay(80);
 824         }
 825
 826         return ret;
 827 }
 828
 829 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
 830 {
 831         u32 frame_val;
 832         unsigned int loops;
 833         int ret;
 834
 835         if ((tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
 836             (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
 837                 return 0;
 838
 839         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 840                 tw32_f(MAC_MI_MODE,
 841                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 842                 udelay(80);
 843         }
 844
 845         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
 846                       MI_COM_PHY_ADDR_MASK);
 847         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 848                       MI_COM_REG_ADDR_MASK);
 849         frame_val |= (val & MI_COM_DATA_MASK);
 850         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
 851
 852         tw32_f(MAC_MI_COM, frame_val);
 853
 854         loops = PHY_BUSY_LOOPS;
 855         while (loops != 0) {
 856                 udelay(10);
 857                 frame_val = tr32(MAC_MI_COM);
 858                 if ((frame_val & MI_COM_BUSY) == 0) {
 859                         udelay(5);
 860                         frame_val = tr32(MAC_MI_COM);
 861                         break;
 862                 }
 863                 loops -= 1;
 864         }
 865
 866         ret = -EBUSY;
 867         if (loops != 0)
 868                 ret = 0;
 869
 870         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 871                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 872                 udelay(80);
 873         }
 874
 875         return ret;
 876 }
 877
 878 static int tg3_bmcr_reset(struct tg3 *tp)
 879 {
 880         u32 phy_control;
 881         int limit, err;
 882
 883         /* OK, reset it, and poll the BMCR_RESET bit until it
 884          * clears or we time out.
 885          */
 886         phy_control = BMCR_RESET;
 887         err = tg3_writephy(tp, MII_BMCR, phy_control);
 888         if (err != 0)
 889                 return -EBUSY;
 890
 891         limit = 5000;
 892         while (limit--) {
 893                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
 894                 if (err != 0)
 895                         return -EBUSY;
 896
 897                 if ((phy_control & BMCR_RESET) == 0) {
 898                         udelay(40);
 899                         break;
 900                 }
 901                 udelay(10);
 902         }
 903         if (limit < 0)
 904                 return -EBUSY;
 905
 906         return 0;
 907 }
 908
 909 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
 910 {
 911         struct tg3 *tp = bp->priv;
 912         u32 val;
 913
 914         spin_lock_bh(&tp->lock);
 915
 916         if (tg3_readphy(tp, reg, &val))
 917                 val = -EIO;
 918
 919         spin_unlock_bh(&tp->lock);
 920
 921         return val;
 922 }
 923
 924 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
 925 {
 926         struct tg3 *tp = bp->priv;
 927         u32 ret = 0;
 928
 929         spin_lock_bh(&tp->lock);
 930
 931         if (tg3_writephy(tp, reg, val))
 932                 ret = -EIO;
 933
 934         spin_unlock_bh(&tp->lock);
 935
 936         return ret;
 937 }
 938
 939 static int tg3_mdio_reset(struct mii_bus *bp)
 940 {
 941         return 0;
 942 }
 943
 944 static void tg3_mdio_config_5785(struct tg3 *tp)
 945 {
 946         u32 val;
 947         struct phy_device *phydev;
 948
 949         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
 950         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
 951         case TG3_PHY_ID_BCM50610:
 952         case TG3_PHY_ID_BCM50610M:
 953                 val = MAC_PHYCFG2_50610_LED_MODES;
 954                 break;
 955         case TG3_PHY_ID_BCMAC131:
 956                 val = MAC_PHYCFG2_AC131_LED_MODES;
 957                 break;
 958         case TG3_PHY_ID_RTL8211C:
 959                 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
 960                 break;
 961         case TG3_PHY_ID_RTL8201E:
 962                 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
 963                 break;
 964         default:
 965                 return;
 966         }
 967
 968         if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
 969                 tw32(MAC_PHYCFG2, val);
 970
 971                 val = tr32(MAC_PHYCFG1);
 972                 val &= ~(MAC_PHYCFG1_RGMII_INT |
 973                          MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
 974                 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
 975                 tw32(MAC_PHYCFG1, val);
 976
 977                 return;
 978         }
 979
 980         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE))
 981                 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
 982                        MAC_PHYCFG2_FMODE_MASK_MASK |
 983                        MAC_PHYCFG2_GMODE_MASK_MASK |
 984                        MAC_PHYCFG2_ACT_MASK_MASK   |
 985                        MAC_PHYCFG2_QUAL_MASK_MASK |
 986                        MAC_PHYCFG2_INBAND_ENABLE;
 987
 988         tw32(MAC_PHYCFG2, val);
 989
 990         val = tr32(MAC_PHYCFG1);
 991         val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
 992                  MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
 993         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
 994                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
 995                         val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
 996                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
 997                         val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
 998         }
 999         val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1000                MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1001         tw32(MAC_PHYCFG1, val);
1002
1003         val = tr32(MAC_EXT_RGMII_MODE);
1004         val &= ~(MAC_RGMII_MODE_RX_INT_B |
1005                  MAC_RGMII_MODE_RX_QUALITY |
1006                  MAC_RGMII_MODE_RX_ACTIVITY |
1007                  MAC_RGMII_MODE_RX_ENG_DET |
1008                  MAC_RGMII_MODE_TX_ENABLE |
1009                  MAC_RGMII_MODE_TX_LOWPWR |
1010                  MAC_RGMII_MODE_TX_RESET);
1011         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
1012                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1013                         val |= MAC_RGMII_MODE_RX_INT_B |
1014                                MAC_RGMII_MODE_RX_QUALITY |
1015                                MAC_RGMII_MODE_RX_ACTIVITY |
1016                                MAC_RGMII_MODE_RX_ENG_DET;
1017                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1018                         val |= MAC_RGMII_MODE_TX_ENABLE |
1019                                MAC_RGMII_MODE_TX_LOWPWR |
1020                                MAC_RGMII_MODE_TX_RESET;
1021         }
1022         tw32(MAC_EXT_RGMII_MODE, val);
1023 }
1024
1025 static void tg3_mdio_start(struct tg3 *tp)
1026 {
1027         tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1028         tw32_f(MAC_MI_MODE, tp->mi_mode);
1029         udelay(80);
1030
1031         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
1032                 u32 funcnum, is_serdes;
1033
1034                 funcnum = tr32(TG3_CPMU_STATUS) & TG3_CPMU_STATUS_PCIE_FUNC;
1035                 if (funcnum)
1036                         tp->phy_addr = 2;
1037                 else
1038                         tp->phy_addr = 1;
1039
1040                 is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1041                 if (is_serdes)
1042                         tp->phy_addr += 7;
1043         } else
1044                 tp->phy_addr = TG3_PHY_MII_ADDR;
1045
1046         if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
1047             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1048                 tg3_mdio_config_5785(tp);
1049 }
1050
1051 static int tg3_mdio_init(struct tg3 *tp)
1052 {
1053         int i;
1054         u32 reg;
1055         struct phy_device *phydev;
1056
1057         tg3_mdio_start(tp);
1058
1059         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1060             (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1061                 return 0;
1062
1063         tp->mdio_bus = mdiobus_alloc();
1064         if (tp->mdio_bus == NULL)
1065                 return -ENOMEM;
1066
1067         tp->mdio_bus->name     = "tg3 mdio bus";
1068         snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1069                  (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1070         tp->mdio_bus->priv     = tp;
1071         tp->mdio_bus->parent   = &tp->pdev->dev;
1072         tp->mdio_bus->read     = &tg3_mdio_read;
1073         tp->mdio_bus->write    = &tg3_mdio_write;
1074         tp->mdio_bus->reset    = &tg3_mdio_reset;
1075         tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
1076         tp->mdio_bus->irq      = &tp->mdio_irq[0];
1077
1078         for (i = 0; i < PHY_MAX_ADDR; i++)
1079                 tp->mdio_bus->irq[i] = PHY_POLL;
1080
1081         /* The bus registration will look for all the PHYs on the mdio bus.
1082          * Unfortunately, it does not ensure the PHY is powered up before
1083          * accessing the PHY ID registers.  A chip reset is the
1084          * quickest way to bring the device back to an operational state..
1085          */
1086         if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1087                 tg3_bmcr_reset(tp);
1088
1089         i = mdiobus_register(tp->mdio_bus);
1090         if (i) {
1091                 printk(KERN_WARNING "%s: mdiobus_reg failed (0x%x)\n",
1092                         tp->dev->name, i);
1093                 mdiobus_free(tp->mdio_bus);
1094                 return i;
1095         }
1096
1097         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1098
1099         if (!phydev || !phydev->drv) {
1100                 printk(KERN_WARNING "%s: No PHY devices\n", tp->dev->name);
1101                 mdiobus_unregister(tp->mdio_bus);
1102                 mdiobus_free(tp->mdio_bus);
1103                 return -ENODEV;
1104         }
1105
1106         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1107         case TG3_PHY_ID_BCM57780:
1108                 phydev->interface = PHY_INTERFACE_MODE_GMII;
1109                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1110                 break;
1111         case TG3_PHY_ID_BCM50610:
1112         case TG3_PHY_ID_BCM50610M:
1113                 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
1114                                      PHY_BRCM_RX_REFCLK_UNUSED |
1115                                      PHY_BRCM_DIS_TXCRXC_NOENRGY |
1116                                      PHY_BRCM_AUTO_PWRDWN_ENABLE;
1117                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)
1118                         phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1119                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1120                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1121                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1122                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1123                 /* fallthru */
1124         case TG3_PHY_ID_RTL8211C:
1125                 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1126                 break;
1127         case TG3_PHY_ID_RTL8201E:
1128         case TG3_PHY_ID_BCMAC131:
1129                 phydev->interface = PHY_INTERFACE_MODE_MII;
1130                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1131                 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
1132                 break;
1133         }
1134
1135         tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1136
1137         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1138                 tg3_mdio_config_5785(tp);
1139
1140         return 0;
1141 }
1142
1143 static void tg3_mdio_fini(struct tg3 *tp)
1144 {
1145         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1146                 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
1147                 mdiobus_unregister(tp->mdio_bus);
1148                 mdiobus_free(tp->mdio_bus);
1149         }
1150 }
1151
1152 /* tp->lock is held. */
1153 static inline void tg3_generate_fw_event(struct tg3 *tp)
1154 {
1155         u32 val;
1156
1157         val = tr32(GRC_RX_CPU_EVENT);
1158         val |= GRC_RX_CPU_DRIVER_EVENT;
1159         tw32_f(GRC_RX_CPU_EVENT, val);
1160
1161         tp->last_event_jiffies = jiffies;
1162 }
1163
1164 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1165
1166 /* tp->lock is held. */
1167 static void tg3_wait_for_event_ack(struct tg3 *tp)
1168 {
1169         int i;
1170         unsigned int delay_cnt;
1171         long time_remain;
1172
1173         /* If enough time has passed, no wait is necessary. */
1174         time_remain = (long)(tp->last_event_jiffies + 1 +
1175                       usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1176                       (long)jiffies;
1177         if (time_remain < 0)
1178                 return;
1179
1180         /* Check if we can shorten the wait time. */
1181         delay_cnt = jiffies_to_usecs(time_remain);
1182         if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1183                 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1184         delay_cnt = (delay_cnt >> 3) + 1;
1185
1186         for (i = 0; i < delay_cnt; i++) {
1187                 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1188                         break;
1189                 udelay(8);
1190         }
1191 }
1192
1193 /* tp->lock is held. */
1194 static void tg3_ump_link_report(struct tg3 *tp)
1195 {
1196         u32 reg;
1197         u32 val;
1198
1199         if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1200             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
1201                 return;
1202
1203         tg3_wait_for_event_ack(tp);
1204
1205         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1206
1207         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1208
1209         val = 0;
1210         if (!tg3_readphy(tp, MII_BMCR, &reg))
1211                 val = reg << 16;
1212         if (!tg3_readphy(tp, MII_BMSR, &reg))
1213                 val |= (reg & 0xffff);
1214         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1215
1216         val = 0;
1217         if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1218                 val = reg << 16;
1219         if (!tg3_readphy(tp, MII_LPA, &reg))
1220                 val |= (reg & 0xffff);
1221         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1222
1223         val = 0;
1224         if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) {
1225                 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1226                         val = reg << 16;
1227                 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1228                         val |= (reg & 0xffff);
1229         }
1230         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1231
1232         if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1233                 val = reg << 16;
1234         else
1235                 val = 0;
1236         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1237
1238         tg3_generate_fw_event(tp);
1239 }
1240
1241 static void tg3_link_report(struct tg3 *tp)
1242 {
1243         if (!netif_carrier_ok(tp->dev)) {
1244                 if (netif_msg_link(tp))
1245                         printk(KERN_INFO PFX "%s: Link is down.\n",
1246                                tp->dev->name);
1247                 tg3_ump_link_report(tp);
1248         } else if (netif_msg_link(tp)) {
1249                 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1250                        tp->dev->name,
1251                        (tp->link_config.active_speed == SPEED_1000 ?
1252                         1000 :
1253                         (tp->link_config.active_speed == SPEED_100 ?
1254                          100 : 10)),
1255                        (tp->link_config.active_duplex == DUPLEX_FULL ?
1256                         "full" : "half"));
1257
1258                 printk(KERN_INFO PFX
1259                        "%s: Flow control is %s for TX and %s for RX.\n",
1260                        tp->dev->name,
1261                        (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1262                        "on" : "off",
1263                        (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1264                        "on" : "off");
1265                 tg3_ump_link_report(tp);
1266         }
1267 }
1268
1269 static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1270 {
1271         u16 miireg;
1272
1273         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1274                 miireg = ADVERTISE_PAUSE_CAP;
1275         else if (flow_ctrl & FLOW_CTRL_TX)
1276                 miireg = ADVERTISE_PAUSE_ASYM;
1277         else if (flow_ctrl & FLOW_CTRL_RX)
1278                 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1279         else
1280                 miireg = 0;
1281
1282         return miireg;
1283 }
1284
1285 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1286 {
1287         u16 miireg;
1288
1289         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1290                 miireg = ADVERTISE_1000XPAUSE;
1291         else if (flow_ctrl & FLOW_CTRL_TX)
1292                 miireg = ADVERTISE_1000XPSE_ASYM;
1293         else if (flow_ctrl & FLOW_CTRL_RX)
1294                 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1295         else
1296                 miireg = 0;
1297
1298         return miireg;
1299 }
1300
1301 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1302 {
1303         u8 cap = 0;
1304
1305         if (lcladv & ADVERTISE_1000XPAUSE) {
1306                 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1307                         if (rmtadv & LPA_1000XPAUSE)
1308                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1309                         else if (rmtadv & LPA_1000XPAUSE_ASYM)
1310                                 cap = FLOW_CTRL_RX;
1311                 } else {
1312                         if (rmtadv & LPA_1000XPAUSE)
1313                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1314                 }
1315         } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1316                 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1317                         cap = FLOW_CTRL_TX;
1318         }
1319
1320         return cap;
1321 }
1322
1323 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1324 {
1325         u8 autoneg;
1326         u8 flowctrl = 0;
1327         u32 old_rx_mode = tp->rx_mode;
1328         u32 old_tx_mode = tp->tx_mode;
1329
1330         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
1331                 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
1332         else
1333                 autoneg = tp->link_config.autoneg;
1334
1335         if (autoneg == AUTONEG_ENABLE &&
1336             (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1337                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1338                         flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1339                 else
1340                         flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1341         } else
1342                 flowctrl = tp->link_config.flowctrl;
1343
1344         tp->link_config.active_flowctrl = flowctrl;
1345
1346         if (flowctrl & FLOW_CTRL_RX)
1347                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1348         else
1349                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1350
1351         if (old_rx_mode != tp->rx_mode)
1352                 tw32_f(MAC_RX_MODE, tp->rx_mode);
1353
1354         if (flowctrl & FLOW_CTRL_TX)
1355                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1356         else
1357                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1358
1359         if (old_tx_mode != tp->tx_mode)
1360                 tw32_f(MAC_TX_MODE, tp->tx_mode);
1361 }
1362
1363 static void tg3_adjust_link(struct net_device *dev)
1364 {
1365         u8 oldflowctrl, linkmesg = 0;
1366         u32 mac_mode, lcl_adv, rmt_adv;
1367         struct tg3 *tp = netdev_priv(dev);
1368         struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1369
1370         spin_lock_bh(&tp->lock);
1371
1372         mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1373                                     MAC_MODE_HALF_DUPLEX);
1374
1375         oldflowctrl = tp->link_config.active_flowctrl;
1376
1377         if (phydev->link) {
1378                 lcl_adv = 0;
1379                 rmt_adv = 0;
1380
1381                 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1382                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1383                 else if (phydev->speed == SPEED_1000 ||
1384                          GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
1385                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
1386                 else
1387                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1388
1389                 if (phydev->duplex == DUPLEX_HALF)
1390                         mac_mode |= MAC_MODE_HALF_DUPLEX;
1391                 else {
1392                         lcl_adv = tg3_advert_flowctrl_1000T(
1393                                   tp->link_config.flowctrl);
1394
1395                         if (phydev->pause)
1396                                 rmt_adv = LPA_PAUSE_CAP;
1397                         if (phydev->asym_pause)
1398                                 rmt_adv |= LPA_PAUSE_ASYM;
1399                 }
1400
1401                 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1402         } else
1403                 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1404
1405         if (mac_mode != tp->mac_mode) {
1406                 tp->mac_mode = mac_mode;
1407                 tw32_f(MAC_MODE, tp->mac_mode);
1408                 udelay(40);
1409         }
1410
1411         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1412                 if (phydev->speed == SPEED_10)
1413                         tw32(MAC_MI_STAT,
1414                              MAC_MI_STAT_10MBPS_MODE |
1415                              MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1416                 else
1417                         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1418         }
1419
1420         if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1421                 tw32(MAC_TX_LENGTHS,
1422                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1423                       (6 << TX_LENGTHS_IPG_SHIFT) |
1424                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1425         else
1426                 tw32(MAC_TX_LENGTHS,
1427                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1428                       (6 << TX_LENGTHS_IPG_SHIFT) |
1429                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1430
1431         if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1432             (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1433             phydev->speed != tp->link_config.active_speed ||
1434             phydev->duplex != tp->link_config.active_duplex ||
1435             oldflowctrl != tp->link_config.active_flowctrl)
1436             linkmesg = 1;
1437
1438         tp->link_config.active_speed = phydev->speed;
1439         tp->link_config.active_duplex = phydev->duplex;
1440
1441         spin_unlock_bh(&tp->lock);
1442
1443         if (linkmesg)
1444                 tg3_link_report(tp);
1445 }
1446
1447 static int tg3_phy_init(struct tg3 *tp)
1448 {
1449         struct phy_device *phydev;
1450
1451         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
1452                 return 0;
1453
1454         /* Bring the PHY back to a known state. */
1455         tg3_bmcr_reset(tp);
1456
1457         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1458
1459         /* Attach the MAC to the PHY. */
1460         phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
1461                              phydev->dev_flags, phydev->interface);
1462         if (IS_ERR(phydev)) {
1463                 printk(KERN_ERR "%s: Could not attach to PHY\n", tp->dev->name);
1464                 return PTR_ERR(phydev);
1465         }
1466
1467         /* Mask with MAC supported features. */
1468         switch (phydev->interface) {
1469         case PHY_INTERFACE_MODE_GMII:
1470         case PHY_INTERFACE_MODE_RGMII:
1471                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1472                         phydev->supported &= (PHY_GBIT_FEATURES |
1473                                               SUPPORTED_Pause |
1474                                               SUPPORTED_Asym_Pause);
1475                         break;
1476                 }
1477                 /* fallthru */
1478         case PHY_INTERFACE_MODE_MII:
1479                 phydev->supported &= (PHY_BASIC_FEATURES |
1480                                       SUPPORTED_Pause |
1481                                       SUPPORTED_Asym_Pause);
1482                 break;
1483         default:
1484                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1485                 return -EINVAL;
1486         }
1487
1488         tp->tg3_flags3 |= TG3_FLG3_PHY_CONNECTED;
1489
1490         phydev->advertising = phydev->supported;
1491
1492         return 0;
1493 }
1494
1495 static void tg3_phy_start(struct tg3 *tp)
1496 {
1497         struct phy_device *phydev;
1498
1499         if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1500                 return;
1501
1502         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1503
1504         if (tp->link_config.phy_is_low_power) {
1505                 tp->link_config.phy_is_low_power = 0;
1506                 phydev->speed = tp->link_config.orig_speed;
1507                 phydev->duplex = tp->link_config.orig_duplex;
1508                 phydev->autoneg = tp->link_config.orig_autoneg;
1509                 phydev->advertising = tp->link_config.orig_advertising;
1510         }
1511
1512         phy_start(phydev);
1513
1514         phy_start_aneg(phydev);
1515 }
1516
1517 static void tg3_phy_stop(struct tg3 *tp)
1518 {
1519         if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1520                 return;
1521
1522         phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1523 }
1524
1525 static void tg3_phy_fini(struct tg3 *tp)
1526 {
1527         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
1528                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1529                 tp->tg3_flags3 &= ~TG3_FLG3_PHY_CONNECTED;
1530         }
1531 }
1532
1533 static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1534 {
1535         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1536         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1537 }
1538
1539 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1540 {
1541         u32 phytest;
1542
1543         if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1544                 u32 phy;
1545
1546                 tg3_writephy(tp, MII_TG3_FET_TEST,
1547                              phytest | MII_TG3_FET_SHADOW_EN);
1548                 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1549                         if (enable)
1550                                 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1551                         else
1552                                 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1553                         tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1554                 }
1555                 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1556         }
1557 }
1558
1559 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1560 {
1561         u32 reg;
1562
1563         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
1564                 return;
1565
1566         if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1567                 tg3_phy_fet_toggle_apd(tp, enable);
1568                 return;
1569         }
1570
1571         reg = MII_TG3_MISC_SHDW_WREN |
1572               MII_TG3_MISC_SHDW_SCR5_SEL |
1573               MII_TG3_MISC_SHDW_SCR5_LPED |
1574               MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1575               MII_TG3_MISC_SHDW_SCR5_SDTL |
1576               MII_TG3_MISC_SHDW_SCR5_C125OE;
1577         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1578                 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1579
1580         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1581
1582
1583         reg = MII_TG3_MISC_SHDW_WREN |
1584               MII_TG3_MISC_SHDW_APD_SEL |
1585               MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1586         if (enable)
1587                 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1588
1589         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1590 }
1591
1592 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1593 {
1594         u32 phy;
1595
1596         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1597             (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1598                 return;
1599
1600         if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1601                 u32 ephy;
1602
1603                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1604                         u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1605
1606                         tg3_writephy(tp, MII_TG3_FET_TEST,
1607                                      ephy | MII_TG3_FET_SHADOW_EN);
1608                         if (!tg3_readphy(tp, reg, &phy)) {
1609                                 if (enable)
1610                                         phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1611                                 else
1612                                         phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1613                                 tg3_writephy(tp, reg, phy);
1614                         }
1615                         tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
1616                 }
1617         } else {
1618                 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1619                       MII_TG3_AUXCTL_SHDWSEL_MISC;
1620                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1621                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1622                         if (enable)
1623                                 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1624                         else
1625                                 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1626                         phy |= MII_TG3_AUXCTL_MISC_WREN;
1627                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1628                 }
1629         }
1630 }
1631
1632 static void tg3_phy_set_wirespeed(struct tg3 *tp)
1633 {
1634         u32 val;
1635
1636         if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
1637                 return;
1638
1639         if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1640             !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1641                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1642                              (val | (1 << 15) | (1 << 4)));
1643 }
1644
1645 static void tg3_phy_apply_otp(struct tg3 *tp)
1646 {
1647         u32 otp, phy;
1648
1649         if (!tp->phy_otp)
1650                 return;
1651
1652         otp = tp->phy_otp;
1653
1654         /* Enable SM_DSP clock and tx 6dB coding. */
1655         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1656               MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1657               MII_TG3_AUXCTL_ACTL_TX_6DB;
1658         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1659
1660         phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1661         phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1662         tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1663
1664         phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1665               ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1666         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1667
1668         phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1669         phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1670         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1671
1672         phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1673         tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1674
1675         phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1676         tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1677
1678         phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1679               ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1680         tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1681
1682         /* Turn off SM_DSP clock. */
1683         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1684               MII_TG3_AUXCTL_ACTL_TX_6DB;
1685         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1686 }
1687
1688 static int tg3_wait_macro_done(struct tg3 *tp)
1689 {
1690         int limit = 100;
1691
1692         while (limit--) {
1693                 u32 tmp32;
1694
1695                 if (!tg3_readphy(tp, 0x16, &tmp32)) {
1696                         if ((tmp32 & 0x1000) == 0)
1697                                 break;
1698                 }
1699         }
1700         if (limit < 0)
1701                 return -EBUSY;
1702
1703         return 0;
1704 }
1705
1706 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1707 {
1708         static const u32 test_pat[4][6] = {
1709         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1710         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1711         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1712         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1713         };
1714         int chan;
1715
1716         for (chan = 0; chan < 4; chan++) {
1717                 int i;
1718
1719                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1720                              (chan * 0x2000) | 0x0200);
1721                 tg3_writephy(tp, 0x16, 0x0002);
1722
1723                 for (i = 0; i < 6; i++)
1724                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1725                                      test_pat[chan][i]);
1726
1727                 tg3_writephy(tp, 0x16, 0x0202);
1728                 if (tg3_wait_macro_done(tp)) {
1729                         *resetp = 1;
1730                         return -EBUSY;
1731                 }
1732
1733                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1734                              (chan * 0x2000) | 0x0200);
1735                 tg3_writephy(tp, 0x16, 0x0082);
1736                 if (tg3_wait_macro_done(tp)) {
1737                         *resetp = 1;
1738                         return -EBUSY;
1739                 }
1740
1741                 tg3_writephy(tp, 0x16, 0x0802);
1742                 if (tg3_wait_macro_done(tp)) {
1743                         *resetp = 1;
1744                         return -EBUSY;
1745                 }
1746
1747                 for (i = 0; i < 6; i += 2) {
1748                         u32 low, high;
1749
1750                         if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1751                             tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1752                             tg3_wait_macro_done(tp)) {
1753                                 *resetp = 1;
1754                                 return -EBUSY;
1755                         }
1756                         low &= 0x7fff;
1757                         high &= 0x000f;
1758                         if (low != test_pat[chan][i] ||
1759                             high != test_pat[chan][i+1]) {
1760                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1761                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1762                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1763
1764                                 return -EBUSY;
1765                         }
1766                 }
1767         }
1768
1769         return 0;
1770 }
1771
1772 static int tg3_phy_reset_chanpat(struct tg3 *tp)
1773 {
1774         int chan;
1775
1776         for (chan = 0; chan < 4; chan++) {
1777                 int i;
1778
1779                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1780                              (chan * 0x2000) | 0x0200);
1781                 tg3_writephy(tp, 0x16, 0x0002);
1782                 for (i = 0; i < 6; i++)
1783                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1784                 tg3_writephy(tp, 0x16, 0x0202);
1785                 if (tg3_wait_macro_done(tp))
1786                         return -EBUSY;
1787         }
1788
1789         return 0;
1790 }
1791
1792 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1793 {
1794         u32 reg32, phy9_orig;
1795         int retries, do_phy_reset, err;
1796
1797         retries = 10;
1798         do_phy_reset = 1;
1799         do {
1800                 if (do_phy_reset) {
1801                         err = tg3_bmcr_reset(tp);
1802                         if (err)
1803                                 return err;
1804                         do_phy_reset = 0;
1805                 }
1806
1807                 /* Disable transmitter and interrupt.  */
1808                 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1809                         continue;
1810
1811                 reg32 |= 0x3000;
1812                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1813
1814                 /* Set full-duplex, 1000 mbps.  */
1815                 tg3_writephy(tp, MII_BMCR,
1816                              BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1817
1818                 /* Set to master mode.  */
1819                 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1820                         continue;
1821
1822                 tg3_writephy(tp, MII_TG3_CTRL,
1823                              (MII_TG3_CTRL_AS_MASTER |
1824                               MII_TG3_CTRL_ENABLE_AS_MASTER));
1825
1826                 /* Enable SM_DSP_CLOCK and 6dB.  */
1827                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1828
1829                 /* Block the PHY control access.  */
1830                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1831                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
1832
1833                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1834                 if (!err)
1835                         break;
1836         } while (--retries);
1837
1838         err = tg3_phy_reset_chanpat(tp);
1839         if (err)
1840                 return err;
1841
1842         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1843         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
1844
1845         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1846         tg3_writephy(tp, 0x16, 0x0000);
1847
1848         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1849             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1850                 /* Set Extended packet length bit for jumbo frames */
1851                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1852         }
1853         else {
1854                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1855         }
1856
1857         tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1858
1859         if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1860                 reg32 &= ~0x3000;
1861                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1862         } else if (!err)
1863                 err = -EBUSY;
1864
1865         return err;
1866 }
1867
1868 /* This will reset the tigon3 PHY if there is no valid
1869  * link unless the FORCE argument is non-zero.
1870  */
1871 static int tg3_phy_reset(struct tg3 *tp)
1872 {
1873         u32 cpmuctrl;
1874         u32 phy_status;
1875         int err;
1876
1877         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1878                 u32 val;
1879
1880                 val = tr32(GRC_MISC_CFG);
1881                 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1882                 udelay(40);
1883         }
1884         err  = tg3_readphy(tp, MII_BMSR, &phy_status);
1885         err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1886         if (err != 0)
1887                 return -EBUSY;
1888
1889         if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1890                 netif_carrier_off(tp->dev);
1891                 tg3_link_report(tp);
1892         }
1893
1894         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1895             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1896             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1897                 err = tg3_phy_reset_5703_4_5(tp);
1898                 if (err)
1899                         return err;
1900                 goto out;
1901         }
1902
1903         cpmuctrl = 0;
1904         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1905             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1906                 cpmuctrl = tr32(TG3_CPMU_CTRL);
1907                 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1908                         tw32(TG3_CPMU_CTRL,
1909                              cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1910         }
1911
1912         err = tg3_bmcr_reset(tp);
1913         if (err)
1914                 return err;
1915
1916         if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1917                 u32 phy;
1918
1919                 phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1920                 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy);
1921
1922                 tw32(TG3_CPMU_CTRL, cpmuctrl);
1923         }
1924
1925         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
1926             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
1927                 u32 val;
1928
1929                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1930                 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1931                     CPMU_LSPD_1000MB_MACCLK_12_5) {
1932                         val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1933                         udelay(40);
1934                         tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1935                 }
1936         }
1937
1938         tg3_phy_apply_otp(tp);
1939
1940         if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
1941                 tg3_phy_toggle_apd(tp, true);
1942         else
1943                 tg3_phy_toggle_apd(tp, false);
1944
1945 out:
1946         if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1947                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1948                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1949                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1950                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1951                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
1952                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1953         }
1954         if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
1955                 tg3_writephy(tp, 0x1c, 0x8d68);
1956                 tg3_writephy(tp, 0x1c, 0x8d68);
1957         }
1958         if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1959                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1960                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1961                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1962                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1963                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1964                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1965                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1966                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1967         }
1968         else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1969                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1970                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1971                 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1972                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1973                         tg3_writephy(tp, MII_TG3_TEST1,
1974                                      MII_TG3_TEST1_TRIM_EN | 0x4);
1975                 } else
1976                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
1977                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1978         }
1979         /* Set Extended packet length bit (bit 14) on all chips that */
1980         /* support jumbo frames */
1981         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1982                 /* Cannot do read-modify-write on 5401 */
1983                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1984         } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1985                 u32 phy_reg;
1986
1987                 /* Set bit 14 with read-modify-write to preserve other bits */
1988                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1989                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1990                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1991         }
1992
1993         /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1994          * jumbo frames transmission.
1995          */
1996         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1997                 u32 phy_reg;
1998
1999                 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
2000                     tg3_writephy(tp, MII_TG3_EXT_CTRL,
2001                                  phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
2002         }
2003
2004         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2005                 /* adjust output voltage */
2006                 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
2007         }
2008
2009         tg3_phy_toggle_automdix(tp, 1);
2010         tg3_phy_set_wirespeed(tp);
2011         return 0;
2012 }
2013
2014 static void tg3_frob_aux_power(struct tg3 *tp)
2015 {
2016         struct tg3 *tp_peer = tp;
2017
2018         if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
2019                 return;
2020
2021         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2022             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
2023             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
2024                 struct net_device *dev_peer;
2025
2026                 dev_peer = pci_get_drvdata(tp->pdev_peer);
2027                 /* remove_one() may have been run on the peer. */
2028                 if (!dev_peer)
2029                         tp_peer = tp;
2030                 else
2031                         tp_peer = netdev_priv(dev_peer);
2032         }
2033
2034         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2035             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
2036             (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2037             (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
2038                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2039                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2040                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2041                                     (GRC_LCLCTRL_GPIO_OE0 |
2042                                      GRC_LCLCTRL_GPIO_OE1 |
2043                                      GRC_LCLCTRL_GPIO_OE2 |
2044                                      GRC_LCLCTRL_GPIO_OUTPUT0 |
2045                                      GRC_LCLCTRL_GPIO_OUTPUT1),
2046                                     100);
2047                 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2048                            tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2049                         /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2050                         u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2051                                              GRC_LCLCTRL_GPIO_OE1 |
2052                                              GRC_LCLCTRL_GPIO_OE2 |
2053                                              GRC_LCLCTRL_GPIO_OUTPUT0 |
2054                                              GRC_LCLCTRL_GPIO_OUTPUT1 |
2055                                              tp->grc_local_ctrl;
2056                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2057
2058                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2059                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2060
2061                         grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2062                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2063                 } else {
2064                         u32 no_gpio2;
2065                         u32 grc_local_ctrl = 0;
2066
2067                         if (tp_peer != tp &&
2068                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2069                                 return;
2070
2071                         /* Workaround to prevent overdrawing Amps. */
2072                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2073                             ASIC_REV_5714) {
2074                                 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2075                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2076                                             grc_local_ctrl, 100);
2077                         }
2078
2079                         /* On 5753 and variants, GPIO2 cannot be used. */
2080                         no_gpio2 = tp->nic_sram_data_cfg &
2081                                     NIC_SRAM_DATA_CFG_NO_GPIO2;
2082
2083                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2084                                          GRC_LCLCTRL_GPIO_OE1 |
2085                                          GRC_LCLCTRL_GPIO_OE2 |
2086                                          GRC_LCLCTRL_GPIO_OUTPUT1 |
2087                                          GRC_LCLCTRL_GPIO_OUTPUT2;
2088                         if (no_gpio2) {
2089                                 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2090                                                     GRC_LCLCTRL_GPIO_OUTPUT2);
2091                         }
2092                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2093                                                     grc_local_ctrl, 100);
2094
2095                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2096
2097                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2098                                                     grc_local_ctrl, 100);
2099
2100                         if (!no_gpio2) {
2101                                 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2102                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2103                                             grc_local_ctrl, 100);
2104                         }
2105                 }
2106         } else {
2107                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2108                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2109                         if (tp_peer != tp &&
2110                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2111                                 return;
2112
2113                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2114                                     (GRC_LCLCTRL_GPIO_OE1 |
2115                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2116
2117                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2118                                     GRC_LCLCTRL_GPIO_OE1, 100);
2119
2120                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2121                                     (GRC_LCLCTRL_GPIO_OE1 |
2122                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2123                 }
2124         }
2125 }
2126
2127 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2128 {
2129         if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2130                 return 1;
2131         else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411) {
2132                 if (speed != SPEED_10)
2133                         return 1;
2134         } else if (speed == SPEED_10)
2135                 return 1;
2136
2137         return 0;
2138 }
2139
2140 static int tg3_setup_phy(struct tg3 *, int);
2141
2142 #define RESET_KIND_SHUTDOWN     0
2143 #define RESET_KIND_INIT         1
2144 #define RESET_KIND_SUSPEND      2
2145
2146 static void tg3_write_sig_post_reset(struct tg3 *, int);
2147 static int tg3_halt_cpu(struct tg3 *, u32);
2148
2149 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2150 {
2151         u32 val;
2152
2153         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2154                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2155                         u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2156                         u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2157
2158                         sg_dig_ctrl |=
2159                                 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2160                         tw32(SG_DIG_CTRL, sg_dig_ctrl);
2161                         tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2162                 }
2163                 return;
2164         }
2165
2166         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2167                 tg3_bmcr_reset(tp);
2168                 val = tr32(GRC_MISC_CFG);
2169                 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2170                 udelay(40);
2171                 return;
2172         } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
2173                 u32 phytest;
2174                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2175                         u32 phy;
2176
2177                         tg3_writephy(tp, MII_ADVERTISE, 0);
2178                         tg3_writephy(tp, MII_BMCR,
2179                                      BMCR_ANENABLE | BMCR_ANRESTART);
2180
2181                         tg3_writephy(tp, MII_TG3_FET_TEST,
2182                                      phytest | MII_TG3_FET_SHADOW_EN);
2183                         if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
2184                                 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
2185                                 tg3_writephy(tp,
2186                                              MII_TG3_FET_SHDW_AUXMODE4,
2187                                              phy);
2188                         }
2189                         tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2190                 }
2191                 return;
2192         } else if (do_low_power) {
2193                 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2194                              MII_TG3_EXT_CTRL_FORCE_LED_OFF);
2195
2196                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2197                              MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2198                              MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2199                              MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2200                              MII_TG3_AUXCTL_PCTL_VREG_11V);
2201         }
2202
2203         /* The PHY should not be powered down on some chips because
2204          * of bugs.
2205          */
2206         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2207             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2208             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2209              (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
2210                 return;
2211
2212         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2213             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2214                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2215                 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2216                 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2217                 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2218         }
2219
2220         tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2221 }
2222
2223 /* tp->lock is held. */
2224 static int tg3_nvram_lock(struct tg3 *tp)
2225 {
2226         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2227                 int i;
2228
2229                 if (tp->nvram_lock_cnt == 0) {
2230                         tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2231                         for (i = 0; i < 8000; i++) {
2232                                 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2233                                         break;
2234                                 udelay(20);
2235                         }
2236                         if (i == 8000) {
2237                                 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2238                                 return -ENODEV;
2239                         }
2240                 }
2241                 tp->nvram_lock_cnt++;
2242         }
2243         return 0;
2244 }
2245
2246 /* tp->lock is held. */
2247 static void tg3_nvram_unlock(struct tg3 *tp)
2248 {
2249         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2250                 if (tp->nvram_lock_cnt > 0)
2251                         tp->nvram_lock_cnt--;
2252                 if (tp->nvram_lock_cnt == 0)
2253                         tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2254         }
2255 }
2256
2257 /* tp->lock is held. */
2258 static void tg3_enable_nvram_access(struct tg3 *tp)
2259 {
2260         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2261             !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2262                 u32 nvaccess = tr32(NVRAM_ACCESS);
2263
2264                 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2265         }
2266 }
2267
2268 /* tp->lock is held. */
2269 static void tg3_disable_nvram_access(struct tg3 *tp)
2270 {
2271         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2272             !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2273                 u32 nvaccess = tr32(NVRAM_ACCESS);
2274
2275                 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2276         }
2277 }
2278
2279 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2280                                         u32 offset, u32 *val)
2281 {
2282         u32 tmp;
2283         int i;
2284
2285         if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2286                 return -EINVAL;
2287
2288         tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2289                                         EEPROM_ADDR_DEVID_MASK |
2290                                         EEPROM_ADDR_READ);
2291         tw32(GRC_EEPROM_ADDR,
2292              tmp |
2293              (0 << EEPROM_ADDR_DEVID_SHIFT) |
2294              ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2295               EEPROM_ADDR_ADDR_MASK) |
2296              EEPROM_ADDR_READ | EEPROM_ADDR_START);
2297
2298         for (i = 0; i < 1000; i++) {
2299                 tmp = tr32(GRC_EEPROM_ADDR);
2300
2301                 if (tmp & EEPROM_ADDR_COMPLETE)
2302                         break;
2303                 msleep(1);
2304         }
2305         if (!(tmp & EEPROM_ADDR_COMPLETE))
2306                 return -EBUSY;
2307
2308         tmp = tr32(GRC_EEPROM_DATA);
2309
2310         /*
2311          * The data will always be opposite the native endian
2312          * format.  Perform a blind byteswap to compensate.
2313          */
2314         *val = swab32(tmp);
2315
2316         return 0;
2317 }
2318
2319 #define NVRAM_CMD_TIMEOUT 10000
2320
2321 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2322 {
2323         int i;
2324
2325         tw32(NVRAM_CMD, nvram_cmd);
2326         for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2327                 udelay(10);
2328                 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2329                         udelay(10);
2330                         break;
2331                 }
2332         }
2333
2334         if (i == NVRAM_CMD_TIMEOUT)
2335                 return -EBUSY;
2336
2337         return 0;
2338 }
2339
2340 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2341 {
2342         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2343             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2344             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2345            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2346             (tp->nvram_jedecnum == JEDEC_ATMEL))
2347
2348                 addr = ((addr / tp->nvram_pagesize) <<
2349                         ATMEL_AT45DB0X1B_PAGE_POS) +
2350                        (addr % tp->nvram_pagesize);
2351
2352         return addr;
2353 }
2354
2355 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2356 {
2357         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2358             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2359             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2360            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2361             (tp->nvram_jedecnum == JEDEC_ATMEL))
2362
2363                 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2364                         tp->nvram_pagesize) +
2365                        (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2366
2367         return addr;
2368 }
2369
2370 /* NOTE: Data read in from NVRAM is byteswapped according to
2371  * the byteswapping settings for all other register accesses.
2372  * tg3 devices are BE devices, so on a BE machine, the data
2373  * returned will be exactly as it is seen in NVRAM.  On a LE
2374  * machine, the 32-bit value will be byteswapped.
2375  */
2376 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2377 {
2378         int ret;
2379
2380         if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2381                 return tg3_nvram_read_using_eeprom(tp, offset, val);
2382
2383         offset = tg3_nvram_phys_addr(tp, offset);
2384
2385         if (offset > NVRAM_ADDR_MSK)
2386                 return -EINVAL;
2387
2388         ret = tg3_nvram_lock(tp);
2389         if (ret)
2390                 return ret;
2391
2392         tg3_enable_nvram_access(tp);
2393
2394         tw32(NVRAM_ADDR, offset);
2395         ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2396                 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2397
2398         if (ret == 0)
2399                 *val = tr32(NVRAM_RDDATA);
2400
2401         tg3_disable_nvram_access(tp);
2402
2403         tg3_nvram_unlock(tp);
2404
2405         return ret;
2406 }
2407
2408 /* Ensures NVRAM data is in bytestream format. */
2409 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
2410 {
2411         u32 v;
2412         int res = tg3_nvram_read(tp, offset, &v);
2413         if (!res)
2414                 *val = cpu_to_be32(v);
2415         return res;
2416 }
2417
2418 /* tp->lock is held. */
2419 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2420 {
2421         u32 addr_high, addr_low;
2422         int i;
2423
2424         addr_high = ((tp->dev->dev_addr[0] << 8) |
2425                      tp->dev->dev_addr[1]);
2426         addr_low = ((tp->dev->dev_addr[2] << 24) |
2427                     (tp->dev->dev_addr[3] << 16) |
2428                     (tp->dev->dev_addr[4] <<  8) |
2429                     (tp->dev->dev_addr[5] <<  0));
2430         for (i = 0; i < 4; i++) {
2431                 if (i == 1 && skip_mac_1)
2432                         continue;
2433                 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2434                 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2435         }
2436
2437         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2438             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2439                 for (i = 0; i < 12; i++) {
2440                         tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2441                         tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2442                 }
2443         }
2444
2445         addr_high = (tp->dev->dev_addr[0] +
2446                      tp->dev->dev_addr[1] +
2447                      tp->dev->dev_addr[2] +
2448                      tp->dev->dev_addr[3] +
2449                      tp->dev->dev_addr[4] +
2450                      tp->dev->dev_addr[5]) &
2451                 TX_BACKOFF_SEED_MASK;
2452         tw32(MAC_TX_BACKOFF_SEED, addr_high);
2453 }
2454
2455 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
2456 {
2457         u32 misc_host_ctrl;
2458         bool device_should_wake, do_low_power;
2459
2460         /* Make sure register accesses (indirect or otherwise)
2461          * will function correctly.
2462          */
2463         pci_write_config_dword(tp->pdev,
2464                                TG3PCI_MISC_HOST_CTRL,
2465                                tp->misc_host_ctrl);
2466
2467         switch (state) {
2468         case PCI_D0:
2469                 pci_enable_wake(tp->pdev, state, false);
2470                 pci_set_power_state(tp->pdev, PCI_D0);
2471
2472                 /* Switch out of Vaux if it is a NIC */
2473                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
2474                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
2475
2476                 return 0;
2477
2478         case PCI_D1:
2479         case PCI_D2:
2480         case PCI_D3hot:
2481                 break;
2482
2483         default:
2484                 printk(KERN_ERR PFX "%s: Invalid power state (D%d) requested\n",
2485                         tp->dev->name, state);
2486                 return -EINVAL;
2487         }
2488
2489         /* Restore the CLKREQ setting. */
2490         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2491                 u16 lnkctl;
2492
2493                 pci_read_config_word(tp->pdev,
2494                                      tp->pcie_cap + PCI_EXP_LNKCTL,
2495                                      &lnkctl);
2496                 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2497                 pci_write_config_word(tp->pdev,
2498                                       tp->pcie_cap + PCI_EXP_LNKCTL,
2499                                       lnkctl);
2500         }
2501
2502         misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2503         tw32(TG3PCI_MISC_HOST_CTRL,
2504              misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2505
2506         device_should_wake = pci_pme_capable(tp->pdev, state) &&
2507                              device_may_wakeup(&tp->pdev->dev) &&
2508                              (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2509
2510         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
2511                 do_low_power = false;
2512                 if ((tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) &&
2513                     !tp->link_config.phy_is_low_power) {
2514                         struct phy_device *phydev;
2515                         u32 phyid, advertising;
2516
2517                         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
2518
2519                         tp->link_config.phy_is_low_power = 1;
2520
2521                         tp->link_config.orig_speed = phydev->speed;
2522                         tp->link_config.orig_duplex = phydev->duplex;
2523                         tp->link_config.orig_autoneg = phydev->autoneg;
2524                         tp->link_config.orig_advertising = phydev->advertising;
2525
2526                         advertising = ADVERTISED_TP |
2527                                       ADVERTISED_Pause |
2528                                       ADVERTISED_Autoneg |
2529                                       ADVERTISED_10baseT_Half;
2530
2531                         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2532                             device_should_wake) {
2533                                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2534                                         advertising |=
2535                                                 ADVERTISED_100baseT_Half |
2536                                                 ADVERTISED_100baseT_Full |
2537                                                 ADVERTISED_10baseT_Full;
2538                                 else
2539                                         advertising |= ADVERTISED_10baseT_Full;
2540                         }
2541
2542                         phydev->advertising = advertising;
2543
2544                         phy_start_aneg(phydev);
2545
2546                         phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2547                         if (phyid != TG3_PHY_ID_BCMAC131) {
2548                                 phyid &= TG3_PHY_OUI_MASK;
2549                                 if (phyid == TG3_PHY_OUI_1 ||
2550                                     phyid == TG3_PHY_OUI_2 ||
2551                                     phyid == TG3_PHY_OUI_3)
2552                                         do_low_power = true;
2553                         }
2554                 }
2555         } else {
2556                 do_low_power = true;
2557
2558                 if (tp->link_config.phy_is_low_power == 0) {
2559                         tp->link_config.phy_is_low_power = 1;
2560                         tp->link_config.orig_speed = tp->link_config.speed;
2561                         tp->link_config.orig_duplex = tp->link_config.duplex;
2562                         tp->link_config.orig_autoneg = tp->link_config.autoneg;
2563                 }
2564
2565                 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
2566                         tp->link_config.speed = SPEED_10;
2567                         tp->link_config.duplex = DUPLEX_HALF;
2568                         tp->link_config.autoneg = AUTONEG_ENABLE;
2569                         tg3_setup_phy(tp, 0);
2570                 }
2571         }
2572
2573         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2574                 u32 val;
2575
2576                 val = tr32(GRC_VCPU_EXT_CTRL);
2577                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2578         } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2579                 int i;
2580                 u32 val;
2581
2582                 for (i = 0; i < 200; i++) {
2583                         tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2584                         if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2585                                 break;
2586                         msleep(1);
2587                 }
2588         }
2589         if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2590                 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2591                                                      WOL_DRV_STATE_SHUTDOWN |
2592                                                      WOL_DRV_WOL |
2593                                                      WOL_SET_MAGIC_PKT);
2594
2595         if (device_should_wake) {
2596                 u32 mac_mode;
2597
2598                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
2599                         if (do_low_power) {
2600                                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2601                                 udelay(40);
2602                         }
2603
2604                         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
2605                                 mac_mode = MAC_MODE_PORT_MODE_GMII;
2606                         else
2607                                 mac_mode = MAC_MODE_PORT_MODE_MII;
2608
2609                         mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2610                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2611                             ASIC_REV_5700) {
2612                                 u32 speed = (tp->tg3_flags &
2613                                              TG3_FLAG_WOL_SPEED_100MB) ?
2614                                              SPEED_100 : SPEED_10;
2615                                 if (tg3_5700_link_polarity(tp, speed))
2616                                         mac_mode |= MAC_MODE_LINK_POLARITY;
2617                                 else
2618                                         mac_mode &= ~MAC_MODE_LINK_POLARITY;
2619                         }
2620                 } else {
2621                         mac_mode = MAC_MODE_PORT_MODE_TBI;
2622                 }
2623
2624                 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
2625                         tw32(MAC_LED_CTRL, tp->led_ctrl);
2626
2627                 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2628                 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2629                     !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2630                     ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2631                      (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2632                         mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
2633
2634                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2635                         mac_mode |= tp->mac_mode &
2636                                     (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
2637                         if (mac_mode & MAC_MODE_APE_TX_EN)
2638                                 mac_mode |= MAC_MODE_TDE_ENABLE;
2639                 }
2640
2641                 tw32_f(MAC_MODE, mac_mode);
2642                 udelay(100);
2643
2644                 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2645                 udelay(10);
2646         }
2647
2648         if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2649             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2650              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2651                 u32 base_val;
2652
2653                 base_val = tp->pci_clock_ctrl;
2654                 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2655                              CLOCK_CTRL_TXCLK_DISABLE);
2656
2657                 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2658                             CLOCK_CTRL_PWRDOWN_PLL133, 40);
2659         } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
2660                    (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
2661                    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
2662                 /* do nothing */
2663         } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2664                      (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2665                 u32 newbits1, newbits2;
2666
2667                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2668                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2669                         newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2670                                     CLOCK_CTRL_TXCLK_DISABLE |
2671                                     CLOCK_CTRL_ALTCLK);
2672                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2673                 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2674                         newbits1 = CLOCK_CTRL_625_CORE;
2675                         newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2676                 } else {
2677                         newbits1 = CLOCK_CTRL_ALTCLK;
2678                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2679                 }
2680
2681                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2682                             40);
2683
2684                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2685                             40);
2686
2687                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2688                         u32 newbits3;
2689
2690                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2691                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2692                                 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2693                                             CLOCK_CTRL_TXCLK_DISABLE |
2694                                             CLOCK_CTRL_44MHZ_CORE);
2695                         } else {
2696                                 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2697                         }
2698
2699                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
2700                                     tp->pci_clock_ctrl | newbits3, 40);
2701                 }
2702         }
2703
2704         if (!(device_should_wake) &&
2705             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
2706                 tg3_power_down_phy(tp, do_low_power);
2707
2708         tg3_frob_aux_power(tp);
2709
2710         /* Workaround for unstable PLL clock */
2711         if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2712             (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2713                 u32 val = tr32(0x7d00);
2714
2715                 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2716                 tw32(0x7d00, val);
2717                 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2718                         int err;
2719
2720                         err = tg3_nvram_lock(tp);
2721                         tg3_halt_cpu(tp, RX_CPU_BASE);
2722                         if (!err)
2723                                 tg3_nvram_unlock(tp);
2724                 }
2725         }
2726
2727         tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2728
2729         if (device_should_wake)
2730                 pci_enable_wake(tp->pdev, state, true);
2731
2732         /* Finally, set the new power state. */
2733         pci_set_power_state(tp->pdev, state);
2734
2735         return 0;
2736 }
2737
2738 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2739 {
2740         switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2741         case MII_TG3_AUX_STAT_10HALF:
2742                 *speed = SPEED_10;
2743                 *duplex = DUPLEX_HALF;
2744                 break;
2745
2746         case MII_TG3_AUX_STAT_10FULL:
2747                 *speed = SPEED_10;
2748                 *duplex = DUPLEX_FULL;
2749                 break;
2750
2751         case MII_TG3_AUX_STAT_100HALF:
2752                 *speed = SPEED_100;
2753                 *duplex = DUPLEX_HALF;
2754                 break;
2755
2756         case MII_TG3_AUX_STAT_100FULL:
2757                 *speed = SPEED_100;
2758                 *duplex = DUPLEX_FULL;
2759                 break;
2760
2761         case MII_TG3_AUX_STAT_1000HALF:
2762                 *speed = SPEED_1000;
2763                 *duplex = DUPLEX_HALF;
2764                 break;
2765
2766         case MII_TG3_AUX_STAT_1000FULL:
2767                 *speed = SPEED_1000;
2768                 *duplex = DUPLEX_FULL;
2769                 break;
2770
2771         default:
2772                 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
2773                         *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2774                                  SPEED_10;
2775                         *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2776                                   DUPLEX_HALF;
2777                         break;
2778                 }
2779                 *speed = SPEED_INVALID;
2780                 *duplex = DUPLEX_INVALID;
2781                 break;
2782         }
2783 }
2784
2785 static void tg3_phy_copper_begin(struct tg3 *tp)
2786 {
2787         u32 new_adv;
2788         int i;
2789
2790         if (tp->link_config.phy_is_low_power) {
2791                 /* Entering low power mode.  Disable gigabit and
2792                  * 100baseT advertisements.
2793                  */
2794                 tg3_writephy(tp, MII_TG3_CTRL, 0);
2795
2796                 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2797                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2798                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2799                         new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2800
2801                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2802         } else if (tp->link_config.speed == SPEED_INVALID) {
2803                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
2804                         tp->link_config.advertising &=
2805                                 ~(ADVERTISED_1000baseT_Half |
2806                                   ADVERTISED_1000baseT_Full);
2807
2808                 new_adv = ADVERTISE_CSMA;
2809                 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2810                         new_adv |= ADVERTISE_10HALF;
2811                 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2812                         new_adv |= ADVERTISE_10FULL;
2813                 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2814                         new_adv |= ADVERTISE_100HALF;
2815                 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2816                         new_adv |= ADVERTISE_100FULL;
2817
2818                 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2819
2820                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2821
2822                 if (tp->link_config.advertising &
2823                     (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2824                         new_adv = 0;
2825                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2826                                 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2827                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2828                                 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2829                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
2830                             (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2831                              tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2832                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2833                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2834                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2835                 } else {
2836                         tg3_writephy(tp, MII_TG3_CTRL, 0);
2837                 }
2838         } else {
2839                 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2840                 new_adv |= ADVERTISE_CSMA;
2841
2842                 /* Asking for a specific link mode. */
2843                 if (tp->link_config.speed == SPEED_1000) {
2844                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2845
2846                         if (tp->link_config.duplex == DUPLEX_FULL)
2847                                 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2848                         else
2849                                 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2850                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2851                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2852                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2853                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2854                 } else {
2855                         if (tp->link_config.speed == SPEED_100) {
2856                                 if (tp->link_config.duplex == DUPLEX_FULL)
2857                                         new_adv |= ADVERTISE_100FULL;
2858                                 else
2859                                         new_adv |= ADVERTISE_100HALF;
2860                         } else {
2861                                 if (tp->link_config.duplex == DUPLEX_FULL)
2862                                         new_adv |= ADVERTISE_10FULL;
2863                                 else
2864                                         new_adv |= ADVERTISE_10HALF;
2865                         }
2866                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2867
2868                         new_adv = 0;
2869                 }
2870
2871                 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2872         }
2873
2874         if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2875             tp->link_config.speed != SPEED_INVALID) {
2876                 u32 bmcr, orig_bmcr;
2877
2878                 tp->link_config.active_speed = tp->link_config.speed;
2879                 tp->link_config.active_duplex = tp->link_config.duplex;
2880
2881                 bmcr = 0;
2882                 switch (tp->link_config.speed) {
2883                 default:
2884                 case SPEED_10:
2885                         break;
2886
2887                 case SPEED_100:
2888                         bmcr |= BMCR_SPEED100;
2889                         break;
2890
2891                 case SPEED_1000:
2892                         bmcr |= TG3_BMCR_SPEED1000;
2893                         break;
2894                 }
2895
2896                 if (tp->link_config.duplex == DUPLEX_FULL)
2897                         bmcr |= BMCR_FULLDPLX;
2898
2899                 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2900                     (bmcr != orig_bmcr)) {
2901                         tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2902                         for (i = 0; i < 1500; i++) {
2903                                 u32 tmp;
2904
2905                                 udelay(10);
2906                                 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2907                                     tg3_readphy(tp, MII_BMSR, &tmp))
2908                                         continue;
2909                                 if (!(tmp & BMSR_LSTATUS)) {
2910                                         udelay(40);
2911                                         break;
2912                                 }
2913                         }
2914                         tg3_writephy(tp, MII_BMCR, bmcr);
2915                         udelay(40);
2916                 }
2917         } else {
2918                 tg3_writephy(tp, MII_BMCR,
2919                              BMCR_ANENABLE | BMCR_ANRESTART);
2920         }
2921 }
2922
2923 static int tg3_init_5401phy_dsp(struct tg3 *tp)
2924 {
2925         int err;
2926
2927         /* Turn off tap power management. */
2928         /* Set Extended packet length bit */
2929         err  = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2930
2931         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
2932         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
2933
2934         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
2935         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
2936
2937         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2938         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
2939
2940         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2941         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
2942
2943         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2944         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
2945
2946         udelay(40);
2947
2948         return err;
2949 }
2950
2951 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
2952 {
2953         u32 adv_reg, all_mask = 0;
2954
2955         if (mask & ADVERTISED_10baseT_Half)
2956                 all_mask |= ADVERTISE_10HALF;
2957         if (mask & ADVERTISED_10baseT_Full)
2958                 all_mask |= ADVERTISE_10FULL;
2959         if (mask & ADVERTISED_100baseT_Half)
2960                 all_mask |= ADVERTISE_100HALF;
2961         if (mask & ADVERTISED_100baseT_Full)
2962                 all_mask |= ADVERTISE_100FULL;
2963
2964         if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
2965                 return 0;
2966
2967         if ((adv_reg & all_mask) != all_mask)
2968                 return 0;
2969         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
2970                 u32 tg3_ctrl;
2971
2972                 all_mask = 0;
2973                 if (mask & ADVERTISED_1000baseT_Half)
2974                         all_mask |= ADVERTISE_1000HALF;
2975                 if (mask & ADVERTISED_1000baseT_Full)
2976                         all_mask |= ADVERTISE_1000FULL;
2977
2978                 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
2979                         return 0;
2980
2981                 if ((tg3_ctrl & all_mask) != all_mask)
2982                         return 0;
2983         }
2984         return 1;
2985 }
2986
2987 static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
2988 {
2989         u32 curadv, reqadv;
2990
2991         if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
2992                 return 1;
2993
2994         curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2995         reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2996
2997         if (tp->link_config.active_duplex == DUPLEX_FULL) {
2998                 if (curadv != reqadv)
2999                         return 0;
3000
3001                 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
3002                         tg3_readphy(tp, MII_LPA, rmtadv);
3003         } else {
3004                 /* Reprogram the advertisement register, even if it
3005                  * does not affect the current link.  If the link
3006                  * gets renegotiated in the future, we can save an
3007                  * additional renegotiation cycle by advertising
3008                  * it correctly in the first place.
3009                  */
3010                 if (curadv != reqadv) {
3011                         *lcladv &= ~(ADVERTISE_PAUSE_CAP |
3012                                      ADVERTISE_PAUSE_ASYM);
3013                         tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
3014                 }
3015         }
3016
3017         return 1;
3018 }
3019
3020 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
3021 {
3022         int current_link_up;
3023         u32 bmsr, dummy;
3024         u32 lcl_adv, rmt_adv;
3025         u16 current_speed;
3026         u8 current_duplex;
3027         int i, err;
3028
3029         tw32(MAC_EVENT, 0);
3030
3031         tw32_f(MAC_STATUS,
3032              (MAC_STATUS_SYNC_CHANGED |
3033               MAC_STATUS_CFG_CHANGED |
3034               MAC_STATUS_MI_COMPLETION |
3035               MAC_STATUS_LNKSTATE_CHANGED));
3036         udelay(40);
3037
3038         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
3039                 tw32_f(MAC_MI_MODE,
3040                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
3041                 udelay(80);
3042         }
3043
3044         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
3045
3046         /* Some third-party PHYs need to be reset on link going
3047          * down.
3048          */
3049         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3050              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
3051              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
3052             netif_carrier_ok(tp->dev)) {
3053                 tg3_readphy(tp, MII_BMSR, &bmsr);
3054                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3055                     !(bmsr & BMSR_LSTATUS))
3056                         force_reset = 1;
3057         }
3058         if (force_reset)
3059                 tg3_phy_reset(tp);
3060
3061         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
3062                 tg3_readphy(tp, MII_BMSR, &bmsr);
3063                 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
3064                     !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
3065                         bmsr = 0;
3066
3067                 if (!(bmsr & BMSR_LSTATUS)) {
3068                         err = tg3_init_5401phy_dsp(tp);
3069                         if (err)
3070                                 return err;
3071
3072                         tg3_readphy(tp, MII_BMSR, &bmsr);
3073                         for (i = 0; i < 1000; i++) {
3074                                 udelay(10);
3075                                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3076                                     (bmsr & BMSR_LSTATUS)) {
3077                                         udelay(40);
3078                                         break;
3079                                 }
3080                         }
3081
3082                         if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
3083                             !(bmsr & BMSR_LSTATUS) &&
3084                             tp->link_config.active_speed == SPEED_1000) {
3085                                 err = tg3_phy_reset(tp);
3086                                 if (!err)
3087                                         err = tg3_init_5401phy_dsp(tp);
3088                                 if (err)
3089                                         return err;
3090                         }
3091                 }
3092         } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3093                    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3094                 /* 5701 {A0,B0} CRC bug workaround */
3095                 tg3_writephy(tp, 0x15, 0x0a75);
3096                 tg3_writephy(tp, 0x1c, 0x8c68);
3097                 tg3_writephy(tp, 0x1c, 0x8d68);
3098                 tg3_writephy(tp, 0x1c, 0x8c68);
3099         }
3100
3101         /* Clear pending interrupts... */
3102         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3103         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3104
3105         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
3106                 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
3107         else if (!(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
3108                 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3109
3110         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3111             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3112                 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3113                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
3114                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3115                 else
3116                         tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3117         }
3118
3119         current_link_up = 0;
3120         current_speed = SPEED_INVALID;
3121         current_duplex = DUPLEX_INVALID;
3122
3123         if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
3124                 u32 val;
3125
3126                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3127                 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3128                 if (!(val & (1 << 10))) {
3129                         val |= (1 << 10);
3130                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3131                         goto relink;
3132                 }
3133         }
3134
3135         bmsr = 0;
3136         for (i = 0; i < 100; i++) {
3137                 tg3_readphy(tp, MII_BMSR, &bmsr);
3138                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3139                     (bmsr & BMSR_LSTATUS))
3140                         break;
3141                 udelay(40);
3142         }
3143
3144         if (bmsr & BMSR_LSTATUS) {
3145                 u32 aux_stat, bmcr;
3146
3147                 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3148                 for (i = 0; i < 2000; i++) {
3149                         udelay(10);
3150                         if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3151                             aux_stat)
3152                                 break;
3153                 }
3154
3155                 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3156                                              &current_speed,
3157                                              &current_duplex);
3158
3159                 bmcr = 0;
3160                 for (i = 0; i < 200; i++) {
3161                         tg3_readphy(tp, MII_BMCR, &bmcr);
3162                         if (tg3_readphy(tp, MII_BMCR, &bmcr))
3163                                 continue;
3164                         if (bmcr && bmcr != 0x7fff)
3165                                 break;
3166                         udelay(10);
3167                 }
3168
3169                 lcl_adv = 0;
3170                 rmt_adv = 0;
3171
3172                 tp->link_config.active_speed = current_speed;
3173                 tp->link_config.active_duplex = current_duplex;
3174
3175                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3176                         if ((bmcr & BMCR_ANENABLE) &&
3177                             tg3_copper_is_advertising_all(tp,
3178                                                 tp->link_config.advertising)) {
3179                                 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3180                                                                   &rmt_adv))
3181                                         current_link_up = 1;
3182                         }
3183                 } else {
3184                         if (!(bmcr & BMCR_ANENABLE) &&
3185                             tp->link_config.speed == current_speed &&
3186                             tp->link_config.duplex == current_duplex &&
3187                             tp->link_config.flowctrl ==
3188                             tp->link_config.active_flowctrl) {
3189                                 current_link_up = 1;
3190                         }
3191                 }
3192
3193                 if (current_link_up == 1 &&
3194                     tp->link_config.active_duplex == DUPLEX_FULL)
3195                         tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
3196         }
3197
3198 relink:
3199         if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
3200                 u32 tmp;
3201
3202                 tg3_phy_copper_begin(tp);
3203
3204                 tg3_readphy(tp, MII_BMSR, &tmp);
3205                 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
3206                     (tmp & BMSR_LSTATUS))
3207                         current_link_up = 1;
3208         }
3209
3210         tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3211         if (current_link_up == 1) {
3212                 if (tp->link_config.active_speed == SPEED_100 ||
3213                     tp->link_config.active_speed == SPEED_10)
3214                         tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3215                 else
3216                         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3217         } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)
3218                 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3219         else
3220                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3221
3222         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3223         if (tp->link_config.active_duplex == DUPLEX_HALF)
3224                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3225
3226         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
3227                 if (current_link_up == 1 &&
3228                     tg3_5700_link_polarity(tp, tp->link_config.active_speed))
3229                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
3230                 else
3231                         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
3232         }
3233
3234         /* ??? Without this setting Netgear GA302T PHY does not
3235          * ??? send/receive packets...
3236          */
3237         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
3238             tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3239                 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3240                 tw32_f(MAC_MI_MODE, tp->mi_mode);
3241                 udelay(80);
3242         }
3243
3244         tw32_f(MAC_MODE, tp->mac_mode);
3245         udelay(40);
3246
3247         if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3248                 /* Polled via timer. */
3249                 tw32_f(MAC_EVENT, 0);
3250         } else {
3251                 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3252         }
3253         udelay(40);
3254
3255         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3256             current_link_up == 1 &&
3257             tp->link_config.active_speed == SPEED_1000 &&
3258             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3259              (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3260                 udelay(120);
3261                 tw32_f(MAC_STATUS,
3262                      (MAC_STATUS_SYNC_CHANGED |
3263                       MAC_STATUS_CFG_CHANGED));
3264                 udelay(40);
3265                 tg3_write_mem(tp,
3266                               NIC_SRAM_FIRMWARE_MBOX,
3267                               NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3268         }
3269
3270         /* Prevent send BD corruption. */
3271         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3272                 u16 oldlnkctl, newlnkctl;
3273
3274                 pci_read_config_word(tp->pdev,
3275                                      tp->pcie_cap + PCI_EXP_LNKCTL,
3276                                      &oldlnkctl);
3277                 if (tp->link_config.active_speed == SPEED_100 ||
3278                     tp->link_config.active_speed == SPEED_10)
3279                         newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3280                 else
3281                         newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3282                 if (newlnkctl != oldlnkctl)
3283                         pci_write_config_word(tp->pdev,
3284                                               tp->pcie_cap + PCI_EXP_LNKCTL,
3285                                               newlnkctl);
3286         }
3287
3288         if (current_link_up != netif_carrier_ok(tp->dev)) {
3289                 if (current_link_up)
3290                         netif_carrier_on(tp->dev);
3291                 else
3292                         netif_carrier_off(tp->dev);
3293                 tg3_link_report(tp);
3294         }
3295
3296         return 0;
3297 }
3298
3299 struct tg3_fiber_aneginfo {
3300         int state;
3301 #define ANEG_STATE_UNKNOWN              0
3302 #define ANEG_STATE_AN_ENABLE            1
3303 #define ANEG_STATE_RESTART_INIT         2
3304 #define ANEG_STATE_RESTART              3
3305 #define ANEG_STATE_DISABLE_LINK_OK      4
3306 #define ANEG_STATE_ABILITY_DETECT_INIT  5
3307 #define ANEG_STATE_ABILITY_DETECT       6
3308 #define ANEG_STATE_ACK_DETECT_INIT      7
3309 #define ANEG_STATE_ACK_DETECT           8
3310 #define ANEG_STATE_COMPLETE_ACK_INIT    9
3311 #define ANEG_STATE_COMPLETE_ACK         10
3312 #define ANEG_STATE_IDLE_DETECT_INIT     11
3313 #define ANEG_STATE_IDLE_DETECT          12
3314 #define ANEG_STATE_LINK_OK              13
3315 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT  14
3316 #define ANEG_STATE_NEXT_PAGE_WAIT       15
3317
3318         u32 flags;
3319 #define MR_AN_ENABLE            0x00000001
3320 #define MR_RESTART_AN           0x00000002
3321 #define MR_AN_COMPLETE          0x00000004
3322 #define MR_PAGE_RX              0x00000008
3323 #define MR_NP_LOADED            0x00000010
3324 #define MR_TOGGLE_TX            0x00000020
3325 #define MR_LP_ADV_FULL_DUPLEX   0x00000040
3326 #define MR_LP_ADV_HALF_DUPLEX   0x00000080
3327 #define MR_LP_ADV_SYM_PAUSE     0x00000100
3328 #define MR_LP_ADV_ASYM_PAUSE    0x00000200
3329 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3330 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3331 #define MR_LP_ADV_NEXT_PAGE     0x00001000
3332 #define MR_TOGGLE_RX            0x00002000
3333 #define MR_NP_RX                0x00004000
3334
3335 #define MR_LINK_OK              0x80000000
3336
3337         unsigned long link_time, cur_time;
3338
3339         u32 ability_match_cfg;
3340         int ability_match_count;
3341
3342         char ability_match, idle_match, ack_match;
3343
3344         u32 txconfig, rxconfig;
3345 #define ANEG_CFG_NP             0x00000080
3346 #define ANEG_CFG_ACK            0x00000040
3347 #define ANEG_CFG_RF2            0x00000020
3348 #define ANEG_CFG_RF1            0x00000010
3349 #define ANEG_CFG_PS2            0x00000001
3350 #define ANEG_CFG_PS1            0x00008000
3351 #define ANEG_CFG_HD             0x00004000
3352 #define ANEG_CFG_FD             0x00002000
3353 #define ANEG_CFG_INVAL          0x00001f06
3354
3355 };
3356 #define ANEG_OK         0
3357 #define ANEG_DONE       1
3358 #define ANEG_TIMER_ENAB 2
3359 #define ANEG_FAILED     -1
3360
3361 #define ANEG_STATE_SETTLE_TIME  10000
3362
3363 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3364                                    struct tg3_fiber_aneginfo *ap)
3365 {
3366         u16 flowctrl;
3367         unsigned long delta;
3368         u32 rx_cfg_reg;
3369         int ret;
3370
3371         if (ap->state == ANEG_STATE_UNKNOWN) {
3372                 ap->rxconfig = 0;
3373                 ap->link_time = 0;
3374                 ap->cur_time = 0;
3375                 ap->ability_match_cfg = 0;
3376                 ap->ability_match_count = 0;
3377                 ap->ability_match = 0;
3378                 ap->idle_match = 0;
3379                 ap->ack_match = 0;
3380         }
3381         ap->cur_time++;
3382
3383         if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3384                 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3385
3386                 if (rx_cfg_reg != ap->ability_match_cfg) {
3387                         ap->ability_match_cfg = rx_cfg_reg;
3388                         ap->ability_match = 0;
3389                         ap->ability_match_count = 0;
3390                 } else {
3391                         if (++ap->ability_match_count > 1) {
3392                                 ap->ability_match = 1;
3393                                 ap->ability_match_cfg = rx_cfg_reg;
3394                         }
3395                 }
3396                 if (rx_cfg_reg & ANEG_CFG_ACK)
3397                         ap->ack_match = 1;
3398                 else
3399                         ap->ack_match = 0;
3400
3401                 ap->idle_match = 0;
3402         } else {
3403                 ap->idle_match = 1;
3404                 ap->ability_match_cfg = 0;
3405                 ap->ability_match_count = 0;
3406                 ap->ability_match = 0;
3407                 ap->ack_match = 0;
3408
3409                 rx_cfg_reg = 0;
3410         }
3411
3412         ap->rxconfig = rx_cfg_reg;
3413         ret = ANEG_OK;
3414
3415         switch(ap->state) {
3416         case ANEG_STATE_UNKNOWN:
3417                 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3418                         ap->state = ANEG_STATE_AN_ENABLE;
3419
3420                 /* fallthru */
3421         case ANEG_STATE_AN_ENABLE:
3422                 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3423                 if (ap->flags & MR_AN_ENABLE) {
3424                         ap->link_time = 0;
3425                         ap->cur_time = 0;
3426                         ap->ability_match_cfg = 0;
3427                         ap->ability_match_count = 0;
3428                         ap->ability_match = 0;
3429                         ap->idle_match = 0;
3430                         ap->ack_match = 0;
3431
3432                         ap->state = ANEG_STATE_RESTART_INIT;
3433                 } else {
3434                         ap->state = ANEG_STATE_DISABLE_LINK_OK;
3435                 }
3436                 break;
3437
3438         case ANEG_STATE_RESTART_INIT:
3439                 ap->link_time = ap->cur_time;
3440                 ap->flags &= ~(MR_NP_LOADED);
3441                 ap->txconfig = 0;
3442                 tw32(MAC_TX_AUTO_NEG, 0);
3443                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3444                 tw32_f(MAC_MODE, tp->mac_mode);
3445                 udelay(40);
3446
3447                 ret = ANEG_TIMER_ENAB;
3448                 ap->state = ANEG_STATE_RESTART;
3449
3450                 /* fallthru */
3451         case ANEG_STATE_RESTART:
3452                 delta = ap->cur_time - ap->link_time;
3453                 if (delta > ANEG_STATE_SETTLE_TIME) {
3454                         ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3455                 } else {
3456                         ret = ANEG_TIMER_ENAB;
3457                 }
3458                 break;
3459
3460         case ANEG_STATE_DISABLE_LINK_OK:
3461                 ret = ANEG_DONE;
3462                 break;
3463
3464         case ANEG_STATE_ABILITY_DETECT_INIT:
3465                 ap->flags &= ~(MR_TOGGLE_TX);
3466                 ap->txconfig = ANEG_CFG_FD;
3467                 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3468                 if (flowctrl & ADVERTISE_1000XPAUSE)
3469                         ap->txconfig |= ANEG_CFG_PS1;
3470                 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3471                         ap->txconfig |= ANEG_CFG_PS2;
3472                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3473                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3474                 tw32_f(MAC_MODE, tp->mac_mode);
3475                 udelay(40);
3476
3477                 ap->state = ANEG_STATE_ABILITY_DETECT;
3478                 break;
3479
3480         case ANEG_STATE_ABILITY_DETECT:
3481                 if (ap->ability_match != 0 && ap->rxconfig != 0) {
3482                         ap->state = ANEG_STATE_ACK_DETECT_INIT;
3483                 }
3484                 break;
3485
3486         case ANEG_STATE_ACK_DETECT_INIT:
3487                 ap->txconfig |= ANEG_CFG_ACK;
3488                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3489                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3490                 tw32_f(MAC_MODE, tp->mac_mode);
3491                 udelay(40);
3492
3493                 ap->state = ANEG_STATE_ACK_DETECT;
3494
3495                 /* fallthru */
3496         case ANEG_STATE_ACK_DETECT:
3497                 if (ap->ack_match != 0) {
3498                         if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3499                             (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3500                                 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3501                         } else {
3502                                 ap->state = ANEG_STATE_AN_ENABLE;
3503                         }
3504                 } else if (ap->ability_match != 0 &&
3505                            ap->rxconfig == 0) {
3506                         ap->state = ANEG_STATE_AN_ENABLE;
3507                 }
3508                 break;
3509
3510         case ANEG_STATE_COMPLETE_ACK_INIT:
3511                 if (ap->rxconfig & ANEG_CFG_INVAL) {
3512                         ret = ANEG_FAILED;
3513                         break;
3514                 }
3515                 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3516                                MR_LP_ADV_HALF_DUPLEX |
3517                                MR_LP_ADV_SYM_PAUSE |
3518                                MR_LP_ADV_ASYM_PAUSE |
3519                                MR_LP_ADV_REMOTE_FAULT1 |
3520                                MR_LP_ADV_REMOTE_FAULT2 |
3521                                MR_LP_ADV_NEXT_PAGE |
3522                                MR_TOGGLE_RX |
3523                                MR_NP_RX);
3524                 if (ap->rxconfig & ANEG_CFG_FD)
3525                         ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3526                 if (ap->rxconfig & ANEG_CFG_HD)
3527                         ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3528                 if (ap->rxconfig & ANEG_CFG_PS1)
3529                         ap->flags |= MR_LP_ADV_SYM_PAUSE;
3530                 if (ap->rxconfig & ANEG_CFG_PS2)
3531                         ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3532                 if (ap->rxconfig & ANEG_CFG_RF1)
3533                         ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3534                 if (ap->rxconfig & ANEG_CFG_RF2)
3535                         ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3536                 if (ap->rxconfig & ANEG_CFG_NP)
3537                         ap->flags |= MR_LP_ADV_NEXT_PAGE;
3538
3539                 ap->link_time = ap->cur_time;
3540
3541                 ap->flags ^= (MR_TOGGLE_TX);
3542                 if (ap->rxconfig & 0x0008)
3543                         ap->flags |= MR_TOGGLE_RX;
3544                 if (ap->rxconfig & ANEG_CFG_NP)
3545                         ap->flags |= MR_NP_RX;
3546                 ap->flags |= MR_PAGE_RX;
3547
3548                 ap->state = ANEG_STATE_COMPLETE_ACK;
3549                 ret = ANEG_TIMER_ENAB;
3550                 break;
3551
3552         case ANEG_STATE_COMPLETE_ACK:
3553                 if (ap->ability_match != 0 &&
3554                     ap->rxconfig == 0) {
3555                         ap->state = ANEG_STATE_AN_ENABLE;
3556                         break;
3557                 }
3558                 delta = ap->cur_time - ap->link_time;
3559                 if (delta > ANEG_STATE_SETTLE_TIME) {
3560                         if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3561                                 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3562                         } else {
3563                                 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3564                                     !(ap->flags & MR_NP_RX)) {
3565                                         ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3566                                 } else {
3567                                         ret = ANEG_FAILED;
3568                                 }
3569                         }
3570                 }
3571                 break;
3572
3573         case ANEG_STATE_IDLE_DETECT_INIT:
3574                 ap->link_time = ap->cur_time;
3575                 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3576                 tw32_f(MAC_MODE, tp->mac_mode);
3577                 udelay(40);
3578
3579                 ap->state = ANEG_STATE_IDLE_DETECT;
3580                 ret = ANEG_TIMER_ENAB;
3581                 break;
3582
3583         case ANEG_STATE_IDLE_DETECT:
3584                 if (ap->ability_match != 0 &&
3585                     ap->rxconfig == 0) {
3586                         ap->state = ANEG_STATE_AN_ENABLE;
3587                         break;
3588                 }
3589                 delta = ap->cur_time - ap->link_time;
3590                 if (delta > ANEG_STATE_SETTLE_TIME) {
3591                         /* XXX another gem from the Broadcom driver :( */
3592                         ap->state = ANEG_STATE_LINK_OK;
3593                 }
3594                 break;
3595
3596         case ANEG_STATE_LINK_OK:
3597                 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3598                 ret = ANEG_DONE;
3599                 break;
3600
3601         case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3602                 /* ??? unimplemented */
3603                 break;
3604
3605         case ANEG_STATE_NEXT_PAGE_WAIT:
3606                 /* ??? unimplemented */
3607                 break;
3608
3609         default:
3610                 ret = ANEG_FAILED;
3611                 break;
3612         }
3613
3614         return ret;
3615 }
3616
3617 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
3618 {
3619         int res = 0;
3620         struct tg3_fiber_aneginfo aninfo;
3621         int status = ANEG_FAILED;
3622         unsigned int tick;
3623         u32 tmp;
3624
3625         tw32_f(MAC_TX_AUTO_NEG, 0);
3626
3627         tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3628         tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3629         udelay(40);
3630
3631         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3632         udelay(40);
3633
3634         memset(&aninfo, 0, sizeof(aninfo));
3635         aninfo.flags |= MR_AN_ENABLE;
3636         aninfo.state = ANEG_STATE_UNKNOWN;
3637         aninfo.cur_time = 0;
3638         tick = 0;
3639         while (++tick < 195000) {
3640                 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3641                 if (status == ANEG_DONE || status == ANEG_FAILED)
3642                         break;
3643
3644                 udelay(1);
3645         }
3646
3647         tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3648         tw32_f(MAC_MODE, tp->mac_mode);
3649         udelay(40);
3650
3651         *txflags = aninfo.txconfig;
3652         *rxflags = aninfo.flags;
3653
3654         if (status == ANEG_DONE &&
3655             (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3656                              MR_LP_ADV_FULL_DUPLEX)))
3657                 res = 1;
3658
3659         return res;
3660 }
3661
3662 static void tg3_init_bcm8002(struct tg3 *tp)
3663 {
3664         u32 mac_status = tr32(MAC_STATUS);
3665         int i;
3666
3667         /* Reset when initting first time or we have a link. */
3668         if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3669             !(mac_status & MAC_STATUS_PCS_SYNCED))
3670                 return;
3671
3672         /* Set PLL lock range. */
3673         tg3_writephy(tp, 0x16, 0x8007);
3674
3675         /* SW reset */
3676         tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3677
3678         /* Wait for reset to complete. */
3679         /* XXX schedule_timeout() ... */
3680         for (i = 0; i < 500; i++)
3681                 udelay(10);
3682
3683         /* Config mode; select PMA/Ch 1 regs. */
3684         tg3_writephy(tp, 0x10, 0x8411);
3685
3686         /* Enable auto-lock and comdet, select txclk for tx. */
3687         tg3_writephy(tp, 0x11, 0x0a10);
3688
3689         tg3_writephy(tp, 0x18, 0x00a0);
3690         tg3_writephy(tp, 0x16, 0x41ff);
3691
3692         /* Assert and deassert POR. */
3693         tg3_writephy(tp, 0x13, 0x0400);
3694         udelay(40);
3695         tg3_writephy(tp, 0x13, 0x0000);
3696
3697         tg3_writephy(tp, 0x11, 0x0a50);
3698         udelay(40);
3699         tg3_writephy(tp, 0x11, 0x0a10);
3700
3701         /* Wait for signal to stabilize */
3702         /* XXX schedule_timeout() ... */
3703         for (i = 0; i < 15000; i++)
3704                 udelay(10);
3705
3706         /* Deselect the channel register so we can read the PHYID
3707          * later.
3708          */
3709         tg3_writephy(tp, 0x10, 0x8011);
3710 }
3711
3712 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3713 {
3714         u16 flowctrl;
3715         u32 sg_dig_ctrl, sg_dig_status;
3716         u32 serdes_cfg, expected_sg_dig_ctrl;
3717         int workaround, port_a;
3718         int current_link_up;
3719
3720         serdes_cfg = 0;
3721         expected_sg_dig_ctrl = 0;
3722         workaround = 0;
3723         port_a = 1;
3724         current_link_up = 0;
3725
3726         if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3727             tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3728                 workaround = 1;
3729                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3730                         port_a = 0;
3731
3732                 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3733                 /* preserve bits 20-23 for voltage regulator */
3734                 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3735         }
3736
3737         sg_dig_ctrl = tr32(SG_DIG_CTRL);
3738
3739         if (tp->link_config.autoneg != AUTONEG_ENABLE) {
3740                 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
3741                         if (workaround) {
3742                                 u32 val = serdes_cfg;
3743
3744                                 if (port_a)
3745                                         val |= 0xc010000;
3746                                 else
3747                                         val |= 0x4010000;
3748                                 tw32_f(MAC_SERDES_CFG, val);
3749                         }
3750
3751                         tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3752                 }
3753                 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3754                         tg3_setup_flow_control(tp, 0, 0);
3755                         current_link_up = 1;
3756                 }
3757                 goto out;
3758         }
3759
3760         /* Want auto-negotiation.  */
3761         expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
3762
3763         flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3764         if (flowctrl & ADVERTISE_1000XPAUSE)
3765                 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3766         if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3767                 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
3768
3769         if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3770                 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
3771                     tp->serdes_counter &&
3772                     ((mac_status & (MAC_STATUS_PCS_SYNCED |
3773                                     MAC_STATUS_RCVD_CFG)) ==
3774                      MAC_STATUS_PCS_SYNCED)) {
3775                         tp->serdes_counter--;
3776                         current_link_up = 1;
3777                         goto out;
3778                 }
3779 restart_autoneg:
3780                 if (workaround)
3781                         tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
3782                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
3783                 udelay(5);
3784                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3785
3786                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3787                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3788         } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3789                                  MAC_STATUS_SIGNAL_DET)) {
3790                 sg_dig_status = tr32(SG_DIG_STATUS);
3791                 mac_status = tr32(MAC_STATUS);
3792
3793                 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
3794                     (mac_status & MAC_STATUS_PCS_SYNCED)) {
3795                         u32 local_adv = 0, remote_adv = 0;
3796
3797                         if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3798                                 local_adv |= ADVERTISE_1000XPAUSE;
3799                         if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3800                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3801
3802                         if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
3803                                 remote_adv |= LPA_1000XPAUSE;
3804                         if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
3805                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3806
3807                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3808                         current_link_up = 1;
3809                         tp->serdes_counter = 0;
3810                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3811                 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3812                         if (tp->serdes_counter)
3813                                 tp->serdes_counter--;
3814                         else {
3815                                 if (workaround) {
3816                                         u32 val = serdes_cfg;
3817
3818                                         if (port_a)
3819                                                 val |= 0xc010000;
3820                                         else
3821                                                 val |= 0x4010000;
3822
3823                                         tw32_f(MAC_SERDES_CFG, val);
3824                                 }
3825
3826                                 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3827                                 udelay(40);
3828
3829                                 /* Link parallel detection - link is up */
3830                                 /* only if we have PCS_SYNC and not */
3831                                 /* receiving config code words */
3832                                 mac_status = tr32(MAC_STATUS);
3833                                 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3834                                     !(mac_status & MAC_STATUS_RCVD_CFG)) {
3835                                         tg3_setup_flow_control(tp, 0, 0);
3836                                         current_link_up = 1;
3837                                         tp->tg3_flags2 |=
3838                                                 TG3_FLG2_PARALLEL_DETECT;
3839                                         tp->serdes_counter =
3840                                                 SERDES_PARALLEL_DET_TIMEOUT;
3841                                 } else
3842                                         goto restart_autoneg;
3843                         }
3844                 }
3845         } else {
3846                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3847                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3848         }
3849
3850 out:
3851         return current_link_up;
3852 }
3853
3854 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3855 {
3856         int current_link_up = 0;
3857
3858         if (!(mac_status & MAC_STATUS_PCS_SYNCED))
3859                 goto out;
3860
3861         if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3862                 u32 txflags, rxflags;
3863                 int i;
3864
3865                 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3866                         u32 local_adv = 0, remote_adv = 0;
3867
3868                         if (txflags & ANEG_CFG_PS1)
3869                                 local_adv |= ADVERTISE_1000XPAUSE;
3870                         if (txflags & ANEG_CFG_PS2)
3871                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3872
3873                         if (rxflags & MR_LP_ADV_SYM_PAUSE)
3874                                 remote_adv |= LPA_1000XPAUSE;
3875                         if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3876                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3877
3878                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3879
3880                         current_link_up = 1;
3881                 }
3882                 for (i = 0; i < 30; i++) {
3883                         udelay(20);
3884                         tw32_f(MAC_STATUS,
3885                                (MAC_STATUS_SYNC_CHANGED |
3886                                 MAC_STATUS_CFG_CHANGED));
3887                         udelay(40);
3888                         if ((tr32(MAC_STATUS) &
3889                              (MAC_STATUS_SYNC_CHANGED |
3890                               MAC_STATUS_CFG_CHANGED)) == 0)
3891                                 break;
3892                 }
3893
3894                 mac_status = tr32(MAC_STATUS);
3895                 if (current_link_up == 0 &&
3896                     (mac_status & MAC_STATUS_PCS_SYNCED) &&
3897                     !(mac_status & MAC_STATUS_RCVD_CFG))
3898                         current_link_up = 1;
3899         } else {
3900                 tg3_setup_flow_control(tp, 0, 0);
3901
3902                 /* Forcing 1000FD link up. */
3903                 current_link_up = 1;
3904
3905                 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3906                 udelay(40);
3907
3908                 tw32_f(MAC_MODE, tp->mac_mode);
3909                 udelay(40);
3910         }
3911
3912 out:
3913         return current_link_up;
3914 }
3915
3916 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3917 {
3918         u32 orig_pause_cfg;
3919         u16 orig_active_speed;
3920         u8 orig_active_duplex;
3921         u32 mac_status;
3922         int current_link_up;
3923         int i;
3924
3925         orig_pause_cfg = tp->link_config.active_flowctrl;
3926         orig_active_speed = tp->link_config.active_speed;
3927         orig_active_duplex = tp->link_config.active_duplex;
3928
3929         if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3930             netif_carrier_ok(tp->dev) &&
3931             (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3932                 mac_status = tr32(MAC_STATUS);
3933                 mac_status &= (MAC_STATUS_PCS_SYNCED |
3934                                MAC_STATUS_SIGNAL_DET |
3935                                MAC_STATUS_CFG_CHANGED |
3936                                MAC_STATUS_RCVD_CFG);
3937                 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3938                                    MAC_STATUS_SIGNAL_DET)) {
3939                         tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3940                                             MAC_STATUS_CFG_CHANGED));
3941                         return 0;
3942                 }
3943         }
3944
3945         tw32_f(MAC_TX_AUTO_NEG, 0);
3946
3947         tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
3948         tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
3949         tw32_f(MAC_MODE, tp->mac_mode);
3950         udelay(40);
3951
3952         if (tp->phy_id == PHY_ID_BCM8002)
3953                 tg3_init_bcm8002(tp);
3954
3955         /* Enable link change event even when serdes polling.  */
3956         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3957         udelay(40);
3958
3959         current_link_up = 0;
3960         mac_status = tr32(MAC_STATUS);
3961
3962         if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
3963                 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
3964         else
3965                 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
3966
3967         tp->napi[0].hw_status->status =
3968                 (SD_STATUS_UPDATED |
3969                  (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
3970
3971         for (i = 0; i < 100; i++) {
3972                 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3973                                     MAC_STATUS_CFG_CHANGED));
3974                 udelay(5);
3975                 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3976                                          MAC_STATUS_CFG_CHANGED |
3977                                          MAC_STATUS_LNKSTATE_CHANGED)) == 0)
3978                         break;
3979         }
3980
3981         mac_status = tr32(MAC_STATUS);
3982         if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
3983                 current_link_up = 0;
3984                 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
3985                     tp->serdes_counter == 0) {
3986                         tw32_f(MAC_MODE, (tp->mac_mode |
3987                                           MAC_MODE_SEND_CONFIGS));
3988                         udelay(1);
3989                         tw32_f(MAC_MODE, tp->mac_mode);
3990                 }
3991         }
3992
3993         if (current_link_up == 1) {
3994                 tp->link_config.active_speed = SPEED_1000;
3995                 tp->link_config.active_duplex = DUPLEX_FULL;
3996                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3997                                     LED_CTRL_LNKLED_OVERRIDE |
3998                                     LED_CTRL_1000MBPS_ON));
3999         } else {
4000                 tp->link_config.active_speed = SPEED_INVALID;
4001                 tp->link_config.active_duplex = DUPLEX_INVALID;
4002                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4003                                     LED_CTRL_LNKLED_OVERRIDE |
4004                                     LED_CTRL_TRAFFIC_OVERRIDE));
4005         }
4006
4007         if (current_link_up != netif_carrier_ok(tp->dev)) {
4008                 if (current_link_up)
4009                         netif_carrier_on(tp->dev);
4010                 else
4011                         netif_carrier_off(tp->dev);
4012                 tg3_link_report(tp);
4013         } else {
4014                 u32 now_pause_cfg = tp->link_config.active_flowctrl;
4015                 if (orig_pause_cfg != now_pause_cfg ||
4016                     orig_active_speed != tp->link_config.active_speed ||
4017                     orig_active_duplex != tp->link_config.active_duplex)
4018                         tg3_link_report(tp);
4019         }
4020
4021         return 0;
4022 }
4023
4024 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
4025 {
4026         int current_link_up, err = 0;
4027         u32 bmsr, bmcr;
4028         u16 current_speed;
4029         u8 current_duplex;
4030         u32 local_adv, remote_adv;
4031
4032         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4033         tw32_f(MAC_MODE, tp->mac_mode);
4034         udelay(40);
4035
4036         tw32(MAC_EVENT, 0);
4037
4038         tw32_f(MAC_STATUS,
4039              (MAC_STATUS_SYNC_CHANGED |
4040               MAC_STATUS_CFG_CHANGED |
4041               MAC_STATUS_MI_COMPLETION |
4042               MAC_STATUS_LNKSTATE_CHANGED));
4043         udelay(40);
4044
4045         if (force_reset)
4046                 tg3_phy_reset(tp);
4047
4048         current_link_up = 0;
4049         current_speed = SPEED_INVALID;
4050         current_duplex = DUPLEX_INVALID;
4051
4052         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4053         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4054         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
4055                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4056                         bmsr |= BMSR_LSTATUS;
4057                 else
4058                         bmsr &= ~BMSR_LSTATUS;
4059         }
4060
4061         err |= tg3_readphy(tp, MII_BMCR, &bmcr);
4062
4063         if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
4064             (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4065                 /* do nothing, just check for link up at the end */
4066         } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4067                 u32 adv, new_adv;
4068
4069                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4070                 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4071                                   ADVERTISE_1000XPAUSE |
4072                                   ADVERTISE_1000XPSE_ASYM |
4073                                   ADVERTISE_SLCT);
4074
4075                 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4076
4077                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4078                         new_adv |= ADVERTISE_1000XHALF;
4079                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4080                         new_adv |= ADVERTISE_1000XFULL;
4081
4082                 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4083                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
4084                         bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4085                         tg3_writephy(tp, MII_BMCR, bmcr);
4086
4087                         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4088                         tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
4089                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4090
4091                         return err;
4092                 }
4093         } else {
4094                 u32 new_bmcr;
4095
4096                 bmcr &= ~BMCR_SPEED1000;
4097                 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4098
4099                 if (tp->link_config.duplex == DUPLEX_FULL)
4100                         new_bmcr |= BMCR_FULLDPLX;
4101
4102                 if (new_bmcr != bmcr) {
4103                         /* BMCR_SPEED1000 is a reserved bit that needs
4104                          * to be set on write.
4105                          */
4106                         new_bmcr |= BMCR_SPEED1000;
4107
4108                         /* Force a linkdown */
4109                         if (netif_carrier_ok(tp->dev)) {
4110                                 u32 adv;
4111
4112                                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4113                                 adv &= ~(ADVERTISE_1000XFULL |
4114                                          ADVERTISE_1000XHALF |
4115                                          ADVERTISE_SLCT);
4116                                 tg3_writephy(tp, MII_ADVERTISE, adv);
4117                                 tg3_writephy(tp, MII_BMCR, bmcr |
4118                                                            BMCR_ANRESTART |
4119                                                            BMCR_ANENABLE);
4120                                 udelay(10);
4121                                 netif_carrier_off(tp->dev);
4122                         }
4123                         tg3_writephy(tp, MII_BMCR, new_bmcr);
4124                         bmcr = new_bmcr;
4125                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4126                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4127                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4128                             ASIC_REV_5714) {
4129                                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4130                                         bmsr |= BMSR_LSTATUS;
4131                                 else
4132                                         bmsr &= ~BMSR_LSTATUS;
4133                         }
4134                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4135                 }
4136         }
4137
4138         if (bmsr & BMSR_LSTATUS) {
4139                 current_speed = SPEED_1000;
4140                 current_link_up = 1;
4141                 if (bmcr & BMCR_FULLDPLX)
4142                         current_duplex = DUPLEX_FULL;
4143                 else
4144                         current_duplex = DUPLEX_HALF;
4145
4146                 local_adv = 0;
4147                 remote_adv = 0;
4148
4149                 if (bmcr & BMCR_ANENABLE) {
4150                         u32 common;
4151
4152                         err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4153                         err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4154                         common = local_adv & remote_adv;
4155                         if (common & (ADVERTISE_1000XHALF |
4156                                       ADVERTISE_1000XFULL)) {
4157                                 if (common & ADVERTISE_1000XFULL)
4158                                         current_duplex = DUPLEX_FULL;
4159                                 else
4160                                         current_duplex = DUPLEX_HALF;
4161                         }
4162                         else
4163                                 current_link_up = 0;
4164                 }
4165         }
4166
4167         if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4168                 tg3_setup_flow_control(tp, local_adv, remote_adv);
4169
4170         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4171         if (tp->link_config.active_duplex == DUPLEX_HALF)
4172                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4173
4174         tw32_f(MAC_MODE, tp->mac_mode);
4175         udelay(40);
4176
4177         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4178
4179         tp->link_config.active_speed = current_speed;
4180         tp->link_config.active_duplex = current_duplex;
4181
4182         if (current_link_up != netif_carrier_ok(tp->dev)) {
4183                 if (current_link_up)
4184                         netif_carrier_on(tp->dev);
4185                 else {
4186                         netif_carrier_off(tp->dev);
4187                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4188                 }
4189                 tg3_link_report(tp);
4190         }
4191         return err;
4192 }
4193
4194 static void tg3_serdes_parallel_detect(struct tg3 *tp)
4195 {
4196         if (tp->serdes_counter) {
4197                 /* Give autoneg time to complete. */
4198                 tp->serdes_counter--;
4199                 return;
4200         }
4201         if (!netif_carrier_ok(tp->dev) &&
4202             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4203                 u32 bmcr;
4204
4205                 tg3_readphy(tp, MII_BMCR, &bmcr);
4206                 if (bmcr & BMCR_ANENABLE) {
4207                         u32 phy1, phy2;
4208
4209                         /* Select shadow register 0x1f */
4210                         tg3_writephy(tp, 0x1c, 0x7c00);
4211                         tg3_readphy(tp, 0x1c, &phy1);
4212
4213                         /* Select expansion interrupt status register */
4214                         tg3_writephy(tp, 0x17, 0x0f01);
4215                         tg3_readphy(tp, 0x15, &phy2);
4216                         tg3_readphy(tp, 0x15, &phy2);
4217
4218                         if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4219                                 /* We have signal detect and not receiving
4220                                  * config code words, link is up by parallel
4221                                  * detection.
4222                                  */
4223
4224                                 bmcr &= ~BMCR_ANENABLE;
4225                                 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4226                                 tg3_writephy(tp, MII_BMCR, bmcr);
4227                                 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
4228                         }
4229                 }
4230         }
4231         else if (netif_carrier_ok(tp->dev) &&
4232                  (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4233                  (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4234                 u32 phy2;
4235
4236                 /* Select expansion interrupt status register */
4237                 tg3_writephy(tp, 0x17, 0x0f01);
4238                 tg3_readphy(tp, 0x15, &phy2);
4239                 if (phy2 & 0x20) {
4240                         u32 bmcr;
4241
4242                         /* Config code words received, turn on autoneg. */
4243                         tg3_readphy(tp, MII_BMCR, &bmcr);
4244                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4245
4246                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4247
4248                 }
4249         }
4250 }
4251
4252 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4253 {
4254         int err;
4255
4256         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
4257                 err = tg3_setup_fiber_phy(tp, force_reset);
4258         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
4259                 err = tg3_setup_fiber_mii_phy(tp, force_reset);
4260         } else {
4261                 err = tg3_setup_copper_phy(tp, force_reset);
4262         }
4263
4264         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
4265                 u32 val, scale;
4266
4267                 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4268                 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4269                         scale = 65;
4270                 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4271                         scale = 6;
4272                 else
4273                         scale = 12;
4274
4275                 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4276                 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4277                 tw32(GRC_MISC_CFG, val);
4278         }
4279
4280         if (tp->link_config.active_speed == SPEED_1000 &&
4281             tp->link_config.active_duplex == DUPLEX_HALF)
4282                 tw32(MAC_TX_LENGTHS,
4283                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4284                       (6 << TX_LENGTHS_IPG_SHIFT) |
4285                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
4286         else
4287                 tw32(MAC_TX_LENGTHS,
4288                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4289                       (6 << TX_LENGTHS_IPG_SHIFT) |
4290                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
4291
4292         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4293                 if (netif_carrier_ok(tp->dev)) {
4294                         tw32(HOSTCC_STAT_COAL_TICKS,
4295                              tp->coal.stats_block_coalesce_usecs);
4296                 } else {
4297                         tw32(HOSTCC_STAT_COAL_TICKS, 0);
4298                 }
4299         }
4300
4301         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4302                 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
4303                 if (!netif_carrier_ok(tp->dev))
4304                         val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4305                               tp->pwrmgmt_thresh;
4306                 else
4307                         val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4308                 tw32(PCIE_PWR_MGMT_THRESH, val);
4309         }
4310
4311         return err;
4312 }
4313
4314 /* This is called whenever we suspect that the system chipset is re-
4315  * ordering the sequence of MMIO to the tx send mailbox. The symptom
4316  * is bogus tx completions. We try to recover by setting the
4317  * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4318  * in the workqueue.
4319  */
4320 static void tg3_tx_recover(struct tg3 *tp)
4321 {
4322         BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4323                tp->write32_tx_mbox == tg3_write_indirect_mbox);
4324
4325         printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
4326                "mapped I/O cycles to the network device, attempting to "
4327                "recover. Please report the problem to the driver maintainer "
4328                "and include system chipset information.\n", tp->dev->name);
4329
4330         spin_lock(&tp->lock);
4331         tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
4332         spin_unlock(&tp->lock);
4333 }
4334
4335 static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
4336 {
4337         smp_mb();
4338         return tnapi->tx_pending -
4339                ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
4340 }
4341
4342 /* Tigon3 never reports partial packet sends.  So we do not
4343  * need special logic to handle SKBs that have not had all
4344  * of their frags sent yet, like SunGEM does.
4345  */
4346 static void tg3_tx(struct tg3_napi *tnapi)
4347 {
4348         struct tg3 *tp = tnapi->tp;
4349         u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
4350         u32 sw_idx = tnapi->tx_cons;
4351         struct netdev_queue *txq;
4352         int index = tnapi - tp->napi;
4353
4354         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
4355                 index--;
4356
4357         txq = netdev_get_tx_queue(tp->dev, index);
4358
4359         while (sw_idx != hw_idx) {
4360                 struct ring_info *ri = &tnapi->tx_buffers[sw_idx];
4361                 struct sk_buff *skb = ri->skb;
4362                 int i, tx_bug = 0;
4363
4364                 if (unlikely(skb == NULL)) {
4365                         tg3_tx_recover(tp);
4366                         return;
4367                 }
4368
4369                 pci_unmap_single(tp->pdev,
4370                                  pci_unmap_addr(ri, mapping),
4371                                  skb_headlen(skb),
4372                                  PCI_DMA_TODEVICE);
4373
4374                 ri->skb = NULL;
4375
4376                 sw_idx = NEXT_TX(sw_idx);
4377
4378                 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
4379                         ri = &tnapi->tx_buffers[sw_idx];
4380                         if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4381                                 tx_bug = 1;
4382
4383                         pci_unmap_page(tp->pdev,
4384                                        pci_unmap_addr(ri, mapping),
4385                                        skb_shinfo(skb)->frags[i].size,
4386                                        PCI_DMA_TODEVICE);
4387                         sw_idx = NEXT_TX(sw_idx);
4388                 }
4389
4390                 dev_kfree_skb(skb);
4391
4392                 if (unlikely(tx_bug)) {
4393                         tg3_tx_recover(tp);
4394                         return;
4395                 }
4396         }
4397
4398         tnapi->tx_cons = sw_idx;
4399
4400         /* Need to make the tx_cons update visible to tg3_start_xmit()
4401          * before checking for netif_queue_stopped().  Without the
4402          * memory barrier, there is a small possibility that tg3_start_xmit()
4403          * will miss it and cause the queue to be stopped forever.
4404          */
4405         smp_mb();
4406
4407         if (unlikely(netif_tx_queue_stopped(txq) &&
4408                      (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
4409                 __netif_tx_lock(txq, smp_processor_id());
4410                 if (netif_tx_queue_stopped(txq) &&
4411                     (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
4412                         netif_tx_wake_queue(txq);
4413                 __netif_tx_unlock(txq);
4414         }
4415 }
4416
4417 static void tg3_rx_skb_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
4418 {
4419         if (!ri->skb)
4420                 return;
4421
4422         pci_unmap_single(tp->pdev, pci_unmap_addr(ri, mapping),
4423                          map_sz, PCI_DMA_FROMDEVICE);
4424         dev_kfree_skb_any(ri->skb);
4425         ri->skb = NULL;
4426 }
4427
4428 /* Returns size of skb allocated or < 0 on error.
4429  *
4430  * We only need to fill in the address because the other members
4431  * of the RX descriptor are invariant, see tg3_init_rings.
4432  *
4433  * Note the purposeful assymetry of cpu vs. chip accesses.  For
4434  * posting buffers we only dirty the first cache line of the RX
4435  * descriptor (containing the address).  Whereas for the RX status
4436  * buffers the cpu only reads the last cacheline of the RX descriptor
4437  * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4438  */
4439 static int tg3_alloc_rx_skb(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
4440                             u32 opaque_key, u32 dest_idx_unmasked)
4441 {
4442         struct tg3_rx_buffer_desc *desc;
4443         struct ring_info *map, *src_map;
4444         struct sk_buff *skb;
4445         dma_addr_t mapping;
4446         int skb_size, dest_idx;
4447
4448         src_map = NULL;
4449         switch (opaque_key) {
4450         case RXD_OPAQUE_RING_STD:
4451                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4452                 desc = &tpr->rx_std[dest_idx];
4453                 map = &tpr->rx_std_buffers[dest_idx];
4454                 skb_size = tp->rx_pkt_map_sz;
4455                 break;
4456
4457         case RXD_OPAQUE_RING_JUMBO:
4458                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4459                 desc = &tpr->rx_jmb[dest_idx].std;
4460                 map = &tpr->rx_jmb_buffers[dest_idx];
4461                 skb_size = TG3_RX_JMB_MAP_SZ;
4462                 break;
4463
4464         default:
4465                 return -EINVAL;
4466         }
4467
4468         /* Do not overwrite any of the map or rp information
4469          * until we are sure we can commit to a new buffer.
4470          *
4471          * Callers depend upon this behavior and assume that
4472          * we leave everything unchanged if we fail.
4473          */
4474         skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset);
4475         if (skb == NULL)
4476                 return -ENOMEM;
4477
4478         skb_reserve(skb, tp->rx_offset);
4479
4480         mapping = pci_map_single(tp->pdev, skb->data, skb_size,
4481                                  PCI_DMA_FROMDEVICE);
4482         if (pci_dma_mapping_error(tp->pdev, mapping)) {
4483                 dev_kfree_skb(skb);
4484                 return -EIO;
4485         }
4486
4487         map->skb = skb;
4488         pci_unmap_addr_set(map, mapping, mapping);
4489
4490         desc->addr_hi = ((u64)mapping >> 32);
4491         desc->addr_lo = ((u64)mapping & 0xffffffff);
4492
4493         return skb_size;
4494 }
4495
4496 /* We only need to move over in the address because the other
4497  * members of the RX descriptor are invariant.  See notes above
4498  * tg3_alloc_rx_skb for full details.
4499  */
4500 static void tg3_recycle_rx(struct tg3_napi *tnapi,
4501                            struct tg3_rx_prodring_set *dpr,
4502                            u32 opaque_key, int src_idx,
4503                            u32 dest_idx_unmasked)
4504 {
4505         struct tg3 *tp = tnapi->tp;
4506         struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4507         struct ring_info *src_map, *dest_map;
4508         int dest_idx;
4509         struct tg3_rx_prodring_set *spr = &tp->prodring[0];
4510
4511         switch (opaque_key) {
4512         case RXD_OPAQUE_RING_STD:
4513                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4514                 dest_desc = &dpr->rx_std[dest_idx];
4515                 dest_map = &dpr->rx_std_buffers[dest_idx];
4516                 src_desc = &spr->rx_std[src_idx];
4517                 src_map = &spr->rx_std_buffers[src_idx];
4518                 break;
4519
4520         case RXD_OPAQUE_RING_JUMBO:
4521                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4522                 dest_desc = &dpr->rx_jmb[dest_idx].std;
4523                 dest_map = &dpr->rx_jmb_buffers[dest_idx];
4524                 src_desc = &spr->rx_jmb[src_idx].std;
4525                 src_map = &spr->rx_jmb_buffers[src_idx];
4526                 break;
4527
4528         default:
4529                 return;
4530         }
4531
4532         dest_map->skb = src_map->skb;
4533         pci_unmap_addr_set(dest_map, mapping,
4534                            pci_unmap_addr(src_map, mapping));
4535         dest_desc->addr_hi = src_desc->addr_hi;
4536         dest_desc->addr_lo = src_desc->addr_lo;
4537         src_map->skb = NULL;
4538 }
4539
4540 /* The RX ring scheme is composed of multiple rings which post fresh
4541  * buffers to the chip, and one special ring the chip uses to report
4542  * status back to the host.
4543  *
4544  * The special ring reports the status of received packets to the
4545  * host.  The chip does not write into the original descriptor the
4546  * RX buffer was obtained from.  The chip simply takes the original
4547  * descriptor as provided by the host, updates the status and length
4548  * field, then writes this into the next status ring entry.
4549  *
4550  * Each ring the host uses to post buffers to the chip is described
4551  * by a TG3_BDINFO entry in the chips SRAM area.  When a packet arrives,
4552  * it is first placed into the on-chip ram.  When the packet's length
4553  * is known, it walks down the TG3_BDINFO entries to select the ring.
4554  * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4555  * which is within the range of the new packet's length is chosen.
4556  *
4557  * The "separate ring for rx status" scheme may sound queer, but it makes
4558  * sense from a cache coherency perspective.  If only the host writes
4559  * to the buffer post rings, and only the chip writes to the rx status
4560  * rings, then cache lines never move beyond shared-modified state.
4561  * If both the host and chip were to write into the same ring, cache line
4562  * eviction could occur since both entities want it in an exclusive state.
4563  */
4564 static int tg3_rx(struct tg3_napi *tnapi, int budget)
4565 {
4566         struct tg3 *tp = tnapi->tp;
4567         u32 work_mask, rx_std_posted = 0;
4568         u32 std_prod_idx, jmb_prod_idx;
4569         u32 sw_idx = tnapi->rx_rcb_ptr;
4570         u16 hw_idx;
4571         int received;
4572         struct tg3_rx_prodring_set *tpr = tnapi->prodring;
4573
4574         hw_idx = *(tnapi->rx_rcb_prod_idx);
4575         /*
4576          * We need to order the read of hw_idx and the read of
4577          * the opaque cookie.
4578          */
4579         rmb();
4580         work_mask = 0;
4581         received = 0;
4582         std_prod_idx = tpr->rx_std_prod_idx;
4583         jmb_prod_idx = tpr->rx_jmb_prod_idx;
4584         while (sw_idx != hw_idx && budget > 0) {
4585                 struct ring_info *ri;
4586                 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
4587                 unsigned int len;
4588                 struct sk_buff *skb;
4589                 dma_addr_t dma_addr;
4590                 u32 opaque_key, desc_idx, *post_ptr;
4591
4592                 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4593                 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4594                 if (opaque_key == RXD_OPAQUE_RING_STD) {
4595                         ri = &tp->prodring[0].rx_std_buffers[desc_idx];
4596                         dma_addr = pci_unmap_addr(ri, mapping);
4597                         skb = ri->skb;
4598                         post_ptr = &std_prod_idx;
4599                         rx_std_posted++;
4600                 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
4601                         ri = &tp->prodring[0].rx_jmb_buffers[desc_idx];
4602                         dma_addr = pci_unmap_addr(ri, mapping);
4603                         skb = ri->skb;
4604                         post_ptr = &jmb_prod_idx;
4605                 } else
4606                         goto next_pkt_nopost;
4607
4608                 work_mask |= opaque_key;
4609
4610                 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4611                     (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4612                 drop_it:
4613                         tg3_recycle_rx(tnapi, tpr, opaque_key,
4614                                        desc_idx, *post_ptr);
4615                 drop_it_no_recycle:
4616                         /* Other statistics kept track of by card. */
4617                         tp->net_stats.rx_dropped++;
4618                         goto next_pkt;
4619                 }
4620
4621                 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4622                       ETH_FCS_LEN;
4623
4624                 if (len > RX_COPY_THRESHOLD &&
4625                     tp->rx_offset == NET_IP_ALIGN) {
4626                     /* rx_offset will likely not equal NET_IP_ALIGN
4627                      * if this is a 5701 card running in PCI-X mode
4628                      * [see tg3_get_invariants()]
4629                      */
4630                         int skb_size;
4631
4632                         skb_size = tg3_alloc_rx_skb(tp, tpr, opaque_key,
4633                                                     *post_ptr);
4634                         if (skb_size < 0)
4635                                 goto drop_it;
4636
4637                         ri->skb = NULL;
4638
4639                         pci_unmap_single(tp->pdev, dma_addr, skb_size,
4640                                          PCI_DMA_FROMDEVICE);
4641
4642                         skb_put(skb, len);
4643                 } else {
4644                         struct sk_buff *copy_skb;
4645
4646                         tg3_recycle_rx(tnapi, tpr, opaque_key,
4647                                        desc_idx, *post_ptr);
4648
4649                         copy_skb = netdev_alloc_skb(tp->dev,
4650                                                     len + TG3_RAW_IP_ALIGN);
4651                         if (copy_skb == NULL)
4652                                 goto drop_it_no_recycle;
4653
4654                         skb_reserve(copy_skb, TG3_RAW_IP_ALIGN);
4655                         skb_put(copy_skb, len);
4656                         pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4657                         skb_copy_from_linear_data(skb, copy_skb->data, len);
4658                         pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4659
4660                         /* We'll reuse the original ring buffer. */
4661                         skb = copy_skb;
4662                 }
4663
4664                 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4665                     (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4666                     (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4667                       >> RXD_TCPCSUM_SHIFT) == 0xffff))
4668                         skb->ip_summed = CHECKSUM_UNNECESSARY;
4669                 else
4670                         skb->ip_summed = CHECKSUM_NONE;
4671
4672                 skb->protocol = eth_type_trans(skb, tp->dev);
4673
4674                 if (len > (tp->dev->mtu + ETH_HLEN) &&
4675                     skb->protocol != htons(ETH_P_8021Q)) {
4676                         dev_kfree_skb(skb);
4677                         goto next_pkt;
4678                 }
4679
4680 #if TG3_VLAN_TAG_USED
4681                 if (tp->vlgrp != NULL &&
4682                     desc->type_flags & RXD_FLAG_VLAN) {
4683                         vlan_gro_receive(&tnapi->napi, tp->vlgrp,
4684                                          desc->err_vlan & RXD_VLAN_MASK, skb);
4685                 } else
4686 #endif
4687                         napi_gro_receive(&tnapi->napi, skb);
4688
4689                 received++;
4690                 budget--;
4691
4692 next_pkt:
4693                 (*post_ptr)++;
4694
4695                 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4696                         u32 idx = *post_ptr % TG3_RX_RING_SIZE;
4697                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, idx);
4698                         work_mask &= ~RXD_OPAQUE_RING_STD;
4699                         rx_std_posted = 0;
4700                 }
4701 next_pkt_nopost:
4702                 sw_idx++;
4703                 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
4704
4705                 /* Refresh hw_idx to see if there is new work */
4706                 if (sw_idx == hw_idx) {
4707                         hw_idx = *(tnapi->rx_rcb_prod_idx);
4708                         rmb();
4709                 }
4710         }
4711
4712         /* ACK the status ring. */
4713         tnapi->rx_rcb_ptr = sw_idx;
4714         tw32_rx_mbox(tnapi->consmbox, sw_idx);
4715
4716         /* Refill RX ring(s). */
4717         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) || tnapi == &tp->napi[1]) {
4718                 if (work_mask & RXD_OPAQUE_RING_STD) {
4719                         tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4720                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4721                                      tpr->rx_std_prod_idx);
4722                 }
4723                 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4724                         tpr->rx_jmb_prod_idx = jmb_prod_idx %
4725                                                TG3_RX_JUMBO_RING_SIZE;
4726                         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
4727                                      tpr->rx_jmb_prod_idx);
4728                 }
4729                 mmiowb();
4730         } else if (work_mask) {
4731                 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
4732                  * updated before the producer indices can be updated.
4733                  */
4734                 smp_wmb();
4735
4736                 tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4737                 tpr->rx_jmb_prod_idx = jmb_prod_idx % TG3_RX_JUMBO_RING_SIZE;
4738
4739                 napi_schedule(&tp->napi[1].napi);
4740         }
4741
4742         return received;
4743 }
4744
4745 static void tg3_poll_link(struct tg3 *tp)
4746 {
4747         /* handle link change and other phy events */
4748         if (!(tp->tg3_flags &
4749               (TG3_FLAG_USE_LINKCHG_REG |
4750                TG3_FLAG_POLL_SERDES))) {
4751                 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
4752
4753                 if (sblk->status & SD_STATUS_LINK_CHG) {
4754                         sblk->status = SD_STATUS_UPDATED |
4755                                        (sblk->status & ~SD_STATUS_LINK_CHG);
4756                         spin_lock(&tp->lock);
4757                         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4758                                 tw32_f(MAC_STATUS,
4759                                      (MAC_STATUS_SYNC_CHANGED |
4760                                       MAC_STATUS_CFG_CHANGED |
4761                                       MAC_STATUS_MI_COMPLETION |
4762                                       MAC_STATUS_LNKSTATE_CHANGED));
4763                                 udelay(40);
4764                         } else
4765                                 tg3_setup_phy(tp, 0);
4766                         spin_unlock(&tp->lock);
4767                 }
4768         }
4769 }
4770
4771 static void tg3_rx_prodring_xfer(struct tg3 *tp,
4772                                  struct tg3_rx_prodring_set *dpr,
4773                                  struct tg3_rx_prodring_set *spr)
4774 {
4775         u32 si, di, cpycnt, src_prod_idx;
4776         int i;
4777
4778         while (1) {
4779                 src_prod_idx = spr->rx_std_prod_idx;
4780
4781                 /* Make sure updates to the rx_std_buffers[] entries and the
4782                  * standard producer index are seen in the correct order.
4783                  */
4784                 smp_rmb();
4785
4786                 if (spr->rx_std_cons_idx == src_prod_idx)
4787                         break;
4788
4789                 if (spr->rx_std_cons_idx < src_prod_idx)
4790                         cpycnt = src_prod_idx - spr->rx_std_cons_idx;
4791                 else
4792                         cpycnt = TG3_RX_RING_SIZE - spr->rx_std_cons_idx;
4793
4794                 cpycnt = min(cpycnt, TG3_RX_RING_SIZE - dpr->rx_std_prod_idx);
4795
4796                 si = spr->rx_std_cons_idx;
4797                 di = dpr->rx_std_prod_idx;
4798
4799                 memcpy(&dpr->rx_std_buffers[di],
4800                        &spr->rx_std_buffers[si],
4801                        cpycnt * sizeof(struct ring_info));
4802
4803                 for (i = 0; i < cpycnt; i++, di++, si++) {
4804                         struct tg3_rx_buffer_desc *sbd, *dbd;
4805                         sbd = &spr->rx_std[si];
4806                         dbd = &dpr->rx_std[di];
4807                         dbd->addr_hi = sbd->addr_hi;
4808                         dbd->addr_lo = sbd->addr_lo;
4809                 }
4810
4811                 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) %
4812                                        TG3_RX_RING_SIZE;
4813                 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) %
4814                                        TG3_RX_RING_SIZE;
4815         }
4816
4817         while (1) {
4818                 src_prod_idx = spr->rx_jmb_prod_idx;
4819
4820                 /* Make sure updates to the rx_jmb_buffers[] entries and
4821                  * the jumbo producer index are seen in the correct order.
4822                  */
4823                 smp_rmb();
4824
4825                 if (spr->rx_jmb_cons_idx == src_prod_idx)
4826                         break;
4827
4828                 if (spr->rx_jmb_cons_idx < src_prod_idx)
4829                         cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
4830                 else
4831                         cpycnt = TG3_RX_JUMBO_RING_SIZE - spr->rx_jmb_cons_idx;
4832
4833                 cpycnt = min(cpycnt,
4834                              TG3_RX_JUMBO_RING_SIZE - dpr->rx_jmb_prod_idx);
4835
4836                 si = spr->rx_jmb_cons_idx;
4837                 di = dpr->rx_jmb_prod_idx;
4838
4839                 memcpy(&dpr->rx_jmb_buffers[di],
4840                        &spr->rx_jmb_buffers[si],
4841                        cpycnt * sizeof(struct ring_info));
4842
4843                 for (i = 0; i < cpycnt; i++, di++, si++) {
4844                         struct tg3_rx_buffer_desc *sbd, *dbd;
4845                         sbd = &spr->rx_jmb[si].std;
4846                         dbd = &dpr->rx_jmb[di].std;
4847                         dbd->addr_hi = sbd->addr_hi;
4848                         dbd->addr_lo = sbd->addr_lo;
4849                 }
4850
4851                 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) %
4852                                        TG3_RX_JUMBO_RING_SIZE;
4853                 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) %
4854                                        TG3_RX_JUMBO_RING_SIZE;
4855         }
4856 }
4857
4858 static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
4859 {
4860         struct tg3 *tp = tnapi->tp;
4861
4862         /* run TX completion thread */
4863         if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
4864                 tg3_tx(tnapi);
4865                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4866                         return work_done;
4867         }
4868
4869         /* run RX thread, within the bounds set by NAPI.
4870          * All RX "locking" is done by ensuring outside
4871          * code synchronizes with tg3->napi.poll()
4872          */
4873         if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
4874                 work_done += tg3_rx(tnapi, budget - work_done);
4875
4876         if ((tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) && tnapi == &tp->napi[1]) {
4877                 int i;
4878                 u32 std_prod_idx = tp->prodring[0].rx_std_prod_idx;
4879                 u32 jmb_prod_idx = tp->prodring[0].rx_jmb_prod_idx;
4880
4881                 for (i = 2; i < tp->irq_cnt; i++)
4882                         tg3_rx_prodring_xfer(tp, tnapi->prodring,
4883                                              tp->napi[i].prodring);
4884
4885                 wmb();
4886
4887                 if (std_prod_idx != tp->prodring[0].rx_std_prod_idx) {
4888                         u32 mbox = TG3_RX_STD_PROD_IDX_REG;
4889                         tw32_rx_mbox(mbox, tp->prodring[0].rx_std_prod_idx);
4890                 }
4891
4892                 if (jmb_prod_idx != tp->prodring[0].rx_jmb_prod_idx) {
4893                         u32 mbox = TG3_RX_JMB_PROD_IDX_REG;
4894                         tw32_rx_mbox(mbox, tp->prodring[0].rx_jmb_prod_idx);
4895                 }
4896
4897                 mmiowb();
4898         }
4899
4900         return work_done;
4901 }
4902
4903 static int tg3_poll_msix(struct napi_struct *napi, int budget)
4904 {
4905         struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
4906         struct tg3 *tp = tnapi->tp;
4907         int work_done = 0;
4908         struct tg3_hw_status *sblk = tnapi->hw_status;
4909
4910         while (1) {
4911                 work_done = tg3_poll_work(tnapi, work_done, budget);
4912
4913                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4914                         goto tx_recovery;
4915
4916                 if (unlikely(work_done >= budget))
4917                         break;
4918
4919                 /* tp->last_tag is used in tg3_restart_ints() below
4920                  * to tell the hw how much work has been processed,
4921                  * so we must read it before checking for more work.
4922                  */
4923                 tnapi->last_tag = sblk->status_tag;
4924                 tnapi->last_irq_tag = tnapi->last_tag;
4925                 rmb();
4926
4927                 /* check for RX/TX work to do */
4928                 if (sblk->idx[0].tx_consumer == tnapi->tx_cons &&
4929                     *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr) {
4930                         napi_complete(napi);
4931                         /* Reenable interrupts. */
4932                         tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
4933                         mmiowb();
4934                         break;
4935                 }
4936         }
4937
4938         return work_done;
4939
4940 tx_recovery:
4941         /* work_done is guaranteed to be less than budget. */
4942         napi_complete(napi);
4943         schedule_work(&tp->reset_task);
4944         return work_done;
4945 }
4946
4947 static int tg3_poll(struct napi_struct *napi, int budget)
4948 {
4949         struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
4950         struct tg3 *tp = tnapi->tp;
4951         int work_done = 0;
4952         struct tg3_hw_status *sblk = tnapi->hw_status;
4953
4954         while (1) {
4955                 tg3_poll_link(tp);
4956
4957                 work_done = tg3_poll_work(tnapi, work_done, budget);
4958
4959                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4960                         goto tx_recovery;
4961
4962                 if (unlikely(work_done >= budget))
4963                         break;
4964
4965                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
4966                         /* tp->last_tag is used in tg3_int_reenable() below
4967                          * to tell the hw how much work has been processed,
4968                          * so we must read it before checking for more work.
4969                          */
4970                         tnapi->last_tag = sblk->status_tag;
4971                         tnapi->last_irq_tag = tnapi->last_tag;
4972                         rmb();
4973                 } else
4974                         sblk->status &= ~SD_STATUS_UPDATED;
4975
4976                 if (likely(!tg3_has_work(tnapi))) {
4977                         napi_complete(napi);
4978                         tg3_int_reenable(tnapi);
4979                         break;
4980                 }
4981         }
4982
4983         return work_done;
4984
4985 tx_recovery:
4986         /* work_done is guaranteed to be less than budget. */
4987         napi_complete(napi);
4988         schedule_work(&tp->reset_task);
4989         return work_done;
4990 }
4991
4992 static void tg3_irq_quiesce(struct tg3 *tp)
4993 {
4994         int i;
4995
4996         BUG_ON(tp->irq_sync);
4997
4998         tp->irq_sync = 1;
4999         smp_mb();
5000
5001         for (i = 0; i < tp->irq_cnt; i++)
5002                 synchronize_irq(tp->napi[i].irq_vec);
5003 }
5004
5005 static inline int tg3_irq_sync(struct tg3 *tp)
5006 {
5007         return tp->irq_sync;
5008 }
5009
5010 /* Fully shutdown all tg3 driver activity elsewhere in the system.
5011  * If irq_sync is non-zero, then the IRQ handler must be synchronized
5012  * with as well.  Most of the time, this is not necessary except when
5013  * shutting down the device.
5014  */
5015 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
5016 {
5017         spin_lock_bh(&tp->lock);
5018         if (irq_sync)
5019                 tg3_irq_quiesce(tp);
5020 }
5021
5022 static inline void tg3_full_unlock(struct tg3 *tp)
5023 {
5024         spin_unlock_bh(&tp->lock);
5025 }
5026
5027 /* One-shot MSI handler - Chip automatically disables interrupt
5028  * after sending MSI so driver doesn't have to do it.
5029  */
5030 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
5031 {
5032         struct tg3_napi *tnapi = dev_id;
5033         struct tg3 *tp = tnapi->tp;
5034
5035         prefetch(tnapi->hw_status);
5036         if (tnapi->rx_rcb)
5037                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5038
5039         if (likely(!tg3_irq_sync(tp)))
5040                 napi_schedule(&tnapi->napi);
5041
5042         return IRQ_HANDLED;
5043 }
5044
5045 /* MSI ISR - No need to check for interrupt sharing and no need to
5046  * flush status block and interrupt mailbox. PCI ordering rules
5047  * guarantee that MSI will arrive after the status block.
5048  */
5049 static irqreturn_t tg3_msi(int irq, void *dev_id)
5050 {
5051         struct tg3_napi *tnapi = dev_id;
5052         struct tg3 *tp = tnapi->tp;
5053
5054         prefetch(tnapi->hw_status);
5055         if (tnapi->rx_rcb)
5056                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5057         /*
5058          * Writing any value to intr-mbox-0 clears PCI INTA# and
5059          * chip-internal interrupt pending events.
5060          * Writing non-zero to intr-mbox-0 additional tells the
5061          * NIC to stop sending us irqs, engaging "in-intr-handler"
5062          * event coalescing.
5063          */
5064         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5065         if (likely(!tg3_irq_sync(tp)))
5066                 napi_schedule(&tnapi->napi);
5067
5068         return IRQ_RETVAL(1);
5069 }
5070
5071 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
5072 {
5073         struct tg3_napi *tnapi = dev_id;
5074         struct tg3 *tp = tnapi->tp;
5075         struct tg3_hw_status *sblk = tnapi->hw_status;
5076         unsigned int handled = 1;
5077
5078         /* In INTx mode, it is possible for the interrupt to arrive at
5079          * the CPU before the status block posted prior to the interrupt.
5080          * Reading the PCI State register will confirm whether the
5081          * interrupt is ours and will flush the status block.
5082          */
5083         if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
5084                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5085                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5086                         handled = 0;
5087                         goto out;
5088                 }
5089         }
5090
5091         /*
5092          * Writing any value to intr-mbox-0 clears PCI INTA# and
5093          * chip-internal interrupt pending events.
5094          * Writing non-zero to intr-mbox-0 additional tells the
5095          * NIC to stop sending us irqs, engaging "in-intr-handler"
5096          * event coalescing.
5097          *
5098          * Flush the mailbox to de-assert the IRQ immediately to prevent
5099          * spurious interrupts.  The flush impacts performance but
5100          * excessive spurious interrupts can be worse in some cases.
5101          */
5102         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5103         if (tg3_irq_sync(tp))
5104                 goto out;
5105         sblk->status &= ~SD_STATUS_UPDATED;
5106         if (likely(tg3_has_work(tnapi))) {
5107                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5108                 napi_schedule(&tnapi->napi);
5109         } else {
5110                 /* No work, shared interrupt perhaps?  re-enable
5111                  * interrupts, and flush that PCI write
5112                  */
5113                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
5114                                0x00000000);
5115         }
5116 out:
5117         return IRQ_RETVAL(handled);
5118 }
5119
5120 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
5121 {
5122         struct tg3_napi *tnapi = dev_id;
5123         struct tg3 *tp = tnapi->tp;
5124         struct tg3_hw_status *sblk = tnapi->hw_status;
5125         unsigned int handled = 1;
5126
5127         /* In INTx mode, it is possible for the interrupt to arrive at
5128          * the CPU before the status block posted prior to the interrupt.
5129          * Reading the PCI State register will confirm whether the
5130          * interrupt is ours and will flush the status block.
5131          */
5132         if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
5133                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5134                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5135                         handled = 0;
5136                         goto out;
5137                 }
5138         }
5139
5140         /*
5141          * writing any value to intr-mbox-0 clears PCI INTA# and
5142          * chip-internal interrupt pending events.
5143          * writing non-zero to intr-mbox-0 additional tells the
5144          * NIC to stop sending us irqs, engaging "in-intr-handler"
5145          * event coalescing.
5146          *
5147          * Flush the mailbox to de-assert the IRQ immediately to prevent
5148          * spurious interrupts.  The flush impacts performance but
5149          * excessive spurious interrupts can be worse in some cases.
5150          */
5151         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5152
5153         /*
5154          * In a shared interrupt configuration, sometimes other devices'
5155          * interrupts will scream.  We record the current status tag here
5156          * so that the above check can report that the screaming interrupts
5157          * are unhandled.  Eventually they will be silenced.
5158          */
5159         tnapi->last_irq_tag = sblk->status_tag;
5160
5161         if (tg3_irq_sync(tp))
5162                 goto out;
5163
5164         prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5165
5166         napi_schedule(&tnapi->napi);
5167
5168 out:
5169         return IRQ_RETVAL(handled);
5170 }
5171
5172 /* ISR for interrupt test */
5173 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
5174 {
5175         struct tg3_napi *tnapi = dev_id;
5176         struct tg3 *tp = tnapi->tp;
5177         struct tg3_hw_status *sblk = tnapi->hw_status;
5178
5179         if ((sblk->status & SD_STATUS_UPDATED) ||
5180             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5181                 tg3_disable_ints(tp);
5182                 return IRQ_RETVAL(1);
5183         }
5184         return IRQ_RETVAL(0);
5185 }
5186
5187 static int tg3_init_hw(struct tg3 *, int);
5188 static int tg3_halt(struct tg3 *, int, int);
5189
5190 /* Restart hardware after configuration changes, self-test, etc.
5191  * Invoked with tp->lock held.
5192  */
5193 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
5194         __releases(tp->lock)
5195         __acquires(tp->lock)
5196 {
5197         int err;
5198
5199         err = tg3_init_hw(tp, reset_phy);
5200         if (err) {
5201                 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
5202                        "aborting.\n", tp->dev->name);
5203                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5204                 tg3_full_unlock(tp);
5205                 del_timer_sync(&tp->timer);
5206                 tp->irq_sync = 0;
5207                 tg3_napi_enable(tp);
5208                 dev_close(tp->dev);
5209                 tg3_full_lock(tp, 0);
5210         }
5211         return err;
5212 }
5213
5214 #ifdef CONFIG_NET_POLL_CONTROLLER
5215 static void tg3_poll_controller(struct net_device *dev)
5216 {
5217         int i;
5218         struct tg3 *tp = netdev_priv(dev);
5219
5220         for (i = 0; i < tp->irq_cnt; i++)
5221                 tg3_interrupt(tp->napi[i].irq_vec, dev);
5222 }
5223 #endif
5224
5225 static void tg3_reset_task(struct work_struct *work)
5226 {
5227         struct tg3 *tp = container_of(work, struct tg3, reset_task);
5228         int err;
5229         unsigned int restart_timer;
5230
5231         tg3_full_lock(tp, 0);
5232
5233         if (!netif_running(tp->dev)) {
5234                 tg3_full_unlock(tp);
5235                 return;
5236         }
5237
5238         tg3_full_unlock(tp);
5239
5240         tg3_phy_stop(tp);
5241
5242         tg3_netif_stop(tp);
5243
5244         tg3_full_lock(tp, 1);
5245
5246         restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
5247         tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
5248
5249         if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
5250                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
5251                 tp->write32_rx_mbox = tg3_write_flush_reg32;
5252                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
5253                 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
5254         }
5255
5256         tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
5257         err = tg3_init_hw(tp, 1);
5258         if (err)
5259                 goto out;
5260
5261         tg3_netif_start(tp);
5262
5263         if (restart_timer)
5264                 mod_timer(&tp->timer, jiffies + 1);
5265
5266 out:
5267         tg3_full_unlock(tp);
5268
5269         if (!err)
5270                 tg3_phy_start(tp);
5271 }
5272
5273 static void tg3_dump_short_state(struct tg3 *tp)
5274 {
5275         printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
5276                tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
5277         printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
5278                tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
5279 }
5280
5281 static void tg3_tx_timeout(struct net_device *dev)
5282 {
5283         struct tg3 *tp = netdev_priv(dev);
5284
5285         if (netif_msg_tx_err(tp)) {
5286                 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
5287                        dev->name);
5288                 tg3_dump_short_state(tp);
5289         }
5290
5291         schedule_work(&tp->reset_task);
5292 }
5293
5294 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5295 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
5296 {
5297         u32 base = (u32) mapping & 0xffffffff;
5298
5299         return ((base > 0xffffdcc0) &&
5300                 (base + len + 8 < base));
5301 }
5302
5303 /* Test for DMA addresses > 40-bit */
5304 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
5305                                           int len)
5306 {
5307 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
5308         if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
5309                 return (((u64) mapping + len) > DMA_BIT_MASK(40));
5310         return 0;
5311 #else
5312         return 0;
5313 #endif
5314 }
5315
5316 static void tg3_set_txd(struct tg3_napi *, int, dma_addr_t, int, u32, u32);
5317
5318 /* Workaround 4GB and 40-bit hardware DMA bugs. */
5319 static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
5320                                        struct sk_buff *skb, u32 last_plus_one,
5321                                        u32 *start, u32 base_flags, u32 mss)
5322 {
5323         struct tg3 *tp = tnapi->tp;
5324         struct sk_buff *new_skb;
5325         dma_addr_t new_addr = 0;
5326         u32 entry = *start;
5327         int i, ret = 0;
5328
5329         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5330                 new_skb = skb_copy(skb, GFP_ATOMIC);
5331         else {
5332                 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5333
5334                 new_skb = skb_copy_expand(skb,
5335                                           skb_headroom(skb) + more_headroom,
5336                                           skb_tailroom(skb), GFP_ATOMIC);
5337         }
5338
5339         if (!new_skb) {
5340                 ret = -1;
5341         } else {
5342                 /* New SKB is guaranteed to be linear. */
5343                 entry = *start;
5344                 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
5345                                           PCI_DMA_TODEVICE);
5346                 /* Make sure the mapping succeeded */
5347                 if (pci_dma_mapping_error(tp->pdev, new_addr)) {
5348                         ret = -1;
5349                         dev_kfree_skb(new_skb);
5350                         new_skb = NULL;
5351
5352                 /* Make sure new skb does not cross any 4G boundaries.
5353                  * Drop the packet if it does.
5354                  */
5355                 } else if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5356                             tg3_4g_overflow_test(new_addr, new_skb->len)) {
5357                         pci_unmap_single(tp->pdev, new_addr, new_skb->len,
5358                                          PCI_DMA_TODEVICE);
5359                         ret = -1;
5360                         dev_kfree_skb(new_skb);
5361                         new_skb = NULL;
5362                 } else {
5363                         tg3_set_txd(tnapi, entry, new_addr, new_skb->len,
5364                                     base_flags, 1 | (mss << 1));
5365                         *start = NEXT_TX(entry);
5366                 }
5367         }
5368
5369         /* Now clean up the sw ring entries. */
5370         i = 0;
5371         while (entry != last_plus_one) {
5372                 int len;
5373
5374                 if (i == 0)
5375                         len = skb_headlen(skb);
5376                 else
5377                         len = skb_shinfo(skb)->frags[i-1].size;
5378
5379                 pci_unmap_single(tp->pdev,
5380                                  pci_unmap_addr(&tnapi->tx_buffers[entry],
5381                                                 mapping),
5382                                  len, PCI_DMA_TODEVICE);
5383                 if (i == 0) {
5384                         tnapi->tx_buffers[entry].skb = new_skb;
5385                         pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5386                                            new_addr);
5387                 } else {
5388                         tnapi->tx_buffers[entry].skb = NULL;
5389                 }
5390                 entry = NEXT_TX(entry);
5391                 i++;
5392         }
5393
5394         dev_kfree_skb(skb);
5395
5396         return ret;
5397 }
5398
5399 static void tg3_set_txd(struct tg3_napi *tnapi, int entry,
5400                         dma_addr_t mapping, int len, u32 flags,
5401                         u32 mss_and_is_end)
5402 {
5403         struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry];
5404         int is_end = (mss_and_is_end & 0x1);
5405         u32 mss = (mss_and_is_end >> 1);
5406         u32 vlan_tag = 0;
5407
5408         if (is_end)
5409                 flags |= TXD_FLAG_END;
5410         if (flags & TXD_FLAG_VLAN) {
5411                 vlan_tag = flags >> 16;
5412                 flags &= 0xffff;
5413         }
5414         vlan_tag |= (mss << TXD_MSS_SHIFT);
5415
5416         txd->addr_hi = ((u64) mapping >> 32);
5417         txd->addr_lo = ((u64) mapping & 0xffffffff);
5418         txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5419         txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5420 }
5421
5422 /* hard_start_xmit for devices that don't have any bugs and
5423  * support TG3_FLG2_HW_TSO_2 and TG3_FLG2_HW_TSO_3 only.
5424  */
5425 static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
5426                                   struct net_device *dev)
5427 {
5428         struct tg3 *tp = netdev_priv(dev);
5429         u32 len, entry, base_flags, mss;
5430         dma_addr_t mapping;
5431         struct tg3_napi *tnapi;
5432         struct netdev_queue *txq;
5433         unsigned int i, last;
5434
5435
5436         txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5437         tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5438         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
5439                 tnapi++;
5440
5441         /* We are running in BH disabled context with netif_tx_lock
5442          * and TX reclaim runs via tp->napi.poll inside of a software
5443          * interrupt.  Furthermore, IRQ processing runs lockless so we have
5444          * no IRQ context deadlocks to worry about either.  Rejoice!
5445          */
5446         if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5447                 if (!netif_tx_queue_stopped(txq)) {
5448                         netif_tx_stop_queue(txq);
5449
5450                         /* This is a hard error, log it. */
5451                         printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5452                                "queue awake!\n", dev->name);
5453                 }
5454                 return NETDEV_TX_BUSY;
5455         }
5456
5457         entry = tnapi->tx_prod;
5458         base_flags = 0;
5459         mss = 0;
5460         if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5461                 int tcp_opt_len, ip_tcp_len;
5462                 u32 hdrlen;
5463
5464                 if (skb_header_cloned(skb) &&
5465                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5466                         dev_kfree_skb(skb);
5467                         goto out_unlock;
5468                 }
5469
5470                 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
5471                         hdrlen = skb_headlen(skb) - ETH_HLEN;
5472                 else {
5473                         struct iphdr *iph = ip_hdr(skb);
5474
5475                         tcp_opt_len = tcp_optlen(skb);
5476                         ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5477
5478                         iph->check = 0;
5479                         iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
5480                         hdrlen = ip_tcp_len + tcp_opt_len;
5481                 }
5482
5483                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5484                         mss |= (hdrlen & 0xc) << 12;
5485                         if (hdrlen & 0x10)
5486                                 base_flags |= 0x00000010;
5487                         base_flags |= (hdrlen & 0x3e0) << 5;
5488                 } else
5489                         mss |= hdrlen << 9;
5490
5491                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5492                                TXD_FLAG_CPU_POST_DMA);
5493
5494                 tcp_hdr(skb)->check = 0;
5495
5496         }
5497         else if (skb->ip_summed == CHECKSUM_PARTIAL)
5498                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5499 #if TG3_VLAN_TAG_USED
5500         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5501                 base_flags |= (TXD_FLAG_VLAN |
5502                                (vlan_tx_tag_get(skb) << 16));
5503 #endif
5504
5505         len = skb_headlen(skb);
5506
5507         /* Queue skb data, a.k.a. the main skb fragment. */
5508         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5509         if (pci_dma_mapping_error(tp->pdev, mapping)) {
5510                 dev_kfree_skb(skb);
5511                 goto out_unlock;
5512         }
5513
5514         tnapi->tx_buffers[entry].skb = skb;
5515         pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
5516
5517         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
5518             !mss && skb->len > ETH_DATA_LEN)
5519                 base_flags |= TXD_FLAG_JMB_PKT;
5520
5521         tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5522                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5523
5524         entry = NEXT_TX(entry);
5525
5526         /* Now loop through additional data fragments, and queue them. */
5527         if (skb_shinfo(skb)->nr_frags > 0) {
5528                 last = skb_shinfo(skb)->nr_frags - 1;
5529                 for (i = 0; i <= last; i++) {
5530                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5531
5532                         len = frag->size;
5533                         mapping = pci_map_page(tp->pdev,
5534                                                frag->page,
5535                                                frag->page_offset,
5536                                                len, PCI_DMA_TODEVICE);
5537                         if (pci_dma_mapping_error(tp->pdev, mapping))
5538                                 goto dma_error;
5539
5540                         tnapi->tx_buffers[entry].skb = NULL;
5541                         pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5542                                            mapping);
5543
5544                         tg3_set_txd(tnapi, entry, mapping, len,
5545                                     base_flags, (i == last) | (mss << 1));
5546
5547                         entry = NEXT_TX(entry);
5548                 }
5549         }
5550
5551         /* Packets are ready, update Tx producer idx local and on card. */
5552         tw32_tx_mbox(tnapi->prodmbox, entry);
5553
5554         tnapi->tx_prod = entry;
5555         if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5556                 netif_tx_stop_queue(txq);
5557                 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5558                         netif_tx_wake_queue(txq);
5559         }
5560
5561 out_unlock:
5562         mmiowb();
5563
5564         return NETDEV_TX_OK;
5565
5566 dma_error:
5567         last = i;
5568         entry = tnapi->tx_prod;
5569         tnapi->tx_buffers[entry].skb = NULL;
5570         pci_unmap_single(tp->pdev,
5571                          pci_unmap_addr(&tnapi->tx_buffers[entry], mapping),
5572                          skb_headlen(skb),
5573                          PCI_DMA_TODEVICE);
5574         for (i = 0; i <= last; i++) {
5575                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5576                 entry = NEXT_TX(entry);
5577
5578                 pci_unmap_page(tp->pdev,
5579                                pci_unmap_addr(&tnapi->tx_buffers[entry],
5580                                               mapping),
5581                                frag->size, PCI_DMA_TODEVICE);
5582         }
5583
5584         dev_kfree_skb(skb);
5585         return NETDEV_TX_OK;
5586 }
5587
5588 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *,
5589                                           struct net_device *);
5590
5591 /* Use GSO to workaround a rare TSO bug that may be triggered when the
5592  * TSO header is greater than 80 bytes.
5593  */
5594 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5595 {
5596         struct sk_buff *segs, *nskb;
5597         u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
5598
5599         /* Estimate the number of fragments in the worst case */
5600         if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
5601                 netif_stop_queue(tp->dev);
5602                 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
5603                         return NETDEV_TX_BUSY;
5604
5605                 netif_wake_queue(tp->dev);
5606         }
5607
5608         segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
5609         if (IS_ERR(segs))
5610                 goto tg3_tso_bug_end;
5611
5612         do {
5613                 nskb = segs;
5614                 segs = segs->next;
5615                 nskb->next = NULL;
5616                 tg3_start_xmit_dma_bug(nskb, tp->dev);
5617         } while (segs);
5618
5619 tg3_tso_bug_end:
5620         dev_kfree_skb(skb);
5621
5622         return NETDEV_TX_OK;
5623 }
5624
5625 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5626  * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5627  */
5628 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
5629                                           struct net_device *dev)
5630 {
5631         struct tg3 *tp = netdev_priv(dev);
5632         u32 len, entry, base_flags, mss;
5633         int would_hit_hwbug;
5634         dma_addr_t mapping;
5635         struct tg3_napi *tnapi;
5636         struct netdev_queue *txq;
5637         unsigned int i, last;
5638
5639
5640         txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5641         tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5642         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
5643                 tnapi++;
5644
5645         /* We are running in BH disabled context with netif_tx_lock
5646          * and TX reclaim runs via tp->napi.poll inside of a software
5647          * interrupt.  Furthermore, IRQ processing runs lockless so we have
5648          * no IRQ context deadlocks to worry about either.  Rejoice!
5649          */
5650         if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5651                 if (!netif_tx_queue_stopped(txq)) {
5652                         netif_tx_stop_queue(txq);
5653
5654                         /* This is a hard error, log it. */
5655                         printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5656                                "queue awake!\n", dev->name);
5657                 }
5658                 return NETDEV_TX_BUSY;
5659         }
5660
5661         entry = tnapi->tx_prod;
5662         base_flags = 0;
5663         if (skb->ip_summed == CHECKSUM_PARTIAL)
5664                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5665
5666         if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5667                 struct iphdr *iph;
5668                 u32 tcp_opt_len, ip_tcp_len, hdr_len;
5669
5670                 if (skb_header_cloned(skb) &&
5671                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5672                         dev_kfree_skb(skb);
5673                         goto out_unlock;
5674                 }
5675
5676                 tcp_opt_len = tcp_optlen(skb);
5677                 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5678
5679                 hdr_len = ip_tcp_len + tcp_opt_len;
5680                 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
5681                              (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
5682                         return (tg3_tso_bug(tp, skb));
5683
5684                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5685                                TXD_FLAG_CPU_POST_DMA);
5686
5687                 iph = ip_hdr(skb);
5688                 iph->check = 0;
5689                 iph->tot_len = htons(mss + hdr_len);
5690                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
5691                         tcp_hdr(skb)->check = 0;
5692                         base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
5693                 } else
5694                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5695                                                                  iph->daddr, 0,
5696                                                                  IPPROTO_TCP,
5697                                                                  0);
5698
5699                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5700                         mss |= (hdr_len & 0xc) << 12;
5701                         if (hdr_len & 0x10)
5702                                 base_flags |= 0x00000010;
5703                         base_flags |= (hdr_len & 0x3e0) << 5;
5704                 } else if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)
5705                         mss |= hdr_len << 9;
5706                 else if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_1) ||
5707                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
5708                         if (tcp_opt_len || iph->ihl > 5) {
5709                                 int tsflags;
5710
5711                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5712                                 mss |= (tsflags << 11);
5713                         }
5714                 } else {
5715                         if (tcp_opt_len || iph->ihl > 5) {
5716                                 int tsflags;
5717
5718                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5719                                 base_flags |= tsflags << 12;
5720                         }
5721                 }
5722         }
5723 #if TG3_VLAN_TAG_USED
5724         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5725                 base_flags |= (TXD_FLAG_VLAN |
5726                                (vlan_tx_tag_get(skb) << 16));
5727 #endif
5728
5729         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
5730             !mss && skb->len > ETH_DATA_LEN)
5731                 base_flags |= TXD_FLAG_JMB_PKT;
5732
5733         len = skb_headlen(skb);
5734
5735         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5736         if (pci_dma_mapping_error(tp->pdev, mapping)) {
5737                 dev_kfree_skb(skb);
5738                 goto out_unlock;
5739         }
5740
5741         tnapi->tx_buffers[entry].skb = skb;
5742         pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
5743
5744         would_hit_hwbug = 0;
5745
5746         if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) && len <= 8)
5747                 would_hit_hwbug = 1;
5748
5749         if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5750             tg3_4g_overflow_test(mapping, len))
5751                 would_hit_hwbug = 1;
5752
5753         if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5754             tg3_40bit_overflow_test(tp, mapping, len))
5755                 would_hit_hwbug = 1;
5756
5757         if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
5758                 would_hit_hwbug = 1;
5759
5760         tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5761                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5762
5763         entry = NEXT_TX(entry);
5764
5765         /* Now loop through additional data fragments, and queue them. */
5766         if (skb_shinfo(skb)->nr_frags > 0) {
5767                 last = skb_shinfo(skb)->nr_frags - 1;
5768                 for (i = 0; i <= last; i++) {
5769                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5770
5771                         len = frag->size;
5772                         mapping = pci_map_page(tp->pdev,
5773                                                frag->page,
5774                                                frag->page_offset,
5775                                                len, PCI_DMA_TODEVICE);
5776
5777                         tnapi->tx_buffers[entry].skb = NULL;
5778                         pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5779                                            mapping);
5780                         if (pci_dma_mapping_error(tp->pdev, mapping))
5781                                 goto dma_error;
5782
5783                         if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) &&
5784                             len <= 8)
5785                                 would_hit_hwbug = 1;
5786
5787                         if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5788                             tg3_4g_overflow_test(mapping, len))
5789                                 would_hit_hwbug = 1;
5790
5791                         if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5792                             tg3_40bit_overflow_test(tp, mapping, len))
5793                                 would_hit_hwbug = 1;
5794
5795                         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5796                                 tg3_set_txd(tnapi, entry, mapping, len,
5797                                             base_flags, (i == last)|(mss << 1));
5798                         else
5799                                 tg3_set_txd(tnapi, entry, mapping, len,
5800                                             base_flags, (i == last));
5801
5802                         entry = NEXT_TX(entry);
5803                 }
5804         }
5805
5806         if (would_hit_hwbug) {
5807                 u32 last_plus_one = entry;
5808                 u32 start;
5809
5810                 start = entry - 1 - skb_shinfo(skb)->nr_frags;
5811                 start &= (TG3_TX_RING_SIZE - 1);
5812
5813                 /* If the workaround fails due to memory/mapping
5814                  * failure, silently drop this packet.
5815                  */
5816                 if (tigon3_dma_hwbug_workaround(tnapi, skb, last_plus_one,
5817                                                 &start, base_flags, mss))
5818                         goto out_unlock;
5819
5820                 entry = start;
5821         }
5822
5823         /* Packets are ready, update Tx producer idx local and on card. */
5824         tw32_tx_mbox(tnapi->prodmbox, entry);
5825
5826         tnapi->tx_prod = entry;
5827         if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5828                 netif_tx_stop_queue(txq);
5829                 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5830                         netif_tx_wake_queue(txq);
5831         }
5832
5833 out_unlock:
5834         mmiowb();
5835
5836         return NETDEV_TX_OK;
5837
5838 dma_error:
5839         last = i;
5840         entry = tnapi->tx_prod;
5841         tnapi->tx_buffers[entry].skb = NULL;
5842         pci_unmap_single(tp->pdev,
5843                          pci_unmap_addr(&tnapi->tx_buffers[entry], mapping),
5844                          skb_headlen(skb),
5845                          PCI_DMA_TODEVICE);
5846         for (i = 0; i <= last; i++) {
5847                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5848                 entry = NEXT_TX(entry);
5849
5850                 pci_unmap_page(tp->pdev,
5851                                pci_unmap_addr(&tnapi->tx_buffers[entry],
5852                                               mapping),
5853                                frag->size, PCI_DMA_TODEVICE);
5854         }
5855
5856         dev_kfree_skb(skb);
5857         return NETDEV_TX_OK;
5858 }
5859
5860 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
5861                                int new_mtu)
5862 {
5863         dev->mtu = new_mtu;
5864
5865         if (new_mtu > ETH_DATA_LEN) {
5866                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
5867                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
5868                         ethtool_op_set_tso(dev, 0);
5869                 }
5870                 else
5871                         tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
5872         } else {
5873                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
5874                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
5875                 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
5876         }
5877 }
5878
5879 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
5880 {
5881         struct tg3 *tp = netdev_priv(dev);
5882         int err;
5883
5884         if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
5885                 return -EINVAL;
5886
5887         if (!netif_running(dev)) {
5888                 /* We'll just catch it later when the
5889                  * device is up'd.
5890                  */
5891                 tg3_set_mtu(dev, tp, new_mtu);
5892                 return 0;
5893         }
5894
5895         tg3_phy_stop(tp);
5896
5897         tg3_netif_stop(tp);
5898
5899         tg3_full_lock(tp, 1);
5900
5901         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5902
5903         tg3_set_mtu(dev, tp, new_mtu);
5904
5905         err = tg3_restart_hw(tp, 0);
5906
5907         if (!err)
5908                 tg3_netif_start(tp);
5909
5910         tg3_full_unlock(tp);
5911
5912         if (!err)
5913                 tg3_phy_start(tp);
5914
5915         return err;
5916 }
5917
5918 static void tg3_rx_prodring_free(struct tg3 *tp,
5919                                  struct tg3_rx_prodring_set *tpr)
5920 {
5921         int i;
5922
5923         if (tpr != &tp->prodring[0]) {
5924                 for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx;
5925                      i = (i + 1) % TG3_RX_RING_SIZE)
5926                         tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
5927                                         tp->rx_pkt_map_sz);
5928
5929                 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
5930                         for (i = tpr->rx_jmb_cons_idx;
5931                              i != tpr->rx_jmb_prod_idx;
5932                              i = (i + 1) % TG3_RX_JUMBO_RING_SIZE) {
5933                                 tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
5934                                                 TG3_RX_JMB_MAP_SZ);
5935                         }
5936                 }
5937
5938                 return;
5939         }
5940
5941         for (i = 0; i < TG3_RX_RING_SIZE; i++)
5942                 tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
5943                                 tp->rx_pkt_map_sz);
5944
5945         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
5946                 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++)
5947                         tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
5948                                         TG3_RX_JMB_MAP_SZ);
5949         }
5950 }
5951
5952 /* Initialize tx/rx rings for packet processing.
5953  *
5954  * The chip has been shut down and the driver detached from
5955  * the networking, so no interrupts or new tx packets will
5956  * end up in the driver.  tp->{tx,}lock are held and thus
5957  * we may not sleep.
5958  */
5959 static int tg3_rx_prodring_alloc(struct tg3 *tp,
5960                                  struct tg3_rx_prodring_set *tpr)
5961 {
5962         u32 i, rx_pkt_dma_sz;
5963
5964         tpr->rx_std_cons_idx = 0;
5965         tpr->rx_std_prod_idx = 0;
5966         tpr->rx_jmb_cons_idx = 0;
5967         tpr->rx_jmb_prod_idx = 0;
5968
5969         if (tpr != &tp->prodring[0]) {
5970                 memset(&tpr->rx_std_buffers[0], 0, TG3_RX_STD_BUFF_RING_SIZE);
5971                 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE)
5972                         memset(&tpr->rx_jmb_buffers[0], 0,
5973                                TG3_RX_JMB_BUFF_RING_SIZE);
5974                 goto done;
5975         }
5976
5977         /* Zero out all descriptors. */
5978         memset(tpr->rx_std, 0, TG3_RX_RING_BYTES);
5979
5980         rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
5981         if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
5982             tp->dev->mtu > ETH_DATA_LEN)
5983                 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
5984         tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
5985
5986         /* Initialize invariants of the rings, we only set this
5987          * stuff once.  This works because the card does not
5988          * write into the rx buffer posting rings.
5989          */
5990         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5991                 struct tg3_rx_buffer_desc *rxd;
5992
5993                 rxd = &tpr->rx_std[i];
5994                 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
5995                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
5996                 rxd->opaque = (RXD_OPAQUE_RING_STD |
5997                                (i << RXD_OPAQUE_INDEX_SHIFT));
5998         }
5999
6000         /* Now allocate fresh SKBs for each rx ring. */
6001         for (i = 0; i < tp->rx_pending; i++) {
6002                 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_STD, i) < 0) {
6003                         printk(KERN_WARNING PFX
6004                                "%s: Using a smaller RX standard ring, "
6005                                "only %d out of %d buffers were allocated "
6006                                "successfully.\n",
6007                                tp->dev->name, i, tp->rx_pending);
6008                         if (i == 0)
6009                                 goto initfail;
6010                         tp->rx_pending = i;
6011                         break;
6012                 }
6013         }
6014
6015         if (!(tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE))
6016                 goto done;
6017
6018         memset(tpr->rx_jmb, 0, TG3_RX_JUMBO_RING_BYTES);
6019
6020         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
6021                 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
6022                         struct tg3_rx_buffer_desc *rxd;
6023
6024                         rxd = &tpr->rx_jmb[i].std;
6025                         rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
6026                         rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
6027                                 RXD_FLAG_JUMBO;
6028                         rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
6029                                (i << RXD_OPAQUE_INDEX_SHIFT));
6030                 }
6031
6032                 for (i = 0; i < tp->rx_jumbo_pending; i++) {
6033                         if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_JUMBO,
6034                                              i) < 0) {
6035                                 printk(KERN_WARNING PFX
6036                                        "%s: Using a smaller RX jumbo ring, "
6037                                        "only %d out of %d buffers were "
6038                                        "allocated successfully.\n",
6039                                        tp->dev->name, i, tp->rx_jumbo_pending);
6040                                 if (i == 0)
6041                                         goto initfail;
6042                                 tp->rx_jumbo_pending = i;
6043                                 break;
6044                         }
6045                 }
6046         }
6047
6048 done:
6049         return 0;
6050
6051 initfail:
6052         tg3_rx_prodring_free(tp, tpr);
6053         return -ENOMEM;
6054 }
6055
6056 static void tg3_rx_prodring_fini(struct tg3 *tp,
6057                                  struct tg3_rx_prodring_set *tpr)
6058 {
6059         kfree(tpr->rx_std_buffers);
6060         tpr->rx_std_buffers = NULL;
6061         kfree(tpr->rx_jmb_buffers);
6062         tpr->rx_jmb_buffers = NULL;
6063         if (tpr->rx_std) {
6064                 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
6065                                     tpr->rx_std, tpr->rx_std_mapping);
6066                 tpr->rx_std = NULL;
6067         }
6068         if (tpr->rx_jmb) {
6069                 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
6070                                     tpr->rx_jmb, tpr->rx_jmb_mapping);
6071                 tpr->rx_jmb = NULL;
6072         }
6073 }
6074
6075 static int tg3_rx_prodring_init(struct tg3 *tp,
6076                                 struct tg3_rx_prodring_set *tpr)
6077 {
6078         tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE, GFP_KERNEL);
6079         if (!tpr->rx_std_buffers)
6080                 return -ENOMEM;
6081
6082         tpr->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
6083                                            &tpr->rx_std_mapping);
6084         if (!tpr->rx_std)
6085                 goto err_out;
6086
6087         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
6088                 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE,
6089                                               GFP_KERNEL);
6090                 if (!tpr->rx_jmb_buffers)
6091                         goto err_out;
6092
6093                 tpr->rx_jmb = pci_alloc_consistent(tp->pdev,
6094                                                    TG3_RX_JUMBO_RING_BYTES,
6095                                                    &tpr->rx_jmb_mapping);
6096                 if (!tpr->rx_jmb)
6097                         goto err_out;
6098         }
6099
6100         return 0;
6101
6102 err_out:
6103         tg3_rx_prodring_fini(tp, tpr);
6104         return -ENOMEM;
6105 }
6106
6107 /* Free up pending packets in all rx/tx rings.
6108  *
6109  * The chip has been shut down and the driver detached from
6110  * the networking, so no interrupts or new tx packets will
6111  * end up in the driver.  tp->{tx,}lock is not held and we are not
6112  * in an interrupt context and thus may sleep.
6113  */
6114 static void tg3_free_rings(struct tg3 *tp)
6115 {
6116         int i, j;
6117
6118         for (j = 0; j < tp->irq_cnt; j++) {
6119                 struct tg3_napi *tnapi = &tp->napi[j];
6120
6121                 if (!tnapi->tx_buffers)
6122                         continue;
6123
6124                 for (i = 0; i < TG3_TX_RING_SIZE; ) {
6125                         struct ring_info *txp;
6126                         struct sk_buff *skb;
6127                         unsigned int k;
6128
6129                         txp = &tnapi->tx_buffers[i];
6130                         skb = txp->skb;
6131
6132                         if (skb == NULL) {
6133                                 i++;
6134                                 continue;
6135                         }
6136
6137                         pci_unmap_single(tp->pdev,
6138                                          pci_unmap_addr(txp, mapping),
6139                                          skb_headlen(skb),
6140                                          PCI_DMA_TODEVICE);
6141                         txp->skb = NULL;
6142
6143                         i++;
6144
6145                         for (k = 0; k < skb_shinfo(skb)->nr_frags; k++) {
6146                                 txp = &tnapi->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
6147                                 pci_unmap_page(tp->pdev,
6148                                                pci_unmap_addr(txp, mapping),
6149                                                skb_shinfo(skb)->frags[k].size,
6150                                                PCI_DMA_TODEVICE);
6151                                 i++;
6152                         }
6153
6154                         dev_kfree_skb_any(skb);
6155                 }
6156
6157                 if (tp->irq_cnt == 1 || j != tp->irq_cnt - 1)
6158                         tg3_rx_prodring_free(tp, &tp->prodring[j]);
6159         }
6160 }
6161
6162 /* Initialize tx/rx rings for packet processing.
6163  *
6164  * The chip has been shut down and the driver detached from
6165  * the networking, so no interrupts or new tx packets will
6166  * end up in the driver.  tp->{tx,}lock are held and thus
6167  * we may not sleep.
6168  */
6169 static int tg3_init_rings(struct tg3 *tp)
6170 {
6171         int i;
6172
6173         /* Free up all the SKBs. */
6174         tg3_free_rings(tp);
6175
6176         for (i = 0; i < tp->irq_cnt; i++) {
6177                 struct tg3_napi *tnapi = &tp->napi[i];
6178
6179                 tnapi->last_tag = 0;
6180                 tnapi->last_irq_tag = 0;
6181                 tnapi->hw_status->status = 0;
6182                 tnapi->hw_status->status_tag = 0;
6183                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6184
6185                 tnapi->tx_prod = 0;
6186                 tnapi->tx_cons = 0;
6187                 if (tnapi->tx_ring)
6188                         memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
6189
6190                 tnapi->rx_rcb_ptr = 0;
6191                 if (tnapi->rx_rcb)
6192                         memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
6193
6194                 if ((tp->irq_cnt == 1 || i != tp->irq_cnt - 1) &&
6195                         tg3_rx_prodring_alloc(tp, &tp->prodring[i]))
6196                         return -ENOMEM;
6197         }
6198
6199         return 0;
6200 }
6201
6202 /*
6203  * Must not be invoked with interrupt sources disabled and
6204  * the hardware shutdown down.
6205  */
6206 static void tg3_free_consistent(struct tg3 *tp)
6207 {
6208         int i;
6209
6210         for (i = 0; i < tp->irq_cnt; i++) {
6211                 struct tg3_napi *tnapi = &tp->napi[i];
6212
6213                 if (tnapi->tx_ring) {
6214                         pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
6215                                 tnapi->tx_ring, tnapi->tx_desc_mapping);
6216                         tnapi->tx_ring = NULL;
6217                 }
6218
6219                 kfree(tnapi->tx_buffers);
6220                 tnapi->tx_buffers = NULL;
6221
6222                 if (tnapi->rx_rcb) {
6223                         pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
6224                                             tnapi->rx_rcb,
6225                                             tnapi->rx_rcb_mapping);
6226                         tnapi->rx_rcb = NULL;
6227                 }
6228
6229                 if (tnapi->hw_status) {
6230                         pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
6231                                             tnapi->hw_status,
6232                                             tnapi->status_mapping);
6233                         tnapi->hw_status = NULL;
6234                 }
6235         }
6236
6237         if (tp->hw_stats) {
6238                 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
6239                                     tp->hw_stats, tp->stats_mapping);
6240                 tp->hw_stats = NULL;
6241         }
6242
6243         for (i = 0; i < (tp->irq_cnt == 1 ? 1 : tp->irq_cnt - 1); i++)
6244                 tg3_rx_prodring_fini(tp, &tp->prodring[i]);
6245 }
6246
6247 /*
6248  * Must not be invoked with interrupt sources disabled and
6249  * the hardware shutdown down.  Can sleep.
6250  */
6251 static int tg3_alloc_consistent(struct tg3 *tp)
6252 {
6253         int i;
6254
6255         for (i = 0; i < (tp->irq_cnt == 1 ? 1 : tp->irq_cnt - 1); i++) {
6256                 if (tg3_rx_prodring_init(tp, &tp->prodring[i]))
6257                         goto err_out;
6258         }
6259
6260         tp->hw_stats = pci_alloc_consistent(tp->pdev,
6261                                             sizeof(struct tg3_hw_stats),
6262                                             &tp->stats_mapping);
6263         if (!tp->hw_stats)
6264                 goto err_out;
6265
6266         memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6267
6268         for (i = 0; i < tp->irq_cnt; i++) {
6269                 struct tg3_napi *tnapi = &tp->napi[i];
6270                 struct tg3_hw_status *sblk;
6271
6272                 tnapi->hw_status = pci_alloc_consistent(tp->pdev,
6273                                                         TG3_HW_STATUS_SIZE,
6274                                                         &tnapi->status_mapping);
6275                 if (!tnapi->hw_status)
6276                         goto err_out;
6277
6278                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6279                 sblk = tnapi->hw_status;
6280
6281                 /* If multivector TSS is enabled, vector 0 does not handle
6282                  * tx interrupts.  Don't allocate any resources for it.
6283                  */
6284                 if ((!i && !(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) ||
6285                     (i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))) {
6286                         tnapi->tx_buffers = kzalloc(sizeof(struct ring_info) *
6287                                                     TG3_TX_RING_SIZE,
6288                                                     GFP_KERNEL);
6289                         if (!tnapi->tx_buffers)
6290                                 goto err_out;
6291
6292                         tnapi->tx_ring = pci_alloc_consistent(tp->pdev,
6293                                                               TG3_TX_RING_BYTES,
6294                                                        &tnapi->tx_desc_mapping);
6295                         if (!tnapi->tx_ring)
6296                                 goto err_out;
6297                 }
6298
6299                 /*
6300                  * When RSS is enabled, the status block format changes
6301                  * slightly.  The "rx_jumbo_consumer", "reserved",
6302                  * and "rx_mini_consumer" members get mapped to the
6303                  * other three rx return ring producer indexes.
6304                  */
6305                 switch (i) {
6306                 default:
6307                         tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
6308                         break;
6309                 case 2:
6310                         tnapi->rx_rcb_prod_idx = &sblk->rx_jumbo_consumer;
6311                         break;
6312                 case 3:
6313                         tnapi->rx_rcb_prod_idx = &sblk->reserved;
6314                         break;
6315                 case 4:
6316                         tnapi->rx_rcb_prod_idx = &sblk->rx_mini_consumer;
6317                         break;
6318                 }
6319
6320                 if (tp->irq_cnt == 1)
6321                         tnapi->prodring = &tp->prodring[0];
6322                 else if (i)
6323                         tnapi->prodring = &tp->prodring[i - 1];
6324
6325                 /*
6326                  * If multivector RSS is enabled, vector 0 does not handle
6327                  * rx or tx interrupts.  Don't allocate any resources for it.
6328                  */
6329                 if (!i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS))
6330                         continue;
6331
6332                 tnapi->rx_rcb = pci_alloc_consistent(tp->pdev,
6333                                                      TG3_RX_RCB_RING_BYTES(tp),
6334                                                      &tnapi->rx_rcb_mapping);
6335                 if (!tnapi->rx_rcb)
6336                         goto err_out;
6337
6338                 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
6339         }
6340
6341         return 0;
6342
6343 err_out:
6344         tg3_free_consistent(tp);
6345         return -ENOMEM;
6346 }
6347
6348 #define MAX_WAIT_CNT 1000
6349
6350 /* To stop a block, clear the enable bit and poll till it
6351  * clears.  tp->lock is held.
6352  */
6353 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
6354 {
6355         unsigned int i;
6356         u32 val;
6357
6358         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6359                 switch (ofs) {
6360                 case RCVLSC_MODE:
6361                 case DMAC_MODE:
6362                 case MBFREE_MODE:
6363                 case BUFMGR_MODE:
6364                 case MEMARB_MODE:
6365                         /* We can't enable/disable these bits of the
6366                          * 5705/5750, just say success.
6367                          */
6368                         return 0;
6369
6370                 default:
6371                         break;
6372                 }
6373         }
6374
6375         val = tr32(ofs);
6376         val &= ~enable_bit;
6377         tw32_f(ofs, val);
6378
6379         for (i = 0; i < MAX_WAIT_CNT; i++) {
6380                 udelay(100);
6381                 val = tr32(ofs);
6382                 if ((val & enable_bit) == 0)
6383                         break;
6384         }
6385
6386         if (i == MAX_WAIT_CNT && !silent) {
6387                 printk(KERN_ERR PFX "tg3_stop_block timed out, "
6388                        "ofs=%lx enable_bit=%x\n",
6389                        ofs, enable_bit);
6390                 return -ENODEV;
6391         }
6392
6393         return 0;
6394 }
6395
6396 /* tp->lock is held. */
6397 static int tg3_abort_hw(struct tg3 *tp, int silent)
6398 {
6399         int i, err;
6400
6401         tg3_disable_ints(tp);
6402
6403         tp->rx_mode &= ~RX_MODE_ENABLE;
6404         tw32_f(MAC_RX_MODE, tp->rx_mode);
6405         udelay(10);
6406
6407         err  = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
6408         err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
6409         err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
6410         err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
6411         err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
6412         err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
6413
6414         err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
6415         err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
6416         err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
6417         err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
6418         err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
6419         err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
6420         err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
6421
6422         tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
6423         tw32_f(MAC_MODE, tp->mac_mode);
6424         udelay(40);
6425
6426         tp->tx_mode &= ~TX_MODE_ENABLE;
6427         tw32_f(MAC_TX_MODE, tp->tx_mode);
6428
6429         for (i = 0; i < MAX_WAIT_CNT; i++) {
6430                 udelay(100);
6431                 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
6432                         break;
6433         }
6434         if (i >= MAX_WAIT_CNT) {
6435                 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
6436                        "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
6437                        tp->dev->name, tr32(MAC_TX_MODE));
6438                 err |= -ENODEV;
6439         }
6440
6441         err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
6442         err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
6443         err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
6444
6445         tw32(FTQ_RESET, 0xffffffff);
6446         tw32(FTQ_RESET, 0x00000000);
6447
6448         err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
6449         err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
6450
6451         for (i = 0; i < tp->irq_cnt; i++) {
6452                 struct tg3_napi *tnapi = &tp->napi[i];
6453                 if (tnapi->hw_status)
6454                         memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6455         }
6456         if (tp->hw_stats)
6457                 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6458
6459         return err;
6460 }
6461
6462 static void tg3_ape_send_event(struct tg3 *tp, u32 event)
6463 {
6464         int i;
6465         u32 apedata;
6466
6467         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
6468         if (apedata != APE_SEG_SIG_MAGIC)
6469                 return;
6470
6471         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
6472         if (!(apedata & APE_FW_STATUS_READY))
6473                 return;
6474
6475         /* Wait for up to 1 millisecond for APE to service previous event. */
6476         for (i = 0; i < 10; i++) {
6477                 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
6478                         return;
6479
6480                 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
6481
6482                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6483                         tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
6484                                         event | APE_EVENT_STATUS_EVENT_PENDING);
6485
6486                 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
6487
6488                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6489                         break;
6490
6491                 udelay(100);
6492         }
6493
6494         if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6495                 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
6496 }
6497
6498 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
6499 {
6500         u32 event;
6501         u32 apedata;
6502
6503         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
6504                 return;
6505
6506         switch (kind) {
6507                 case RESET_KIND_INIT:
6508                         tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
6509                                         APE_HOST_SEG_SIG_MAGIC);
6510                         tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
6511                                         APE_HOST_SEG_LEN_MAGIC);
6512                         apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
6513                         tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
6514                         tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
6515                                         APE_HOST_DRIVER_ID_MAGIC);
6516                         tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
6517                                         APE_HOST_BEHAV_NO_PHYLOCK);
6518
6519                         event = APE_EVENT_STATUS_STATE_START;
6520                         break;
6521                 case RESET_KIND_SHUTDOWN:
6522                         /* With the interface we are currently using,
6523                          * APE does not track driver state.  Wiping
6524                          * out the HOST SEGMENT SIGNATURE forces
6525                          * the APE to assume OS absent status.
6526                          */
6527                         tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
6528
6529                         event = APE_EVENT_STATUS_STATE_UNLOAD;
6530                         break;
6531                 case RESET_KIND_SUSPEND:
6532                         event = APE_EVENT_STATUS_STATE_SUSPEND;
6533                         break;
6534                 default:
6535                         return;
6536         }
6537
6538         event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
6539
6540         tg3_ape_send_event(tp, event);
6541 }
6542
6543 /* tp->lock is held. */
6544 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
6545 {
6546         tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
6547                       NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
6548
6549         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6550                 switch (kind) {
6551                 case RESET_KIND_INIT:
6552                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6553                                       DRV_STATE_START);
6554                         break;
6555
6556                 case RESET_KIND_SHUTDOWN:
6557                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6558                                       DRV_STATE_UNLOAD);
6559                         break;
6560
6561                 case RESET_KIND_SUSPEND:
6562                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6563                                       DRV_STATE_SUSPEND);
6564                         break;
6565
6566                 default:
6567                         break;
6568                 }
6569         }
6570
6571         if (kind == RESET_KIND_INIT ||
6572             kind == RESET_KIND_SUSPEND)
6573                 tg3_ape_driver_state_change(tp, kind);
6574 }
6575
6576 /* tp->lock is held. */
6577 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
6578 {
6579         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6580                 switch (kind) {
6581                 case RESET_KIND_INIT:
6582                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6583                                       DRV_STATE_START_DONE);
6584                         break;
6585
6586                 case RESET_KIND_SHUTDOWN:
6587                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6588                                       DRV_STATE_UNLOAD_DONE);
6589                         break;
6590
6591                 default:
6592                         break;
6593                 }
6594         }
6595
6596         if (kind == RESET_KIND_SHUTDOWN)
6597                 tg3_ape_driver_state_change(tp, kind);
6598 }
6599
6600 /* tp->lock is held. */
6601 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
6602 {
6603         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6604                 switch (kind) {
6605                 case RESET_KIND_INIT:
6606                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6607                                       DRV_STATE_START);
6608                         break;
6609
6610                 case RESET_KIND_SHUTDOWN:
6611                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6612                                       DRV_STATE_UNLOAD);
6613                         break;
6614
6615                 case RESET_KIND_SUSPEND:
6616                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6617                                       DRV_STATE_SUSPEND);
6618                         break;
6619
6620                 default:
6621                         break;
6622                 }
6623         }
6624 }
6625
6626 static int tg3_poll_fw(struct tg3 *tp)
6627 {
6628         int i;
6629         u32 val;
6630
6631         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6632                 /* Wait up to 20ms for init done. */
6633                 for (i = 0; i < 200; i++) {
6634                         if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
6635                                 return 0;
6636                         udelay(100);
6637                 }
6638                 return -ENODEV;
6639         }
6640
6641         /* Wait for firmware initialization to complete. */
6642         for (i = 0; i < 100000; i++) {
6643                 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
6644                 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
6645                         break;
6646                 udelay(10);
6647         }
6648
6649         /* Chip might not be fitted with firmware.  Some Sun onboard
6650          * parts are configured like that.  So don't signal the timeout
6651          * of the above loop as an error, but do report the lack of
6652          * running firmware once.
6653          */
6654         if (i >= 100000 &&
6655             !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
6656                 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
6657
6658                 printk(KERN_INFO PFX "%s: No firmware running.\n",
6659                        tp->dev->name);
6660         }
6661
6662         return 0;
6663 }
6664
6665 /* Save PCI command register before chip reset */
6666 static void tg3_save_pci_state(struct tg3 *tp)
6667 {
6668         pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
6669 }
6670
6671 /* Restore PCI state after chip reset */
6672 static void tg3_restore_pci_state(struct tg3 *tp)
6673 {
6674         u32 val;
6675
6676         /* Re-enable indirect register accesses. */
6677         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
6678                                tp->misc_host_ctrl);
6679
6680         /* Set MAX PCI retry to zero. */
6681         val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
6682         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6683             (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
6684                 val |= PCISTATE_RETRY_SAME_DMA;
6685         /* Allow reads and writes to the APE register and memory space. */
6686         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
6687                 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6688                        PCISTATE_ALLOW_APE_SHMEM_WR;
6689         pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
6690
6691         pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
6692
6693         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
6694                 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6695                         pcie_set_readrq(tp->pdev, 4096);
6696                 else {
6697                         pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
6698                                               tp->pci_cacheline_sz);
6699                         pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
6700                                               tp->pci_lat_timer);
6701                 }
6702         }
6703
6704         /* Make sure PCI-X relaxed ordering bit is clear. */
6705         if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
6706                 u16 pcix_cmd;
6707
6708                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6709                                      &pcix_cmd);
6710                 pcix_cmd &= ~PCI_X_CMD_ERO;
6711                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6712                                       pcix_cmd);
6713         }
6714
6715         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
6716
6717                 /* Chip reset on 5780 will reset MSI enable bit,
6718                  * so need to restore it.
6719                  */
6720                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6721                         u16 ctrl;
6722
6723                         pci_read_config_word(tp->pdev,
6724                                              tp->msi_cap + PCI_MSI_FLAGS,
6725                                              &ctrl);
6726                         pci_write_config_word(tp->pdev,
6727                                               tp->msi_cap + PCI_MSI_FLAGS,
6728                                               ctrl | PCI_MSI_FLAGS_ENABLE);
6729                         val = tr32(MSGINT_MODE);
6730                         tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
6731                 }
6732         }
6733 }
6734
6735 static void tg3_stop_fw(struct tg3 *);
6736
6737 /* tp->lock is held. */
6738 static int tg3_chip_reset(struct tg3 *tp)
6739 {
6740         u32 val;
6741         void (*write_op)(struct tg3 *, u32, u32);
6742         int i, err;
6743
6744         tg3_nvram_lock(tp);
6745
6746         tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
6747
6748         /* No matching tg3_nvram_unlock() after this because
6749          * chip reset below will undo the nvram lock.
6750          */
6751         tp->nvram_lock_cnt = 0;
6752
6753         /* GRC_MISC_CFG core clock reset will clear the memory
6754          * enable bit in PCI register 4 and the MSI enable bit
6755          * on some chips, so we save relevant registers here.
6756          */
6757         tg3_save_pci_state(tp);
6758
6759         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
6760             (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
6761                 tw32(GRC_FASTBOOT_PC, 0);
6762
6763         /*
6764          * We must avoid the readl() that normally takes place.
6765          * It locks machines, causes machine checks, and other
6766          * fun things.  So, temporarily disable the 5701
6767          * hardware workaround, while we do the reset.
6768          */
6769         write_op = tp->write32;
6770         if (write_op == tg3_write_flush_reg32)
6771                 tp->write32 = tg3_write32;
6772
6773         /* Prevent the irq handler from reading or writing PCI registers
6774          * during chip reset when the memory enable bit in the PCI command
6775          * register may be cleared.  The chip does not generate interrupt
6776          * at this time, but the irq handler may still be called due to irq
6777          * sharing or irqpoll.
6778          */
6779         tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
6780         for (i = 0; i < tp->irq_cnt; i++) {
6781                 struct tg3_napi *tnapi = &tp->napi[i];
6782                 if (tnapi->hw_status) {
6783                         tnapi->hw_status->status = 0;
6784                         tnapi->hw_status->status_tag = 0;
6785                 }
6786                 tnapi->last_tag = 0;
6787                 tnapi->last_irq_tag = 0;
6788         }
6789         smp_mb();
6790
6791         for (i = 0; i < tp->irq_cnt; i++)
6792                 synchronize_irq(tp->napi[i].irq_vec);
6793
6794         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6795                 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
6796                 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
6797         }
6798
6799         /* do the reset */
6800         val = GRC_MISC_CFG_CORECLK_RESET;
6801
6802         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
6803                 if (tr32(0x7e2c) == 0x60) {
6804                         tw32(0x7e2c, 0x20);
6805                 }
6806                 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
6807                         tw32(GRC_MISC_CFG, (1 << 29));
6808                         val |= (1 << 29);
6809                 }
6810         }
6811
6812         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6813                 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
6814                 tw32(GRC_VCPU_EXT_CTRL,
6815                      tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
6816         }
6817
6818         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6819                 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
6820         tw32(GRC_MISC_CFG, val);
6821
6822         /* restore 5701 hardware bug workaround write method */
6823         tp->write32 = write_op;
6824
6825         /* Unfortunately, we have to delay before the PCI read back.
6826          * Some 575X chips even will not respond to a PCI cfg access
6827          * when the reset command is given to the chip.
6828          *
6829          * How do these hardware designers expect things to work
6830          * properly if the PCI write is posted for a long period
6831          * of time?  It is always necessary to have some method by
6832          * which a register read back can occur to push the write
6833          * out which does the reset.
6834          *
6835          * For most tg3 variants the trick below was working.
6836          * Ho hum...
6837          */
6838         udelay(120);
6839
6840         /* Flush PCI posted writes.  The normal MMIO registers
6841          * are inaccessible at this time so this is the only
6842          * way to make this reliably (actually, this is no longer
6843          * the case, see above).  I tried to use indirect
6844          * register read/write but this upset some 5701 variants.
6845          */
6846         pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
6847
6848         udelay(120);
6849
6850         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
6851                 u16 val16;
6852
6853                 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
6854                         int i;
6855                         u32 cfg_val;
6856
6857                         /* Wait for link training to complete.  */
6858                         for (i = 0; i < 5000; i++)
6859                                 udelay(100);
6860
6861                         pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
6862                         pci_write_config_dword(tp->pdev, 0xc4,
6863                                                cfg_val | (1 << 15));
6864                 }
6865
6866                 /* Clear the "no snoop" and "relaxed ordering" bits. */
6867                 pci_read_config_word(tp->pdev,
6868                                      tp->pcie_cap + PCI_EXP_DEVCTL,
6869                                      &val16);
6870                 val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
6871                            PCI_EXP_DEVCTL_NOSNOOP_EN);
6872                 /*
6873                  * Older PCIe devices only support the 128 byte
6874                  * MPS setting.  Enforce the restriction.
6875                  */
6876                 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
6877                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784))
6878                         val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
6879                 pci_write_config_word(tp->pdev,
6880                                       tp->pcie_cap + PCI_EXP_DEVCTL,
6881                                       val16);
6882
6883                 pcie_set_readrq(tp->pdev, 4096);
6884
6885                 /* Clear error status */
6886                 pci_write_config_word(tp->pdev,
6887                                       tp->pcie_cap + PCI_EXP_DEVSTA,
6888                                       PCI_EXP_DEVSTA_CED |
6889                                       PCI_EXP_DEVSTA_NFED |
6890                                       PCI_EXP_DEVSTA_FED |
6891                                       PCI_EXP_DEVSTA_URD);
6892         }
6893
6894         tg3_restore_pci_state(tp);
6895
6896         tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
6897
6898         val = 0;
6899         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
6900                 val = tr32(MEMARB_MODE);
6901         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
6902
6903         if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
6904                 tg3_stop_fw(tp);
6905                 tw32(0x5000, 0x400);
6906         }
6907
6908         tw32(GRC_MODE, tp->grc_mode);
6909
6910         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
6911                 val = tr32(0xc4);
6912
6913                 tw32(0xc4, val | (1 << 15));
6914         }
6915
6916         if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
6917             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6918                 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
6919                 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
6920                         tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
6921                 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6922         }
6923
6924         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6925                 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
6926                 tw32_f(MAC_MODE, tp->mac_mode);
6927         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
6928                 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
6929                 tw32_f(MAC_MODE, tp->mac_mode);
6930         } else if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
6931                 tp->mac_mode &= (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
6932                 if (tp->mac_mode & MAC_MODE_APE_TX_EN)
6933                         tp->mac_mode |= MAC_MODE_TDE_ENABLE;
6934                 tw32_f(MAC_MODE, tp->mac_mode);
6935         } else
6936                 tw32_f(MAC_MODE, 0);
6937         udelay(40);
6938
6939         tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
6940
6941         err = tg3_poll_fw(tp);
6942         if (err)
6943                 return err;
6944
6945         tg3_mdio_start(tp);
6946
6947         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6948                 u8 phy_addr;
6949
6950                 phy_addr = tp->phy_addr;
6951                 tp->phy_addr = TG3_PHY_PCIE_ADDR;
6952
6953                 tg3_writephy(tp, TG3_PCIEPHY_BLOCK_ADDR,
6954                              TG3_PCIEPHY_TXB_BLK << TG3_PCIEPHY_BLOCK_SHIFT);
6955                 val = TG3_PCIEPHY_TX0CTRL1_TXOCM | TG3_PCIEPHY_TX0CTRL1_RDCTL |
6956                       TG3_PCIEPHY_TX0CTRL1_TXCMV | TG3_PCIEPHY_TX0CTRL1_TKSEL |
6957                       TG3_PCIEPHY_TX0CTRL1_NB_EN;
6958                 tg3_writephy(tp, TG3_PCIEPHY_TX0CTRL1, val);
6959                 udelay(10);
6960
6961                 tg3_writephy(tp, TG3_PCIEPHY_BLOCK_ADDR,
6962                              TG3_PCIEPHY_XGXS_BLK1 << TG3_PCIEPHY_BLOCK_SHIFT);
6963                 val = TG3_PCIEPHY_PWRMGMT4_LOWPWR_EN |
6964                       TG3_PCIEPHY_PWRMGMT4_L1PLLPD_EN;
6965                 tg3_writephy(tp, TG3_PCIEPHY_PWRMGMT4, val);
6966                 udelay(10);
6967
6968                 tp->phy_addr = phy_addr;
6969         }
6970
6971         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
6972             tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
6973             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
6974             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) {
6975                 val = tr32(0x7c00);
6976
6977                 tw32(0x7c00, val | (1 << 25));
6978         }
6979
6980         /* Reprobe ASF enable state.  */
6981         tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
6982         tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
6983         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
6984         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
6985                 u32 nic_cfg;
6986
6987                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
6988                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
6989                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
6990                         tp->last_event_jiffies = jiffies;
6991                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
6992                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
6993                 }
6994         }
6995
6996         return 0;
6997 }
6998
6999 /* tp->lock is held. */
7000 static void tg3_stop_fw(struct tg3 *tp)
7001 {
7002         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
7003            !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7004                 /* Wait for RX cpu to ACK the previous event. */
7005                 tg3_wait_for_event_ack(tp);
7006
7007                 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
7008
7009                 tg3_generate_fw_event(tp);
7010
7011                 /* Wait for RX cpu to ACK this event. */
7012                 tg3_wait_for_event_ack(tp);
7013         }
7014 }
7015
7016 /* tp->lock is held. */
7017 static int tg3_halt(struct tg3 *tp, int kind, int silent)
7018 {
7019         int err;
7020
7021         tg3_stop_fw(tp);
7022
7023         tg3_write_sig_pre_reset(tp, kind);
7024
7025         tg3_abort_hw(tp, silent);
7026         err = tg3_chip_reset(tp);
7027
7028         __tg3_set_mac_addr(tp, 0);
7029
7030         tg3_write_sig_legacy(tp, kind);
7031         tg3_write_sig_post_reset(tp, kind);
7032
7033         if (err)
7034                 return err;
7035
7036         return 0;
7037 }
7038
7039 #define RX_CPU_SCRATCH_BASE     0x30000
7040 #define RX_CPU_SCRATCH_SIZE     0x04000
7041 #define TX_CPU_SCRATCH_BASE     0x34000
7042 #define TX_CPU_SCRATCH_SIZE     0x04000
7043
7044 /* tp->lock is held. */
7045 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
7046 {
7047         int i;
7048
7049         BUG_ON(offset == TX_CPU_BASE &&
7050             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
7051
7052         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7053                 u32 val = tr32(GRC_VCPU_EXT_CTRL);
7054
7055                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
7056                 return 0;
7057         }
7058         if (offset == RX_CPU_BASE) {
7059                 for (i = 0; i < 10000; i++) {
7060                         tw32(offset + CPU_STATE, 0xffffffff);
7061                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
7062                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7063                                 break;
7064                 }
7065
7066                 tw32(offset + CPU_STATE, 0xffffffff);
7067                 tw32_f(offset + CPU_MODE,  CPU_MODE_HALT);
7068                 udelay(10);
7069         } else {
7070                 for (i = 0; i < 10000; i++) {
7071                         tw32(offset + CPU_STATE, 0xffffffff);
7072                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
7073                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7074                                 break;
7075                 }
7076         }
7077
7078         if (i >= 10000) {
7079                 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
7080                        "and %s CPU\n",
7081                        tp->dev->name,
7082                        (offset == RX_CPU_BASE ? "RX" : "TX"));
7083                 return -ENODEV;
7084         }
7085
7086         /* Clear firmware's nvram arbitration. */
7087         if (tp->tg3_flags & TG3_FLAG_NVRAM)
7088                 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
7089         return 0;
7090 }
7091
7092 struct fw_info {
7093         unsigned int fw_base;
7094         unsigned int fw_len;
7095         const __be32 *fw_data;
7096 };
7097
7098 /* tp->lock is held. */
7099 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
7100                                  int cpu_scratch_size, struct fw_info *info)
7101 {
7102         int err, lock_err, i;
7103         void (*write_op)(struct tg3 *, u32, u32);
7104
7105         if (cpu_base == TX_CPU_BASE &&
7106             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7107                 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
7108                        "TX cpu firmware on %s which is 5705.\n",
7109                        tp->dev->name);
7110                 return -EINVAL;
7111         }
7112
7113         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7114                 write_op = tg3_write_mem;
7115         else
7116                 write_op = tg3_write_indirect_reg32;
7117
7118         /* It is possible that bootcode is still loading at this point.
7119          * Get the nvram lock first before halting the cpu.
7120          */
7121         lock_err = tg3_nvram_lock(tp);
7122         err = tg3_halt_cpu(tp, cpu_base);
7123         if (!lock_err)
7124                 tg3_nvram_unlock(tp);
7125         if (err)
7126                 goto out;
7127
7128         for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
7129                 write_op(tp, cpu_scratch_base + i, 0);
7130         tw32(cpu_base + CPU_STATE, 0xffffffff);
7131         tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
7132         for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
7133                 write_op(tp, (cpu_scratch_base +
7134                               (info->fw_base & 0xffff) +
7135                               (i * sizeof(u32))),
7136                               be32_to_cpu(info->fw_data[i]));
7137
7138         err = 0;
7139
7140 out:
7141         return err;
7142 }
7143
7144 /* tp->lock is held. */
7145 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
7146 {
7147         struct fw_info info;
7148         const __be32 *fw_data;
7149         int err, i;
7150
7151         fw_data = (void *)tp->fw->data;
7152
7153         /* Firmware blob starts with version numbers, followed by
7154            start address and length. We are setting complete length.
7155            length = end_address_of_bss - start_address_of_text.
7156            Remainder is the blob to be loaded contiguously
7157            from start address. */
7158
7159         info.fw_base = be32_to_cpu(fw_data[1]);
7160         info.fw_len = tp->fw->size - 12;
7161         info.fw_data = &fw_data[3];
7162
7163         err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
7164                                     RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
7165                                     &info);
7166         if (err)
7167                 return err;
7168
7169         err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
7170                                     TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
7171                                     &info);
7172         if (err)
7173                 return err;
7174
7175         /* Now startup only the RX cpu. */
7176         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7177         tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
7178
7179         for (i = 0; i < 5; i++) {
7180                 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
7181                         break;
7182                 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7183                 tw32(RX_CPU_BASE + CPU_MODE,  CPU_MODE_HALT);
7184                 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
7185                 udelay(1000);
7186         }
7187         if (i >= 5) {
7188                 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
7189                        "to set RX CPU PC, is %08x should be %08x\n",
7190                        tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
7191                        info.fw_base);
7192                 return -ENODEV;
7193         }
7194         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7195         tw32_f(RX_CPU_BASE + CPU_MODE,  0x00000000);
7196
7197         return 0;
7198 }
7199
7200 /* 5705 needs a special version of the TSO firmware.  */
7201
7202 /* tp->lock is held. */
7203 static int tg3_load_tso_firmware(struct tg3 *tp)
7204 {
7205         struct fw_info info;
7206         const __be32 *fw_data;
7207         unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
7208         int err, i;
7209
7210         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7211                 return 0;
7212
7213         fw_data = (void *)tp->fw->data;
7214
7215         /* Firmware blob starts with version numbers, followed by
7216            start address and length. We are setting complete length.
7217            length = end_address_of_bss - start_address_of_text.
7218            Remainder is the blob to be loaded contiguously
7219            from start address. */
7220
7221         info.fw_base = be32_to_cpu(fw_data[1]);
7222         cpu_scratch_size = tp->fw_len;
7223         info.fw_len = tp->fw->size - 12;
7224         info.fw_data = &fw_data[3];
7225
7226         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7227                 cpu_base = RX_CPU_BASE;
7228                 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
7229         } else {
7230                 cpu_base = TX_CPU_BASE;
7231                 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
7232                 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
7233         }
7234
7235         err = tg3_load_firmware_cpu(tp, cpu_base,
7236                                     cpu_scratch_base, cpu_scratch_size,
7237                                     &info);
7238         if (err)
7239                 return err;
7240
7241         /* Now startup the cpu. */
7242         tw32(cpu_base + CPU_STATE, 0xffffffff);
7243         tw32_f(cpu_base + CPU_PC, info.fw_base);
7244
7245         for (i = 0; i < 5; i++) {
7246                 if (tr32(cpu_base + CPU_PC) == info.fw_base)
7247                         break;
7248                 tw32(cpu_base + CPU_STATE, 0xffffffff);
7249                 tw32(cpu_base + CPU_MODE,  CPU_MODE_HALT);
7250                 tw32_f(cpu_base + CPU_PC, info.fw_base);
7251                 udelay(1000);
7252         }
7253         if (i >= 5) {
7254                 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
7255                        "to set CPU PC, is %08x should be %08x\n",
7256                        tp->dev->name, tr32(cpu_base + CPU_PC),
7257                        info.fw_base);
7258                 return -ENODEV;
7259         }
7260         tw32(cpu_base + CPU_STATE, 0xffffffff);
7261         tw32_f(cpu_base + CPU_MODE,  0x00000000);
7262         return 0;
7263 }
7264
7265
7266 static int tg3_set_mac_addr(struct net_device *dev, void *p)
7267 {
7268         struct tg3 *tp = netdev_priv(dev);
7269         struct sockaddr *addr = p;
7270         int err = 0, skip_mac_1 = 0;
7271
7272         if (!is_valid_ether_addr(addr->sa_data))
7273                 return -EINVAL;
7274
7275         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
7276
7277         if (!netif_running(dev))
7278                 return 0;
7279
7280         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
7281                 u32 addr0_high, addr0_low, addr1_high, addr1_low;
7282
7283                 addr0_high = tr32(MAC_ADDR_0_HIGH);
7284                 addr0_low = tr32(MAC_ADDR_0_LOW);
7285                 addr1_high = tr32(MAC_ADDR_1_HIGH);
7286                 addr1_low = tr32(MAC_ADDR_1_LOW);
7287
7288                 /* Skip MAC addr 1 if ASF is using it. */
7289                 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
7290                     !(addr1_high == 0 && addr1_low == 0))
7291                         skip_mac_1 = 1;
7292         }
7293         spin_lock_bh(&tp->lock);
7294         __tg3_set_mac_addr(tp, skip_mac_1);
7295         spin_unlock_bh(&tp->lock);
7296
7297         return err;
7298 }
7299
7300 /* tp->lock is held. */
7301 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
7302                            dma_addr_t mapping, u32 maxlen_flags,
7303                            u32 nic_addr)
7304 {
7305         tg3_write_mem(tp,
7306                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
7307                       ((u64) mapping >> 32));
7308         tg3_write_mem(tp,
7309                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
7310                       ((u64) mapping & 0xffffffff));
7311         tg3_write_mem(tp,
7312                       (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
7313                        maxlen_flags);
7314
7315         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7316                 tg3_write_mem(tp,
7317                               (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
7318                               nic_addr);
7319 }
7320
7321 static void __tg3_set_rx_mode(struct net_device *);
7322 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
7323 {
7324         int i;
7325
7326         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) {
7327                 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
7328                 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
7329                 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
7330         } else {
7331                 tw32(HOSTCC_TXCOL_TICKS, 0);
7332                 tw32(HOSTCC_TXMAX_FRAMES, 0);
7333                 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
7334         }
7335
7336         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
7337                 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
7338                 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
7339                 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
7340         } else {
7341                 tw32(HOSTCC_RXCOL_TICKS, 0);
7342                 tw32(HOSTCC_RXMAX_FRAMES, 0);
7343                 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
7344         }
7345
7346         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7347                 u32 val = ec->stats_block_coalesce_usecs;
7348
7349                 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
7350                 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
7351
7352                 if (!netif_carrier_ok(tp->dev))
7353                         val = 0;
7354
7355                 tw32(HOSTCC_STAT_COAL_TICKS, val);
7356         }
7357
7358         for (i = 0; i < tp->irq_cnt - 1; i++) {
7359                 u32 reg;
7360
7361                 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
7362                 tw32(reg, ec->rx_coalesce_usecs);
7363                 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
7364                 tw32(reg, ec->rx_max_coalesced_frames);
7365                 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
7366                 tw32(reg, ec->rx_max_coalesced_frames_irq);
7367
7368                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7369                         reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
7370                         tw32(reg, ec->tx_coalesce_usecs);
7371                         reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
7372                         tw32(reg, ec->tx_max_coalesced_frames);
7373                         reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
7374                         tw32(reg, ec->tx_max_coalesced_frames_irq);
7375                 }
7376         }
7377
7378         for (; i < tp->irq_max - 1; i++) {
7379                 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
7380                 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
7381                 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7382
7383                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7384                         tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
7385                         tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
7386                         tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7387                 }
7388         }
7389 }
7390
7391 /* tp->lock is held. */
7392 static void tg3_rings_reset(struct tg3 *tp)
7393 {
7394         int i;
7395         u32 stblk, txrcb, rxrcb, limit;
7396         struct tg3_napi *tnapi = &tp->napi[0];
7397
7398         /* Disable all transmit rings but the first. */
7399         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7400                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
7401         else
7402                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7403
7404         for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7405              txrcb < limit; txrcb += TG3_BDINFO_SIZE)
7406                 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
7407                               BDINFO_FLAGS_DISABLED);
7408
7409
7410         /* Disable all receive return rings but the first. */
7411         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
7412                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
7413         else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7414                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
7415         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
7416                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
7417         else
7418                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7419
7420         for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7421              rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
7422                 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
7423                               BDINFO_FLAGS_DISABLED);
7424
7425         /* Disable interrupts */
7426         tw32_mailbox_f(tp->napi[0].int_mbox, 1);
7427
7428         /* Zero mailbox registers. */
7429         if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) {
7430                 for (i = 1; i < TG3_IRQ_MAX_VECS; i++) {
7431                         tp->napi[i].tx_prod = 0;
7432                         tp->napi[i].tx_cons = 0;
7433                         tw32_mailbox(tp->napi[i].prodmbox, 0);
7434                         tw32_rx_mbox(tp->napi[i].consmbox, 0);
7435                         tw32_mailbox_f(tp->napi[i].int_mbox, 1);
7436                 }
7437         } else {
7438                 tp->napi[0].tx_prod = 0;
7439                 tp->napi[0].tx_cons = 0;
7440                 tw32_mailbox(tp->napi[0].prodmbox, 0);
7441                 tw32_rx_mbox(tp->napi[0].consmbox, 0);
7442         }
7443
7444         /* Make sure the NIC-based send BD rings are disabled. */
7445         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7446                 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
7447                 for (i = 0; i < 16; i++)
7448                         tw32_tx_mbox(mbox + i * 8, 0);
7449         }
7450
7451         txrcb = NIC_SRAM_SEND_RCB;
7452         rxrcb = NIC_SRAM_RCV_RET_RCB;
7453
7454         /* Clear status block in ram. */
7455         memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7456
7457         /* Set status block DMA address */
7458         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7459              ((u64) tnapi->status_mapping >> 32));
7460         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7461              ((u64) tnapi->status_mapping & 0xffffffff));
7462
7463         if (tnapi->tx_ring) {
7464                 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7465                                (TG3_TX_RING_SIZE <<
7466                                 BDINFO_FLAGS_MAXLEN_SHIFT),
7467                                NIC_SRAM_TX_BUFFER_DESC);
7468                 txrcb += TG3_BDINFO_SIZE;
7469         }
7470
7471         if (tnapi->rx_rcb) {
7472                 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7473                                (TG3_RX_RCB_RING_SIZE(tp) <<
7474                                 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7475                 rxrcb += TG3_BDINFO_SIZE;
7476         }
7477
7478         stblk = HOSTCC_STATBLCK_RING1;
7479
7480         for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
7481                 u64 mapping = (u64)tnapi->status_mapping;
7482                 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
7483                 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
7484
7485                 /* Clear status block in ram. */
7486                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7487
7488                 if (tnapi->tx_ring) {
7489                         tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7490                                        (TG3_TX_RING_SIZE <<
7491                                         BDINFO_FLAGS_MAXLEN_SHIFT),
7492                                        NIC_SRAM_TX_BUFFER_DESC);
7493                         txrcb += TG3_BDINFO_SIZE;
7494                 }
7495
7496                 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7497                                (TG3_RX_RCB_RING_SIZE(tp) <<
7498                                 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7499
7500                 stblk += 8;
7501                 rxrcb += TG3_BDINFO_SIZE;
7502         }
7503 }
7504
7505 /* tp->lock is held. */
7506 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
7507 {
7508         u32 val, rdmac_mode;
7509         int i, err, limit;
7510         struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
7511
7512         tg3_disable_ints(tp);
7513
7514         tg3_stop_fw(tp);
7515
7516         tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
7517
7518         if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
7519                 tg3_abort_hw(tp, 1);
7520         }
7521
7522         if (reset_phy &&
7523             !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB))
7524                 tg3_phy_reset(tp);
7525
7526         err = tg3_chip_reset(tp);
7527         if (err)
7528                 return err;
7529
7530         tg3_write_sig_legacy(tp, RESET_KIND_INIT);
7531
7532         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
7533                 val = tr32(TG3_CPMU_CTRL);
7534                 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
7535                 tw32(TG3_CPMU_CTRL, val);
7536
7537                 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7538                 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7539                 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7540                 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7541
7542                 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
7543                 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
7544                 val |= CPMU_LNK_AWARE_MACCLK_6_25;
7545                 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
7546
7547                 val = tr32(TG3_CPMU_HST_ACC);
7548                 val &= ~CPMU_HST_ACC_MACCLK_MASK;
7549                 val |= CPMU_HST_ACC_MACCLK_6_25;
7550                 tw32(TG3_CPMU_HST_ACC, val);
7551         }
7552
7553         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7554                 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
7555                 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
7556                        PCIE_PWR_MGMT_L1_THRESH_4MS;
7557                 tw32(PCIE_PWR_MGMT_THRESH, val);
7558
7559                 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
7560                 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
7561
7562                 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
7563
7564                 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
7565                 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
7566         }
7567
7568         /* This works around an issue with Athlon chipsets on
7569          * B3 tigon3 silicon.  This bit has no effect on any
7570          * other revision.  But do not set this on PCI Express
7571          * chips and don't even touch the clocks if the CPMU is present.
7572          */
7573         if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
7574                 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
7575                         tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
7576                 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7577         }
7578
7579         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
7580             (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
7581                 val = tr32(TG3PCI_PCISTATE);
7582                 val |= PCISTATE_RETRY_SAME_DMA;
7583                 tw32(TG3PCI_PCISTATE, val);
7584         }
7585
7586         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
7587                 /* Allow reads and writes to the
7588                  * APE register and memory space.
7589                  */
7590                 val = tr32(TG3PCI_PCISTATE);
7591                 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
7592                        PCISTATE_ALLOW_APE_SHMEM_WR;
7593                 tw32(TG3PCI_PCISTATE, val);
7594         }
7595
7596         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
7597                 /* Enable some hw fixes.  */
7598                 val = tr32(TG3PCI_MSI_DATA);
7599                 val |= (1 << 26) | (1 << 28) | (1 << 29);
7600                 tw32(TG3PCI_MSI_DATA, val);
7601         }
7602
7603         /* Descriptor ring init may make accesses to the
7604          * NIC SRAM area to setup the TX descriptors, so we
7605          * can only do this after the hardware has been
7606          * successfully reset.
7607          */
7608         err = tg3_init_rings(tp);
7609         if (err)
7610                 return err;
7611
7612         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
7613                 val = tr32(TG3PCI_DMA_RW_CTRL) &
7614                       ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
7615                 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
7616         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
7617                    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
7618                 /* This value is determined during the probe time DMA
7619                  * engine test, tg3_test_dma.
7620                  */
7621                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
7622         }
7623
7624         tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
7625                           GRC_MODE_4X_NIC_SEND_RINGS |
7626                           GRC_MODE_NO_TX_PHDR_CSUM |
7627                           GRC_MODE_NO_RX_PHDR_CSUM);
7628         tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
7629
7630         /* Pseudo-header checksum is done by hardware logic and not
7631          * the offload processers, so make the chip do the pseudo-
7632          * header checksums on receive.  For transmit it is more
7633          * convenient to do the pseudo-header checksum in software
7634          * as Linux does that on transmit for us in all cases.
7635          */
7636         tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
7637
7638         tw32(GRC_MODE,
7639              tp->grc_mode |
7640              (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
7641
7642         /* Setup the timer prescalar register.  Clock is always 66Mhz. */
7643         val = tr32(GRC_MISC_CFG);
7644         val &= ~0xff;
7645         val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
7646         tw32(GRC_MISC_CFG, val);
7647
7648         /* Initialize MBUF/DESC pool. */
7649         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7650                 /* Do nothing.  */
7651         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
7652                 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
7653                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
7654                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
7655                 else
7656                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
7657                 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
7658                 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
7659         }
7660         else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7661                 int fw_len;
7662
7663                 fw_len = tp->fw_len;
7664                 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
7665                 tw32(BUFMGR_MB_POOL_ADDR,
7666                      NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
7667                 tw32(BUFMGR_MB_POOL_SIZE,
7668                      NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
7669         }
7670
7671         if (tp->dev->mtu <= ETH_DATA_LEN) {
7672                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7673                      tp->bufmgr_config.mbuf_read_dma_low_water);
7674                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7675                      tp->bufmgr_config.mbuf_mac_rx_low_water);
7676                 tw32(BUFMGR_MB_HIGH_WATER,
7677                      tp->bufmgr_config.mbuf_high_water);
7678         } else {
7679                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7680                      tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
7681                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7682                      tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
7683                 tw32(BUFMGR_MB_HIGH_WATER,
7684                      tp->bufmgr_config.mbuf_high_water_jumbo);
7685         }
7686         tw32(BUFMGR_DMA_LOW_WATER,
7687              tp->bufmgr_config.dma_low_water);
7688         tw32(BUFMGR_DMA_HIGH_WATER,
7689              tp->bufmgr_config.dma_high_water);
7690
7691         tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
7692         for (i = 0; i < 2000; i++) {
7693                 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
7694                         break;
7695                 udelay(10);
7696         }
7697         if (i >= 2000) {
7698                 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
7699                        tp->dev->name);
7700                 return -ENODEV;
7701         }
7702
7703         /* Setup replenish threshold. */
7704         val = tp->rx_pending / 8;
7705         if (val == 0)
7706                 val = 1;
7707         else if (val > tp->rx_std_max_post)
7708                 val = tp->rx_std_max_post;
7709         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7710                 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
7711                         tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
7712
7713                 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
7714                         val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
7715         }
7716
7717         tw32(RCVBDI_STD_THRESH, val);
7718
7719         /* Initialize TG3_BDINFO's at:
7720          *  RCVDBDI_STD_BD:     standard eth size rx ring
7721          *  RCVDBDI_JUMBO_BD:   jumbo frame rx ring
7722          *  RCVDBDI_MINI_BD:    small frame rx ring (??? does not work)
7723          *
7724          * like so:
7725          *  TG3_BDINFO_HOST_ADDR:       high/low parts of DMA address of ring
7726          *  TG3_BDINFO_MAXLEN_FLAGS:    (rx max buffer size << 16) |
7727          *                              ring attribute flags
7728          *  TG3_BDINFO_NIC_ADDR:        location of descriptors in nic SRAM
7729          *
7730          * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
7731          * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
7732          *
7733          * The size of each ring is fixed in the firmware, but the location is
7734          * configurable.
7735          */
7736         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7737              ((u64) tpr->rx_std_mapping >> 32));
7738         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7739              ((u64) tpr->rx_std_mapping & 0xffffffff));
7740         if (!(tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
7741                 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
7742                      NIC_SRAM_RX_BUFFER_DESC);
7743
7744         /* Disable the mini ring */
7745         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7746                 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
7747                      BDINFO_FLAGS_DISABLED);
7748
7749         /* Program the jumbo buffer descriptor ring control
7750          * blocks on those devices that have them.
7751          */
7752         if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
7753             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
7754                 /* Setup replenish threshold. */
7755                 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
7756
7757                 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
7758                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7759                              ((u64) tpr->rx_jmb_mapping >> 32));
7760                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7761                              ((u64) tpr->rx_jmb_mapping & 0xffffffff));
7762                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7763                              (RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT) |
7764                              BDINFO_FLAGS_USE_EXT_RECV);
7765                         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7766                                 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
7767                                      NIC_SRAM_RX_JUMBO_BUFFER_DESC);
7768                 } else {
7769                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7770                              BDINFO_FLAGS_DISABLED);
7771                 }
7772
7773                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
7774                         val = (RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT) |
7775                               (RX_STD_MAX_SIZE << 2);
7776                 else
7777                         val = RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT;
7778         } else
7779                 val = RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT;
7780
7781         tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
7782
7783         tpr->rx_std_prod_idx = tp->rx_pending;
7784         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx);
7785
7786         tpr->rx_jmb_prod_idx = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
7787                           tp->rx_jumbo_pending : 0;
7788         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx);
7789
7790         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
7791                 tw32(STD_REPLENISH_LWM, 32);
7792                 tw32(JMB_REPLENISH_LWM, 16);
7793         }
7794
7795         tg3_rings_reset(tp);
7796
7797         /* Initialize MAC address and backoff seed. */
7798         __tg3_set_mac_addr(tp, 0);
7799
7800         /* MTU + ethernet header + FCS + optional VLAN tag */
7801         tw32(MAC_RX_MTU_SIZE,
7802              tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
7803
7804         /* The slot time is changed by tg3_setup_phy if we
7805          * run at gigabit with half duplex.
7806          */
7807         tw32(MAC_TX_LENGTHS,
7808              (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
7809              (6 << TX_LENGTHS_IPG_SHIFT) |
7810              (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
7811
7812         /* Receive rules. */
7813         tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
7814         tw32(RCVLPC_CONFIG, 0x0181);
7815
7816         /* Calculate RDMAC_MODE setting early, we need it to determine
7817          * the RCVLPC_STATE_ENABLE mask.
7818          */
7819         rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
7820                       RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
7821                       RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
7822                       RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
7823                       RDMAC_MODE_LNGREAD_ENAB);
7824
7825         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
7826             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7827             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7828                 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
7829                               RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
7830                               RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
7831
7832         /* If statement applies to 5705 and 5750 PCI devices only */
7833         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7834              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7835             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
7836                 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
7837                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7838                         rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
7839                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7840                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
7841                         rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7842                 }
7843         }
7844
7845         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
7846                 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7847
7848         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7849                 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
7850
7851         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
7852             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7853             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7854                 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
7855
7856         /* Receive/send statistics. */
7857         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7858                 val = tr32(RCVLPC_STATS_ENABLE);
7859                 val &= ~RCVLPC_STATSENAB_DACK_FIX;
7860                 tw32(RCVLPC_STATS_ENABLE, val);
7861         } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
7862                    (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
7863                 val = tr32(RCVLPC_STATS_ENABLE);
7864                 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
7865                 tw32(RCVLPC_STATS_ENABLE, val);
7866         } else {
7867                 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
7868         }
7869         tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
7870         tw32(SNDDATAI_STATSENAB, 0xffffff);
7871         tw32(SNDDATAI_STATSCTRL,
7872              (SNDDATAI_SCTRL_ENABLE |
7873               SNDDATAI_SCTRL_FASTUPD));
7874
7875         /* Setup host coalescing engine. */
7876         tw32(HOSTCC_MODE, 0);
7877         for (i = 0; i < 2000; i++) {
7878                 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
7879                         break;
7880                 udelay(10);
7881         }
7882
7883         __tg3_set_coalesce(tp, &tp->coal);
7884
7885         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7886                 /* Status/statistics block address.  See tg3_timer,
7887                  * the tg3_periodic_fetch_stats call there, and
7888                  * tg3_get_stats to see how this works for 5705/5750 chips.
7889                  */
7890                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7891                      ((u64) tp->stats_mapping >> 32));
7892                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7893                      ((u64) tp->stats_mapping & 0xffffffff));
7894                 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
7895
7896                 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
7897
7898                 /* Clear statistics and status block memory areas */
7899                 for (i = NIC_SRAM_STATS_BLK;
7900                      i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
7901                      i += sizeof(u32)) {
7902                         tg3_write_mem(tp, i, 0);
7903                         udelay(40);
7904                 }
7905         }
7906
7907         tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
7908
7909         tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
7910         tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
7911         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7912                 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
7913
7914         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
7915                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
7916                 /* reset to prevent losing 1st rx packet intermittently */
7917                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7918                 udelay(10);
7919         }
7920
7921         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7922                 tp->mac_mode &= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
7923         else
7924                 tp->mac_mode = 0;
7925         tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
7926                 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
7927         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7928             !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7929             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
7930                 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
7931         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
7932         udelay(40);
7933
7934         /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
7935          * If TG3_FLG2_IS_NIC is zero, we should read the
7936          * register to preserve the GPIO settings for LOMs. The GPIOs,
7937          * whether used as inputs or outputs, are set by boot code after
7938          * reset.
7939          */
7940         if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
7941                 u32 gpio_mask;
7942
7943                 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
7944                             GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
7945                             GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
7946
7947                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
7948                         gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
7949                                      GRC_LCLCTRL_GPIO_OUTPUT3;
7950
7951                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
7952                         gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
7953
7954                 tp->grc_local_ctrl &= ~gpio_mask;
7955                 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
7956
7957                 /* GPIO1 must be driven high for eeprom write protect */
7958                 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
7959                         tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
7960                                                GRC_LCLCTRL_GPIO_OUTPUT1);
7961         }
7962         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7963         udelay(100);
7964
7965         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX) {
7966                 val = tr32(MSGINT_MODE);
7967                 val |= MSGINT_MODE_MULTIVEC_EN | MSGINT_MODE_ENABLE;
7968                 tw32(MSGINT_MODE, val);
7969         }
7970
7971         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7972                 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
7973                 udelay(40);
7974         }
7975
7976         val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
7977                WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
7978                WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
7979                WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
7980                WDMAC_MODE_LNGREAD_ENAB);
7981
7982         /* If statement applies to 5705 and 5750 PCI devices only */
7983         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7984              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7985             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
7986                 if ((tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
7987                     (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
7988                      tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
7989                         /* nothing */
7990                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7991                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
7992                            !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
7993                         val |= WDMAC_MODE_RX_ACCEL;
7994                 }
7995         }
7996
7997         /* Enable host coalescing bug fix */
7998         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
7999                 val |= WDMAC_MODE_STATUS_TAG_FIX;
8000
8001         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
8002                 val |= WDMAC_MODE_BURST_ALL_DATA;
8003
8004         tw32_f(WDMAC_MODE, val);
8005         udelay(40);
8006
8007         if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
8008                 u16 pcix_cmd;
8009
8010                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8011                                      &pcix_cmd);
8012                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
8013                         pcix_cmd &= ~PCI_X_CMD_MAX_READ;
8014                         pcix_cmd |= PCI_X_CMD_READ_2K;
8015                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
8016                         pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
8017                         pcix_cmd |= PCI_X_CMD_READ_2K;
8018                 }
8019                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8020                                       pcix_cmd);
8021         }
8022
8023         tw32_f(RDMAC_MODE, rdmac_mode);
8024         udelay(40);
8025
8026         tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
8027         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8028                 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
8029
8030         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
8031                 tw32(SNDDATAC_MODE,
8032                      SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
8033         else
8034                 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
8035
8036         tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
8037         tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
8038         tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
8039         tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
8040         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
8041                 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
8042         val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
8043         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
8044                 val |= SNDBDI_MODE_MULTI_TXQ_EN;
8045         tw32(SNDBDI_MODE, val);
8046         tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
8047
8048         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8049                 err = tg3_load_5701_a0_firmware_fix(tp);
8050                 if (err)
8051                         return err;
8052         }
8053
8054         if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
8055                 err = tg3_load_tso_firmware(tp);
8056                 if (err)
8057                         return err;
8058         }
8059
8060         tp->tx_mode = TX_MODE_ENABLE;
8061         tw32_f(MAC_TX_MODE, tp->tx_mode);
8062         udelay(100);
8063
8064         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) {
8065                 u32 reg = MAC_RSS_INDIR_TBL_0;
8066                 u8 *ent = (u8 *)&val;
8067
8068                 /* Setup the indirection table */
8069                 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
8070                         int idx = i % sizeof(val);
8071
8072                         ent[idx] = i % (tp->irq_cnt - 1);
8073                         if (idx == sizeof(val) - 1) {
8074                                 tw32(reg, val);
8075                                 reg += 4;
8076                         }
8077                 }
8078
8079                 /* Setup the "secret" hash key. */
8080                 tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
8081                 tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
8082                 tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
8083                 tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
8084                 tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
8085                 tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
8086                 tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
8087                 tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
8088                 tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
8089                 tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
8090         }
8091
8092         tp->rx_mode = RX_MODE_ENABLE;
8093         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
8094                 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
8095
8096         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)
8097                 tp->rx_mode |= RX_MODE_RSS_ENABLE |
8098                                RX_MODE_RSS_ITBL_HASH_BITS_7 |
8099                                RX_MODE_RSS_IPV6_HASH_EN |
8100                                RX_MODE_RSS_TCP_IPV6_HASH_EN |
8101                                RX_MODE_RSS_IPV4_HASH_EN |
8102                                RX_MODE_RSS_TCP_IPV4_HASH_EN;
8103
8104         tw32_f(MAC_RX_MODE, tp->rx_mode);
8105         udelay(10);
8106
8107         tw32(MAC_LED_CTRL, tp->led_ctrl);
8108
8109         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
8110         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
8111                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8112                 udelay(10);
8113         }
8114         tw32_f(MAC_RX_MODE, tp->rx_mode);
8115         udelay(10);
8116
8117         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
8118                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
8119                         !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
8120                         /* Set drive transmission level to 1.2V  */
8121                         /* only if the signal pre-emphasis bit is not set  */
8122                         val = tr32(MAC_SERDES_CFG);
8123                         val &= 0xfffff000;
8124                         val |= 0x880;
8125                         tw32(MAC_SERDES_CFG, val);
8126                 }
8127                 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
8128                         tw32(MAC_SERDES_CFG, 0x616000);
8129         }
8130
8131         /* Prevent chip from dropping frames when flow control
8132          * is enabled.
8133          */
8134         tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
8135
8136         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
8137             (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
8138                 /* Use hardware link auto-negotiation */
8139                 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
8140         }
8141
8142         if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
8143             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
8144                 u32 tmp;
8145
8146                 tmp = tr32(SERDES_RX_CTRL);
8147                 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
8148                 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
8149                 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
8150                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8151         }
8152
8153         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
8154                 if (tp->link_config.phy_is_low_power) {
8155                         tp->link_config.phy_is_low_power = 0;
8156                         tp->link_config.speed = tp->link_config.orig_speed;
8157                         tp->link_config.duplex = tp->link_config.orig_duplex;
8158                         tp->link_config.autoneg = tp->link_config.orig_autoneg;
8159                 }
8160
8161                 err = tg3_setup_phy(tp, 0);
8162                 if (err)
8163                         return err;
8164
8165                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
8166                     !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)) {
8167                         u32 tmp;
8168
8169                         /* Clear CRC stats. */
8170                         if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
8171                                 tg3_writephy(tp, MII_TG3_TEST1,
8172                                              tmp | MII_TG3_TEST1_CRC_EN);
8173                                 tg3_readphy(tp, 0x14, &tmp);
8174                         }
8175                 }
8176         }
8177
8178         __tg3_set_rx_mode(tp->dev);
8179
8180         /* Initialize receive rules. */
8181         tw32(MAC_RCV_RULE_0,  0xc2000000 & RCV_RULE_DISABLE_MASK);
8182         tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
8183         tw32(MAC_RCV_RULE_1,  0x86000004 & RCV_RULE_DISABLE_MASK);
8184         tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
8185
8186         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
8187             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
8188                 limit = 8;
8189         else
8190                 limit = 16;
8191         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
8192                 limit -= 4;
8193         switch (limit) {
8194         case 16:
8195                 tw32(MAC_RCV_RULE_15,  0); tw32(MAC_RCV_VALUE_15,  0);
8196         case 15:
8197                 tw32(MAC_RCV_RULE_14,  0); tw32(MAC_RCV_VALUE_14,  0);
8198         case 14:
8199                 tw32(MAC_RCV_RULE_13,  0); tw32(MAC_RCV_VALUE_13,  0);
8200         case 13:
8201                 tw32(MAC_RCV_RULE_12,  0); tw32(MAC_RCV_VALUE_12,  0);
8202         case 12:
8203                 tw32(MAC_RCV_RULE_11,  0); tw32(MAC_RCV_VALUE_11,  0);
8204         case 11:
8205                 tw32(MAC_RCV_RULE_10,  0); tw32(MAC_RCV_VALUE_10,  0);
8206         case 10:
8207                 tw32(MAC_RCV_RULE_9,  0); tw32(MAC_RCV_VALUE_9,  0);
8208         case 9:
8209                 tw32(MAC_RCV_RULE_8,  0); tw32(MAC_RCV_VALUE_8,  0);
8210         case 8:
8211                 tw32(MAC_RCV_RULE_7,  0); tw32(MAC_RCV_VALUE_7,  0);
8212         case 7:
8213                 tw32(MAC_RCV_RULE_6,  0); tw32(MAC_RCV_VALUE_6,  0);
8214         case 6:
8215                 tw32(MAC_RCV_RULE_5,  0); tw32(MAC_RCV_VALUE_5,  0);
8216         case 5:
8217                 tw32(MAC_RCV_RULE_4,  0); tw32(MAC_RCV_VALUE_4,  0);
8218         case 4:
8219                 /* tw32(MAC_RCV_RULE_3,  0); tw32(MAC_RCV_VALUE_3,  0); */
8220         case 3:
8221                 /* tw32(MAC_RCV_RULE_2,  0); tw32(MAC_RCV_VALUE_2,  0); */
8222         case 2:
8223         case 1:
8224
8225         default:
8226                 break;
8227         }
8228
8229         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
8230                 /* Write our heartbeat update interval to APE. */
8231                 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
8232                                 APE_HOST_HEARTBEAT_INT_DISABLE);
8233
8234         tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
8235
8236         return 0;
8237 }
8238
8239 /* Called at device open time to get the chip ready for
8240  * packet processing.  Invoked with tp->lock held.
8241  */
8242 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
8243 {
8244         tg3_switch_clocks(tp);
8245
8246         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
8247
8248         return tg3_reset_hw(tp, reset_phy);
8249 }
8250
8251 #define TG3_STAT_ADD32(PSTAT, REG) \
8252 do {    u32 __val = tr32(REG); \
8253         (PSTAT)->low += __val; \
8254         if ((PSTAT)->low < __val) \
8255                 (PSTAT)->high += 1; \
8256 } while (0)
8257
8258 static void tg3_periodic_fetch_stats(struct tg3 *tp)
8259 {
8260         struct tg3_hw_stats *sp = tp->hw_stats;
8261
8262         if (!netif_carrier_ok(tp->dev))
8263                 return;
8264
8265         TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
8266         TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
8267         TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
8268         TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
8269         TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
8270         TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
8271         TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
8272         TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
8273         TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
8274         TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
8275         TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
8276         TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
8277         TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
8278
8279         TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
8280         TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
8281         TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
8282         TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
8283         TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
8284         TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
8285         TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
8286         TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
8287         TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
8288         TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
8289         TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
8290         TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
8291         TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
8292         TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
8293
8294         TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
8295         TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
8296         TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
8297 }
8298
8299 static void tg3_timer(unsigned long __opaque)
8300 {
8301         struct tg3 *tp = (struct tg3 *) __opaque;
8302
8303         if (tp->irq_sync)
8304                 goto restart_timer;
8305
8306         spin_lock(&tp->lock);
8307
8308         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8309                 /* All of this garbage is because when using non-tagged
8310                  * IRQ status the mailbox/status_block protocol the chip
8311                  * uses with the cpu is race prone.
8312                  */
8313                 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
8314                         tw32(GRC_LOCAL_CTRL,
8315                              tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
8316                 } else {
8317                         tw32(HOSTCC_MODE, tp->coalesce_mode |
8318                              HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
8319                 }
8320
8321                 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
8322                         tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
8323                         spin_unlock(&tp->lock);
8324                         schedule_work(&tp->reset_task);
8325                         return;
8326                 }
8327         }
8328
8329         /* This part only runs once per second. */
8330         if (!--tp->timer_counter) {
8331                 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
8332                         tg3_periodic_fetch_stats(tp);
8333
8334                 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
8335                         u32 mac_stat;
8336                         int phy_event;
8337
8338                         mac_stat = tr32(MAC_STATUS);
8339
8340                         phy_event = 0;
8341                         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
8342                                 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
8343                                         phy_event = 1;
8344                         } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
8345                                 phy_event = 1;
8346
8347                         if (phy_event)
8348                                 tg3_setup_phy(tp, 0);
8349                 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
8350                         u32 mac_stat = tr32(MAC_STATUS);
8351                         int need_setup = 0;
8352
8353                         if (netif_carrier_ok(tp->dev) &&
8354                             (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
8355                                 need_setup = 1;
8356                         }
8357                         if (! netif_carrier_ok(tp->dev) &&
8358                             (mac_stat & (MAC_STATUS_PCS_SYNCED |
8359                                          MAC_STATUS_SIGNAL_DET))) {
8360                                 need_setup = 1;
8361                         }
8362                         if (need_setup) {
8363                                 if (!tp->serdes_counter) {
8364                                         tw32_f(MAC_MODE,
8365                                              (tp->mac_mode &
8366                                               ~MAC_MODE_PORT_MODE_MASK));
8367                                         udelay(40);
8368                                         tw32_f(MAC_MODE, tp->mac_mode);
8369                                         udelay(40);
8370                                 }
8371                                 tg3_setup_phy(tp, 0);
8372                         }
8373                 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
8374                         tg3_serdes_parallel_detect(tp);
8375
8376                 tp->timer_counter = tp->timer_multiplier;
8377         }
8378
8379         /* Heartbeat is only sent once every 2 seconds.
8380          *
8381          * The heartbeat is to tell the ASF firmware that the host
8382          * driver is still alive.  In the event that the OS crashes,
8383          * ASF needs to reset the hardware to free up the FIFO space
8384          * that may be filled with rx packets destined for the host.
8385          * If the FIFO is full, ASF will no longer function properly.
8386          *
8387          * Unintended resets have been reported on real time kernels
8388          * where the timer doesn't run on time.  Netpoll will also have
8389          * same problem.
8390          *
8391          * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
8392          * to check the ring condition when the heartbeat is expiring
8393          * before doing the reset.  This will prevent most unintended
8394          * resets.
8395          */
8396         if (!--tp->asf_counter) {
8397                 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
8398                     !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
8399                         tg3_wait_for_event_ack(tp);
8400
8401                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
8402                                       FWCMD_NICDRV_ALIVE3);
8403                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
8404                         /* 5 seconds timeout */
8405                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
8406
8407                         tg3_generate_fw_event(tp);
8408                 }
8409                 tp->asf_counter = tp->asf_multiplier;
8410         }
8411
8412         spin_unlock(&tp->lock);
8413
8414 restart_timer:
8415         tp->timer.expires = jiffies + tp->timer_offset;
8416         add_timer(&tp->timer);
8417 }
8418
8419 static int tg3_request_irq(struct tg3 *tp, int irq_num)
8420 {
8421         irq_handler_t fn;
8422         unsigned long flags;
8423         char *name;
8424         struct tg3_napi *tnapi = &tp->napi[irq_num];
8425
8426         if (tp->irq_cnt == 1)
8427                 name = tp->dev->name;
8428         else {
8429                 name = &tnapi->irq_lbl[0];
8430                 snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num);
8431                 name[IFNAMSIZ-1] = 0;
8432         }
8433
8434         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8435                 fn = tg3_msi;
8436                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
8437                         fn = tg3_msi_1shot;
8438                 flags = IRQF_SAMPLE_RANDOM;
8439         } else {
8440                 fn = tg3_interrupt;
8441                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8442                         fn = tg3_interrupt_tagged;
8443                 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
8444         }
8445
8446         return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
8447 }
8448
8449 static int tg3_test_interrupt(struct tg3 *tp)
8450 {
8451         struct tg3_napi *tnapi = &tp->napi[0];
8452         struct net_device *dev = tp->dev;
8453         int err, i, intr_ok = 0;
8454         u32 val;
8455
8456         if (!netif_running(dev))
8457                 return -ENODEV;
8458
8459         tg3_disable_ints(tp);
8460
8461         free_irq(tnapi->irq_vec, tnapi);
8462
8463         /*
8464          * Turn off MSI one shot mode.  Otherwise this test has no
8465          * observable way to know whether the interrupt was delivered.
8466          */
8467         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
8468             (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8469                 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
8470                 tw32(MSGINT_MODE, val);
8471         }
8472
8473         err = request_irq(tnapi->irq_vec, tg3_test_isr,
8474                           IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi);
8475         if (err)
8476                 return err;
8477
8478         tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
8479         tg3_enable_ints(tp);
8480
8481         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8482                tnapi->coal_now);
8483
8484         for (i = 0; i < 5; i++) {
8485                 u32 int_mbox, misc_host_ctrl;
8486
8487                 int_mbox = tr32_mailbox(tnapi->int_mbox);
8488                 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
8489
8490                 if ((int_mbox != 0) ||
8491                     (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
8492                         intr_ok = 1;
8493                         break;
8494                 }
8495
8496                 msleep(10);
8497         }
8498
8499         tg3_disable_ints(tp);
8500
8501         free_irq(tnapi->irq_vec, tnapi);
8502
8503         err = tg3_request_irq(tp, 0);
8504
8505         if (err)
8506                 return err;
8507
8508         if (intr_ok) {
8509                 /* Reenable MSI one shot mode. */
8510                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
8511                     (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8512                         val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
8513                         tw32(MSGINT_MODE, val);
8514                 }
8515                 return 0;
8516         }
8517
8518         return -EIO;
8519 }
8520
8521 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
8522  * successfully restored
8523  */
8524 static int tg3_test_msi(struct tg3 *tp)
8525 {
8526         int err;
8527         u16 pci_cmd;
8528
8529         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
8530                 return 0;
8531
8532         /* Turn off SERR reporting in case MSI terminates with Master
8533          * Abort.
8534          */
8535         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
8536         pci_write_config_word(tp->pdev, PCI_COMMAND,
8537                               pci_cmd & ~PCI_COMMAND_SERR);
8538
8539         err = tg3_test_interrupt(tp);
8540
8541         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
8542
8543         if (!err)
8544                 return 0;
8545
8546         /* other failures */
8547         if (err != -EIO)
8548                 return err;
8549
8550         /* MSI test failed, go back to INTx mode */
8551         printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
8552                "switching to INTx mode. Please report this failure to "
8553                "the PCI maintainer and include system chipset information.\n",
8554                        tp->dev->name);
8555
8556         free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8557
8558         pci_disable_msi(tp->pdev);
8559
8560         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8561
8562         err = tg3_request_irq(tp, 0);
8563         if (err)
8564                 return err;
8565
8566         /* Need to reset the chip because the MSI cycle may have terminated
8567          * with Master Abort.
8568          */
8569         tg3_full_lock(tp, 1);
8570
8571         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8572         err = tg3_init_hw(tp, 1);
8573
8574         tg3_full_unlock(tp);
8575
8576         if (err)
8577                 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8578
8579         return err;
8580 }
8581
8582 static int tg3_request_firmware(struct tg3 *tp)
8583 {
8584         const __be32 *fw_data;
8585
8586         if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
8587                 printk(KERN_ERR "%s: Failed to load firmware \"%s\"\n",
8588                        tp->dev->name, tp->fw_needed);
8589                 return -ENOENT;
8590         }
8591
8592         fw_data = (void *)tp->fw->data;
8593
8594         /* Firmware blob starts with version numbers, followed by
8595          * start address and _full_ length including BSS sections
8596          * (which must be longer than the actual data, of course
8597          */
8598
8599         tp->fw_len = be32_to_cpu(fw_data[2]);   /* includes bss */
8600         if (tp->fw_len < (tp->fw->size - 12)) {
8601                 printk(KERN_ERR "%s: bogus length %d in \"%s\"\n",
8602                        tp->dev->name, tp->fw_len, tp->fw_needed);
8603                 release_firmware(tp->fw);
8604                 tp->fw = NULL;
8605                 return -EINVAL;
8606         }
8607
8608         /* We no longer need firmware; we have it. */
8609         tp->fw_needed = NULL;
8610         return 0;
8611 }
8612
8613 static bool tg3_enable_msix(struct tg3 *tp)
8614 {
8615         int i, rc, cpus = num_online_cpus();
8616         struct msix_entry msix_ent[tp->irq_max];
8617
8618         if (cpus == 1)
8619                 /* Just fallback to the simpler MSI mode. */
8620                 return false;
8621
8622         /*
8623          * We want as many rx rings enabled as there are cpus.
8624          * The first MSIX vector only deals with link interrupts, etc,
8625          * so we add one to the number of vectors we are requesting.
8626          */
8627         tp->irq_cnt = min_t(unsigned, cpus + 1, tp->irq_max);
8628
8629         for (i = 0; i < tp->irq_max; i++) {
8630                 msix_ent[i].entry  = i;
8631                 msix_ent[i].vector = 0;
8632         }
8633
8634         rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
8635         if (rc != 0) {
8636                 if (rc < TG3_RSS_MIN_NUM_MSIX_VECS)
8637                         return false;
8638                 if (pci_enable_msix(tp->pdev, msix_ent, rc))
8639                         return false;
8640                 printk(KERN_NOTICE
8641                        "%s: Requested %d MSI-X vectors, received %d\n",
8642                        tp->dev->name, tp->irq_cnt, rc);
8643                 tp->irq_cnt = rc;
8644         }
8645
8646         tp->tg3_flags3 |= TG3_FLG3_ENABLE_RSS;
8647
8648         for (i = 0; i < tp->irq_max; i++)
8649                 tp->napi[i].irq_vec = msix_ent[i].vector;
8650
8651         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
8652                 tp->tg3_flags3 |= TG3_FLG3_ENABLE_TSS;
8653                 tp->dev->real_num_tx_queues = tp->irq_cnt - 1;
8654         } else
8655                 tp->dev->real_num_tx_queues = 1;
8656
8657         return true;
8658 }
8659
8660 static void tg3_ints_init(struct tg3 *tp)
8661 {
8662         if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI_OR_MSIX) &&
8663             !(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8664                 /* All MSI supporting chips should support tagged
8665                  * status.  Assert that this is the case.
8666                  */
8667                 printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
8668                        "Not using MSI.\n", tp->dev->name);
8669                 goto defcfg;
8670         }
8671
8672         if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) && tg3_enable_msix(tp))
8673                 tp->tg3_flags2 |= TG3_FLG2_USING_MSIX;
8674         else if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) &&
8675                  pci_enable_msi(tp->pdev) == 0)
8676                 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
8677
8678         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8679                 u32 msi_mode = tr32(MSGINT_MODE);
8680                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8681                         msi_mode |= MSGINT_MODE_MULTIVEC_EN;
8682                 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
8683         }
8684 defcfg:
8685         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
8686                 tp->irq_cnt = 1;
8687                 tp->napi[0].irq_vec = tp->pdev->irq;
8688                 tp->dev->real_num_tx_queues = 1;
8689         }
8690 }
8691
8692 static void tg3_ints_fini(struct tg3 *tp)
8693 {
8694         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8695                 pci_disable_msix(tp->pdev);
8696         else if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
8697                 pci_disable_msi(tp->pdev);
8698         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI_OR_MSIX;
8699         tp->tg3_flags3 &= ~TG3_FLG3_ENABLE_RSS;
8700 }
8701
8702 static int tg3_open(struct net_device *dev)
8703 {
8704         struct tg3 *tp = netdev_priv(dev);
8705         int i, err;
8706
8707         if (tp->fw_needed) {
8708                 err = tg3_request_firmware(tp);
8709                 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8710                         if (err)
8711                                 return err;
8712                 } else if (err) {
8713                         printk(KERN_WARNING "%s: TSO capability disabled.\n",
8714                                tp->dev->name);
8715                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
8716                 } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8717                         printk(KERN_NOTICE "%s: TSO capability restored.\n",
8718                                tp->dev->name);
8719                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
8720                 }
8721         }
8722
8723         netif_carrier_off(tp->dev);
8724
8725         err = tg3_set_power_state(tp, PCI_D0);
8726         if (err)
8727                 return err;
8728
8729         tg3_full_lock(tp, 0);
8730
8731         tg3_disable_ints(tp);
8732         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
8733
8734         tg3_full_unlock(tp);
8735
8736         /*
8737          * Setup interrupts first so we know how
8738          * many NAPI resources to allocate
8739          */
8740         tg3_ints_init(tp);
8741
8742         /* The placement of this call is tied
8743          * to the setup and use of Host TX descriptors.
8744          */
8745         err = tg3_alloc_consistent(tp);
8746         if (err)
8747                 goto err_out1;
8748
8749         tg3_napi_enable(tp);
8750
8751         for (i = 0; i < tp->irq_cnt; i++) {
8752                 struct tg3_napi *tnapi = &tp->napi[i];
8753                 err = tg3_request_irq(tp, i);
8754                 if (err) {
8755                         for (i--; i >= 0; i--)
8756                                 free_irq(tnapi->irq_vec, tnapi);
8757                         break;
8758                 }
8759         }
8760
8761         if (err)
8762                 goto err_out2;
8763
8764         tg3_full_lock(tp, 0);
8765
8766         err = tg3_init_hw(tp, 1);
8767         if (err) {
8768                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8769                 tg3_free_rings(tp);
8770         } else {
8771                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8772                         tp->timer_offset = HZ;
8773                 else
8774                         tp->timer_offset = HZ / 10;
8775
8776                 BUG_ON(tp->timer_offset > HZ);
8777                 tp->timer_counter = tp->timer_multiplier =
8778                         (HZ / tp->timer_offset);
8779                 tp->asf_counter = tp->asf_multiplier =
8780                         ((HZ / tp->timer_offset) * 2);
8781
8782                 init_timer(&tp->timer);
8783                 tp->timer.expires = jiffies + tp->timer_offset;
8784                 tp->timer.data = (unsigned long) tp;
8785                 tp->timer.function = tg3_timer;
8786         }
8787
8788         tg3_full_unlock(tp);
8789
8790         if (err)
8791                 goto err_out3;
8792
8793         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8794                 err = tg3_test_msi(tp);
8795
8796                 if (err) {
8797                         tg3_full_lock(tp, 0);
8798                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8799                         tg3_free_rings(tp);
8800                         tg3_full_unlock(tp);
8801
8802                         goto err_out2;
8803                 }
8804
8805                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
8806                     (tp->tg3_flags2 & TG3_FLG2_USING_MSI) &&
8807                     (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)) {
8808                         u32 val = tr32(PCIE_TRANSACTION_CFG);
8809
8810                         tw32(PCIE_TRANSACTION_CFG,
8811                              val | PCIE_TRANS_CFG_1SHOT_MSI);
8812                 }
8813         }
8814
8815         tg3_phy_start(tp);
8816
8817         tg3_full_lock(tp, 0);
8818
8819         add_timer(&tp->timer);
8820         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
8821         tg3_enable_ints(tp);
8822
8823         tg3_full_unlock(tp);
8824
8825         netif_tx_start_all_queues(dev);
8826
8827         return 0;
8828
8829 err_out3:
8830         for (i = tp->irq_cnt - 1; i >= 0; i--) {
8831                 struct tg3_napi *tnapi = &tp->napi[i];
8832                 free_irq(tnapi->irq_vec, tnapi);
8833         }
8834
8835 err_out2:
8836         tg3_napi_disable(tp);
8837         tg3_free_consistent(tp);
8838
8839 err_out1:
8840         tg3_ints_fini(tp);
8841         return err;
8842 }
8843
8844 #if 0
8845 /*static*/ void tg3_dump_state(struct tg3 *tp)
8846 {
8847         u32 val32, val32_2, val32_3, val32_4, val32_5;
8848         u16 val16;
8849         int i;
8850         struct tg3_hw_status *sblk = tp->napi[0]->hw_status;
8851
8852         pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
8853         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
8854         printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
8855                val16, val32);
8856
8857         /* MAC block */
8858         printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
8859                tr32(MAC_MODE), tr32(MAC_STATUS));
8860         printk("       MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
8861                tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
8862         printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
8863                tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
8864         printk("       MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
8865                tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
8866
8867         /* Send data initiator control block */
8868         printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
8869                tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
8870         printk("       SNDDATAI_STATSCTRL[%08x]\n",
8871                tr32(SNDDATAI_STATSCTRL));
8872
8873         /* Send data completion control block */
8874         printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
8875
8876         /* Send BD ring selector block */
8877         printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
8878                tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
8879
8880         /* Send BD initiator control block */
8881         printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
8882                tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
8883
8884         /* Send BD completion control block */
8885         printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
8886
8887         /* Receive list placement control block */
8888         printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
8889                tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
8890         printk("       RCVLPC_STATSCTRL[%08x]\n",
8891                tr32(RCVLPC_STATSCTRL));
8892
8893         /* Receive data and receive BD initiator control block */
8894         printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
8895                tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
8896
8897         /* Receive data completion control block */
8898         printk("DEBUG: RCVDCC_MODE[%08x]\n",
8899                tr32(RCVDCC_MODE));
8900
8901         /* Receive BD initiator control block */
8902         printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
8903                tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
8904
8905         /* Receive BD completion control block */
8906         printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
8907                tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
8908
8909         /* Receive list selector control block */
8910         printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
8911                tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
8912
8913         /* Mbuf cluster free block */
8914         printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
8915                tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
8916
8917         /* Host coalescing control block */
8918         printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
8919                tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
8920         printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
8921                tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8922                tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8923         printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
8924                tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8925                tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8926         printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
8927                tr32(HOSTCC_STATS_BLK_NIC_ADDR));
8928         printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
8929                tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
8930
8931         /* Memory arbiter control block */
8932         printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
8933                tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
8934
8935         /* Buffer manager control block */
8936         printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
8937                tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
8938         printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
8939                tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
8940         printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
8941                "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
8942                tr32(BUFMGR_DMA_DESC_POOL_ADDR),
8943                tr32(BUFMGR_DMA_DESC_POOL_SIZE));
8944
8945         /* Read DMA control block */
8946         printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
8947                tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
8948
8949         /* Write DMA control block */
8950         printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
8951                tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
8952
8953         /* DMA completion block */
8954         printk("DEBUG: DMAC_MODE[%08x]\n",
8955                tr32(DMAC_MODE));
8956
8957         /* GRC block */
8958         printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
8959                tr32(GRC_MODE), tr32(GRC_MISC_CFG));
8960         printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
8961                tr32(GRC_LOCAL_CTRL));
8962
8963         /* TG3_BDINFOs */
8964         printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
8965                tr32(RCVDBDI_JUMBO_BD + 0x0),
8966                tr32(RCVDBDI_JUMBO_BD + 0x4),
8967                tr32(RCVDBDI_JUMBO_BD + 0x8),
8968                tr32(RCVDBDI_JUMBO_BD + 0xc));
8969         printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
8970                tr32(RCVDBDI_STD_BD + 0x0),
8971                tr32(RCVDBDI_STD_BD + 0x4),
8972                tr32(RCVDBDI_STD_BD + 0x8),
8973                tr32(RCVDBDI_STD_BD + 0xc));
8974         printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
8975                tr32(RCVDBDI_MINI_BD + 0x0),
8976                tr32(RCVDBDI_MINI_BD + 0x4),
8977                tr32(RCVDBDI_MINI_BD + 0x8),
8978                tr32(RCVDBDI_MINI_BD + 0xc));
8979
8980         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
8981         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
8982         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
8983         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
8984         printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
8985                val32, val32_2, val32_3, val32_4);
8986
8987         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
8988         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
8989         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
8990         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
8991         printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
8992                val32, val32_2, val32_3, val32_4);
8993
8994         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
8995         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
8996         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
8997         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
8998         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
8999         printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
9000                val32, val32_2, val32_3, val32_4, val32_5);
9001
9002         /* SW status block */
9003         printk(KERN_DEBUG
9004          "Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
9005                sblk->status,
9006                sblk->status_tag,
9007                sblk->rx_jumbo_consumer,
9008                sblk->rx_consumer,
9009                sblk->rx_mini_consumer,
9010                sblk->idx[0].rx_producer,
9011                sblk->idx[0].tx_consumer);
9012
9013         /* SW statistics block */
9014         printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
9015                ((u32 *)tp->hw_stats)[0],
9016                ((u32 *)tp->hw_stats)[1],
9017                ((u32 *)tp->hw_stats)[2],
9018                ((u32 *)tp->hw_stats)[3]);
9019
9020         /* Mailboxes */
9021         printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
9022                tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
9023                tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
9024                tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
9025                tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
9026
9027         /* NIC side send descriptors. */
9028         for (i = 0; i < 6; i++) {
9029                 unsigned long txd;
9030
9031                 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
9032                         + (i * sizeof(struct tg3_tx_buffer_desc));
9033                 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
9034                        i,
9035                        readl(txd + 0x0), readl(txd + 0x4),
9036                        readl(txd + 0x8), readl(txd + 0xc));
9037         }
9038
9039         /* NIC side RX descriptors. */
9040         for (i = 0; i < 6; i++) {
9041                 unsigned long rxd;
9042
9043                 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
9044                         + (i * sizeof(struct tg3_rx_buffer_desc));
9045                 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
9046                        i,
9047                        readl(rxd + 0x0), readl(rxd + 0x4),
9048                        readl(rxd + 0x8), readl(rxd + 0xc));
9049                 rxd += (4 * sizeof(u32));
9050                 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
9051                        i,
9052                        readl(rxd + 0x0), readl(rxd + 0x4),
9053                        readl(rxd + 0x8), readl(rxd + 0xc));
9054         }
9055
9056         for (i = 0; i < 6; i++) {
9057                 unsigned long rxd;
9058
9059                 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
9060                         + (i * sizeof(struct tg3_rx_buffer_desc));
9061                 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
9062                        i,
9063                        readl(rxd + 0x0), readl(rxd + 0x4),
9064                        readl(rxd + 0x8), readl(rxd + 0xc));
9065                 rxd += (4 * sizeof(u32));
9066                 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
9067                        i,
9068                        readl(rxd + 0x0), readl(rxd + 0x4),
9069                        readl(rxd + 0x8), readl(rxd + 0xc));
9070         }
9071 }
9072 #endif
9073
9074 static struct net_device_stats *tg3_get_stats(struct net_device *);
9075 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
9076
9077 static int tg3_close(struct net_device *dev)
9078 {
9079         int i;
9080         struct tg3 *tp = netdev_priv(dev);
9081
9082         tg3_napi_disable(tp);
9083         cancel_work_sync(&tp->reset_task);
9084
9085         netif_tx_stop_all_queues(dev);
9086
9087         del_timer_sync(&tp->timer);
9088
9089         tg3_phy_stop(tp);
9090
9091         tg3_full_lock(tp, 1);
9092 #if 0
9093         tg3_dump_state(tp);
9094 #endif
9095
9096         tg3_disable_ints(tp);
9097
9098         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9099         tg3_free_rings(tp);
9100         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
9101
9102         tg3_full_unlock(tp);
9103
9104         for (i = tp->irq_cnt - 1; i >= 0; i--) {
9105                 struct tg3_napi *tnapi = &tp->napi[i];
9106                 free_irq(tnapi->irq_vec, tnapi);
9107         }
9108
9109         tg3_ints_fini(tp);
9110
9111         memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
9112                sizeof(tp->net_stats_prev));
9113         memcpy(&tp->estats_prev, tg3_get_estats(tp),
9114                sizeof(tp->estats_prev));
9115
9116         tg3_free_consistent(tp);
9117
9118         tg3_set_power_state(tp, PCI_D3hot);
9119
9120         netif_carrier_off(tp->dev);
9121
9122         return 0;
9123 }
9124
9125 static inline unsigned long get_stat64(tg3_stat64_t *val)
9126 {
9127         unsigned long ret;
9128
9129 #if (BITS_PER_LONG == 32)
9130         ret = val->low;
9131 #else
9132         ret = ((u64)val->high << 32) | ((u64)val->low);
9133 #endif
9134         return ret;
9135 }
9136
9137 static inline u64 get_estat64(tg3_stat64_t *val)
9138 {
9139        return ((u64)val->high << 32) | ((u64)val->low);
9140 }
9141
9142 static unsigned long calc_crc_errors(struct tg3 *tp)
9143 {
9144         struct tg3_hw_stats *hw_stats = tp->hw_stats;
9145
9146         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
9147             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
9148              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
9149                 u32 val;
9150
9151                 spin_lock_bh(&tp->lock);
9152                 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
9153                         tg3_writephy(tp, MII_TG3_TEST1,
9154                                      val | MII_TG3_TEST1_CRC_EN);
9155                         tg3_readphy(tp, 0x14, &val);
9156                 } else
9157                         val = 0;
9158                 spin_unlock_bh(&tp->lock);
9159
9160                 tp->phy_crc_errors += val;
9161
9162                 return tp->phy_crc_errors;
9163         }
9164
9165         return get_stat64(&hw_stats->rx_fcs_errors);
9166 }
9167
9168 #define ESTAT_ADD(member) \
9169         estats->member =        old_estats->member + \
9170                                 get_estat64(&hw_stats->member)
9171
9172 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
9173 {
9174         struct tg3_ethtool_stats *estats = &tp->estats;
9175         struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
9176         struct tg3_hw_stats *hw_stats = tp->hw_stats;
9177
9178         if (!hw_stats)
9179                 return old_estats;
9180
9181         ESTAT_ADD(rx_octets);
9182         ESTAT_ADD(rx_fragments);
9183         ESTAT_ADD(rx_ucast_packets);
9184         ESTAT_ADD(rx_mcast_packets);
9185         ESTAT_ADD(rx_bcast_packets);
9186         ESTAT_ADD(rx_fcs_errors);
9187         ESTAT_ADD(rx_align_errors);
9188         ESTAT_ADD(rx_xon_pause_rcvd);
9189         ESTAT_ADD(rx_xoff_pause_rcvd);
9190         ESTAT_ADD(rx_mac_ctrl_rcvd);
9191         ESTAT_ADD(rx_xoff_entered);
9192         ESTAT_ADD(rx_frame_too_long_errors);
9193         ESTAT_ADD(rx_jabbers);
9194         ESTAT_ADD(rx_undersize_packets);
9195         ESTAT_ADD(rx_in_length_errors);
9196         ESTAT_ADD(rx_out_length_errors);
9197         ESTAT_ADD(rx_64_or_less_octet_packets);
9198         ESTAT_ADD(rx_65_to_127_octet_packets);
9199         ESTAT_ADD(rx_128_to_255_octet_packets);
9200         ESTAT_ADD(rx_256_to_511_octet_packets);
9201         ESTAT_ADD(rx_512_to_1023_octet_packets);
9202         ESTAT_ADD(rx_1024_to_1522_octet_packets);
9203         ESTAT_ADD(rx_1523_to_2047_octet_packets);
9204         ESTAT_ADD(rx_2048_to_4095_octet_packets);
9205         ESTAT_ADD(rx_4096_to_8191_octet_packets);
9206         ESTAT_ADD(rx_8192_to_9022_octet_packets);
9207
9208         ESTAT_ADD(tx_octets);
9209         ESTAT_ADD(tx_collisions);
9210         ESTAT_ADD(tx_xon_sent);
9211         ESTAT_ADD(tx_xoff_sent);
9212         ESTAT_ADD(tx_flow_control);
9213         ESTAT_ADD(tx_mac_errors);
9214         ESTAT_ADD(tx_single_collisions);
9215         ESTAT_ADD(tx_mult_collisions);
9216         ESTAT_ADD(tx_deferred);
9217         ESTAT_ADD(tx_excessive_collisions);
9218         ESTAT_ADD(tx_late_collisions);
9219         ESTAT_ADD(tx_collide_2times);
9220         ESTAT_ADD(tx_collide_3times);
9221         ESTAT_ADD(tx_collide_4times);
9222         ESTAT_ADD(tx_collide_5times);
9223         ESTAT_ADD(tx_collide_6times);
9224         ESTAT_ADD(tx_collide_7times);
9225         ESTAT_ADD(tx_collide_8times);
9226         ESTAT_ADD(tx_collide_9times);
9227         ESTAT_ADD(tx_collide_10times);
9228         ESTAT_ADD(tx_collide_11times);
9229         ESTAT_ADD(tx_collide_12times);
9230         ESTAT_ADD(tx_collide_13times);
9231         ESTAT_ADD(tx_collide_14times);
9232         ESTAT_ADD(tx_collide_15times);
9233         ESTAT_ADD(tx_ucast_packets);
9234         ESTAT_ADD(tx_mcast_packets);
9235         ESTAT_ADD(tx_bcast_packets);
9236         ESTAT_ADD(tx_carrier_sense_errors);
9237         ESTAT_ADD(tx_discards);
9238         ESTAT_ADD(tx_errors);
9239
9240         ESTAT_ADD(dma_writeq_full);
9241         ESTAT_ADD(dma_write_prioq_full);
9242         ESTAT_ADD(rxbds_empty);
9243         ESTAT_ADD(rx_discards);
9244         ESTAT_ADD(rx_errors);
9245         ESTAT_ADD(rx_threshold_hit);
9246
9247         ESTAT_ADD(dma_readq_full);
9248         ESTAT_ADD(dma_read_prioq_full);
9249         ESTAT_ADD(tx_comp_queue_full);
9250
9251         ESTAT_ADD(ring_set_send_prod_index);
9252         ESTAT_ADD(ring_status_update);
9253         ESTAT_ADD(nic_irqs);
9254         ESTAT_ADD(nic_avoided_irqs);
9255         ESTAT_ADD(nic_tx_threshold_hit);
9256
9257         return estats;
9258 }
9259
9260 static struct net_device_stats *tg3_get_stats(struct net_device *dev)
9261 {
9262         struct tg3 *tp = netdev_priv(dev);
9263         struct net_device_stats *stats = &tp->net_stats;
9264         struct net_device_stats *old_stats = &tp->net_stats_prev;
9265         struct tg3_hw_stats *hw_stats = tp->hw_stats;
9266
9267         if (!hw_stats)
9268                 return old_stats;
9269
9270         stats->rx_packets = old_stats->rx_packets +
9271                 get_stat64(&hw_stats->rx_ucast_packets) +
9272                 get_stat64(&hw_stats->rx_mcast_packets) +
9273                 get_stat64(&hw_stats->rx_bcast_packets);
9274
9275         stats->tx_packets = old_stats->tx_packets +
9276                 get_stat64(&hw_stats->tx_ucast_packets) +
9277                 get_stat64(&hw_stats->tx_mcast_packets) +
9278                 get_stat64(&hw_stats->tx_bcast_packets);
9279
9280         stats->rx_bytes = old_stats->rx_bytes +
9281                 get_stat64(&hw_stats->rx_octets);
9282         stats->tx_bytes = old_stats->tx_bytes +
9283                 get_stat64(&hw_stats->tx_octets);
9284
9285         stats->rx_errors = old_stats->rx_errors +
9286                 get_stat64(&hw_stats->rx_errors);
9287         stats->tx_errors = old_stats->tx_errors +
9288                 get_stat64(&hw_stats->tx_errors) +
9289                 get_stat64(&hw_stats->tx_mac_errors) +
9290                 get_stat64(&hw_stats->tx_carrier_sense_errors) +
9291                 get_stat64(&hw_stats->tx_discards);
9292
9293         stats->multicast = old_stats->multicast +
9294                 get_stat64(&hw_stats->rx_mcast_packets);
9295         stats->collisions = old_stats->collisions +
9296                 get_stat64(&hw_stats->tx_collisions);
9297
9298         stats->rx_length_errors = old_stats->rx_length_errors +
9299                 get_stat64(&hw_stats->rx_frame_too_long_errors) +
9300                 get_stat64(&hw_stats->rx_undersize_packets);
9301
9302         stats->rx_over_errors = old_stats->rx_over_errors +
9303                 get_stat64(&hw_stats->rxbds_empty);
9304         stats->rx_frame_errors = old_stats->rx_frame_errors +
9305                 get_stat64(&hw_stats->rx_align_errors);
9306         stats->tx_aborted_errors = old_stats->tx_aborted_errors +
9307                 get_stat64(&hw_stats->tx_discards);
9308         stats->tx_carrier_errors = old_stats->tx_carrier_errors +
9309                 get_stat64(&hw_stats->tx_carrier_sense_errors);
9310
9311         stats->rx_crc_errors = old_stats->rx_crc_errors +
9312                 calc_crc_errors(tp);
9313
9314         stats->rx_missed_errors = old_stats->rx_missed_errors +
9315                 get_stat64(&hw_stats->rx_discards);
9316
9317         return stats;
9318 }
9319
9320 static inline u32 calc_crc(unsigned char *buf, int len)
9321 {
9322         u32 reg;
9323         u32 tmp;
9324         int j, k;
9325
9326         reg = 0xffffffff;
9327
9328         for (j = 0; j < len; j++) {
9329                 reg ^= buf[j];
9330
9331                 for (k = 0; k < 8; k++) {
9332                         tmp = reg & 0x01;
9333
9334                         reg >>= 1;
9335
9336                         if (tmp) {
9337                                 reg ^= 0xedb88320;
9338                         }
9339                 }
9340         }
9341
9342         return ~reg;
9343 }
9344
9345 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
9346 {
9347         /* accept or reject all multicast frames */
9348         tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
9349         tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
9350         tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
9351         tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
9352 }
9353
9354 static void __tg3_set_rx_mode(struct net_device *dev)
9355 {
9356         struct tg3 *tp = netdev_priv(dev);
9357         u32 rx_mode;
9358
9359         rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
9360                                   RX_MODE_KEEP_VLAN_TAG);
9361
9362         /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
9363          * flag clear.
9364          */
9365 #if TG3_VLAN_TAG_USED
9366         if (!tp->vlgrp &&
9367             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9368                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9369 #else
9370         /* By definition, VLAN is disabled always in this
9371          * case.
9372          */
9373         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9374                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9375 #endif
9376
9377         if (dev->flags & IFF_PROMISC) {
9378                 /* Promiscuous mode. */
9379                 rx_mode |= RX_MODE_PROMISC;
9380         } else if (dev->flags & IFF_ALLMULTI) {
9381                 /* Accept all multicast. */
9382                 tg3_set_multi (tp, 1);
9383         } else if (dev->mc_count < 1) {
9384                 /* Reject all multicast. */
9385                 tg3_set_multi (tp, 0);
9386         } else {
9387                 /* Accept one or more multicast(s). */
9388                 struct dev_mc_list *mclist;
9389                 unsigned int i;
9390                 u32 mc_filter[4] = { 0, };
9391                 u32 regidx;
9392                 u32 bit;
9393                 u32 crc;
9394
9395                 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
9396                      i++, mclist = mclist->next) {
9397
9398                         crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
9399                         bit = ~crc & 0x7f;
9400                         regidx = (bit & 0x60) >> 5;
9401                         bit &= 0x1f;
9402                         mc_filter[regidx] |= (1 << bit);
9403                 }
9404
9405                 tw32(MAC_HASH_REG_0, mc_filter[0]);
9406                 tw32(MAC_HASH_REG_1, mc_filter[1]);
9407                 tw32(MAC_HASH_REG_2, mc_filter[2]);
9408                 tw32(MAC_HASH_REG_3, mc_filter[3]);
9409         }
9410
9411         if (rx_mode != tp->rx_mode) {
9412                 tp->rx_mode = rx_mode;
9413                 tw32_f(MAC_RX_MODE, rx_mode);
9414                 udelay(10);
9415         }
9416 }
9417
9418 static void tg3_set_rx_mode(struct net_device *dev)
9419 {
9420         struct tg3 *tp = netdev_priv(dev);
9421
9422         if (!netif_running(dev))
9423                 return;
9424
9425         tg3_full_lock(tp, 0);
9426         __tg3_set_rx_mode(dev);
9427         tg3_full_unlock(tp);
9428 }
9429
9430 #define TG3_REGDUMP_LEN         (32 * 1024)
9431
9432 static int tg3_get_regs_len(struct net_device *dev)
9433 {
9434         return TG3_REGDUMP_LEN;
9435 }
9436
9437 static void tg3_get_regs(struct net_device *dev,
9438                 struct ethtool_regs *regs, void *_p)
9439 {
9440         u32 *p = _p;
9441         struct tg3 *tp = netdev_priv(dev);
9442         u8 *orig_p = _p;
9443         int i;
9444
9445         regs->version = 0;
9446
9447         memset(p, 0, TG3_REGDUMP_LEN);
9448
9449         if (tp->link_config.phy_is_low_power)
9450                 return;
9451
9452         tg3_full_lock(tp, 0);
9453
9454 #define __GET_REG32(reg)        (*(p)++ = tr32(reg))
9455 #define GET_REG32_LOOP(base,len)                \
9456 do {    p = (u32 *)(orig_p + (base));           \
9457         for (i = 0; i < len; i += 4)            \
9458                 __GET_REG32((base) + i);        \
9459 } while (0)
9460 #define GET_REG32_1(reg)                        \
9461 do {    p = (u32 *)(orig_p + (reg));            \
9462         __GET_REG32((reg));                     \
9463 } while (0)
9464
9465         GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
9466         GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
9467         GET_REG32_LOOP(MAC_MODE, 0x4f0);
9468         GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
9469         GET_REG32_1(SNDDATAC_MODE);
9470         GET_REG32_LOOP(SNDBDS_MODE, 0x80);
9471         GET_REG32_LOOP(SNDBDI_MODE, 0x48);
9472         GET_REG32_1(SNDBDC_MODE);
9473         GET_REG32_LOOP(RCVLPC_MODE, 0x20);
9474         GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
9475         GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
9476         GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
9477         GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
9478         GET_REG32_1(RCVDCC_MODE);
9479         GET_REG32_LOOP(RCVBDI_MODE, 0x20);
9480         GET_REG32_LOOP(RCVCC_MODE, 0x14);
9481         GET_REG32_LOOP(RCVLSC_MODE, 0x08);
9482         GET_REG32_1(MBFREE_MODE);
9483         GET_REG32_LOOP(HOSTCC_MODE, 0x100);
9484         GET_REG32_LOOP(MEMARB_MODE, 0x10);
9485         GET_REG32_LOOP(BUFMGR_MODE, 0x58);
9486         GET_REG32_LOOP(RDMAC_MODE, 0x08);
9487         GET_REG32_LOOP(WDMAC_MODE, 0x08);
9488         GET_REG32_1(RX_CPU_MODE);
9489         GET_REG32_1(RX_CPU_STATE);
9490         GET_REG32_1(RX_CPU_PGMCTR);
9491         GET_REG32_1(RX_CPU_HWBKPT);
9492         GET_REG32_1(TX_CPU_MODE);
9493         GET_REG32_1(TX_CPU_STATE);
9494         GET_REG32_1(TX_CPU_PGMCTR);
9495         GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
9496         GET_REG32_LOOP(FTQ_RESET, 0x120);
9497         GET_REG32_LOOP(MSGINT_MODE, 0x0c);
9498         GET_REG32_1(DMAC_MODE);
9499         GET_REG32_LOOP(GRC_MODE, 0x4c);
9500         if (tp->tg3_flags & TG3_FLAG_NVRAM)
9501                 GET_REG32_LOOP(NVRAM_CMD, 0x24);
9502
9503 #undef __GET_REG32
9504 #undef GET_REG32_LOOP
9505 #undef GET_REG32_1
9506
9507         tg3_full_unlock(tp);
9508 }
9509
9510 static int tg3_get_eeprom_len(struct net_device *dev)
9511 {
9512         struct tg3 *tp = netdev_priv(dev);
9513
9514         return tp->nvram_size;
9515 }
9516
9517 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9518 {
9519         struct tg3 *tp = netdev_priv(dev);
9520         int ret;
9521         u8  *pd;
9522         u32 i, offset, len, b_offset, b_count;
9523         __be32 val;
9524
9525         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9526                 return -EINVAL;
9527
9528         if (tp->link_config.phy_is_low_power)
9529                 return -EAGAIN;
9530
9531         offset = eeprom->offset;
9532         len = eeprom->len;
9533         eeprom->len = 0;
9534
9535         eeprom->magic = TG3_EEPROM_MAGIC;
9536
9537         if (offset & 3) {
9538                 /* adjustments to start on required 4 byte boundary */
9539                 b_offset = offset & 3;
9540                 b_count = 4 - b_offset;
9541                 if (b_count > len) {
9542                         /* i.e. offset=1 len=2 */
9543                         b_count = len;
9544                 }
9545                 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
9546                 if (ret)
9547                         return ret;
9548                 memcpy(data, ((char*)&val) + b_offset, b_count);
9549                 len -= b_count;
9550                 offset += b_count;
9551                 eeprom->len += b_count;
9552         }
9553
9554         /* read bytes upto the last 4 byte boundary */
9555         pd = &data[eeprom->len];
9556         for (i = 0; i < (len - (len & 3)); i += 4) {
9557                 ret = tg3_nvram_read_be32(tp, offset + i, &val);
9558                 if (ret) {
9559                         eeprom->len += i;
9560                         return ret;
9561                 }
9562                 memcpy(pd + i, &val, 4);
9563         }
9564         eeprom->len += i;
9565
9566         if (len & 3) {
9567                 /* read last bytes not ending on 4 byte boundary */
9568                 pd = &data[eeprom->len];
9569                 b_count = len & 3;
9570                 b_offset = offset + len - b_count;
9571                 ret = tg3_nvram_read_be32(tp, b_offset, &val);
9572                 if (ret)
9573                         return ret;
9574                 memcpy(pd, &val, b_count);
9575                 eeprom->len += b_count;
9576         }
9577         return 0;
9578 }
9579
9580 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
9581
9582 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9583 {
9584         struct tg3 *tp = netdev_priv(dev);
9585         int ret;
9586         u32 offset, len, b_offset, odd_len;
9587         u8 *buf;
9588         __be32 start, end;
9589
9590         if (tp->link_config.phy_is_low_power)
9591                 return -EAGAIN;
9592
9593         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
9594             eeprom->magic != TG3_EEPROM_MAGIC)
9595                 return -EINVAL;
9596
9597         offset = eeprom->offset;
9598         len = eeprom->len;
9599
9600         if ((b_offset = (offset & 3))) {
9601                 /* adjustments to start on required 4 byte boundary */
9602                 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
9603                 if (ret)
9604                         return ret;
9605                 len += b_offset;
9606                 offset &= ~3;
9607                 if (len < 4)
9608                         len = 4;
9609         }
9610
9611         odd_len = 0;
9612         if (len & 3) {
9613                 /* adjustments to end on required 4 byte boundary */
9614                 odd_len = 1;
9615                 len = (len + 3) & ~3;
9616                 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
9617                 if (ret)
9618                         return ret;
9619         }
9620
9621         buf = data;
9622         if (b_offset || odd_len) {
9623                 buf = kmalloc(len, GFP_KERNEL);
9624                 if (!buf)
9625                         return -ENOMEM;
9626                 if (b_offset)
9627                         memcpy(buf, &start, 4);
9628                 if (odd_len)
9629                         memcpy(buf+len-4, &end, 4);
9630                 memcpy(buf + b_offset, data, eeprom->len);
9631         }
9632
9633         ret = tg3_nvram_write_block(tp, offset, len, buf);
9634
9635         if (buf != data)
9636                 kfree(buf);
9637
9638         return ret;
9639 }
9640
9641 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9642 {
9643         struct tg3 *tp = netdev_priv(dev);
9644
9645         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9646                 struct phy_device *phydev;
9647                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9648                         return -EAGAIN;
9649                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9650                 return phy_ethtool_gset(phydev, cmd);
9651         }
9652
9653         cmd->supported = (SUPPORTED_Autoneg);
9654
9655         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
9656                 cmd->supported |= (SUPPORTED_1000baseT_Half |
9657                                    SUPPORTED_1000baseT_Full);
9658
9659         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
9660                 cmd->supported |= (SUPPORTED_100baseT_Half |
9661                                   SUPPORTED_100baseT_Full |
9662                                   SUPPORTED_10baseT_Half |
9663                                   SUPPORTED_10baseT_Full |
9664                                   SUPPORTED_TP);
9665                 cmd->port = PORT_TP;
9666         } else {
9667                 cmd->supported |= SUPPORTED_FIBRE;
9668                 cmd->port = PORT_FIBRE;
9669         }
9670
9671         cmd->advertising = tp->link_config.advertising;
9672         if (netif_running(dev)) {
9673                 cmd->speed = tp->link_config.active_speed;
9674                 cmd->duplex = tp->link_config.active_duplex;
9675         }
9676         cmd->phy_address = tp->phy_addr;
9677         cmd->transceiver = XCVR_INTERNAL;
9678         cmd->autoneg = tp->link_config.autoneg;
9679         cmd->maxtxpkt = 0;
9680         cmd->maxrxpkt = 0;
9681         return 0;
9682 }
9683
9684 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9685 {
9686         struct tg3 *tp = netdev_priv(dev);
9687
9688         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9689                 struct phy_device *phydev;
9690                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9691                         return -EAGAIN;
9692                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9693                 return phy_ethtool_sset(phydev, cmd);
9694         }
9695
9696         if (cmd->autoneg != AUTONEG_ENABLE &&
9697             cmd->autoneg != AUTONEG_DISABLE)
9698                 return -EINVAL;
9699
9700         if (cmd->autoneg == AUTONEG_DISABLE &&
9701             cmd->duplex != DUPLEX_FULL &&
9702             cmd->duplex != DUPLEX_HALF)
9703                 return -EINVAL;
9704
9705         if (cmd->autoneg == AUTONEG_ENABLE) {
9706                 u32 mask = ADVERTISED_Autoneg |
9707                            ADVERTISED_Pause |
9708                            ADVERTISED_Asym_Pause;
9709
9710                 if (!(tp->tg3_flags2 & TG3_FLAG_10_100_ONLY))
9711                         mask |= ADVERTISED_1000baseT_Half |
9712                                 ADVERTISED_1000baseT_Full;
9713
9714                 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
9715                         mask |= ADVERTISED_100baseT_Half |
9716                                 ADVERTISED_100baseT_Full |
9717                                 ADVERTISED_10baseT_Half |
9718                                 ADVERTISED_10baseT_Full |
9719                                 ADVERTISED_TP;
9720                 else
9721                         mask |= ADVERTISED_FIBRE;
9722
9723                 if (cmd->advertising & ~mask)
9724                         return -EINVAL;
9725
9726                 mask &= (ADVERTISED_1000baseT_Half |
9727                          ADVERTISED_1000baseT_Full |
9728                          ADVERTISED_100baseT_Half |
9729                          ADVERTISED_100baseT_Full |
9730                          ADVERTISED_10baseT_Half |
9731                          ADVERTISED_10baseT_Full);
9732
9733                 cmd->advertising &= mask;
9734         } else {
9735                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
9736                         if (cmd->speed != SPEED_1000)
9737                                 return -EINVAL;
9738
9739                         if (cmd->duplex != DUPLEX_FULL)
9740                                 return -EINVAL;
9741                 } else {
9742                         if (cmd->speed != SPEED_100 &&
9743                             cmd->speed != SPEED_10)
9744                                 return -EINVAL;
9745                 }
9746         }
9747
9748         tg3_full_lock(tp, 0);
9749
9750         tp->link_config.autoneg = cmd->autoneg;
9751         if (cmd->autoneg == AUTONEG_ENABLE) {
9752                 tp->link_config.advertising = (cmd->advertising |
9753                                               ADVERTISED_Autoneg);
9754                 tp->link_config.speed = SPEED_INVALID;
9755                 tp->link_config.duplex = DUPLEX_INVALID;
9756         } else {
9757                 tp->link_config.advertising = 0;
9758                 tp->link_config.speed = cmd->speed;
9759                 tp->link_config.duplex = cmd->duplex;
9760         }
9761
9762         tp->link_config.orig_speed = tp->link_config.speed;
9763         tp->link_config.orig_duplex = tp->link_config.duplex;
9764         tp->link_config.orig_autoneg = tp->link_config.autoneg;
9765
9766         if (netif_running(dev))
9767                 tg3_setup_phy(tp, 1);
9768
9769         tg3_full_unlock(tp);
9770
9771         return 0;
9772 }
9773
9774 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
9775 {
9776         struct tg3 *tp = netdev_priv(dev);
9777
9778         strcpy(info->driver, DRV_MODULE_NAME);
9779         strcpy(info->version, DRV_MODULE_VERSION);
9780         strcpy(info->fw_version, tp->fw_ver);
9781         strcpy(info->bus_info, pci_name(tp->pdev));
9782 }
9783
9784 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9785 {
9786         struct tg3 *tp = netdev_priv(dev);
9787
9788         if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
9789             device_can_wakeup(&tp->pdev->dev))
9790                 wol->supported = WAKE_MAGIC;
9791         else
9792                 wol->supported = 0;
9793         wol->wolopts = 0;
9794         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
9795             device_can_wakeup(&tp->pdev->dev))
9796                 wol->wolopts = WAKE_MAGIC;
9797         memset(&wol->sopass, 0, sizeof(wol->sopass));
9798 }
9799
9800 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9801 {
9802         struct tg3 *tp = netdev_priv(dev);
9803         struct device *dp = &tp->pdev->dev;
9804
9805         if (wol->wolopts & ~WAKE_MAGIC)
9806                 return -EINVAL;
9807         if ((wol->wolopts & WAKE_MAGIC) &&
9808             !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
9809                 return -EINVAL;
9810
9811         spin_lock_bh(&tp->lock);
9812         if (wol->wolopts & WAKE_MAGIC) {
9813                 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
9814                 device_set_wakeup_enable(dp, true);
9815         } else {
9816                 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
9817                 device_set_wakeup_enable(dp, false);
9818         }
9819         spin_unlock_bh(&tp->lock);
9820
9821         return 0;
9822 }
9823
9824 static u32 tg3_get_msglevel(struct net_device *dev)
9825 {
9826         struct tg3 *tp = netdev_priv(dev);
9827         return tp->msg_enable;
9828 }
9829
9830 static void tg3_set_msglevel(struct net_device *dev, u32 value)
9831 {
9832         struct tg3 *tp = netdev_priv(dev);
9833         tp->msg_enable = value;
9834 }
9835
9836 static int tg3_set_tso(struct net_device *dev, u32 value)
9837 {
9838         struct tg3 *tp = netdev_priv(dev);
9839
9840         if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
9841                 if (value)
9842                         return -EINVAL;
9843                 return 0;
9844         }
9845         if ((dev->features & NETIF_F_IPV6_CSUM) &&
9846             ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
9847              (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3))) {
9848                 if (value) {
9849                         dev->features |= NETIF_F_TSO6;
9850                         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
9851                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9852                             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
9853                              GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
9854                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
9855                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
9856                                 dev->features |= NETIF_F_TSO_ECN;
9857                 } else
9858                         dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
9859         }
9860         return ethtool_op_set_tso(dev, value);
9861 }
9862
9863 static int tg3_nway_reset(struct net_device *dev)
9864 {
9865         struct tg3 *tp = netdev_priv(dev);
9866         int r;
9867
9868         if (!netif_running(dev))
9869                 return -EAGAIN;
9870
9871         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9872                 return -EINVAL;
9873
9874         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9875                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9876                         return -EAGAIN;
9877                 r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
9878         } else {
9879                 u32 bmcr;
9880
9881                 spin_lock_bh(&tp->lock);
9882                 r = -EINVAL;
9883                 tg3_readphy(tp, MII_BMCR, &bmcr);
9884                 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
9885                     ((bmcr & BMCR_ANENABLE) ||
9886                      (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
9887                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
9888                                                    BMCR_ANENABLE);
9889                         r = 0;
9890                 }
9891                 spin_unlock_bh(&tp->lock);
9892         }
9893
9894         return r;
9895 }
9896
9897 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9898 {
9899         struct tg3 *tp = netdev_priv(dev);
9900
9901         ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
9902         ering->rx_mini_max_pending = 0;
9903         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9904                 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
9905         else
9906                 ering->rx_jumbo_max_pending = 0;
9907
9908         ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
9909
9910         ering->rx_pending = tp->rx_pending;
9911         ering->rx_mini_pending = 0;
9912         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9913                 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
9914         else
9915                 ering->rx_jumbo_pending = 0;
9916
9917         ering->tx_pending = tp->napi[0].tx_pending;
9918 }
9919
9920 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9921 {
9922         struct tg3 *tp = netdev_priv(dev);
9923         int i, irq_sync = 0, err = 0;
9924
9925         if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
9926             (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
9927             (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
9928             (ering->tx_pending <= MAX_SKB_FRAGS) ||
9929             ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
9930              (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
9931                 return -EINVAL;
9932
9933         if (netif_running(dev)) {
9934                 tg3_phy_stop(tp);
9935                 tg3_netif_stop(tp);
9936                 irq_sync = 1;
9937         }
9938
9939         tg3_full_lock(tp, irq_sync);
9940
9941         tp->rx_pending = ering->rx_pending;
9942
9943         if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
9944             tp->rx_pending > 63)
9945                 tp->rx_pending = 63;
9946         tp->rx_jumbo_pending = ering->rx_jumbo_pending;
9947
9948         for (i = 0; i < TG3_IRQ_MAX_VECS; i++)
9949                 tp->napi[i].tx_pending = ering->tx_pending;
9950
9951         if (netif_running(dev)) {
9952                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9953                 err = tg3_restart_hw(tp, 1);
9954                 if (!err)
9955                         tg3_netif_start(tp);
9956         }
9957
9958         tg3_full_unlock(tp);
9959
9960         if (irq_sync && !err)
9961                 tg3_phy_start(tp);
9962
9963         return err;
9964 }
9965
9966 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9967 {
9968         struct tg3 *tp = netdev_priv(dev);
9969
9970         epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
9971
9972         if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
9973                 epause->rx_pause = 1;
9974         else
9975                 epause->rx_pause = 0;
9976
9977         if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
9978                 epause->tx_pause = 1;
9979         else
9980                 epause->tx_pause = 0;
9981 }
9982
9983 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9984 {
9985         struct tg3 *tp = netdev_priv(dev);
9986         int err = 0;
9987
9988         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9989                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9990                         return -EAGAIN;
9991
9992                 if (epause->autoneg) {
9993                         u32 newadv;
9994                         struct phy_device *phydev;
9995
9996                         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9997
9998                         if (epause->rx_pause) {
9999                                 if (epause->tx_pause)
10000                                         newadv = ADVERTISED_Pause;
10001                                 else
10002                                         newadv = ADVERTISED_Pause |
10003                                                  ADVERTISED_Asym_Pause;
10004                         } else if (epause->tx_pause) {
10005                                 newadv = ADVERTISED_Asym_Pause;
10006                         } else
10007                                 newadv = 0;
10008
10009                         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
10010                                 u32 oldadv = phydev->advertising &
10011                                              (ADVERTISED_Pause |
10012                                               ADVERTISED_Asym_Pause);
10013                                 if (oldadv != newadv) {
10014                                         phydev->advertising &=
10015                                                 ~(ADVERTISED_Pause |
10016                                                   ADVERTISED_Asym_Pause);
10017                                         phydev->advertising |= newadv;
10018                                         err = phy_start_aneg(phydev);
10019                                 }
10020                         } else {
10021                                 tp->link_config.advertising &=
10022                                                 ~(ADVERTISED_Pause |
10023                                                   ADVERTISED_Asym_Pause);
10024                                 tp->link_config.advertising |= newadv;
10025                         }
10026                 } else {
10027                         if (epause->rx_pause)
10028                                 tp->link_config.flowctrl |= FLOW_CTRL_RX;
10029                         else
10030                                 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
10031
10032                         if (epause->tx_pause)
10033                                 tp->link_config.flowctrl |= FLOW_CTRL_TX;
10034                         else
10035                                 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
10036
10037                         if (netif_running(dev))
10038                                 tg3_setup_flow_control(tp, 0, 0);
10039                 }
10040         } else {
10041                 int irq_sync = 0;
10042
10043                 if (netif_running(dev)) {
10044                         tg3_netif_stop(tp);
10045                         irq_sync = 1;
10046                 }
10047
10048                 tg3_full_lock(tp, irq_sync);
10049
10050                 if (epause->autoneg)
10051                         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
10052                 else
10053                         tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
10054                 if (epause->rx_pause)
10055                         tp->link_config.flowctrl |= FLOW_CTRL_RX;
10056                 else
10057                         tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
10058                 if (epause->tx_pause)
10059                         tp->link_config.flowctrl |= FLOW_CTRL_TX;
10060                 else
10061                         tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
10062
10063                 if (netif_running(dev)) {
10064                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10065                         err = tg3_restart_hw(tp, 1);
10066                         if (!err)
10067                                 tg3_netif_start(tp);
10068                 }
10069
10070                 tg3_full_unlock(tp);
10071         }
10072
10073         return err;
10074 }
10075
10076 static u32 tg3_get_rx_csum(struct net_device *dev)
10077 {
10078         struct tg3 *tp = netdev_priv(dev);
10079         return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
10080 }
10081
10082 static int tg3_set_rx_csum(struct net_device *dev, u32 data)
10083 {
10084         struct tg3 *tp = netdev_priv(dev);
10085
10086         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
10087                 if (data != 0)
10088                         return -EINVAL;
10089                 return 0;
10090         }
10091
10092         spin_lock_bh(&tp->lock);
10093         if (data)
10094                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
10095         else
10096                 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
10097         spin_unlock_bh(&tp->lock);
10098
10099         return 0;
10100 }
10101
10102 static int tg3_set_tx_csum(struct net_device *dev, u32 data)
10103 {
10104         struct tg3 *tp = netdev_priv(dev);
10105
10106         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
10107                 if (data != 0)
10108                         return -EINVAL;
10109                 return 0;
10110         }
10111
10112         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10113                 ethtool_op_set_tx_ipv6_csum(dev, data);
10114         else
10115                 ethtool_op_set_tx_csum(dev, data);
10116
10117         return 0;
10118 }
10119
10120 static int tg3_get_sset_count (struct net_device *dev, int sset)
10121 {
10122         switch (sset) {
10123         case ETH_SS_TEST:
10124                 return TG3_NUM_TEST;
10125         case ETH_SS_STATS:
10126                 return TG3_NUM_STATS;
10127         default:
10128                 return -EOPNOTSUPP;
10129         }
10130 }
10131
10132 static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
10133 {
10134         switch (stringset) {
10135         case ETH_SS_STATS:
10136                 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
10137                 break;
10138         case ETH_SS_TEST:
10139                 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
10140                 break;
10141         default:
10142                 WARN_ON(1);     /* we need a WARN() */
10143                 break;
10144         }
10145 }
10146
10147 static int tg3_phys_id(struct net_device *dev, u32 data)
10148 {
10149         struct tg3 *tp = netdev_priv(dev);
10150         int i;
10151
10152         if (!netif_running(tp->dev))
10153                 return -EAGAIN;
10154
10155         if (data == 0)
10156                 data = UINT_MAX / 2;
10157
10158         for (i = 0; i < (data * 2); i++) {
10159                 if ((i % 2) == 0)
10160                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10161                                            LED_CTRL_1000MBPS_ON |
10162                                            LED_CTRL_100MBPS_ON |
10163                                            LED_CTRL_10MBPS_ON |
10164                                            LED_CTRL_TRAFFIC_OVERRIDE |
10165                                            LED_CTRL_TRAFFIC_BLINK |
10166                                            LED_CTRL_TRAFFIC_LED);
10167
10168                 else
10169                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10170                                            LED_CTRL_TRAFFIC_OVERRIDE);
10171
10172                 if (msleep_interruptible(500))
10173                         break;
10174         }
10175         tw32(MAC_LED_CTRL, tp->led_ctrl);
10176         return 0;
10177 }
10178
10179 static void tg3_get_ethtool_stats (struct net_device *dev,
10180                                    struct ethtool_stats *estats, u64 *tmp_stats)
10181 {
10182         struct tg3 *tp = netdev_priv(dev);
10183         memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
10184 }
10185
10186 #define NVRAM_TEST_SIZE 0x100
10187 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE   0x14
10188 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE   0x18
10189 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE   0x1c
10190 #define NVRAM_SELFBOOT_HW_SIZE 0x20
10191 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
10192
10193 static int tg3_test_nvram(struct tg3 *tp)
10194 {
10195         u32 csum, magic;
10196         __be32 *buf;
10197         int i, j, k, err = 0, size;
10198
10199         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
10200                 return 0;
10201
10202         if (tg3_nvram_read(tp, 0, &magic) != 0)
10203                 return -EIO;
10204
10205         if (magic == TG3_EEPROM_MAGIC)
10206                 size = NVRAM_TEST_SIZE;
10207         else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
10208                 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
10209                     TG3_EEPROM_SB_FORMAT_1) {
10210                         switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
10211                         case TG3_EEPROM_SB_REVISION_0:
10212                                 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
10213                                 break;
10214                         case TG3_EEPROM_SB_REVISION_2:
10215                                 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
10216                                 break;
10217                         case TG3_EEPROM_SB_REVISION_3:
10218                                 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
10219                                 break;
10220                         default:
10221                                 return 0;
10222                         }
10223                 } else
10224                         return 0;
10225         } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
10226                 size = NVRAM_SELFBOOT_HW_SIZE;
10227         else
10228                 return -EIO;
10229
10230         buf = kmalloc(size, GFP_KERNEL);
10231         if (buf == NULL)
10232                 return -ENOMEM;
10233
10234         err = -EIO;
10235         for (i = 0, j = 0; i < size; i += 4, j++) {
10236                 err = tg3_nvram_read_be32(tp, i, &buf[j]);
10237                 if (err)
10238                         break;
10239         }
10240         if (i < size)
10241                 goto out;
10242
10243         /* Selfboot format */
10244         magic = be32_to_cpu(buf[0]);
10245         if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
10246             TG3_EEPROM_MAGIC_FW) {
10247                 u8 *buf8 = (u8 *) buf, csum8 = 0;
10248
10249                 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
10250                     TG3_EEPROM_SB_REVISION_2) {
10251                         /* For rev 2, the csum doesn't include the MBA. */
10252                         for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
10253                                 csum8 += buf8[i];
10254                         for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
10255                                 csum8 += buf8[i];
10256                 } else {
10257                         for (i = 0; i < size; i++)
10258                                 csum8 += buf8[i];
10259                 }
10260
10261                 if (csum8 == 0) {
10262                         err = 0;
10263                         goto out;
10264                 }
10265
10266                 err = -EIO;
10267                 goto out;
10268         }
10269
10270         if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
10271             TG3_EEPROM_MAGIC_HW) {
10272                 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
10273                 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
10274                 u8 *buf8 = (u8 *) buf;
10275
10276                 /* Separate the parity bits and the data bytes.  */
10277                 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
10278                         if ((i == 0) || (i == 8)) {
10279                                 int l;
10280                                 u8 msk;
10281
10282                                 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
10283                                         parity[k++] = buf8[i] & msk;
10284                                 i++;
10285                         }
10286                         else if (i == 16) {
10287                                 int l;
10288                                 u8 msk;
10289
10290                                 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
10291                                         parity[k++] = buf8[i] & msk;
10292                                 i++;
10293
10294                                 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
10295                                         parity[k++] = buf8[i] & msk;
10296                                 i++;
10297                         }
10298                         data[j++] = buf8[i];
10299                 }
10300
10301                 err = -EIO;
10302                 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
10303                         u8 hw8 = hweight8(data[i]);
10304
10305                         if ((hw8 & 0x1) && parity[i])
10306                                 goto out;
10307                         else if (!(hw8 & 0x1) && !parity[i])
10308                                 goto out;
10309                 }
10310                 err = 0;
10311                 goto out;
10312         }
10313
10314         /* Bootstrap checksum at offset 0x10 */
10315         csum = calc_crc((unsigned char *) buf, 0x10);
10316         if (csum != be32_to_cpu(buf[0x10/4]))
10317                 goto out;
10318
10319         /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
10320         csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
10321         if (csum != be32_to_cpu(buf[0xfc/4]))
10322                 goto out;
10323
10324         err = 0;
10325
10326 out:
10327         kfree(buf);
10328         return err;
10329 }
10330
10331 #define TG3_SERDES_TIMEOUT_SEC  2
10332 #define TG3_COPPER_TIMEOUT_SEC  6
10333
10334 static int tg3_test_link(struct tg3 *tp)
10335 {
10336         int i, max;
10337
10338         if (!netif_running(tp->dev))
10339                 return -ENODEV;
10340
10341         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
10342                 max = TG3_SERDES_TIMEOUT_SEC;
10343         else
10344                 max = TG3_COPPER_TIMEOUT_SEC;
10345
10346         for (i = 0; i < max; i++) {
10347                 if (netif_carrier_ok(tp->dev))
10348                         return 0;
10349
10350                 if (msleep_interruptible(1000))
10351                         break;
10352         }
10353
10354         return -EIO;
10355 }
10356
10357 /* Only test the commonly used registers */
10358 static int tg3_test_registers(struct tg3 *tp)
10359 {
10360         int i, is_5705, is_5750;
10361         u32 offset, read_mask, write_mask, val, save_val, read_val;
10362         static struct {
10363                 u16 offset;
10364                 u16 flags;
10365 #define TG3_FL_5705     0x1
10366 #define TG3_FL_NOT_5705 0x2
10367 #define TG3_FL_NOT_5788 0x4
10368 #define TG3_FL_NOT_5750 0x8
10369                 u32 read_mask;
10370                 u32 write_mask;
10371         } reg_tbl[] = {
10372                 /* MAC Control Registers */
10373                 { MAC_MODE, TG3_FL_NOT_5705,
10374                         0x00000000, 0x00ef6f8c },
10375                 { MAC_MODE, TG3_FL_5705,
10376                         0x00000000, 0x01ef6b8c },
10377                 { MAC_STATUS, TG3_FL_NOT_5705,
10378                         0x03800107, 0x00000000 },
10379                 { MAC_STATUS, TG3_FL_5705,
10380                         0x03800100, 0x00000000 },
10381                 { MAC_ADDR_0_HIGH, 0x0000,
10382                         0x00000000, 0x0000ffff },
10383                 { MAC_ADDR_0_LOW, 0x0000,
10384                         0x00000000, 0xffffffff },
10385                 { MAC_RX_MTU_SIZE, 0x0000,
10386                         0x00000000, 0x0000ffff },
10387                 { MAC_TX_MODE, 0x0000,
10388                         0x00000000, 0x00000070 },
10389                 { MAC_TX_LENGTHS, 0x0000,
10390                         0x00000000, 0x00003fff },
10391                 { MAC_RX_MODE, TG3_FL_NOT_5705,
10392                         0x00000000, 0x000007fc },
10393                 { MAC_RX_MODE, TG3_FL_5705,
10394                         0x00000000, 0x000007dc },
10395                 { MAC_HASH_REG_0, 0x0000,
10396                         0x00000000, 0xffffffff },
10397                 { MAC_HASH_REG_1, 0x0000,
10398                         0x00000000, 0xffffffff },
10399                 { MAC_HASH_REG_2, 0x0000,
10400                         0x00000000, 0xffffffff },
10401                 { MAC_HASH_REG_3, 0x0000,
10402                         0x00000000, 0xffffffff },
10403
10404                 /* Receive Data and Receive BD Initiator Control Registers. */
10405                 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
10406                         0x00000000, 0xffffffff },
10407                 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
10408                         0x00000000, 0xffffffff },
10409                 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
10410                         0x00000000, 0x00000003 },
10411                 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
10412                         0x00000000, 0xffffffff },
10413                 { RCVDBDI_STD_BD+0, 0x0000,
10414                         0x00000000, 0xffffffff },
10415                 { RCVDBDI_STD_BD+4, 0x0000,
10416                         0x00000000, 0xffffffff },
10417                 { RCVDBDI_STD_BD+8, 0x0000,
10418                         0x00000000, 0xffff0002 },
10419                 { RCVDBDI_STD_BD+0xc, 0x0000,
10420                         0x00000000, 0xffffffff },
10421
10422                 /* Receive BD Initiator Control Registers. */
10423                 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
10424                         0x00000000, 0xffffffff },
10425                 { RCVBDI_STD_THRESH, TG3_FL_5705,
10426                         0x00000000, 0x000003ff },
10427                 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
10428                         0x00000000, 0xffffffff },
10429
10430                 /* Host Coalescing Control Registers. */
10431                 { HOSTCC_MODE, TG3_FL_NOT_5705,
10432                         0x00000000, 0x00000004 },
10433                 { HOSTCC_MODE, TG3_FL_5705,
10434                         0x00000000, 0x000000f6 },
10435                 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
10436                         0x00000000, 0xffffffff },
10437                 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
10438                         0x00000000, 0x000003ff },
10439                 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
10440                         0x00000000, 0xffffffff },
10441                 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
10442                         0x00000000, 0x000003ff },
10443                 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
10444                         0x00000000, 0xffffffff },
10445                 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10446                         0x00000000, 0x000000ff },
10447                 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
10448                         0x00000000, 0xffffffff },
10449                 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10450                         0x00000000, 0x000000ff },
10451                 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
10452                         0x00000000, 0xffffffff },
10453                 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
10454                         0x00000000, 0xffffffff },
10455                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10456                         0x00000000, 0xffffffff },
10457                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10458                         0x00000000, 0x000000ff },
10459                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10460                         0x00000000, 0xffffffff },
10461                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10462                         0x00000000, 0x000000ff },
10463                 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
10464                         0x00000000, 0xffffffff },
10465                 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
10466                         0x00000000, 0xffffffff },
10467                 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
10468                         0x00000000, 0xffffffff },
10469                 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
10470                         0x00000000, 0xffffffff },
10471                 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
10472                         0x00000000, 0xffffffff },
10473                 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
10474                         0xffffffff, 0x00000000 },
10475                 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
10476                         0xffffffff, 0x00000000 },
10477
10478                 /* Buffer Manager Control Registers. */
10479                 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
10480                         0x00000000, 0x007fff80 },
10481                 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
10482                         0x00000000, 0x007fffff },
10483                 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
10484                         0x00000000, 0x0000003f },
10485                 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
10486                         0x00000000, 0x000001ff },
10487                 { BUFMGR_MB_HIGH_WATER, 0x0000,
10488                         0x00000000, 0x000001ff },
10489                 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
10490                         0xffffffff, 0x00000000 },
10491                 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
10492                         0xffffffff, 0x00000000 },
10493
10494                 /* Mailbox Registers */
10495                 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
10496                         0x00000000, 0x000001ff },
10497                 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
10498                         0x00000000, 0x000001ff },
10499                 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
10500                         0x00000000, 0x000007ff },
10501                 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
10502                         0x00000000, 0x000001ff },
10503
10504                 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
10505         };
10506
10507         is_5705 = is_5750 = 0;
10508         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
10509                 is_5705 = 1;
10510                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10511                         is_5750 = 1;
10512         }
10513
10514         for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
10515                 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
10516                         continue;
10517
10518                 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
10519                         continue;
10520
10521                 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
10522                     (reg_tbl[i].flags & TG3_FL_NOT_5788))
10523                         continue;
10524
10525                 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
10526                         continue;
10527
10528                 offset = (u32) reg_tbl[i].offset;
10529                 read_mask = reg_tbl[i].read_mask;
10530                 write_mask = reg_tbl[i].write_mask;
10531
10532                 /* Save the original register content */
10533                 save_val = tr32(offset);
10534
10535                 /* Determine the read-only value. */
10536                 read_val = save_val & read_mask;
10537
10538                 /* Write zero to the register, then make sure the read-only bits
10539                  * are not changed and the read/write bits are all zeros.
10540                  */
10541                 tw32(offset, 0);
10542
10543                 val = tr32(offset);
10544
10545                 /* Test the read-only and read/write bits. */
10546                 if (((val & read_mask) != read_val) || (val & write_mask))
10547                         goto out;
10548
10549                 /* Write ones to all the bits defined by RdMask and WrMask, then
10550                  * make sure the read-only bits are not changed and the
10551                  * read/write bits are all ones.
10552                  */
10553                 tw32(offset, read_mask | write_mask);
10554
10555                 val = tr32(offset);
10556
10557                 /* Test the read-only bits. */
10558                 if ((val & read_mask) != read_val)
10559                         goto out;
10560
10561                 /* Test the read/write bits. */
10562                 if ((val & write_mask) != write_mask)
10563                         goto out;
10564
10565                 tw32(offset, save_val);
10566         }
10567
10568         return 0;
10569
10570 out:
10571         if (netif_msg_hw(tp))
10572                 printk(KERN_ERR PFX "Register test failed at offset %x\n",
10573                        offset);
10574         tw32(offset, save_val);
10575         return -EIO;
10576 }
10577
10578 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
10579 {
10580         static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
10581         int i;
10582         u32 j;
10583
10584         for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
10585                 for (j = 0; j < len; j += 4) {
10586                         u32 val;
10587
10588                         tg3_write_mem(tp, offset + j, test_pattern[i]);
10589                         tg3_read_mem(tp, offset + j, &val);
10590                         if (val != test_pattern[i])
10591                                 return -EIO;
10592                 }
10593         }
10594         return 0;
10595 }
10596
10597 static int tg3_test_memory(struct tg3 *tp)
10598 {
10599         static struct mem_entry {
10600                 u32 offset;
10601                 u32 len;
10602         } mem_tbl_570x[] = {
10603                 { 0x00000000, 0x00b50},
10604                 { 0x00002000, 0x1c000},
10605                 { 0xffffffff, 0x00000}
10606         }, mem_tbl_5705[] = {
10607                 { 0x00000100, 0x0000c},
10608                 { 0x00000200, 0x00008},
10609                 { 0x00004000, 0x00800},
10610                 { 0x00006000, 0x01000},
10611                 { 0x00008000, 0x02000},
10612                 { 0x00010000, 0x0e000},
10613                 { 0xffffffff, 0x00000}
10614         }, mem_tbl_5755[] = {
10615                 { 0x00000200, 0x00008},
10616                 { 0x00004000, 0x00800},
10617                 { 0x00006000, 0x00800},
10618                 { 0x00008000, 0x02000},
10619                 { 0x00010000, 0x0c000},
10620                 { 0xffffffff, 0x00000}
10621         }, mem_tbl_5906[] = {
10622                 { 0x00000200, 0x00008},
10623                 { 0x00004000, 0x00400},
10624                 { 0x00006000, 0x00400},
10625                 { 0x00008000, 0x01000},
10626                 { 0x00010000, 0x01000},
10627                 { 0xffffffff, 0x00000}
10628         };
10629         struct mem_entry *mem_tbl;
10630         int err = 0;
10631         int i;
10632
10633         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10634                 mem_tbl = mem_tbl_5755;
10635         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10636                 mem_tbl = mem_tbl_5906;
10637         else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
10638                 mem_tbl = mem_tbl_5705;
10639         else
10640                 mem_tbl = mem_tbl_570x;
10641
10642         for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
10643                 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
10644                     mem_tbl[i].len)) != 0)
10645                         break;
10646         }
10647
10648         return err;
10649 }
10650
10651 #define TG3_MAC_LOOPBACK        0
10652 #define TG3_PHY_LOOPBACK        1
10653
10654 static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
10655 {
10656         u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
10657         u32 desc_idx, coal_now;
10658         struct sk_buff *skb, *rx_skb;
10659         u8 *tx_data;
10660         dma_addr_t map;
10661         int num_pkts, tx_len, rx_len, i, err;
10662         struct tg3_rx_buffer_desc *desc;
10663         struct tg3_napi *tnapi, *rnapi;
10664         struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
10665
10666         if (tp->irq_cnt > 1) {
10667                 tnapi = &tp->napi[1];
10668                 rnapi = &tp->napi[1];
10669         } else {
10670                 tnapi = &tp->napi[0];
10671                 rnapi = &tp->napi[0];
10672         }
10673         coal_now = tnapi->coal_now | rnapi->coal_now;
10674
10675         if (loopback_mode == TG3_MAC_LOOPBACK) {
10676                 /* HW errata - mac loopback fails in some cases on 5780.
10677                  * Normal traffic and PHY loopback are not affected by
10678                  * errata.
10679                  */
10680                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
10681                         return 0;
10682
10683                 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
10684                            MAC_MODE_PORT_INT_LPBACK;
10685                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10686                         mac_mode |= MAC_MODE_LINK_POLARITY;
10687                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
10688                         mac_mode |= MAC_MODE_PORT_MODE_MII;
10689                 else
10690                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
10691                 tw32(MAC_MODE, mac_mode);
10692         } else if (loopback_mode == TG3_PHY_LOOPBACK) {
10693                 u32 val;
10694
10695                 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
10696                         tg3_phy_fet_toggle_apd(tp, false);
10697                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
10698                 } else
10699                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
10700
10701                 tg3_phy_toggle_automdix(tp, 0);
10702
10703                 tg3_writephy(tp, MII_BMCR, val);
10704                 udelay(40);
10705
10706                 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
10707                 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
10708                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10709                                 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x1800);
10710                         mac_mode |= MAC_MODE_PORT_MODE_MII;
10711                 } else
10712                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
10713
10714                 /* reset to prevent losing 1st rx packet intermittently */
10715                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
10716                         tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10717                         udelay(10);
10718                         tw32_f(MAC_RX_MODE, tp->rx_mode);
10719                 }
10720                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
10721                         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)
10722                                 mac_mode &= ~MAC_MODE_LINK_POLARITY;
10723                         else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411)
10724                                 mac_mode |= MAC_MODE_LINK_POLARITY;
10725                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
10726                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
10727                 }
10728                 tw32(MAC_MODE, mac_mode);
10729         }
10730         else
10731                 return -EINVAL;
10732
10733         err = -EIO;
10734
10735         tx_len = 1514;
10736         skb = netdev_alloc_skb(tp->dev, tx_len);
10737         if (!skb)
10738                 return -ENOMEM;
10739
10740         tx_data = skb_put(skb, tx_len);
10741         memcpy(tx_data, tp->dev->dev_addr, 6);
10742         memset(tx_data + 6, 0x0, 8);
10743
10744         tw32(MAC_RX_MTU_SIZE, tx_len + 4);
10745
10746         for (i = 14; i < tx_len; i++)
10747                 tx_data[i] = (u8) (i & 0xff);
10748
10749         map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
10750         if (pci_dma_mapping_error(tp->pdev, map)) {
10751                 dev_kfree_skb(skb);
10752                 return -EIO;
10753         }
10754
10755         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10756                rnapi->coal_now);
10757
10758         udelay(10);
10759
10760         rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
10761
10762         num_pkts = 0;
10763
10764         tg3_set_txd(tnapi, tnapi->tx_prod, map, tx_len, 0, 1);
10765
10766         tnapi->tx_prod++;
10767         num_pkts++;
10768
10769         tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
10770         tr32_mailbox(tnapi->prodmbox);
10771
10772         udelay(10);
10773
10774         /* 350 usec to allow enough time on some 10/100 Mbps devices.  */
10775         for (i = 0; i < 35; i++) {
10776                 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10777                        coal_now);
10778
10779                 udelay(10);
10780
10781                 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
10782                 rx_idx = rnapi->hw_status->idx[0].rx_producer;
10783                 if ((tx_idx == tnapi->tx_prod) &&
10784                     (rx_idx == (rx_start_idx + num_pkts)))
10785                         break;
10786         }
10787
10788         pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
10789         dev_kfree_skb(skb);
10790
10791         if (tx_idx != tnapi->tx_prod)
10792                 goto out;
10793
10794         if (rx_idx != rx_start_idx + num_pkts)
10795                 goto out;
10796
10797         desc = &rnapi->rx_rcb[rx_start_idx];
10798         desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
10799         opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
10800         if (opaque_key != RXD_OPAQUE_RING_STD)
10801                 goto out;
10802
10803         if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
10804             (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
10805                 goto out;
10806
10807         rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
10808         if (rx_len != tx_len)
10809                 goto out;
10810
10811         rx_skb = tpr->rx_std_buffers[desc_idx].skb;
10812
10813         map = pci_unmap_addr(&tpr->rx_std_buffers[desc_idx], mapping);
10814         pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
10815
10816         for (i = 14; i < tx_len; i++) {
10817                 if (*(rx_skb->data + i) != (u8) (i & 0xff))
10818                         goto out;
10819         }
10820         err = 0;
10821
10822         /* tg3_free_rings will unmap and free the rx_skb */
10823 out:
10824         return err;
10825 }
10826
10827 #define TG3_MAC_LOOPBACK_FAILED         1
10828 #define TG3_PHY_LOOPBACK_FAILED         2
10829 #define TG3_LOOPBACK_FAILED             (TG3_MAC_LOOPBACK_FAILED |      \
10830                                          TG3_PHY_LOOPBACK_FAILED)
10831
10832 static int tg3_test_loopback(struct tg3 *tp)
10833 {
10834         int err = 0;
10835         u32 cpmuctrl = 0;
10836
10837         if (!netif_running(tp->dev))
10838                 return TG3_LOOPBACK_FAILED;
10839
10840         err = tg3_reset_hw(tp, 1);
10841         if (err)
10842                 return TG3_LOOPBACK_FAILED;
10843
10844         /* Turn off gphy autopowerdown. */
10845         if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10846                 tg3_phy_toggle_apd(tp, false);
10847
10848         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
10849                 int i;
10850                 u32 status;
10851
10852                 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
10853
10854                 /* Wait for up to 40 microseconds to acquire lock. */
10855                 for (i = 0; i < 4; i++) {
10856                         status = tr32(TG3_CPMU_MUTEX_GNT);
10857                         if (status == CPMU_MUTEX_GNT_DRIVER)
10858                                 break;
10859                         udelay(10);
10860                 }
10861
10862                 if (status != CPMU_MUTEX_GNT_DRIVER)
10863                         return TG3_LOOPBACK_FAILED;
10864
10865                 /* Turn off link-based power management. */
10866                 cpmuctrl = tr32(TG3_CPMU_CTRL);
10867                 tw32(TG3_CPMU_CTRL,
10868                      cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
10869                                   CPMU_CTRL_LINK_AWARE_MODE));
10870         }
10871
10872         if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
10873                 err |= TG3_MAC_LOOPBACK_FAILED;
10874
10875         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
10876                 tw32(TG3_CPMU_CTRL, cpmuctrl);
10877
10878                 /* Release the mutex */
10879                 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
10880         }
10881
10882         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
10883             !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
10884                 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
10885                         err |= TG3_PHY_LOOPBACK_FAILED;
10886         }
10887
10888         /* Re-enable gphy autopowerdown. */
10889         if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10890                 tg3_phy_toggle_apd(tp, true);
10891
10892         return err;
10893 }
10894
10895 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
10896                           u64 *data)
10897 {
10898         struct tg3 *tp = netdev_priv(dev);
10899
10900         if (tp->link_config.phy_is_low_power)
10901                 tg3_set_power_state(tp, PCI_D0);
10902
10903         memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
10904
10905         if (tg3_test_nvram(tp) != 0) {
10906                 etest->flags |= ETH_TEST_FL_FAILED;
10907                 data[0] = 1;
10908         }
10909         if (tg3_test_link(tp) != 0) {
10910                 etest->flags |= ETH_TEST_FL_FAILED;
10911                 data[1] = 1;
10912         }
10913         if (etest->flags & ETH_TEST_FL_OFFLINE) {
10914                 int err, err2 = 0, irq_sync = 0;
10915
10916                 if (netif_running(dev)) {
10917                         tg3_phy_stop(tp);
10918                         tg3_netif_stop(tp);
10919                         irq_sync = 1;
10920                 }
10921
10922                 tg3_full_lock(tp, irq_sync);
10923
10924                 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
10925                 err = tg3_nvram_lock(tp);
10926                 tg3_halt_cpu(tp, RX_CPU_BASE);
10927                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10928                         tg3_halt_cpu(tp, TX_CPU_BASE);
10929                 if (!err)
10930                         tg3_nvram_unlock(tp);
10931
10932                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
10933                         tg3_phy_reset(tp);
10934
10935                 if (tg3_test_registers(tp) != 0) {
10936                         etest->flags |= ETH_TEST_FL_FAILED;
10937                         data[2] = 1;
10938                 }
10939                 if (tg3_test_memory(tp) != 0) {
10940                         etest->flags |= ETH_TEST_FL_FAILED;
10941                         data[3] = 1;
10942                 }
10943                 if ((data[4] = tg3_test_loopback(tp)) != 0)
10944                         etest->flags |= ETH_TEST_FL_FAILED;
10945
10946                 tg3_full_unlock(tp);
10947
10948                 if (tg3_test_interrupt(tp) != 0) {
10949                         etest->flags |= ETH_TEST_FL_FAILED;
10950                         data[5] = 1;
10951                 }
10952
10953                 tg3_full_lock(tp, 0);
10954
10955                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10956                 if (netif_running(dev)) {
10957                         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
10958                         err2 = tg3_restart_hw(tp, 1);
10959                         if (!err2)
10960                                 tg3_netif_start(tp);
10961                 }
10962
10963                 tg3_full_unlock(tp);
10964
10965                 if (irq_sync && !err2)
10966                         tg3_phy_start(tp);
10967         }
10968         if (tp->link_config.phy_is_low_power)
10969                 tg3_set_power_state(tp, PCI_D3hot);
10970
10971 }
10972
10973 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
10974 {
10975         struct mii_ioctl_data *data = if_mii(ifr);
10976         struct tg3 *tp = netdev_priv(dev);
10977         int err;
10978
10979         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
10980                 struct phy_device *phydev;
10981                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
10982                         return -EAGAIN;
10983                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
10984                 return phy_mii_ioctl(phydev, data, cmd);
10985         }
10986
10987         switch(cmd) {
10988         case SIOCGMIIPHY:
10989                 data->phy_id = tp->phy_addr;
10990
10991                 /* fallthru */
10992         case SIOCGMIIREG: {
10993                 u32 mii_regval;
10994
10995                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10996                         break;                  /* We have no PHY */
10997
10998                 if (tp->link_config.phy_is_low_power)
10999                         return -EAGAIN;
11000
11001                 spin_lock_bh(&tp->lock);
11002                 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
11003                 spin_unlock_bh(&tp->lock);
11004
11005                 data->val_out = mii_regval;
11006
11007                 return err;
11008         }
11009
11010         case SIOCSMIIREG:
11011                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
11012                         break;                  /* We have no PHY */
11013
11014                 if (tp->link_config.phy_is_low_power)
11015                         return -EAGAIN;
11016
11017                 spin_lock_bh(&tp->lock);
11018                 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
11019                 spin_unlock_bh(&tp->lock);
11020
11021                 return err;
11022
11023         default:
11024                 /* do nothing */
11025                 break;
11026         }
11027         return -EOPNOTSUPP;
11028 }
11029
11030 #if TG3_VLAN_TAG_USED
11031 static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
11032 {
11033         struct tg3 *tp = netdev_priv(dev);
11034
11035         if (!netif_running(dev)) {
11036                 tp->vlgrp = grp;
11037                 return;
11038         }
11039
11040         tg3_netif_stop(tp);
11041
11042         tg3_full_lock(tp, 0);
11043
11044         tp->vlgrp = grp;
11045
11046         /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
11047         __tg3_set_rx_mode(dev);
11048
11049         tg3_netif_start(tp);
11050
11051         tg3_full_unlock(tp);
11052 }
11053 #endif
11054
11055 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11056 {
11057         struct tg3 *tp = netdev_priv(dev);
11058
11059         memcpy(ec, &tp->coal, sizeof(*ec));
11060         return 0;
11061 }
11062
11063 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11064 {
11065         struct tg3 *tp = netdev_priv(dev);
11066         u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
11067         u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
11068
11069         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
11070                 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
11071                 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
11072                 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
11073                 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
11074         }
11075
11076         if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
11077             (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
11078             (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
11079             (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
11080             (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
11081             (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
11082             (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
11083             (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
11084             (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
11085             (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
11086                 return -EINVAL;
11087
11088         /* No rx interrupts will be generated if both are zero */
11089         if ((ec->rx_coalesce_usecs == 0) &&
11090             (ec->rx_max_coalesced_frames == 0))
11091                 return -EINVAL;
11092
11093         /* No tx interrupts will be generated if both are zero */
11094         if ((ec->tx_coalesce_usecs == 0) &&
11095             (ec->tx_max_coalesced_frames == 0))
11096                 return -EINVAL;
11097
11098         /* Only copy relevant parameters, ignore all others. */
11099         tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
11100         tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
11101         tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
11102         tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
11103         tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
11104         tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
11105         tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
11106         tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
11107         tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
11108
11109         if (netif_running(dev)) {
11110                 tg3_full_lock(tp, 0);
11111                 __tg3_set_coalesce(tp, &tp->coal);
11112                 tg3_full_unlock(tp);
11113         }
11114         return 0;
11115 }
11116
11117 static const struct ethtool_ops tg3_ethtool_ops = {
11118         .get_settings           = tg3_get_settings,
11119         .set_settings           = tg3_set_settings,
11120         .get_drvinfo            = tg3_get_drvinfo,
11121         .get_regs_len           = tg3_get_regs_len,
11122         .get_regs               = tg3_get_regs,
11123         .get_wol                = tg3_get_wol,
11124         .set_wol                = tg3_set_wol,
11125         .get_msglevel           = tg3_get_msglevel,
11126         .set_msglevel           = tg3_set_msglevel,
11127         .nway_reset             = tg3_nway_reset,
11128         .get_link               = ethtool_op_get_link,
11129         .get_eeprom_len         = tg3_get_eeprom_len,
11130         .get_eeprom             = tg3_get_eeprom,
11131         .set_eeprom             = tg3_set_eeprom,
11132         .get_ringparam          = tg3_get_ringparam,
11133         .set_ringparam          = tg3_set_ringparam,
11134         .get_pauseparam         = tg3_get_pauseparam,
11135         .set_pauseparam         = tg3_set_pauseparam,
11136         .get_rx_csum            = tg3_get_rx_csum,
11137         .set_rx_csum            = tg3_set_rx_csum,
11138         .set_tx_csum            = tg3_set_tx_csum,
11139         .set_sg                 = ethtool_op_set_sg,
11140         .set_tso                = tg3_set_tso,
11141         .self_test              = tg3_self_test,
11142         .get_strings            = tg3_get_strings,
11143         .phys_id                = tg3_phys_id,
11144         .get_ethtool_stats      = tg3_get_ethtool_stats,
11145         .get_coalesce           = tg3_get_coalesce,
11146         .set_coalesce           = tg3_set_coalesce,
11147         .get_sset_count         = tg3_get_sset_count,
11148 };
11149
11150 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
11151 {
11152         u32 cursize, val, magic;
11153
11154         tp->nvram_size = EEPROM_CHIP_SIZE;
11155
11156         if (tg3_nvram_read(tp, 0, &magic) != 0)
11157                 return;
11158
11159         if ((magic != TG3_EEPROM_MAGIC) &&
11160             ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
11161             ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
11162                 return;
11163
11164         /*
11165          * Size the chip by reading offsets at increasing powers of two.
11166          * When we encounter our validation signature, we know the addressing
11167          * has wrapped around, and thus have our chip size.
11168          */
11169         cursize = 0x10;
11170
11171         while (cursize < tp->nvram_size) {
11172                 if (tg3_nvram_read(tp, cursize, &val) != 0)
11173                         return;
11174
11175                 if (val == magic)
11176                         break;
11177
11178                 cursize <<= 1;
11179         }
11180
11181         tp->nvram_size = cursize;
11182 }
11183
11184 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
11185 {
11186         u32 val;
11187
11188         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
11189             tg3_nvram_read(tp, 0, &val) != 0)
11190                 return;
11191
11192         /* Selfboot format */
11193         if (val != TG3_EEPROM_MAGIC) {
11194                 tg3_get_eeprom_size(tp);
11195                 return;
11196         }
11197
11198         if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
11199                 if (val != 0) {
11200                         /* This is confusing.  We want to operate on the
11201                          * 16-bit value at offset 0xf2.  The tg3_nvram_read()
11202                          * call will read from NVRAM and byteswap the data
11203                          * according to the byteswapping settings for all
11204                          * other register accesses.  This ensures the data we
11205                          * want will always reside in the lower 16-bits.
11206                          * However, the data in NVRAM is in LE format, which
11207                          * means the data from the NVRAM read will always be
11208                          * opposite the endianness of the CPU.  The 16-bit
11209                          * byteswap then brings the data to CPU endianness.
11210                          */
11211                         tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
11212                         return;
11213                 }
11214         }
11215         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11216 }
11217
11218 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
11219 {
11220         u32 nvcfg1;
11221
11222         nvcfg1 = tr32(NVRAM_CFG1);
11223         if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
11224                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11225         } else {
11226                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11227                 tw32(NVRAM_CFG1, nvcfg1);
11228         }
11229
11230         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
11231             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
11232                 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
11233                 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
11234                         tp->nvram_jedecnum = JEDEC_ATMEL;
11235                         tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11236                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11237                         break;
11238                 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
11239                         tp->nvram_jedecnum = JEDEC_ATMEL;
11240                         tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
11241                         break;
11242                 case FLASH_VENDOR_ATMEL_EEPROM:
11243                         tp->nvram_jedecnum = JEDEC_ATMEL;
11244                         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11245                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11246                         break;
11247                 case FLASH_VENDOR_ST:
11248                         tp->nvram_jedecnum = JEDEC_ST;
11249                         tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
11250                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11251                         break;
11252                 case FLASH_VENDOR_SAIFUN:
11253                         tp->nvram_jedecnum = JEDEC_SAIFUN;
11254                         tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
11255                         break;
11256                 case FLASH_VENDOR_SST_SMALL:
11257                 case FLASH_VENDOR_SST_LARGE:
11258                         tp->nvram_jedecnum = JEDEC_SST;
11259                         tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
11260                         break;
11261                 }
11262         } else {
11263                 tp->nvram_jedecnum = JEDEC_ATMEL;
11264                 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11265                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11266         }
11267 }
11268
11269 static void __devinit tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
11270 {
11271         switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
11272         case FLASH_5752PAGE_SIZE_256:
11273                 tp->nvram_pagesize = 256;
11274                 break;
11275         case FLASH_5752PAGE_SIZE_512:
11276                 tp->nvram_pagesize = 512;
11277                 break;
11278         case FLASH_5752PAGE_SIZE_1K:
11279                 tp->nvram_pagesize = 1024;
11280                 break;
11281         case FLASH_5752PAGE_SIZE_2K:
11282                 tp->nvram_pagesize = 2048;
11283                 break;
11284         case FLASH_5752PAGE_SIZE_4K:
11285                 tp->nvram_pagesize = 4096;
11286                 break;
11287         case FLASH_5752PAGE_SIZE_264:
11288                 tp->nvram_pagesize = 264;
11289                 break;
11290         case FLASH_5752PAGE_SIZE_528:
11291                 tp->nvram_pagesize = 528;
11292                 break;
11293         }
11294 }
11295
11296 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
11297 {
11298         u32 nvcfg1;
11299
11300         nvcfg1 = tr32(NVRAM_CFG1);
11301
11302         /* NVRAM protection for TPM */
11303         if (nvcfg1 & (1 << 27))
11304                 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11305
11306         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11307         case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
11308         case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
11309                 tp->nvram_jedecnum = JEDEC_ATMEL;
11310                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11311                 break;
11312         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11313                 tp->nvram_jedecnum = JEDEC_ATMEL;
11314                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11315                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11316                 break;
11317         case FLASH_5752VENDOR_ST_M45PE10:
11318         case FLASH_5752VENDOR_ST_M45PE20:
11319         case FLASH_5752VENDOR_ST_M45PE40:
11320                 tp->nvram_jedecnum = JEDEC_ST;
11321                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11322                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11323                 break;
11324         }
11325
11326         if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
11327                 tg3_nvram_get_pagesize(tp, nvcfg1);
11328         } else {
11329                 /* For eeprom, set pagesize to maximum eeprom size */
11330                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11331
11332                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11333                 tw32(NVRAM_CFG1, nvcfg1);
11334         }
11335 }
11336
11337 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
11338 {
11339         u32 nvcfg1, protect = 0;
11340
11341         nvcfg1 = tr32(NVRAM_CFG1);
11342
11343         /* NVRAM protection for TPM */
11344         if (nvcfg1 & (1 << 27)) {
11345                 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11346                 protect = 1;
11347         }
11348
11349         nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11350         switch (nvcfg1) {
11351         case FLASH_5755VENDOR_ATMEL_FLASH_1:
11352         case FLASH_5755VENDOR_ATMEL_FLASH_2:
11353         case FLASH_5755VENDOR_ATMEL_FLASH_3:
11354         case FLASH_5755VENDOR_ATMEL_FLASH_5:
11355                 tp->nvram_jedecnum = JEDEC_ATMEL;
11356                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11357                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11358                 tp->nvram_pagesize = 264;
11359                 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
11360                     nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
11361                         tp->nvram_size = (protect ? 0x3e200 :
11362                                           TG3_NVRAM_SIZE_512KB);
11363                 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
11364                         tp->nvram_size = (protect ? 0x1f200 :
11365                                           TG3_NVRAM_SIZE_256KB);
11366                 else
11367                         tp->nvram_size = (protect ? 0x1f200 :
11368                                           TG3_NVRAM_SIZE_128KB);
11369                 break;
11370         case FLASH_5752VENDOR_ST_M45PE10:
11371         case FLASH_5752VENDOR_ST_M45PE20:
11372         case FLASH_5752VENDOR_ST_M45PE40:
11373                 tp->nvram_jedecnum = JEDEC_ST;
11374                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11375                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11376                 tp->nvram_pagesize = 256;
11377                 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
11378                         tp->nvram_size = (protect ?
11379                                           TG3_NVRAM_SIZE_64KB :
11380                                           TG3_NVRAM_SIZE_128KB);
11381                 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
11382                         tp->nvram_size = (protect ?
11383                                           TG3_NVRAM_SIZE_64KB :
11384                                           TG3_NVRAM_SIZE_256KB);
11385                 else
11386                         tp->nvram_size = (protect ?
11387                                           TG3_NVRAM_SIZE_128KB :
11388                                           TG3_NVRAM_SIZE_512KB);
11389                 break;
11390         }
11391 }
11392
11393 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
11394 {
11395         u32 nvcfg1;
11396
11397         nvcfg1 = tr32(NVRAM_CFG1);
11398
11399         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11400         case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
11401         case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11402         case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
11403         case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11404                 tp->nvram_jedecnum = JEDEC_ATMEL;
11405                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11406                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11407
11408                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11409                 tw32(NVRAM_CFG1, nvcfg1);
11410                 break;
11411         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11412         case FLASH_5755VENDOR_ATMEL_FLASH_1:
11413         case FLASH_5755VENDOR_ATMEL_FLASH_2:
11414         case FLASH_5755VENDOR_ATMEL_FLASH_3:
11415                 tp->nvram_jedecnum = JEDEC_ATMEL;
11416                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11417                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11418                 tp->nvram_pagesize = 264;
11419                 break;
11420         case FLASH_5752VENDOR_ST_M45PE10:
11421         case FLASH_5752VENDOR_ST_M45PE20:
11422         case FLASH_5752VENDOR_ST_M45PE40:
11423                 tp->nvram_jedecnum = JEDEC_ST;
11424                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11425                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11426                 tp->nvram_pagesize = 256;
11427                 break;
11428         }
11429 }
11430
11431 static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
11432 {
11433         u32 nvcfg1, protect = 0;
11434
11435         nvcfg1 = tr32(NVRAM_CFG1);
11436
11437         /* NVRAM protection for TPM */
11438         if (nvcfg1 & (1 << 27)) {
11439                 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11440                 protect = 1;
11441         }
11442
11443         nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11444         switch (nvcfg1) {
11445         case FLASH_5761VENDOR_ATMEL_ADB021D:
11446         case FLASH_5761VENDOR_ATMEL_ADB041D:
11447         case FLASH_5761VENDOR_ATMEL_ADB081D:
11448         case FLASH_5761VENDOR_ATMEL_ADB161D:
11449         case FLASH_5761VENDOR_ATMEL_MDB021D:
11450         case FLASH_5761VENDOR_ATMEL_MDB041D:
11451         case FLASH_5761VENDOR_ATMEL_MDB081D:
11452         case FLASH_5761VENDOR_ATMEL_MDB161D:
11453                 tp->nvram_jedecnum = JEDEC_ATMEL;
11454                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11455                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11456                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11457                 tp->nvram_pagesize = 256;
11458                 break;
11459         case FLASH_5761VENDOR_ST_A_M45PE20:
11460         case FLASH_5761VENDOR_ST_A_M45PE40:
11461         case FLASH_5761VENDOR_ST_A_M45PE80:
11462         case FLASH_5761VENDOR_ST_A_M45PE16:
11463         case FLASH_5761VENDOR_ST_M_M45PE20:
11464         case FLASH_5761VENDOR_ST_M_M45PE40:
11465         case FLASH_5761VENDOR_ST_M_M45PE80:
11466         case FLASH_5761VENDOR_ST_M_M45PE16:
11467                 tp->nvram_jedecnum = JEDEC_ST;
11468                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11469                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11470                 tp->nvram_pagesize = 256;
11471                 break;
11472         }
11473
11474         if (protect) {
11475                 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
11476         } else {
11477                 switch (nvcfg1) {
11478                 case FLASH_5761VENDOR_ATMEL_ADB161D:
11479                 case FLASH_5761VENDOR_ATMEL_MDB161D:
11480                 case FLASH_5761VENDOR_ST_A_M45PE16:
11481                 case FLASH_5761VENDOR_ST_M_M45PE16:
11482                         tp->nvram_size = TG3_NVRAM_SIZE_2MB;
11483                         break;
11484                 case FLASH_5761VENDOR_ATMEL_ADB081D:
11485                 case FLASH_5761VENDOR_ATMEL_MDB081D:
11486                 case FLASH_5761VENDOR_ST_A_M45PE80:
11487                 case FLASH_5761VENDOR_ST_M_M45PE80:
11488                         tp->nvram_size = TG3_NVRAM_SIZE_1MB;
11489                         break;
11490                 case FLASH_5761VENDOR_ATMEL_ADB041D:
11491                 case FLASH_5761VENDOR_ATMEL_MDB041D:
11492                 case FLASH_5761VENDOR_ST_A_M45PE40:
11493                 case FLASH_5761VENDOR_ST_M_M45PE40:
11494                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11495                         break;
11496                 case FLASH_5761VENDOR_ATMEL_ADB021D:
11497                 case FLASH_5761VENDOR_ATMEL_MDB021D:
11498                 case FLASH_5761VENDOR_ST_A_M45PE20:
11499                 case FLASH_5761VENDOR_ST_M_M45PE20:
11500                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11501                         break;
11502                 }
11503         }
11504 }
11505
11506 static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
11507 {
11508         tp->nvram_jedecnum = JEDEC_ATMEL;
11509         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11510         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11511 }
11512
11513 static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
11514 {
11515         u32 nvcfg1;
11516
11517         nvcfg1 = tr32(NVRAM_CFG1);
11518
11519         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11520         case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11521         case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11522                 tp->nvram_jedecnum = JEDEC_ATMEL;
11523                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11524                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11525
11526                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11527                 tw32(NVRAM_CFG1, nvcfg1);
11528                 return;
11529         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11530         case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11531         case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11532         case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11533         case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11534         case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11535         case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11536                 tp->nvram_jedecnum = JEDEC_ATMEL;
11537                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11538                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11539
11540                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11541                 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11542                 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11543                 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11544                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11545                         break;
11546                 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11547                 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11548                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11549                         break;
11550                 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11551                 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11552                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11553                         break;
11554                 }
11555                 break;
11556         case FLASH_5752VENDOR_ST_M45PE10:
11557         case FLASH_5752VENDOR_ST_M45PE20:
11558         case FLASH_5752VENDOR_ST_M45PE40:
11559                 tp->nvram_jedecnum = JEDEC_ST;
11560                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11561                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11562
11563                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11564                 case FLASH_5752VENDOR_ST_M45PE10:
11565                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11566                         break;
11567                 case FLASH_5752VENDOR_ST_M45PE20:
11568                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11569                         break;
11570                 case FLASH_5752VENDOR_ST_M45PE40:
11571                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11572                         break;
11573                 }
11574                 break;
11575         default:
11576                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11577                 return;
11578         }
11579
11580         tg3_nvram_get_pagesize(tp, nvcfg1);
11581         if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11582                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11583 }
11584
11585
11586 static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp)
11587 {
11588         u32 nvcfg1;
11589
11590         nvcfg1 = tr32(NVRAM_CFG1);
11591
11592         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11593         case FLASH_5717VENDOR_ATMEL_EEPROM:
11594         case FLASH_5717VENDOR_MICRO_EEPROM:
11595                 tp->nvram_jedecnum = JEDEC_ATMEL;
11596                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11597                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11598
11599                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11600                 tw32(NVRAM_CFG1, nvcfg1);
11601                 return;
11602         case FLASH_5717VENDOR_ATMEL_MDB011D:
11603         case FLASH_5717VENDOR_ATMEL_ADB011B:
11604         case FLASH_5717VENDOR_ATMEL_ADB011D:
11605         case FLASH_5717VENDOR_ATMEL_MDB021D:
11606         case FLASH_5717VENDOR_ATMEL_ADB021B:
11607         case FLASH_5717VENDOR_ATMEL_ADB021D:
11608         case FLASH_5717VENDOR_ATMEL_45USPT:
11609                 tp->nvram_jedecnum = JEDEC_ATMEL;
11610                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11611                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11612
11613                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11614                 case FLASH_5717VENDOR_ATMEL_MDB021D:
11615                 case FLASH_5717VENDOR_ATMEL_ADB021B:
11616                 case FLASH_5717VENDOR_ATMEL_ADB021D:
11617                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11618                         break;
11619                 default:
11620                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11621                         break;
11622                 }
11623                 break;
11624         case FLASH_5717VENDOR_ST_M_M25PE10:
11625         case FLASH_5717VENDOR_ST_A_M25PE10:
11626         case FLASH_5717VENDOR_ST_M_M45PE10:
11627         case FLASH_5717VENDOR_ST_A_M45PE10:
11628         case FLASH_5717VENDOR_ST_M_M25PE20:
11629         case FLASH_5717VENDOR_ST_A_M25PE20:
11630         case FLASH_5717VENDOR_ST_M_M45PE20:
11631         case FLASH_5717VENDOR_ST_A_M45PE20:
11632         case FLASH_5717VENDOR_ST_25USPT:
11633         case FLASH_5717VENDOR_ST_45USPT:
11634                 tp->nvram_jedecnum = JEDEC_ST;
11635                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11636                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11637
11638                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11639                 case FLASH_5717VENDOR_ST_M_M25PE20:
11640                 case FLASH_5717VENDOR_ST_A_M25PE20:
11641                 case FLASH_5717VENDOR_ST_M_M45PE20:
11642                 case FLASH_5717VENDOR_ST_A_M45PE20:
11643                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11644                         break;
11645                 default:
11646                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11647                         break;
11648                 }
11649                 break;
11650         default:
11651                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11652                 return;
11653         }
11654
11655         tg3_nvram_get_pagesize(tp, nvcfg1);
11656         if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11657                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11658 }
11659
11660 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
11661 static void __devinit tg3_nvram_init(struct tg3 *tp)
11662 {
11663         tw32_f(GRC_EEPROM_ADDR,
11664              (EEPROM_ADDR_FSM_RESET |
11665               (EEPROM_DEFAULT_CLOCK_PERIOD <<
11666                EEPROM_ADDR_CLKPERD_SHIFT)));
11667
11668         msleep(1);
11669
11670         /* Enable seeprom accesses. */
11671         tw32_f(GRC_LOCAL_CTRL,
11672              tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
11673         udelay(100);
11674
11675         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11676             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
11677                 tp->tg3_flags |= TG3_FLAG_NVRAM;
11678
11679                 if (tg3_nvram_lock(tp)) {
11680                         printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
11681                                "tg3_nvram_init failed.\n", tp->dev->name);
11682                         return;
11683                 }
11684                 tg3_enable_nvram_access(tp);
11685
11686                 tp->nvram_size = 0;
11687
11688                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
11689                         tg3_get_5752_nvram_info(tp);
11690                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
11691                         tg3_get_5755_nvram_info(tp);
11692                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
11693                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11694                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11695                         tg3_get_5787_nvram_info(tp);
11696                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
11697                         tg3_get_5761_nvram_info(tp);
11698                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11699                         tg3_get_5906_nvram_info(tp);
11700                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
11701                         tg3_get_57780_nvram_info(tp);
11702                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
11703                         tg3_get_5717_nvram_info(tp);
11704                 else
11705                         tg3_get_nvram_info(tp);
11706
11707                 if (tp->nvram_size == 0)
11708                         tg3_get_nvram_size(tp);
11709
11710                 tg3_disable_nvram_access(tp);
11711                 tg3_nvram_unlock(tp);
11712
11713         } else {
11714                 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
11715
11716                 tg3_get_eeprom_size(tp);
11717         }
11718 }
11719
11720 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
11721                                     u32 offset, u32 len, u8 *buf)
11722 {
11723         int i, j, rc = 0;
11724         u32 val;
11725
11726         for (i = 0; i < len; i += 4) {
11727                 u32 addr;
11728                 __be32 data;
11729
11730                 addr = offset + i;
11731
11732                 memcpy(&data, buf + i, 4);
11733
11734                 /*
11735                  * The SEEPROM interface expects the data to always be opposite
11736                  * the native endian format.  We accomplish this by reversing
11737                  * all the operations that would have been performed on the
11738                  * data from a call to tg3_nvram_read_be32().
11739                  */
11740                 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
11741
11742                 val = tr32(GRC_EEPROM_ADDR);
11743                 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
11744
11745                 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
11746                         EEPROM_ADDR_READ);
11747                 tw32(GRC_EEPROM_ADDR, val |
11748                         (0 << EEPROM_ADDR_DEVID_SHIFT) |
11749                         (addr & EEPROM_ADDR_ADDR_MASK) |
11750                         EEPROM_ADDR_START |
11751                         EEPROM_ADDR_WRITE);
11752
11753                 for (j = 0; j < 1000; j++) {
11754                         val = tr32(GRC_EEPROM_ADDR);
11755
11756                         if (val & EEPROM_ADDR_COMPLETE)
11757                                 break;
11758                         msleep(1);
11759                 }
11760                 if (!(val & EEPROM_ADDR_COMPLETE)) {
11761                         rc = -EBUSY;
11762                         break;
11763                 }
11764         }
11765
11766         return rc;
11767 }
11768
11769 /* offset and length are dword aligned */
11770 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
11771                 u8 *buf)
11772 {
11773         int ret = 0;
11774         u32 pagesize = tp->nvram_pagesize;
11775         u32 pagemask = pagesize - 1;
11776         u32 nvram_cmd;
11777         u8 *tmp;
11778
11779         tmp = kmalloc(pagesize, GFP_KERNEL);
11780         if (tmp == NULL)
11781                 return -ENOMEM;
11782
11783         while (len) {
11784                 int j;
11785                 u32 phy_addr, page_off, size;
11786
11787                 phy_addr = offset & ~pagemask;
11788
11789                 for (j = 0; j < pagesize; j += 4) {
11790                         ret = tg3_nvram_read_be32(tp, phy_addr + j,
11791                                                   (__be32 *) (tmp + j));
11792                         if (ret)
11793                                 break;
11794                 }
11795                 if (ret)
11796                         break;
11797
11798                 page_off = offset & pagemask;
11799                 size = pagesize;
11800                 if (len < size)
11801                         size = len;
11802
11803                 len -= size;
11804
11805                 memcpy(tmp + page_off, buf, size);
11806
11807                 offset = offset + (pagesize - page_off);
11808
11809                 tg3_enable_nvram_access(tp);
11810
11811                 /*
11812                  * Before we can erase the flash page, we need
11813                  * to issue a special "write enable" command.
11814                  */
11815                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11816
11817                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11818                         break;
11819
11820                 /* Erase the target page */
11821                 tw32(NVRAM_ADDR, phy_addr);
11822
11823                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
11824                         NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
11825
11826                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11827                         break;
11828
11829                 /* Issue another write enable to start the write. */
11830                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11831
11832                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11833                         break;
11834
11835                 for (j = 0; j < pagesize; j += 4) {
11836                         __be32 data;
11837
11838                         data = *((__be32 *) (tmp + j));
11839
11840                         tw32(NVRAM_WRDATA, be32_to_cpu(data));
11841
11842                         tw32(NVRAM_ADDR, phy_addr + j);
11843
11844                         nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
11845                                 NVRAM_CMD_WR;
11846
11847                         if (j == 0)
11848                                 nvram_cmd |= NVRAM_CMD_FIRST;
11849                         else if (j == (pagesize - 4))
11850                                 nvram_cmd |= NVRAM_CMD_LAST;
11851
11852                         if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11853                                 break;
11854                 }
11855                 if (ret)
11856                         break;
11857         }
11858
11859         nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11860         tg3_nvram_exec_cmd(tp, nvram_cmd);
11861
11862         kfree(tmp);
11863
11864         return ret;
11865 }
11866
11867 /* offset and length are dword aligned */
11868 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
11869                 u8 *buf)
11870 {
11871         int i, ret = 0;
11872
11873         for (i = 0; i < len; i += 4, offset += 4) {
11874                 u32 page_off, phy_addr, nvram_cmd;
11875                 __be32 data;
11876
11877                 memcpy(&data, buf + i, 4);
11878                 tw32(NVRAM_WRDATA, be32_to_cpu(data));
11879
11880                 page_off = offset % tp->nvram_pagesize;
11881
11882                 phy_addr = tg3_nvram_phys_addr(tp, offset);
11883
11884                 tw32(NVRAM_ADDR, phy_addr);
11885
11886                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
11887
11888                 if ((page_off == 0) || (i == 0))
11889                         nvram_cmd |= NVRAM_CMD_FIRST;
11890                 if (page_off == (tp->nvram_pagesize - 4))
11891                         nvram_cmd |= NVRAM_CMD_LAST;
11892
11893                 if (i == (len - 4))
11894                         nvram_cmd |= NVRAM_CMD_LAST;
11895
11896                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
11897                     !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
11898                     (tp->nvram_jedecnum == JEDEC_ST) &&
11899                     (nvram_cmd & NVRAM_CMD_FIRST)) {
11900
11901                         if ((ret = tg3_nvram_exec_cmd(tp,
11902                                 NVRAM_CMD_WREN | NVRAM_CMD_GO |
11903                                 NVRAM_CMD_DONE)))
11904
11905                                 break;
11906                 }
11907                 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11908                         /* We always do complete word writes to eeprom. */
11909                         nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
11910                 }
11911
11912                 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11913                         break;
11914         }
11915         return ret;
11916 }
11917
11918 /* offset and length are dword aligned */
11919 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
11920 {
11921         int ret;
11922
11923         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
11924                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
11925                        ~GRC_LCLCTRL_GPIO_OUTPUT1);
11926                 udelay(40);
11927         }
11928
11929         if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
11930                 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
11931         }
11932         else {
11933                 u32 grc_mode;
11934
11935                 ret = tg3_nvram_lock(tp);
11936                 if (ret)
11937                         return ret;
11938
11939                 tg3_enable_nvram_access(tp);
11940                 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
11941                     !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM))
11942                         tw32(NVRAM_WRITE1, 0x406);
11943
11944                 grc_mode = tr32(GRC_MODE);
11945                 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
11946
11947                 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
11948                         !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11949
11950                         ret = tg3_nvram_write_block_buffered(tp, offset, len,
11951                                 buf);
11952                 }
11953                 else {
11954                         ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
11955                                 buf);
11956                 }
11957
11958                 grc_mode = tr32(GRC_MODE);
11959                 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
11960
11961                 tg3_disable_nvram_access(tp);
11962                 tg3_nvram_unlock(tp);
11963         }
11964
11965         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
11966                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
11967                 udelay(40);
11968         }
11969
11970         return ret;
11971 }
11972
11973 struct subsys_tbl_ent {
11974         u16 subsys_vendor, subsys_devid;
11975         u32 phy_id;
11976 };
11977
11978 static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
11979         /* Broadcom boards. */
11980         { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
11981         { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
11982         { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
11983         { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 },              /* BCM95700A9 */
11984         { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
11985         { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
11986         { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 },              /* BCM95701A7 */
11987         { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
11988         { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
11989         { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
11990         { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
11991
11992         /* 3com boards. */
11993         { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
11994         { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
11995         { PCI_VENDOR_ID_3COM, 0x1004, 0 },              /* 3C996SX */
11996         { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
11997         { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
11998
11999         /* DELL boards. */
12000         { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
12001         { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
12002         { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
12003         { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
12004
12005         /* Compaq boards. */
12006         { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
12007         { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
12008         { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 },              /* CHANGELING */
12009         { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
12010         { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
12011
12012         /* IBM boards. */
12013         { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
12014 };
12015
12016 static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
12017 {
12018         int i;
12019
12020         for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
12021                 if ((subsys_id_to_phy_id[i].subsys_vendor ==
12022                      tp->pdev->subsystem_vendor) &&
12023                     (subsys_id_to_phy_id[i].subsys_devid ==
12024                      tp->pdev->subsystem_device))
12025                         return &subsys_id_to_phy_id[i];
12026         }
12027         return NULL;
12028 }
12029
12030 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
12031 {
12032         u32 val;
12033         u16 pmcsr;
12034
12035         /* On some early chips the SRAM cannot be accessed in D3hot state,
12036          * so need make sure we're in D0.
12037          */
12038         pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
12039         pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
12040         pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
12041         msleep(1);
12042
12043         /* Make sure register accesses (indirect or otherwise)
12044          * will function correctly.
12045          */
12046         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12047                                tp->misc_host_ctrl);
12048
12049         /* The memory arbiter has to be enabled in order for SRAM accesses
12050          * to succeed.  Normally on powerup the tg3 chip firmware will make
12051          * sure it is enabled, but other entities such as system netboot
12052          * code might disable it.
12053          */
12054         val = tr32(MEMARB_MODE);
12055         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
12056
12057         tp->phy_id = PHY_ID_INVALID;
12058         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12059
12060         /* Assume an onboard device and WOL capable by default.  */
12061         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
12062
12063         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12064                 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
12065                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12066                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12067                 }
12068                 val = tr32(VCPU_CFGSHDW);
12069                 if (val & VCPU_CFGSHDW_ASPM_DBNC)
12070                         tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
12071                 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
12072                     (val & VCPU_CFGSHDW_WOL_MAGPKT))
12073                         tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12074                 goto done;
12075         }
12076
12077         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
12078         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
12079                 u32 nic_cfg, led_cfg;
12080                 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
12081                 int eeprom_phy_serdes = 0;
12082
12083                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
12084                 tp->nic_sram_data_cfg = nic_cfg;
12085
12086                 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
12087                 ver >>= NIC_SRAM_DATA_VER_SHIFT;
12088                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
12089                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
12090                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
12091                     (ver > 0) && (ver < 0x100))
12092                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
12093
12094                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
12095                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
12096
12097                 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
12098                     NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
12099                         eeprom_phy_serdes = 1;
12100
12101                 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
12102                 if (nic_phy_id != 0) {
12103                         u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
12104                         u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
12105
12106                         eeprom_phy_id  = (id1 >> 16) << 10;
12107                         eeprom_phy_id |= (id2 & 0xfc00) << 16;
12108                         eeprom_phy_id |= (id2 & 0x03ff) <<  0;
12109                 } else
12110                         eeprom_phy_id = 0;
12111
12112                 tp->phy_id = eeprom_phy_id;
12113                 if (eeprom_phy_serdes) {
12114                         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
12115                                 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
12116                         else
12117                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
12118                 }
12119
12120                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
12121                         led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
12122                                     SHASTA_EXT_LED_MODE_MASK);
12123                 else
12124                         led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
12125
12126                 switch (led_cfg) {
12127                 default:
12128                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
12129                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12130                         break;
12131
12132                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
12133                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12134                         break;
12135
12136                 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
12137                         tp->led_ctrl = LED_CTRL_MODE_MAC;
12138
12139                         /* Default to PHY_1_MODE if 0 (MAC_MODE) is
12140                          * read on some older 5700/5701 bootcode.
12141                          */
12142                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
12143                             ASIC_REV_5700 ||
12144                             GET_ASIC_REV(tp->pci_chip_rev_id) ==
12145                             ASIC_REV_5701)
12146                                 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12147
12148                         break;
12149
12150                 case SHASTA_EXT_LED_SHARED:
12151                         tp->led_ctrl = LED_CTRL_MODE_SHARED;
12152                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
12153                             tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
12154                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12155                                                  LED_CTRL_MODE_PHY_2);
12156                         break;
12157
12158                 case SHASTA_EXT_LED_MAC:
12159                         tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
12160                         break;
12161
12162                 case SHASTA_EXT_LED_COMBO:
12163                         tp->led_ctrl = LED_CTRL_MODE_COMBO;
12164                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
12165                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12166                                                  LED_CTRL_MODE_PHY_2);
12167                         break;
12168
12169                 }
12170
12171                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12172                      GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
12173                     tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
12174                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12175
12176                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
12177                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12178
12179                 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
12180                         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
12181                         if ((tp->pdev->subsystem_vendor ==
12182                              PCI_VENDOR_ID_ARIMA) &&
12183                             (tp->pdev->subsystem_device == 0x205a ||
12184                              tp->pdev->subsystem_device == 0x2063))
12185                                 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12186                 } else {
12187                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12188                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12189                 }
12190
12191                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
12192                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
12193                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
12194                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
12195                 }
12196
12197                 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
12198                         (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
12199                         tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
12200
12201                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
12202                     !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
12203                         tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
12204
12205                 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
12206                     (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
12207                         tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12208
12209                 if (cfg2 & (1 << 17))
12210                         tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
12211
12212                 /* serdes signal pre-emphasis in register 0x590 set by */
12213                 /* bootcode if bit 18 is set */
12214                 if (cfg2 & (1 << 18))
12215                         tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
12216
12217                 if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
12218                       GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
12219                     (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
12220                         tp->tg3_flags3 |= TG3_FLG3_PHY_ENABLE_APD;
12221
12222                 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12223                         u32 cfg3;
12224
12225                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
12226                         if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
12227                                 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
12228                 }
12229
12230                 if (cfg4 & NIC_SRAM_RGMII_STD_IBND_DISABLE)
12231                         tp->tg3_flags3 |= TG3_FLG3_RGMII_STD_IBND_DISABLE;
12232                 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
12233                         tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
12234                 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
12235                         tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
12236         }
12237 done:
12238         device_init_wakeup(&tp->pdev->dev, tp->tg3_flags & TG3_FLAG_WOL_CAP);
12239         device_set_wakeup_enable(&tp->pdev->dev,
12240                                  tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
12241 }
12242
12243 static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
12244 {
12245         int i;
12246         u32 val;
12247
12248         tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
12249         tw32(OTP_CTRL, cmd);
12250
12251         /* Wait for up to 1 ms for command to execute. */
12252         for (i = 0; i < 100; i++) {
12253                 val = tr32(OTP_STATUS);
12254                 if (val & OTP_STATUS_CMD_DONE)
12255                         break;
12256                 udelay(10);
12257         }
12258
12259         return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
12260 }
12261
12262 /* Read the gphy configuration from the OTP region of the chip.  The gphy
12263  * configuration is a 32-bit value that straddles the alignment boundary.
12264  * We do two 32-bit reads and then shift and merge the results.
12265  */
12266 static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
12267 {
12268         u32 bhalf_otp, thalf_otp;
12269
12270         tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
12271
12272         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
12273                 return 0;
12274
12275         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
12276
12277         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12278                 return 0;
12279
12280         thalf_otp = tr32(OTP_READ_DATA);
12281
12282         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
12283
12284         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12285                 return 0;
12286
12287         bhalf_otp = tr32(OTP_READ_DATA);
12288
12289         return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
12290 }
12291
12292 static int __devinit tg3_phy_probe(struct tg3 *tp)
12293 {
12294         u32 hw_phy_id_1, hw_phy_id_2;
12295         u32 hw_phy_id, hw_phy_id_masked;
12296         int err;
12297
12298         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
12299                 return tg3_phy_init(tp);
12300
12301         /* Reading the PHY ID register can conflict with ASF
12302          * firmware access to the PHY hardware.
12303          */
12304         err = 0;
12305         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12306             (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
12307                 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
12308         } else {
12309                 /* Now read the physical PHY_ID from the chip and verify
12310                  * that it is sane.  If it doesn't look good, we fall back
12311                  * to either the hard-coded table based PHY_ID and failing
12312                  * that the value found in the eeprom area.
12313                  */
12314                 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
12315                 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
12316
12317                 hw_phy_id  = (hw_phy_id_1 & 0xffff) << 10;
12318                 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
12319                 hw_phy_id |= (hw_phy_id_2 & 0x03ff) <<  0;
12320
12321                 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
12322         }
12323
12324         if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
12325                 tp->phy_id = hw_phy_id;
12326                 if (hw_phy_id_masked == PHY_ID_BCM8002)
12327                         tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
12328                 else
12329                         tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
12330         } else {
12331                 if (tp->phy_id != PHY_ID_INVALID) {
12332                         /* Do nothing, phy ID already set up in
12333                          * tg3_get_eeprom_hw_cfg().
12334                          */
12335                 } else {
12336                         struct subsys_tbl_ent *p;
12337
12338                         /* No eeprom signature?  Try the hardcoded
12339                          * subsys device table.
12340                          */
12341                         p = lookup_by_subsys(tp);
12342                         if (!p)
12343                                 return -ENODEV;
12344
12345                         tp->phy_id = p->phy_id;
12346                         if (!tp->phy_id ||
12347                             tp->phy_id == PHY_ID_BCM8002)
12348                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
12349                 }
12350         }
12351
12352         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
12353             !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
12354             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
12355                 u32 bmsr, adv_reg, tg3_ctrl, mask;
12356
12357                 tg3_readphy(tp, MII_BMSR, &bmsr);
12358                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
12359                     (bmsr & BMSR_LSTATUS))
12360                         goto skip_phy_reset;
12361
12362                 err = tg3_phy_reset(tp);
12363                 if (err)
12364                         return err;
12365
12366                 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
12367                            ADVERTISE_100HALF | ADVERTISE_100FULL |
12368                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
12369                 tg3_ctrl = 0;
12370                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
12371                         tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
12372                                     MII_TG3_CTRL_ADV_1000_FULL);
12373                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12374                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
12375                                 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
12376                                              MII_TG3_CTRL_ENABLE_AS_MASTER);
12377                 }
12378
12379                 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
12380                         ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
12381                         ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
12382                 if (!tg3_copper_is_advertising_all(tp, mask)) {
12383                         tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12384
12385                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
12386                                 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12387
12388                         tg3_writephy(tp, MII_BMCR,
12389                                      BMCR_ANENABLE | BMCR_ANRESTART);
12390                 }
12391                 tg3_phy_set_wirespeed(tp);
12392
12393                 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12394                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
12395                         tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12396         }
12397
12398 skip_phy_reset:
12399         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
12400                 err = tg3_init_5401phy_dsp(tp);
12401                 if (err)
12402                         return err;
12403         }
12404
12405         if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
12406                 err = tg3_init_5401phy_dsp(tp);
12407         }
12408
12409         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
12410                 tp->link_config.advertising =
12411                         (ADVERTISED_1000baseT_Half |
12412                          ADVERTISED_1000baseT_Full |
12413                          ADVERTISED_Autoneg |
12414                          ADVERTISED_FIBRE);
12415         if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
12416                 tp->link_config.advertising &=
12417                         ~(ADVERTISED_1000baseT_Half |
12418                           ADVERTISED_1000baseT_Full);
12419
12420         return err;
12421 }
12422
12423 static void __devinit tg3_read_partno(struct tg3 *tp)
12424 {
12425         unsigned char vpd_data[256];   /* in little-endian format */
12426         unsigned int i;
12427         u32 magic;
12428
12429         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
12430             tg3_nvram_read(tp, 0x0, &magic))
12431                 goto out_not_found;
12432
12433         if (magic == TG3_EEPROM_MAGIC) {
12434                 for (i = 0; i < 256; i += 4) {
12435                         u32 tmp;
12436
12437                         /* The data is in little-endian format in NVRAM.
12438                          * Use the big-endian read routines to preserve
12439                          * the byte order as it exists in NVRAM.
12440                          */
12441                         if (tg3_nvram_read_be32(tp, 0x100 + i, &tmp))
12442                                 goto out_not_found;
12443
12444                         memcpy(&vpd_data[i], &tmp, sizeof(tmp));
12445                 }
12446         } else {
12447                 int vpd_cap;
12448
12449                 vpd_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_VPD);
12450                 for (i = 0; i < 256; i += 4) {
12451                         u32 tmp, j = 0;
12452                         __le32 v;
12453                         u16 tmp16;
12454
12455                         pci_write_config_word(tp->pdev, vpd_cap + PCI_VPD_ADDR,
12456                                               i);
12457                         while (j++ < 100) {
12458                                 pci_read_config_word(tp->pdev, vpd_cap +
12459                                                      PCI_VPD_ADDR, &tmp16);
12460                                 if (tmp16 & 0x8000)
12461                                         break;
12462                                 msleep(1);
12463                         }
12464                         if (!(tmp16 & 0x8000))
12465                                 goto out_not_found;
12466
12467                         pci_read_config_dword(tp->pdev, vpd_cap + PCI_VPD_DATA,
12468                                               &tmp);
12469                         v = cpu_to_le32(tmp);
12470                         memcpy(&vpd_data[i], &v, sizeof(v));
12471                 }
12472         }
12473
12474         /* Now parse and find the part number. */
12475         for (i = 0; i < 254; ) {
12476                 unsigned char val = vpd_data[i];
12477                 unsigned int block_end;
12478
12479                 if (val == 0x82 || val == 0x91) {
12480                         i = (i + 3 +
12481                              (vpd_data[i + 1] +
12482                               (vpd_data[i + 2] << 8)));
12483                         continue;
12484                 }
12485
12486                 if (val != 0x90)
12487                         goto out_not_found;
12488
12489                 block_end = (i + 3 +
12490                              (vpd_data[i + 1] +
12491                               (vpd_data[i + 2] << 8)));
12492                 i += 3;
12493
12494                 if (block_end > 256)
12495                         goto out_not_found;
12496
12497                 while (i < (block_end - 2)) {
12498                         if (vpd_data[i + 0] == 'P' &&
12499                             vpd_data[i + 1] == 'N') {
12500                                 int partno_len = vpd_data[i + 2];
12501
12502                                 i += 3;
12503                                 if (partno_len > 24 || (partno_len + i) > 256)
12504                                         goto out_not_found;
12505
12506                                 memcpy(tp->board_part_number,
12507                                        &vpd_data[i], partno_len);
12508
12509                                 /* Success. */
12510                                 return;
12511                         }
12512                         i += 3 + vpd_data[i + 2];
12513                 }
12514
12515                 /* Part number not found. */
12516                 goto out_not_found;
12517         }
12518
12519 out_not_found:
12520         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12521                 strcpy(tp->board_part_number, "BCM95906");
12522         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12523                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
12524                 strcpy(tp->board_part_number, "BCM57780");
12525         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12526                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
12527                 strcpy(tp->board_part_number, "BCM57760");
12528         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12529                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
12530                 strcpy(tp->board_part_number, "BCM57790");
12531         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12532                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
12533                 strcpy(tp->board_part_number, "BCM57788");
12534         else
12535                 strcpy(tp->board_part_number, "none");
12536 }
12537
12538 static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
12539 {
12540         u32 val;
12541
12542         if (tg3_nvram_read(tp, offset, &val) ||
12543             (val & 0xfc000000) != 0x0c000000 ||
12544             tg3_nvram_read(tp, offset + 4, &val) ||
12545             val != 0)
12546                 return 0;
12547
12548         return 1;
12549 }
12550
12551 static void __devinit tg3_read_bc_ver(struct tg3 *tp)
12552 {
12553         u32 val, offset, start, ver_offset;
12554         int i;
12555         bool newver = false;
12556
12557         if (tg3_nvram_read(tp, 0xc, &offset) ||
12558             tg3_nvram_read(tp, 0x4, &start))
12559                 return;
12560
12561         offset = tg3_nvram_logical_addr(tp, offset);
12562
12563         if (tg3_nvram_read(tp, offset, &val))
12564                 return;
12565
12566         if ((val & 0xfc000000) == 0x0c000000) {
12567                 if (tg3_nvram_read(tp, offset + 4, &val))
12568                         return;
12569
12570                 if (val == 0)
12571                         newver = true;
12572         }
12573
12574         if (newver) {
12575                 if (tg3_nvram_read(tp, offset + 8, &ver_offset))
12576                         return;
12577
12578                 offset = offset + ver_offset - start;
12579                 for (i = 0; i < 16; i += 4) {
12580                         __be32 v;
12581                         if (tg3_nvram_read_be32(tp, offset + i, &v))
12582                                 return;
12583
12584                         memcpy(tp->fw_ver + i, &v, sizeof(v));
12585                 }
12586         } else {
12587                 u32 major, minor;
12588
12589                 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
12590                         return;
12591
12592                 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
12593                         TG3_NVM_BCVER_MAJSFT;
12594                 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
12595                 snprintf(&tp->fw_ver[0], 32, "v%d.%02d", major, minor);
12596         }
12597 }
12598
12599 static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
12600 {
12601         u32 val, major, minor;
12602
12603         /* Use native endian representation */
12604         if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
12605                 return;
12606
12607         major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
12608                 TG3_NVM_HWSB_CFG1_MAJSFT;
12609         minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
12610                 TG3_NVM_HWSB_CFG1_MINSFT;
12611
12612         snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
12613 }
12614
12615 static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
12616 {
12617         u32 offset, major, minor, build;
12618
12619         tp->fw_ver[0] = 's';
12620         tp->fw_ver[1] = 'b';
12621         tp->fw_ver[2] = '\0';
12622
12623         if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
12624                 return;
12625
12626         switch (val & TG3_EEPROM_SB_REVISION_MASK) {
12627         case TG3_EEPROM_SB_REVISION_0:
12628                 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
12629                 break;
12630         case TG3_EEPROM_SB_REVISION_2:
12631                 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
12632                 break;
12633         case TG3_EEPROM_SB_REVISION_3:
12634                 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
12635                 break;
12636         default:
12637                 return;
12638         }
12639
12640         if (tg3_nvram_read(tp, offset, &val))
12641                 return;
12642
12643         build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
12644                 TG3_EEPROM_SB_EDH_BLD_SHFT;
12645         major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
12646                 TG3_EEPROM_SB_EDH_MAJ_SHFT;
12647         minor =  val & TG3_EEPROM_SB_EDH_MIN_MASK;
12648
12649         if (minor > 99 || build > 26)
12650                 return;
12651
12652         snprintf(&tp->fw_ver[2], 30, " v%d.%02d", major, minor);
12653
12654         if (build > 0) {
12655                 tp->fw_ver[8] = 'a' + build - 1;
12656                 tp->fw_ver[9] = '\0';
12657         }
12658 }
12659
12660 static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
12661 {
12662         u32 val, offset, start;
12663         int i, vlen;
12664
12665         for (offset = TG3_NVM_DIR_START;
12666              offset < TG3_NVM_DIR_END;
12667              offset += TG3_NVM_DIRENT_SIZE) {
12668                 if (tg3_nvram_read(tp, offset, &val))
12669                         return;
12670
12671                 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
12672                         break;
12673         }
12674
12675         if (offset == TG3_NVM_DIR_END)
12676                 return;
12677
12678         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
12679                 start = 0x08000000;
12680         else if (tg3_nvram_read(tp, offset - 4, &start))
12681                 return;
12682
12683         if (tg3_nvram_read(tp, offset + 4, &offset) ||
12684             !tg3_fw_img_is_valid(tp, offset) ||
12685             tg3_nvram_read(tp, offset + 8, &val))
12686                 return;
12687
12688         offset += val - start;
12689
12690         vlen = strlen(tp->fw_ver);
12691
12692         tp->fw_ver[vlen++] = ',';
12693         tp->fw_ver[vlen++] = ' ';
12694
12695         for (i = 0; i < 4; i++) {
12696                 __be32 v;
12697                 if (tg3_nvram_read_be32(tp, offset, &v))
12698                         return;
12699
12700                 offset += sizeof(v);
12701
12702                 if (vlen > TG3_VER_SIZE - sizeof(v)) {
12703                         memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
12704                         break;
12705                 }
12706
12707                 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
12708                 vlen += sizeof(v);
12709         }
12710 }
12711
12712 static void __devinit tg3_read_dash_ver(struct tg3 *tp)
12713 {
12714         int vlen;
12715         u32 apedata;
12716
12717         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) ||
12718             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
12719                 return;
12720
12721         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
12722         if (apedata != APE_SEG_SIG_MAGIC)
12723                 return;
12724
12725         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
12726         if (!(apedata & APE_FW_STATUS_READY))
12727                 return;
12728
12729         apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
12730
12731         vlen = strlen(tp->fw_ver);
12732
12733         snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " DASH v%d.%d.%d.%d",
12734                  (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
12735                  (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
12736                  (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
12737                  (apedata & APE_FW_VERSION_BLDMSK));
12738 }
12739
12740 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
12741 {
12742         u32 val;
12743
12744         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) {
12745                 tp->fw_ver[0] = 's';
12746                 tp->fw_ver[1] = 'b';
12747                 tp->fw_ver[2] = '\0';
12748
12749                 return;
12750         }
12751
12752         if (tg3_nvram_read(tp, 0, &val))
12753                 return;
12754
12755         if (val == TG3_EEPROM_MAGIC)
12756                 tg3_read_bc_ver(tp);
12757         else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
12758                 tg3_read_sb_ver(tp, val);
12759         else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
12760                 tg3_read_hwsb_ver(tp);
12761         else
12762                 return;
12763
12764         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12765              (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
12766                 return;
12767
12768         tg3_read_mgmtfw_ver(tp);
12769
12770         tp->fw_ver[TG3_VER_SIZE - 1] = 0;
12771 }
12772
12773 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
12774
12775 static int __devinit tg3_get_invariants(struct tg3 *tp)
12776 {
12777         static struct pci_device_id write_reorder_chipsets[] = {
12778                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12779                              PCI_DEVICE_ID_AMD_FE_GATE_700C) },
12780                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12781                              PCI_DEVICE_ID_AMD_8131_BRIDGE) },
12782                 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
12783                              PCI_DEVICE_ID_VIA_8385_0) },
12784                 { },
12785         };
12786         u32 misc_ctrl_reg;
12787         u32 pci_state_reg, grc_misc_cfg;
12788         u32 val;
12789         u16 pci_cmd;
12790         int err;
12791
12792         /* Force memory write invalidate off.  If we leave it on,
12793          * then on 5700_BX chips we have to enable a workaround.
12794          * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
12795          * to match the cacheline size.  The Broadcom driver have this
12796          * workaround but turns MWI off all the times so never uses
12797          * it.  This seems to suggest that the workaround is insufficient.
12798          */
12799         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12800         pci_cmd &= ~PCI_COMMAND_INVALIDATE;
12801         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12802
12803         /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
12804          * has the register indirect write enable bit set before
12805          * we try to access any of the MMIO registers.  It is also
12806          * critical that the PCI-X hw workaround situation is decided
12807          * before that as well.
12808          */
12809         pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12810                               &misc_ctrl_reg);
12811
12812         tp->pci_chip_rev_id = (misc_ctrl_reg >>
12813                                MISC_HOST_CTRL_CHIPREV_SHIFT);
12814         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
12815                 u32 prod_id_asic_rev;
12816
12817                 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
12818                     tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
12819                     tp->pdev->device == TG3PCI_DEVICE_TIGON3_5724)
12820                         pci_read_config_dword(tp->pdev,
12821                                               TG3PCI_GEN2_PRODID_ASICREV,
12822                                               &prod_id_asic_rev);
12823                 else
12824                         pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
12825                                               &prod_id_asic_rev);
12826
12827                 tp->pci_chip_rev_id = prod_id_asic_rev;
12828         }
12829
12830         /* Wrong chip ID in 5752 A0. This code can be removed later
12831          * as A0 is not in production.
12832          */
12833         if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
12834                 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
12835
12836         /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
12837          * we need to disable memory and use config. cycles
12838          * only to access all registers. The 5702/03 chips
12839          * can mistakenly decode the special cycles from the
12840          * ICH chipsets as memory write cycles, causing corruption
12841          * of register and memory space. Only certain ICH bridges
12842          * will drive special cycles with non-zero data during the
12843          * address phase which can fall within the 5703's address
12844          * range. This is not an ICH bug as the PCI spec allows
12845          * non-zero address during special cycles. However, only
12846          * these ICH bridges are known to drive non-zero addresses
12847          * during special cycles.
12848          *
12849          * Since special cycles do not cross PCI bridges, we only
12850          * enable this workaround if the 5703 is on the secondary
12851          * bus of these ICH bridges.
12852          */
12853         if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
12854             (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
12855                 static struct tg3_dev_id {
12856                         u32     vendor;
12857                         u32     device;
12858                         u32     rev;
12859                 } ich_chipsets[] = {
12860                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
12861                           PCI_ANY_ID },
12862                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
12863                           PCI_ANY_ID },
12864                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
12865                           0xa },
12866                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
12867                           PCI_ANY_ID },
12868                         { },
12869                 };
12870                 struct tg3_dev_id *pci_id = &ich_chipsets[0];
12871                 struct pci_dev *bridge = NULL;
12872
12873                 while (pci_id->vendor != 0) {
12874                         bridge = pci_get_device(pci_id->vendor, pci_id->device,
12875                                                 bridge);
12876                         if (!bridge) {
12877                                 pci_id++;
12878                                 continue;
12879                         }
12880                         if (pci_id->rev != PCI_ANY_ID) {
12881                                 if (bridge->revision > pci_id->rev)
12882                                         continue;
12883                         }
12884                         if (bridge->subordinate &&
12885                             (bridge->subordinate->number ==
12886                              tp->pdev->bus->number)) {
12887
12888                                 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
12889                                 pci_dev_put(bridge);
12890                                 break;
12891                         }
12892                 }
12893         }
12894
12895         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
12896                 static struct tg3_dev_id {
12897                         u32     vendor;
12898                         u32     device;
12899                 } bridge_chipsets[] = {
12900                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
12901                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
12902                         { },
12903                 };
12904                 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
12905                 struct pci_dev *bridge = NULL;
12906
12907                 while (pci_id->vendor != 0) {
12908                         bridge = pci_get_device(pci_id->vendor,
12909                                                 pci_id->device,
12910                                                 bridge);
12911                         if (!bridge) {
12912                                 pci_id++;
12913                                 continue;
12914                         }
12915                         if (bridge->subordinate &&
12916                             (bridge->subordinate->number <=
12917                              tp->pdev->bus->number) &&
12918                             (bridge->subordinate->subordinate >=
12919                              tp->pdev->bus->number)) {
12920                                 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
12921                                 pci_dev_put(bridge);
12922                                 break;
12923                         }
12924                 }
12925         }
12926
12927         /* The EPB bridge inside 5714, 5715, and 5780 cannot support
12928          * DMA addresses > 40-bit. This bridge may have other additional
12929          * 57xx devices behind it in some 4-port NIC designs for example.
12930          * Any tg3 device found behind the bridge will also need the 40-bit
12931          * DMA workaround.
12932          */
12933         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
12934             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
12935                 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
12936                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
12937                 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
12938         }
12939         else {
12940                 struct pci_dev *bridge = NULL;
12941
12942                 do {
12943                         bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
12944                                                 PCI_DEVICE_ID_SERVERWORKS_EPB,
12945                                                 bridge);
12946                         if (bridge && bridge->subordinate &&
12947                             (bridge->subordinate->number <=
12948                              tp->pdev->bus->number) &&
12949                             (bridge->subordinate->subordinate >=
12950                              tp->pdev->bus->number)) {
12951                                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
12952                                 pci_dev_put(bridge);
12953                                 break;
12954                         }
12955                 } while (bridge);
12956         }
12957
12958         /* Initialize misc host control in PCI block. */
12959         tp->misc_host_ctrl |= (misc_ctrl_reg &
12960                                MISC_HOST_CTRL_CHIPREV);
12961         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12962                                tp->misc_host_ctrl);
12963
12964         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
12965             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
12966             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
12967                 tp->pdev_peer = tg3_find_peer(tp);
12968
12969         /* Intentionally exclude ASIC_REV_5906 */
12970         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12971             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
12972             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12973             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
12974             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12975             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
12976             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
12977                 tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
12978
12979         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
12980             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
12981             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
12982             (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
12983             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
12984                 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
12985
12986         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
12987             (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
12988                 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
12989
12990         /* 5700 B0 chips do not support checksumming correctly due
12991          * to hardware bugs.
12992          */
12993         if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
12994                 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
12995         else {
12996                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
12997                 tp->dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
12998                 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
12999                         tp->dev->features |= NETIF_F_IPV6_CSUM;
13000         }
13001
13002         /* Determine TSO capabilities */
13003         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
13004                 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_3;
13005         else if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13006                  GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13007                 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
13008         else if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
13009                 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
13010                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 &&
13011                     tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
13012                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
13013         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13014                    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13015                    tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
13016                 tp->tg3_flags2 |= TG3_FLG2_TSO_BUG;
13017                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
13018                         tp->fw_needed = FIRMWARE_TG3TSO5;
13019                 else
13020                         tp->fw_needed = FIRMWARE_TG3TSO;
13021         }
13022
13023         tp->irq_max = 1;
13024
13025         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
13026                 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
13027                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
13028                     GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
13029                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
13030                      tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
13031                      tp->pdev_peer == tp->pdev))
13032                         tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
13033
13034                 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13035                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13036                         tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
13037                 }
13038
13039                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
13040                         tp->tg3_flags |= TG3_FLAG_SUPPORT_MSIX;
13041                         tp->irq_max = TG3_IRQ_MAX_VECS;
13042                 }
13043         }
13044
13045         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13046             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13047                 tp->tg3_flags3 |= TG3_FLG3_SHORT_DMA_BUG;
13048         else if (!(tp->tg3_flags3 & TG3_FLG3_5755_PLUS)) {
13049                 tp->tg3_flags3 |= TG3_FLG3_4G_DMA_BNDRY_BUG;
13050                 tp->tg3_flags3 |= TG3_FLG3_40BIT_DMA_LIMIT_BUG;
13051         }
13052
13053         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
13054              (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
13055             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
13056                 tp->tg3_flags |= TG3_FLAG_JUMBO_CAPABLE;
13057
13058         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13059                               &pci_state_reg);
13060
13061         tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
13062         if (tp->pcie_cap != 0) {
13063                 u16 lnkctl;
13064
13065                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
13066
13067                 pcie_set_readrq(tp->pdev, 4096);
13068
13069                 pci_read_config_word(tp->pdev,
13070                                      tp->pcie_cap + PCI_EXP_LNKCTL,
13071                                      &lnkctl);
13072                 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
13073                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13074                                 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
13075                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13076                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13077                             tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
13078                             tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
13079                                 tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
13080                 }
13081         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
13082                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
13083         } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
13084                    (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13085                 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
13086                 if (!tp->pcix_cap) {
13087                         printk(KERN_ERR PFX "Cannot find PCI-X "
13088                                             "capability, aborting.\n");
13089                         return -EIO;
13090                 }
13091
13092                 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
13093                         tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
13094         }
13095
13096         /* If we have an AMD 762 or VIA K8T800 chipset, write
13097          * reordering to the mailbox registers done by the host
13098          * controller can cause major troubles.  We read back from
13099          * every mailbox register write to force the writes to be
13100          * posted to the chip in order.
13101          */
13102         if (pci_dev_present(write_reorder_chipsets) &&
13103             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13104                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
13105
13106         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
13107                              &tp->pci_cacheline_sz);
13108         pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13109                              &tp->pci_lat_timer);
13110         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13111             tp->pci_lat_timer < 64) {
13112                 tp->pci_lat_timer = 64;
13113                 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13114                                       tp->pci_lat_timer);
13115         }
13116
13117         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
13118                 /* 5700 BX chips need to have their TX producer index
13119                  * mailboxes written twice to workaround a bug.
13120                  */
13121                 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
13122
13123                 /* If we are in PCI-X mode, enable register write workaround.
13124                  *
13125                  * The workaround is to use indirect register accesses
13126                  * for all chip writes not to mailbox registers.
13127                  */
13128                 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
13129                         u32 pm_reg;
13130
13131                         tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13132
13133                         /* The chip can have it's power management PCI config
13134                          * space registers clobbered due to this bug.
13135                          * So explicitly force the chip into D0 here.
13136                          */
13137                         pci_read_config_dword(tp->pdev,
13138                                               tp->pm_cap + PCI_PM_CTRL,
13139                                               &pm_reg);
13140                         pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
13141                         pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
13142                         pci_write_config_dword(tp->pdev,
13143                                                tp->pm_cap + PCI_PM_CTRL,
13144                                                pm_reg);
13145
13146                         /* Also, force SERR#/PERR# in PCI command. */
13147                         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13148                         pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
13149                         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13150                 }
13151         }
13152
13153         if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
13154                 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
13155         if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
13156                 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
13157
13158         /* Chip-specific fixup from Broadcom driver */
13159         if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
13160             (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
13161                 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
13162                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
13163         }
13164
13165         /* Default fast path register access methods */
13166         tp->read32 = tg3_read32;
13167         tp->write32 = tg3_write32;
13168         tp->read32_mbox = tg3_read32;
13169         tp->write32_mbox = tg3_write32;
13170         tp->write32_tx_mbox = tg3_write32;
13171         tp->write32_rx_mbox = tg3_write32;
13172
13173         /* Various workaround register access methods */
13174         if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
13175                 tp->write32 = tg3_write_indirect_reg32;
13176         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
13177                  ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
13178                   tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
13179                 /*
13180                  * Back to back register writes can cause problems on these
13181                  * chips, the workaround is to read back all reg writes
13182                  * except those to mailbox regs.
13183                  *
13184                  * See tg3_write_indirect_reg32().
13185                  */
13186                 tp->write32 = tg3_write_flush_reg32;
13187         }
13188
13189         if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
13190             (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
13191                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
13192                 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
13193                         tp->write32_rx_mbox = tg3_write_flush_reg32;
13194         }
13195
13196         if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
13197                 tp->read32 = tg3_read_indirect_reg32;
13198                 tp->write32 = tg3_write_indirect_reg32;
13199                 tp->read32_mbox = tg3_read_indirect_mbox;
13200                 tp->write32_mbox = tg3_write_indirect_mbox;
13201                 tp->write32_tx_mbox = tg3_write_indirect_mbox;
13202                 tp->write32_rx_mbox = tg3_write_indirect_mbox;
13203
13204                 iounmap(tp->regs);
13205                 tp->regs = NULL;
13206
13207                 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13208                 pci_cmd &= ~PCI_COMMAND_MEMORY;
13209                 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13210         }
13211         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13212                 tp->read32_mbox = tg3_read32_mbox_5906;
13213                 tp->write32_mbox = tg3_write32_mbox_5906;
13214                 tp->write32_tx_mbox = tg3_write32_mbox_5906;
13215                 tp->write32_rx_mbox = tg3_write32_mbox_5906;
13216         }
13217
13218         if (tp->write32 == tg3_write_indirect_reg32 ||
13219             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13220              (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13221               GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
13222                 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
13223
13224         /* Get eeprom hw config before calling tg3_set_power_state().
13225          * In particular, the TG3_FLG2_IS_NIC flag must be
13226          * determined before calling tg3_set_power_state() so that
13227          * we know whether or not to switch out of Vaux power.
13228          * When the flag is set, it means that GPIO1 is used for eeprom
13229          * write protect and also implies that it is a LOM where GPIOs
13230          * are not used to switch power.
13231          */
13232         tg3_get_eeprom_hw_cfg(tp);
13233
13234         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
13235                 /* Allow reads and writes to the
13236                  * APE register and memory space.
13237                  */
13238                 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
13239                                  PCISTATE_ALLOW_APE_SHMEM_WR;
13240                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
13241                                        pci_state_reg);
13242         }
13243
13244         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13245             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13246             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13247             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13248             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
13249                 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
13250
13251         /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
13252          * GPIO1 driven high will bring 5700's external PHY out of reset.
13253          * It is also used as eeprom write protect on LOMs.
13254          */
13255         tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
13256         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13257             (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
13258                 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
13259                                        GRC_LCLCTRL_GPIO_OUTPUT1);
13260         /* Unused GPIO3 must be driven as output on 5752 because there
13261          * are no pull-up resistors on unused GPIO pins.
13262          */
13263         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
13264                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
13265
13266         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13267             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
13268                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13269
13270         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
13271             tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
13272                 /* Turn off the debug UART. */
13273                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13274                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
13275                         /* Keep VMain power. */
13276                         tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
13277                                               GRC_LCLCTRL_GPIO_OUTPUT0;
13278         }
13279
13280         /* Force the chip into D0. */
13281         err = tg3_set_power_state(tp, PCI_D0);
13282         if (err) {
13283                 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
13284                        pci_name(tp->pdev));
13285                 return err;
13286         }
13287
13288         /* Derive initial jumbo mode from MTU assigned in
13289          * ether_setup() via the alloc_etherdev() call
13290          */
13291         if (tp->dev->mtu > ETH_DATA_LEN &&
13292             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
13293                 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
13294
13295         /* Determine WakeOnLan speed to use. */
13296         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13297             tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
13298             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
13299             tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
13300                 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
13301         } else {
13302                 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
13303         }
13304
13305         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13306                 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
13307
13308         /* A few boards don't want Ethernet@WireSpeed phy feature */
13309         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13310             ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
13311              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
13312              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
13313             (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) ||
13314             (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
13315                 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
13316
13317         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
13318             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
13319                 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
13320         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
13321                 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
13322
13323         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
13324             !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
13325             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
13326             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 &&
13327             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) {
13328                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13329                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
13330                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13331                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
13332                         if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
13333                             tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
13334                                 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
13335                         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
13336                                 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
13337                 } else
13338                         tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
13339         }
13340
13341         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13342             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
13343                 tp->phy_otp = tg3_read_otp_phycfg(tp);
13344                 if (tp->phy_otp == 0)
13345                         tp->phy_otp = TG3_OTP_DEFAULT;
13346         }
13347
13348         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
13349                 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
13350         else
13351                 tp->mi_mode = MAC_MI_MODE_BASE;
13352
13353         tp->coalesce_mode = 0;
13354         if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
13355             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
13356                 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
13357
13358         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13359             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
13360                 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
13361
13362         err = tg3_mdio_init(tp);
13363         if (err)
13364                 return err;
13365
13366         /* Initialize data/descriptor byte/word swapping. */
13367         val = tr32(GRC_MODE);
13368         val &= GRC_MODE_HOST_STACKUP;
13369         tw32(GRC_MODE, val | tp->grc_mode);
13370
13371         tg3_switch_clocks(tp);
13372
13373         /* Clear this out for sanity. */
13374         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
13375
13376         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13377                               &pci_state_reg);
13378         if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
13379             (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
13380                 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
13381
13382                 if (chiprevid == CHIPREV_ID_5701_A0 ||
13383                     chiprevid == CHIPREV_ID_5701_B0 ||
13384                     chiprevid == CHIPREV_ID_5701_B2 ||
13385                     chiprevid == CHIPREV_ID_5701_B5) {
13386                         void __iomem *sram_base;
13387
13388                         /* Write some dummy words into the SRAM status block
13389                          * area, see if it reads back correctly.  If the return
13390                          * value is bad, force enable the PCIX workaround.
13391                          */
13392                         sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
13393
13394                         writel(0x00000000, sram_base);
13395                         writel(0x00000000, sram_base + 4);
13396                         writel(0xffffffff, sram_base + 4);
13397                         if (readl(sram_base) != 0x00000000)
13398                                 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13399                 }
13400         }
13401
13402         udelay(50);
13403         tg3_nvram_init(tp);
13404
13405         grc_misc_cfg = tr32(GRC_MISC_CFG);
13406         grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
13407
13408         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13409             (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
13410              grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
13411                 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
13412
13413         if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
13414             (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
13415                 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
13416         if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
13417                 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
13418                                       HOSTCC_MODE_CLRTICK_TXBD);
13419
13420                 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
13421                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13422                                        tp->misc_host_ctrl);
13423         }
13424
13425         /* Preserve the APE MAC_MODE bits */
13426         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
13427                 tp->mac_mode = tr32(MAC_MODE) |
13428                                MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
13429         else
13430                 tp->mac_mode = TG3_DEF_MAC_MODE;
13431
13432         /* these are limited to 10/100 only */
13433         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13434              (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
13435             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13436              tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13437              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
13438               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
13439               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
13440             (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13441              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
13442               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
13443               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
13444             tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
13445             (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
13446                 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
13447
13448         err = tg3_phy_probe(tp);
13449         if (err) {
13450                 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
13451                        pci_name(tp->pdev), err);
13452                 /* ... but do not return immediately ... */
13453                 tg3_mdio_fini(tp);
13454         }
13455
13456         tg3_read_partno(tp);
13457         tg3_read_fw_ver(tp);
13458
13459         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
13460                 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
13461         } else {
13462                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13463                         tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
13464                 else
13465                         tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
13466         }
13467
13468         /* 5700 {AX,BX} chips have a broken status block link
13469          * change bit implementation, so we must use the
13470          * status register in those cases.
13471          */
13472         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13473                 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
13474         else
13475                 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
13476
13477         /* The led_ctrl is set during tg3_phy_probe, here we might
13478          * have to force the link status polling mechanism based
13479          * upon subsystem IDs.
13480          */
13481         if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
13482             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13483             !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
13484                 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
13485                                   TG3_FLAG_USE_LINKCHG_REG);
13486         }
13487
13488         /* For all SERDES we poll the MAC status register. */
13489         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
13490                 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
13491         else
13492                 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
13493
13494         tp->rx_offset = NET_IP_ALIGN;
13495         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13496             (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
13497                 tp->rx_offset = 0;
13498
13499         tp->rx_std_max_post = TG3_RX_RING_SIZE;
13500
13501         /* Increment the rx prod index on the rx std ring by at most
13502          * 8 for these chips to workaround hw errata.
13503          */
13504         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13505             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13506             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
13507                 tp->rx_std_max_post = 8;
13508
13509         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
13510                 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
13511                                      PCIE_PWR_MGMT_L1_THRESH_MSK;
13512
13513         return err;
13514 }
13515
13516 #ifdef CONFIG_SPARC
13517 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
13518 {
13519         struct net_device *dev = tp->dev;
13520         struct pci_dev *pdev = tp->pdev;
13521         struct device_node *dp = pci_device_to_OF_node(pdev);
13522         const unsigned char *addr;
13523         int len;
13524
13525         addr = of_get_property(dp, "local-mac-address", &len);
13526         if (addr && len == 6) {
13527                 memcpy(dev->dev_addr, addr, 6);
13528                 memcpy(dev->perm_addr, dev->dev_addr, 6);
13529                 return 0;
13530         }
13531         return -ENODEV;
13532 }
13533
13534 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
13535 {
13536         struct net_device *dev = tp->dev;
13537
13538         memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
13539         memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
13540         return 0;
13541 }
13542 #endif
13543
13544 static int __devinit tg3_get_device_address(struct tg3 *tp)
13545 {
13546         struct net_device *dev = tp->dev;
13547         u32 hi, lo, mac_offset;
13548         int addr_ok = 0;
13549
13550 #ifdef CONFIG_SPARC
13551         if (!tg3_get_macaddr_sparc(tp))
13552                 return 0;
13553 #endif
13554
13555         mac_offset = 0x7c;
13556         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
13557             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13558                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
13559                         mac_offset = 0xcc;
13560                 if (tg3_nvram_lock(tp))
13561                         tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
13562                 else
13563                         tg3_nvram_unlock(tp);
13564         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
13565                 if (tr32(TG3_CPMU_STATUS) & TG3_CPMU_STATUS_PCIE_FUNC)
13566                         mac_offset = 0xcc;
13567         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13568                 mac_offset = 0x10;
13569
13570         /* First try to get it from MAC address mailbox. */
13571         tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
13572         if ((hi >> 16) == 0x484b) {
13573                 dev->dev_addr[0] = (hi >>  8) & 0xff;
13574                 dev->dev_addr[1] = (hi >>  0) & 0xff;
13575
13576                 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
13577                 dev->dev_addr[2] = (lo >> 24) & 0xff;
13578                 dev->dev_addr[3] = (lo >> 16) & 0xff;
13579                 dev->dev_addr[4] = (lo >>  8) & 0xff;
13580                 dev->dev_addr[5] = (lo >>  0) & 0xff;
13581
13582                 /* Some old bootcode may report a 0 MAC address in SRAM */
13583                 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
13584         }
13585         if (!addr_ok) {
13586                 /* Next, try NVRAM. */
13587                 if (!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) &&
13588                     !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
13589                     !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
13590                         memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
13591                         memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
13592                 }
13593                 /* Finally just fetch it out of the MAC control regs. */
13594                 else {
13595                         hi = tr32(MAC_ADDR_0_HIGH);
13596                         lo = tr32(MAC_ADDR_0_LOW);
13597
13598                         dev->dev_addr[5] = lo & 0xff;
13599                         dev->dev_addr[4] = (lo >> 8) & 0xff;
13600                         dev->dev_addr[3] = (lo >> 16) & 0xff;
13601                         dev->dev_addr[2] = (lo >> 24) & 0xff;
13602                         dev->dev_addr[1] = hi & 0xff;
13603                         dev->dev_addr[0] = (hi >> 8) & 0xff;
13604                 }
13605         }
13606
13607         if (!is_valid_ether_addr(&dev->dev_addr[0])) {
13608 #ifdef CONFIG_SPARC
13609                 if (!tg3_get_default_macaddr_sparc(tp))
13610                         return 0;
13611 #endif
13612                 return -EINVAL;
13613         }
13614         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
13615         return 0;
13616 }
13617
13618 #define BOUNDARY_SINGLE_CACHELINE       1
13619 #define BOUNDARY_MULTI_CACHELINE        2
13620
13621 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
13622 {
13623         int cacheline_size;
13624         u8 byte;
13625         int goal;
13626
13627         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
13628         if (byte == 0)
13629                 cacheline_size = 1024;
13630         else
13631                 cacheline_size = (int) byte * 4;
13632
13633         /* On 5703 and later chips, the boundary bits have no
13634          * effect.
13635          */
13636         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13637             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13638             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13639                 goto out;
13640
13641 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
13642         goal = BOUNDARY_MULTI_CACHELINE;
13643 #else
13644 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
13645         goal = BOUNDARY_SINGLE_CACHELINE;
13646 #else
13647         goal = 0;
13648 #endif
13649 #endif
13650
13651         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
13652                 val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
13653                 goto out;
13654         }
13655
13656         if (!goal)
13657                 goto out;
13658
13659         /* PCI controllers on most RISC systems tend to disconnect
13660          * when a device tries to burst across a cache-line boundary.
13661          * Therefore, letting tg3 do so just wastes PCI bandwidth.
13662          *
13663          * Unfortunately, for PCI-E there are only limited
13664          * write-side controls for this, and thus for reads
13665          * we will still get the disconnects.  We'll also waste
13666          * these PCI cycles for both read and write for chips
13667          * other than 5700 and 5701 which do not implement the
13668          * boundary bits.
13669          */
13670         if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13671             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
13672                 switch (cacheline_size) {
13673                 case 16:
13674                 case 32:
13675                 case 64:
13676                 case 128:
13677                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13678                                 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
13679                                         DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
13680                         } else {
13681                                 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13682                                         DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13683                         }
13684                         break;
13685
13686                 case 256:
13687                         val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
13688                                 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
13689                         break;
13690
13691                 default:
13692                         val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13693                                 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13694                         break;
13695                 }
13696         } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13697                 switch (cacheline_size) {
13698                 case 16:
13699                 case 32:
13700                 case 64:
13701                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13702                                 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13703                                 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
13704                                 break;
13705                         }
13706                         /* fallthrough */
13707                 case 128:
13708                 default:
13709                         val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13710                         val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
13711                         break;
13712                 }
13713         } else {
13714                 switch (cacheline_size) {
13715                 case 16:
13716                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13717                                 val |= (DMA_RWCTRL_READ_BNDRY_16 |
13718                                         DMA_RWCTRL_WRITE_BNDRY_16);
13719                                 break;
13720                         }
13721                         /* fallthrough */
13722                 case 32:
13723                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13724                                 val |= (DMA_RWCTRL_READ_BNDRY_32 |
13725                                         DMA_RWCTRL_WRITE_BNDRY_32);
13726                                 break;
13727                         }
13728                         /* fallthrough */
13729                 case 64:
13730                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13731                                 val |= (DMA_RWCTRL_READ_BNDRY_64 |
13732                                         DMA_RWCTRL_WRITE_BNDRY_64);
13733                                 break;
13734                         }
13735                         /* fallthrough */
13736                 case 128:
13737                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13738                                 val |= (DMA_RWCTRL_READ_BNDRY_128 |
13739                                         DMA_RWCTRL_WRITE_BNDRY_128);
13740                                 break;
13741                         }
13742                         /* fallthrough */
13743                 case 256:
13744                         val |= (DMA_RWCTRL_READ_BNDRY_256 |
13745                                 DMA_RWCTRL_WRITE_BNDRY_256);
13746                         break;
13747                 case 512:
13748                         val |= (DMA_RWCTRL_READ_BNDRY_512 |
13749                                 DMA_RWCTRL_WRITE_BNDRY_512);
13750                         break;
13751                 case 1024:
13752                 default:
13753                         val |= (DMA_RWCTRL_READ_BNDRY_1024 |
13754                                 DMA_RWCTRL_WRITE_BNDRY_1024);
13755                         break;
13756                 }
13757         }
13758
13759 out:
13760         return val;
13761 }
13762
13763 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
13764 {
13765         struct tg3_internal_buffer_desc test_desc;
13766         u32 sram_dma_descs;
13767         int i, ret;
13768
13769         sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
13770
13771         tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
13772         tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
13773         tw32(RDMAC_STATUS, 0);
13774         tw32(WDMAC_STATUS, 0);
13775
13776         tw32(BUFMGR_MODE, 0);
13777         tw32(FTQ_RESET, 0);
13778
13779         test_desc.addr_hi = ((u64) buf_dma) >> 32;
13780         test_desc.addr_lo = buf_dma & 0xffffffff;
13781         test_desc.nic_mbuf = 0x00002100;
13782         test_desc.len = size;
13783
13784         /*
13785          * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
13786          * the *second* time the tg3 driver was getting loaded after an
13787          * initial scan.
13788          *
13789          * Broadcom tells me:
13790          *   ...the DMA engine is connected to the GRC block and a DMA
13791          *   reset may affect the GRC block in some unpredictable way...
13792          *   The behavior of resets to individual blocks has not been tested.
13793          *
13794          * Broadcom noted the GRC reset will also reset all sub-components.
13795          */
13796         if (to_device) {
13797                 test_desc.cqid_sqid = (13 << 8) | 2;
13798
13799                 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
13800                 udelay(40);
13801         } else {
13802                 test_desc.cqid_sqid = (16 << 8) | 7;
13803
13804                 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
13805                 udelay(40);
13806         }
13807         test_desc.flags = 0x00000005;
13808
13809         for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
13810                 u32 val;
13811
13812                 val = *(((u32 *)&test_desc) + i);
13813                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
13814                                        sram_dma_descs + (i * sizeof(u32)));
13815                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
13816         }
13817         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
13818
13819         if (to_device) {
13820                 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
13821         } else {
13822                 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
13823         }
13824
13825         ret = -ENODEV;
13826         for (i = 0; i < 40; i++) {
13827                 u32 val;
13828
13829                 if (to_device)
13830                         val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
13831                 else
13832                         val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
13833                 if ((val & 0xffff) == sram_dma_descs) {
13834                         ret = 0;
13835                         break;
13836                 }
13837
13838                 udelay(100);
13839         }
13840
13841         return ret;
13842 }
13843
13844 #define TEST_BUFFER_SIZE        0x2000
13845
13846 static int __devinit tg3_test_dma(struct tg3 *tp)
13847 {
13848         dma_addr_t buf_dma;
13849         u32 *buf, saved_dma_rwctrl;
13850         int ret = 0;
13851
13852         buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
13853         if (!buf) {
13854                 ret = -ENOMEM;
13855                 goto out_nofree;
13856         }
13857
13858         tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
13859                           (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
13860
13861         tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
13862
13863         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
13864                 goto out;
13865
13866         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13867                 /* DMA read watermark not used on PCIE */
13868                 tp->dma_rwctrl |= 0x00180000;
13869         } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
13870                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
13871                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
13872                         tp->dma_rwctrl |= 0x003f0000;
13873                 else
13874                         tp->dma_rwctrl |= 0x003f000f;
13875         } else {
13876                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13877                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
13878                         u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
13879                         u32 read_water = 0x7;
13880
13881                         /* If the 5704 is behind the EPB bridge, we can
13882                          * do the less restrictive ONE_DMA workaround for
13883                          * better performance.
13884                          */
13885                         if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
13886                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13887                                 tp->dma_rwctrl |= 0x8000;
13888                         else if (ccval == 0x6 || ccval == 0x7)
13889                                 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
13890
13891                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
13892                                 read_water = 4;
13893                         /* Set bit 23 to enable PCIX hw bug fix */
13894                         tp->dma_rwctrl |=
13895                                 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
13896                                 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
13897                                 (1 << 23);
13898                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
13899                         /* 5780 always in PCIX mode */
13900                         tp->dma_rwctrl |= 0x00144000;
13901                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
13902                         /* 5714 always in PCIX mode */
13903                         tp->dma_rwctrl |= 0x00148000;
13904                 } else {
13905                         tp->dma_rwctrl |= 0x001b000f;
13906                 }
13907         }
13908
13909         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13910             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13911                 tp->dma_rwctrl &= 0xfffffff0;
13912
13913         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13914             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
13915                 /* Remove this if it causes problems for some boards. */
13916                 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
13917
13918                 /* On 5700/5701 chips, we need to set this bit.
13919                  * Otherwise the chip will issue cacheline transactions
13920                  * to streamable DMA memory with not all the byte
13921                  * enables turned on.  This is an error on several
13922                  * RISC PCI controllers, in particular sparc64.
13923                  *
13924                  * On 5703/5704 chips, this bit has been reassigned
13925                  * a different meaning.  In particular, it is used
13926                  * on those chips to enable a PCI-X workaround.
13927                  */
13928                 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
13929         }
13930
13931         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13932
13933 #if 0
13934         /* Unneeded, already done by tg3_get_invariants.  */
13935         tg3_switch_clocks(tp);
13936 #endif
13937
13938         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13939             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
13940                 goto out;
13941
13942         /* It is best to perform DMA test with maximum write burst size
13943          * to expose the 5700/5701 write DMA bug.
13944          */
13945         saved_dma_rwctrl = tp->dma_rwctrl;
13946         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
13947         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13948
13949         while (1) {
13950                 u32 *p = buf, i;
13951
13952                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
13953                         p[i] = i;
13954
13955                 /* Send the buffer to the chip. */
13956                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
13957                 if (ret) {
13958                         printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
13959                         break;
13960                 }
13961
13962 #if 0
13963                 /* validate data reached card RAM correctly. */
13964                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
13965                         u32 val;
13966                         tg3_read_mem(tp, 0x2100 + (i*4), &val);
13967                         if (le32_to_cpu(val) != p[i]) {
13968                                 printk(KERN_ERR "  tg3_test_dma()  Card buffer corrupted on write! (%d != %d)\n", val, i);
13969                                 /* ret = -ENODEV here? */
13970                         }
13971                         p[i] = 0;
13972                 }
13973 #endif
13974                 /* Now read it back. */
13975                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
13976                 if (ret) {
13977                         printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
13978
13979                         break;
13980                 }
13981
13982                 /* Verify it. */
13983                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
13984                         if (p[i] == i)
13985                                 continue;
13986
13987                         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
13988                             DMA_RWCTRL_WRITE_BNDRY_16) {
13989                                 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
13990                                 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
13991                                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13992                                 break;
13993                         } else {
13994                                 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
13995                                 ret = -ENODEV;
13996                                 goto out;
13997                         }
13998                 }
13999
14000                 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
14001                         /* Success. */
14002                         ret = 0;
14003                         break;
14004                 }
14005         }
14006         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
14007             DMA_RWCTRL_WRITE_BNDRY_16) {
14008                 static struct pci_device_id dma_wait_state_chipsets[] = {
14009                         { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
14010                                      PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
14011                         { },
14012                 };
14013
14014                 /* DMA test passed without adjusting DMA boundary,
14015                  * now look for chipsets that are known to expose the
14016                  * DMA bug without failing the test.
14017                  */
14018                 if (pci_dev_present(dma_wait_state_chipsets)) {
14019                         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14020                         tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14021                 }
14022                 else
14023                         /* Safe to use the calculated DMA boundary. */
14024                         tp->dma_rwctrl = saved_dma_rwctrl;
14025
14026                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14027         }
14028
14029 out:
14030         pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
14031 out_nofree:
14032         return ret;
14033 }
14034
14035 static void __devinit tg3_init_link_config(struct tg3 *tp)
14036 {
14037         tp->link_config.advertising =
14038                 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
14039                  ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
14040                  ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
14041                  ADVERTISED_Autoneg | ADVERTISED_MII);
14042         tp->link_config.speed = SPEED_INVALID;
14043         tp->link_config.duplex = DUPLEX_INVALID;
14044         tp->link_config.autoneg = AUTONEG_ENABLE;
14045         tp->link_config.active_speed = SPEED_INVALID;
14046         tp->link_config.active_duplex = DUPLEX_INVALID;
14047         tp->link_config.phy_is_low_power = 0;
14048         tp->link_config.orig_speed = SPEED_INVALID;
14049         tp->link_config.orig_duplex = DUPLEX_INVALID;
14050         tp->link_config.orig_autoneg = AUTONEG_INVALID;
14051 }
14052
14053 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
14054 {
14055         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS &&
14056             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) {
14057                 tp->bufmgr_config.mbuf_read_dma_low_water =
14058                         DEFAULT_MB_RDMA_LOW_WATER_5705;
14059                 tp->bufmgr_config.mbuf_mac_rx_low_water =
14060                         DEFAULT_MB_MACRX_LOW_WATER_5705;
14061                 tp->bufmgr_config.mbuf_high_water =
14062                         DEFAULT_MB_HIGH_WATER_5705;
14063                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
14064                         tp->bufmgr_config.mbuf_mac_rx_low_water =
14065                                 DEFAULT_MB_MACRX_LOW_WATER_5906;
14066                         tp->bufmgr_config.mbuf_high_water =
14067                                 DEFAULT_MB_HIGH_WATER_5906;
14068                 }
14069
14070                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14071                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
14072                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14073                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
14074                 tp->bufmgr_config.mbuf_high_water_jumbo =
14075                         DEFAULT_MB_HIGH_WATER_JUMBO_5780;
14076         } else {
14077                 tp->bufmgr_config.mbuf_read_dma_low_water =
14078                         DEFAULT_MB_RDMA_LOW_WATER;
14079                 tp->bufmgr_config.mbuf_mac_rx_low_water =
14080                         DEFAULT_MB_MACRX_LOW_WATER;
14081                 tp->bufmgr_config.mbuf_high_water =
14082                         DEFAULT_MB_HIGH_WATER;
14083
14084                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14085                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
14086                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14087                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
14088                 tp->bufmgr_config.mbuf_high_water_jumbo =
14089                         DEFAULT_MB_HIGH_WATER_JUMBO;
14090         }
14091
14092         tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
14093         tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
14094 }
14095
14096 static char * __devinit tg3_phy_string(struct tg3 *tp)
14097 {
14098         switch (tp->phy_id & PHY_ID_MASK) {
14099         case PHY_ID_BCM5400:    return "5400";
14100         case PHY_ID_BCM5401:    return "5401";
14101         case PHY_ID_BCM5411:    return "5411";
14102         case PHY_ID_BCM5701:    return "5701";
14103         case PHY_ID_BCM5703:    return "5703";
14104         case PHY_ID_BCM5704:    return "5704";
14105         case PHY_ID_BCM5705:    return "5705";
14106         case PHY_ID_BCM5750:    return "5750";
14107         case PHY_ID_BCM5752:    return "5752";
14108         case PHY_ID_BCM5714:    return "5714";
14109         case PHY_ID_BCM5780:    return "5780";
14110         case PHY_ID_BCM5755:    return "5755";
14111         case PHY_ID_BCM5787:    return "5787";
14112         case PHY_ID_BCM5784:    return "5784";
14113         case PHY_ID_BCM5756:    return "5722/5756";
14114         case PHY_ID_BCM5906:    return "5906";
14115         case PHY_ID_BCM5761:    return "5761";
14116         case PHY_ID_BCM5717:    return "5717";
14117         case PHY_ID_BCM8002:    return "8002/serdes";
14118         case 0:                 return "serdes";
14119         default:                return "unknown";
14120         }
14121 }
14122
14123 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
14124 {
14125         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
14126                 strcpy(str, "PCI Express");
14127                 return str;
14128         } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
14129                 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
14130
14131                 strcpy(str, "PCIX:");
14132
14133                 if ((clock_ctrl == 7) ||
14134                     ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
14135                      GRC_MISC_CFG_BOARD_ID_5704CIOBE))
14136                         strcat(str, "133MHz");
14137                 else if (clock_ctrl == 0)
14138                         strcat(str, "33MHz");
14139                 else if (clock_ctrl == 2)
14140                         strcat(str, "50MHz");
14141                 else if (clock_ctrl == 4)
14142                         strcat(str, "66MHz");
14143                 else if (clock_ctrl == 6)
14144                         strcat(str, "100MHz");
14145         } else {
14146                 strcpy(str, "PCI:");
14147                 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
14148                         strcat(str, "66MHz");
14149                 else
14150                         strcat(str, "33MHz");
14151         }
14152         if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
14153                 strcat(str, ":32-bit");
14154         else
14155                 strcat(str, ":64-bit");
14156         return str;
14157 }
14158
14159 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
14160 {
14161         struct pci_dev *peer;
14162         unsigned int func, devnr = tp->pdev->devfn & ~7;
14163
14164         for (func = 0; func < 8; func++) {
14165                 peer = pci_get_slot(tp->pdev->bus, devnr | func);
14166                 if (peer && peer != tp->pdev)
14167                         break;
14168                 pci_dev_put(peer);
14169         }
14170         /* 5704 can be configured in single-port mode, set peer to
14171          * tp->pdev in that case.
14172          */
14173         if (!peer) {
14174                 peer = tp->pdev;
14175                 return peer;
14176         }
14177
14178         /*
14179          * We don't need to keep the refcount elevated; there's no way
14180          * to remove one half of this device without removing the other
14181          */
14182         pci_dev_put(peer);
14183
14184         return peer;
14185 }
14186
14187 static void __devinit tg3_init_coal(struct tg3 *tp)
14188 {
14189         struct ethtool_coalesce *ec = &tp->coal;
14190
14191         memset(ec, 0, sizeof(*ec));
14192         ec->cmd = ETHTOOL_GCOALESCE;
14193         ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
14194         ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
14195         ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
14196         ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
14197         ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
14198         ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
14199         ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
14200         ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
14201         ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
14202
14203         if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
14204                                  HOSTCC_MODE_CLRTICK_TXBD)) {
14205                 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
14206                 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
14207                 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
14208                 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
14209         }
14210
14211         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
14212                 ec->rx_coalesce_usecs_irq = 0;
14213                 ec->tx_coalesce_usecs_irq = 0;
14214                 ec->stats_block_coalesce_usecs = 0;
14215         }
14216 }
14217
14218 static const struct net_device_ops tg3_netdev_ops = {
14219         .ndo_open               = tg3_open,
14220         .ndo_stop               = tg3_close,
14221         .ndo_start_xmit         = tg3_start_xmit,
14222         .ndo_get_stats          = tg3_get_stats,
14223         .ndo_validate_addr      = eth_validate_addr,
14224         .ndo_set_multicast_list = tg3_set_rx_mode,
14225         .ndo_set_mac_address    = tg3_set_mac_addr,
14226         .ndo_do_ioctl           = tg3_ioctl,
14227         .ndo_tx_timeout         = tg3_tx_timeout,
14228         .ndo_change_mtu         = tg3_change_mtu,
14229 #if TG3_VLAN_TAG_USED
14230         .ndo_vlan_rx_register   = tg3_vlan_rx_register,
14231 #endif
14232 #ifdef CONFIG_NET_POLL_CONTROLLER
14233         .ndo_poll_controller    = tg3_poll_controller,
14234 #endif
14235 };
14236
14237 static const struct net_device_ops tg3_netdev_ops_dma_bug = {
14238         .ndo_open               = tg3_open,
14239         .ndo_stop               = tg3_close,
14240         .ndo_start_xmit         = tg3_start_xmit_dma_bug,
14241         .ndo_get_stats          = tg3_get_stats,
14242         .ndo_validate_addr      = eth_validate_addr,
14243         .ndo_set_multicast_list = tg3_set_rx_mode,
14244         .ndo_set_mac_address    = tg3_set_mac_addr,
14245         .ndo_do_ioctl           = tg3_ioctl,
14246         .ndo_tx_timeout         = tg3_tx_timeout,
14247         .ndo_change_mtu         = tg3_change_mtu,
14248 #if TG3_VLAN_TAG_USED
14249         .ndo_vlan_rx_register   = tg3_vlan_rx_register,
14250 #endif
14251 #ifdef CONFIG_NET_POLL_CONTROLLER
14252         .ndo_poll_controller    = tg3_poll_controller,
14253 #endif
14254 };
14255
14256 static int __devinit tg3_init_one(struct pci_dev *pdev,
14257                                   const struct pci_device_id *ent)
14258 {
14259         static int tg3_version_printed = 0;
14260         struct net_device *dev;
14261         struct tg3 *tp;
14262         int i, err, pm_cap;
14263         u32 sndmbx, rcvmbx, intmbx;
14264         char str[40];
14265         u64 dma_mask, persist_dma_mask;
14266
14267         if (tg3_version_printed++ == 0)
14268                 printk(KERN_INFO "%s", version);
14269
14270         err = pci_enable_device(pdev);
14271         if (err) {
14272                 printk(KERN_ERR PFX "Cannot enable PCI device, "
14273                        "aborting.\n");
14274                 return err;
14275         }
14276
14277         err = pci_request_regions(pdev, DRV_MODULE_NAME);
14278         if (err) {
14279                 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
14280                        "aborting.\n");
14281                 goto err_out_disable_pdev;
14282         }
14283
14284         pci_set_master(pdev);
14285
14286         /* Find power-management capability. */
14287         pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
14288         if (pm_cap == 0) {
14289                 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
14290                        "aborting.\n");
14291                 err = -EIO;
14292                 goto err_out_free_res;
14293         }
14294
14295         dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
14296         if (!dev) {
14297                 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
14298                 err = -ENOMEM;
14299                 goto err_out_free_res;
14300         }
14301
14302         SET_NETDEV_DEV(dev, &pdev->dev);
14303
14304 #if TG3_VLAN_TAG_USED
14305         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
14306 #endif
14307
14308         tp = netdev_priv(dev);
14309         tp->pdev = pdev;
14310         tp->dev = dev;
14311         tp->pm_cap = pm_cap;
14312         tp->rx_mode = TG3_DEF_RX_MODE;
14313         tp->tx_mode = TG3_DEF_TX_MODE;
14314
14315         if (tg3_debug > 0)
14316                 tp->msg_enable = tg3_debug;
14317         else
14318                 tp->msg_enable = TG3_DEF_MSG_ENABLE;
14319
14320         /* The word/byte swap controls here control register access byte
14321          * swapping.  DMA data byte swapping is controlled in the GRC_MODE
14322          * setting below.
14323          */
14324         tp->misc_host_ctrl =
14325                 MISC_HOST_CTRL_MASK_PCI_INT |
14326                 MISC_HOST_CTRL_WORD_SWAP |
14327                 MISC_HOST_CTRL_INDIR_ACCESS |
14328                 MISC_HOST_CTRL_PCISTATE_RW;
14329
14330         /* The NONFRM (non-frame) byte/word swap controls take effect
14331          * on descriptor entries, anything which isn't packet data.
14332          *
14333          * The StrongARM chips on the board (one for tx, one for rx)
14334          * are running in big-endian mode.
14335          */
14336         tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
14337                         GRC_MODE_WSWAP_NONFRM_DATA);
14338 #ifdef __BIG_ENDIAN
14339         tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
14340 #endif
14341         spin_lock_init(&tp->lock);
14342         spin_lock_init(&tp->indirect_lock);
14343         INIT_WORK(&tp->reset_task, tg3_reset_task);
14344
14345         tp->regs = pci_ioremap_bar(pdev, BAR_0);
14346         if (!tp->regs) {
14347                 printk(KERN_ERR PFX "Cannot map device registers, "
14348                        "aborting.\n");
14349                 err = -ENOMEM;
14350                 goto err_out_free_dev;
14351         }
14352
14353         tg3_init_link_config(tp);
14354
14355         tp->rx_pending = TG3_DEF_RX_RING_PENDING;
14356         tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
14357
14358         dev->ethtool_ops = &tg3_ethtool_ops;
14359         dev->watchdog_timeo = TG3_TX_TIMEOUT;
14360         dev->irq = pdev->irq;
14361
14362         err = tg3_get_invariants(tp);
14363         if (err) {
14364                 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
14365                        "aborting.\n");
14366                 goto err_out_iounmap;
14367         }
14368
14369         if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
14370             tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
14371                 dev->netdev_ops = &tg3_netdev_ops;
14372         else
14373                 dev->netdev_ops = &tg3_netdev_ops_dma_bug;
14374
14375
14376         /* The EPB bridge inside 5714, 5715, and 5780 and any
14377          * device behind the EPB cannot support DMA addresses > 40-bit.
14378          * On 64-bit systems with IOMMU, use 40-bit dma_mask.
14379          * On 64-bit systems without IOMMU, use 64-bit dma_mask and
14380          * do DMA address check in tg3_start_xmit().
14381          */
14382         if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
14383                 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
14384         else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
14385                 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
14386 #ifdef CONFIG_HIGHMEM
14387                 dma_mask = DMA_BIT_MASK(64);
14388 #endif
14389         } else
14390                 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
14391
14392         /* Configure DMA attributes. */
14393         if (dma_mask > DMA_BIT_MASK(32)) {
14394                 err = pci_set_dma_mask(pdev, dma_mask);
14395                 if (!err) {
14396                         dev->features |= NETIF_F_HIGHDMA;
14397                         err = pci_set_consistent_dma_mask(pdev,
14398                                                           persist_dma_mask);
14399                         if (err < 0) {
14400                                 printk(KERN_ERR PFX "Unable to obtain 64 bit "
14401                                        "DMA for consistent allocations\n");
14402                                 goto err_out_iounmap;
14403                         }
14404                 }
14405         }
14406         if (err || dma_mask == DMA_BIT_MASK(32)) {
14407                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
14408                 if (err) {
14409                         printk(KERN_ERR PFX "No usable DMA configuration, "
14410                                "aborting.\n");
14411                         goto err_out_iounmap;
14412                 }
14413         }
14414
14415         tg3_init_bufmgr_config(tp);
14416
14417         /* Selectively allow TSO based on operating conditions */
14418         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
14419             (tp->fw_needed && !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)))
14420                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
14421         else {
14422                 tp->tg3_flags2 &= ~(TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG);
14423                 tp->fw_needed = NULL;
14424         }
14425
14426         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
14427                 tp->fw_needed = FIRMWARE_TG3;
14428
14429         /* TSO is on by default on chips that support hardware TSO.
14430          * Firmware TSO on older chips gives lower performance, so it
14431          * is off by default, but can be enabled using ethtool.
14432          */
14433         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) &&
14434             (dev->features & NETIF_F_IP_CSUM))
14435                 dev->features |= NETIF_F_TSO;
14436
14437         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
14438             (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3)) {
14439                 if (dev->features & NETIF_F_IPV6_CSUM)
14440                         dev->features |= NETIF_F_TSO6;
14441                 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
14442                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
14443                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
14444                      GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
14445                         GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
14446                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
14447                         dev->features |= NETIF_F_TSO_ECN;
14448         }
14449
14450         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
14451             !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
14452             !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
14453                 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
14454                 tp->rx_pending = 63;
14455         }
14456
14457         err = tg3_get_device_address(tp);
14458         if (err) {
14459                 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
14460                        "aborting.\n");
14461                 goto err_out_fw;
14462         }
14463
14464         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
14465                 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
14466                 if (!tp->aperegs) {
14467                         printk(KERN_ERR PFX "Cannot map APE registers, "
14468                                "aborting.\n");
14469                         err = -ENOMEM;
14470                         goto err_out_fw;
14471                 }
14472
14473                 tg3_ape_lock_init(tp);
14474
14475                 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
14476                         tg3_read_dash_ver(tp);
14477         }
14478
14479         /*
14480          * Reset chip in case UNDI or EFI driver did not shutdown
14481          * DMA self test will enable WDMAC and we'll see (spurious)
14482          * pending DMA on the PCI bus at that point.
14483          */
14484         if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
14485             (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
14486                 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
14487                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14488         }
14489
14490         err = tg3_test_dma(tp);
14491         if (err) {
14492                 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
14493                 goto err_out_apeunmap;
14494         }
14495
14496         /* flow control autonegotiation is default behavior */
14497         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
14498         tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
14499
14500         intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
14501         rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
14502         sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
14503         for (i = 0; i < TG3_IRQ_MAX_VECS; i++) {
14504                 struct tg3_napi *tnapi = &tp->napi[i];
14505
14506                 tnapi->tp = tp;
14507                 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
14508
14509                 tnapi->int_mbox = intmbx;
14510                 if (i < 4)
14511                         intmbx += 0x8;
14512                 else
14513                         intmbx += 0x4;
14514
14515                 tnapi->consmbox = rcvmbx;
14516                 tnapi->prodmbox = sndmbx;
14517
14518                 if (i) {
14519                         tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
14520                         netif_napi_add(dev, &tnapi->napi, tg3_poll_msix, 64);
14521                 } else {
14522                         tnapi->coal_now = HOSTCC_MODE_NOW;
14523                         netif_napi_add(dev, &tnapi->napi, tg3_poll, 64);
14524                 }
14525
14526                 if (!(tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX))
14527                         break;
14528
14529                 /*
14530                  * If we support MSIX, we'll be using RSS.  If we're using
14531                  * RSS, the first vector only handles link interrupts and the
14532                  * remaining vectors handle rx and tx interrupts.  Reuse the
14533                  * mailbox values for the next iteration.  The values we setup
14534                  * above are still useful for the single vectored mode.
14535                  */
14536                 if (!i)
14537                         continue;
14538
14539                 rcvmbx += 0x8;
14540
14541                 if (sndmbx & 0x4)
14542                         sndmbx -= 0x4;
14543                 else
14544                         sndmbx += 0xc;
14545         }
14546
14547         tg3_init_coal(tp);
14548
14549         pci_set_drvdata(pdev, dev);
14550
14551         err = register_netdev(dev);
14552         if (err) {
14553                 printk(KERN_ERR PFX "Cannot register net device, "
14554                        "aborting.\n");
14555                 goto err_out_apeunmap;
14556         }
14557
14558         printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
14559                dev->name,
14560                tp->board_part_number,
14561                tp->pci_chip_rev_id,
14562                tg3_bus_string(tp, str),
14563                dev->dev_addr);
14564
14565         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
14566                 struct phy_device *phydev;
14567                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
14568                 printk(KERN_INFO
14569                        "%s: attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
14570                        tp->dev->name, phydev->drv->name,
14571                        dev_name(&phydev->dev));
14572         } else
14573                 printk(KERN_INFO
14574                        "%s: attached PHY is %s (%s Ethernet) (WireSpeed[%d])\n",
14575                        tp->dev->name, tg3_phy_string(tp),
14576                        ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
14577                         ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
14578                          "10/100/1000Base-T")),
14579                        (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0);
14580
14581         printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
14582                dev->name,
14583                (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
14584                (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
14585                (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
14586                (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
14587                (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
14588         printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
14589                dev->name, tp->dma_rwctrl,
14590                (pdev->dma_mask == DMA_BIT_MASK(32)) ? 32 :
14591                 (((u64) pdev->dma_mask == DMA_BIT_MASK(40)) ? 40 : 64));
14592
14593         return 0;
14594
14595 err_out_apeunmap:
14596         if (tp->aperegs) {
14597                 iounmap(tp->aperegs);
14598                 tp->aperegs = NULL;
14599         }
14600
14601 err_out_fw:
14602         if (tp->fw)
14603                 release_firmware(tp->fw);
14604
14605 err_out_iounmap:
14606         if (tp->regs) {
14607                 iounmap(tp->regs);
14608                 tp->regs = NULL;
14609         }
14610
14611 err_out_free_dev:
14612         free_netdev(dev);
14613
14614 err_out_free_res:
14615         pci_release_regions(pdev);
14616
14617 err_out_disable_pdev:
14618         pci_disable_device(pdev);
14619         pci_set_drvdata(pdev, NULL);
14620         return err;
14621 }
14622
14623 static void __devexit tg3_remove_one(struct pci_dev *pdev)
14624 {
14625         struct net_device *dev = pci_get_drvdata(pdev);
14626
14627         if (dev) {
14628                 struct tg3 *tp = netdev_priv(dev);
14629
14630                 if (tp->fw)
14631                         release_firmware(tp->fw);
14632
14633                 flush_scheduled_work();
14634
14635                 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
14636                         tg3_phy_fini(tp);
14637                         tg3_mdio_fini(tp);
14638                 }
14639
14640                 unregister_netdev(dev);
14641                 if (tp->aperegs) {
14642                         iounmap(tp->aperegs);
14643                         tp->aperegs = NULL;
14644                 }
14645                 if (tp->regs) {
14646                         iounmap(tp->regs);
14647                         tp->regs = NULL;
14648                 }
14649                 free_netdev(dev);
14650                 pci_release_regions(pdev);
14651                 pci_disable_device(pdev);
14652                 pci_set_drvdata(pdev, NULL);
14653         }
14654 }
14655
14656 static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
14657 {
14658         struct net_device *dev = pci_get_drvdata(pdev);
14659         struct tg3 *tp = netdev_priv(dev);
14660         pci_power_t target_state;
14661         int err;
14662
14663         /* PCI register 4 needs to be saved whether netif_running() or not.
14664          * MSI address and data need to be saved if using MSI and
14665          * netif_running().
14666          */
14667         pci_save_state(pdev);
14668
14669         if (!netif_running(dev))
14670                 return 0;
14671
14672         flush_scheduled_work();
14673         tg3_phy_stop(tp);
14674         tg3_netif_stop(tp);
14675
14676         del_timer_sync(&tp->timer);
14677
14678         tg3_full_lock(tp, 1);
14679         tg3_disable_ints(tp);
14680         tg3_full_unlock(tp);
14681
14682         netif_device_detach(dev);
14683
14684         tg3_full_lock(tp, 0);
14685         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14686         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
14687         tg3_full_unlock(tp);
14688
14689         target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot;
14690
14691         err = tg3_set_power_state(tp, target_state);
14692         if (err) {
14693                 int err2;
14694
14695                 tg3_full_lock(tp, 0);
14696
14697                 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
14698                 err2 = tg3_restart_hw(tp, 1);
14699                 if (err2)
14700                         goto out;
14701
14702                 tp->timer.expires = jiffies + tp->timer_offset;
14703                 add_timer(&tp->timer);
14704
14705                 netif_device_attach(dev);
14706                 tg3_netif_start(tp);
14707
14708 out:
14709                 tg3_full_unlock(tp);
14710
14711                 if (!err2)
14712                         tg3_phy_start(tp);
14713         }
14714
14715         return err;
14716 }
14717
14718 static int tg3_resume(struct pci_dev *pdev)
14719 {
14720         struct net_device *dev = pci_get_drvdata(pdev);
14721         struct tg3 *tp = netdev_priv(dev);
14722         int err;
14723
14724         pci_restore_state(tp->pdev);
14725
14726         if (!netif_running(dev))
14727                 return 0;
14728
14729         err = tg3_set_power_state(tp, PCI_D0);
14730         if (err)
14731                 return err;
14732
14733         netif_device_attach(dev);
14734
14735         tg3_full_lock(tp, 0);
14736
14737         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
14738         err = tg3_restart_hw(tp, 1);
14739         if (err)
14740                 goto out;
14741
14742         tp->timer.expires = jiffies + tp->timer_offset;
14743         add_timer(&tp->timer);
14744
14745         tg3_netif_start(tp);
14746
14747 out:
14748         tg3_full_unlock(tp);
14749
14750         if (!err)
14751                 tg3_phy_start(tp);
14752
14753         return err;
14754 }
14755
14756 static struct pci_driver tg3_driver = {
14757         .name           = DRV_MODULE_NAME,
14758         .id_table       = tg3_pci_tbl,
14759         .probe          = tg3_init_one,
14760         .remove         = __devexit_p(tg3_remove_one),
14761         .suspend        = tg3_suspend,
14762         .resume         = tg3_resume
14763 };
14764
14765 static int __init tg3_init(void)
14766 {
14767         return pci_register_driver(&tg3_driver);
14768 }
14769
14770 static void __exit tg3_cleanup(void)
14771 {
14772         pci_unregister_driver(&tg3_driver);
14773 }
14774
14775 module_init(tg3_init);
14776 module_exit(tg3_cleanup);