2 * tg3.c: Broadcom Tigon3 ethernet driver.
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
7 * Copyright (C) 2005-2007 Broadcom Corporation.
10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/kernel.h>
22 #include <linux/types.h>
23 #include <linux/compiler.h>
24 #include <linux/slab.h>
25 #include <linux/delay.h>
27 #include <linux/init.h>
28 #include <linux/ioport.h>
29 #include <linux/pci.h>
30 #include <linux/netdevice.h>
31 #include <linux/etherdevice.h>
32 #include <linux/skbuff.h>
33 #include <linux/ethtool.h>
34 #include <linux/mii.h>
35 #include <linux/if_vlan.h>
37 #include <linux/tcp.h>
38 #include <linux/workqueue.h>
39 #include <linux/prefetch.h>
40 #include <linux/dma-mapping.h>
42 #include <net/checksum.h>
45 #include <asm/system.h>
47 #include <asm/byteorder.h>
48 #include <asm/uaccess.h>
51 #include <asm/idprom.h>
55 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
56 #define TG3_VLAN_TAG_USED 1
58 #define TG3_VLAN_TAG_USED 0
61 #define TG3_TSO_SUPPORT 1
65 #define DRV_MODULE_NAME "tg3"
66 #define PFX DRV_MODULE_NAME ": "
67 #define DRV_MODULE_VERSION "3.92"
68 #define DRV_MODULE_RELDATE "May 2, 2008"
70 #define TG3_DEF_MAC_MODE 0
71 #define TG3_DEF_RX_MODE 0
72 #define TG3_DEF_TX_MODE 0
73 #define TG3_DEF_MSG_ENABLE \
83 /* length of time before we decide the hardware is borked,
84 * and dev->tx_timeout() should be called to fix the problem
86 #define TG3_TX_TIMEOUT (5 * HZ)
88 /* hardware minimum and maximum for a single frame's data payload */
89 #define TG3_MIN_MTU 60
90 #define TG3_MAX_MTU(tp) \
91 ((tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) ? 9000 : 1500)
93 /* These numbers seem to be hard coded in the NIC firmware somehow.
94 * You can't change the ring sizes, but you can change where you place
95 * them in the NIC onboard memory.
97 #define TG3_RX_RING_SIZE 512
98 #define TG3_DEF_RX_RING_PENDING 200
99 #define TG3_RX_JUMBO_RING_SIZE 256
100 #define TG3_DEF_RX_JUMBO_RING_PENDING 100
102 /* Do not place this n-ring entries value into the tp struct itself,
103 * we really want to expose these constants to GCC so that modulo et
104 * al. operations are done with shifts and masks instead of with
105 * hw multiply/modulo instructions. Another solution would be to
106 * replace things like '% foo' with '& (foo - 1)'.
108 #define TG3_RX_RCB_RING_SIZE(tp) \
109 ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ? 512 : 1024)
111 #define TG3_TX_RING_SIZE 512
112 #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
114 #define TG3_RX_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
116 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
117 TG3_RX_JUMBO_RING_SIZE)
118 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
119 TG3_RX_RCB_RING_SIZE(tp))
120 #define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
122 #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
124 #define RX_PKT_BUF_SZ (1536 + tp->rx_offset + 64)
125 #define RX_JUMBO_PKT_BUF_SZ (9046 + tp->rx_offset + 64)
127 /* minimum number of free TX descriptors required to wake up TX process */
128 #define TG3_TX_WAKEUP_THRESH(tp) ((tp)->tx_pending / 4)
130 /* number of ETHTOOL_GSTATS u64's */
131 #define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
133 #define TG3_NUM_TEST 6
135 static char version[] __devinitdata =
136 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
138 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
139 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
140 MODULE_LICENSE("GPL");
141 MODULE_VERSION(DRV_MODULE_VERSION);
143 static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
144 module_param(tg3_debug, int, 0);
145 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
147 static struct pci_device_id tg3_pci_tbl[] = {
148 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
149 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
150 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
151 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
152 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
153 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
154 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
155 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
156 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
157 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
158 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
159 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
160 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
161 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
162 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
163 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
164 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
165 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
166 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
167 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
168 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
169 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
170 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
171 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
172 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
173 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
174 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
175 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
176 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
177 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
178 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
179 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
180 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
181 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
182 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
183 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
184 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
185 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
186 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
187 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
188 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
189 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
190 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
191 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
192 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
193 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
194 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
195 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
196 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
197 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
198 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
199 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
200 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
201 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
202 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
203 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
204 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
205 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
206 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
207 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
208 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
209 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
210 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
211 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
212 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
216 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
218 static const struct {
219 const char string[ETH_GSTRING_LEN];
220 } ethtool_stats_keys[TG3_NUM_STATS] = {
223 { "rx_ucast_packets" },
224 { "rx_mcast_packets" },
225 { "rx_bcast_packets" },
227 { "rx_align_errors" },
228 { "rx_xon_pause_rcvd" },
229 { "rx_xoff_pause_rcvd" },
230 { "rx_mac_ctrl_rcvd" },
231 { "rx_xoff_entered" },
232 { "rx_frame_too_long_errors" },
234 { "rx_undersize_packets" },
235 { "rx_in_length_errors" },
236 { "rx_out_length_errors" },
237 { "rx_64_or_less_octet_packets" },
238 { "rx_65_to_127_octet_packets" },
239 { "rx_128_to_255_octet_packets" },
240 { "rx_256_to_511_octet_packets" },
241 { "rx_512_to_1023_octet_packets" },
242 { "rx_1024_to_1522_octet_packets" },
243 { "rx_1523_to_2047_octet_packets" },
244 { "rx_2048_to_4095_octet_packets" },
245 { "rx_4096_to_8191_octet_packets" },
246 { "rx_8192_to_9022_octet_packets" },
253 { "tx_flow_control" },
255 { "tx_single_collisions" },
256 { "tx_mult_collisions" },
258 { "tx_excessive_collisions" },
259 { "tx_late_collisions" },
260 { "tx_collide_2times" },
261 { "tx_collide_3times" },
262 { "tx_collide_4times" },
263 { "tx_collide_5times" },
264 { "tx_collide_6times" },
265 { "tx_collide_7times" },
266 { "tx_collide_8times" },
267 { "tx_collide_9times" },
268 { "tx_collide_10times" },
269 { "tx_collide_11times" },
270 { "tx_collide_12times" },
271 { "tx_collide_13times" },
272 { "tx_collide_14times" },
273 { "tx_collide_15times" },
274 { "tx_ucast_packets" },
275 { "tx_mcast_packets" },
276 { "tx_bcast_packets" },
277 { "tx_carrier_sense_errors" },
281 { "dma_writeq_full" },
282 { "dma_write_prioq_full" },
286 { "rx_threshold_hit" },
288 { "dma_readq_full" },
289 { "dma_read_prioq_full" },
290 { "tx_comp_queue_full" },
292 { "ring_set_send_prod_index" },
293 { "ring_status_update" },
295 { "nic_avoided_irqs" },
296 { "nic_tx_threshold_hit" }
299 static const struct {
300 const char string[ETH_GSTRING_LEN];
301 } ethtool_test_keys[TG3_NUM_TEST] = {
302 { "nvram test (online) " },
303 { "link test (online) " },
304 { "register test (offline)" },
305 { "memory test (offline)" },
306 { "loopback test (offline)" },
307 { "interrupt test (offline)" },
310 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
312 writel(val, tp->regs + off);
315 static u32 tg3_read32(struct tg3 *tp, u32 off)
317 return (readl(tp->regs + off));
320 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
322 writel(val, tp->aperegs + off);
325 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
327 return (readl(tp->aperegs + off));
330 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
334 spin_lock_irqsave(&tp->indirect_lock, flags);
335 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
336 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
337 spin_unlock_irqrestore(&tp->indirect_lock, flags);
340 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
342 writel(val, tp->regs + off);
343 readl(tp->regs + off);
346 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
351 spin_lock_irqsave(&tp->indirect_lock, flags);
352 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
353 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
354 spin_unlock_irqrestore(&tp->indirect_lock, flags);
358 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
362 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
363 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
364 TG3_64BIT_REG_LOW, val);
367 if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
368 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
369 TG3_64BIT_REG_LOW, val);
373 spin_lock_irqsave(&tp->indirect_lock, flags);
374 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
375 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
376 spin_unlock_irqrestore(&tp->indirect_lock, flags);
378 /* In indirect mode when disabling interrupts, we also need
379 * to clear the interrupt bit in the GRC local ctrl register.
381 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
383 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
384 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
388 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
393 spin_lock_irqsave(&tp->indirect_lock, flags);
394 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
395 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
396 spin_unlock_irqrestore(&tp->indirect_lock, flags);
400 /* usec_wait specifies the wait time in usec when writing to certain registers
401 * where it is unsafe to read back the register without some delay.
402 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
403 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
405 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
407 if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
408 (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
409 /* Non-posted methods */
410 tp->write32(tp, off, val);
413 tg3_write32(tp, off, val);
418 /* Wait again after the read for the posted method to guarantee that
419 * the wait time is met.
425 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
427 tp->write32_mbox(tp, off, val);
428 if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
429 !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
430 tp->read32_mbox(tp, off);
433 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
435 void __iomem *mbox = tp->regs + off;
437 if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
439 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
443 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
445 return (readl(tp->regs + off + GRCMBOX_BASE));
448 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
450 writel(val, tp->regs + off + GRCMBOX_BASE);
453 #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
454 #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
455 #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
456 #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
457 #define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
459 #define tw32(reg,val) tp->write32(tp, reg, val)
460 #define tw32_f(reg,val) _tw32_flush(tp,(reg),(val), 0)
461 #define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
462 #define tr32(reg) tp->read32(tp, reg)
464 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
468 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
469 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
472 spin_lock_irqsave(&tp->indirect_lock, flags);
473 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
474 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
475 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
477 /* Always leave this as zero. */
478 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
480 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
481 tw32_f(TG3PCI_MEM_WIN_DATA, val);
483 /* Always leave this as zero. */
484 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
486 spin_unlock_irqrestore(&tp->indirect_lock, flags);
489 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
493 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
494 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
499 spin_lock_irqsave(&tp->indirect_lock, flags);
500 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
501 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
502 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
504 /* Always leave this as zero. */
505 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
507 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
508 *val = tr32(TG3PCI_MEM_WIN_DATA);
510 /* Always leave this as zero. */
511 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
513 spin_unlock_irqrestore(&tp->indirect_lock, flags);
516 static void tg3_ape_lock_init(struct tg3 *tp)
520 /* Make sure the driver hasn't any stale locks. */
521 for (i = 0; i < 8; i++)
522 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + 4 * i,
523 APE_LOCK_GRANT_DRIVER);
526 static int tg3_ape_lock(struct tg3 *tp, int locknum)
532 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
536 case TG3_APE_LOCK_MEM:
544 tg3_ape_write32(tp, TG3_APE_LOCK_REQ + off, APE_LOCK_REQ_DRIVER);
546 /* Wait for up to 1 millisecond to acquire lock. */
547 for (i = 0; i < 100; i++) {
548 status = tg3_ape_read32(tp, TG3_APE_LOCK_GRANT + off);
549 if (status == APE_LOCK_GRANT_DRIVER)
554 if (status != APE_LOCK_GRANT_DRIVER) {
555 /* Revoke the lock request. */
556 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off,
557 APE_LOCK_GRANT_DRIVER);
565 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
569 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
573 case TG3_APE_LOCK_MEM:
580 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off, APE_LOCK_GRANT_DRIVER);
583 static void tg3_disable_ints(struct tg3 *tp)
585 tw32(TG3PCI_MISC_HOST_CTRL,
586 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
587 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
590 static inline void tg3_cond_int(struct tg3 *tp)
592 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
593 (tp->hw_status->status & SD_STATUS_UPDATED))
594 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
596 tw32(HOSTCC_MODE, tp->coalesce_mode |
597 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
600 static void tg3_enable_ints(struct tg3 *tp)
605 tw32(TG3PCI_MISC_HOST_CTRL,
606 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
607 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
608 (tp->last_tag << 24));
609 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
610 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
611 (tp->last_tag << 24));
615 static inline unsigned int tg3_has_work(struct tg3 *tp)
617 struct tg3_hw_status *sblk = tp->hw_status;
618 unsigned int work_exists = 0;
620 /* check for phy events */
621 if (!(tp->tg3_flags &
622 (TG3_FLAG_USE_LINKCHG_REG |
623 TG3_FLAG_POLL_SERDES))) {
624 if (sblk->status & SD_STATUS_LINK_CHG)
627 /* check for RX/TX work to do */
628 if (sblk->idx[0].tx_consumer != tp->tx_cons ||
629 sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
636 * similar to tg3_enable_ints, but it accurately determines whether there
637 * is new work pending and can return without flushing the PIO write
638 * which reenables interrupts
640 static void tg3_restart_ints(struct tg3 *tp)
642 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
646 /* When doing tagged status, this work check is unnecessary.
647 * The last_tag we write above tells the chip which piece of
648 * work we've completed.
650 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
652 tw32(HOSTCC_MODE, tp->coalesce_mode |
653 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
656 static inline void tg3_netif_stop(struct tg3 *tp)
658 tp->dev->trans_start = jiffies; /* prevent tx timeout */
659 napi_disable(&tp->napi);
660 netif_tx_disable(tp->dev);
663 static inline void tg3_netif_start(struct tg3 *tp)
665 netif_wake_queue(tp->dev);
666 /* NOTE: unconditional netif_wake_queue is only appropriate
667 * so long as all callers are assured to have free tx slots
668 * (such as after tg3_init_hw)
670 napi_enable(&tp->napi);
671 tp->hw_status->status |= SD_STATUS_UPDATED;
675 static void tg3_switch_clocks(struct tg3 *tp)
677 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
680 if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
681 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
684 orig_clock_ctrl = clock_ctrl;
685 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
686 CLOCK_CTRL_CLKRUN_OENABLE |
688 tp->pci_clock_ctrl = clock_ctrl;
690 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
691 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
692 tw32_wait_f(TG3PCI_CLOCK_CTRL,
693 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
695 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
696 tw32_wait_f(TG3PCI_CLOCK_CTRL,
698 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
700 tw32_wait_f(TG3PCI_CLOCK_CTRL,
701 clock_ctrl | (CLOCK_CTRL_ALTCLK),
704 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
707 #define PHY_BUSY_LOOPS 5000
709 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
715 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
717 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
723 frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
724 MI_COM_PHY_ADDR_MASK);
725 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
726 MI_COM_REG_ADDR_MASK);
727 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
729 tw32_f(MAC_MI_COM, frame_val);
731 loops = PHY_BUSY_LOOPS;
734 frame_val = tr32(MAC_MI_COM);
736 if ((frame_val & MI_COM_BUSY) == 0) {
738 frame_val = tr32(MAC_MI_COM);
746 *val = frame_val & MI_COM_DATA_MASK;
750 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
751 tw32_f(MAC_MI_MODE, tp->mi_mode);
758 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
764 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 &&
765 (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
768 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
770 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
774 frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
775 MI_COM_PHY_ADDR_MASK);
776 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
777 MI_COM_REG_ADDR_MASK);
778 frame_val |= (val & MI_COM_DATA_MASK);
779 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
781 tw32_f(MAC_MI_COM, frame_val);
783 loops = PHY_BUSY_LOOPS;
786 frame_val = tr32(MAC_MI_COM);
787 if ((frame_val & MI_COM_BUSY) == 0) {
789 frame_val = tr32(MAC_MI_COM);
799 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
800 tw32_f(MAC_MI_MODE, tp->mi_mode);
807 static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
809 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
810 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
813 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
817 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
818 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
821 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
824 if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &ephy)) {
825 tg3_writephy(tp, MII_TG3_EPHY_TEST,
826 ephy | MII_TG3_EPHY_SHADOW_EN);
827 if (!tg3_readphy(tp, MII_TG3_EPHYTST_MISCCTRL, &phy)) {
829 phy |= MII_TG3_EPHYTST_MISCCTRL_MDIX;
831 phy &= ~MII_TG3_EPHYTST_MISCCTRL_MDIX;
832 tg3_writephy(tp, MII_TG3_EPHYTST_MISCCTRL, phy);
834 tg3_writephy(tp, MII_TG3_EPHY_TEST, ephy);
837 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
838 MII_TG3_AUXCTL_SHDWSEL_MISC;
839 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
840 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
842 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
844 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
845 phy |= MII_TG3_AUXCTL_MISC_WREN;
846 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
851 static void tg3_phy_set_wirespeed(struct tg3 *tp)
855 if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
858 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
859 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
860 tg3_writephy(tp, MII_TG3_AUX_CTRL,
861 (val | (1 << 15) | (1 << 4)));
864 static int tg3_bmcr_reset(struct tg3 *tp)
869 /* OK, reset it, and poll the BMCR_RESET bit until it
870 * clears or we time out.
872 phy_control = BMCR_RESET;
873 err = tg3_writephy(tp, MII_BMCR, phy_control);
879 err = tg3_readphy(tp, MII_BMCR, &phy_control);
883 if ((phy_control & BMCR_RESET) == 0) {
895 static void tg3_phy_apply_otp(struct tg3 *tp)
904 /* Enable SM_DSP clock and tx 6dB coding. */
905 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
906 MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
907 MII_TG3_AUXCTL_ACTL_TX_6DB;
908 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
910 phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
911 phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
912 tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
914 phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
915 ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
916 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
918 phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
919 phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
920 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
922 phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
923 tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
925 phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
926 tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
928 phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
929 ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
930 tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
932 /* Turn off SM_DSP clock. */
933 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
934 MII_TG3_AUXCTL_ACTL_TX_6DB;
935 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
938 static int tg3_wait_macro_done(struct tg3 *tp)
945 if (!tg3_readphy(tp, 0x16, &tmp32)) {
946 if ((tmp32 & 0x1000) == 0)
956 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
958 static const u32 test_pat[4][6] = {
959 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
960 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
961 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
962 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
966 for (chan = 0; chan < 4; chan++) {
969 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
970 (chan * 0x2000) | 0x0200);
971 tg3_writephy(tp, 0x16, 0x0002);
973 for (i = 0; i < 6; i++)
974 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
977 tg3_writephy(tp, 0x16, 0x0202);
978 if (tg3_wait_macro_done(tp)) {
983 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
984 (chan * 0x2000) | 0x0200);
985 tg3_writephy(tp, 0x16, 0x0082);
986 if (tg3_wait_macro_done(tp)) {
991 tg3_writephy(tp, 0x16, 0x0802);
992 if (tg3_wait_macro_done(tp)) {
997 for (i = 0; i < 6; i += 2) {
1000 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1001 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1002 tg3_wait_macro_done(tp)) {
1008 if (low != test_pat[chan][i] ||
1009 high != test_pat[chan][i+1]) {
1010 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1011 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1012 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1022 static int tg3_phy_reset_chanpat(struct tg3 *tp)
1026 for (chan = 0; chan < 4; chan++) {
1029 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1030 (chan * 0x2000) | 0x0200);
1031 tg3_writephy(tp, 0x16, 0x0002);
1032 for (i = 0; i < 6; i++)
1033 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1034 tg3_writephy(tp, 0x16, 0x0202);
1035 if (tg3_wait_macro_done(tp))
1042 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1044 u32 reg32, phy9_orig;
1045 int retries, do_phy_reset, err;
1051 err = tg3_bmcr_reset(tp);
1057 /* Disable transmitter and interrupt. */
1058 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32))
1062 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1064 /* Set full-duplex, 1000 mbps. */
1065 tg3_writephy(tp, MII_BMCR,
1066 BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1068 /* Set to master mode. */
1069 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1072 tg3_writephy(tp, MII_TG3_CTRL,
1073 (MII_TG3_CTRL_AS_MASTER |
1074 MII_TG3_CTRL_ENABLE_AS_MASTER));
1076 /* Enable SM_DSP_CLOCK and 6dB. */
1077 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1079 /* Block the PHY control access. */
1080 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1081 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
1083 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1086 } while (--retries);
1088 err = tg3_phy_reset_chanpat(tp);
1092 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1093 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
1095 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1096 tg3_writephy(tp, 0x16, 0x0000);
1098 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1099 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1100 /* Set Extended packet length bit for jumbo frames */
1101 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1104 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1107 tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1109 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32)) {
1111 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1118 static void tg3_link_report(struct tg3 *);
1120 /* This will reset the tigon3 PHY if there is no valid
1121 * link unless the FORCE argument is non-zero.
1123 static int tg3_phy_reset(struct tg3 *tp)
1129 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1132 val = tr32(GRC_MISC_CFG);
1133 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1136 err = tg3_readphy(tp, MII_BMSR, &phy_status);
1137 err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1141 if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1142 netif_carrier_off(tp->dev);
1143 tg3_link_report(tp);
1146 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1147 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1148 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1149 err = tg3_phy_reset_5703_4_5(tp);
1156 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1157 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1158 cpmuctrl = tr32(TG3_CPMU_CTRL);
1159 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1161 cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1164 err = tg3_bmcr_reset(tp);
1168 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1171 phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1172 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy);
1174 tw32(TG3_CPMU_CTRL, cpmuctrl);
1177 if (tp->tg3_flags3 & TG3_FLG3_5761_5784_AX_FIXES) {
1180 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1181 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1182 CPMU_LSPD_1000MB_MACCLK_12_5) {
1183 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1185 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1188 /* Disable GPHY autopowerdown. */
1189 tg3_writephy(tp, MII_TG3_MISC_SHDW,
1190 MII_TG3_MISC_SHDW_WREN |
1191 MII_TG3_MISC_SHDW_APD_SEL |
1192 MII_TG3_MISC_SHDW_APD_WKTM_84MS);
1195 tg3_phy_apply_otp(tp);
1198 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1199 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1200 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1201 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1202 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1203 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
1204 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1206 if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
1207 tg3_writephy(tp, 0x1c, 0x8d68);
1208 tg3_writephy(tp, 0x1c, 0x8d68);
1210 if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1211 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1212 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1213 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1214 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1215 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1216 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1217 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1218 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1220 else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1221 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1222 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1223 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1224 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1225 tg3_writephy(tp, MII_TG3_TEST1,
1226 MII_TG3_TEST1_TRIM_EN | 0x4);
1228 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
1229 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1231 /* Set Extended packet length bit (bit 14) on all chips that */
1232 /* support jumbo frames */
1233 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1234 /* Cannot do read-modify-write on 5401 */
1235 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1236 } else if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1239 /* Set bit 14 with read-modify-write to preserve other bits */
1240 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1241 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1242 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1245 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1246 * jumbo frames transmission.
1248 if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1251 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
1252 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1253 phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1256 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1257 /* adjust output voltage */
1258 tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x12);
1261 tg3_phy_toggle_automdix(tp, 1);
1262 tg3_phy_set_wirespeed(tp);
1266 static void tg3_frob_aux_power(struct tg3 *tp)
1268 struct tg3 *tp_peer = tp;
1270 if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
1273 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
1274 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
1275 struct net_device *dev_peer;
1277 dev_peer = pci_get_drvdata(tp->pdev_peer);
1278 /* remove_one() may have been run on the peer. */
1282 tp_peer = netdev_priv(dev_peer);
1285 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1286 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
1287 (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1288 (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
1289 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1290 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1291 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1292 (GRC_LCLCTRL_GPIO_OE0 |
1293 GRC_LCLCTRL_GPIO_OE1 |
1294 GRC_LCLCTRL_GPIO_OE2 |
1295 GRC_LCLCTRL_GPIO_OUTPUT0 |
1296 GRC_LCLCTRL_GPIO_OUTPUT1),
1300 u32 grc_local_ctrl = 0;
1302 if (tp_peer != tp &&
1303 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1306 /* Workaround to prevent overdrawing Amps. */
1307 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
1309 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
1310 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1311 grc_local_ctrl, 100);
1314 /* On 5753 and variants, GPIO2 cannot be used. */
1315 no_gpio2 = tp->nic_sram_data_cfg &
1316 NIC_SRAM_DATA_CFG_NO_GPIO2;
1318 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
1319 GRC_LCLCTRL_GPIO_OE1 |
1320 GRC_LCLCTRL_GPIO_OE2 |
1321 GRC_LCLCTRL_GPIO_OUTPUT1 |
1322 GRC_LCLCTRL_GPIO_OUTPUT2;
1324 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
1325 GRC_LCLCTRL_GPIO_OUTPUT2);
1327 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1328 grc_local_ctrl, 100);
1330 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
1332 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1333 grc_local_ctrl, 100);
1336 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
1337 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1338 grc_local_ctrl, 100);
1342 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
1343 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
1344 if (tp_peer != tp &&
1345 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1348 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1349 (GRC_LCLCTRL_GPIO_OE1 |
1350 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1352 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1353 GRC_LCLCTRL_GPIO_OE1, 100);
1355 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1356 (GRC_LCLCTRL_GPIO_OE1 |
1357 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1362 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
1364 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
1366 else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411) {
1367 if (speed != SPEED_10)
1369 } else if (speed == SPEED_10)
1375 static int tg3_setup_phy(struct tg3 *, int);
1377 #define RESET_KIND_SHUTDOWN 0
1378 #define RESET_KIND_INIT 1
1379 #define RESET_KIND_SUSPEND 2
1381 static void tg3_write_sig_post_reset(struct tg3 *, int);
1382 static int tg3_halt_cpu(struct tg3 *, u32);
1383 static int tg3_nvram_lock(struct tg3 *);
1384 static void tg3_nvram_unlock(struct tg3 *);
1386 static void tg3_power_down_phy(struct tg3 *tp)
1390 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
1391 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1392 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
1393 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
1396 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
1397 tw32(SG_DIG_CTRL, sg_dig_ctrl);
1398 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
1403 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1405 val = tr32(GRC_MISC_CFG);
1406 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
1410 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1411 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
1412 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x01b2);
1415 /* The PHY should not be powered down on some chips because
1418 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1419 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1420 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
1421 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
1424 if (tp->tg3_flags3 & TG3_FLG3_5761_5784_AX_FIXES) {
1425 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1426 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1427 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
1428 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1431 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
1434 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
1437 u16 power_control, power_caps;
1438 int pm = tp->pm_cap;
1440 /* Make sure register accesses (indirect or otherwise)
1441 * will function correctly.
1443 pci_write_config_dword(tp->pdev,
1444 TG3PCI_MISC_HOST_CTRL,
1445 tp->misc_host_ctrl);
1447 pci_read_config_word(tp->pdev,
1450 power_control |= PCI_PM_CTRL_PME_STATUS;
1451 power_control &= ~(PCI_PM_CTRL_STATE_MASK);
1455 pci_write_config_word(tp->pdev,
1458 udelay(100); /* Delay after power state change */
1460 /* Switch out of Vaux if it is a NIC */
1461 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
1462 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
1479 printk(KERN_WARNING PFX "%s: Invalid power state (%d) "
1481 tp->dev->name, state);
1485 power_control |= PCI_PM_CTRL_PME_ENABLE;
1487 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
1488 tw32(TG3PCI_MISC_HOST_CTRL,
1489 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
1491 if (tp->link_config.phy_is_low_power == 0) {
1492 tp->link_config.phy_is_low_power = 1;
1493 tp->link_config.orig_speed = tp->link_config.speed;
1494 tp->link_config.orig_duplex = tp->link_config.duplex;
1495 tp->link_config.orig_autoneg = tp->link_config.autoneg;
1498 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
1499 tp->link_config.speed = SPEED_10;
1500 tp->link_config.duplex = DUPLEX_HALF;
1501 tp->link_config.autoneg = AUTONEG_ENABLE;
1502 tg3_setup_phy(tp, 0);
1505 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1508 val = tr32(GRC_VCPU_EXT_CTRL);
1509 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
1510 } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
1514 for (i = 0; i < 200; i++) {
1515 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
1516 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
1521 if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
1522 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
1523 WOL_DRV_STATE_SHUTDOWN |
1527 pci_read_config_word(tp->pdev, pm + PCI_PM_PMC, &power_caps);
1529 if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE) {
1532 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
1533 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
1536 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
1537 mac_mode = MAC_MODE_PORT_MODE_GMII;
1539 mac_mode = MAC_MODE_PORT_MODE_MII;
1541 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
1542 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
1544 u32 speed = (tp->tg3_flags &
1545 TG3_FLAG_WOL_SPEED_100MB) ?
1546 SPEED_100 : SPEED_10;
1547 if (tg3_5700_link_polarity(tp, speed))
1548 mac_mode |= MAC_MODE_LINK_POLARITY;
1550 mac_mode &= ~MAC_MODE_LINK_POLARITY;
1553 mac_mode = MAC_MODE_PORT_MODE_TBI;
1556 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
1557 tw32(MAC_LED_CTRL, tp->led_ctrl);
1559 if (((power_caps & PCI_PM_CAP_PME_D3cold) &&
1560 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)))
1561 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
1563 tw32_f(MAC_MODE, mac_mode);
1566 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
1570 if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
1571 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1572 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
1575 base_val = tp->pci_clock_ctrl;
1576 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
1577 CLOCK_CTRL_TXCLK_DISABLE);
1579 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
1580 CLOCK_CTRL_PWRDOWN_PLL133, 40);
1581 } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1582 (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
1583 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
1585 } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
1586 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
1587 u32 newbits1, newbits2;
1589 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1590 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1591 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
1592 CLOCK_CTRL_TXCLK_DISABLE |
1594 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1595 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
1596 newbits1 = CLOCK_CTRL_625_CORE;
1597 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
1599 newbits1 = CLOCK_CTRL_ALTCLK;
1600 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1603 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
1606 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
1609 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
1612 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1613 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1614 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
1615 CLOCK_CTRL_TXCLK_DISABLE |
1616 CLOCK_CTRL_44MHZ_CORE);
1618 newbits3 = CLOCK_CTRL_44MHZ_CORE;
1621 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1622 tp->pci_clock_ctrl | newbits3, 40);
1626 if (!(tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
1627 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
1628 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
1629 tg3_power_down_phy(tp);
1631 tg3_frob_aux_power(tp);
1633 /* Workaround for unstable PLL clock */
1634 if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
1635 (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
1636 u32 val = tr32(0x7d00);
1638 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
1640 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
1643 err = tg3_nvram_lock(tp);
1644 tg3_halt_cpu(tp, RX_CPU_BASE);
1646 tg3_nvram_unlock(tp);
1650 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
1652 /* Finally, set the new power state. */
1653 pci_write_config_word(tp->pdev, pm + PCI_PM_CTRL, power_control);
1654 udelay(100); /* Delay after power state change */
1659 /* tp->lock is held. */
1660 static void tg3_wait_for_event_ack(struct tg3 *tp)
1664 /* Wait for up to 2.5 milliseconds */
1665 for (i = 0; i < 250000; i++) {
1666 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1672 /* tp->lock is held. */
1673 static void tg3_ump_link_report(struct tg3 *tp)
1678 if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1679 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
1682 tg3_wait_for_event_ack(tp);
1684 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1686 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1689 if (!tg3_readphy(tp, MII_BMCR, ®))
1691 if (!tg3_readphy(tp, MII_BMSR, ®))
1692 val |= (reg & 0xffff);
1693 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1696 if (!tg3_readphy(tp, MII_ADVERTISE, ®))
1698 if (!tg3_readphy(tp, MII_LPA, ®))
1699 val |= (reg & 0xffff);
1700 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1703 if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) {
1704 if (!tg3_readphy(tp, MII_CTRL1000, ®))
1706 if (!tg3_readphy(tp, MII_STAT1000, ®))
1707 val |= (reg & 0xffff);
1709 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1711 if (!tg3_readphy(tp, MII_PHYADDR, ®))
1715 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1717 val = tr32(GRC_RX_CPU_EVENT);
1718 val |= GRC_RX_CPU_DRIVER_EVENT;
1719 tw32_f(GRC_RX_CPU_EVENT, val);
1722 static void tg3_link_report(struct tg3 *tp)
1724 if (!netif_carrier_ok(tp->dev)) {
1725 if (netif_msg_link(tp))
1726 printk(KERN_INFO PFX "%s: Link is down.\n",
1728 tg3_ump_link_report(tp);
1729 } else if (netif_msg_link(tp)) {
1730 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1732 (tp->link_config.active_speed == SPEED_1000 ?
1734 (tp->link_config.active_speed == SPEED_100 ?
1736 (tp->link_config.active_duplex == DUPLEX_FULL ?
1739 printk(KERN_INFO PFX
1740 "%s: Flow control is %s for TX and %s for RX.\n",
1742 (tp->link_config.active_flowctrl & TG3_FLOW_CTRL_TX) ?
1744 (tp->link_config.active_flowctrl & TG3_FLOW_CTRL_RX) ?
1746 tg3_ump_link_report(tp);
1750 static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1754 if ((flow_ctrl & TG3_FLOW_CTRL_TX) && (flow_ctrl & TG3_FLOW_CTRL_RX))
1755 miireg = ADVERTISE_PAUSE_CAP;
1756 else if (flow_ctrl & TG3_FLOW_CTRL_TX)
1757 miireg = ADVERTISE_PAUSE_ASYM;
1758 else if (flow_ctrl & TG3_FLOW_CTRL_RX)
1759 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1766 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1770 if ((flow_ctrl & TG3_FLOW_CTRL_TX) && (flow_ctrl & TG3_FLOW_CTRL_RX))
1771 miireg = ADVERTISE_1000XPAUSE;
1772 else if (flow_ctrl & TG3_FLOW_CTRL_TX)
1773 miireg = ADVERTISE_1000XPSE_ASYM;
1774 else if (flow_ctrl & TG3_FLOW_CTRL_RX)
1775 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1782 static u8 tg3_resolve_flowctrl_1000T(u16 lcladv, u16 rmtadv)
1786 if (lcladv & ADVERTISE_PAUSE_CAP) {
1787 if (lcladv & ADVERTISE_PAUSE_ASYM) {
1788 if (rmtadv & LPA_PAUSE_CAP)
1789 cap = TG3_FLOW_CTRL_TX | TG3_FLOW_CTRL_RX;
1790 else if (rmtadv & LPA_PAUSE_ASYM)
1791 cap = TG3_FLOW_CTRL_RX;
1793 if (rmtadv & LPA_PAUSE_CAP)
1794 cap = TG3_FLOW_CTRL_TX | TG3_FLOW_CTRL_RX;
1796 } else if (lcladv & ADVERTISE_PAUSE_ASYM) {
1797 if ((rmtadv & LPA_PAUSE_CAP) && (rmtadv & LPA_PAUSE_ASYM))
1798 cap = TG3_FLOW_CTRL_TX;
1804 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1808 if (lcladv & ADVERTISE_1000XPAUSE) {
1809 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1810 if (rmtadv & LPA_1000XPAUSE)
1811 cap = TG3_FLOW_CTRL_TX | TG3_FLOW_CTRL_RX;
1812 else if (rmtadv & LPA_1000XPAUSE_ASYM)
1813 cap = TG3_FLOW_CTRL_RX;
1815 if (rmtadv & LPA_1000XPAUSE)
1816 cap = TG3_FLOW_CTRL_TX | TG3_FLOW_CTRL_RX;
1818 } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1819 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1820 cap = TG3_FLOW_CTRL_TX;
1826 static void tg3_setup_flow_control(struct tg3 *tp, u32 local_adv, u32 remote_adv)
1828 u8 new_tg3_flags = 0;
1829 u32 old_rx_mode = tp->rx_mode;
1830 u32 old_tx_mode = tp->tx_mode;
1832 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
1833 (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1834 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1835 new_tg3_flags = tg3_resolve_flowctrl_1000X(local_adv,
1838 new_tg3_flags = tg3_resolve_flowctrl_1000T(local_adv,
1841 new_tg3_flags = tp->link_config.flowctrl;
1844 tp->link_config.active_flowctrl = new_tg3_flags;
1846 if (new_tg3_flags & TG3_FLOW_CTRL_RX)
1847 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1849 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1851 if (old_rx_mode != tp->rx_mode) {
1852 tw32_f(MAC_RX_MODE, tp->rx_mode);
1855 if (new_tg3_flags & TG3_FLOW_CTRL_TX)
1856 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1858 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1860 if (old_tx_mode != tp->tx_mode) {
1861 tw32_f(MAC_TX_MODE, tp->tx_mode);
1865 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
1867 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
1868 case MII_TG3_AUX_STAT_10HALF:
1870 *duplex = DUPLEX_HALF;
1873 case MII_TG3_AUX_STAT_10FULL:
1875 *duplex = DUPLEX_FULL;
1878 case MII_TG3_AUX_STAT_100HALF:
1880 *duplex = DUPLEX_HALF;
1883 case MII_TG3_AUX_STAT_100FULL:
1885 *duplex = DUPLEX_FULL;
1888 case MII_TG3_AUX_STAT_1000HALF:
1889 *speed = SPEED_1000;
1890 *duplex = DUPLEX_HALF;
1893 case MII_TG3_AUX_STAT_1000FULL:
1894 *speed = SPEED_1000;
1895 *duplex = DUPLEX_FULL;
1899 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1900 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
1902 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
1906 *speed = SPEED_INVALID;
1907 *duplex = DUPLEX_INVALID;
1912 static void tg3_phy_copper_begin(struct tg3 *tp)
1917 if (tp->link_config.phy_is_low_power) {
1918 /* Entering low power mode. Disable gigabit and
1919 * 100baseT advertisements.
1921 tg3_writephy(tp, MII_TG3_CTRL, 0);
1923 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
1924 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1925 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
1926 new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
1928 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1929 } else if (tp->link_config.speed == SPEED_INVALID) {
1930 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
1931 tp->link_config.advertising &=
1932 ~(ADVERTISED_1000baseT_Half |
1933 ADVERTISED_1000baseT_Full);
1935 new_adv = ADVERTISE_CSMA;
1936 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
1937 new_adv |= ADVERTISE_10HALF;
1938 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
1939 new_adv |= ADVERTISE_10FULL;
1940 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
1941 new_adv |= ADVERTISE_100HALF;
1942 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
1943 new_adv |= ADVERTISE_100FULL;
1945 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
1947 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1949 if (tp->link_config.advertising &
1950 (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
1952 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
1953 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
1954 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
1955 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
1956 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
1957 (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1958 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
1959 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1960 MII_TG3_CTRL_ENABLE_AS_MASTER);
1961 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1963 tg3_writephy(tp, MII_TG3_CTRL, 0);
1966 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
1967 new_adv |= ADVERTISE_CSMA;
1969 /* Asking for a specific link mode. */
1970 if (tp->link_config.speed == SPEED_1000) {
1971 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1973 if (tp->link_config.duplex == DUPLEX_FULL)
1974 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
1976 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
1977 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1978 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
1979 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1980 MII_TG3_CTRL_ENABLE_AS_MASTER);
1982 if (tp->link_config.speed == SPEED_100) {
1983 if (tp->link_config.duplex == DUPLEX_FULL)
1984 new_adv |= ADVERTISE_100FULL;
1986 new_adv |= ADVERTISE_100HALF;
1988 if (tp->link_config.duplex == DUPLEX_FULL)
1989 new_adv |= ADVERTISE_10FULL;
1991 new_adv |= ADVERTISE_10HALF;
1993 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1998 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2001 if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2002 tp->link_config.speed != SPEED_INVALID) {
2003 u32 bmcr, orig_bmcr;
2005 tp->link_config.active_speed = tp->link_config.speed;
2006 tp->link_config.active_duplex = tp->link_config.duplex;
2009 switch (tp->link_config.speed) {
2015 bmcr |= BMCR_SPEED100;
2019 bmcr |= TG3_BMCR_SPEED1000;
2023 if (tp->link_config.duplex == DUPLEX_FULL)
2024 bmcr |= BMCR_FULLDPLX;
2026 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2027 (bmcr != orig_bmcr)) {
2028 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2029 for (i = 0; i < 1500; i++) {
2033 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2034 tg3_readphy(tp, MII_BMSR, &tmp))
2036 if (!(tmp & BMSR_LSTATUS)) {
2041 tg3_writephy(tp, MII_BMCR, bmcr);
2045 tg3_writephy(tp, MII_BMCR,
2046 BMCR_ANENABLE | BMCR_ANRESTART);
2050 static int tg3_init_5401phy_dsp(struct tg3 *tp)
2054 /* Turn off tap power management. */
2055 /* Set Extended packet length bit */
2056 err = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2058 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
2059 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
2061 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
2062 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
2064 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2065 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
2067 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2068 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
2070 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2071 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
2078 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
2080 u32 adv_reg, all_mask = 0;
2082 if (mask & ADVERTISED_10baseT_Half)
2083 all_mask |= ADVERTISE_10HALF;
2084 if (mask & ADVERTISED_10baseT_Full)
2085 all_mask |= ADVERTISE_10FULL;
2086 if (mask & ADVERTISED_100baseT_Half)
2087 all_mask |= ADVERTISE_100HALF;
2088 if (mask & ADVERTISED_100baseT_Full)
2089 all_mask |= ADVERTISE_100FULL;
2091 if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
2094 if ((adv_reg & all_mask) != all_mask)
2096 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
2100 if (mask & ADVERTISED_1000baseT_Half)
2101 all_mask |= ADVERTISE_1000HALF;
2102 if (mask & ADVERTISED_1000baseT_Full)
2103 all_mask |= ADVERTISE_1000FULL;
2105 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
2108 if ((tg3_ctrl & all_mask) != all_mask)
2114 static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
2118 if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
2121 curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2122 reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2124 if (tp->link_config.active_duplex == DUPLEX_FULL) {
2125 if (curadv != reqadv)
2128 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
2129 tg3_readphy(tp, MII_LPA, rmtadv);
2131 /* Reprogram the advertisement register, even if it
2132 * does not affect the current link. If the link
2133 * gets renegotiated in the future, we can save an
2134 * additional renegotiation cycle by advertising
2135 * it correctly in the first place.
2137 if (curadv != reqadv) {
2138 *lcladv &= ~(ADVERTISE_PAUSE_CAP |
2139 ADVERTISE_PAUSE_ASYM);
2140 tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
2147 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
2149 int current_link_up;
2151 u32 lcl_adv, rmt_adv;
2159 (MAC_STATUS_SYNC_CHANGED |
2160 MAC_STATUS_CFG_CHANGED |
2161 MAC_STATUS_MI_COMPLETION |
2162 MAC_STATUS_LNKSTATE_CHANGED));
2165 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
2167 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
2171 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
2173 /* Some third-party PHYs need to be reset on link going
2176 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2177 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2178 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
2179 netif_carrier_ok(tp->dev)) {
2180 tg3_readphy(tp, MII_BMSR, &bmsr);
2181 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
2182 !(bmsr & BMSR_LSTATUS))
2188 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
2189 tg3_readphy(tp, MII_BMSR, &bmsr);
2190 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
2191 !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
2194 if (!(bmsr & BMSR_LSTATUS)) {
2195 err = tg3_init_5401phy_dsp(tp);
2199 tg3_readphy(tp, MII_BMSR, &bmsr);
2200 for (i = 0; i < 1000; i++) {
2202 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
2203 (bmsr & BMSR_LSTATUS)) {
2209 if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
2210 !(bmsr & BMSR_LSTATUS) &&
2211 tp->link_config.active_speed == SPEED_1000) {
2212 err = tg3_phy_reset(tp);
2214 err = tg3_init_5401phy_dsp(tp);
2219 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2220 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
2221 /* 5701 {A0,B0} CRC bug workaround */
2222 tg3_writephy(tp, 0x15, 0x0a75);
2223 tg3_writephy(tp, 0x1c, 0x8c68);
2224 tg3_writephy(tp, 0x1c, 0x8d68);
2225 tg3_writephy(tp, 0x1c, 0x8c68);
2228 /* Clear pending interrupts... */
2229 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
2230 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
2232 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
2233 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
2234 else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
2235 tg3_writephy(tp, MII_TG3_IMASK, ~0);
2237 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2238 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2239 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
2240 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2241 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
2243 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
2246 current_link_up = 0;
2247 current_speed = SPEED_INVALID;
2248 current_duplex = DUPLEX_INVALID;
2250 if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
2253 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
2254 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
2255 if (!(val & (1 << 10))) {
2257 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
2263 for (i = 0; i < 100; i++) {
2264 tg3_readphy(tp, MII_BMSR, &bmsr);
2265 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
2266 (bmsr & BMSR_LSTATUS))
2271 if (bmsr & BMSR_LSTATUS) {
2274 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
2275 for (i = 0; i < 2000; i++) {
2277 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
2282 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
2287 for (i = 0; i < 200; i++) {
2288 tg3_readphy(tp, MII_BMCR, &bmcr);
2289 if (tg3_readphy(tp, MII_BMCR, &bmcr))
2291 if (bmcr && bmcr != 0x7fff)
2299 tp->link_config.active_speed = current_speed;
2300 tp->link_config.active_duplex = current_duplex;
2302 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2303 if ((bmcr & BMCR_ANENABLE) &&
2304 tg3_copper_is_advertising_all(tp,
2305 tp->link_config.advertising)) {
2306 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
2308 current_link_up = 1;
2311 if (!(bmcr & BMCR_ANENABLE) &&
2312 tp->link_config.speed == current_speed &&
2313 tp->link_config.duplex == current_duplex &&
2314 tp->link_config.flowctrl ==
2315 tp->link_config.active_flowctrl) {
2316 current_link_up = 1;
2320 if (current_link_up == 1 &&
2321 tp->link_config.active_duplex == DUPLEX_FULL)
2322 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
2326 if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
2329 tg3_phy_copper_begin(tp);
2331 tg3_readphy(tp, MII_BMSR, &tmp);
2332 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
2333 (tmp & BMSR_LSTATUS))
2334 current_link_up = 1;
2337 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
2338 if (current_link_up == 1) {
2339 if (tp->link_config.active_speed == SPEED_100 ||
2340 tp->link_config.active_speed == SPEED_10)
2341 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
2343 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
2345 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
2347 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
2348 if (tp->link_config.active_duplex == DUPLEX_HALF)
2349 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
2351 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
2352 if (current_link_up == 1 &&
2353 tg3_5700_link_polarity(tp, tp->link_config.active_speed))
2354 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
2356 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
2359 /* ??? Without this setting Netgear GA302T PHY does not
2360 * ??? send/receive packets...
2362 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
2363 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
2364 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
2365 tw32_f(MAC_MI_MODE, tp->mi_mode);
2369 tw32_f(MAC_MODE, tp->mac_mode);
2372 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
2373 /* Polled via timer. */
2374 tw32_f(MAC_EVENT, 0);
2376 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2380 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
2381 current_link_up == 1 &&
2382 tp->link_config.active_speed == SPEED_1000 &&
2383 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
2384 (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
2387 (MAC_STATUS_SYNC_CHANGED |
2388 MAC_STATUS_CFG_CHANGED));
2391 NIC_SRAM_FIRMWARE_MBOX,
2392 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
2395 if (current_link_up != netif_carrier_ok(tp->dev)) {
2396 if (current_link_up)
2397 netif_carrier_on(tp->dev);
2399 netif_carrier_off(tp->dev);
2400 tg3_link_report(tp);
2406 struct tg3_fiber_aneginfo {
2408 #define ANEG_STATE_UNKNOWN 0
2409 #define ANEG_STATE_AN_ENABLE 1
2410 #define ANEG_STATE_RESTART_INIT 2
2411 #define ANEG_STATE_RESTART 3
2412 #define ANEG_STATE_DISABLE_LINK_OK 4
2413 #define ANEG_STATE_ABILITY_DETECT_INIT 5
2414 #define ANEG_STATE_ABILITY_DETECT 6
2415 #define ANEG_STATE_ACK_DETECT_INIT 7
2416 #define ANEG_STATE_ACK_DETECT 8
2417 #define ANEG_STATE_COMPLETE_ACK_INIT 9
2418 #define ANEG_STATE_COMPLETE_ACK 10
2419 #define ANEG_STATE_IDLE_DETECT_INIT 11
2420 #define ANEG_STATE_IDLE_DETECT 12
2421 #define ANEG_STATE_LINK_OK 13
2422 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
2423 #define ANEG_STATE_NEXT_PAGE_WAIT 15
2426 #define MR_AN_ENABLE 0x00000001
2427 #define MR_RESTART_AN 0x00000002
2428 #define MR_AN_COMPLETE 0x00000004
2429 #define MR_PAGE_RX 0x00000008
2430 #define MR_NP_LOADED 0x00000010
2431 #define MR_TOGGLE_TX 0x00000020
2432 #define MR_LP_ADV_FULL_DUPLEX 0x00000040
2433 #define MR_LP_ADV_HALF_DUPLEX 0x00000080
2434 #define MR_LP_ADV_SYM_PAUSE 0x00000100
2435 #define MR_LP_ADV_ASYM_PAUSE 0x00000200
2436 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
2437 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
2438 #define MR_LP_ADV_NEXT_PAGE 0x00001000
2439 #define MR_TOGGLE_RX 0x00002000
2440 #define MR_NP_RX 0x00004000
2442 #define MR_LINK_OK 0x80000000
2444 unsigned long link_time, cur_time;
2446 u32 ability_match_cfg;
2447 int ability_match_count;
2449 char ability_match, idle_match, ack_match;
2451 u32 txconfig, rxconfig;
2452 #define ANEG_CFG_NP 0x00000080
2453 #define ANEG_CFG_ACK 0x00000040
2454 #define ANEG_CFG_RF2 0x00000020
2455 #define ANEG_CFG_RF1 0x00000010
2456 #define ANEG_CFG_PS2 0x00000001
2457 #define ANEG_CFG_PS1 0x00008000
2458 #define ANEG_CFG_HD 0x00004000
2459 #define ANEG_CFG_FD 0x00002000
2460 #define ANEG_CFG_INVAL 0x00001f06
2465 #define ANEG_TIMER_ENAB 2
2466 #define ANEG_FAILED -1
2468 #define ANEG_STATE_SETTLE_TIME 10000
2470 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
2471 struct tg3_fiber_aneginfo *ap)
2474 unsigned long delta;
2478 if (ap->state == ANEG_STATE_UNKNOWN) {
2482 ap->ability_match_cfg = 0;
2483 ap->ability_match_count = 0;
2484 ap->ability_match = 0;
2490 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
2491 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
2493 if (rx_cfg_reg != ap->ability_match_cfg) {
2494 ap->ability_match_cfg = rx_cfg_reg;
2495 ap->ability_match = 0;
2496 ap->ability_match_count = 0;
2498 if (++ap->ability_match_count > 1) {
2499 ap->ability_match = 1;
2500 ap->ability_match_cfg = rx_cfg_reg;
2503 if (rx_cfg_reg & ANEG_CFG_ACK)
2511 ap->ability_match_cfg = 0;
2512 ap->ability_match_count = 0;
2513 ap->ability_match = 0;
2519 ap->rxconfig = rx_cfg_reg;
2523 case ANEG_STATE_UNKNOWN:
2524 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
2525 ap->state = ANEG_STATE_AN_ENABLE;
2528 case ANEG_STATE_AN_ENABLE:
2529 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
2530 if (ap->flags & MR_AN_ENABLE) {
2533 ap->ability_match_cfg = 0;
2534 ap->ability_match_count = 0;
2535 ap->ability_match = 0;
2539 ap->state = ANEG_STATE_RESTART_INIT;
2541 ap->state = ANEG_STATE_DISABLE_LINK_OK;
2545 case ANEG_STATE_RESTART_INIT:
2546 ap->link_time = ap->cur_time;
2547 ap->flags &= ~(MR_NP_LOADED);
2549 tw32(MAC_TX_AUTO_NEG, 0);
2550 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2551 tw32_f(MAC_MODE, tp->mac_mode);
2554 ret = ANEG_TIMER_ENAB;
2555 ap->state = ANEG_STATE_RESTART;
2558 case ANEG_STATE_RESTART:
2559 delta = ap->cur_time - ap->link_time;
2560 if (delta > ANEG_STATE_SETTLE_TIME) {
2561 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
2563 ret = ANEG_TIMER_ENAB;
2567 case ANEG_STATE_DISABLE_LINK_OK:
2571 case ANEG_STATE_ABILITY_DETECT_INIT:
2572 ap->flags &= ~(MR_TOGGLE_TX);
2573 ap->txconfig = ANEG_CFG_FD;
2574 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
2575 if (flowctrl & ADVERTISE_1000XPAUSE)
2576 ap->txconfig |= ANEG_CFG_PS1;
2577 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
2578 ap->txconfig |= ANEG_CFG_PS2;
2579 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2580 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2581 tw32_f(MAC_MODE, tp->mac_mode);
2584 ap->state = ANEG_STATE_ABILITY_DETECT;
2587 case ANEG_STATE_ABILITY_DETECT:
2588 if (ap->ability_match != 0 && ap->rxconfig != 0) {
2589 ap->state = ANEG_STATE_ACK_DETECT_INIT;
2593 case ANEG_STATE_ACK_DETECT_INIT:
2594 ap->txconfig |= ANEG_CFG_ACK;
2595 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2596 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2597 tw32_f(MAC_MODE, tp->mac_mode);
2600 ap->state = ANEG_STATE_ACK_DETECT;
2603 case ANEG_STATE_ACK_DETECT:
2604 if (ap->ack_match != 0) {
2605 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
2606 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
2607 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
2609 ap->state = ANEG_STATE_AN_ENABLE;
2611 } else if (ap->ability_match != 0 &&
2612 ap->rxconfig == 0) {
2613 ap->state = ANEG_STATE_AN_ENABLE;
2617 case ANEG_STATE_COMPLETE_ACK_INIT:
2618 if (ap->rxconfig & ANEG_CFG_INVAL) {
2622 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
2623 MR_LP_ADV_HALF_DUPLEX |
2624 MR_LP_ADV_SYM_PAUSE |
2625 MR_LP_ADV_ASYM_PAUSE |
2626 MR_LP_ADV_REMOTE_FAULT1 |
2627 MR_LP_ADV_REMOTE_FAULT2 |
2628 MR_LP_ADV_NEXT_PAGE |
2631 if (ap->rxconfig & ANEG_CFG_FD)
2632 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
2633 if (ap->rxconfig & ANEG_CFG_HD)
2634 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
2635 if (ap->rxconfig & ANEG_CFG_PS1)
2636 ap->flags |= MR_LP_ADV_SYM_PAUSE;
2637 if (ap->rxconfig & ANEG_CFG_PS2)
2638 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
2639 if (ap->rxconfig & ANEG_CFG_RF1)
2640 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
2641 if (ap->rxconfig & ANEG_CFG_RF2)
2642 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
2643 if (ap->rxconfig & ANEG_CFG_NP)
2644 ap->flags |= MR_LP_ADV_NEXT_PAGE;
2646 ap->link_time = ap->cur_time;
2648 ap->flags ^= (MR_TOGGLE_TX);
2649 if (ap->rxconfig & 0x0008)
2650 ap->flags |= MR_TOGGLE_RX;
2651 if (ap->rxconfig & ANEG_CFG_NP)
2652 ap->flags |= MR_NP_RX;
2653 ap->flags |= MR_PAGE_RX;
2655 ap->state = ANEG_STATE_COMPLETE_ACK;
2656 ret = ANEG_TIMER_ENAB;
2659 case ANEG_STATE_COMPLETE_ACK:
2660 if (ap->ability_match != 0 &&
2661 ap->rxconfig == 0) {
2662 ap->state = ANEG_STATE_AN_ENABLE;
2665 delta = ap->cur_time - ap->link_time;
2666 if (delta > ANEG_STATE_SETTLE_TIME) {
2667 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
2668 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2670 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
2671 !(ap->flags & MR_NP_RX)) {
2672 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2680 case ANEG_STATE_IDLE_DETECT_INIT:
2681 ap->link_time = ap->cur_time;
2682 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2683 tw32_f(MAC_MODE, tp->mac_mode);
2686 ap->state = ANEG_STATE_IDLE_DETECT;
2687 ret = ANEG_TIMER_ENAB;
2690 case ANEG_STATE_IDLE_DETECT:
2691 if (ap->ability_match != 0 &&
2692 ap->rxconfig == 0) {
2693 ap->state = ANEG_STATE_AN_ENABLE;
2696 delta = ap->cur_time - ap->link_time;
2697 if (delta > ANEG_STATE_SETTLE_TIME) {
2698 /* XXX another gem from the Broadcom driver :( */
2699 ap->state = ANEG_STATE_LINK_OK;
2703 case ANEG_STATE_LINK_OK:
2704 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
2708 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
2709 /* ??? unimplemented */
2712 case ANEG_STATE_NEXT_PAGE_WAIT:
2713 /* ??? unimplemented */
2724 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
2727 struct tg3_fiber_aneginfo aninfo;
2728 int status = ANEG_FAILED;
2732 tw32_f(MAC_TX_AUTO_NEG, 0);
2734 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
2735 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
2738 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
2741 memset(&aninfo, 0, sizeof(aninfo));
2742 aninfo.flags |= MR_AN_ENABLE;
2743 aninfo.state = ANEG_STATE_UNKNOWN;
2744 aninfo.cur_time = 0;
2746 while (++tick < 195000) {
2747 status = tg3_fiber_aneg_smachine(tp, &aninfo);
2748 if (status == ANEG_DONE || status == ANEG_FAILED)
2754 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2755 tw32_f(MAC_MODE, tp->mac_mode);
2758 *txflags = aninfo.txconfig;
2759 *rxflags = aninfo.flags;
2761 if (status == ANEG_DONE &&
2762 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
2763 MR_LP_ADV_FULL_DUPLEX)))
2769 static void tg3_init_bcm8002(struct tg3 *tp)
2771 u32 mac_status = tr32(MAC_STATUS);
2774 /* Reset when initting first time or we have a link. */
2775 if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
2776 !(mac_status & MAC_STATUS_PCS_SYNCED))
2779 /* Set PLL lock range. */
2780 tg3_writephy(tp, 0x16, 0x8007);
2783 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
2785 /* Wait for reset to complete. */
2786 /* XXX schedule_timeout() ... */
2787 for (i = 0; i < 500; i++)
2790 /* Config mode; select PMA/Ch 1 regs. */
2791 tg3_writephy(tp, 0x10, 0x8411);
2793 /* Enable auto-lock and comdet, select txclk for tx. */
2794 tg3_writephy(tp, 0x11, 0x0a10);
2796 tg3_writephy(tp, 0x18, 0x00a0);
2797 tg3_writephy(tp, 0x16, 0x41ff);
2799 /* Assert and deassert POR. */
2800 tg3_writephy(tp, 0x13, 0x0400);
2802 tg3_writephy(tp, 0x13, 0x0000);
2804 tg3_writephy(tp, 0x11, 0x0a50);
2806 tg3_writephy(tp, 0x11, 0x0a10);
2808 /* Wait for signal to stabilize */
2809 /* XXX schedule_timeout() ... */
2810 for (i = 0; i < 15000; i++)
2813 /* Deselect the channel register so we can read the PHYID
2816 tg3_writephy(tp, 0x10, 0x8011);
2819 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
2822 u32 sg_dig_ctrl, sg_dig_status;
2823 u32 serdes_cfg, expected_sg_dig_ctrl;
2824 int workaround, port_a;
2825 int current_link_up;
2828 expected_sg_dig_ctrl = 0;
2831 current_link_up = 0;
2833 if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
2834 tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
2836 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
2839 /* preserve bits 0-11,13,14 for signal pre-emphasis */
2840 /* preserve bits 20-23 for voltage regulator */
2841 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
2844 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2846 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
2847 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
2849 u32 val = serdes_cfg;
2855 tw32_f(MAC_SERDES_CFG, val);
2858 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
2860 if (mac_status & MAC_STATUS_PCS_SYNCED) {
2861 tg3_setup_flow_control(tp, 0, 0);
2862 current_link_up = 1;
2867 /* Want auto-negotiation. */
2868 expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
2870 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
2871 if (flowctrl & ADVERTISE_1000XPAUSE)
2872 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
2873 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
2874 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
2876 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
2877 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
2878 tp->serdes_counter &&
2879 ((mac_status & (MAC_STATUS_PCS_SYNCED |
2880 MAC_STATUS_RCVD_CFG)) ==
2881 MAC_STATUS_PCS_SYNCED)) {
2882 tp->serdes_counter--;
2883 current_link_up = 1;
2888 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
2889 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
2891 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
2893 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
2894 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2895 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
2896 MAC_STATUS_SIGNAL_DET)) {
2897 sg_dig_status = tr32(SG_DIG_STATUS);
2898 mac_status = tr32(MAC_STATUS);
2900 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
2901 (mac_status & MAC_STATUS_PCS_SYNCED)) {
2902 u32 local_adv = 0, remote_adv = 0;
2904 if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
2905 local_adv |= ADVERTISE_1000XPAUSE;
2906 if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
2907 local_adv |= ADVERTISE_1000XPSE_ASYM;
2909 if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
2910 remote_adv |= LPA_1000XPAUSE;
2911 if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
2912 remote_adv |= LPA_1000XPAUSE_ASYM;
2914 tg3_setup_flow_control(tp, local_adv, remote_adv);
2915 current_link_up = 1;
2916 tp->serdes_counter = 0;
2917 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2918 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
2919 if (tp->serdes_counter)
2920 tp->serdes_counter--;
2923 u32 val = serdes_cfg;
2930 tw32_f(MAC_SERDES_CFG, val);
2933 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
2936 /* Link parallel detection - link is up */
2937 /* only if we have PCS_SYNC and not */
2938 /* receiving config code words */
2939 mac_status = tr32(MAC_STATUS);
2940 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
2941 !(mac_status & MAC_STATUS_RCVD_CFG)) {
2942 tg3_setup_flow_control(tp, 0, 0);
2943 current_link_up = 1;
2945 TG3_FLG2_PARALLEL_DETECT;
2946 tp->serdes_counter =
2947 SERDES_PARALLEL_DET_TIMEOUT;
2949 goto restart_autoneg;
2953 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
2954 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2958 return current_link_up;
2961 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
2963 int current_link_up = 0;
2965 if (!(mac_status & MAC_STATUS_PCS_SYNCED))
2968 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2969 u32 txflags, rxflags;
2972 if (fiber_autoneg(tp, &txflags, &rxflags)) {
2973 u32 local_adv = 0, remote_adv = 0;
2975 if (txflags & ANEG_CFG_PS1)
2976 local_adv |= ADVERTISE_1000XPAUSE;
2977 if (txflags & ANEG_CFG_PS2)
2978 local_adv |= ADVERTISE_1000XPSE_ASYM;
2980 if (rxflags & MR_LP_ADV_SYM_PAUSE)
2981 remote_adv |= LPA_1000XPAUSE;
2982 if (rxflags & MR_LP_ADV_ASYM_PAUSE)
2983 remote_adv |= LPA_1000XPAUSE_ASYM;
2985 tg3_setup_flow_control(tp, local_adv, remote_adv);
2987 current_link_up = 1;
2989 for (i = 0; i < 30; i++) {
2992 (MAC_STATUS_SYNC_CHANGED |
2993 MAC_STATUS_CFG_CHANGED));
2995 if ((tr32(MAC_STATUS) &
2996 (MAC_STATUS_SYNC_CHANGED |
2997 MAC_STATUS_CFG_CHANGED)) == 0)
3001 mac_status = tr32(MAC_STATUS);
3002 if (current_link_up == 0 &&
3003 (mac_status & MAC_STATUS_PCS_SYNCED) &&
3004 !(mac_status & MAC_STATUS_RCVD_CFG))
3005 current_link_up = 1;
3007 tg3_setup_flow_control(tp, 0, 0);
3009 /* Forcing 1000FD link up. */
3010 current_link_up = 1;
3012 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3015 tw32_f(MAC_MODE, tp->mac_mode);
3020 return current_link_up;
3023 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3026 u16 orig_active_speed;
3027 u8 orig_active_duplex;
3029 int current_link_up;
3032 orig_pause_cfg = tp->link_config.active_flowctrl;
3033 orig_active_speed = tp->link_config.active_speed;
3034 orig_active_duplex = tp->link_config.active_duplex;
3036 if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3037 netif_carrier_ok(tp->dev) &&
3038 (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3039 mac_status = tr32(MAC_STATUS);
3040 mac_status &= (MAC_STATUS_PCS_SYNCED |
3041 MAC_STATUS_SIGNAL_DET |
3042 MAC_STATUS_CFG_CHANGED |
3043 MAC_STATUS_RCVD_CFG);
3044 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3045 MAC_STATUS_SIGNAL_DET)) {
3046 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3047 MAC_STATUS_CFG_CHANGED));
3052 tw32_f(MAC_TX_AUTO_NEG, 0);
3054 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
3055 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
3056 tw32_f(MAC_MODE, tp->mac_mode);
3059 if (tp->phy_id == PHY_ID_BCM8002)
3060 tg3_init_bcm8002(tp);
3062 /* Enable link change event even when serdes polling. */
3063 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3066 current_link_up = 0;
3067 mac_status = tr32(MAC_STATUS);
3069 if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
3070 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
3072 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
3074 tp->hw_status->status =
3075 (SD_STATUS_UPDATED |
3076 (tp->hw_status->status & ~SD_STATUS_LINK_CHG));
3078 for (i = 0; i < 100; i++) {
3079 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3080 MAC_STATUS_CFG_CHANGED));
3082 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3083 MAC_STATUS_CFG_CHANGED |
3084 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
3088 mac_status = tr32(MAC_STATUS);
3089 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
3090 current_link_up = 0;
3091 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
3092 tp->serdes_counter == 0) {
3093 tw32_f(MAC_MODE, (tp->mac_mode |
3094 MAC_MODE_SEND_CONFIGS));
3096 tw32_f(MAC_MODE, tp->mac_mode);
3100 if (current_link_up == 1) {
3101 tp->link_config.active_speed = SPEED_1000;
3102 tp->link_config.active_duplex = DUPLEX_FULL;
3103 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3104 LED_CTRL_LNKLED_OVERRIDE |
3105 LED_CTRL_1000MBPS_ON));
3107 tp->link_config.active_speed = SPEED_INVALID;
3108 tp->link_config.active_duplex = DUPLEX_INVALID;
3109 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3110 LED_CTRL_LNKLED_OVERRIDE |
3111 LED_CTRL_TRAFFIC_OVERRIDE));
3114 if (current_link_up != netif_carrier_ok(tp->dev)) {
3115 if (current_link_up)
3116 netif_carrier_on(tp->dev);
3118 netif_carrier_off(tp->dev);
3119 tg3_link_report(tp);
3121 u32 now_pause_cfg = tp->link_config.active_flowctrl;
3122 if (orig_pause_cfg != now_pause_cfg ||
3123 orig_active_speed != tp->link_config.active_speed ||
3124 orig_active_duplex != tp->link_config.active_duplex)
3125 tg3_link_report(tp);
3131 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
3133 int current_link_up, err = 0;
3137 u32 local_adv, remote_adv;
3139 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3140 tw32_f(MAC_MODE, tp->mac_mode);
3146 (MAC_STATUS_SYNC_CHANGED |
3147 MAC_STATUS_CFG_CHANGED |
3148 MAC_STATUS_MI_COMPLETION |
3149 MAC_STATUS_LNKSTATE_CHANGED));
3155 current_link_up = 0;
3156 current_speed = SPEED_INVALID;
3157 current_duplex = DUPLEX_INVALID;
3159 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
3160 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
3161 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
3162 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
3163 bmsr |= BMSR_LSTATUS;
3165 bmsr &= ~BMSR_LSTATUS;
3168 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
3170 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
3171 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
3172 /* do nothing, just check for link up at the end */
3173 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3176 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
3177 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
3178 ADVERTISE_1000XPAUSE |
3179 ADVERTISE_1000XPSE_ASYM |
3182 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3184 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
3185 new_adv |= ADVERTISE_1000XHALF;
3186 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
3187 new_adv |= ADVERTISE_1000XFULL;
3189 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
3190 tg3_writephy(tp, MII_ADVERTISE, new_adv);
3191 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
3192 tg3_writephy(tp, MII_BMCR, bmcr);
3194 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3195 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
3196 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3203 bmcr &= ~BMCR_SPEED1000;
3204 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
3206 if (tp->link_config.duplex == DUPLEX_FULL)
3207 new_bmcr |= BMCR_FULLDPLX;
3209 if (new_bmcr != bmcr) {
3210 /* BMCR_SPEED1000 is a reserved bit that needs
3211 * to be set on write.
3213 new_bmcr |= BMCR_SPEED1000;
3215 /* Force a linkdown */
3216 if (netif_carrier_ok(tp->dev)) {
3219 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
3220 adv &= ~(ADVERTISE_1000XFULL |
3221 ADVERTISE_1000XHALF |
3223 tg3_writephy(tp, MII_ADVERTISE, adv);
3224 tg3_writephy(tp, MII_BMCR, bmcr |
3228 netif_carrier_off(tp->dev);
3230 tg3_writephy(tp, MII_BMCR, new_bmcr);
3232 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
3233 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
3234 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
3236 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
3237 bmsr |= BMSR_LSTATUS;
3239 bmsr &= ~BMSR_LSTATUS;
3241 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3245 if (bmsr & BMSR_LSTATUS) {
3246 current_speed = SPEED_1000;
3247 current_link_up = 1;
3248 if (bmcr & BMCR_FULLDPLX)
3249 current_duplex = DUPLEX_FULL;
3251 current_duplex = DUPLEX_HALF;
3256 if (bmcr & BMCR_ANENABLE) {
3259 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
3260 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
3261 common = local_adv & remote_adv;
3262 if (common & (ADVERTISE_1000XHALF |
3263 ADVERTISE_1000XFULL)) {
3264 if (common & ADVERTISE_1000XFULL)
3265 current_duplex = DUPLEX_FULL;
3267 current_duplex = DUPLEX_HALF;
3270 current_link_up = 0;
3274 if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
3275 tg3_setup_flow_control(tp, local_adv, remote_adv);
3277 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3278 if (tp->link_config.active_duplex == DUPLEX_HALF)
3279 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3281 tw32_f(MAC_MODE, tp->mac_mode);
3284 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3286 tp->link_config.active_speed = current_speed;
3287 tp->link_config.active_duplex = current_duplex;
3289 if (current_link_up != netif_carrier_ok(tp->dev)) {
3290 if (current_link_up)
3291 netif_carrier_on(tp->dev);
3293 netif_carrier_off(tp->dev);
3294 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3296 tg3_link_report(tp);
3301 static void tg3_serdes_parallel_detect(struct tg3 *tp)
3303 if (tp->serdes_counter) {
3304 /* Give autoneg time to complete. */
3305 tp->serdes_counter--;
3308 if (!netif_carrier_ok(tp->dev) &&
3309 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
3312 tg3_readphy(tp, MII_BMCR, &bmcr);
3313 if (bmcr & BMCR_ANENABLE) {
3316 /* Select shadow register 0x1f */
3317 tg3_writephy(tp, 0x1c, 0x7c00);
3318 tg3_readphy(tp, 0x1c, &phy1);
3320 /* Select expansion interrupt status register */
3321 tg3_writephy(tp, 0x17, 0x0f01);
3322 tg3_readphy(tp, 0x15, &phy2);
3323 tg3_readphy(tp, 0x15, &phy2);
3325 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
3326 /* We have signal detect and not receiving
3327 * config code words, link is up by parallel
3331 bmcr &= ~BMCR_ANENABLE;
3332 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
3333 tg3_writephy(tp, MII_BMCR, bmcr);
3334 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
3338 else if (netif_carrier_ok(tp->dev) &&
3339 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
3340 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
3343 /* Select expansion interrupt status register */
3344 tg3_writephy(tp, 0x17, 0x0f01);
3345 tg3_readphy(tp, 0x15, &phy2);
3349 /* Config code words received, turn on autoneg. */
3350 tg3_readphy(tp, MII_BMCR, &bmcr);
3351 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
3353 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3359 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
3363 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
3364 err = tg3_setup_fiber_phy(tp, force_reset);
3365 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
3366 err = tg3_setup_fiber_mii_phy(tp, force_reset);
3368 err = tg3_setup_copper_phy(tp, force_reset);
3371 if (tp->pci_chip_rev_id == CHIPREV_ID_5784_A0 ||
3372 tp->pci_chip_rev_id == CHIPREV_ID_5784_A1) {
3375 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
3376 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
3378 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
3383 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
3384 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
3385 tw32(GRC_MISC_CFG, val);
3388 if (tp->link_config.active_speed == SPEED_1000 &&
3389 tp->link_config.active_duplex == DUPLEX_HALF)
3390 tw32(MAC_TX_LENGTHS,
3391 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
3392 (6 << TX_LENGTHS_IPG_SHIFT) |
3393 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
3395 tw32(MAC_TX_LENGTHS,
3396 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
3397 (6 << TX_LENGTHS_IPG_SHIFT) |
3398 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
3400 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
3401 if (netif_carrier_ok(tp->dev)) {
3402 tw32(HOSTCC_STAT_COAL_TICKS,
3403 tp->coal.stats_block_coalesce_usecs);
3405 tw32(HOSTCC_STAT_COAL_TICKS, 0);
3409 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
3410 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
3411 if (!netif_carrier_ok(tp->dev))
3412 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
3415 val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
3416 tw32(PCIE_PWR_MGMT_THRESH, val);
3422 /* This is called whenever we suspect that the system chipset is re-
3423 * ordering the sequence of MMIO to the tx send mailbox. The symptom
3424 * is bogus tx completions. We try to recover by setting the
3425 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
3428 static void tg3_tx_recover(struct tg3 *tp)
3430 BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
3431 tp->write32_tx_mbox == tg3_write_indirect_mbox);
3433 printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
3434 "mapped I/O cycles to the network device, attempting to "
3435 "recover. Please report the problem to the driver maintainer "
3436 "and include system chipset information.\n", tp->dev->name);
3438 spin_lock(&tp->lock);
3439 tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
3440 spin_unlock(&tp->lock);
3443 static inline u32 tg3_tx_avail(struct tg3 *tp)
3446 return (tp->tx_pending -
3447 ((tp->tx_prod - tp->tx_cons) & (TG3_TX_RING_SIZE - 1)));
3450 /* Tigon3 never reports partial packet sends. So we do not
3451 * need special logic to handle SKBs that have not had all
3452 * of their frags sent yet, like SunGEM does.
3454 static void tg3_tx(struct tg3 *tp)
3456 u32 hw_idx = tp->hw_status->idx[0].tx_consumer;
3457 u32 sw_idx = tp->tx_cons;
3459 while (sw_idx != hw_idx) {
3460 struct tx_ring_info *ri = &tp->tx_buffers[sw_idx];
3461 struct sk_buff *skb = ri->skb;
3464 if (unlikely(skb == NULL)) {
3469 pci_unmap_single(tp->pdev,
3470 pci_unmap_addr(ri, mapping),
3476 sw_idx = NEXT_TX(sw_idx);
3478 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
3479 ri = &tp->tx_buffers[sw_idx];
3480 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
3483 pci_unmap_page(tp->pdev,
3484 pci_unmap_addr(ri, mapping),
3485 skb_shinfo(skb)->frags[i].size,
3488 sw_idx = NEXT_TX(sw_idx);
3493 if (unlikely(tx_bug)) {
3499 tp->tx_cons = sw_idx;
3501 /* Need to make the tx_cons update visible to tg3_start_xmit()
3502 * before checking for netif_queue_stopped(). Without the
3503 * memory barrier, there is a small possibility that tg3_start_xmit()
3504 * will miss it and cause the queue to be stopped forever.
3508 if (unlikely(netif_queue_stopped(tp->dev) &&
3509 (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))) {
3510 netif_tx_lock(tp->dev);
3511 if (netif_queue_stopped(tp->dev) &&
3512 (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))
3513 netif_wake_queue(tp->dev);
3514 netif_tx_unlock(tp->dev);
3518 /* Returns size of skb allocated or < 0 on error.
3520 * We only need to fill in the address because the other members
3521 * of the RX descriptor are invariant, see tg3_init_rings.
3523 * Note the purposeful assymetry of cpu vs. chip accesses. For
3524 * posting buffers we only dirty the first cache line of the RX
3525 * descriptor (containing the address). Whereas for the RX status
3526 * buffers the cpu only reads the last cacheline of the RX descriptor
3527 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
3529 static int tg3_alloc_rx_skb(struct tg3 *tp, u32 opaque_key,
3530 int src_idx, u32 dest_idx_unmasked)
3532 struct tg3_rx_buffer_desc *desc;
3533 struct ring_info *map, *src_map;
3534 struct sk_buff *skb;
3536 int skb_size, dest_idx;
3539 switch (opaque_key) {
3540 case RXD_OPAQUE_RING_STD:
3541 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
3542 desc = &tp->rx_std[dest_idx];
3543 map = &tp->rx_std_buffers[dest_idx];
3545 src_map = &tp->rx_std_buffers[src_idx];
3546 skb_size = tp->rx_pkt_buf_sz;
3549 case RXD_OPAQUE_RING_JUMBO:
3550 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
3551 desc = &tp->rx_jumbo[dest_idx];
3552 map = &tp->rx_jumbo_buffers[dest_idx];
3554 src_map = &tp->rx_jumbo_buffers[src_idx];
3555 skb_size = RX_JUMBO_PKT_BUF_SZ;
3562 /* Do not overwrite any of the map or rp information
3563 * until we are sure we can commit to a new buffer.
3565 * Callers depend upon this behavior and assume that
3566 * we leave everything unchanged if we fail.
3568 skb = netdev_alloc_skb(tp->dev, skb_size);
3572 skb_reserve(skb, tp->rx_offset);
3574 mapping = pci_map_single(tp->pdev, skb->data,
3575 skb_size - tp->rx_offset,
3576 PCI_DMA_FROMDEVICE);
3579 pci_unmap_addr_set(map, mapping, mapping);
3581 if (src_map != NULL)
3582 src_map->skb = NULL;
3584 desc->addr_hi = ((u64)mapping >> 32);
3585 desc->addr_lo = ((u64)mapping & 0xffffffff);
3590 /* We only need to move over in the address because the other
3591 * members of the RX descriptor are invariant. See notes above
3592 * tg3_alloc_rx_skb for full details.
3594 static void tg3_recycle_rx(struct tg3 *tp, u32 opaque_key,
3595 int src_idx, u32 dest_idx_unmasked)
3597 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
3598 struct ring_info *src_map, *dest_map;
3601 switch (opaque_key) {
3602 case RXD_OPAQUE_RING_STD:
3603 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
3604 dest_desc = &tp->rx_std[dest_idx];
3605 dest_map = &tp->rx_std_buffers[dest_idx];
3606 src_desc = &tp->rx_std[src_idx];
3607 src_map = &tp->rx_std_buffers[src_idx];
3610 case RXD_OPAQUE_RING_JUMBO:
3611 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
3612 dest_desc = &tp->rx_jumbo[dest_idx];
3613 dest_map = &tp->rx_jumbo_buffers[dest_idx];
3614 src_desc = &tp->rx_jumbo[src_idx];
3615 src_map = &tp->rx_jumbo_buffers[src_idx];
3622 dest_map->skb = src_map->skb;
3623 pci_unmap_addr_set(dest_map, mapping,
3624 pci_unmap_addr(src_map, mapping));
3625 dest_desc->addr_hi = src_desc->addr_hi;
3626 dest_desc->addr_lo = src_desc->addr_lo;
3628 src_map->skb = NULL;
3631 #if TG3_VLAN_TAG_USED
3632 static int tg3_vlan_rx(struct tg3 *tp, struct sk_buff *skb, u16 vlan_tag)
3634 return vlan_hwaccel_receive_skb(skb, tp->vlgrp, vlan_tag);
3638 /* The RX ring scheme is composed of multiple rings which post fresh
3639 * buffers to the chip, and one special ring the chip uses to report
3640 * status back to the host.
3642 * The special ring reports the status of received packets to the
3643 * host. The chip does not write into the original descriptor the
3644 * RX buffer was obtained from. The chip simply takes the original
3645 * descriptor as provided by the host, updates the status and length
3646 * field, then writes this into the next status ring entry.
3648 * Each ring the host uses to post buffers to the chip is described
3649 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
3650 * it is first placed into the on-chip ram. When the packet's length
3651 * is known, it walks down the TG3_BDINFO entries to select the ring.
3652 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
3653 * which is within the range of the new packet's length is chosen.
3655 * The "separate ring for rx status" scheme may sound queer, but it makes
3656 * sense from a cache coherency perspective. If only the host writes
3657 * to the buffer post rings, and only the chip writes to the rx status
3658 * rings, then cache lines never move beyond shared-modified state.
3659 * If both the host and chip were to write into the same ring, cache line
3660 * eviction could occur since both entities want it in an exclusive state.
3662 static int tg3_rx(struct tg3 *tp, int budget)
3664 u32 work_mask, rx_std_posted = 0;
3665 u32 sw_idx = tp->rx_rcb_ptr;
3669 hw_idx = tp->hw_status->idx[0].rx_producer;
3671 * We need to order the read of hw_idx and the read of
3672 * the opaque cookie.
3677 while (sw_idx != hw_idx && budget > 0) {
3678 struct tg3_rx_buffer_desc *desc = &tp->rx_rcb[sw_idx];
3680 struct sk_buff *skb;
3681 dma_addr_t dma_addr;
3682 u32 opaque_key, desc_idx, *post_ptr;
3684 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
3685 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
3686 if (opaque_key == RXD_OPAQUE_RING_STD) {
3687 dma_addr = pci_unmap_addr(&tp->rx_std_buffers[desc_idx],
3689 skb = tp->rx_std_buffers[desc_idx].skb;
3690 post_ptr = &tp->rx_std_ptr;
3692 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
3693 dma_addr = pci_unmap_addr(&tp->rx_jumbo_buffers[desc_idx],
3695 skb = tp->rx_jumbo_buffers[desc_idx].skb;
3696 post_ptr = &tp->rx_jumbo_ptr;
3699 goto next_pkt_nopost;
3702 work_mask |= opaque_key;
3704 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
3705 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
3707 tg3_recycle_rx(tp, opaque_key,
3708 desc_idx, *post_ptr);
3710 /* Other statistics kept track of by card. */
3711 tp->net_stats.rx_dropped++;
3715 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4; /* omit crc */
3717 if (len > RX_COPY_THRESHOLD
3718 && tp->rx_offset == 2
3719 /* rx_offset != 2 iff this is a 5701 card running
3720 * in PCI-X mode [see tg3_get_invariants()] */
3724 skb_size = tg3_alloc_rx_skb(tp, opaque_key,
3725 desc_idx, *post_ptr);
3729 pci_unmap_single(tp->pdev, dma_addr,
3730 skb_size - tp->rx_offset,
3731 PCI_DMA_FROMDEVICE);
3735 struct sk_buff *copy_skb;
3737 tg3_recycle_rx(tp, opaque_key,
3738 desc_idx, *post_ptr);
3740 copy_skb = netdev_alloc_skb(tp->dev, len + 2);
3741 if (copy_skb == NULL)
3742 goto drop_it_no_recycle;
3744 skb_reserve(copy_skb, 2);
3745 skb_put(copy_skb, len);
3746 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
3747 skb_copy_from_linear_data(skb, copy_skb->data, len);
3748 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
3750 /* We'll reuse the original ring buffer. */
3754 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
3755 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
3756 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
3757 >> RXD_TCPCSUM_SHIFT) == 0xffff))
3758 skb->ip_summed = CHECKSUM_UNNECESSARY;
3760 skb->ip_summed = CHECKSUM_NONE;
3762 skb->protocol = eth_type_trans(skb, tp->dev);
3763 #if TG3_VLAN_TAG_USED
3764 if (tp->vlgrp != NULL &&
3765 desc->type_flags & RXD_FLAG_VLAN) {
3766 tg3_vlan_rx(tp, skb,
3767 desc->err_vlan & RXD_VLAN_MASK);
3770 netif_receive_skb(skb);
3772 tp->dev->last_rx = jiffies;
3779 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
3780 u32 idx = *post_ptr % TG3_RX_RING_SIZE;
3782 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX +
3783 TG3_64BIT_REG_LOW, idx);
3784 work_mask &= ~RXD_OPAQUE_RING_STD;
3789 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
3791 /* Refresh hw_idx to see if there is new work */
3792 if (sw_idx == hw_idx) {
3793 hw_idx = tp->hw_status->idx[0].rx_producer;
3798 /* ACK the status ring. */
3799 tp->rx_rcb_ptr = sw_idx;
3800 tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, sw_idx);
3802 /* Refill RX ring(s). */
3803 if (work_mask & RXD_OPAQUE_RING_STD) {
3804 sw_idx = tp->rx_std_ptr % TG3_RX_RING_SIZE;
3805 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
3808 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
3809 sw_idx = tp->rx_jumbo_ptr % TG3_RX_JUMBO_RING_SIZE;
3810 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
3818 static int tg3_poll_work(struct tg3 *tp, int work_done, int budget)
3820 struct tg3_hw_status *sblk = tp->hw_status;
3822 /* handle link change and other phy events */
3823 if (!(tp->tg3_flags &
3824 (TG3_FLAG_USE_LINKCHG_REG |
3825 TG3_FLAG_POLL_SERDES))) {
3826 if (sblk->status & SD_STATUS_LINK_CHG) {
3827 sblk->status = SD_STATUS_UPDATED |
3828 (sblk->status & ~SD_STATUS_LINK_CHG);
3829 spin_lock(&tp->lock);
3830 tg3_setup_phy(tp, 0);
3831 spin_unlock(&tp->lock);
3835 /* run TX completion thread */
3836 if (sblk->idx[0].tx_consumer != tp->tx_cons) {
3838 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
3842 /* run RX thread, within the bounds set by NAPI.
3843 * All RX "locking" is done by ensuring outside
3844 * code synchronizes with tg3->napi.poll()
3846 if (sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
3847 work_done += tg3_rx(tp, budget - work_done);
3852 static int tg3_poll(struct napi_struct *napi, int budget)
3854 struct tg3 *tp = container_of(napi, struct tg3, napi);
3856 struct tg3_hw_status *sblk = tp->hw_status;
3859 work_done = tg3_poll_work(tp, work_done, budget);
3861 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
3864 if (unlikely(work_done >= budget))
3867 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
3868 /* tp->last_tag is used in tg3_restart_ints() below
3869 * to tell the hw how much work has been processed,
3870 * so we must read it before checking for more work.
3872 tp->last_tag = sblk->status_tag;
3875 sblk->status &= ~SD_STATUS_UPDATED;
3877 if (likely(!tg3_has_work(tp))) {
3878 netif_rx_complete(tp->dev, napi);
3879 tg3_restart_ints(tp);
3887 /* work_done is guaranteed to be less than budget. */
3888 netif_rx_complete(tp->dev, napi);
3889 schedule_work(&tp->reset_task);
3893 static void tg3_irq_quiesce(struct tg3 *tp)
3895 BUG_ON(tp->irq_sync);
3900 synchronize_irq(tp->pdev->irq);
3903 static inline int tg3_irq_sync(struct tg3 *tp)
3905 return tp->irq_sync;
3908 /* Fully shutdown all tg3 driver activity elsewhere in the system.
3909 * If irq_sync is non-zero, then the IRQ handler must be synchronized
3910 * with as well. Most of the time, this is not necessary except when
3911 * shutting down the device.
3913 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
3915 spin_lock_bh(&tp->lock);
3917 tg3_irq_quiesce(tp);
3920 static inline void tg3_full_unlock(struct tg3 *tp)
3922 spin_unlock_bh(&tp->lock);
3925 /* One-shot MSI handler - Chip automatically disables interrupt
3926 * after sending MSI so driver doesn't have to do it.
3928 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
3930 struct net_device *dev = dev_id;
3931 struct tg3 *tp = netdev_priv(dev);
3933 prefetch(tp->hw_status);
3934 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3936 if (likely(!tg3_irq_sync(tp)))
3937 netif_rx_schedule(dev, &tp->napi);
3942 /* MSI ISR - No need to check for interrupt sharing and no need to
3943 * flush status block and interrupt mailbox. PCI ordering rules
3944 * guarantee that MSI will arrive after the status block.
3946 static irqreturn_t tg3_msi(int irq, void *dev_id)
3948 struct net_device *dev = dev_id;
3949 struct tg3 *tp = netdev_priv(dev);
3951 prefetch(tp->hw_status);
3952 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3954 * Writing any value to intr-mbox-0 clears PCI INTA# and
3955 * chip-internal interrupt pending events.
3956 * Writing non-zero to intr-mbox-0 additional tells the
3957 * NIC to stop sending us irqs, engaging "in-intr-handler"
3960 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
3961 if (likely(!tg3_irq_sync(tp)))
3962 netif_rx_schedule(dev, &tp->napi);
3964 return IRQ_RETVAL(1);
3967 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
3969 struct net_device *dev = dev_id;
3970 struct tg3 *tp = netdev_priv(dev);
3971 struct tg3_hw_status *sblk = tp->hw_status;
3972 unsigned int handled = 1;
3974 /* In INTx mode, it is possible for the interrupt to arrive at
3975 * the CPU before the status block posted prior to the interrupt.
3976 * Reading the PCI State register will confirm whether the
3977 * interrupt is ours and will flush the status block.
3979 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
3980 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
3981 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3988 * Writing any value to intr-mbox-0 clears PCI INTA# and
3989 * chip-internal interrupt pending events.
3990 * Writing non-zero to intr-mbox-0 additional tells the
3991 * NIC to stop sending us irqs, engaging "in-intr-handler"
3994 * Flush the mailbox to de-assert the IRQ immediately to prevent
3995 * spurious interrupts. The flush impacts performance but
3996 * excessive spurious interrupts can be worse in some cases.
3998 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
3999 if (tg3_irq_sync(tp))
4001 sblk->status &= ~SD_STATUS_UPDATED;
4002 if (likely(tg3_has_work(tp))) {
4003 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4004 netif_rx_schedule(dev, &tp->napi);
4006 /* No work, shared interrupt perhaps? re-enable
4007 * interrupts, and flush that PCI write
4009 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
4013 return IRQ_RETVAL(handled);
4016 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
4018 struct net_device *dev = dev_id;
4019 struct tg3 *tp = netdev_priv(dev);
4020 struct tg3_hw_status *sblk = tp->hw_status;
4021 unsigned int handled = 1;
4023 /* In INTx mode, it is possible for the interrupt to arrive at
4024 * the CPU before the status block posted prior to the interrupt.
4025 * Reading the PCI State register will confirm whether the
4026 * interrupt is ours and will flush the status block.
4028 if (unlikely(sblk->status_tag == tp->last_tag)) {
4029 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4030 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4037 * writing any value to intr-mbox-0 clears PCI INTA# and
4038 * chip-internal interrupt pending events.
4039 * writing non-zero to intr-mbox-0 additional tells the
4040 * NIC to stop sending us irqs, engaging "in-intr-handler"
4043 * Flush the mailbox to de-assert the IRQ immediately to prevent
4044 * spurious interrupts. The flush impacts performance but
4045 * excessive spurious interrupts can be worse in some cases.
4047 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4048 if (tg3_irq_sync(tp))
4050 if (netif_rx_schedule_prep(dev, &tp->napi)) {
4051 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4052 /* Update last_tag to mark that this status has been
4053 * seen. Because interrupt may be shared, we may be
4054 * racing with tg3_poll(), so only update last_tag
4055 * if tg3_poll() is not scheduled.
4057 tp->last_tag = sblk->status_tag;
4058 __netif_rx_schedule(dev, &tp->napi);
4061 return IRQ_RETVAL(handled);
4064 /* ISR for interrupt test */
4065 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
4067 struct net_device *dev = dev_id;
4068 struct tg3 *tp = netdev_priv(dev);
4069 struct tg3_hw_status *sblk = tp->hw_status;
4071 if ((sblk->status & SD_STATUS_UPDATED) ||
4072 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4073 tg3_disable_ints(tp);
4074 return IRQ_RETVAL(1);
4076 return IRQ_RETVAL(0);
4079 static int tg3_init_hw(struct tg3 *, int);
4080 static int tg3_halt(struct tg3 *, int, int);
4082 /* Restart hardware after configuration changes, self-test, etc.
4083 * Invoked with tp->lock held.
4085 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
4086 __releases(tp->lock)
4087 __acquires(tp->lock)
4091 err = tg3_init_hw(tp, reset_phy);
4093 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
4094 "aborting.\n", tp->dev->name);
4095 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
4096 tg3_full_unlock(tp);
4097 del_timer_sync(&tp->timer);
4099 napi_enable(&tp->napi);
4101 tg3_full_lock(tp, 0);
4106 #ifdef CONFIG_NET_POLL_CONTROLLER
4107 static void tg3_poll_controller(struct net_device *dev)
4109 struct tg3 *tp = netdev_priv(dev);
4111 tg3_interrupt(tp->pdev->irq, dev);
4115 static void tg3_reset_task(struct work_struct *work)
4117 struct tg3 *tp = container_of(work, struct tg3, reset_task);
4118 unsigned int restart_timer;
4120 tg3_full_lock(tp, 0);
4122 if (!netif_running(tp->dev)) {
4123 tg3_full_unlock(tp);
4127 tg3_full_unlock(tp);
4131 tg3_full_lock(tp, 1);
4133 restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
4134 tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
4136 if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
4137 tp->write32_tx_mbox = tg3_write32_tx_mbox;
4138 tp->write32_rx_mbox = tg3_write_flush_reg32;
4139 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
4140 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
4143 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
4144 if (tg3_init_hw(tp, 1))
4147 tg3_netif_start(tp);
4150 mod_timer(&tp->timer, jiffies + 1);
4153 tg3_full_unlock(tp);
4156 static void tg3_dump_short_state(struct tg3 *tp)
4158 printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
4159 tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
4160 printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
4161 tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
4164 static void tg3_tx_timeout(struct net_device *dev)
4166 struct tg3 *tp = netdev_priv(dev);
4168 if (netif_msg_tx_err(tp)) {
4169 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
4171 tg3_dump_short_state(tp);
4174 schedule_work(&tp->reset_task);
4177 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
4178 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
4180 u32 base = (u32) mapping & 0xffffffff;
4182 return ((base > 0xffffdcc0) &&
4183 (base + len + 8 < base));
4186 /* Test for DMA addresses > 40-bit */
4187 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
4190 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
4191 if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
4192 return (((u64) mapping + len) > DMA_40BIT_MASK);
4199 static void tg3_set_txd(struct tg3 *, int, dma_addr_t, int, u32, u32);
4201 /* Workaround 4GB and 40-bit hardware DMA bugs. */
4202 static int tigon3_dma_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
4203 u32 last_plus_one, u32 *start,
4204 u32 base_flags, u32 mss)
4206 struct sk_buff *new_skb;
4207 dma_addr_t new_addr = 0;
4211 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
4212 new_skb = skb_copy(skb, GFP_ATOMIC);
4214 int more_headroom = 4 - ((unsigned long)skb->data & 3);
4216 new_skb = skb_copy_expand(skb,
4217 skb_headroom(skb) + more_headroom,
4218 skb_tailroom(skb), GFP_ATOMIC);
4224 /* New SKB is guaranteed to be linear. */
4226 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
4228 /* Make sure new skb does not cross any 4G boundaries.
4229 * Drop the packet if it does.
4231 if (tg3_4g_overflow_test(new_addr, new_skb->len)) {
4233 dev_kfree_skb(new_skb);
4236 tg3_set_txd(tp, entry, new_addr, new_skb->len,
4237 base_flags, 1 | (mss << 1));
4238 *start = NEXT_TX(entry);
4242 /* Now clean up the sw ring entries. */
4244 while (entry != last_plus_one) {
4248 len = skb_headlen(skb);
4250 len = skb_shinfo(skb)->frags[i-1].size;
4251 pci_unmap_single(tp->pdev,
4252 pci_unmap_addr(&tp->tx_buffers[entry], mapping),
4253 len, PCI_DMA_TODEVICE);
4255 tp->tx_buffers[entry].skb = new_skb;
4256 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, new_addr);
4258 tp->tx_buffers[entry].skb = NULL;
4260 entry = NEXT_TX(entry);
4269 static void tg3_set_txd(struct tg3 *tp, int entry,
4270 dma_addr_t mapping, int len, u32 flags,
4273 struct tg3_tx_buffer_desc *txd = &tp->tx_ring[entry];
4274 int is_end = (mss_and_is_end & 0x1);
4275 u32 mss = (mss_and_is_end >> 1);
4279 flags |= TXD_FLAG_END;
4280 if (flags & TXD_FLAG_VLAN) {
4281 vlan_tag = flags >> 16;
4284 vlan_tag |= (mss << TXD_MSS_SHIFT);
4286 txd->addr_hi = ((u64) mapping >> 32);
4287 txd->addr_lo = ((u64) mapping & 0xffffffff);
4288 txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
4289 txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
4292 /* hard_start_xmit for devices that don't have any bugs and
4293 * support TG3_FLG2_HW_TSO_2 only.
4295 static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
4297 struct tg3 *tp = netdev_priv(dev);
4299 u32 len, entry, base_flags, mss;
4301 len = skb_headlen(skb);
4303 /* We are running in BH disabled context with netif_tx_lock
4304 * and TX reclaim runs via tp->napi.poll inside of a software
4305 * interrupt. Furthermore, IRQ processing runs lockless so we have
4306 * no IRQ context deadlocks to worry about either. Rejoice!
4308 if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
4309 if (!netif_queue_stopped(dev)) {
4310 netif_stop_queue(dev);
4312 /* This is a hard error, log it. */
4313 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
4314 "queue awake!\n", dev->name);
4316 return NETDEV_TX_BUSY;
4319 entry = tp->tx_prod;
4322 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
4323 int tcp_opt_len, ip_tcp_len;
4325 if (skb_header_cloned(skb) &&
4326 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
4331 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
4332 mss |= (skb_headlen(skb) - ETH_HLEN) << 9;
4334 struct iphdr *iph = ip_hdr(skb);
4336 tcp_opt_len = tcp_optlen(skb);
4337 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
4340 iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
4341 mss |= (ip_tcp_len + tcp_opt_len) << 9;
4344 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
4345 TXD_FLAG_CPU_POST_DMA);
4347 tcp_hdr(skb)->check = 0;
4350 else if (skb->ip_summed == CHECKSUM_PARTIAL)
4351 base_flags |= TXD_FLAG_TCPUDP_CSUM;
4352 #if TG3_VLAN_TAG_USED
4353 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
4354 base_flags |= (TXD_FLAG_VLAN |
4355 (vlan_tx_tag_get(skb) << 16));
4358 /* Queue skb data, a.k.a. the main skb fragment. */
4359 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
4361 tp->tx_buffers[entry].skb = skb;
4362 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4364 tg3_set_txd(tp, entry, mapping, len, base_flags,
4365 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
4367 entry = NEXT_TX(entry);
4369 /* Now loop through additional data fragments, and queue them. */
4370 if (skb_shinfo(skb)->nr_frags > 0) {
4371 unsigned int i, last;
4373 last = skb_shinfo(skb)->nr_frags - 1;
4374 for (i = 0; i <= last; i++) {
4375 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4378 mapping = pci_map_page(tp->pdev,
4381 len, PCI_DMA_TODEVICE);
4383 tp->tx_buffers[entry].skb = NULL;
4384 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4386 tg3_set_txd(tp, entry, mapping, len,
4387 base_flags, (i == last) | (mss << 1));
4389 entry = NEXT_TX(entry);
4393 /* Packets are ready, update Tx producer idx local and on card. */
4394 tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
4396 tp->tx_prod = entry;
4397 if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
4398 netif_stop_queue(dev);
4399 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
4400 netif_wake_queue(tp->dev);
4406 dev->trans_start = jiffies;
4408 return NETDEV_TX_OK;
4411 static int tg3_start_xmit_dma_bug(struct sk_buff *, struct net_device *);
4413 /* Use GSO to workaround a rare TSO bug that may be triggered when the
4414 * TSO header is greater than 80 bytes.
4416 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
4418 struct sk_buff *segs, *nskb;
4420 /* Estimate the number of fragments in the worst case */
4421 if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))) {
4422 netif_stop_queue(tp->dev);
4423 if (tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))
4424 return NETDEV_TX_BUSY;
4426 netif_wake_queue(tp->dev);
4429 segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
4431 goto tg3_tso_bug_end;
4437 tg3_start_xmit_dma_bug(nskb, tp->dev);
4443 return NETDEV_TX_OK;
4446 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
4447 * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
4449 static int tg3_start_xmit_dma_bug(struct sk_buff *skb, struct net_device *dev)
4451 struct tg3 *tp = netdev_priv(dev);
4453 u32 len, entry, base_flags, mss;
4454 int would_hit_hwbug;
4456 len = skb_headlen(skb);
4458 /* We are running in BH disabled context with netif_tx_lock
4459 * and TX reclaim runs via tp->napi.poll inside of a software
4460 * interrupt. Furthermore, IRQ processing runs lockless so we have
4461 * no IRQ context deadlocks to worry about either. Rejoice!
4463 if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
4464 if (!netif_queue_stopped(dev)) {
4465 netif_stop_queue(dev);
4467 /* This is a hard error, log it. */
4468 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
4469 "queue awake!\n", dev->name);
4471 return NETDEV_TX_BUSY;
4474 entry = tp->tx_prod;
4476 if (skb->ip_summed == CHECKSUM_PARTIAL)
4477 base_flags |= TXD_FLAG_TCPUDP_CSUM;
4479 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
4481 int tcp_opt_len, ip_tcp_len, hdr_len;
4483 if (skb_header_cloned(skb) &&
4484 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
4489 tcp_opt_len = tcp_optlen(skb);
4490 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
4492 hdr_len = ip_tcp_len + tcp_opt_len;
4493 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
4494 (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
4495 return (tg3_tso_bug(tp, skb));
4497 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
4498 TXD_FLAG_CPU_POST_DMA);
4502 iph->tot_len = htons(mss + hdr_len);
4503 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
4504 tcp_hdr(skb)->check = 0;
4505 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
4507 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4512 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
4513 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
4514 if (tcp_opt_len || iph->ihl > 5) {
4517 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
4518 mss |= (tsflags << 11);
4521 if (tcp_opt_len || iph->ihl > 5) {
4524 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
4525 base_flags |= tsflags << 12;
4529 #if TG3_VLAN_TAG_USED
4530 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
4531 base_flags |= (TXD_FLAG_VLAN |
4532 (vlan_tx_tag_get(skb) << 16));
4535 /* Queue skb data, a.k.a. the main skb fragment. */
4536 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
4538 tp->tx_buffers[entry].skb = skb;
4539 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4541 would_hit_hwbug = 0;
4543 if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
4544 would_hit_hwbug = 1;
4545 else if (tg3_4g_overflow_test(mapping, len))
4546 would_hit_hwbug = 1;
4548 tg3_set_txd(tp, entry, mapping, len, base_flags,
4549 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
4551 entry = NEXT_TX(entry);
4553 /* Now loop through additional data fragments, and queue them. */
4554 if (skb_shinfo(skb)->nr_frags > 0) {
4555 unsigned int i, last;
4557 last = skb_shinfo(skb)->nr_frags - 1;
4558 for (i = 0; i <= last; i++) {
4559 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4562 mapping = pci_map_page(tp->pdev,
4565 len, PCI_DMA_TODEVICE);
4567 tp->tx_buffers[entry].skb = NULL;
4568 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4570 if (tg3_4g_overflow_test(mapping, len))
4571 would_hit_hwbug = 1;
4573 if (tg3_40bit_overflow_test(tp, mapping, len))
4574 would_hit_hwbug = 1;
4576 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
4577 tg3_set_txd(tp, entry, mapping, len,
4578 base_flags, (i == last)|(mss << 1));
4580 tg3_set_txd(tp, entry, mapping, len,
4581 base_flags, (i == last));
4583 entry = NEXT_TX(entry);
4587 if (would_hit_hwbug) {
4588 u32 last_plus_one = entry;
4591 start = entry - 1 - skb_shinfo(skb)->nr_frags;
4592 start &= (TG3_TX_RING_SIZE - 1);
4594 /* If the workaround fails due to memory/mapping
4595 * failure, silently drop this packet.
4597 if (tigon3_dma_hwbug_workaround(tp, skb, last_plus_one,
4598 &start, base_flags, mss))
4604 /* Packets are ready, update Tx producer idx local and on card. */
4605 tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
4607 tp->tx_prod = entry;
4608 if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
4609 netif_stop_queue(dev);
4610 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
4611 netif_wake_queue(tp->dev);
4617 dev->trans_start = jiffies;
4619 return NETDEV_TX_OK;
4622 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
4627 if (new_mtu > ETH_DATA_LEN) {
4628 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
4629 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
4630 ethtool_op_set_tso(dev, 0);
4633 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
4635 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
4636 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
4637 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
4641 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
4643 struct tg3 *tp = netdev_priv(dev);
4646 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
4649 if (!netif_running(dev)) {
4650 /* We'll just catch it later when the
4653 tg3_set_mtu(dev, tp, new_mtu);
4659 tg3_full_lock(tp, 1);
4661 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
4663 tg3_set_mtu(dev, tp, new_mtu);
4665 err = tg3_restart_hw(tp, 0);
4668 tg3_netif_start(tp);
4670 tg3_full_unlock(tp);
4675 /* Free up pending packets in all rx/tx rings.
4677 * The chip has been shut down and the driver detached from
4678 * the networking, so no interrupts or new tx packets will
4679 * end up in the driver. tp->{tx,}lock is not held and we are not
4680 * in an interrupt context and thus may sleep.
4682 static void tg3_free_rings(struct tg3 *tp)
4684 struct ring_info *rxp;
4687 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
4688 rxp = &tp->rx_std_buffers[i];
4690 if (rxp->skb == NULL)
4692 pci_unmap_single(tp->pdev,
4693 pci_unmap_addr(rxp, mapping),
4694 tp->rx_pkt_buf_sz - tp->rx_offset,
4695 PCI_DMA_FROMDEVICE);
4696 dev_kfree_skb_any(rxp->skb);
4700 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
4701 rxp = &tp->rx_jumbo_buffers[i];
4703 if (rxp->skb == NULL)
4705 pci_unmap_single(tp->pdev,
4706 pci_unmap_addr(rxp, mapping),
4707 RX_JUMBO_PKT_BUF_SZ - tp->rx_offset,
4708 PCI_DMA_FROMDEVICE);
4709 dev_kfree_skb_any(rxp->skb);
4713 for (i = 0; i < TG3_TX_RING_SIZE; ) {
4714 struct tx_ring_info *txp;
4715 struct sk_buff *skb;
4718 txp = &tp->tx_buffers[i];
4726 pci_unmap_single(tp->pdev,
4727 pci_unmap_addr(txp, mapping),
4734 for (j = 0; j < skb_shinfo(skb)->nr_frags; j++) {
4735 txp = &tp->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
4736 pci_unmap_page(tp->pdev,
4737 pci_unmap_addr(txp, mapping),
4738 skb_shinfo(skb)->frags[j].size,
4743 dev_kfree_skb_any(skb);
4747 /* Initialize tx/rx rings for packet processing.
4749 * The chip has been shut down and the driver detached from
4750 * the networking, so no interrupts or new tx packets will
4751 * end up in the driver. tp->{tx,}lock are held and thus
4754 static int tg3_init_rings(struct tg3 *tp)
4758 /* Free up all the SKBs. */
4761 /* Zero out all descriptors. */
4762 memset(tp->rx_std, 0, TG3_RX_RING_BYTES);
4763 memset(tp->rx_jumbo, 0, TG3_RX_JUMBO_RING_BYTES);
4764 memset(tp->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
4765 memset(tp->tx_ring, 0, TG3_TX_RING_BYTES);
4767 tp->rx_pkt_buf_sz = RX_PKT_BUF_SZ;
4768 if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
4769 (tp->dev->mtu > ETH_DATA_LEN))
4770 tp->rx_pkt_buf_sz = RX_JUMBO_PKT_BUF_SZ;
4772 /* Initialize invariants of the rings, we only set this
4773 * stuff once. This works because the card does not
4774 * write into the rx buffer posting rings.
4776 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
4777 struct tg3_rx_buffer_desc *rxd;
4779 rxd = &tp->rx_std[i];
4780 rxd->idx_len = (tp->rx_pkt_buf_sz - tp->rx_offset - 64)
4782 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
4783 rxd->opaque = (RXD_OPAQUE_RING_STD |
4784 (i << RXD_OPAQUE_INDEX_SHIFT));
4787 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
4788 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
4789 struct tg3_rx_buffer_desc *rxd;
4791 rxd = &tp->rx_jumbo[i];
4792 rxd->idx_len = (RX_JUMBO_PKT_BUF_SZ - tp->rx_offset - 64)
4794 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
4796 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
4797 (i << RXD_OPAQUE_INDEX_SHIFT));
4801 /* Now allocate fresh SKBs for each rx ring. */
4802 for (i = 0; i < tp->rx_pending; i++) {
4803 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_STD, -1, i) < 0) {
4804 printk(KERN_WARNING PFX
4805 "%s: Using a smaller RX standard ring, "
4806 "only %d out of %d buffers were allocated "
4808 tp->dev->name, i, tp->rx_pending);
4816 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
4817 for (i = 0; i < tp->rx_jumbo_pending; i++) {
4818 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_JUMBO,
4820 printk(KERN_WARNING PFX
4821 "%s: Using a smaller RX jumbo ring, "
4822 "only %d out of %d buffers were "
4823 "allocated successfully.\n",
4824 tp->dev->name, i, tp->rx_jumbo_pending);
4829 tp->rx_jumbo_pending = i;
4838 * Must not be invoked with interrupt sources disabled and
4839 * the hardware shutdown down.
4841 static void tg3_free_consistent(struct tg3 *tp)
4843 kfree(tp->rx_std_buffers);
4844 tp->rx_std_buffers = NULL;
4846 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
4847 tp->rx_std, tp->rx_std_mapping);
4851 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
4852 tp->rx_jumbo, tp->rx_jumbo_mapping);
4853 tp->rx_jumbo = NULL;
4856 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
4857 tp->rx_rcb, tp->rx_rcb_mapping);
4861 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
4862 tp->tx_ring, tp->tx_desc_mapping);
4865 if (tp->hw_status) {
4866 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
4867 tp->hw_status, tp->status_mapping);
4868 tp->hw_status = NULL;
4871 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
4872 tp->hw_stats, tp->stats_mapping);
4873 tp->hw_stats = NULL;
4878 * Must not be invoked with interrupt sources disabled and
4879 * the hardware shutdown down. Can sleep.
4881 static int tg3_alloc_consistent(struct tg3 *tp)
4883 tp->rx_std_buffers = kzalloc((sizeof(struct ring_info) *
4885 TG3_RX_JUMBO_RING_SIZE)) +
4886 (sizeof(struct tx_ring_info) *
4889 if (!tp->rx_std_buffers)
4892 tp->rx_jumbo_buffers = &tp->rx_std_buffers[TG3_RX_RING_SIZE];
4893 tp->tx_buffers = (struct tx_ring_info *)
4894 &tp->rx_jumbo_buffers[TG3_RX_JUMBO_RING_SIZE];
4896 tp->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
4897 &tp->rx_std_mapping);
4901 tp->rx_jumbo = pci_alloc_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
4902 &tp->rx_jumbo_mapping);
4907 tp->rx_rcb = pci_alloc_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
4908 &tp->rx_rcb_mapping);
4912 tp->tx_ring = pci_alloc_consistent(tp->pdev, TG3_TX_RING_BYTES,
4913 &tp->tx_desc_mapping);
4917 tp->hw_status = pci_alloc_consistent(tp->pdev,
4919 &tp->status_mapping);
4923 tp->hw_stats = pci_alloc_consistent(tp->pdev,
4924 sizeof(struct tg3_hw_stats),
4925 &tp->stats_mapping);
4929 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
4930 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
4935 tg3_free_consistent(tp);
4939 #define MAX_WAIT_CNT 1000
4941 /* To stop a block, clear the enable bit and poll till it
4942 * clears. tp->lock is held.
4944 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
4949 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
4956 /* We can't enable/disable these bits of the
4957 * 5705/5750, just say success.
4970 for (i = 0; i < MAX_WAIT_CNT; i++) {
4973 if ((val & enable_bit) == 0)
4977 if (i == MAX_WAIT_CNT && !silent) {
4978 printk(KERN_ERR PFX "tg3_stop_block timed out, "
4979 "ofs=%lx enable_bit=%x\n",
4987 /* tp->lock is held. */
4988 static int tg3_abort_hw(struct tg3 *tp, int silent)
4992 tg3_disable_ints(tp);
4994 tp->rx_mode &= ~RX_MODE_ENABLE;
4995 tw32_f(MAC_RX_MODE, tp->rx_mode);
4998 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
4999 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
5000 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
5001 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
5002 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
5003 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
5005 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
5006 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
5007 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
5008 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
5009 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
5010 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
5011 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
5013 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
5014 tw32_f(MAC_MODE, tp->mac_mode);
5017 tp->tx_mode &= ~TX_MODE_ENABLE;
5018 tw32_f(MAC_TX_MODE, tp->tx_mode);
5020 for (i = 0; i < MAX_WAIT_CNT; i++) {
5022 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
5025 if (i >= MAX_WAIT_CNT) {
5026 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
5027 "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
5028 tp->dev->name, tr32(MAC_TX_MODE));
5032 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
5033 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
5034 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
5036 tw32(FTQ_RESET, 0xffffffff);
5037 tw32(FTQ_RESET, 0x00000000);
5039 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
5040 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
5043 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
5045 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
5050 /* tp->lock is held. */
5051 static int tg3_nvram_lock(struct tg3 *tp)
5053 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
5056 if (tp->nvram_lock_cnt == 0) {
5057 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
5058 for (i = 0; i < 8000; i++) {
5059 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
5064 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
5068 tp->nvram_lock_cnt++;
5073 /* tp->lock is held. */
5074 static void tg3_nvram_unlock(struct tg3 *tp)
5076 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
5077 if (tp->nvram_lock_cnt > 0)
5078 tp->nvram_lock_cnt--;
5079 if (tp->nvram_lock_cnt == 0)
5080 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
5084 /* tp->lock is held. */
5085 static void tg3_enable_nvram_access(struct tg3 *tp)
5087 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
5088 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
5089 u32 nvaccess = tr32(NVRAM_ACCESS);
5091 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
5095 /* tp->lock is held. */
5096 static void tg3_disable_nvram_access(struct tg3 *tp)
5098 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
5099 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
5100 u32 nvaccess = tr32(NVRAM_ACCESS);
5102 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
5106 static void tg3_ape_send_event(struct tg3 *tp, u32 event)
5111 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
5112 if (apedata != APE_SEG_SIG_MAGIC)
5115 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
5116 if (apedata != APE_FW_STATUS_READY)
5119 /* Wait for up to 1 millisecond for APE to service previous event. */
5120 for (i = 0; i < 10; i++) {
5121 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
5124 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
5126 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5127 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
5128 event | APE_EVENT_STATUS_EVENT_PENDING);
5130 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
5132 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5138 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5139 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
5142 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
5147 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
5151 case RESET_KIND_INIT:
5152 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
5153 APE_HOST_SEG_SIG_MAGIC);
5154 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
5155 APE_HOST_SEG_LEN_MAGIC);
5156 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
5157 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
5158 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
5159 APE_HOST_DRIVER_ID_MAGIC);
5160 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
5161 APE_HOST_BEHAV_NO_PHYLOCK);
5163 event = APE_EVENT_STATUS_STATE_START;
5165 case RESET_KIND_SHUTDOWN:
5166 event = APE_EVENT_STATUS_STATE_UNLOAD;
5168 case RESET_KIND_SUSPEND:
5169 event = APE_EVENT_STATUS_STATE_SUSPEND;
5175 event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
5177 tg3_ape_send_event(tp, event);
5180 /* tp->lock is held. */
5181 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
5183 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
5184 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
5186 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
5188 case RESET_KIND_INIT:
5189 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5193 case RESET_KIND_SHUTDOWN:
5194 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5198 case RESET_KIND_SUSPEND:
5199 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5208 if (kind == RESET_KIND_INIT ||
5209 kind == RESET_KIND_SUSPEND)
5210 tg3_ape_driver_state_change(tp, kind);
5213 /* tp->lock is held. */
5214 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
5216 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
5218 case RESET_KIND_INIT:
5219 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5220 DRV_STATE_START_DONE);
5223 case RESET_KIND_SHUTDOWN:
5224 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5225 DRV_STATE_UNLOAD_DONE);
5233 if (kind == RESET_KIND_SHUTDOWN)
5234 tg3_ape_driver_state_change(tp, kind);
5237 /* tp->lock is held. */
5238 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
5240 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
5242 case RESET_KIND_INIT:
5243 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5247 case RESET_KIND_SHUTDOWN:
5248 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5252 case RESET_KIND_SUSPEND:
5253 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5263 static int tg3_poll_fw(struct tg3 *tp)
5268 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
5269 /* Wait up to 20ms for init done. */
5270 for (i = 0; i < 200; i++) {
5271 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
5278 /* Wait for firmware initialization to complete. */
5279 for (i = 0; i < 100000; i++) {
5280 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
5281 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
5286 /* Chip might not be fitted with firmware. Some Sun onboard
5287 * parts are configured like that. So don't signal the timeout
5288 * of the above loop as an error, but do report the lack of
5289 * running firmware once.
5292 !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
5293 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
5295 printk(KERN_INFO PFX "%s: No firmware running.\n",
5302 /* Save PCI command register before chip reset */
5303 static void tg3_save_pci_state(struct tg3 *tp)
5305 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
5308 /* Restore PCI state after chip reset */
5309 static void tg3_restore_pci_state(struct tg3 *tp)
5313 /* Re-enable indirect register accesses. */
5314 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
5315 tp->misc_host_ctrl);
5317 /* Set MAX PCI retry to zero. */
5318 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
5319 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
5320 (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
5321 val |= PCISTATE_RETRY_SAME_DMA;
5322 /* Allow reads and writes to the APE register and memory space. */
5323 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
5324 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
5325 PCISTATE_ALLOW_APE_SHMEM_WR;
5326 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
5328 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
5330 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
5331 pcie_set_readrq(tp->pdev, 4096);
5333 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
5334 tp->pci_cacheline_sz);
5335 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
5339 /* Make sure PCI-X relaxed ordering bit is clear. */
5343 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
5345 pcix_cmd &= ~PCI_X_CMD_ERO;
5346 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
5350 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
5352 /* Chip reset on 5780 will reset MSI enable bit,
5353 * so need to restore it.
5355 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
5358 pci_read_config_word(tp->pdev,
5359 tp->msi_cap + PCI_MSI_FLAGS,
5361 pci_write_config_word(tp->pdev,
5362 tp->msi_cap + PCI_MSI_FLAGS,
5363 ctrl | PCI_MSI_FLAGS_ENABLE);
5364 val = tr32(MSGINT_MODE);
5365 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
5370 static void tg3_stop_fw(struct tg3 *);
5372 /* tp->lock is held. */
5373 static int tg3_chip_reset(struct tg3 *tp)
5376 void (*write_op)(struct tg3 *, u32, u32);
5381 /* No matching tg3_nvram_unlock() after this because
5382 * chip reset below will undo the nvram lock.
5384 tp->nvram_lock_cnt = 0;
5386 /* GRC_MISC_CFG core clock reset will clear the memory
5387 * enable bit in PCI register 4 and the MSI enable bit
5388 * on some chips, so we save relevant registers here.
5390 tg3_save_pci_state(tp);
5392 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
5393 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
5394 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
5395 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
5396 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
5397 tw32(GRC_FASTBOOT_PC, 0);
5400 * We must avoid the readl() that normally takes place.
5401 * It locks machines, causes machine checks, and other
5402 * fun things. So, temporarily disable the 5701
5403 * hardware workaround, while we do the reset.
5405 write_op = tp->write32;
5406 if (write_op == tg3_write_flush_reg32)
5407 tp->write32 = tg3_write32;
5409 /* Prevent the irq handler from reading or writing PCI registers
5410 * during chip reset when the memory enable bit in the PCI command
5411 * register may be cleared. The chip does not generate interrupt
5412 * at this time, but the irq handler may still be called due to irq
5413 * sharing or irqpoll.
5415 tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
5416 if (tp->hw_status) {
5417 tp->hw_status->status = 0;
5418 tp->hw_status->status_tag = 0;
5422 synchronize_irq(tp->pdev->irq);
5425 val = GRC_MISC_CFG_CORECLK_RESET;
5427 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
5428 if (tr32(0x7e2c) == 0x60) {
5431 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
5432 tw32(GRC_MISC_CFG, (1 << 29));
5437 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
5438 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
5439 tw32(GRC_VCPU_EXT_CTRL,
5440 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
5443 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
5444 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
5445 tw32(GRC_MISC_CFG, val);
5447 /* restore 5701 hardware bug workaround write method */
5448 tp->write32 = write_op;
5450 /* Unfortunately, we have to delay before the PCI read back.
5451 * Some 575X chips even will not respond to a PCI cfg access
5452 * when the reset command is given to the chip.
5454 * How do these hardware designers expect things to work
5455 * properly if the PCI write is posted for a long period
5456 * of time? It is always necessary to have some method by
5457 * which a register read back can occur to push the write
5458 * out which does the reset.
5460 * For most tg3 variants the trick below was working.
5465 /* Flush PCI posted writes. The normal MMIO registers
5466 * are inaccessible at this time so this is the only
5467 * way to make this reliably (actually, this is no longer
5468 * the case, see above). I tried to use indirect
5469 * register read/write but this upset some 5701 variants.
5471 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
5475 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
5476 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
5480 /* Wait for link training to complete. */
5481 for (i = 0; i < 5000; i++)
5484 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
5485 pci_write_config_dword(tp->pdev, 0xc4,
5486 cfg_val | (1 << 15));
5488 /* Set PCIE max payload size and clear error status. */
5489 pci_write_config_dword(tp->pdev, 0xd8, 0xf5000);
5492 tg3_restore_pci_state(tp);
5494 tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
5497 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
5498 val = tr32(MEMARB_MODE);
5499 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
5501 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
5503 tw32(0x5000, 0x400);
5506 tw32(GRC_MODE, tp->grc_mode);
5508 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
5511 tw32(0xc4, val | (1 << 15));
5514 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
5515 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
5516 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
5517 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
5518 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
5519 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
5522 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
5523 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
5524 tw32_f(MAC_MODE, tp->mac_mode);
5525 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
5526 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
5527 tw32_f(MAC_MODE, tp->mac_mode);
5529 tw32_f(MAC_MODE, 0);
5532 err = tg3_poll_fw(tp);
5536 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
5537 tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
5540 tw32(0x7c00, val | (1 << 25));
5543 /* Reprobe ASF enable state. */
5544 tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
5545 tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
5546 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
5547 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
5550 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
5551 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
5552 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
5553 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
5554 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
5561 /* tp->lock is held. */
5562 static void tg3_stop_fw(struct tg3 *tp)
5564 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
5565 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
5568 /* Wait for RX cpu to ACK the previous event. */
5569 tg3_wait_for_event_ack(tp);
5571 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
5572 val = tr32(GRC_RX_CPU_EVENT);
5573 val |= GRC_RX_CPU_DRIVER_EVENT;
5574 tw32(GRC_RX_CPU_EVENT, val);
5576 /* Wait for RX cpu to ACK this event. */
5577 tg3_wait_for_event_ack(tp);
5581 /* tp->lock is held. */
5582 static int tg3_halt(struct tg3 *tp, int kind, int silent)
5588 tg3_write_sig_pre_reset(tp, kind);
5590 tg3_abort_hw(tp, silent);
5591 err = tg3_chip_reset(tp);
5593 tg3_write_sig_legacy(tp, kind);
5594 tg3_write_sig_post_reset(tp, kind);
5602 #define TG3_FW_RELEASE_MAJOR 0x0
5603 #define TG3_FW_RELASE_MINOR 0x0
5604 #define TG3_FW_RELEASE_FIX 0x0
5605 #define TG3_FW_START_ADDR 0x08000000
5606 #define TG3_FW_TEXT_ADDR 0x08000000
5607 #define TG3_FW_TEXT_LEN 0x9c0
5608 #define TG3_FW_RODATA_ADDR 0x080009c0
5609 #define TG3_FW_RODATA_LEN 0x60
5610 #define TG3_FW_DATA_ADDR 0x08000a40
5611 #define TG3_FW_DATA_LEN 0x20
5612 #define TG3_FW_SBSS_ADDR 0x08000a60
5613 #define TG3_FW_SBSS_LEN 0xc
5614 #define TG3_FW_BSS_ADDR 0x08000a70
5615 #define TG3_FW_BSS_LEN 0x10
5617 static const u32 tg3FwText[(TG3_FW_TEXT_LEN / sizeof(u32)) + 1] = {
5618 0x00000000, 0x10000003, 0x00000000, 0x0000000d, 0x0000000d, 0x3c1d0800,
5619 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100000, 0x0e000018, 0x00000000,
5620 0x0000000d, 0x3c1d0800, 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100034,
5621 0x0e00021c, 0x00000000, 0x0000000d, 0x00000000, 0x00000000, 0x00000000,
5622 0x27bdffe0, 0x3c1cc000, 0xafbf0018, 0xaf80680c, 0x0e00004c, 0x241b2105,
5623 0x97850000, 0x97870002, 0x9782002c, 0x9783002e, 0x3c040800, 0x248409c0,
5624 0xafa00014, 0x00021400, 0x00621825, 0x00052c00, 0xafa30010, 0x8f860010,
5625 0x00e52825, 0x0e000060, 0x24070102, 0x3c02ac00, 0x34420100, 0x3c03ac01,
5626 0x34630100, 0xaf820490, 0x3c02ffff, 0xaf820494, 0xaf830498, 0xaf82049c,
5627 0x24020001, 0xaf825ce0, 0x0e00003f, 0xaf825d00, 0x0e000140, 0x00000000,
5628 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x2402ffff, 0xaf825404, 0x8f835400,
5629 0x34630400, 0xaf835400, 0xaf825404, 0x3c020800, 0x24420034, 0xaf82541c,
5630 0x03e00008, 0xaf805400, 0x00000000, 0x00000000, 0x3c020800, 0x34423000,
5631 0x3c030800, 0x34633000, 0x3c040800, 0x348437ff, 0x3c010800, 0xac220a64,
5632 0x24020040, 0x3c010800, 0xac220a68, 0x3c010800, 0xac200a60, 0xac600000,
5633 0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
5634 0x00804821, 0x8faa0010, 0x3c020800, 0x8c420a60, 0x3c040800, 0x8c840a68,
5635 0x8fab0014, 0x24430001, 0x0044102b, 0x3c010800, 0xac230a60, 0x14400003,
5636 0x00004021, 0x3c010800, 0xac200a60, 0x3c020800, 0x8c420a60, 0x3c030800,
5637 0x8c630a64, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
5638 0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020800, 0x8c420a60,
5639 0x3c030800, 0x8c630a64, 0x8f84680c, 0x00021140, 0x00431021, 0xac440008,
5640 0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
5641 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5642 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5644 0x02000008, 0x00000000, 0x0a0001e3, 0x3c0a0001, 0x0a0001e3, 0x3c0a0002,
5645 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5646 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5647 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5648 0x0a0001e3, 0x3c0a0007, 0x0a0001e3, 0x3c0a0008, 0x0a0001e3, 0x3c0a0009,
5649 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000b,
5650 0x0a0001e3, 0x3c0a000c, 0x0a0001e3, 0x3c0a000d, 0x0a0001e3, 0x00000000,
5651 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000e, 0x0a0001e3, 0x00000000,
5652 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5653 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5654 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a0013, 0x0a0001e3, 0x3c0a0014,
5655 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5656 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5657 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5658 0x27bdffe0, 0x00001821, 0x00001021, 0xafbf0018, 0xafb10014, 0xafb00010,
5659 0x3c010800, 0x00220821, 0xac200a70, 0x3c010800, 0x00220821, 0xac200a74,
5660 0x3c010800, 0x00220821, 0xac200a78, 0x24630001, 0x1860fff5, 0x2442000c,
5661 0x24110001, 0x8f906810, 0x32020004, 0x14400005, 0x24040001, 0x3c020800,
5662 0x8c420a78, 0x18400003, 0x00002021, 0x0e000182, 0x00000000, 0x32020001,
5663 0x10400003, 0x00000000, 0x0e000169, 0x00000000, 0x0a000153, 0xaf915028,
5664 0x8fbf0018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020, 0x3c050800,
5665 0x8ca50a70, 0x3c060800, 0x8cc60a80, 0x3c070800, 0x8ce70a78, 0x27bdffe0,
5666 0x3c040800, 0x248409d0, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014,
5667 0x0e00017b, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x24020001,
5668 0x8f836810, 0x00821004, 0x00021027, 0x00621824, 0x03e00008, 0xaf836810,
5669 0x27bdffd8, 0xafbf0024, 0x1080002e, 0xafb00020, 0x8f825cec, 0xafa20018,
5670 0x8f825cec, 0x3c100800, 0x26100a78, 0xafa2001c, 0x34028000, 0xaf825cec,
5671 0x8e020000, 0x18400016, 0x00000000, 0x3c020800, 0x94420a74, 0x8fa3001c,
5672 0x000221c0, 0xac830004, 0x8fa2001c, 0x3c010800, 0x0e000201, 0xac220a74,
5673 0x10400005, 0x00000000, 0x8e020000, 0x24420001, 0x0a0001df, 0xae020000,
5674 0x3c020800, 0x8c420a70, 0x00021c02, 0x000321c0, 0x0a0001c5, 0xafa2001c,
5675 0x0e000201, 0x00000000, 0x1040001f, 0x00000000, 0x8e020000, 0x8fa3001c,
5676 0x24420001, 0x3c010800, 0xac230a70, 0x3c010800, 0xac230a74, 0x0a0001df,
5677 0xae020000, 0x3c100800, 0x26100a78, 0x8e020000, 0x18400028, 0x00000000,
5678 0x0e000201, 0x00000000, 0x14400024, 0x00000000, 0x8e020000, 0x3c030800,
5679 0x8c630a70, 0x2442ffff, 0xafa3001c, 0x18400006, 0xae020000, 0x00031402,
5680 0x000221c0, 0x8c820004, 0x3c010800, 0xac220a70, 0x97a2001e, 0x2442ff00,
5681 0x2c420300, 0x1440000b, 0x24024000, 0x3c040800, 0x248409dc, 0xafa00010,
5682 0xafa00014, 0x8fa6001c, 0x24050008, 0x0e000060, 0x00003821, 0x0a0001df,
5683 0x00000000, 0xaf825cf8, 0x3c020800, 0x8c420a40, 0x8fa3001c, 0x24420001,
5684 0xaf835cf8, 0x3c010800, 0xac220a40, 0x8fbf0024, 0x8fb00020, 0x03e00008,
5685 0x27bd0028, 0x27bdffe0, 0x3c040800, 0x248409e8, 0x00002821, 0x00003021,
5686 0x00003821, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x8fbf0018,
5687 0x03e00008, 0x27bd0020, 0x8f82680c, 0x8f85680c, 0x00021827, 0x0003182b,
5688 0x00031823, 0x00431024, 0x00441021, 0x00a2282b, 0x10a00006, 0x00000000,
5689 0x00401821, 0x8f82680c, 0x0043102b, 0x1440fffd, 0x00000000, 0x03e00008,
5690 0x00000000, 0x3c040800, 0x8c840000, 0x3c030800, 0x8c630a40, 0x0064102b,
5691 0x54400002, 0x00831023, 0x00641023, 0x2c420008, 0x03e00008, 0x38420001,
5692 0x27bdffe0, 0x00802821, 0x3c040800, 0x24840a00, 0x00003021, 0x00003821,
5693 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x0a000216, 0x00000000,
5694 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000, 0x27bdffe0, 0x3c1cc000,
5695 0xafbf0018, 0x0e00004c, 0xaf80680c, 0x3c040800, 0x24840a10, 0x03802821,
5696 0x00003021, 0x00003821, 0xafa00010, 0x0e000060, 0xafa00014, 0x2402ffff,
5697 0xaf825404, 0x3c0200aa, 0x0e000234, 0xaf825434, 0x8fbf0018, 0x03e00008,
5698 0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe8, 0xafb00010,
5699 0x24100001, 0xafbf0014, 0x3c01c003, 0xac200000, 0x8f826810, 0x30422000,
5700 0x10400003, 0x00000000, 0x0e000246, 0x00000000, 0x0a00023a, 0xaf905428,
5701 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x27bdfff8, 0x8f845d0c,
5702 0x3c0200ff, 0x3c030800, 0x8c630a50, 0x3442fff8, 0x00821024, 0x1043001e,
5703 0x3c0500ff, 0x34a5fff8, 0x3c06c003, 0x3c074000, 0x00851824, 0x8c620010,
5704 0x3c010800, 0xac230a50, 0x30420008, 0x10400005, 0x00871025, 0x8cc20000,
5705 0x24420001, 0xacc20000, 0x00871025, 0xaf825d0c, 0x8fa20000, 0x24420001,
5706 0xafa20000, 0x8fa20000, 0x8fa20000, 0x24420001, 0xafa20000, 0x8fa20000,
5707 0x8f845d0c, 0x3c030800, 0x8c630a50, 0x00851024, 0x1443ffe8, 0x00851824,
5708 0x27bd0008, 0x03e00008, 0x00000000, 0x00000000, 0x00000000
5711 static const u32 tg3FwRodata[(TG3_FW_RODATA_LEN / sizeof(u32)) + 1] = {
5712 0x35373031, 0x726c7341, 0x00000000, 0x00000000, 0x53774576, 0x656e7430,
5713 0x00000000, 0x726c7045, 0x76656e74, 0x31000000, 0x556e6b6e, 0x45766e74,
5714 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
5715 0x00000000, 0x00000000, 0x4d61696e, 0x43707542, 0x00000000, 0x00000000,
5719 #if 0 /* All zeros, don't eat up space with it. */
5720 u32 tg3FwData[(TG3_FW_DATA_LEN / sizeof(u32)) + 1] = {
5721 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
5722 0x00000000, 0x00000000, 0x00000000, 0x00000000
5726 #define RX_CPU_SCRATCH_BASE 0x30000
5727 #define RX_CPU_SCRATCH_SIZE 0x04000
5728 #define TX_CPU_SCRATCH_BASE 0x34000
5729 #define TX_CPU_SCRATCH_SIZE 0x04000
5731 /* tp->lock is held. */
5732 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
5736 BUG_ON(offset == TX_CPU_BASE &&
5737 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
5739 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
5740 u32 val = tr32(GRC_VCPU_EXT_CTRL);
5742 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
5745 if (offset == RX_CPU_BASE) {
5746 for (i = 0; i < 10000; i++) {
5747 tw32(offset + CPU_STATE, 0xffffffff);
5748 tw32(offset + CPU_MODE, CPU_MODE_HALT);
5749 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
5753 tw32(offset + CPU_STATE, 0xffffffff);
5754 tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
5757 for (i = 0; i < 10000; i++) {
5758 tw32(offset + CPU_STATE, 0xffffffff);
5759 tw32(offset + CPU_MODE, CPU_MODE_HALT);
5760 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
5766 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
5769 (offset == RX_CPU_BASE ? "RX" : "TX"));
5773 /* Clear firmware's nvram arbitration. */
5774 if (tp->tg3_flags & TG3_FLAG_NVRAM)
5775 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
5780 unsigned int text_base;
5781 unsigned int text_len;
5782 const u32 *text_data;
5783 unsigned int rodata_base;
5784 unsigned int rodata_len;
5785 const u32 *rodata_data;
5786 unsigned int data_base;
5787 unsigned int data_len;
5788 const u32 *data_data;
5791 /* tp->lock is held. */
5792 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
5793 int cpu_scratch_size, struct fw_info *info)
5795 int err, lock_err, i;
5796 void (*write_op)(struct tg3 *, u32, u32);
5798 if (cpu_base == TX_CPU_BASE &&
5799 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5800 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
5801 "TX cpu firmware on %s which is 5705.\n",
5806 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
5807 write_op = tg3_write_mem;
5809 write_op = tg3_write_indirect_reg32;
5811 /* It is possible that bootcode is still loading at this point.
5812 * Get the nvram lock first before halting the cpu.
5814 lock_err = tg3_nvram_lock(tp);
5815 err = tg3_halt_cpu(tp, cpu_base);
5817 tg3_nvram_unlock(tp);
5821 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
5822 write_op(tp, cpu_scratch_base + i, 0);
5823 tw32(cpu_base + CPU_STATE, 0xffffffff);
5824 tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
5825 for (i = 0; i < (info->text_len / sizeof(u32)); i++)
5826 write_op(tp, (cpu_scratch_base +
5827 (info->text_base & 0xffff) +
5830 info->text_data[i] : 0));
5831 for (i = 0; i < (info->rodata_len / sizeof(u32)); i++)
5832 write_op(tp, (cpu_scratch_base +
5833 (info->rodata_base & 0xffff) +
5835 (info->rodata_data ?
5836 info->rodata_data[i] : 0));
5837 for (i = 0; i < (info->data_len / sizeof(u32)); i++)
5838 write_op(tp, (cpu_scratch_base +
5839 (info->data_base & 0xffff) +
5842 info->data_data[i] : 0));
5850 /* tp->lock is held. */
5851 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
5853 struct fw_info info;
5856 info.text_base = TG3_FW_TEXT_ADDR;
5857 info.text_len = TG3_FW_TEXT_LEN;
5858 info.text_data = &tg3FwText[0];
5859 info.rodata_base = TG3_FW_RODATA_ADDR;
5860 info.rodata_len = TG3_FW_RODATA_LEN;
5861 info.rodata_data = &tg3FwRodata[0];
5862 info.data_base = TG3_FW_DATA_ADDR;
5863 info.data_len = TG3_FW_DATA_LEN;
5864 info.data_data = NULL;
5866 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
5867 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
5872 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
5873 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
5878 /* Now startup only the RX cpu. */
5879 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5880 tw32_f(RX_CPU_BASE + CPU_PC, TG3_FW_TEXT_ADDR);
5882 for (i = 0; i < 5; i++) {
5883 if (tr32(RX_CPU_BASE + CPU_PC) == TG3_FW_TEXT_ADDR)
5885 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5886 tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
5887 tw32_f(RX_CPU_BASE + CPU_PC, TG3_FW_TEXT_ADDR);
5891 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
5892 "to set RX CPU PC, is %08x should be %08x\n",
5893 tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
5897 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5898 tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
5904 #define TG3_TSO_FW_RELEASE_MAJOR 0x1
5905 #define TG3_TSO_FW_RELASE_MINOR 0x6
5906 #define TG3_TSO_FW_RELEASE_FIX 0x0
5907 #define TG3_TSO_FW_START_ADDR 0x08000000
5908 #define TG3_TSO_FW_TEXT_ADDR 0x08000000
5909 #define TG3_TSO_FW_TEXT_LEN 0x1aa0
5910 #define TG3_TSO_FW_RODATA_ADDR 0x08001aa0
5911 #define TG3_TSO_FW_RODATA_LEN 0x60
5912 #define TG3_TSO_FW_DATA_ADDR 0x08001b20
5913 #define TG3_TSO_FW_DATA_LEN 0x30
5914 #define TG3_TSO_FW_SBSS_ADDR 0x08001b50
5915 #define TG3_TSO_FW_SBSS_LEN 0x2c
5916 #define TG3_TSO_FW_BSS_ADDR 0x08001b80
5917 #define TG3_TSO_FW_BSS_LEN 0x894
5919 static const u32 tg3TsoFwText[(TG3_TSO_FW_TEXT_LEN / 4) + 1] = {
5920 0x0e000003, 0x00000000, 0x08001b24, 0x00000000, 0x10000003, 0x00000000,
5921 0x0000000d, 0x0000000d, 0x3c1d0800, 0x37bd4000, 0x03a0f021, 0x3c100800,
5922 0x26100000, 0x0e000010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
5923 0xafbf0018, 0x0e0005d8, 0x34840002, 0x0e000668, 0x00000000, 0x3c030800,
5924 0x90631b68, 0x24020002, 0x3c040800, 0x24841aac, 0x14620003, 0x24050001,
5925 0x3c040800, 0x24841aa0, 0x24060006, 0x00003821, 0xafa00010, 0x0e00067c,
5926 0xafa00014, 0x8f625c50, 0x34420001, 0xaf625c50, 0x8f625c90, 0x34420001,
5927 0xaf625c90, 0x2402ffff, 0x0e000034, 0xaf625404, 0x8fbf0018, 0x03e00008,
5928 0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c,
5929 0xafb20018, 0xafb10014, 0x0e00005b, 0xafb00010, 0x24120002, 0x24110001,
5930 0x8f706820, 0x32020100, 0x10400003, 0x00000000, 0x0e0000bb, 0x00000000,
5931 0x8f706820, 0x32022000, 0x10400004, 0x32020001, 0x0e0001f0, 0x24040001,
5932 0x32020001, 0x10400003, 0x00000000, 0x0e0000a3, 0x00000000, 0x3c020800,
5933 0x90421b98, 0x14520003, 0x00000000, 0x0e0004c0, 0x00000000, 0x0a00003c,
5934 0xaf715028, 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008,
5935 0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ac0, 0x00002821, 0x00003021,
5936 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x3c040800,
5937 0x248423d8, 0xa4800000, 0x3c010800, 0xa0201b98, 0x3c010800, 0xac201b9c,
5938 0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
5939 0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bbc, 0x8f624434, 0x3c010800,
5940 0xac221b88, 0x8f624438, 0x3c010800, 0xac221b8c, 0x8f624410, 0xac80f7a8,
5941 0x3c010800, 0xac201b84, 0x3c010800, 0xac2023e0, 0x3c010800, 0xac2023c8,
5942 0x3c010800, 0xac2023cc, 0x3c010800, 0xac202400, 0x3c010800, 0xac221b90,
5943 0x8f620068, 0x24030007, 0x00021702, 0x10430005, 0x00000000, 0x8f620068,
5944 0x00021702, 0x14400004, 0x24020001, 0x3c010800, 0x0a000097, 0xac20240c,
5945 0xac820034, 0x3c040800, 0x24841acc, 0x3c050800, 0x8ca5240c, 0x00003021,
5946 0x00003821, 0xafa00010, 0x0e00067c, 0xafa00014, 0x8fbf0018, 0x03e00008,
5947 0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ad8, 0x00002821, 0x00003021,
5948 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x0e00005b,
5949 0x00000000, 0x0e0000b4, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020,
5950 0x24020001, 0x8f636820, 0x00821004, 0x00021027, 0x00621824, 0x03e00008,
5951 0xaf636820, 0x27bdffd0, 0xafbf002c, 0xafb60028, 0xafb50024, 0xafb40020,
5952 0xafb3001c, 0xafb20018, 0xafb10014, 0xafb00010, 0x8f675c5c, 0x3c030800,
5953 0x24631bbc, 0x8c620000, 0x14470005, 0x3c0200ff, 0x3c020800, 0x90421b98,
5954 0x14400119, 0x3c0200ff, 0x3442fff8, 0x00e28824, 0xac670000, 0x00111902,
5955 0x306300ff, 0x30e20003, 0x000211c0, 0x00622825, 0x00a04021, 0x00071602,
5956 0x3c030800, 0x90631b98, 0x3044000f, 0x14600036, 0x00804821, 0x24020001,
5957 0x3c010800, 0xa0221b98, 0x00051100, 0x00821025, 0x3c010800, 0xac201b9c,
5958 0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
5959 0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bb0, 0x3c010800, 0xac201bb4,
5960 0x3c010800, 0xa42223d8, 0x9622000c, 0x30437fff, 0x3c010800, 0xa4222410,
5961 0x30428000, 0x3c010800, 0xa4231bc6, 0x10400005, 0x24020001, 0x3c010800,
5962 0xac2223f4, 0x0a000102, 0x2406003e, 0x24060036, 0x3c010800, 0xac2023f4,
5963 0x9622000a, 0x3c030800, 0x94631bc6, 0x3c010800, 0xac2023f0, 0x3c010800,
5964 0xac2023f8, 0x00021302, 0x00021080, 0x00c21021, 0x00621821, 0x3c010800,
5965 0xa42223d0, 0x3c010800, 0x0a000115, 0xa4231b96, 0x9622000c, 0x3c010800,
5966 0xa42223ec, 0x3c040800, 0x24841b9c, 0x8c820000, 0x00021100, 0x3c010800,
5967 0x00220821, 0xac311bc8, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
5968 0xac271bcc, 0x8c820000, 0x25030001, 0x306601ff, 0x00021100, 0x3c010800,
5969 0x00220821, 0xac261bd0, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
5970 0xac291bd4, 0x96230008, 0x3c020800, 0x8c421bac, 0x00432821, 0x3c010800,
5971 0xac251bac, 0x9622000a, 0x30420004, 0x14400018, 0x00061100, 0x8f630c14,
5972 0x3063000f, 0x2c620002, 0x1440000b, 0x3c02c000, 0x8f630c14, 0x3c020800,
5973 0x8c421b40, 0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002,
5974 0x1040fff7, 0x3c02c000, 0x00e21825, 0xaf635c5c, 0x8f625c50, 0x30420002,
5975 0x10400014, 0x00000000, 0x0a000147, 0x00000000, 0x3c030800, 0x8c631b80,
5976 0x3c040800, 0x94841b94, 0x01221025, 0x3c010800, 0xa42223da, 0x24020001,
5977 0x3c010800, 0xac221bb8, 0x24630001, 0x0085202a, 0x3c010800, 0x10800003,
5978 0xac231b80, 0x3c010800, 0xa4251b94, 0x3c060800, 0x24c61b9c, 0x8cc20000,
5979 0x24420001, 0xacc20000, 0x28420080, 0x14400005, 0x00000000, 0x0e000656,
5980 0x24040002, 0x0a0001e6, 0x00000000, 0x3c020800, 0x8c421bb8, 0x10400078,
5981 0x24020001, 0x3c050800, 0x90a51b98, 0x14a20072, 0x00000000, 0x3c150800,
5982 0x96b51b96, 0x3c040800, 0x8c841bac, 0x32a3ffff, 0x0083102a, 0x1440006c,
5983 0x00000000, 0x14830003, 0x00000000, 0x3c010800, 0xac2523f0, 0x1060005c,
5984 0x00009021, 0x24d60004, 0x0060a021, 0x24d30014, 0x8ec20000, 0x00028100,
5985 0x3c110800, 0x02308821, 0x0e000625, 0x8e311bc8, 0x00402821, 0x10a00054,
5986 0x00000000, 0x9628000a, 0x31020040, 0x10400005, 0x2407180c, 0x8e22000c,
5987 0x2407188c, 0x00021400, 0xaca20018, 0x3c030800, 0x00701821, 0x8c631bd0,
5988 0x3c020800, 0x00501021, 0x8c421bd4, 0x00031d00, 0x00021400, 0x00621825,
5989 0xaca30014, 0x8ec30004, 0x96220008, 0x00432023, 0x3242ffff, 0x3083ffff,
5990 0x00431021, 0x0282102a, 0x14400002, 0x02b23023, 0x00803021, 0x8e620000,
5991 0x30c4ffff, 0x00441021, 0xae620000, 0x8e220000, 0xaca20000, 0x8e220004,
5992 0x8e63fff4, 0x00431021, 0xaca20004, 0xa4a6000e, 0x8e62fff4, 0x00441021,
5993 0xae62fff4, 0x96230008, 0x0043102a, 0x14400005, 0x02469021, 0x8e62fff0,
5994 0xae60fff4, 0x24420001, 0xae62fff0, 0xaca00008, 0x3242ffff, 0x14540008,
5995 0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x24020905, 0xa4a2000c,
5996 0x0a0001cb, 0x34e70020, 0xa4a2000c, 0x3c020800, 0x8c4223f0, 0x10400003,
5997 0x3c024b65, 0x0a0001d3, 0x34427654, 0x3c02b49a, 0x344289ab, 0xaca2001c,
5998 0x30e2ffff, 0xaca20010, 0x0e0005a2, 0x00a02021, 0x3242ffff, 0x0054102b,
5999 0x1440ffa9, 0x00000000, 0x24020002, 0x3c010800, 0x0a0001e6, 0xa0221b98,
6000 0x8ec2083c, 0x24420001, 0x0a0001e6, 0xaec2083c, 0x0e0004c0, 0x00000000,
6001 0x8fbf002c, 0x8fb60028, 0x8fb50024, 0x8fb40020, 0x8fb3001c, 0x8fb20018,
6002 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0030, 0x27bdffd0, 0xafbf0028,
6003 0xafb30024, 0xafb20020, 0xafb1001c, 0xafb00018, 0x8f725c9c, 0x3c0200ff,
6004 0x3442fff8, 0x3c070800, 0x24e71bb4, 0x02428824, 0x9623000e, 0x8ce20000,
6005 0x00431021, 0xace20000, 0x8e220010, 0x30420020, 0x14400011, 0x00809821,
6006 0x0e00063b, 0x02202021, 0x3c02c000, 0x02421825, 0xaf635c9c, 0x8f625c90,
6007 0x30420002, 0x1040011e, 0x00000000, 0xaf635c9c, 0x8f625c90, 0x30420002,
6008 0x10400119, 0x00000000, 0x0a00020d, 0x00000000, 0x8e240008, 0x8e230014,
6009 0x00041402, 0x000231c0, 0x00031502, 0x304201ff, 0x2442ffff, 0x3042007f,
6010 0x00031942, 0x30637800, 0x00021100, 0x24424000, 0x00624821, 0x9522000a,
6011 0x3084ffff, 0x30420008, 0x104000b0, 0x000429c0, 0x3c020800, 0x8c422400,
6012 0x14400024, 0x24c50008, 0x94c20014, 0x3c010800, 0xa42223d0, 0x8cc40010,
6013 0x00041402, 0x3c010800, 0xa42223d2, 0x3c010800, 0xa42423d4, 0x94c2000e,
6014 0x3083ffff, 0x00431023, 0x3c010800, 0xac222408, 0x94c2001a, 0x3c010800,
6015 0xac262400, 0x3c010800, 0xac322404, 0x3c010800, 0xac2223fc, 0x3c02c000,
6016 0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e5, 0x00000000,
6017 0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e0, 0x00000000, 0x0a000246,
6018 0x00000000, 0x94c2000e, 0x3c030800, 0x946323d4, 0x00434023, 0x3103ffff,
6019 0x2c620008, 0x1040001c, 0x00000000, 0x94c20014, 0x24420028, 0x00a22821,
6020 0x00031042, 0x1840000b, 0x00002021, 0x24e60848, 0x00403821, 0x94a30000,
6021 0x8cc20000, 0x24840001, 0x00431021, 0xacc20000, 0x0087102a, 0x1440fff9,
6022 0x24a50002, 0x31020001, 0x1040001f, 0x3c024000, 0x3c040800, 0x248423fc,
6023 0xa0a00001, 0x94a30000, 0x8c820000, 0x00431021, 0x0a000285, 0xac820000,
6024 0x8f626800, 0x3c030010, 0x00431024, 0x10400009, 0x00000000, 0x94c2001a,
6025 0x3c030800, 0x8c6323fc, 0x00431021, 0x3c010800, 0xac2223fc, 0x0a000286,
6026 0x3c024000, 0x94c2001a, 0x94c4001c, 0x3c030800, 0x8c6323fc, 0x00441023,
6027 0x00621821, 0x3c010800, 0xac2323fc, 0x3c024000, 0x02421825, 0xaf635c9c,
6028 0x8f625c90, 0x30420002, 0x1440fffc, 0x00000000, 0x9522000a, 0x30420010,
6029 0x1040009b, 0x00000000, 0x3c030800, 0x946323d4, 0x3c070800, 0x24e72400,
6030 0x8ce40000, 0x8f626800, 0x24630030, 0x00832821, 0x3c030010, 0x00431024,
6031 0x1440000a, 0x00000000, 0x94a20004, 0x3c040800, 0x8c842408, 0x3c030800,
6032 0x8c6323fc, 0x00441023, 0x00621821, 0x3c010800, 0xac2323fc, 0x3c040800,
6033 0x8c8423fc, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402, 0x00822021,
6034 0x00041027, 0xa4a20006, 0x3c030800, 0x8c632404, 0x3c0200ff, 0x3442fff8,
6035 0x00628824, 0x96220008, 0x24050001, 0x24034000, 0x000231c0, 0x00801021,
6036 0xa4c2001a, 0xa4c0001c, 0xace00000, 0x3c010800, 0xac251b60, 0xaf635cb8,
6037 0x8f625cb0, 0x30420002, 0x10400003, 0x00000000, 0x3c010800, 0xac201b60,
6038 0x8e220008, 0xaf625cb8, 0x8f625cb0, 0x30420002, 0x10400003, 0x00000000,
6039 0x3c010800, 0xac201b60, 0x3c020800, 0x8c421b60, 0x1040ffec, 0x00000000,
6040 0x3c040800, 0x0e00063b, 0x8c842404, 0x0a00032a, 0x00000000, 0x3c030800,
6041 0x90631b98, 0x24020002, 0x14620003, 0x3c034b65, 0x0a0002e1, 0x00008021,
6042 0x8e22001c, 0x34637654, 0x10430002, 0x24100002, 0x24100001, 0x00c02021,
6043 0x0e000350, 0x02003021, 0x24020003, 0x3c010800, 0xa0221b98, 0x24020002,
6044 0x1202000a, 0x24020001, 0x3c030800, 0x8c6323f0, 0x10620006, 0x00000000,
6045 0x3c020800, 0x944223d8, 0x00021400, 0x0a00031f, 0xae220014, 0x3c040800,
6046 0x248423da, 0x94820000, 0x00021400, 0xae220014, 0x3c020800, 0x8c421bbc,
6047 0x3c03c000, 0x3c010800, 0xa0201b98, 0x00431025, 0xaf625c5c, 0x8f625c50,
6048 0x30420002, 0x10400009, 0x00000000, 0x2484f7e2, 0x8c820000, 0x00431025,
6049 0xaf625c5c, 0x8f625c50, 0x30420002, 0x1440fffa, 0x00000000, 0x3c020800,
6050 0x24421b84, 0x8c430000, 0x24630001, 0xac430000, 0x8f630c14, 0x3063000f,
6051 0x2c620002, 0x1440000c, 0x3c024000, 0x8f630c14, 0x3c020800, 0x8c421b40,
6052 0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7,
6053 0x00000000, 0x3c024000, 0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002,
6054 0x1440fffc, 0x00000000, 0x12600003, 0x00000000, 0x0e0004c0, 0x00000000,
6055 0x8fbf0028, 0x8fb30024, 0x8fb20020, 0x8fb1001c, 0x8fb00018, 0x03e00008,
6056 0x27bd0030, 0x8f634450, 0x3c040800, 0x24841b88, 0x8c820000, 0x00031c02,
6057 0x0043102b, 0x14400007, 0x3c038000, 0x8c840004, 0x8f624450, 0x00021c02,
6058 0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
6059 0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3c024000,
6060 0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00000000,
6061 0x03e00008, 0x00000000, 0x27bdffe0, 0x00805821, 0x14c00011, 0x256e0008,
6062 0x3c020800, 0x8c4223f4, 0x10400007, 0x24020016, 0x3c010800, 0xa42223d2,
6063 0x2402002a, 0x3c010800, 0x0a000364, 0xa42223d4, 0x8d670010, 0x00071402,
6064 0x3c010800, 0xa42223d2, 0x3c010800, 0xa42723d4, 0x3c040800, 0x948423d4,
6065 0x3c030800, 0x946323d2, 0x95cf0006, 0x3c020800, 0x944223d0, 0x00832023,
6066 0x01e2c023, 0x3065ffff, 0x24a20028, 0x01c24821, 0x3082ffff, 0x14c0001a,
6067 0x01226021, 0x9582000c, 0x3042003f, 0x3c010800, 0xa42223d6, 0x95820004,
6068 0x95830006, 0x3c010800, 0xac2023e4, 0x3c010800, 0xac2023e8, 0x00021400,
6069 0x00431025, 0x3c010800, 0xac221bc0, 0x95220004, 0x3c010800, 0xa4221bc4,
6070 0x95230002, 0x01e51023, 0x0043102a, 0x10400010, 0x24020001, 0x3c010800,
6071 0x0a000398, 0xac2223f8, 0x3c030800, 0x8c6323e8, 0x3c020800, 0x94421bc4,
6072 0x00431021, 0xa5220004, 0x3c020800, 0x94421bc0, 0xa5820004, 0x3c020800,
6073 0x8c421bc0, 0xa5820006, 0x3c020800, 0x8c4223f0, 0x3c0d0800, 0x8dad23e4,
6074 0x3c0a0800, 0x144000e5, 0x8d4a23e8, 0x3c020800, 0x94421bc4, 0x004a1821,
6075 0x3063ffff, 0x0062182b, 0x24020002, 0x10c2000d, 0x01435023, 0x3c020800,
6076 0x944223d6, 0x30420009, 0x10400008, 0x00000000, 0x9582000c, 0x3042fff6,
6077 0xa582000c, 0x3c020800, 0x944223d6, 0x30420009, 0x01a26823, 0x3c020800,
6078 0x8c4223f8, 0x1040004a, 0x01203821, 0x3c020800, 0x944223d2, 0x00004021,
6079 0xa520000a, 0x01e21023, 0xa5220002, 0x3082ffff, 0x00021042, 0x18400008,
6080 0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021, 0x0103102a,
6081 0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061402,
6082 0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021, 0x2527000c,
6083 0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004, 0x1440fffb,
6084 0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023, 0x01803821,
6085 0x3082ffff, 0xa4e00010, 0x00621821, 0x00021042, 0x18400010, 0x00c33021,
6086 0x00404821, 0x94e20000, 0x24e70002, 0x00c23021, 0x30e2007f, 0x14400006,
6087 0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80, 0x00625824, 0x25670008,
6088 0x0109102a, 0x1440fff3, 0x00000000, 0x30820001, 0x10400005, 0x00061c02,
6089 0xa0e00001, 0x94e20000, 0x00c23021, 0x00061c02, 0x30c2ffff, 0x00623021,
6090 0x00061402, 0x00c23021, 0x0a00047d, 0x30c6ffff, 0x24020002, 0x14c20081,
6091 0x00000000, 0x3c020800, 0x8c42240c, 0x14400007, 0x00000000, 0x3c020800,
6092 0x944223d2, 0x95230002, 0x01e21023, 0x10620077, 0x00000000, 0x3c020800,
6093 0x944223d2, 0x01e21023, 0xa5220002, 0x3c020800, 0x8c42240c, 0x1040001a,
6094 0x31e3ffff, 0x8dc70010, 0x3c020800, 0x94421b96, 0x00e04021, 0x00072c02,
6095 0x00aa2021, 0x00431023, 0x00823823, 0x00072402, 0x30e2ffff, 0x00823821,
6096 0x00071027, 0xa522000a, 0x3102ffff, 0x3c040800, 0x948423d4, 0x00453023,
6097 0x00e02821, 0x00641823, 0x006d1821, 0x00c33021, 0x00061c02, 0x30c2ffff,
6098 0x0a00047d, 0x00623021, 0x01203821, 0x00004021, 0x3082ffff, 0x00021042,
6099 0x18400008, 0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021,
6100 0x0103102a, 0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021,
6101 0x00061402, 0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021,
6102 0x2527000c, 0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004,
6103 0x1440fffb, 0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023,
6104 0x01803821, 0x3082ffff, 0xa4e00010, 0x3c040800, 0x948423d4, 0x00621821,
6105 0x00c33021, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061c02, 0x3c020800,
6106 0x944223d0, 0x00c34821, 0x00441023, 0x00021fc2, 0x00431021, 0x00021043,
6107 0x18400010, 0x00003021, 0x00402021, 0x94e20000, 0x24e70002, 0x00c23021,
6108 0x30e2007f, 0x14400006, 0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80,
6109 0x00625824, 0x25670008, 0x0104102a, 0x1440fff3, 0x00000000, 0x3c020800,
6110 0x944223ec, 0x00c23021, 0x3122ffff, 0x00c23021, 0x00061c02, 0x30c2ffff,
6111 0x00623021, 0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010,
6112 0xadc00014, 0x0a00049d, 0xadc00000, 0x8dc70010, 0x00e04021, 0x11400007,
6113 0x00072c02, 0x00aa3021, 0x00061402, 0x30c3ffff, 0x00433021, 0x00061402,
6114 0x00c22821, 0x00051027, 0xa522000a, 0x3c030800, 0x946323d4, 0x3102ffff,
6115 0x01e21021, 0x00433023, 0x00cd3021, 0x00061c02, 0x30c2ffff, 0x00623021,
6116 0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010, 0x3102ffff,
6117 0x00051c00, 0x00431025, 0xadc20010, 0x3c020800, 0x8c4223f4, 0x10400005,
6118 0x2de205eb, 0x14400002, 0x25e2fff2, 0x34028870, 0xa5c20034, 0x3c030800,
6119 0x246323e8, 0x8c620000, 0x24420001, 0xac620000, 0x3c040800, 0x8c8423e4,
6120 0x3c020800, 0x8c421bc0, 0x3303ffff, 0x00832021, 0x00431821, 0x0062102b,
6121 0x3c010800, 0xac2423e4, 0x10400003, 0x2482ffff, 0x3c010800, 0xac2223e4,
6122 0x3c010800, 0xac231bc0, 0x03e00008, 0x27bd0020, 0x27bdffb8, 0x3c050800,
6123 0x24a51b96, 0xafbf0044, 0xafbe0040, 0xafb7003c, 0xafb60038, 0xafb50034,
6124 0xafb40030, 0xafb3002c, 0xafb20028, 0xafb10024, 0xafb00020, 0x94a90000,
6125 0x3c020800, 0x944223d0, 0x3c030800, 0x8c631bb0, 0x3c040800, 0x8c841bac,
6126 0x01221023, 0x0064182a, 0xa7a9001e, 0x106000be, 0xa7a20016, 0x24be0022,
6127 0x97b6001e, 0x24b3001a, 0x24b70016, 0x8fc20000, 0x14400008, 0x00000000,
6128 0x8fc2fff8, 0x97a30016, 0x8fc4fff4, 0x00431021, 0x0082202a, 0x148000b0,
6129 0x00000000, 0x97d50818, 0x32a2ffff, 0x104000a3, 0x00009021, 0x0040a021,
6130 0x00008821, 0x0e000625, 0x00000000, 0x00403021, 0x14c00007, 0x00000000,
6131 0x3c020800, 0x8c4223dc, 0x24420001, 0x3c010800, 0x0a000596, 0xac2223dc,
6132 0x3c100800, 0x02118021, 0x8e101bc8, 0x9608000a, 0x31020040, 0x10400005,
6133 0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x31020080,
6134 0x54400001, 0x34e70010, 0x3c020800, 0x00511021, 0x8c421bd0, 0x3c030800,
6135 0x00711821, 0x8c631bd4, 0x00021500, 0x00031c00, 0x00431025, 0xacc20014,
6136 0x96040008, 0x3242ffff, 0x00821021, 0x0282102a, 0x14400002, 0x02b22823,
6137 0x00802821, 0x8e020000, 0x02459021, 0xacc20000, 0x8e020004, 0x00c02021,
6138 0x26310010, 0xac820004, 0x30e2ffff, 0xac800008, 0xa485000e, 0xac820010,
6139 0x24020305, 0x0e0005a2, 0xa482000c, 0x3242ffff, 0x0054102b, 0x1440ffc5,
6140 0x3242ffff, 0x0a00058e, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
6141 0x10400067, 0x00000000, 0x8e62fff0, 0x00028900, 0x3c100800, 0x02118021,
6142 0x0e000625, 0x8e101bc8, 0x00403021, 0x14c00005, 0x00000000, 0x8e62082c,
6143 0x24420001, 0x0a000596, 0xae62082c, 0x9608000a, 0x31020040, 0x10400005,
6144 0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x3c020800,
6145 0x00511021, 0x8c421bd0, 0x3c030800, 0x00711821, 0x8c631bd4, 0x00021500,
6146 0x00031c00, 0x00431025, 0xacc20014, 0x8e63fff4, 0x96020008, 0x00432023,
6147 0x3242ffff, 0x3083ffff, 0x00431021, 0x02c2102a, 0x10400003, 0x00802821,
6148 0x97a9001e, 0x01322823, 0x8e620000, 0x30a4ffff, 0x00441021, 0xae620000,
6149 0xa4c5000e, 0x8e020000, 0xacc20000, 0x8e020004, 0x8e63fff4, 0x00431021,
6150 0xacc20004, 0x8e63fff4, 0x96020008, 0x00641821, 0x0062102a, 0x14400006,
6151 0x02459021, 0x8e62fff0, 0xae60fff4, 0x24420001, 0x0a000571, 0xae62fff0,
6152 0xae63fff4, 0xacc00008, 0x3242ffff, 0x10560003, 0x31020004, 0x10400006,
6153 0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x34e70020, 0x24020905,
6154 0xa4c2000c, 0x8ee30000, 0x8ee20004, 0x14620007, 0x3c02b49a, 0x8ee20860,
6155 0x54400001, 0x34e70400, 0x3c024b65, 0x0a000588, 0x34427654, 0x344289ab,
6156 0xacc2001c, 0x30e2ffff, 0xacc20010, 0x0e0005a2, 0x00c02021, 0x3242ffff,
6157 0x0056102b, 0x1440ff9b, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
6158 0x1440ff48, 0x00000000, 0x8fbf0044, 0x8fbe0040, 0x8fb7003c, 0x8fb60038,
6159 0x8fb50034, 0x8fb40030, 0x8fb3002c, 0x8fb20028, 0x8fb10024, 0x8fb00020,
6160 0x03e00008, 0x27bd0048, 0x27bdffe8, 0xafbf0014, 0xafb00010, 0x8f624450,
6161 0x8f634410, 0x0a0005b1, 0x00808021, 0x8f626820, 0x30422000, 0x10400003,
6162 0x00000000, 0x0e0001f0, 0x00002021, 0x8f624450, 0x8f634410, 0x3042ffff,
6163 0x0043102b, 0x1440fff5, 0x00000000, 0x8f630c14, 0x3063000f, 0x2c620002,
6164 0x1440000b, 0x00000000, 0x8f630c14, 0x3c020800, 0x8c421b40, 0x3063000f,
6165 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7, 0x00000000,
6166 0xaf705c18, 0x8f625c10, 0x30420002, 0x10400009, 0x00000000, 0x8f626820,
6167 0x30422000, 0x1040fff8, 0x00000000, 0x0e0001f0, 0x00002021, 0x0a0005c4,
6168 0x00000000, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000,
6169 0x00000000, 0x00000000, 0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010,
6170 0xaf60680c, 0x8f626804, 0x34420082, 0xaf626804, 0x8f634000, 0x24020b50,
6171 0x3c010800, 0xac221b54, 0x24020b78, 0x3c010800, 0xac221b64, 0x34630002,
6172 0xaf634000, 0x0e000605, 0x00808021, 0x3c010800, 0xa0221b68, 0x304200ff,
6173 0x24030002, 0x14430005, 0x00000000, 0x3c020800, 0x8c421b54, 0x0a0005f8,
6174 0xac5000c0, 0x3c020800, 0x8c421b54, 0xac5000bc, 0x8f624434, 0x8f634438,
6175 0x8f644410, 0x3c010800, 0xac221b5c, 0x3c010800, 0xac231b6c, 0x3c010800,
6176 0xac241b58, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x3c040800,
6177 0x8c870000, 0x3c03aa55, 0x3463aa55, 0x3c06c003, 0xac830000, 0x8cc20000,
6178 0x14430007, 0x24050002, 0x3c0355aa, 0x346355aa, 0xac830000, 0x8cc20000,
6179 0x50430001, 0x24050001, 0x3c020800, 0xac470000, 0x03e00008, 0x00a01021,
6180 0x27bdfff8, 0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe,
6181 0x00000000, 0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008,
6182 0x27bd0008, 0x8f634450, 0x3c020800, 0x8c421b5c, 0x00031c02, 0x0043102b,
6183 0x14400008, 0x3c038000, 0x3c040800, 0x8c841b6c, 0x8f624450, 0x00021c02,
6184 0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
6185 0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff,
6186 0x2442e000, 0x2c422001, 0x14400003, 0x3c024000, 0x0a000648, 0x2402ffff,
6187 0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021,
6188 0x03e00008, 0x00000000, 0x8f624450, 0x3c030800, 0x8c631b58, 0x0a000651,
6189 0x3042ffff, 0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000,
6190 0x03e00008, 0x00000000, 0x27bdffe0, 0x00802821, 0x3c040800, 0x24841af0,
6191 0x00003021, 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014,
6192 0x0a000660, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000,
6193 0x00000000, 0x00000000, 0x3c020800, 0x34423000, 0x3c030800, 0x34633000,
6194 0x3c040800, 0x348437ff, 0x3c010800, 0xac221b74, 0x24020040, 0x3c010800,
6195 0xac221b78, 0x3c010800, 0xac201b70, 0xac600000, 0x24630004, 0x0083102b,
6196 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000, 0x00804821, 0x8faa0010,
6197 0x3c020800, 0x8c421b70, 0x3c040800, 0x8c841b78, 0x8fab0014, 0x24430001,
6198 0x0044102b, 0x3c010800, 0xac231b70, 0x14400003, 0x00004021, 0x3c010800,
6199 0xac201b70, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74, 0x91240000,
6200 0x00021140, 0x00431021, 0x00481021, 0x25080001, 0xa0440000, 0x29020008,
6201 0x1440fff4, 0x25290001, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74,
6202 0x8f64680c, 0x00021140, 0x00431021, 0xac440008, 0xac45000c, 0xac460010,
6203 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c, 0x00000000, 0x00000000,
6206 static const u32 tg3TsoFwRodata[] = {
6207 0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
6208 0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x496e0000, 0x73746b6f,
6209 0x66662a2a, 0x00000000, 0x53774576, 0x656e7430, 0x00000000, 0x00000000,
6210 0x00000000, 0x00000000, 0x66617461, 0x6c457272, 0x00000000, 0x00000000,
6214 static const u32 tg3TsoFwData[] = {
6215 0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x362e3000, 0x00000000,
6216 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
6220 /* 5705 needs a special version of the TSO firmware. */
6221 #define TG3_TSO5_FW_RELEASE_MAJOR 0x1
6222 #define TG3_TSO5_FW_RELASE_MINOR 0x2
6223 #define TG3_TSO5_FW_RELEASE_FIX 0x0
6224 #define TG3_TSO5_FW_START_ADDR 0x00010000
6225 #define TG3_TSO5_FW_TEXT_ADDR 0x00010000
6226 #define TG3_TSO5_FW_TEXT_LEN 0xe90
6227 #define TG3_TSO5_FW_RODATA_ADDR 0x00010e90
6228 #define TG3_TSO5_FW_RODATA_LEN 0x50
6229 #define TG3_TSO5_FW_DATA_ADDR 0x00010f00
6230 #define TG3_TSO5_FW_DATA_LEN 0x20
6231 #define TG3_TSO5_FW_SBSS_ADDR 0x00010f20
6232 #define TG3_TSO5_FW_SBSS_LEN 0x28
6233 #define TG3_TSO5_FW_BSS_ADDR 0x00010f50
6234 #define TG3_TSO5_FW_BSS_LEN 0x88
6236 static const u32 tg3Tso5FwText[(TG3_TSO5_FW_TEXT_LEN / 4) + 1] = {
6237 0x0c004003, 0x00000000, 0x00010f04, 0x00000000, 0x10000003, 0x00000000,
6238 0x0000000d, 0x0000000d, 0x3c1d0001, 0x37bde000, 0x03a0f021, 0x3c100001,
6239 0x26100000, 0x0c004010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
6240 0xafbf0018, 0x0c0042e8, 0x34840002, 0x0c004364, 0x00000000, 0x3c030001,
6241 0x90630f34, 0x24020002, 0x3c040001, 0x24840e9c, 0x14620003, 0x24050001,
6242 0x3c040001, 0x24840e90, 0x24060002, 0x00003821, 0xafa00010, 0x0c004378,
6243 0xafa00014, 0x0c00402c, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020,
6244 0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c, 0xafb20018, 0xafb10014,
6245 0x0c0042d4, 0xafb00010, 0x3c128000, 0x24110001, 0x8f706810, 0x32020400,
6246 0x10400007, 0x00000000, 0x8f641008, 0x00921024, 0x14400003, 0x00000000,
6247 0x0c004064, 0x00000000, 0x3c020001, 0x90420f56, 0x10510003, 0x32020200,
6248 0x1040fff1, 0x00000000, 0x0c0041b4, 0x00000000, 0x08004034, 0x00000000,
6249 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020,
6250 0x27bdffe0, 0x3c040001, 0x24840eb0, 0x00002821, 0x00003021, 0x00003821,
6251 0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0000d021, 0x24020130,
6252 0xaf625000, 0x3c010001, 0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018,
6253 0x03e00008, 0x27bd0020, 0x00000000, 0x00000000, 0x3c030001, 0x24630f60,
6254 0x90620000, 0x27bdfff0, 0x14400003, 0x0080c021, 0x08004073, 0x00004821,
6255 0x3c022000, 0x03021024, 0x10400003, 0x24090002, 0x08004073, 0xa0600000,
6256 0x24090001, 0x00181040, 0x30431f80, 0x346f8008, 0x1520004b, 0x25eb0028,
6257 0x3c040001, 0x00832021, 0x8c848010, 0x3c050001, 0x24a50f7a, 0x00041402,
6258 0xa0a20000, 0x3c010001, 0xa0240f7b, 0x3c020001, 0x00431021, 0x94428014,
6259 0x3c010001, 0xa0220f7c, 0x3c0c0001, 0x01836021, 0x8d8c8018, 0x304200ff,
6260 0x24420008, 0x000220c3, 0x24020001, 0x3c010001, 0xa0220f60, 0x0124102b,
6261 0x1040000c, 0x00003821, 0x24a6000e, 0x01602821, 0x8ca20000, 0x8ca30004,
6262 0x24a50008, 0x24e70001, 0xacc20000, 0xacc30004, 0x00e4102b, 0x1440fff8,
6263 0x24c60008, 0x00003821, 0x3c080001, 0x25080f7b, 0x91060000, 0x3c020001,
6264 0x90420f7c, 0x2503000d, 0x00c32821, 0x00461023, 0x00021fc2, 0x00431021,
6265 0x00021043, 0x1840000c, 0x00002021, 0x91020001, 0x00461023, 0x00021fc2,
6266 0x00431021, 0x00021843, 0x94a20000, 0x24e70001, 0x00822021, 0x00e3102a,
6267 0x1440fffb, 0x24a50002, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
6268 0x00822021, 0x3c02ffff, 0x01821024, 0x3083ffff, 0x00431025, 0x3c010001,
6269 0x080040fa, 0xac220f80, 0x3c050001, 0x24a50f7c, 0x90a20000, 0x3c0c0001,
6270 0x01836021, 0x8d8c8018, 0x000220c2, 0x1080000e, 0x00003821, 0x01603021,
6271 0x24a5000c, 0x8ca20000, 0x8ca30004, 0x24a50008, 0x24e70001, 0xacc20000,
6272 0xacc30004, 0x00e4102b, 0x1440fff8, 0x24c60008, 0x3c050001, 0x24a50f7c,
6273 0x90a20000, 0x30430007, 0x24020004, 0x10620011, 0x28620005, 0x10400005,
6274 0x24020002, 0x10620008, 0x000710c0, 0x080040fa, 0x00000000, 0x24020006,
6275 0x1062000e, 0x000710c0, 0x080040fa, 0x00000000, 0x00a21821, 0x9463000c,
6276 0x004b1021, 0x080040fa, 0xa4430000, 0x000710c0, 0x00a21821, 0x8c63000c,
6277 0x004b1021, 0x080040fa, 0xac430000, 0x00a21821, 0x8c63000c, 0x004b2021,
6278 0x00a21021, 0xac830000, 0x94420010, 0xa4820004, 0x95e70006, 0x3c020001,
6279 0x90420f7c, 0x3c030001, 0x90630f7a, 0x00e2c823, 0x3c020001, 0x90420f7b,
6280 0x24630028, 0x01e34021, 0x24420028, 0x15200012, 0x01e23021, 0x94c2000c,
6281 0x3c010001, 0xa4220f78, 0x94c20004, 0x94c30006, 0x3c010001, 0xa4200f76,
6282 0x3c010001, 0xa4200f72, 0x00021400, 0x00431025, 0x3c010001, 0xac220f6c,
6283 0x95020004, 0x3c010001, 0x08004124, 0xa4220f70, 0x3c020001, 0x94420f70,
6284 0x3c030001, 0x94630f72, 0x00431021, 0xa5020004, 0x3c020001, 0x94420f6c,
6285 0xa4c20004, 0x3c020001, 0x8c420f6c, 0xa4c20006, 0x3c040001, 0x94840f72,
6286 0x3c020001, 0x94420f70, 0x3c0a0001, 0x954a0f76, 0x00441821, 0x3063ffff,
6287 0x0062182a, 0x24020002, 0x1122000b, 0x00832023, 0x3c030001, 0x94630f78,
6288 0x30620009, 0x10400006, 0x3062fff6, 0xa4c2000c, 0x3c020001, 0x94420f78,
6289 0x30420009, 0x01425023, 0x24020001, 0x1122001b, 0x29220002, 0x50400005,
6290 0x24020002, 0x11200007, 0x31a2ffff, 0x08004197, 0x00000000, 0x1122001d,
6291 0x24020016, 0x08004197, 0x31a2ffff, 0x3c0e0001, 0x95ce0f80, 0x10800005,
6292 0x01806821, 0x01c42021, 0x00041c02, 0x3082ffff, 0x00627021, 0x000e1027,
6293 0xa502000a, 0x3c030001, 0x90630f7b, 0x31a2ffff, 0x00e21021, 0x0800418d,
6294 0x00432023, 0x3c020001, 0x94420f80, 0x00442021, 0x00041c02, 0x3082ffff,
6295 0x00622021, 0x00807021, 0x00041027, 0x08004185, 0xa502000a, 0x3c050001,
6296 0x24a50f7a, 0x90a30000, 0x14620002, 0x24e2fff2, 0xa5e20034, 0x90a20000,
6297 0x00e21023, 0xa5020002, 0x3c030001, 0x94630f80, 0x3c020001, 0x94420f5a,
6298 0x30e5ffff, 0x00641821, 0x00451023, 0x00622023, 0x00041c02, 0x3082ffff,
6299 0x00622021, 0x00041027, 0xa502000a, 0x3c030001, 0x90630f7c, 0x24620001,
6300 0x14a20005, 0x00807021, 0x01631021, 0x90420000, 0x08004185, 0x00026200,
6301 0x24620002, 0x14a20003, 0x306200fe, 0x004b1021, 0x944c0000, 0x3c020001,
6302 0x94420f82, 0x3183ffff, 0x3c040001, 0x90840f7b, 0x00431021, 0x00e21021,
6303 0x00442023, 0x008a2021, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
6304 0x00822021, 0x00806821, 0x00041027, 0xa4c20010, 0x31a2ffff, 0x000e1c00,
6305 0x00431025, 0x3c040001, 0x24840f72, 0xade20010, 0x94820000, 0x3c050001,
6306 0x94a50f76, 0x3c030001, 0x8c630f6c, 0x24420001, 0x00b92821, 0xa4820000,
6307 0x3322ffff, 0x00622021, 0x0083182b, 0x3c010001, 0xa4250f76, 0x10600003,
6308 0x24a2ffff, 0x3c010001, 0xa4220f76, 0x3c024000, 0x03021025, 0x3c010001,
6309 0xac240f6c, 0xaf621008, 0x03e00008, 0x27bd0010, 0x3c030001, 0x90630f56,
6310 0x27bdffe8, 0x24020001, 0xafbf0014, 0x10620026, 0xafb00010, 0x8f620cf4,
6311 0x2442ffff, 0x3042007f, 0x00021100, 0x8c434000, 0x3c010001, 0xac230f64,
6312 0x8c434008, 0x24444000, 0x8c5c4004, 0x30620040, 0x14400002, 0x24020088,
6313 0x24020008, 0x3c010001, 0xa4220f68, 0x30620004, 0x10400005, 0x24020001,
6314 0x3c010001, 0xa0220f57, 0x080041d5, 0x00031402, 0x3c010001, 0xa0200f57,
6315 0x00031402, 0x3c010001, 0xa4220f54, 0x9483000c, 0x24020001, 0x3c010001,
6316 0xa4200f50, 0x3c010001, 0xa0220f56, 0x3c010001, 0xa4230f62, 0x24020001,
6317 0x1342001e, 0x00000000, 0x13400005, 0x24020003, 0x13420067, 0x00000000,
6318 0x080042cf, 0x00000000, 0x3c020001, 0x94420f62, 0x241a0001, 0x3c010001,
6319 0xa4200f5e, 0x3c010001, 0xa4200f52, 0x304407ff, 0x00021bc2, 0x00031823,
6320 0x3063003e, 0x34630036, 0x00021242, 0x3042003c, 0x00621821, 0x3c010001,
6321 0xa4240f58, 0x00832021, 0x24630030, 0x3c010001, 0xa4240f5a, 0x3c010001,
6322 0xa4230f5c, 0x3c060001, 0x24c60f52, 0x94c50000, 0x94c30002, 0x3c040001,
6323 0x94840f5a, 0x00651021, 0x0044102a, 0x10400013, 0x3c108000, 0x00a31021,
6324 0xa4c20000, 0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008,
6325 0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4,
6326 0x00501024, 0x104000b7, 0x00000000, 0x0800420f, 0x00000000, 0x3c030001,
6327 0x94630f50, 0x00851023, 0xa4c40000, 0x00621821, 0x3042ffff, 0x3c010001,
6328 0xa4230f50, 0xaf620ce8, 0x3c020001, 0x94420f68, 0x34420024, 0xaf620cec,
6329 0x94c30002, 0x3c020001, 0x94420f50, 0x14620012, 0x3c028000, 0x3c108000,
6330 0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008, 0x00901024,
6331 0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024,
6332 0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003, 0xaf620cf4, 0x3c108000,
6333 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000,
6334 0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003,
6335 0x3c070001, 0x24e70f50, 0x94e20000, 0x03821021, 0xaf620ce0, 0x3c020001,
6336 0x8c420f64, 0xaf620ce4, 0x3c050001, 0x94a50f54, 0x94e30000, 0x3c040001,
6337 0x94840f58, 0x3c020001, 0x94420f5e, 0x00a32823, 0x00822023, 0x30a6ffff,
6338 0x3083ffff, 0x00c3102b, 0x14400043, 0x00000000, 0x3c020001, 0x94420f5c,
6339 0x00021400, 0x00621025, 0xaf620ce8, 0x94e20000, 0x3c030001, 0x94630f54,
6340 0x00441021, 0xa4e20000, 0x3042ffff, 0x14430021, 0x3c020008, 0x3c020001,
6341 0x90420f57, 0x10400006, 0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624,
6342 0x0800427c, 0x0000d021, 0x3c020001, 0x94420f68, 0x3c030008, 0x34630624,
6343 0x00431025, 0xaf620cec, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
6344 0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
6345 0x00000000, 0x8f620cf4, 0x00501024, 0x10400015, 0x00000000, 0x08004283,
6346 0x00000000, 0x3c030001, 0x94630f68, 0x34420624, 0x3c108000, 0x00621825,
6347 0x3c028000, 0xaf630cec, 0xaf620cf4, 0x8f641008, 0x00901024, 0x14400003,
6348 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7,
6349 0x00000000, 0x3c010001, 0x080042cf, 0xa4200f5e, 0x3c020001, 0x94420f5c,
6350 0x00021400, 0x00c21025, 0xaf620ce8, 0x3c020001, 0x90420f57, 0x10400009,
6351 0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624, 0x0000d021, 0x00431025,
6352 0xaf620cec, 0x080042c1, 0x3c108000, 0x3c020001, 0x94420f68, 0x3c030008,
6353 0x34630604, 0x00431025, 0xaf620cec, 0x3c020001, 0x94420f5e, 0x00451021,
6354 0x3c010001, 0xa4220f5e, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
6355 0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
6356 0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x8fbf0014,
6357 0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000, 0x27bdffe0, 0x3c040001,
6358 0x24840ec0, 0x00002821, 0x00003021, 0x00003821, 0xafbf0018, 0xafa00010,
6359 0x0c004378, 0xafa00014, 0x0000d021, 0x24020130, 0xaf625000, 0x3c010001,
6360 0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018, 0x03e00008, 0x27bd0020,
6361 0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010, 0xaf60680c, 0x8f626804,
6362 0x34420082, 0xaf626804, 0x8f634000, 0x24020b50, 0x3c010001, 0xac220f20,
6363 0x24020b78, 0x3c010001, 0xac220f30, 0x34630002, 0xaf634000, 0x0c004315,
6364 0x00808021, 0x3c010001, 0xa0220f34, 0x304200ff, 0x24030002, 0x14430005,
6365 0x00000000, 0x3c020001, 0x8c420f20, 0x08004308, 0xac5000c0, 0x3c020001,
6366 0x8c420f20, 0xac5000bc, 0x8f624434, 0x8f634438, 0x8f644410, 0x3c010001,
6367 0xac220f28, 0x3c010001, 0xac230f38, 0x3c010001, 0xac240f24, 0x8fbf0014,
6368 0x8fb00010, 0x03e00008, 0x27bd0018, 0x03e00008, 0x24020001, 0x27bdfff8,
6369 0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe, 0x00000000,
6370 0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008, 0x27bd0008,
6371 0x8f634450, 0x3c020001, 0x8c420f28, 0x00031c02, 0x0043102b, 0x14400008,
6372 0x3c038000, 0x3c040001, 0x8c840f38, 0x8f624450, 0x00021c02, 0x0083102b,
6373 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024, 0x1440fffd,
6374 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff, 0x2442e000,
6375 0x2c422001, 0x14400003, 0x3c024000, 0x08004347, 0x2402ffff, 0x00822025,
6376 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021, 0x03e00008,
6377 0x00000000, 0x8f624450, 0x3c030001, 0x8c630f24, 0x08004350, 0x3042ffff,
6378 0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000, 0x03e00008,
6379 0x00000000, 0x27bdffe0, 0x00802821, 0x3c040001, 0x24840ed0, 0x00003021,
6380 0x00003821, 0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0800435f,
6381 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x3c020001, 0x3442d600,
6382 0x3c030001, 0x3463d600, 0x3c040001, 0x3484ddff, 0x3c010001, 0xac220f40,
6383 0x24020040, 0x3c010001, 0xac220f44, 0x3c010001, 0xac200f3c, 0xac600000,
6384 0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
6385 0x00804821, 0x8faa0010, 0x3c020001, 0x8c420f3c, 0x3c040001, 0x8c840f44,
6386 0x8fab0014, 0x24430001, 0x0044102b, 0x3c010001, 0xac230f3c, 0x14400003,
6387 0x00004021, 0x3c010001, 0xac200f3c, 0x3c020001, 0x8c420f3c, 0x3c030001,
6388 0x8c630f40, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
6389 0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020001, 0x8c420f3c,
6390 0x3c030001, 0x8c630f40, 0x8f64680c, 0x00021140, 0x00431021, 0xac440008,
6391 0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
6392 0x00000000, 0x00000000, 0x00000000,
6395 static const u32 tg3Tso5FwRodata[(TG3_TSO5_FW_RODATA_LEN / 4) + 1] = {
6396 0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
6397 0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x00000000, 0x00000000,
6398 0x73746b6f, 0x66666c64, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
6399 0x00000000, 0x00000000, 0x00000000,
6402 static const u32 tg3Tso5FwData[(TG3_TSO5_FW_DATA_LEN / 4) + 1] = {
6403 0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x322e3000, 0x00000000,
6404 0x00000000, 0x00000000, 0x00000000,
6407 /* tp->lock is held. */
6408 static int tg3_load_tso_firmware(struct tg3 *tp)
6410 struct fw_info info;
6411 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
6414 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6417 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6418 info.text_base = TG3_TSO5_FW_TEXT_ADDR;
6419 info.text_len = TG3_TSO5_FW_TEXT_LEN;
6420 info.text_data = &tg3Tso5FwText[0];
6421 info.rodata_base = TG3_TSO5_FW_RODATA_ADDR;
6422 info.rodata_len = TG3_TSO5_FW_RODATA_LEN;
6423 info.rodata_data = &tg3Tso5FwRodata[0];
6424 info.data_base = TG3_TSO5_FW_DATA_ADDR;
6425 info.data_len = TG3_TSO5_FW_DATA_LEN;
6426 info.data_data = &tg3Tso5FwData[0];
6427 cpu_base = RX_CPU_BASE;
6428 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
6429 cpu_scratch_size = (info.text_len +
6432 TG3_TSO5_FW_SBSS_LEN +
6433 TG3_TSO5_FW_BSS_LEN);
6435 info.text_base = TG3_TSO_FW_TEXT_ADDR;
6436 info.text_len = TG3_TSO_FW_TEXT_LEN;
6437 info.text_data = &tg3TsoFwText[0];
6438 info.rodata_base = TG3_TSO_FW_RODATA_ADDR;
6439 info.rodata_len = TG3_TSO_FW_RODATA_LEN;
6440 info.rodata_data = &tg3TsoFwRodata[0];
6441 info.data_base = TG3_TSO_FW_DATA_ADDR;
6442 info.data_len = TG3_TSO_FW_DATA_LEN;
6443 info.data_data = &tg3TsoFwData[0];
6444 cpu_base = TX_CPU_BASE;
6445 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
6446 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
6449 err = tg3_load_firmware_cpu(tp, cpu_base,
6450 cpu_scratch_base, cpu_scratch_size,
6455 /* Now startup the cpu. */
6456 tw32(cpu_base + CPU_STATE, 0xffffffff);
6457 tw32_f(cpu_base + CPU_PC, info.text_base);
6459 for (i = 0; i < 5; i++) {
6460 if (tr32(cpu_base + CPU_PC) == info.text_base)
6462 tw32(cpu_base + CPU_STATE, 0xffffffff);
6463 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
6464 tw32_f(cpu_base + CPU_PC, info.text_base);
6468 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
6469 "to set CPU PC, is %08x should be %08x\n",
6470 tp->dev->name, tr32(cpu_base + CPU_PC),
6474 tw32(cpu_base + CPU_STATE, 0xffffffff);
6475 tw32_f(cpu_base + CPU_MODE, 0x00000000);
6480 /* tp->lock is held. */
6481 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
6483 u32 addr_high, addr_low;
6486 addr_high = ((tp->dev->dev_addr[0] << 8) |
6487 tp->dev->dev_addr[1]);
6488 addr_low = ((tp->dev->dev_addr[2] << 24) |
6489 (tp->dev->dev_addr[3] << 16) |
6490 (tp->dev->dev_addr[4] << 8) |
6491 (tp->dev->dev_addr[5] << 0));
6492 for (i = 0; i < 4; i++) {
6493 if (i == 1 && skip_mac_1)
6495 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
6496 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
6499 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
6500 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
6501 for (i = 0; i < 12; i++) {
6502 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
6503 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
6507 addr_high = (tp->dev->dev_addr[0] +
6508 tp->dev->dev_addr[1] +
6509 tp->dev->dev_addr[2] +
6510 tp->dev->dev_addr[3] +
6511 tp->dev->dev_addr[4] +
6512 tp->dev->dev_addr[5]) &
6513 TX_BACKOFF_SEED_MASK;
6514 tw32(MAC_TX_BACKOFF_SEED, addr_high);
6517 static int tg3_set_mac_addr(struct net_device *dev, void *p)
6519 struct tg3 *tp = netdev_priv(dev);
6520 struct sockaddr *addr = p;
6521 int err = 0, skip_mac_1 = 0;
6523 if (!is_valid_ether_addr(addr->sa_data))
6526 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
6528 if (!netif_running(dev))
6531 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6532 u32 addr0_high, addr0_low, addr1_high, addr1_low;
6534 addr0_high = tr32(MAC_ADDR_0_HIGH);
6535 addr0_low = tr32(MAC_ADDR_0_LOW);
6536 addr1_high = tr32(MAC_ADDR_1_HIGH);
6537 addr1_low = tr32(MAC_ADDR_1_LOW);
6539 /* Skip MAC addr 1 if ASF is using it. */
6540 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
6541 !(addr1_high == 0 && addr1_low == 0))
6544 spin_lock_bh(&tp->lock);
6545 __tg3_set_mac_addr(tp, skip_mac_1);
6546 spin_unlock_bh(&tp->lock);
6551 /* tp->lock is held. */
6552 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
6553 dma_addr_t mapping, u32 maxlen_flags,
6557 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
6558 ((u64) mapping >> 32));
6560 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
6561 ((u64) mapping & 0xffffffff));
6563 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
6566 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6568 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
6572 static void __tg3_set_rx_mode(struct net_device *);
6573 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
6575 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
6576 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
6577 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
6578 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
6579 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6580 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
6581 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
6583 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
6584 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
6585 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6586 u32 val = ec->stats_block_coalesce_usecs;
6588 if (!netif_carrier_ok(tp->dev))
6591 tw32(HOSTCC_STAT_COAL_TICKS, val);
6595 /* tp->lock is held. */
6596 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
6598 u32 val, rdmac_mode;
6601 tg3_disable_ints(tp);
6605 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
6607 if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
6608 tg3_abort_hw(tp, 1);
6614 err = tg3_chip_reset(tp);
6618 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
6620 if (tp->pci_chip_rev_id == CHIPREV_ID_5784_A0 ||
6621 tp->pci_chip_rev_id == CHIPREV_ID_5784_A1) {
6622 val = tr32(TG3_CPMU_CTRL);
6623 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
6624 tw32(TG3_CPMU_CTRL, val);
6626 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
6627 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
6628 val |= CPMU_LSPD_10MB_MACCLK_6_25;
6629 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
6631 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
6632 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
6633 val |= CPMU_LNK_AWARE_MACCLK_6_25;
6634 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
6636 val = tr32(TG3_CPMU_HST_ACC);
6637 val &= ~CPMU_HST_ACC_MACCLK_MASK;
6638 val |= CPMU_HST_ACC_MACCLK_6_25;
6639 tw32(TG3_CPMU_HST_ACC, val);
6642 /* This works around an issue with Athlon chipsets on
6643 * B3 tigon3 silicon. This bit has no effect on any
6644 * other revision. But do not set this on PCI Express
6645 * chips and don't even touch the clocks if the CPMU is present.
6647 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
6648 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
6649 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
6650 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6653 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6654 (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
6655 val = tr32(TG3PCI_PCISTATE);
6656 val |= PCISTATE_RETRY_SAME_DMA;
6657 tw32(TG3PCI_PCISTATE, val);
6660 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
6661 /* Allow reads and writes to the
6662 * APE register and memory space.
6664 val = tr32(TG3PCI_PCISTATE);
6665 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6666 PCISTATE_ALLOW_APE_SHMEM_WR;
6667 tw32(TG3PCI_PCISTATE, val);
6670 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
6671 /* Enable some hw fixes. */
6672 val = tr32(TG3PCI_MSI_DATA);
6673 val |= (1 << 26) | (1 << 28) | (1 << 29);
6674 tw32(TG3PCI_MSI_DATA, val);
6677 /* Descriptor ring init may make accesses to the
6678 * NIC SRAM area to setup the TX descriptors, so we
6679 * can only do this after the hardware has been
6680 * successfully reset.
6682 err = tg3_init_rings(tp);
6686 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
6687 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
6688 /* This value is determined during the probe time DMA
6689 * engine test, tg3_test_dma.
6691 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
6694 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
6695 GRC_MODE_4X_NIC_SEND_RINGS |
6696 GRC_MODE_NO_TX_PHDR_CSUM |
6697 GRC_MODE_NO_RX_PHDR_CSUM);
6698 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
6700 /* Pseudo-header checksum is done by hardware logic and not
6701 * the offload processers, so make the chip do the pseudo-
6702 * header checksums on receive. For transmit it is more
6703 * convenient to do the pseudo-header checksum in software
6704 * as Linux does that on transmit for us in all cases.
6706 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
6710 (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
6712 /* Setup the timer prescalar register. Clock is always 66Mhz. */
6713 val = tr32(GRC_MISC_CFG);
6715 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
6716 tw32(GRC_MISC_CFG, val);
6718 /* Initialize MBUF/DESC pool. */
6719 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
6721 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
6722 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
6723 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
6724 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
6726 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
6727 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
6728 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
6730 else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
6733 fw_len = (TG3_TSO5_FW_TEXT_LEN +
6734 TG3_TSO5_FW_RODATA_LEN +
6735 TG3_TSO5_FW_DATA_LEN +
6736 TG3_TSO5_FW_SBSS_LEN +
6737 TG3_TSO5_FW_BSS_LEN);
6738 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
6739 tw32(BUFMGR_MB_POOL_ADDR,
6740 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
6741 tw32(BUFMGR_MB_POOL_SIZE,
6742 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
6745 if (tp->dev->mtu <= ETH_DATA_LEN) {
6746 tw32(BUFMGR_MB_RDMA_LOW_WATER,
6747 tp->bufmgr_config.mbuf_read_dma_low_water);
6748 tw32(BUFMGR_MB_MACRX_LOW_WATER,
6749 tp->bufmgr_config.mbuf_mac_rx_low_water);
6750 tw32(BUFMGR_MB_HIGH_WATER,
6751 tp->bufmgr_config.mbuf_high_water);
6753 tw32(BUFMGR_MB_RDMA_LOW_WATER,
6754 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
6755 tw32(BUFMGR_MB_MACRX_LOW_WATER,
6756 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
6757 tw32(BUFMGR_MB_HIGH_WATER,
6758 tp->bufmgr_config.mbuf_high_water_jumbo);
6760 tw32(BUFMGR_DMA_LOW_WATER,
6761 tp->bufmgr_config.dma_low_water);
6762 tw32(BUFMGR_DMA_HIGH_WATER,
6763 tp->bufmgr_config.dma_high_water);
6765 tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
6766 for (i = 0; i < 2000; i++) {
6767 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
6772 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
6777 /* Setup replenish threshold. */
6778 val = tp->rx_pending / 8;
6781 else if (val > tp->rx_std_max_post)
6782 val = tp->rx_std_max_post;
6783 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6784 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
6785 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
6787 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
6788 val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
6791 tw32(RCVBDI_STD_THRESH, val);
6793 /* Initialize TG3_BDINFO's at:
6794 * RCVDBDI_STD_BD: standard eth size rx ring
6795 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
6796 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
6799 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
6800 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
6801 * ring attribute flags
6802 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
6804 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
6805 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
6807 * The size of each ring is fixed in the firmware, but the location is
6810 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
6811 ((u64) tp->rx_std_mapping >> 32));
6812 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
6813 ((u64) tp->rx_std_mapping & 0xffffffff));
6814 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
6815 NIC_SRAM_RX_BUFFER_DESC);
6817 /* Don't even try to program the JUMBO/MINI buffer descriptor
6820 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6821 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
6822 RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT);
6824 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
6825 RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
6827 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
6828 BDINFO_FLAGS_DISABLED);
6830 /* Setup replenish threshold. */
6831 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
6833 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
6834 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
6835 ((u64) tp->rx_jumbo_mapping >> 32));
6836 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
6837 ((u64) tp->rx_jumbo_mapping & 0xffffffff));
6838 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
6839 RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
6840 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
6841 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
6843 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
6844 BDINFO_FLAGS_DISABLED);
6849 /* There is only one send ring on 5705/5750, no need to explicitly
6850 * disable the others.
6852 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6853 /* Clear out send RCB ring in SRAM. */
6854 for (i = NIC_SRAM_SEND_RCB; i < NIC_SRAM_RCV_RET_RCB; i += TG3_BDINFO_SIZE)
6855 tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
6856 BDINFO_FLAGS_DISABLED);
6861 tw32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
6862 tw32_tx_mbox(MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
6864 tg3_set_bdinfo(tp, NIC_SRAM_SEND_RCB,
6865 tp->tx_desc_mapping,
6866 (TG3_TX_RING_SIZE <<
6867 BDINFO_FLAGS_MAXLEN_SHIFT),
6868 NIC_SRAM_TX_BUFFER_DESC);
6870 /* There is only one receive return ring on 5705/5750, no need
6871 * to explicitly disable the others.
6873 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6874 for (i = NIC_SRAM_RCV_RET_RCB; i < NIC_SRAM_STATS_BLK;
6875 i += TG3_BDINFO_SIZE) {
6876 tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
6877 BDINFO_FLAGS_DISABLED);
6882 tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, 0);
6884 tg3_set_bdinfo(tp, NIC_SRAM_RCV_RET_RCB,
6886 (TG3_RX_RCB_RING_SIZE(tp) <<
6887 BDINFO_FLAGS_MAXLEN_SHIFT),
6890 tp->rx_std_ptr = tp->rx_pending;
6891 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
6894 tp->rx_jumbo_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
6895 tp->rx_jumbo_pending : 0;
6896 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
6899 /* Initialize MAC address and backoff seed. */
6900 __tg3_set_mac_addr(tp, 0);
6902 /* MTU + ethernet header + FCS + optional VLAN tag */
6903 tw32(MAC_RX_MTU_SIZE, tp->dev->mtu + ETH_HLEN + 8);
6905 /* The slot time is changed by tg3_setup_phy if we
6906 * run at gigabit with half duplex.
6908 tw32(MAC_TX_LENGTHS,
6909 (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
6910 (6 << TX_LENGTHS_IPG_SHIFT) |
6911 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
6913 /* Receive rules. */
6914 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
6915 tw32(RCVLPC_CONFIG, 0x0181);
6917 /* Calculate RDMAC_MODE setting early, we need it to determine
6918 * the RCVLPC_STATE_ENABLE mask.
6920 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
6921 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
6922 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
6923 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
6924 RDMAC_MODE_LNGREAD_ENAB);
6926 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784)
6927 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
6928 RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
6929 RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
6931 /* If statement applies to 5705 and 5750 PCI devices only */
6932 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
6933 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
6934 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
6935 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
6936 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6937 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
6938 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
6939 !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
6940 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
6944 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6945 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
6947 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6948 rdmac_mode |= (1 << 27);
6950 /* Receive/send statistics. */
6951 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
6952 val = tr32(RCVLPC_STATS_ENABLE);
6953 val &= ~RCVLPC_STATSENAB_DACK_FIX;
6954 tw32(RCVLPC_STATS_ENABLE, val);
6955 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
6956 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
6957 val = tr32(RCVLPC_STATS_ENABLE);
6958 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
6959 tw32(RCVLPC_STATS_ENABLE, val);
6961 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
6963 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
6964 tw32(SNDDATAI_STATSENAB, 0xffffff);
6965 tw32(SNDDATAI_STATSCTRL,
6966 (SNDDATAI_SCTRL_ENABLE |
6967 SNDDATAI_SCTRL_FASTUPD));
6969 /* Setup host coalescing engine. */
6970 tw32(HOSTCC_MODE, 0);
6971 for (i = 0; i < 2000; i++) {
6972 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
6977 __tg3_set_coalesce(tp, &tp->coal);
6979 /* set status block DMA address */
6980 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
6981 ((u64) tp->status_mapping >> 32));
6982 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
6983 ((u64) tp->status_mapping & 0xffffffff));
6985 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6986 /* Status/statistics block address. See tg3_timer,
6987 * the tg3_periodic_fetch_stats call there, and
6988 * tg3_get_stats to see how this works for 5705/5750 chips.
6990 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
6991 ((u64) tp->stats_mapping >> 32));
6992 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
6993 ((u64) tp->stats_mapping & 0xffffffff));
6994 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
6995 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
6998 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
7000 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
7001 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
7002 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7003 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
7005 /* Clear statistics/status block in chip, and status block in ram. */
7006 for (i = NIC_SRAM_STATS_BLK;
7007 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
7009 tg3_write_mem(tp, i, 0);
7012 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
7014 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
7015 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
7016 /* reset to prevent losing 1st rx packet intermittently */
7017 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7021 tp->mac_mode = MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
7022 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
7023 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7024 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7025 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
7026 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
7027 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
7030 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
7031 * If TG3_FLG2_IS_NIC is zero, we should read the
7032 * register to preserve the GPIO settings for LOMs. The GPIOs,
7033 * whether used as inputs or outputs, are set by boot code after
7036 if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
7039 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
7040 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
7041 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
7043 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
7044 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
7045 GRC_LCLCTRL_GPIO_OUTPUT3;
7047 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
7048 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
7050 tp->grc_local_ctrl &= ~gpio_mask;
7051 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
7053 /* GPIO1 must be driven high for eeprom write protect */
7054 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
7055 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
7056 GRC_LCLCTRL_GPIO_OUTPUT1);
7058 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7061 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0);
7064 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7065 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
7069 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
7070 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
7071 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
7072 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
7073 WDMAC_MODE_LNGREAD_ENAB);
7075 /* If statement applies to 5705 and 5750 PCI devices only */
7076 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7077 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7078 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
7079 if ((tp->tg3_flags & TG3_FLG2_TSO_CAPABLE) &&
7080 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
7081 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
7083 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7084 !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
7085 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
7086 val |= WDMAC_MODE_RX_ACCEL;
7090 /* Enable host coalescing bug fix */
7091 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) ||
7092 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787) ||
7093 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784) ||
7094 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761))
7097 tw32_f(WDMAC_MODE, val);
7100 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
7103 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7105 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
7106 pcix_cmd &= ~PCI_X_CMD_MAX_READ;
7107 pcix_cmd |= PCI_X_CMD_READ_2K;
7108 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
7109 pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
7110 pcix_cmd |= PCI_X_CMD_READ_2K;
7112 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7116 tw32_f(RDMAC_MODE, rdmac_mode);
7119 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
7120 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7121 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
7123 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
7125 SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
7127 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
7129 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
7130 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
7131 tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
7132 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
7133 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7134 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
7135 tw32(SNDBDI_MODE, SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE);
7136 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
7138 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
7139 err = tg3_load_5701_a0_firmware_fix(tp);
7144 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7145 err = tg3_load_tso_firmware(tp);
7150 tp->tx_mode = TX_MODE_ENABLE;
7151 tw32_f(MAC_TX_MODE, tp->tx_mode);
7154 tp->rx_mode = RX_MODE_ENABLE;
7155 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
7156 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
7157 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
7159 tw32_f(MAC_RX_MODE, tp->rx_mode);
7162 if (tp->link_config.phy_is_low_power) {
7163 tp->link_config.phy_is_low_power = 0;
7164 tp->link_config.speed = tp->link_config.orig_speed;
7165 tp->link_config.duplex = tp->link_config.orig_duplex;
7166 tp->link_config.autoneg = tp->link_config.orig_autoneg;
7169 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
7170 tw32_f(MAC_MI_MODE, tp->mi_mode);
7173 tw32(MAC_LED_CTRL, tp->led_ctrl);
7175 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
7176 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
7177 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7180 tw32_f(MAC_RX_MODE, tp->rx_mode);
7183 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
7184 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
7185 !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
7186 /* Set drive transmission level to 1.2V */
7187 /* only if the signal pre-emphasis bit is not set */
7188 val = tr32(MAC_SERDES_CFG);
7191 tw32(MAC_SERDES_CFG, val);
7193 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
7194 tw32(MAC_SERDES_CFG, 0x616000);
7197 /* Prevent chip from dropping frames when flow control
7200 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
7202 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
7203 (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
7204 /* Use hardware link auto-negotiation */
7205 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
7208 if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
7209 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
7212 tmp = tr32(SERDES_RX_CTRL);
7213 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
7214 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
7215 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
7216 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7219 err = tg3_setup_phy(tp, 0);
7223 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7224 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906) {
7227 /* Clear CRC stats. */
7228 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
7229 tg3_writephy(tp, MII_TG3_TEST1,
7230 tmp | MII_TG3_TEST1_CRC_EN);
7231 tg3_readphy(tp, 0x14, &tmp);
7235 __tg3_set_rx_mode(tp->dev);
7237 /* Initialize receive rules. */
7238 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
7239 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
7240 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
7241 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
7243 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7244 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
7248 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
7252 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
7254 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
7256 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
7258 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
7260 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
7262 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
7264 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
7266 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
7268 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
7270 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
7272 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
7274 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
7276 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
7278 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
7286 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7287 /* Write our heartbeat update interval to APE. */
7288 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
7289 APE_HOST_HEARTBEAT_INT_DISABLE);
7291 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
7296 /* Called at device open time to get the chip ready for
7297 * packet processing. Invoked with tp->lock held.
7299 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
7303 /* Force the chip into D0. */
7304 err = tg3_set_power_state(tp, PCI_D0);
7308 tg3_switch_clocks(tp);
7310 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
7312 err = tg3_reset_hw(tp, reset_phy);
7318 #define TG3_STAT_ADD32(PSTAT, REG) \
7319 do { u32 __val = tr32(REG); \
7320 (PSTAT)->low += __val; \
7321 if ((PSTAT)->low < __val) \
7322 (PSTAT)->high += 1; \
7325 static void tg3_periodic_fetch_stats(struct tg3 *tp)
7327 struct tg3_hw_stats *sp = tp->hw_stats;
7329 if (!netif_carrier_ok(tp->dev))
7332 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
7333 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
7334 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
7335 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
7336 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
7337 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
7338 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
7339 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
7340 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
7341 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
7342 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
7343 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
7344 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
7346 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
7347 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
7348 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
7349 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
7350 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
7351 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
7352 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
7353 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
7354 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
7355 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
7356 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
7357 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
7358 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
7359 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
7361 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
7362 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
7363 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
7366 static void tg3_timer(unsigned long __opaque)
7368 struct tg3 *tp = (struct tg3 *) __opaque;
7373 spin_lock(&tp->lock);
7375 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
7376 /* All of this garbage is because when using non-tagged
7377 * IRQ status the mailbox/status_block protocol the chip
7378 * uses with the cpu is race prone.
7380 if (tp->hw_status->status & SD_STATUS_UPDATED) {
7381 tw32(GRC_LOCAL_CTRL,
7382 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
7384 tw32(HOSTCC_MODE, tp->coalesce_mode |
7385 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
7388 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
7389 tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
7390 spin_unlock(&tp->lock);
7391 schedule_work(&tp->reset_task);
7396 /* This part only runs once per second. */
7397 if (!--tp->timer_counter) {
7398 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7399 tg3_periodic_fetch_stats(tp);
7401 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
7405 mac_stat = tr32(MAC_STATUS);
7408 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
7409 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
7411 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
7415 tg3_setup_phy(tp, 0);
7416 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
7417 u32 mac_stat = tr32(MAC_STATUS);
7420 if (netif_carrier_ok(tp->dev) &&
7421 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
7424 if (! netif_carrier_ok(tp->dev) &&
7425 (mac_stat & (MAC_STATUS_PCS_SYNCED |
7426 MAC_STATUS_SIGNAL_DET))) {
7430 if (!tp->serdes_counter) {
7433 ~MAC_MODE_PORT_MODE_MASK));
7435 tw32_f(MAC_MODE, tp->mac_mode);
7438 tg3_setup_phy(tp, 0);
7440 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
7441 tg3_serdes_parallel_detect(tp);
7443 tp->timer_counter = tp->timer_multiplier;
7446 /* Heartbeat is only sent once every 2 seconds.
7448 * The heartbeat is to tell the ASF firmware that the host
7449 * driver is still alive. In the event that the OS crashes,
7450 * ASF needs to reset the hardware to free up the FIFO space
7451 * that may be filled with rx packets destined for the host.
7452 * If the FIFO is full, ASF will no longer function properly.
7454 * Unintended resets have been reported on real time kernels
7455 * where the timer doesn't run on time. Netpoll will also have
7458 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
7459 * to check the ring condition when the heartbeat is expiring
7460 * before doing the reset. This will prevent most unintended
7463 if (!--tp->asf_counter) {
7464 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
7467 tg3_wait_for_event_ack(tp);
7469 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
7470 FWCMD_NICDRV_ALIVE3);
7471 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
7472 /* 5 seconds timeout */
7473 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
7474 val = tr32(GRC_RX_CPU_EVENT);
7475 val |= GRC_RX_CPU_DRIVER_EVENT;
7476 tw32_f(GRC_RX_CPU_EVENT, val);
7478 tp->asf_counter = tp->asf_multiplier;
7481 spin_unlock(&tp->lock);
7484 tp->timer.expires = jiffies + tp->timer_offset;
7485 add_timer(&tp->timer);
7488 static int tg3_request_irq(struct tg3 *tp)
7491 unsigned long flags;
7492 struct net_device *dev = tp->dev;
7494 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7496 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
7498 flags = IRQF_SAMPLE_RANDOM;
7501 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
7502 fn = tg3_interrupt_tagged;
7503 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
7505 return (request_irq(tp->pdev->irq, fn, flags, dev->name, dev));
7508 static int tg3_test_interrupt(struct tg3 *tp)
7510 struct net_device *dev = tp->dev;
7511 int err, i, intr_ok = 0;
7513 if (!netif_running(dev))
7516 tg3_disable_ints(tp);
7518 free_irq(tp->pdev->irq, dev);
7520 err = request_irq(tp->pdev->irq, tg3_test_isr,
7521 IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, dev);
7525 tp->hw_status->status &= ~SD_STATUS_UPDATED;
7526 tg3_enable_ints(tp);
7528 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
7531 for (i = 0; i < 5; i++) {
7532 u32 int_mbox, misc_host_ctrl;
7534 int_mbox = tr32_mailbox(MAILBOX_INTERRUPT_0 +
7536 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
7538 if ((int_mbox != 0) ||
7539 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
7547 tg3_disable_ints(tp);
7549 free_irq(tp->pdev->irq, dev);
7551 err = tg3_request_irq(tp);
7562 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
7563 * successfully restored
7565 static int tg3_test_msi(struct tg3 *tp)
7567 struct net_device *dev = tp->dev;
7571 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
7574 /* Turn off SERR reporting in case MSI terminates with Master
7577 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
7578 pci_write_config_word(tp->pdev, PCI_COMMAND,
7579 pci_cmd & ~PCI_COMMAND_SERR);
7581 err = tg3_test_interrupt(tp);
7583 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
7588 /* other failures */
7592 /* MSI test failed, go back to INTx mode */
7593 printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
7594 "switching to INTx mode. Please report this failure to "
7595 "the PCI maintainer and include system chipset information.\n",
7598 free_irq(tp->pdev->irq, dev);
7599 pci_disable_msi(tp->pdev);
7601 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7603 err = tg3_request_irq(tp);
7607 /* Need to reset the chip because the MSI cycle may have terminated
7608 * with Master Abort.
7610 tg3_full_lock(tp, 1);
7612 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7613 err = tg3_init_hw(tp, 1);
7615 tg3_full_unlock(tp);
7618 free_irq(tp->pdev->irq, dev);
7623 static int tg3_open(struct net_device *dev)
7625 struct tg3 *tp = netdev_priv(dev);
7628 netif_carrier_off(tp->dev);
7630 tg3_full_lock(tp, 0);
7632 err = tg3_set_power_state(tp, PCI_D0);
7634 tg3_full_unlock(tp);
7638 tg3_disable_ints(tp);
7639 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
7641 tg3_full_unlock(tp);
7643 /* The placement of this call is tied
7644 * to the setup and use of Host TX descriptors.
7646 err = tg3_alloc_consistent(tp);
7650 if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) {
7651 /* All MSI supporting chips should support tagged
7652 * status. Assert that this is the case.
7654 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
7655 printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
7656 "Not using MSI.\n", tp->dev->name);
7657 } else if (pci_enable_msi(tp->pdev) == 0) {
7660 msi_mode = tr32(MSGINT_MODE);
7661 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
7662 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
7665 err = tg3_request_irq(tp);
7668 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7669 pci_disable_msi(tp->pdev);
7670 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7672 tg3_free_consistent(tp);
7676 napi_enable(&tp->napi);
7678 tg3_full_lock(tp, 0);
7680 err = tg3_init_hw(tp, 1);
7682 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7685 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
7686 tp->timer_offset = HZ;
7688 tp->timer_offset = HZ / 10;
7690 BUG_ON(tp->timer_offset > HZ);
7691 tp->timer_counter = tp->timer_multiplier =
7692 (HZ / tp->timer_offset);
7693 tp->asf_counter = tp->asf_multiplier =
7694 ((HZ / tp->timer_offset) * 2);
7696 init_timer(&tp->timer);
7697 tp->timer.expires = jiffies + tp->timer_offset;
7698 tp->timer.data = (unsigned long) tp;
7699 tp->timer.function = tg3_timer;
7702 tg3_full_unlock(tp);
7705 napi_disable(&tp->napi);
7706 free_irq(tp->pdev->irq, dev);
7707 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7708 pci_disable_msi(tp->pdev);
7709 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7711 tg3_free_consistent(tp);
7715 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7716 err = tg3_test_msi(tp);
7719 tg3_full_lock(tp, 0);
7721 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7722 pci_disable_msi(tp->pdev);
7723 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7725 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7727 tg3_free_consistent(tp);
7729 tg3_full_unlock(tp);
7731 napi_disable(&tp->napi);
7736 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7737 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI) {
7738 u32 val = tr32(PCIE_TRANSACTION_CFG);
7740 tw32(PCIE_TRANSACTION_CFG,
7741 val | PCIE_TRANS_CFG_1SHOT_MSI);
7746 tg3_full_lock(tp, 0);
7748 add_timer(&tp->timer);
7749 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
7750 tg3_enable_ints(tp);
7752 tg3_full_unlock(tp);
7754 netif_start_queue(dev);
7760 /*static*/ void tg3_dump_state(struct tg3 *tp)
7762 u32 val32, val32_2, val32_3, val32_4, val32_5;
7766 pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
7767 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
7768 printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
7772 printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
7773 tr32(MAC_MODE), tr32(MAC_STATUS));
7774 printk(" MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
7775 tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
7776 printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
7777 tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
7778 printk(" MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
7779 tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
7781 /* Send data initiator control block */
7782 printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
7783 tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
7784 printk(" SNDDATAI_STATSCTRL[%08x]\n",
7785 tr32(SNDDATAI_STATSCTRL));
7787 /* Send data completion control block */
7788 printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
7790 /* Send BD ring selector block */
7791 printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
7792 tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
7794 /* Send BD initiator control block */
7795 printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
7796 tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
7798 /* Send BD completion control block */
7799 printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
7801 /* Receive list placement control block */
7802 printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
7803 tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
7804 printk(" RCVLPC_STATSCTRL[%08x]\n",
7805 tr32(RCVLPC_STATSCTRL));
7807 /* Receive data and receive BD initiator control block */
7808 printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
7809 tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
7811 /* Receive data completion control block */
7812 printk("DEBUG: RCVDCC_MODE[%08x]\n",
7815 /* Receive BD initiator control block */
7816 printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
7817 tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
7819 /* Receive BD completion control block */
7820 printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
7821 tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
7823 /* Receive list selector control block */
7824 printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
7825 tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
7827 /* Mbuf cluster free block */
7828 printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
7829 tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
7831 /* Host coalescing control block */
7832 printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
7833 tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
7834 printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
7835 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
7836 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
7837 printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
7838 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
7839 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
7840 printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
7841 tr32(HOSTCC_STATS_BLK_NIC_ADDR));
7842 printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
7843 tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
7845 /* Memory arbiter control block */
7846 printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
7847 tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
7849 /* Buffer manager control block */
7850 printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
7851 tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
7852 printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
7853 tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
7854 printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
7855 "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
7856 tr32(BUFMGR_DMA_DESC_POOL_ADDR),
7857 tr32(BUFMGR_DMA_DESC_POOL_SIZE));
7859 /* Read DMA control block */
7860 printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
7861 tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
7863 /* Write DMA control block */
7864 printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
7865 tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
7867 /* DMA completion block */
7868 printk("DEBUG: DMAC_MODE[%08x]\n",
7872 printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
7873 tr32(GRC_MODE), tr32(GRC_MISC_CFG));
7874 printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
7875 tr32(GRC_LOCAL_CTRL));
7878 printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
7879 tr32(RCVDBDI_JUMBO_BD + 0x0),
7880 tr32(RCVDBDI_JUMBO_BD + 0x4),
7881 tr32(RCVDBDI_JUMBO_BD + 0x8),
7882 tr32(RCVDBDI_JUMBO_BD + 0xc));
7883 printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
7884 tr32(RCVDBDI_STD_BD + 0x0),
7885 tr32(RCVDBDI_STD_BD + 0x4),
7886 tr32(RCVDBDI_STD_BD + 0x8),
7887 tr32(RCVDBDI_STD_BD + 0xc));
7888 printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
7889 tr32(RCVDBDI_MINI_BD + 0x0),
7890 tr32(RCVDBDI_MINI_BD + 0x4),
7891 tr32(RCVDBDI_MINI_BD + 0x8),
7892 tr32(RCVDBDI_MINI_BD + 0xc));
7894 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
7895 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
7896 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
7897 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
7898 printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
7899 val32, val32_2, val32_3, val32_4);
7901 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
7902 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
7903 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
7904 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
7905 printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
7906 val32, val32_2, val32_3, val32_4);
7908 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
7909 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
7910 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
7911 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
7912 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
7913 printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
7914 val32, val32_2, val32_3, val32_4, val32_5);
7916 /* SW status block */
7917 printk("DEBUG: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
7918 tp->hw_status->status,
7919 tp->hw_status->status_tag,
7920 tp->hw_status->rx_jumbo_consumer,
7921 tp->hw_status->rx_consumer,
7922 tp->hw_status->rx_mini_consumer,
7923 tp->hw_status->idx[0].rx_producer,
7924 tp->hw_status->idx[0].tx_consumer);
7926 /* SW statistics block */
7927 printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
7928 ((u32 *)tp->hw_stats)[0],
7929 ((u32 *)tp->hw_stats)[1],
7930 ((u32 *)tp->hw_stats)[2],
7931 ((u32 *)tp->hw_stats)[3]);
7934 printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
7935 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
7936 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
7937 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
7938 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
7940 /* NIC side send descriptors. */
7941 for (i = 0; i < 6; i++) {
7944 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
7945 + (i * sizeof(struct tg3_tx_buffer_desc));
7946 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
7948 readl(txd + 0x0), readl(txd + 0x4),
7949 readl(txd + 0x8), readl(txd + 0xc));
7952 /* NIC side RX descriptors. */
7953 for (i = 0; i < 6; i++) {
7956 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
7957 + (i * sizeof(struct tg3_rx_buffer_desc));
7958 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
7960 readl(rxd + 0x0), readl(rxd + 0x4),
7961 readl(rxd + 0x8), readl(rxd + 0xc));
7962 rxd += (4 * sizeof(u32));
7963 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
7965 readl(rxd + 0x0), readl(rxd + 0x4),
7966 readl(rxd + 0x8), readl(rxd + 0xc));
7969 for (i = 0; i < 6; i++) {
7972 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
7973 + (i * sizeof(struct tg3_rx_buffer_desc));
7974 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
7976 readl(rxd + 0x0), readl(rxd + 0x4),
7977 readl(rxd + 0x8), readl(rxd + 0xc));
7978 rxd += (4 * sizeof(u32));
7979 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
7981 readl(rxd + 0x0), readl(rxd + 0x4),
7982 readl(rxd + 0x8), readl(rxd + 0xc));
7987 static struct net_device_stats *tg3_get_stats(struct net_device *);
7988 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
7990 static int tg3_close(struct net_device *dev)
7992 struct tg3 *tp = netdev_priv(dev);
7994 napi_disable(&tp->napi);
7995 cancel_work_sync(&tp->reset_task);
7997 netif_stop_queue(dev);
7999 del_timer_sync(&tp->timer);
8001 tg3_full_lock(tp, 1);
8006 tg3_disable_ints(tp);
8008 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8010 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
8012 tg3_full_unlock(tp);
8014 free_irq(tp->pdev->irq, dev);
8015 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8016 pci_disable_msi(tp->pdev);
8017 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8020 memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
8021 sizeof(tp->net_stats_prev));
8022 memcpy(&tp->estats_prev, tg3_get_estats(tp),
8023 sizeof(tp->estats_prev));
8025 tg3_free_consistent(tp);
8027 tg3_set_power_state(tp, PCI_D3hot);
8029 netif_carrier_off(tp->dev);
8034 static inline unsigned long get_stat64(tg3_stat64_t *val)
8038 #if (BITS_PER_LONG == 32)
8041 ret = ((u64)val->high << 32) | ((u64)val->low);
8046 static unsigned long calc_crc_errors(struct tg3 *tp)
8048 struct tg3_hw_stats *hw_stats = tp->hw_stats;
8050 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
8051 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
8052 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
8055 spin_lock_bh(&tp->lock);
8056 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
8057 tg3_writephy(tp, MII_TG3_TEST1,
8058 val | MII_TG3_TEST1_CRC_EN);
8059 tg3_readphy(tp, 0x14, &val);
8062 spin_unlock_bh(&tp->lock);
8064 tp->phy_crc_errors += val;
8066 return tp->phy_crc_errors;
8069 return get_stat64(&hw_stats->rx_fcs_errors);
8072 #define ESTAT_ADD(member) \
8073 estats->member = old_estats->member + \
8074 get_stat64(&hw_stats->member)
8076 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
8078 struct tg3_ethtool_stats *estats = &tp->estats;
8079 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
8080 struct tg3_hw_stats *hw_stats = tp->hw_stats;
8085 ESTAT_ADD(rx_octets);
8086 ESTAT_ADD(rx_fragments);
8087 ESTAT_ADD(rx_ucast_packets);
8088 ESTAT_ADD(rx_mcast_packets);
8089 ESTAT_ADD(rx_bcast_packets);
8090 ESTAT_ADD(rx_fcs_errors);
8091 ESTAT_ADD(rx_align_errors);
8092 ESTAT_ADD(rx_xon_pause_rcvd);
8093 ESTAT_ADD(rx_xoff_pause_rcvd);
8094 ESTAT_ADD(rx_mac_ctrl_rcvd);
8095 ESTAT_ADD(rx_xoff_entered);
8096 ESTAT_ADD(rx_frame_too_long_errors);
8097 ESTAT_ADD(rx_jabbers);
8098 ESTAT_ADD(rx_undersize_packets);
8099 ESTAT_ADD(rx_in_length_errors);
8100 ESTAT_ADD(rx_out_length_errors);
8101 ESTAT_ADD(rx_64_or_less_octet_packets);
8102 ESTAT_ADD(rx_65_to_127_octet_packets);
8103 ESTAT_ADD(rx_128_to_255_octet_packets);
8104 ESTAT_ADD(rx_256_to_511_octet_packets);
8105 ESTAT_ADD(rx_512_to_1023_octet_packets);
8106 ESTAT_ADD(rx_1024_to_1522_octet_packets);
8107 ESTAT_ADD(rx_1523_to_2047_octet_packets);
8108 ESTAT_ADD(rx_2048_to_4095_octet_packets);
8109 ESTAT_ADD(rx_4096_to_8191_octet_packets);
8110 ESTAT_ADD(rx_8192_to_9022_octet_packets);
8112 ESTAT_ADD(tx_octets);
8113 ESTAT_ADD(tx_collisions);
8114 ESTAT_ADD(tx_xon_sent);
8115 ESTAT_ADD(tx_xoff_sent);
8116 ESTAT_ADD(tx_flow_control);
8117 ESTAT_ADD(tx_mac_errors);
8118 ESTAT_ADD(tx_single_collisions);
8119 ESTAT_ADD(tx_mult_collisions);
8120 ESTAT_ADD(tx_deferred);
8121 ESTAT_ADD(tx_excessive_collisions);
8122 ESTAT_ADD(tx_late_collisions);
8123 ESTAT_ADD(tx_collide_2times);
8124 ESTAT_ADD(tx_collide_3times);
8125 ESTAT_ADD(tx_collide_4times);
8126 ESTAT_ADD(tx_collide_5times);
8127 ESTAT_ADD(tx_collide_6times);
8128 ESTAT_ADD(tx_collide_7times);
8129 ESTAT_ADD(tx_collide_8times);
8130 ESTAT_ADD(tx_collide_9times);
8131 ESTAT_ADD(tx_collide_10times);
8132 ESTAT_ADD(tx_collide_11times);
8133 ESTAT_ADD(tx_collide_12times);
8134 ESTAT_ADD(tx_collide_13times);
8135 ESTAT_ADD(tx_collide_14times);
8136 ESTAT_ADD(tx_collide_15times);
8137 ESTAT_ADD(tx_ucast_packets);
8138 ESTAT_ADD(tx_mcast_packets);
8139 ESTAT_ADD(tx_bcast_packets);
8140 ESTAT_ADD(tx_carrier_sense_errors);
8141 ESTAT_ADD(tx_discards);
8142 ESTAT_ADD(tx_errors);
8144 ESTAT_ADD(dma_writeq_full);
8145 ESTAT_ADD(dma_write_prioq_full);
8146 ESTAT_ADD(rxbds_empty);
8147 ESTAT_ADD(rx_discards);
8148 ESTAT_ADD(rx_errors);
8149 ESTAT_ADD(rx_threshold_hit);
8151 ESTAT_ADD(dma_readq_full);
8152 ESTAT_ADD(dma_read_prioq_full);
8153 ESTAT_ADD(tx_comp_queue_full);
8155 ESTAT_ADD(ring_set_send_prod_index);
8156 ESTAT_ADD(ring_status_update);
8157 ESTAT_ADD(nic_irqs);
8158 ESTAT_ADD(nic_avoided_irqs);
8159 ESTAT_ADD(nic_tx_threshold_hit);
8164 static struct net_device_stats *tg3_get_stats(struct net_device *dev)
8166 struct tg3 *tp = netdev_priv(dev);
8167 struct net_device_stats *stats = &tp->net_stats;
8168 struct net_device_stats *old_stats = &tp->net_stats_prev;
8169 struct tg3_hw_stats *hw_stats = tp->hw_stats;
8174 stats->rx_packets = old_stats->rx_packets +
8175 get_stat64(&hw_stats->rx_ucast_packets) +
8176 get_stat64(&hw_stats->rx_mcast_packets) +
8177 get_stat64(&hw_stats->rx_bcast_packets);
8179 stats->tx_packets = old_stats->tx_packets +
8180 get_stat64(&hw_stats->tx_ucast_packets) +
8181 get_stat64(&hw_stats->tx_mcast_packets) +
8182 get_stat64(&hw_stats->tx_bcast_packets);
8184 stats->rx_bytes = old_stats->rx_bytes +
8185 get_stat64(&hw_stats->rx_octets);
8186 stats->tx_bytes = old_stats->tx_bytes +
8187 get_stat64(&hw_stats->tx_octets);
8189 stats->rx_errors = old_stats->rx_errors +
8190 get_stat64(&hw_stats->rx_errors);
8191 stats->tx_errors = old_stats->tx_errors +
8192 get_stat64(&hw_stats->tx_errors) +
8193 get_stat64(&hw_stats->tx_mac_errors) +
8194 get_stat64(&hw_stats->tx_carrier_sense_errors) +
8195 get_stat64(&hw_stats->tx_discards);
8197 stats->multicast = old_stats->multicast +
8198 get_stat64(&hw_stats->rx_mcast_packets);
8199 stats->collisions = old_stats->collisions +
8200 get_stat64(&hw_stats->tx_collisions);
8202 stats->rx_length_errors = old_stats->rx_length_errors +
8203 get_stat64(&hw_stats->rx_frame_too_long_errors) +
8204 get_stat64(&hw_stats->rx_undersize_packets);
8206 stats->rx_over_errors = old_stats->rx_over_errors +
8207 get_stat64(&hw_stats->rxbds_empty);
8208 stats->rx_frame_errors = old_stats->rx_frame_errors +
8209 get_stat64(&hw_stats->rx_align_errors);
8210 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
8211 get_stat64(&hw_stats->tx_discards);
8212 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
8213 get_stat64(&hw_stats->tx_carrier_sense_errors);
8215 stats->rx_crc_errors = old_stats->rx_crc_errors +
8216 calc_crc_errors(tp);
8218 stats->rx_missed_errors = old_stats->rx_missed_errors +
8219 get_stat64(&hw_stats->rx_discards);
8224 static inline u32 calc_crc(unsigned char *buf, int len)
8232 for (j = 0; j < len; j++) {
8235 for (k = 0; k < 8; k++) {
8249 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
8251 /* accept or reject all multicast frames */
8252 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
8253 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
8254 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
8255 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
8258 static void __tg3_set_rx_mode(struct net_device *dev)
8260 struct tg3 *tp = netdev_priv(dev);
8263 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
8264 RX_MODE_KEEP_VLAN_TAG);
8266 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
8269 #if TG3_VLAN_TAG_USED
8271 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
8272 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
8274 /* By definition, VLAN is disabled always in this
8277 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
8278 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
8281 if (dev->flags & IFF_PROMISC) {
8282 /* Promiscuous mode. */
8283 rx_mode |= RX_MODE_PROMISC;
8284 } else if (dev->flags & IFF_ALLMULTI) {
8285 /* Accept all multicast. */
8286 tg3_set_multi (tp, 1);
8287 } else if (dev->mc_count < 1) {
8288 /* Reject all multicast. */
8289 tg3_set_multi (tp, 0);
8291 /* Accept one or more multicast(s). */
8292 struct dev_mc_list *mclist;
8294 u32 mc_filter[4] = { 0, };
8299 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
8300 i++, mclist = mclist->next) {
8302 crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
8304 regidx = (bit & 0x60) >> 5;
8306 mc_filter[regidx] |= (1 << bit);
8309 tw32(MAC_HASH_REG_0, mc_filter[0]);
8310 tw32(MAC_HASH_REG_1, mc_filter[1]);
8311 tw32(MAC_HASH_REG_2, mc_filter[2]);
8312 tw32(MAC_HASH_REG_3, mc_filter[3]);
8315 if (rx_mode != tp->rx_mode) {
8316 tp->rx_mode = rx_mode;
8317 tw32_f(MAC_RX_MODE, rx_mode);
8322 static void tg3_set_rx_mode(struct net_device *dev)
8324 struct tg3 *tp = netdev_priv(dev);
8326 if (!netif_running(dev))
8329 tg3_full_lock(tp, 0);
8330 __tg3_set_rx_mode(dev);
8331 tg3_full_unlock(tp);
8334 #define TG3_REGDUMP_LEN (32 * 1024)
8336 static int tg3_get_regs_len(struct net_device *dev)
8338 return TG3_REGDUMP_LEN;
8341 static void tg3_get_regs(struct net_device *dev,
8342 struct ethtool_regs *regs, void *_p)
8345 struct tg3 *tp = netdev_priv(dev);
8351 memset(p, 0, TG3_REGDUMP_LEN);
8353 if (tp->link_config.phy_is_low_power)
8356 tg3_full_lock(tp, 0);
8358 #define __GET_REG32(reg) (*(p)++ = tr32(reg))
8359 #define GET_REG32_LOOP(base,len) \
8360 do { p = (u32 *)(orig_p + (base)); \
8361 for (i = 0; i < len; i += 4) \
8362 __GET_REG32((base) + i); \
8364 #define GET_REG32_1(reg) \
8365 do { p = (u32 *)(orig_p + (reg)); \
8366 __GET_REG32((reg)); \
8369 GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
8370 GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
8371 GET_REG32_LOOP(MAC_MODE, 0x4f0);
8372 GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
8373 GET_REG32_1(SNDDATAC_MODE);
8374 GET_REG32_LOOP(SNDBDS_MODE, 0x80);
8375 GET_REG32_LOOP(SNDBDI_MODE, 0x48);
8376 GET_REG32_1(SNDBDC_MODE);
8377 GET_REG32_LOOP(RCVLPC_MODE, 0x20);
8378 GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
8379 GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
8380 GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
8381 GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
8382 GET_REG32_1(RCVDCC_MODE);
8383 GET_REG32_LOOP(RCVBDI_MODE, 0x20);
8384 GET_REG32_LOOP(RCVCC_MODE, 0x14);
8385 GET_REG32_LOOP(RCVLSC_MODE, 0x08);
8386 GET_REG32_1(MBFREE_MODE);
8387 GET_REG32_LOOP(HOSTCC_MODE, 0x100);
8388 GET_REG32_LOOP(MEMARB_MODE, 0x10);
8389 GET_REG32_LOOP(BUFMGR_MODE, 0x58);
8390 GET_REG32_LOOP(RDMAC_MODE, 0x08);
8391 GET_REG32_LOOP(WDMAC_MODE, 0x08);
8392 GET_REG32_1(RX_CPU_MODE);
8393 GET_REG32_1(RX_CPU_STATE);
8394 GET_REG32_1(RX_CPU_PGMCTR);
8395 GET_REG32_1(RX_CPU_HWBKPT);
8396 GET_REG32_1(TX_CPU_MODE);
8397 GET_REG32_1(TX_CPU_STATE);
8398 GET_REG32_1(TX_CPU_PGMCTR);
8399 GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
8400 GET_REG32_LOOP(FTQ_RESET, 0x120);
8401 GET_REG32_LOOP(MSGINT_MODE, 0x0c);
8402 GET_REG32_1(DMAC_MODE);
8403 GET_REG32_LOOP(GRC_MODE, 0x4c);
8404 if (tp->tg3_flags & TG3_FLAG_NVRAM)
8405 GET_REG32_LOOP(NVRAM_CMD, 0x24);
8408 #undef GET_REG32_LOOP
8411 tg3_full_unlock(tp);
8414 static int tg3_get_eeprom_len(struct net_device *dev)
8416 struct tg3 *tp = netdev_priv(dev);
8418 return tp->nvram_size;
8421 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val);
8422 static int tg3_nvram_read_le(struct tg3 *tp, u32 offset, __le32 *val);
8423 static int tg3_nvram_read_swab(struct tg3 *tp, u32 offset, u32 *val);
8425 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
8427 struct tg3 *tp = netdev_priv(dev);
8430 u32 i, offset, len, b_offset, b_count;
8433 if (tp->link_config.phy_is_low_power)
8436 offset = eeprom->offset;
8440 eeprom->magic = TG3_EEPROM_MAGIC;
8443 /* adjustments to start on required 4 byte boundary */
8444 b_offset = offset & 3;
8445 b_count = 4 - b_offset;
8446 if (b_count > len) {
8447 /* i.e. offset=1 len=2 */
8450 ret = tg3_nvram_read_le(tp, offset-b_offset, &val);
8453 memcpy(data, ((char*)&val) + b_offset, b_count);
8456 eeprom->len += b_count;
8459 /* read bytes upto the last 4 byte boundary */
8460 pd = &data[eeprom->len];
8461 for (i = 0; i < (len - (len & 3)); i += 4) {
8462 ret = tg3_nvram_read_le(tp, offset + i, &val);
8467 memcpy(pd + i, &val, 4);
8472 /* read last bytes not ending on 4 byte boundary */
8473 pd = &data[eeprom->len];
8475 b_offset = offset + len - b_count;
8476 ret = tg3_nvram_read_le(tp, b_offset, &val);
8479 memcpy(pd, &val, b_count);
8480 eeprom->len += b_count;
8485 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
8487 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
8489 struct tg3 *tp = netdev_priv(dev);
8491 u32 offset, len, b_offset, odd_len;
8495 if (tp->link_config.phy_is_low_power)
8498 if (eeprom->magic != TG3_EEPROM_MAGIC)
8501 offset = eeprom->offset;
8504 if ((b_offset = (offset & 3))) {
8505 /* adjustments to start on required 4 byte boundary */
8506 ret = tg3_nvram_read_le(tp, offset-b_offset, &start);
8517 /* adjustments to end on required 4 byte boundary */
8519 len = (len + 3) & ~3;
8520 ret = tg3_nvram_read_le(tp, offset+len-4, &end);
8526 if (b_offset || odd_len) {
8527 buf = kmalloc(len, GFP_KERNEL);
8531 memcpy(buf, &start, 4);
8533 memcpy(buf+len-4, &end, 4);
8534 memcpy(buf + b_offset, data, eeprom->len);
8537 ret = tg3_nvram_write_block(tp, offset, len, buf);
8545 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
8547 struct tg3 *tp = netdev_priv(dev);
8549 cmd->supported = (SUPPORTED_Autoneg);
8551 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
8552 cmd->supported |= (SUPPORTED_1000baseT_Half |
8553 SUPPORTED_1000baseT_Full);
8555 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
8556 cmd->supported |= (SUPPORTED_100baseT_Half |
8557 SUPPORTED_100baseT_Full |
8558 SUPPORTED_10baseT_Half |
8559 SUPPORTED_10baseT_Full |
8561 cmd->port = PORT_TP;
8563 cmd->supported |= SUPPORTED_FIBRE;
8564 cmd->port = PORT_FIBRE;
8567 cmd->advertising = tp->link_config.advertising;
8568 if (netif_running(dev)) {
8569 cmd->speed = tp->link_config.active_speed;
8570 cmd->duplex = tp->link_config.active_duplex;
8572 cmd->phy_address = PHY_ADDR;
8573 cmd->transceiver = 0;
8574 cmd->autoneg = tp->link_config.autoneg;
8580 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
8582 struct tg3 *tp = netdev_priv(dev);
8584 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
8585 /* These are the only valid advertisement bits allowed. */
8586 if (cmd->autoneg == AUTONEG_ENABLE &&
8587 (cmd->advertising & ~(ADVERTISED_1000baseT_Half |
8588 ADVERTISED_1000baseT_Full |
8589 ADVERTISED_Autoneg |
8592 /* Fiber can only do SPEED_1000. */
8593 else if ((cmd->autoneg != AUTONEG_ENABLE) &&
8594 (cmd->speed != SPEED_1000))
8596 /* Copper cannot force SPEED_1000. */
8597 } else if ((cmd->autoneg != AUTONEG_ENABLE) &&
8598 (cmd->speed == SPEED_1000))
8600 else if ((cmd->speed == SPEED_1000) &&
8601 (tp->tg3_flags & TG3_FLAG_10_100_ONLY))
8604 tg3_full_lock(tp, 0);
8606 tp->link_config.autoneg = cmd->autoneg;
8607 if (cmd->autoneg == AUTONEG_ENABLE) {
8608 tp->link_config.advertising = (cmd->advertising |
8609 ADVERTISED_Autoneg);
8610 tp->link_config.speed = SPEED_INVALID;
8611 tp->link_config.duplex = DUPLEX_INVALID;
8613 tp->link_config.advertising = 0;
8614 tp->link_config.speed = cmd->speed;
8615 tp->link_config.duplex = cmd->duplex;
8618 tp->link_config.orig_speed = tp->link_config.speed;
8619 tp->link_config.orig_duplex = tp->link_config.duplex;
8620 tp->link_config.orig_autoneg = tp->link_config.autoneg;
8622 if (netif_running(dev))
8623 tg3_setup_phy(tp, 1);
8625 tg3_full_unlock(tp);
8630 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
8632 struct tg3 *tp = netdev_priv(dev);
8634 strcpy(info->driver, DRV_MODULE_NAME);
8635 strcpy(info->version, DRV_MODULE_VERSION);
8636 strcpy(info->fw_version, tp->fw_ver);
8637 strcpy(info->bus_info, pci_name(tp->pdev));
8640 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8642 struct tg3 *tp = netdev_priv(dev);
8644 if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
8645 wol->supported = WAKE_MAGIC;
8649 if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)
8650 wol->wolopts = WAKE_MAGIC;
8651 memset(&wol->sopass, 0, sizeof(wol->sopass));
8654 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8656 struct tg3 *tp = netdev_priv(dev);
8658 if (wol->wolopts & ~WAKE_MAGIC)
8660 if ((wol->wolopts & WAKE_MAGIC) &&
8661 !(tp->tg3_flags & TG3_FLAG_WOL_CAP))
8664 spin_lock_bh(&tp->lock);
8665 if (wol->wolopts & WAKE_MAGIC)
8666 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
8668 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
8669 spin_unlock_bh(&tp->lock);
8674 static u32 tg3_get_msglevel(struct net_device *dev)
8676 struct tg3 *tp = netdev_priv(dev);
8677 return tp->msg_enable;
8680 static void tg3_set_msglevel(struct net_device *dev, u32 value)
8682 struct tg3 *tp = netdev_priv(dev);
8683 tp->msg_enable = value;
8686 static int tg3_set_tso(struct net_device *dev, u32 value)
8688 struct tg3 *tp = netdev_priv(dev);
8690 if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8695 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) &&
8696 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)) {
8698 dev->features |= NETIF_F_TSO6;
8699 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
8700 dev->features |= NETIF_F_TSO_ECN;
8702 dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
8704 return ethtool_op_set_tso(dev, value);
8707 static int tg3_nway_reset(struct net_device *dev)
8709 struct tg3 *tp = netdev_priv(dev);
8713 if (!netif_running(dev))
8716 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
8719 spin_lock_bh(&tp->lock);
8721 tg3_readphy(tp, MII_BMCR, &bmcr);
8722 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
8723 ((bmcr & BMCR_ANENABLE) ||
8724 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
8725 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
8729 spin_unlock_bh(&tp->lock);
8734 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
8736 struct tg3 *tp = netdev_priv(dev);
8738 ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
8739 ering->rx_mini_max_pending = 0;
8740 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
8741 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
8743 ering->rx_jumbo_max_pending = 0;
8745 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
8747 ering->rx_pending = tp->rx_pending;
8748 ering->rx_mini_pending = 0;
8749 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
8750 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
8752 ering->rx_jumbo_pending = 0;
8754 ering->tx_pending = tp->tx_pending;
8757 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
8759 struct tg3 *tp = netdev_priv(dev);
8760 int irq_sync = 0, err = 0;
8762 if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
8763 (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
8764 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
8765 (ering->tx_pending <= MAX_SKB_FRAGS) ||
8766 ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
8767 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
8770 if (netif_running(dev)) {
8775 tg3_full_lock(tp, irq_sync);
8777 tp->rx_pending = ering->rx_pending;
8779 if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
8780 tp->rx_pending > 63)
8781 tp->rx_pending = 63;
8782 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
8783 tp->tx_pending = ering->tx_pending;
8785 if (netif_running(dev)) {
8786 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8787 err = tg3_restart_hw(tp, 1);
8789 tg3_netif_start(tp);
8792 tg3_full_unlock(tp);
8797 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
8799 struct tg3 *tp = netdev_priv(dev);
8801 epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
8803 if (tp->link_config.active_flowctrl & TG3_FLOW_CTRL_RX)
8804 epause->rx_pause = 1;
8806 epause->rx_pause = 0;
8808 if (tp->link_config.active_flowctrl & TG3_FLOW_CTRL_TX)
8809 epause->tx_pause = 1;
8811 epause->tx_pause = 0;
8814 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
8816 struct tg3 *tp = netdev_priv(dev);
8817 int irq_sync = 0, err = 0;
8819 if (netif_running(dev)) {
8824 tg3_full_lock(tp, irq_sync);
8826 if (epause->autoneg)
8827 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
8829 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
8830 if (epause->rx_pause)
8831 tp->link_config.flowctrl |= TG3_FLOW_CTRL_RX;
8833 tp->link_config.flowctrl &= ~TG3_FLOW_CTRL_RX;
8834 if (epause->tx_pause)
8835 tp->link_config.flowctrl |= TG3_FLOW_CTRL_TX;
8837 tp->link_config.flowctrl &= ~TG3_FLOW_CTRL_TX;
8839 if (netif_running(dev)) {
8840 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8841 err = tg3_restart_hw(tp, 1);
8843 tg3_netif_start(tp);
8846 tg3_full_unlock(tp);
8851 static u32 tg3_get_rx_csum(struct net_device *dev)
8853 struct tg3 *tp = netdev_priv(dev);
8854 return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
8857 static int tg3_set_rx_csum(struct net_device *dev, u32 data)
8859 struct tg3 *tp = netdev_priv(dev);
8861 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
8867 spin_lock_bh(&tp->lock);
8869 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
8871 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
8872 spin_unlock_bh(&tp->lock);
8877 static int tg3_set_tx_csum(struct net_device *dev, u32 data)
8879 struct tg3 *tp = netdev_priv(dev);
8881 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
8887 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
8888 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
8889 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
8890 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
8891 ethtool_op_set_tx_ipv6_csum(dev, data);
8893 ethtool_op_set_tx_csum(dev, data);
8898 static int tg3_get_sset_count (struct net_device *dev, int sset)
8902 return TG3_NUM_TEST;
8904 return TG3_NUM_STATS;
8910 static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
8912 switch (stringset) {
8914 memcpy(buf, ðtool_stats_keys, sizeof(ethtool_stats_keys));
8917 memcpy(buf, ðtool_test_keys, sizeof(ethtool_test_keys));
8920 WARN_ON(1); /* we need a WARN() */
8925 static int tg3_phys_id(struct net_device *dev, u32 data)
8927 struct tg3 *tp = netdev_priv(dev);
8930 if (!netif_running(tp->dev))
8934 data = UINT_MAX / 2;
8936 for (i = 0; i < (data * 2); i++) {
8938 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
8939 LED_CTRL_1000MBPS_ON |
8940 LED_CTRL_100MBPS_ON |
8941 LED_CTRL_10MBPS_ON |
8942 LED_CTRL_TRAFFIC_OVERRIDE |
8943 LED_CTRL_TRAFFIC_BLINK |
8944 LED_CTRL_TRAFFIC_LED);
8947 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
8948 LED_CTRL_TRAFFIC_OVERRIDE);
8950 if (msleep_interruptible(500))
8953 tw32(MAC_LED_CTRL, tp->led_ctrl);
8957 static void tg3_get_ethtool_stats (struct net_device *dev,
8958 struct ethtool_stats *estats, u64 *tmp_stats)
8960 struct tg3 *tp = netdev_priv(dev);
8961 memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
8964 #define NVRAM_TEST_SIZE 0x100
8965 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
8966 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
8967 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
8968 #define NVRAM_SELFBOOT_HW_SIZE 0x20
8969 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
8971 static int tg3_test_nvram(struct tg3 *tp)
8975 int i, j, k, err = 0, size;
8977 if (tg3_nvram_read_swab(tp, 0, &magic) != 0)
8980 if (magic == TG3_EEPROM_MAGIC)
8981 size = NVRAM_TEST_SIZE;
8982 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
8983 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
8984 TG3_EEPROM_SB_FORMAT_1) {
8985 switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
8986 case TG3_EEPROM_SB_REVISION_0:
8987 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
8989 case TG3_EEPROM_SB_REVISION_2:
8990 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
8992 case TG3_EEPROM_SB_REVISION_3:
8993 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
9000 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
9001 size = NVRAM_SELFBOOT_HW_SIZE;
9005 buf = kmalloc(size, GFP_KERNEL);
9010 for (i = 0, j = 0; i < size; i += 4, j++) {
9011 if ((err = tg3_nvram_read_le(tp, i, &buf[j])) != 0)
9017 /* Selfboot format */
9018 magic = swab32(le32_to_cpu(buf[0]));
9019 if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
9020 TG3_EEPROM_MAGIC_FW) {
9021 u8 *buf8 = (u8 *) buf, csum8 = 0;
9023 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
9024 TG3_EEPROM_SB_REVISION_2) {
9025 /* For rev 2, the csum doesn't include the MBA. */
9026 for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
9028 for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
9031 for (i = 0; i < size; i++)
9044 if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
9045 TG3_EEPROM_MAGIC_HW) {
9046 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
9047 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
9048 u8 *buf8 = (u8 *) buf;
9050 /* Separate the parity bits and the data bytes. */
9051 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
9052 if ((i == 0) || (i == 8)) {
9056 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
9057 parity[k++] = buf8[i] & msk;
9064 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
9065 parity[k++] = buf8[i] & msk;
9068 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
9069 parity[k++] = buf8[i] & msk;
9072 data[j++] = buf8[i];
9076 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
9077 u8 hw8 = hweight8(data[i]);
9079 if ((hw8 & 0x1) && parity[i])
9081 else if (!(hw8 & 0x1) && !parity[i])
9088 /* Bootstrap checksum at offset 0x10 */
9089 csum = calc_crc((unsigned char *) buf, 0x10);
9090 if(csum != le32_to_cpu(buf[0x10/4]))
9093 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
9094 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
9095 if (csum != le32_to_cpu(buf[0xfc/4]))
9105 #define TG3_SERDES_TIMEOUT_SEC 2
9106 #define TG3_COPPER_TIMEOUT_SEC 6
9108 static int tg3_test_link(struct tg3 *tp)
9112 if (!netif_running(tp->dev))
9115 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
9116 max = TG3_SERDES_TIMEOUT_SEC;
9118 max = TG3_COPPER_TIMEOUT_SEC;
9120 for (i = 0; i < max; i++) {
9121 if (netif_carrier_ok(tp->dev))
9124 if (msleep_interruptible(1000))
9131 /* Only test the commonly used registers */
9132 static int tg3_test_registers(struct tg3 *tp)
9134 int i, is_5705, is_5750;
9135 u32 offset, read_mask, write_mask, val, save_val, read_val;
9139 #define TG3_FL_5705 0x1
9140 #define TG3_FL_NOT_5705 0x2
9141 #define TG3_FL_NOT_5788 0x4
9142 #define TG3_FL_NOT_5750 0x8
9146 /* MAC Control Registers */
9147 { MAC_MODE, TG3_FL_NOT_5705,
9148 0x00000000, 0x00ef6f8c },
9149 { MAC_MODE, TG3_FL_5705,
9150 0x00000000, 0x01ef6b8c },
9151 { MAC_STATUS, TG3_FL_NOT_5705,
9152 0x03800107, 0x00000000 },
9153 { MAC_STATUS, TG3_FL_5705,
9154 0x03800100, 0x00000000 },
9155 { MAC_ADDR_0_HIGH, 0x0000,
9156 0x00000000, 0x0000ffff },
9157 { MAC_ADDR_0_LOW, 0x0000,
9158 0x00000000, 0xffffffff },
9159 { MAC_RX_MTU_SIZE, 0x0000,
9160 0x00000000, 0x0000ffff },
9161 { MAC_TX_MODE, 0x0000,
9162 0x00000000, 0x00000070 },
9163 { MAC_TX_LENGTHS, 0x0000,
9164 0x00000000, 0x00003fff },
9165 { MAC_RX_MODE, TG3_FL_NOT_5705,
9166 0x00000000, 0x000007fc },
9167 { MAC_RX_MODE, TG3_FL_5705,
9168 0x00000000, 0x000007dc },
9169 { MAC_HASH_REG_0, 0x0000,
9170 0x00000000, 0xffffffff },
9171 { MAC_HASH_REG_1, 0x0000,
9172 0x00000000, 0xffffffff },
9173 { MAC_HASH_REG_2, 0x0000,
9174 0x00000000, 0xffffffff },
9175 { MAC_HASH_REG_3, 0x0000,
9176 0x00000000, 0xffffffff },
9178 /* Receive Data and Receive BD Initiator Control Registers. */
9179 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
9180 0x00000000, 0xffffffff },
9181 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
9182 0x00000000, 0xffffffff },
9183 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
9184 0x00000000, 0x00000003 },
9185 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
9186 0x00000000, 0xffffffff },
9187 { RCVDBDI_STD_BD+0, 0x0000,
9188 0x00000000, 0xffffffff },
9189 { RCVDBDI_STD_BD+4, 0x0000,
9190 0x00000000, 0xffffffff },
9191 { RCVDBDI_STD_BD+8, 0x0000,
9192 0x00000000, 0xffff0002 },
9193 { RCVDBDI_STD_BD+0xc, 0x0000,
9194 0x00000000, 0xffffffff },
9196 /* Receive BD Initiator Control Registers. */
9197 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
9198 0x00000000, 0xffffffff },
9199 { RCVBDI_STD_THRESH, TG3_FL_5705,
9200 0x00000000, 0x000003ff },
9201 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
9202 0x00000000, 0xffffffff },
9204 /* Host Coalescing Control Registers. */
9205 { HOSTCC_MODE, TG3_FL_NOT_5705,
9206 0x00000000, 0x00000004 },
9207 { HOSTCC_MODE, TG3_FL_5705,
9208 0x00000000, 0x000000f6 },
9209 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
9210 0x00000000, 0xffffffff },
9211 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
9212 0x00000000, 0x000003ff },
9213 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
9214 0x00000000, 0xffffffff },
9215 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
9216 0x00000000, 0x000003ff },
9217 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
9218 0x00000000, 0xffffffff },
9219 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
9220 0x00000000, 0x000000ff },
9221 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
9222 0x00000000, 0xffffffff },
9223 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
9224 0x00000000, 0x000000ff },
9225 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
9226 0x00000000, 0xffffffff },
9227 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
9228 0x00000000, 0xffffffff },
9229 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
9230 0x00000000, 0xffffffff },
9231 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
9232 0x00000000, 0x000000ff },
9233 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
9234 0x00000000, 0xffffffff },
9235 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
9236 0x00000000, 0x000000ff },
9237 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
9238 0x00000000, 0xffffffff },
9239 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
9240 0x00000000, 0xffffffff },
9241 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
9242 0x00000000, 0xffffffff },
9243 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
9244 0x00000000, 0xffffffff },
9245 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
9246 0x00000000, 0xffffffff },
9247 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
9248 0xffffffff, 0x00000000 },
9249 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
9250 0xffffffff, 0x00000000 },
9252 /* Buffer Manager Control Registers. */
9253 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
9254 0x00000000, 0x007fff80 },
9255 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
9256 0x00000000, 0x007fffff },
9257 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
9258 0x00000000, 0x0000003f },
9259 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
9260 0x00000000, 0x000001ff },
9261 { BUFMGR_MB_HIGH_WATER, 0x0000,
9262 0x00000000, 0x000001ff },
9263 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
9264 0xffffffff, 0x00000000 },
9265 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
9266 0xffffffff, 0x00000000 },
9268 /* Mailbox Registers */
9269 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
9270 0x00000000, 0x000001ff },
9271 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
9272 0x00000000, 0x000001ff },
9273 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
9274 0x00000000, 0x000007ff },
9275 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
9276 0x00000000, 0x000001ff },
9278 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
9281 is_5705 = is_5750 = 0;
9282 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
9284 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
9288 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
9289 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
9292 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
9295 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
9296 (reg_tbl[i].flags & TG3_FL_NOT_5788))
9299 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
9302 offset = (u32) reg_tbl[i].offset;
9303 read_mask = reg_tbl[i].read_mask;
9304 write_mask = reg_tbl[i].write_mask;
9306 /* Save the original register content */
9307 save_val = tr32(offset);
9309 /* Determine the read-only value. */
9310 read_val = save_val & read_mask;
9312 /* Write zero to the register, then make sure the read-only bits
9313 * are not changed and the read/write bits are all zeros.
9319 /* Test the read-only and read/write bits. */
9320 if (((val & read_mask) != read_val) || (val & write_mask))
9323 /* Write ones to all the bits defined by RdMask and WrMask, then
9324 * make sure the read-only bits are not changed and the
9325 * read/write bits are all ones.
9327 tw32(offset, read_mask | write_mask);
9331 /* Test the read-only bits. */
9332 if ((val & read_mask) != read_val)
9335 /* Test the read/write bits. */
9336 if ((val & write_mask) != write_mask)
9339 tw32(offset, save_val);
9345 if (netif_msg_hw(tp))
9346 printk(KERN_ERR PFX "Register test failed at offset %x\n",
9348 tw32(offset, save_val);
9352 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
9354 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
9358 for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
9359 for (j = 0; j < len; j += 4) {
9362 tg3_write_mem(tp, offset + j, test_pattern[i]);
9363 tg3_read_mem(tp, offset + j, &val);
9364 if (val != test_pattern[i])
9371 static int tg3_test_memory(struct tg3 *tp)
9373 static struct mem_entry {
9376 } mem_tbl_570x[] = {
9377 { 0x00000000, 0x00b50},
9378 { 0x00002000, 0x1c000},
9379 { 0xffffffff, 0x00000}
9380 }, mem_tbl_5705[] = {
9381 { 0x00000100, 0x0000c},
9382 { 0x00000200, 0x00008},
9383 { 0x00004000, 0x00800},
9384 { 0x00006000, 0x01000},
9385 { 0x00008000, 0x02000},
9386 { 0x00010000, 0x0e000},
9387 { 0xffffffff, 0x00000}
9388 }, mem_tbl_5755[] = {
9389 { 0x00000200, 0x00008},
9390 { 0x00004000, 0x00800},
9391 { 0x00006000, 0x00800},
9392 { 0x00008000, 0x02000},
9393 { 0x00010000, 0x0c000},
9394 { 0xffffffff, 0x00000}
9395 }, mem_tbl_5906[] = {
9396 { 0x00000200, 0x00008},
9397 { 0x00004000, 0x00400},
9398 { 0x00006000, 0x00400},
9399 { 0x00008000, 0x01000},
9400 { 0x00010000, 0x01000},
9401 { 0xffffffff, 0x00000}
9403 struct mem_entry *mem_tbl;
9407 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
9408 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
9409 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
9410 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
9411 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
9412 mem_tbl = mem_tbl_5755;
9413 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
9414 mem_tbl = mem_tbl_5906;
9416 mem_tbl = mem_tbl_5705;
9418 mem_tbl = mem_tbl_570x;
9420 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
9421 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
9422 mem_tbl[i].len)) != 0)
9429 #define TG3_MAC_LOOPBACK 0
9430 #define TG3_PHY_LOOPBACK 1
9432 static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
9434 u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
9436 struct sk_buff *skb, *rx_skb;
9439 int num_pkts, tx_len, rx_len, i, err;
9440 struct tg3_rx_buffer_desc *desc;
9442 if (loopback_mode == TG3_MAC_LOOPBACK) {
9443 /* HW errata - mac loopback fails in some cases on 5780.
9444 * Normal traffic and PHY loopback are not affected by
9447 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
9450 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
9451 MAC_MODE_PORT_INT_LPBACK;
9452 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
9453 mac_mode |= MAC_MODE_LINK_POLARITY;
9454 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
9455 mac_mode |= MAC_MODE_PORT_MODE_MII;
9457 mac_mode |= MAC_MODE_PORT_MODE_GMII;
9458 tw32(MAC_MODE, mac_mode);
9459 } else if (loopback_mode == TG3_PHY_LOOPBACK) {
9462 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
9465 if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &phytest)) {
9468 tg3_writephy(tp, MII_TG3_EPHY_TEST,
9469 phytest | MII_TG3_EPHY_SHADOW_EN);
9470 if (!tg3_readphy(tp, 0x1b, &phy))
9471 tg3_writephy(tp, 0x1b, phy & ~0x20);
9472 tg3_writephy(tp, MII_TG3_EPHY_TEST, phytest);
9474 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
9476 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
9478 tg3_phy_toggle_automdix(tp, 0);
9480 tg3_writephy(tp, MII_BMCR, val);
9483 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
9484 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
9485 tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x1800);
9486 mac_mode |= MAC_MODE_PORT_MODE_MII;
9488 mac_mode |= MAC_MODE_PORT_MODE_GMII;
9490 /* reset to prevent losing 1st rx packet intermittently */
9491 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
9492 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
9494 tw32_f(MAC_RX_MODE, tp->rx_mode);
9496 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
9497 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)
9498 mac_mode &= ~MAC_MODE_LINK_POLARITY;
9499 else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411)
9500 mac_mode |= MAC_MODE_LINK_POLARITY;
9501 tg3_writephy(tp, MII_TG3_EXT_CTRL,
9502 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
9504 tw32(MAC_MODE, mac_mode);
9512 skb = netdev_alloc_skb(tp->dev, tx_len);
9516 tx_data = skb_put(skb, tx_len);
9517 memcpy(tx_data, tp->dev->dev_addr, 6);
9518 memset(tx_data + 6, 0x0, 8);
9520 tw32(MAC_RX_MTU_SIZE, tx_len + 4);
9522 for (i = 14; i < tx_len; i++)
9523 tx_data[i] = (u8) (i & 0xff);
9525 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
9527 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
9532 rx_start_idx = tp->hw_status->idx[0].rx_producer;
9536 tg3_set_txd(tp, tp->tx_prod, map, tx_len, 0, 1);
9541 tw32_tx_mbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW,
9543 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW);
9547 /* 250 usec to allow enough time on some 10/100 Mbps devices. */
9548 for (i = 0; i < 25; i++) {
9549 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
9554 tx_idx = tp->hw_status->idx[0].tx_consumer;
9555 rx_idx = tp->hw_status->idx[0].rx_producer;
9556 if ((tx_idx == tp->tx_prod) &&
9557 (rx_idx == (rx_start_idx + num_pkts)))
9561 pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
9564 if (tx_idx != tp->tx_prod)
9567 if (rx_idx != rx_start_idx + num_pkts)
9570 desc = &tp->rx_rcb[rx_start_idx];
9571 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
9572 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
9573 if (opaque_key != RXD_OPAQUE_RING_STD)
9576 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
9577 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
9580 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
9581 if (rx_len != tx_len)
9584 rx_skb = tp->rx_std_buffers[desc_idx].skb;
9586 map = pci_unmap_addr(&tp->rx_std_buffers[desc_idx], mapping);
9587 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
9589 for (i = 14; i < tx_len; i++) {
9590 if (*(rx_skb->data + i) != (u8) (i & 0xff))
9595 /* tg3_free_rings will unmap and free the rx_skb */
9600 #define TG3_MAC_LOOPBACK_FAILED 1
9601 #define TG3_PHY_LOOPBACK_FAILED 2
9602 #define TG3_LOOPBACK_FAILED (TG3_MAC_LOOPBACK_FAILED | \
9603 TG3_PHY_LOOPBACK_FAILED)
9605 static int tg3_test_loopback(struct tg3 *tp)
9610 if (!netif_running(tp->dev))
9611 return TG3_LOOPBACK_FAILED;
9613 err = tg3_reset_hw(tp, 1);
9615 return TG3_LOOPBACK_FAILED;
9617 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
9618 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
9622 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
9624 /* Wait for up to 40 microseconds to acquire lock. */
9625 for (i = 0; i < 4; i++) {
9626 status = tr32(TG3_CPMU_MUTEX_GNT);
9627 if (status == CPMU_MUTEX_GNT_DRIVER)
9632 if (status != CPMU_MUTEX_GNT_DRIVER)
9633 return TG3_LOOPBACK_FAILED;
9635 /* Turn off link-based power management. */
9636 cpmuctrl = tr32(TG3_CPMU_CTRL);
9638 cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
9639 CPMU_CTRL_LINK_AWARE_MODE));
9642 if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
9643 err |= TG3_MAC_LOOPBACK_FAILED;
9645 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
9646 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
9647 tw32(TG3_CPMU_CTRL, cpmuctrl);
9649 /* Release the mutex */
9650 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
9653 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
9654 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
9655 err |= TG3_PHY_LOOPBACK_FAILED;
9661 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
9664 struct tg3 *tp = netdev_priv(dev);
9666 if (tp->link_config.phy_is_low_power)
9667 tg3_set_power_state(tp, PCI_D0);
9669 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
9671 if (tg3_test_nvram(tp) != 0) {
9672 etest->flags |= ETH_TEST_FL_FAILED;
9675 if (tg3_test_link(tp) != 0) {
9676 etest->flags |= ETH_TEST_FL_FAILED;
9679 if (etest->flags & ETH_TEST_FL_OFFLINE) {
9680 int err, irq_sync = 0;
9682 if (netif_running(dev)) {
9687 tg3_full_lock(tp, irq_sync);
9689 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
9690 err = tg3_nvram_lock(tp);
9691 tg3_halt_cpu(tp, RX_CPU_BASE);
9692 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
9693 tg3_halt_cpu(tp, TX_CPU_BASE);
9695 tg3_nvram_unlock(tp);
9697 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
9700 if (tg3_test_registers(tp) != 0) {
9701 etest->flags |= ETH_TEST_FL_FAILED;
9704 if (tg3_test_memory(tp) != 0) {
9705 etest->flags |= ETH_TEST_FL_FAILED;
9708 if ((data[4] = tg3_test_loopback(tp)) != 0)
9709 etest->flags |= ETH_TEST_FL_FAILED;
9711 tg3_full_unlock(tp);
9713 if (tg3_test_interrupt(tp) != 0) {
9714 etest->flags |= ETH_TEST_FL_FAILED;
9718 tg3_full_lock(tp, 0);
9720 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9721 if (netif_running(dev)) {
9722 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
9723 if (!tg3_restart_hw(tp, 1))
9724 tg3_netif_start(tp);
9727 tg3_full_unlock(tp);
9729 if (tp->link_config.phy_is_low_power)
9730 tg3_set_power_state(tp, PCI_D3hot);
9734 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
9736 struct mii_ioctl_data *data = if_mii(ifr);
9737 struct tg3 *tp = netdev_priv(dev);
9742 data->phy_id = PHY_ADDR;
9748 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9749 break; /* We have no PHY */
9751 if (tp->link_config.phy_is_low_power)
9754 spin_lock_bh(&tp->lock);
9755 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
9756 spin_unlock_bh(&tp->lock);
9758 data->val_out = mii_regval;
9764 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9765 break; /* We have no PHY */
9767 if (!capable(CAP_NET_ADMIN))
9770 if (tp->link_config.phy_is_low_power)
9773 spin_lock_bh(&tp->lock);
9774 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
9775 spin_unlock_bh(&tp->lock);
9786 #if TG3_VLAN_TAG_USED
9787 static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
9789 struct tg3 *tp = netdev_priv(dev);
9791 if (netif_running(dev))
9794 tg3_full_lock(tp, 0);
9798 /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
9799 __tg3_set_rx_mode(dev);
9801 if (netif_running(dev))
9802 tg3_netif_start(tp);
9804 tg3_full_unlock(tp);
9808 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
9810 struct tg3 *tp = netdev_priv(dev);
9812 memcpy(ec, &tp->coal, sizeof(*ec));
9816 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
9818 struct tg3 *tp = netdev_priv(dev);
9819 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
9820 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
9822 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
9823 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
9824 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
9825 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
9826 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
9829 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
9830 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
9831 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
9832 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
9833 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
9834 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
9835 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
9836 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
9837 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
9838 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
9841 /* No rx interrupts will be generated if both are zero */
9842 if ((ec->rx_coalesce_usecs == 0) &&
9843 (ec->rx_max_coalesced_frames == 0))
9846 /* No tx interrupts will be generated if both are zero */
9847 if ((ec->tx_coalesce_usecs == 0) &&
9848 (ec->tx_max_coalesced_frames == 0))
9851 /* Only copy relevant parameters, ignore all others. */
9852 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
9853 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
9854 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
9855 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
9856 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
9857 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
9858 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
9859 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
9860 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
9862 if (netif_running(dev)) {
9863 tg3_full_lock(tp, 0);
9864 __tg3_set_coalesce(tp, &tp->coal);
9865 tg3_full_unlock(tp);
9870 static const struct ethtool_ops tg3_ethtool_ops = {
9871 .get_settings = tg3_get_settings,
9872 .set_settings = tg3_set_settings,
9873 .get_drvinfo = tg3_get_drvinfo,
9874 .get_regs_len = tg3_get_regs_len,
9875 .get_regs = tg3_get_regs,
9876 .get_wol = tg3_get_wol,
9877 .set_wol = tg3_set_wol,
9878 .get_msglevel = tg3_get_msglevel,
9879 .set_msglevel = tg3_set_msglevel,
9880 .nway_reset = tg3_nway_reset,
9881 .get_link = ethtool_op_get_link,
9882 .get_eeprom_len = tg3_get_eeprom_len,
9883 .get_eeprom = tg3_get_eeprom,
9884 .set_eeprom = tg3_set_eeprom,
9885 .get_ringparam = tg3_get_ringparam,
9886 .set_ringparam = tg3_set_ringparam,
9887 .get_pauseparam = tg3_get_pauseparam,
9888 .set_pauseparam = tg3_set_pauseparam,
9889 .get_rx_csum = tg3_get_rx_csum,
9890 .set_rx_csum = tg3_set_rx_csum,
9891 .set_tx_csum = tg3_set_tx_csum,
9892 .set_sg = ethtool_op_set_sg,
9893 .set_tso = tg3_set_tso,
9894 .self_test = tg3_self_test,
9895 .get_strings = tg3_get_strings,
9896 .phys_id = tg3_phys_id,
9897 .get_ethtool_stats = tg3_get_ethtool_stats,
9898 .get_coalesce = tg3_get_coalesce,
9899 .set_coalesce = tg3_set_coalesce,
9900 .get_sset_count = tg3_get_sset_count,
9903 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
9905 u32 cursize, val, magic;
9907 tp->nvram_size = EEPROM_CHIP_SIZE;
9909 if (tg3_nvram_read_swab(tp, 0, &magic) != 0)
9912 if ((magic != TG3_EEPROM_MAGIC) &&
9913 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
9914 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
9918 * Size the chip by reading offsets at increasing powers of two.
9919 * When we encounter our validation signature, we know the addressing
9920 * has wrapped around, and thus have our chip size.
9924 while (cursize < tp->nvram_size) {
9925 if (tg3_nvram_read_swab(tp, cursize, &val) != 0)
9934 tp->nvram_size = cursize;
9937 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
9941 if (tg3_nvram_read_swab(tp, 0, &val) != 0)
9944 /* Selfboot format */
9945 if (val != TG3_EEPROM_MAGIC) {
9946 tg3_get_eeprom_size(tp);
9950 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
9952 tp->nvram_size = (val >> 16) * 1024;
9956 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
9959 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
9963 nvcfg1 = tr32(NVRAM_CFG1);
9964 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
9965 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9968 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
9969 tw32(NVRAM_CFG1, nvcfg1);
9972 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
9973 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
9974 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
9975 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
9976 tp->nvram_jedecnum = JEDEC_ATMEL;
9977 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
9978 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9980 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
9981 tp->nvram_jedecnum = JEDEC_ATMEL;
9982 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
9984 case FLASH_VENDOR_ATMEL_EEPROM:
9985 tp->nvram_jedecnum = JEDEC_ATMEL;
9986 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9987 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9989 case FLASH_VENDOR_ST:
9990 tp->nvram_jedecnum = JEDEC_ST;
9991 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
9992 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9994 case FLASH_VENDOR_SAIFUN:
9995 tp->nvram_jedecnum = JEDEC_SAIFUN;
9996 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
9998 case FLASH_VENDOR_SST_SMALL:
9999 case FLASH_VENDOR_SST_LARGE:
10000 tp->nvram_jedecnum = JEDEC_SST;
10001 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
10006 tp->nvram_jedecnum = JEDEC_ATMEL;
10007 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
10008 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10012 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
10016 nvcfg1 = tr32(NVRAM_CFG1);
10018 /* NVRAM protection for TPM */
10019 if (nvcfg1 & (1 << 27))
10020 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10022 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10023 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
10024 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
10025 tp->nvram_jedecnum = JEDEC_ATMEL;
10026 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10028 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10029 tp->nvram_jedecnum = JEDEC_ATMEL;
10030 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10031 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10033 case FLASH_5752VENDOR_ST_M45PE10:
10034 case FLASH_5752VENDOR_ST_M45PE20:
10035 case FLASH_5752VENDOR_ST_M45PE40:
10036 tp->nvram_jedecnum = JEDEC_ST;
10037 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10038 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10042 if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
10043 switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
10044 case FLASH_5752PAGE_SIZE_256:
10045 tp->nvram_pagesize = 256;
10047 case FLASH_5752PAGE_SIZE_512:
10048 tp->nvram_pagesize = 512;
10050 case FLASH_5752PAGE_SIZE_1K:
10051 tp->nvram_pagesize = 1024;
10053 case FLASH_5752PAGE_SIZE_2K:
10054 tp->nvram_pagesize = 2048;
10056 case FLASH_5752PAGE_SIZE_4K:
10057 tp->nvram_pagesize = 4096;
10059 case FLASH_5752PAGE_SIZE_264:
10060 tp->nvram_pagesize = 264;
10065 /* For eeprom, set pagesize to maximum eeprom size */
10066 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10068 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10069 tw32(NVRAM_CFG1, nvcfg1);
10073 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
10075 u32 nvcfg1, protect = 0;
10077 nvcfg1 = tr32(NVRAM_CFG1);
10079 /* NVRAM protection for TPM */
10080 if (nvcfg1 & (1 << 27)) {
10081 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10085 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
10087 case FLASH_5755VENDOR_ATMEL_FLASH_1:
10088 case FLASH_5755VENDOR_ATMEL_FLASH_2:
10089 case FLASH_5755VENDOR_ATMEL_FLASH_3:
10090 case FLASH_5755VENDOR_ATMEL_FLASH_5:
10091 tp->nvram_jedecnum = JEDEC_ATMEL;
10092 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10093 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10094 tp->nvram_pagesize = 264;
10095 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
10096 nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
10097 tp->nvram_size = (protect ? 0x3e200 :
10098 TG3_NVRAM_SIZE_512KB);
10099 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
10100 tp->nvram_size = (protect ? 0x1f200 :
10101 TG3_NVRAM_SIZE_256KB);
10103 tp->nvram_size = (protect ? 0x1f200 :
10104 TG3_NVRAM_SIZE_128KB);
10106 case FLASH_5752VENDOR_ST_M45PE10:
10107 case FLASH_5752VENDOR_ST_M45PE20:
10108 case FLASH_5752VENDOR_ST_M45PE40:
10109 tp->nvram_jedecnum = JEDEC_ST;
10110 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10111 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10112 tp->nvram_pagesize = 256;
10113 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
10114 tp->nvram_size = (protect ?
10115 TG3_NVRAM_SIZE_64KB :
10116 TG3_NVRAM_SIZE_128KB);
10117 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
10118 tp->nvram_size = (protect ?
10119 TG3_NVRAM_SIZE_64KB :
10120 TG3_NVRAM_SIZE_256KB);
10122 tp->nvram_size = (protect ?
10123 TG3_NVRAM_SIZE_128KB :
10124 TG3_NVRAM_SIZE_512KB);
10129 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
10133 nvcfg1 = tr32(NVRAM_CFG1);
10135 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10136 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
10137 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
10138 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
10139 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
10140 tp->nvram_jedecnum = JEDEC_ATMEL;
10141 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10142 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10144 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10145 tw32(NVRAM_CFG1, nvcfg1);
10147 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10148 case FLASH_5755VENDOR_ATMEL_FLASH_1:
10149 case FLASH_5755VENDOR_ATMEL_FLASH_2:
10150 case FLASH_5755VENDOR_ATMEL_FLASH_3:
10151 tp->nvram_jedecnum = JEDEC_ATMEL;
10152 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10153 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10154 tp->nvram_pagesize = 264;
10156 case FLASH_5752VENDOR_ST_M45PE10:
10157 case FLASH_5752VENDOR_ST_M45PE20:
10158 case FLASH_5752VENDOR_ST_M45PE40:
10159 tp->nvram_jedecnum = JEDEC_ST;
10160 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10161 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10162 tp->nvram_pagesize = 256;
10167 static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
10169 u32 nvcfg1, protect = 0;
10171 nvcfg1 = tr32(NVRAM_CFG1);
10173 /* NVRAM protection for TPM */
10174 if (nvcfg1 & (1 << 27)) {
10175 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10179 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
10181 case FLASH_5761VENDOR_ATMEL_ADB021D:
10182 case FLASH_5761VENDOR_ATMEL_ADB041D:
10183 case FLASH_5761VENDOR_ATMEL_ADB081D:
10184 case FLASH_5761VENDOR_ATMEL_ADB161D:
10185 case FLASH_5761VENDOR_ATMEL_MDB021D:
10186 case FLASH_5761VENDOR_ATMEL_MDB041D:
10187 case FLASH_5761VENDOR_ATMEL_MDB081D:
10188 case FLASH_5761VENDOR_ATMEL_MDB161D:
10189 tp->nvram_jedecnum = JEDEC_ATMEL;
10190 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10191 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10192 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10193 tp->nvram_pagesize = 256;
10195 case FLASH_5761VENDOR_ST_A_M45PE20:
10196 case FLASH_5761VENDOR_ST_A_M45PE40:
10197 case FLASH_5761VENDOR_ST_A_M45PE80:
10198 case FLASH_5761VENDOR_ST_A_M45PE16:
10199 case FLASH_5761VENDOR_ST_M_M45PE20:
10200 case FLASH_5761VENDOR_ST_M_M45PE40:
10201 case FLASH_5761VENDOR_ST_M_M45PE80:
10202 case FLASH_5761VENDOR_ST_M_M45PE16:
10203 tp->nvram_jedecnum = JEDEC_ST;
10204 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10205 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10206 tp->nvram_pagesize = 256;
10211 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
10214 case FLASH_5761VENDOR_ATMEL_ADB161D:
10215 case FLASH_5761VENDOR_ATMEL_MDB161D:
10216 case FLASH_5761VENDOR_ST_A_M45PE16:
10217 case FLASH_5761VENDOR_ST_M_M45PE16:
10218 tp->nvram_size = TG3_NVRAM_SIZE_2MB;
10220 case FLASH_5761VENDOR_ATMEL_ADB081D:
10221 case FLASH_5761VENDOR_ATMEL_MDB081D:
10222 case FLASH_5761VENDOR_ST_A_M45PE80:
10223 case FLASH_5761VENDOR_ST_M_M45PE80:
10224 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
10226 case FLASH_5761VENDOR_ATMEL_ADB041D:
10227 case FLASH_5761VENDOR_ATMEL_MDB041D:
10228 case FLASH_5761VENDOR_ST_A_M45PE40:
10229 case FLASH_5761VENDOR_ST_M_M45PE40:
10230 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10232 case FLASH_5761VENDOR_ATMEL_ADB021D:
10233 case FLASH_5761VENDOR_ATMEL_MDB021D:
10234 case FLASH_5761VENDOR_ST_A_M45PE20:
10235 case FLASH_5761VENDOR_ST_M_M45PE20:
10236 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
10242 static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
10244 tp->nvram_jedecnum = JEDEC_ATMEL;
10245 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10246 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10249 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
10250 static void __devinit tg3_nvram_init(struct tg3 *tp)
10252 tw32_f(GRC_EEPROM_ADDR,
10253 (EEPROM_ADDR_FSM_RESET |
10254 (EEPROM_DEFAULT_CLOCK_PERIOD <<
10255 EEPROM_ADDR_CLKPERD_SHIFT)));
10259 /* Enable seeprom accesses. */
10260 tw32_f(GRC_LOCAL_CTRL,
10261 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
10264 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
10265 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
10266 tp->tg3_flags |= TG3_FLAG_NVRAM;
10268 if (tg3_nvram_lock(tp)) {
10269 printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
10270 "tg3_nvram_init failed.\n", tp->dev->name);
10273 tg3_enable_nvram_access(tp);
10275 tp->nvram_size = 0;
10277 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
10278 tg3_get_5752_nvram_info(tp);
10279 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
10280 tg3_get_5755_nvram_info(tp);
10281 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
10282 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784)
10283 tg3_get_5787_nvram_info(tp);
10284 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
10285 tg3_get_5761_nvram_info(tp);
10286 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10287 tg3_get_5906_nvram_info(tp);
10289 tg3_get_nvram_info(tp);
10291 if (tp->nvram_size == 0)
10292 tg3_get_nvram_size(tp);
10294 tg3_disable_nvram_access(tp);
10295 tg3_nvram_unlock(tp);
10298 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
10300 tg3_get_eeprom_size(tp);
10304 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
10305 u32 offset, u32 *val)
10310 if (offset > EEPROM_ADDR_ADDR_MASK ||
10314 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
10315 EEPROM_ADDR_DEVID_MASK |
10317 tw32(GRC_EEPROM_ADDR,
10319 (0 << EEPROM_ADDR_DEVID_SHIFT) |
10320 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
10321 EEPROM_ADDR_ADDR_MASK) |
10322 EEPROM_ADDR_READ | EEPROM_ADDR_START);
10324 for (i = 0; i < 1000; i++) {
10325 tmp = tr32(GRC_EEPROM_ADDR);
10327 if (tmp & EEPROM_ADDR_COMPLETE)
10331 if (!(tmp & EEPROM_ADDR_COMPLETE))
10334 *val = tr32(GRC_EEPROM_DATA);
10338 #define NVRAM_CMD_TIMEOUT 10000
10340 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
10344 tw32(NVRAM_CMD, nvram_cmd);
10345 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
10347 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
10352 if (i == NVRAM_CMD_TIMEOUT) {
10358 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
10360 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
10361 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
10362 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
10363 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
10364 (tp->nvram_jedecnum == JEDEC_ATMEL))
10366 addr = ((addr / tp->nvram_pagesize) <<
10367 ATMEL_AT45DB0X1B_PAGE_POS) +
10368 (addr % tp->nvram_pagesize);
10373 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
10375 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
10376 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
10377 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
10378 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
10379 (tp->nvram_jedecnum == JEDEC_ATMEL))
10381 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
10382 tp->nvram_pagesize) +
10383 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
10388 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
10392 if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
10393 return tg3_nvram_read_using_eeprom(tp, offset, val);
10395 offset = tg3_nvram_phys_addr(tp, offset);
10397 if (offset > NVRAM_ADDR_MSK)
10400 ret = tg3_nvram_lock(tp);
10404 tg3_enable_nvram_access(tp);
10406 tw32(NVRAM_ADDR, offset);
10407 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
10408 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
10411 *val = swab32(tr32(NVRAM_RDDATA));
10413 tg3_disable_nvram_access(tp);
10415 tg3_nvram_unlock(tp);
10420 static int tg3_nvram_read_le(struct tg3 *tp, u32 offset, __le32 *val)
10423 int res = tg3_nvram_read(tp, offset, &v);
10425 *val = cpu_to_le32(v);
10429 static int tg3_nvram_read_swab(struct tg3 *tp, u32 offset, u32 *val)
10434 err = tg3_nvram_read(tp, offset, &tmp);
10435 *val = swab32(tmp);
10439 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
10440 u32 offset, u32 len, u8 *buf)
10445 for (i = 0; i < len; i += 4) {
10451 memcpy(&data, buf + i, 4);
10453 tw32(GRC_EEPROM_DATA, le32_to_cpu(data));
10455 val = tr32(GRC_EEPROM_ADDR);
10456 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
10458 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
10460 tw32(GRC_EEPROM_ADDR, val |
10461 (0 << EEPROM_ADDR_DEVID_SHIFT) |
10462 (addr & EEPROM_ADDR_ADDR_MASK) |
10463 EEPROM_ADDR_START |
10464 EEPROM_ADDR_WRITE);
10466 for (j = 0; j < 1000; j++) {
10467 val = tr32(GRC_EEPROM_ADDR);
10469 if (val & EEPROM_ADDR_COMPLETE)
10473 if (!(val & EEPROM_ADDR_COMPLETE)) {
10482 /* offset and length are dword aligned */
10483 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
10487 u32 pagesize = tp->nvram_pagesize;
10488 u32 pagemask = pagesize - 1;
10492 tmp = kmalloc(pagesize, GFP_KERNEL);
10498 u32 phy_addr, page_off, size;
10500 phy_addr = offset & ~pagemask;
10502 for (j = 0; j < pagesize; j += 4) {
10503 if ((ret = tg3_nvram_read_le(tp, phy_addr + j,
10504 (__le32 *) (tmp + j))))
10510 page_off = offset & pagemask;
10517 memcpy(tmp + page_off, buf, size);
10519 offset = offset + (pagesize - page_off);
10521 tg3_enable_nvram_access(tp);
10524 * Before we can erase the flash page, we need
10525 * to issue a special "write enable" command.
10527 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
10529 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
10532 /* Erase the target page */
10533 tw32(NVRAM_ADDR, phy_addr);
10535 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
10536 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
10538 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
10541 /* Issue another write enable to start the write. */
10542 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
10544 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
10547 for (j = 0; j < pagesize; j += 4) {
10550 data = *((__be32 *) (tmp + j));
10551 /* swab32(le32_to_cpu(data)), actually */
10552 tw32(NVRAM_WRDATA, be32_to_cpu(data));
10554 tw32(NVRAM_ADDR, phy_addr + j);
10556 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
10560 nvram_cmd |= NVRAM_CMD_FIRST;
10561 else if (j == (pagesize - 4))
10562 nvram_cmd |= NVRAM_CMD_LAST;
10564 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
10571 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
10572 tg3_nvram_exec_cmd(tp, nvram_cmd);
10579 /* offset and length are dword aligned */
10580 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
10585 for (i = 0; i < len; i += 4, offset += 4) {
10586 u32 page_off, phy_addr, nvram_cmd;
10589 memcpy(&data, buf + i, 4);
10590 tw32(NVRAM_WRDATA, be32_to_cpu(data));
10592 page_off = offset % tp->nvram_pagesize;
10594 phy_addr = tg3_nvram_phys_addr(tp, offset);
10596 tw32(NVRAM_ADDR, phy_addr);
10598 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
10600 if ((page_off == 0) || (i == 0))
10601 nvram_cmd |= NVRAM_CMD_FIRST;
10602 if (page_off == (tp->nvram_pagesize - 4))
10603 nvram_cmd |= NVRAM_CMD_LAST;
10605 if (i == (len - 4))
10606 nvram_cmd |= NVRAM_CMD_LAST;
10608 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752) &&
10609 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5755) &&
10610 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787) &&
10611 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784) &&
10612 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) &&
10613 (tp->nvram_jedecnum == JEDEC_ST) &&
10614 (nvram_cmd & NVRAM_CMD_FIRST)) {
10616 if ((ret = tg3_nvram_exec_cmd(tp,
10617 NVRAM_CMD_WREN | NVRAM_CMD_GO |
10622 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
10623 /* We always do complete word writes to eeprom. */
10624 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
10627 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
10633 /* offset and length are dword aligned */
10634 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
10638 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
10639 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
10640 ~GRC_LCLCTRL_GPIO_OUTPUT1);
10644 if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
10645 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
10650 ret = tg3_nvram_lock(tp);
10654 tg3_enable_nvram_access(tp);
10655 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
10656 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM))
10657 tw32(NVRAM_WRITE1, 0x406);
10659 grc_mode = tr32(GRC_MODE);
10660 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
10662 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
10663 !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
10665 ret = tg3_nvram_write_block_buffered(tp, offset, len,
10669 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
10673 grc_mode = tr32(GRC_MODE);
10674 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
10676 tg3_disable_nvram_access(tp);
10677 tg3_nvram_unlock(tp);
10680 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
10681 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
10688 struct subsys_tbl_ent {
10689 u16 subsys_vendor, subsys_devid;
10693 static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
10694 /* Broadcom boards. */
10695 { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
10696 { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
10697 { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
10698 { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 }, /* BCM95700A9 */
10699 { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
10700 { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
10701 { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 }, /* BCM95701A7 */
10702 { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
10703 { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
10704 { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
10705 { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
10708 { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
10709 { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
10710 { PCI_VENDOR_ID_3COM, 0x1004, 0 }, /* 3C996SX */
10711 { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
10712 { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
10715 { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
10716 { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
10717 { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
10718 { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
10720 /* Compaq boards. */
10721 { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
10722 { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
10723 { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 }, /* CHANGELING */
10724 { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
10725 { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
10728 { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
10731 static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
10735 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
10736 if ((subsys_id_to_phy_id[i].subsys_vendor ==
10737 tp->pdev->subsystem_vendor) &&
10738 (subsys_id_to_phy_id[i].subsys_devid ==
10739 tp->pdev->subsystem_device))
10740 return &subsys_id_to_phy_id[i];
10745 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
10750 /* On some early chips the SRAM cannot be accessed in D3hot state,
10751 * so need make sure we're in D0.
10753 pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
10754 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
10755 pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
10758 /* Make sure register accesses (indirect or otherwise)
10759 * will function correctly.
10761 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
10762 tp->misc_host_ctrl);
10764 /* The memory arbiter has to be enabled in order for SRAM accesses
10765 * to succeed. Normally on powerup the tg3 chip firmware will make
10766 * sure it is enabled, but other entities such as system netboot
10767 * code might disable it.
10769 val = tr32(MEMARB_MODE);
10770 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
10772 tp->phy_id = PHY_ID_INVALID;
10773 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
10775 /* Assume an onboard device and WOL capable by default. */
10776 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
10778 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
10779 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
10780 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
10781 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
10783 val = tr32(VCPU_CFGSHDW);
10784 if (val & VCPU_CFGSHDW_ASPM_DBNC)
10785 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
10786 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
10787 (val & VCPU_CFGSHDW_WOL_MAGPKT))
10788 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
10792 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
10793 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
10794 u32 nic_cfg, led_cfg;
10795 u32 nic_phy_id, ver, cfg2 = 0, eeprom_phy_id;
10796 int eeprom_phy_serdes = 0;
10798 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
10799 tp->nic_sram_data_cfg = nic_cfg;
10801 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
10802 ver >>= NIC_SRAM_DATA_VER_SHIFT;
10803 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
10804 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
10805 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
10806 (ver > 0) && (ver < 0x100))
10807 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
10809 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
10810 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
10811 eeprom_phy_serdes = 1;
10813 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
10814 if (nic_phy_id != 0) {
10815 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
10816 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
10818 eeprom_phy_id = (id1 >> 16) << 10;
10819 eeprom_phy_id |= (id2 & 0xfc00) << 16;
10820 eeprom_phy_id |= (id2 & 0x03ff) << 0;
10824 tp->phy_id = eeprom_phy_id;
10825 if (eeprom_phy_serdes) {
10826 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
10827 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
10829 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
10832 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10833 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
10834 SHASTA_EXT_LED_MODE_MASK);
10836 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
10840 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
10841 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
10844 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
10845 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
10848 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
10849 tp->led_ctrl = LED_CTRL_MODE_MAC;
10851 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
10852 * read on some older 5700/5701 bootcode.
10854 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
10856 GET_ASIC_REV(tp->pci_chip_rev_id) ==
10858 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
10862 case SHASTA_EXT_LED_SHARED:
10863 tp->led_ctrl = LED_CTRL_MODE_SHARED;
10864 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
10865 tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
10866 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
10867 LED_CTRL_MODE_PHY_2);
10870 case SHASTA_EXT_LED_MAC:
10871 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
10874 case SHASTA_EXT_LED_COMBO:
10875 tp->led_ctrl = LED_CTRL_MODE_COMBO;
10876 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
10877 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
10878 LED_CTRL_MODE_PHY_2);
10883 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
10884 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
10885 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
10886 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
10888 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
10889 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
10891 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
10892 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
10893 if ((tp->pdev->subsystem_vendor ==
10894 PCI_VENDOR_ID_ARIMA) &&
10895 (tp->pdev->subsystem_device == 0x205a ||
10896 tp->pdev->subsystem_device == 0x2063))
10897 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
10899 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
10900 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
10903 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
10904 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
10905 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10906 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
10908 if (nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE)
10909 tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
10910 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
10911 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
10912 tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
10914 if (tp->tg3_flags & TG3_FLAG_WOL_CAP &&
10915 nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE)
10916 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
10918 if (cfg2 & (1 << 17))
10919 tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
10921 /* serdes signal pre-emphasis in register 0x590 set by */
10922 /* bootcode if bit 18 is set */
10923 if (cfg2 & (1 << 18))
10924 tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
10926 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
10929 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
10930 if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
10931 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
10936 static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
10941 tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
10942 tw32(OTP_CTRL, cmd);
10944 /* Wait for up to 1 ms for command to execute. */
10945 for (i = 0; i < 100; i++) {
10946 val = tr32(OTP_STATUS);
10947 if (val & OTP_STATUS_CMD_DONE)
10952 return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
10955 /* Read the gphy configuration from the OTP region of the chip. The gphy
10956 * configuration is a 32-bit value that straddles the alignment boundary.
10957 * We do two 32-bit reads and then shift and merge the results.
10959 static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
10961 u32 bhalf_otp, thalf_otp;
10963 tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
10965 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
10968 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
10970 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
10973 thalf_otp = tr32(OTP_READ_DATA);
10975 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
10977 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
10980 bhalf_otp = tr32(OTP_READ_DATA);
10982 return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
10985 static int __devinit tg3_phy_probe(struct tg3 *tp)
10987 u32 hw_phy_id_1, hw_phy_id_2;
10988 u32 hw_phy_id, hw_phy_id_masked;
10991 /* Reading the PHY ID register can conflict with ASF
10992 * firwmare access to the PHY hardware.
10995 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
10996 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
10997 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
10999 /* Now read the physical PHY_ID from the chip and verify
11000 * that it is sane. If it doesn't look good, we fall back
11001 * to either the hard-coded table based PHY_ID and failing
11002 * that the value found in the eeprom area.
11004 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
11005 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
11007 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
11008 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
11009 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
11011 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
11014 if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
11015 tp->phy_id = hw_phy_id;
11016 if (hw_phy_id_masked == PHY_ID_BCM8002)
11017 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11019 tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
11021 if (tp->phy_id != PHY_ID_INVALID) {
11022 /* Do nothing, phy ID already set up in
11023 * tg3_get_eeprom_hw_cfg().
11026 struct subsys_tbl_ent *p;
11028 /* No eeprom signature? Try the hardcoded
11029 * subsys device table.
11031 p = lookup_by_subsys(tp);
11035 tp->phy_id = p->phy_id;
11037 tp->phy_id == PHY_ID_BCM8002)
11038 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11042 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
11043 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
11044 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
11045 u32 bmsr, adv_reg, tg3_ctrl, mask;
11047 tg3_readphy(tp, MII_BMSR, &bmsr);
11048 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
11049 (bmsr & BMSR_LSTATUS))
11050 goto skip_phy_reset;
11052 err = tg3_phy_reset(tp);
11056 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
11057 ADVERTISE_100HALF | ADVERTISE_100FULL |
11058 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
11060 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
11061 tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
11062 MII_TG3_CTRL_ADV_1000_FULL);
11063 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
11064 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
11065 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
11066 MII_TG3_CTRL_ENABLE_AS_MASTER);
11069 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
11070 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
11071 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
11072 if (!tg3_copper_is_advertising_all(tp, mask)) {
11073 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
11075 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
11076 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
11078 tg3_writephy(tp, MII_BMCR,
11079 BMCR_ANENABLE | BMCR_ANRESTART);
11081 tg3_phy_set_wirespeed(tp);
11083 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
11084 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
11085 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
11089 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
11090 err = tg3_init_5401phy_dsp(tp);
11095 if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
11096 err = tg3_init_5401phy_dsp(tp);
11099 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
11100 tp->link_config.advertising =
11101 (ADVERTISED_1000baseT_Half |
11102 ADVERTISED_1000baseT_Full |
11103 ADVERTISED_Autoneg |
11105 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
11106 tp->link_config.advertising &=
11107 ~(ADVERTISED_1000baseT_Half |
11108 ADVERTISED_1000baseT_Full);
11113 static void __devinit tg3_read_partno(struct tg3 *tp)
11115 unsigned char vpd_data[256];
11119 if (tg3_nvram_read_swab(tp, 0x0, &magic))
11120 goto out_not_found;
11122 if (magic == TG3_EEPROM_MAGIC) {
11123 for (i = 0; i < 256; i += 4) {
11126 if (tg3_nvram_read(tp, 0x100 + i, &tmp))
11127 goto out_not_found;
11129 vpd_data[i + 0] = ((tmp >> 0) & 0xff);
11130 vpd_data[i + 1] = ((tmp >> 8) & 0xff);
11131 vpd_data[i + 2] = ((tmp >> 16) & 0xff);
11132 vpd_data[i + 3] = ((tmp >> 24) & 0xff);
11137 vpd_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_VPD);
11138 for (i = 0; i < 256; i += 4) {
11143 pci_write_config_word(tp->pdev, vpd_cap + PCI_VPD_ADDR,
11145 while (j++ < 100) {
11146 pci_read_config_word(tp->pdev, vpd_cap +
11147 PCI_VPD_ADDR, &tmp16);
11148 if (tmp16 & 0x8000)
11152 if (!(tmp16 & 0x8000))
11153 goto out_not_found;
11155 pci_read_config_dword(tp->pdev, vpd_cap + PCI_VPD_DATA,
11157 v = cpu_to_le32(tmp);
11158 memcpy(&vpd_data[i], &v, 4);
11162 /* Now parse and find the part number. */
11163 for (i = 0; i < 254; ) {
11164 unsigned char val = vpd_data[i];
11165 unsigned int block_end;
11167 if (val == 0x82 || val == 0x91) {
11170 (vpd_data[i + 2] << 8)));
11175 goto out_not_found;
11177 block_end = (i + 3 +
11179 (vpd_data[i + 2] << 8)));
11182 if (block_end > 256)
11183 goto out_not_found;
11185 while (i < (block_end - 2)) {
11186 if (vpd_data[i + 0] == 'P' &&
11187 vpd_data[i + 1] == 'N') {
11188 int partno_len = vpd_data[i + 2];
11191 if (partno_len > 24 || (partno_len + i) > 256)
11192 goto out_not_found;
11194 memcpy(tp->board_part_number,
11195 &vpd_data[i], partno_len);
11200 i += 3 + vpd_data[i + 2];
11203 /* Part number not found. */
11204 goto out_not_found;
11208 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11209 strcpy(tp->board_part_number, "BCM95906");
11211 strcpy(tp->board_part_number, "none");
11214 static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
11218 if (tg3_nvram_read_swab(tp, offset, &val) ||
11219 (val & 0xfc000000) != 0x0c000000 ||
11220 tg3_nvram_read_swab(tp, offset + 4, &val) ||
11227 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
11229 u32 val, offset, start;
11233 if (tg3_nvram_read_swab(tp, 0, &val))
11236 if (val != TG3_EEPROM_MAGIC)
11239 if (tg3_nvram_read_swab(tp, 0xc, &offset) ||
11240 tg3_nvram_read_swab(tp, 0x4, &start))
11243 offset = tg3_nvram_logical_addr(tp, offset);
11245 if (!tg3_fw_img_is_valid(tp, offset) ||
11246 tg3_nvram_read_swab(tp, offset + 8, &ver_offset))
11249 offset = offset + ver_offset - start;
11250 for (i = 0; i < 16; i += 4) {
11252 if (tg3_nvram_read_le(tp, offset + i, &v))
11255 memcpy(tp->fw_ver + i, &v, 4);
11258 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
11259 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
11262 for (offset = TG3_NVM_DIR_START;
11263 offset < TG3_NVM_DIR_END;
11264 offset += TG3_NVM_DIRENT_SIZE) {
11265 if (tg3_nvram_read_swab(tp, offset, &val))
11268 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
11272 if (offset == TG3_NVM_DIR_END)
11275 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
11276 start = 0x08000000;
11277 else if (tg3_nvram_read_swab(tp, offset - 4, &start))
11280 if (tg3_nvram_read_swab(tp, offset + 4, &offset) ||
11281 !tg3_fw_img_is_valid(tp, offset) ||
11282 tg3_nvram_read_swab(tp, offset + 8, &val))
11285 offset += val - start;
11287 bcnt = strlen(tp->fw_ver);
11289 tp->fw_ver[bcnt++] = ',';
11290 tp->fw_ver[bcnt++] = ' ';
11292 for (i = 0; i < 4; i++) {
11294 if (tg3_nvram_read_le(tp, offset, &v))
11297 offset += sizeof(v);
11299 if (bcnt > TG3_VER_SIZE - sizeof(v)) {
11300 memcpy(&tp->fw_ver[bcnt], &v, TG3_VER_SIZE - bcnt);
11304 memcpy(&tp->fw_ver[bcnt], &v, sizeof(v));
11308 tp->fw_ver[TG3_VER_SIZE - 1] = 0;
11311 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
11313 static int __devinit tg3_get_invariants(struct tg3 *tp)
11315 static struct pci_device_id write_reorder_chipsets[] = {
11316 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
11317 PCI_DEVICE_ID_AMD_FE_GATE_700C) },
11318 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
11319 PCI_DEVICE_ID_AMD_8131_BRIDGE) },
11320 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
11321 PCI_DEVICE_ID_VIA_8385_0) },
11325 u32 cacheline_sz_reg;
11326 u32 pci_state_reg, grc_misc_cfg;
11331 /* Force memory write invalidate off. If we leave it on,
11332 * then on 5700_BX chips we have to enable a workaround.
11333 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
11334 * to match the cacheline size. The Broadcom driver have this
11335 * workaround but turns MWI off all the times so never uses
11336 * it. This seems to suggest that the workaround is insufficient.
11338 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
11339 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
11340 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
11342 /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
11343 * has the register indirect write enable bit set before
11344 * we try to access any of the MMIO registers. It is also
11345 * critical that the PCI-X hw workaround situation is decided
11346 * before that as well.
11348 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11351 tp->pci_chip_rev_id = (misc_ctrl_reg >>
11352 MISC_HOST_CTRL_CHIPREV_SHIFT);
11353 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
11354 u32 prod_id_asic_rev;
11356 pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
11357 &prod_id_asic_rev);
11358 tp->pci_chip_rev_id = prod_id_asic_rev & PROD_ID_ASIC_REV_MASK;
11361 /* Wrong chip ID in 5752 A0. This code can be removed later
11362 * as A0 is not in production.
11364 if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
11365 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
11367 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
11368 * we need to disable memory and use config. cycles
11369 * only to access all registers. The 5702/03 chips
11370 * can mistakenly decode the special cycles from the
11371 * ICH chipsets as memory write cycles, causing corruption
11372 * of register and memory space. Only certain ICH bridges
11373 * will drive special cycles with non-zero data during the
11374 * address phase which can fall within the 5703's address
11375 * range. This is not an ICH bug as the PCI spec allows
11376 * non-zero address during special cycles. However, only
11377 * these ICH bridges are known to drive non-zero addresses
11378 * during special cycles.
11380 * Since special cycles do not cross PCI bridges, we only
11381 * enable this workaround if the 5703 is on the secondary
11382 * bus of these ICH bridges.
11384 if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
11385 (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
11386 static struct tg3_dev_id {
11390 } ich_chipsets[] = {
11391 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
11393 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
11395 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
11397 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
11401 struct tg3_dev_id *pci_id = &ich_chipsets[0];
11402 struct pci_dev *bridge = NULL;
11404 while (pci_id->vendor != 0) {
11405 bridge = pci_get_device(pci_id->vendor, pci_id->device,
11411 if (pci_id->rev != PCI_ANY_ID) {
11412 if (bridge->revision > pci_id->rev)
11415 if (bridge->subordinate &&
11416 (bridge->subordinate->number ==
11417 tp->pdev->bus->number)) {
11419 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
11420 pci_dev_put(bridge);
11426 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
11427 static struct tg3_dev_id {
11430 } bridge_chipsets[] = {
11431 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
11432 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
11435 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
11436 struct pci_dev *bridge = NULL;
11438 while (pci_id->vendor != 0) {
11439 bridge = pci_get_device(pci_id->vendor,
11446 if (bridge->subordinate &&
11447 (bridge->subordinate->number <=
11448 tp->pdev->bus->number) &&
11449 (bridge->subordinate->subordinate >=
11450 tp->pdev->bus->number)) {
11451 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
11452 pci_dev_put(bridge);
11458 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
11459 * DMA addresses > 40-bit. This bridge may have other additional
11460 * 57xx devices behind it in some 4-port NIC designs for example.
11461 * Any tg3 device found behind the bridge will also need the 40-bit
11464 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
11465 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
11466 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
11467 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
11468 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
11471 struct pci_dev *bridge = NULL;
11474 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
11475 PCI_DEVICE_ID_SERVERWORKS_EPB,
11477 if (bridge && bridge->subordinate &&
11478 (bridge->subordinate->number <=
11479 tp->pdev->bus->number) &&
11480 (bridge->subordinate->subordinate >=
11481 tp->pdev->bus->number)) {
11482 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
11483 pci_dev_put(bridge);
11489 /* Initialize misc host control in PCI block. */
11490 tp->misc_host_ctrl |= (misc_ctrl_reg &
11491 MISC_HOST_CTRL_CHIPREV);
11492 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11493 tp->misc_host_ctrl);
11495 pci_read_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
11496 &cacheline_sz_reg);
11498 tp->pci_cacheline_sz = (cacheline_sz_reg >> 0) & 0xff;
11499 tp->pci_lat_timer = (cacheline_sz_reg >> 8) & 0xff;
11500 tp->pci_hdr_type = (cacheline_sz_reg >> 16) & 0xff;
11501 tp->pci_bist = (cacheline_sz_reg >> 24) & 0xff;
11503 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
11504 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714))
11505 tp->pdev_peer = tg3_find_peer(tp);
11507 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
11508 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
11509 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
11510 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
11511 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11512 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
11513 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
11514 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
11515 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
11517 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
11518 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
11519 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
11521 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
11522 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
11523 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
11524 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
11525 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
11526 tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
11527 tp->pdev_peer == tp->pdev))
11528 tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
11530 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
11531 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
11532 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11533 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
11534 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
11535 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
11536 tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
11538 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
11539 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
11541 tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
11542 tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
11546 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 &&
11547 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750 &&
11548 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
11549 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5755 &&
11550 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787 &&
11551 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
11552 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761 &&
11553 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
11554 tp->tg3_flags2 |= TG3_FLG2_JUMBO_CAPABLE;
11556 pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
11557 if (pcie_cap != 0) {
11558 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
11560 pcie_set_readrq(tp->pdev, 4096);
11562 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
11565 pci_read_config_word(tp->pdev,
11566 pcie_cap + PCI_EXP_LNKCTL,
11568 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN)
11569 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
11573 /* If we have an AMD 762 or VIA K8T800 chipset, write
11574 * reordering to the mailbox registers done by the host
11575 * controller can cause major troubles. We read back from
11576 * every mailbox register write to force the writes to be
11577 * posted to the chip in order.
11579 if (pci_dev_present(write_reorder_chipsets) &&
11580 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
11581 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
11583 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
11584 tp->pci_lat_timer < 64) {
11585 tp->pci_lat_timer = 64;
11587 cacheline_sz_reg = ((tp->pci_cacheline_sz & 0xff) << 0);
11588 cacheline_sz_reg |= ((tp->pci_lat_timer & 0xff) << 8);
11589 cacheline_sz_reg |= ((tp->pci_hdr_type & 0xff) << 16);
11590 cacheline_sz_reg |= ((tp->pci_bist & 0xff) << 24);
11592 pci_write_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
11596 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
11597 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
11598 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
11599 if (!tp->pcix_cap) {
11600 printk(KERN_ERR PFX "Cannot find PCI-X "
11601 "capability, aborting.\n");
11606 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
11609 if (tp->pcix_cap && (pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0) {
11610 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
11612 /* If this is a 5700 BX chipset, and we are in PCI-X
11613 * mode, enable register write workaround.
11615 * The workaround is to use indirect register accesses
11616 * for all chip writes not to mailbox registers.
11618 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
11621 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
11623 /* The chip can have it's power management PCI config
11624 * space registers clobbered due to this bug.
11625 * So explicitly force the chip into D0 here.
11627 pci_read_config_dword(tp->pdev,
11628 tp->pm_cap + PCI_PM_CTRL,
11630 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
11631 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
11632 pci_write_config_dword(tp->pdev,
11633 tp->pm_cap + PCI_PM_CTRL,
11636 /* Also, force SERR#/PERR# in PCI command. */
11637 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
11638 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
11639 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
11643 /* 5700 BX chips need to have their TX producer index mailboxes
11644 * written twice to workaround a bug.
11646 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX)
11647 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
11649 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
11650 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
11651 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
11652 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
11654 /* Chip-specific fixup from Broadcom driver */
11655 if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
11656 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
11657 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
11658 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
11661 /* Default fast path register access methods */
11662 tp->read32 = tg3_read32;
11663 tp->write32 = tg3_write32;
11664 tp->read32_mbox = tg3_read32;
11665 tp->write32_mbox = tg3_write32;
11666 tp->write32_tx_mbox = tg3_write32;
11667 tp->write32_rx_mbox = tg3_write32;
11669 /* Various workaround register access methods */
11670 if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
11671 tp->write32 = tg3_write_indirect_reg32;
11672 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
11673 ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
11674 tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
11676 * Back to back register writes can cause problems on these
11677 * chips, the workaround is to read back all reg writes
11678 * except those to mailbox regs.
11680 * See tg3_write_indirect_reg32().
11682 tp->write32 = tg3_write_flush_reg32;
11686 if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
11687 (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
11688 tp->write32_tx_mbox = tg3_write32_tx_mbox;
11689 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
11690 tp->write32_rx_mbox = tg3_write_flush_reg32;
11693 if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
11694 tp->read32 = tg3_read_indirect_reg32;
11695 tp->write32 = tg3_write_indirect_reg32;
11696 tp->read32_mbox = tg3_read_indirect_mbox;
11697 tp->write32_mbox = tg3_write_indirect_mbox;
11698 tp->write32_tx_mbox = tg3_write_indirect_mbox;
11699 tp->write32_rx_mbox = tg3_write_indirect_mbox;
11704 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
11705 pci_cmd &= ~PCI_COMMAND_MEMORY;
11706 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
11708 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
11709 tp->read32_mbox = tg3_read32_mbox_5906;
11710 tp->write32_mbox = tg3_write32_mbox_5906;
11711 tp->write32_tx_mbox = tg3_write32_mbox_5906;
11712 tp->write32_rx_mbox = tg3_write32_mbox_5906;
11715 if (tp->write32 == tg3_write_indirect_reg32 ||
11716 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
11717 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11718 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
11719 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
11721 /* Get eeprom hw config before calling tg3_set_power_state().
11722 * In particular, the TG3_FLG2_IS_NIC flag must be
11723 * determined before calling tg3_set_power_state() so that
11724 * we know whether or not to switch out of Vaux power.
11725 * When the flag is set, it means that GPIO1 is used for eeprom
11726 * write protect and also implies that it is a LOM where GPIOs
11727 * are not used to switch power.
11729 tg3_get_eeprom_hw_cfg(tp);
11731 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
11732 /* Allow reads and writes to the
11733 * APE register and memory space.
11735 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
11736 PCISTATE_ALLOW_APE_SHMEM_WR;
11737 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
11741 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11742 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
11743 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
11745 if (tp->pci_chip_rev_id == CHIPREV_ID_5784_A0 ||
11746 tp->pci_chip_rev_id == CHIPREV_ID_5784_A1 ||
11747 tp->pci_chip_rev_id == CHIPREV_ID_5761_A0 ||
11748 tp->pci_chip_rev_id == CHIPREV_ID_5761_A1)
11749 tp->tg3_flags3 |= TG3_FLG3_5761_5784_AX_FIXES;
11752 /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
11753 * GPIO1 driven high will bring 5700's external PHY out of reset.
11754 * It is also used as eeprom write protect on LOMs.
11756 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
11757 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
11758 (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
11759 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
11760 GRC_LCLCTRL_GPIO_OUTPUT1);
11761 /* Unused GPIO3 must be driven as output on 5752 because there
11762 * are no pull-up resistors on unused GPIO pins.
11764 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
11765 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
11767 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
11768 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
11770 /* Force the chip into D0. */
11771 err = tg3_set_power_state(tp, PCI_D0);
11773 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
11774 pci_name(tp->pdev));
11778 /* 5700 B0 chips do not support checksumming correctly due
11779 * to hardware bugs.
11781 if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
11782 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
11784 /* Derive initial jumbo mode from MTU assigned in
11785 * ether_setup() via the alloc_etherdev() call
11787 if (tp->dev->mtu > ETH_DATA_LEN &&
11788 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
11789 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
11791 /* Determine WakeOnLan speed to use. */
11792 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11793 tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
11794 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
11795 tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
11796 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
11798 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
11801 /* A few boards don't want Ethernet@WireSpeed phy feature */
11802 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
11803 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
11804 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
11805 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
11806 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) ||
11807 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
11808 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
11810 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
11811 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
11812 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
11813 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
11814 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
11816 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
11817 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
11818 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
11819 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11820 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
11821 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
11822 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
11823 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
11824 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
11825 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
11826 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
11827 tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
11830 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
11831 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
11832 tp->phy_otp = tg3_read_otp_phycfg(tp);
11833 if (tp->phy_otp == 0)
11834 tp->phy_otp = TG3_OTP_DEFAULT;
11837 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11838 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
11839 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
11841 tp->mi_mode = MAC_MI_MODE_BASE;
11843 tp->coalesce_mode = 0;
11844 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
11845 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
11846 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
11848 /* Initialize MAC MI mode, polling disabled. */
11849 tw32_f(MAC_MI_MODE, tp->mi_mode);
11852 /* Initialize data/descriptor byte/word swapping. */
11853 val = tr32(GRC_MODE);
11854 val &= GRC_MODE_HOST_STACKUP;
11855 tw32(GRC_MODE, val | tp->grc_mode);
11857 tg3_switch_clocks(tp);
11859 /* Clear this out for sanity. */
11860 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
11862 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
11864 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
11865 (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
11866 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
11868 if (chiprevid == CHIPREV_ID_5701_A0 ||
11869 chiprevid == CHIPREV_ID_5701_B0 ||
11870 chiprevid == CHIPREV_ID_5701_B2 ||
11871 chiprevid == CHIPREV_ID_5701_B5) {
11872 void __iomem *sram_base;
11874 /* Write some dummy words into the SRAM status block
11875 * area, see if it reads back correctly. If the return
11876 * value is bad, force enable the PCIX workaround.
11878 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
11880 writel(0x00000000, sram_base);
11881 writel(0x00000000, sram_base + 4);
11882 writel(0xffffffff, sram_base + 4);
11883 if (readl(sram_base) != 0x00000000)
11884 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
11889 tg3_nvram_init(tp);
11891 grc_misc_cfg = tr32(GRC_MISC_CFG);
11892 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
11894 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
11895 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
11896 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
11897 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
11899 if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
11900 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
11901 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
11902 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
11903 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
11904 HOSTCC_MODE_CLRTICK_TXBD);
11906 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
11907 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11908 tp->misc_host_ctrl);
11911 /* these are limited to 10/100 only */
11912 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
11913 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
11914 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
11915 tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
11916 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
11917 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
11918 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
11919 (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
11920 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
11921 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
11922 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
11923 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11924 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
11926 err = tg3_phy_probe(tp);
11928 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
11929 pci_name(tp->pdev), err);
11930 /* ... but do not return immediately ... */
11933 tg3_read_partno(tp);
11934 tg3_read_fw_ver(tp);
11936 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
11937 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
11939 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
11940 tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
11942 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
11945 /* 5700 {AX,BX} chips have a broken status block link
11946 * change bit implementation, so we must use the
11947 * status register in those cases.
11949 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
11950 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
11952 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
11954 /* The led_ctrl is set during tg3_phy_probe, here we might
11955 * have to force the link status polling mechanism based
11956 * upon subsystem IDs.
11958 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
11959 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
11960 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
11961 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
11962 TG3_FLAG_USE_LINKCHG_REG);
11965 /* For all SERDES we poll the MAC status register. */
11966 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
11967 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
11969 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
11971 /* All chips before 5787 can get confused if TX buffers
11972 * straddle the 4GB address boundary in some cases.
11974 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
11975 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
11976 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11977 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
11978 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11979 tp->dev->hard_start_xmit = tg3_start_xmit;
11981 tp->dev->hard_start_xmit = tg3_start_xmit_dma_bug;
11984 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
11985 (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
11988 tp->rx_std_max_post = TG3_RX_RING_SIZE;
11990 /* Increment the rx prod index on the rx std ring by at most
11991 * 8 for these chips to workaround hw errata.
11993 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
11994 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
11995 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
11996 tp->rx_std_max_post = 8;
11998 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
11999 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
12000 PCIE_PWR_MGMT_L1_THRESH_MSK;
12005 #ifdef CONFIG_SPARC
12006 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
12008 struct net_device *dev = tp->dev;
12009 struct pci_dev *pdev = tp->pdev;
12010 struct device_node *dp = pci_device_to_OF_node(pdev);
12011 const unsigned char *addr;
12014 addr = of_get_property(dp, "local-mac-address", &len);
12015 if (addr && len == 6) {
12016 memcpy(dev->dev_addr, addr, 6);
12017 memcpy(dev->perm_addr, dev->dev_addr, 6);
12023 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
12025 struct net_device *dev = tp->dev;
12027 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
12028 memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
12033 static int __devinit tg3_get_device_address(struct tg3 *tp)
12035 struct net_device *dev = tp->dev;
12036 u32 hi, lo, mac_offset;
12039 #ifdef CONFIG_SPARC
12040 if (!tg3_get_macaddr_sparc(tp))
12045 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
12046 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
12047 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
12049 if (tg3_nvram_lock(tp))
12050 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
12052 tg3_nvram_unlock(tp);
12054 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12057 /* First try to get it from MAC address mailbox. */
12058 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
12059 if ((hi >> 16) == 0x484b) {
12060 dev->dev_addr[0] = (hi >> 8) & 0xff;
12061 dev->dev_addr[1] = (hi >> 0) & 0xff;
12063 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
12064 dev->dev_addr[2] = (lo >> 24) & 0xff;
12065 dev->dev_addr[3] = (lo >> 16) & 0xff;
12066 dev->dev_addr[4] = (lo >> 8) & 0xff;
12067 dev->dev_addr[5] = (lo >> 0) & 0xff;
12069 /* Some old bootcode may report a 0 MAC address in SRAM */
12070 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
12073 /* Next, try NVRAM. */
12074 if (!tg3_nvram_read(tp, mac_offset + 0, &hi) &&
12075 !tg3_nvram_read(tp, mac_offset + 4, &lo)) {
12076 dev->dev_addr[0] = ((hi >> 16) & 0xff);
12077 dev->dev_addr[1] = ((hi >> 24) & 0xff);
12078 dev->dev_addr[2] = ((lo >> 0) & 0xff);
12079 dev->dev_addr[3] = ((lo >> 8) & 0xff);
12080 dev->dev_addr[4] = ((lo >> 16) & 0xff);
12081 dev->dev_addr[5] = ((lo >> 24) & 0xff);
12083 /* Finally just fetch it out of the MAC control regs. */
12085 hi = tr32(MAC_ADDR_0_HIGH);
12086 lo = tr32(MAC_ADDR_0_LOW);
12088 dev->dev_addr[5] = lo & 0xff;
12089 dev->dev_addr[4] = (lo >> 8) & 0xff;
12090 dev->dev_addr[3] = (lo >> 16) & 0xff;
12091 dev->dev_addr[2] = (lo >> 24) & 0xff;
12092 dev->dev_addr[1] = hi & 0xff;
12093 dev->dev_addr[0] = (hi >> 8) & 0xff;
12097 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
12098 #ifdef CONFIG_SPARC
12099 if (!tg3_get_default_macaddr_sparc(tp))
12104 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
12108 #define BOUNDARY_SINGLE_CACHELINE 1
12109 #define BOUNDARY_MULTI_CACHELINE 2
12111 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
12113 int cacheline_size;
12117 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
12119 cacheline_size = 1024;
12121 cacheline_size = (int) byte * 4;
12123 /* On 5703 and later chips, the boundary bits have no
12126 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
12127 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
12128 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
12131 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
12132 goal = BOUNDARY_MULTI_CACHELINE;
12134 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
12135 goal = BOUNDARY_SINGLE_CACHELINE;
12144 /* PCI controllers on most RISC systems tend to disconnect
12145 * when a device tries to burst across a cache-line boundary.
12146 * Therefore, letting tg3 do so just wastes PCI bandwidth.
12148 * Unfortunately, for PCI-E there are only limited
12149 * write-side controls for this, and thus for reads
12150 * we will still get the disconnects. We'll also waste
12151 * these PCI cycles for both read and write for chips
12152 * other than 5700 and 5701 which do not implement the
12155 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
12156 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
12157 switch (cacheline_size) {
12162 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12163 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
12164 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
12166 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
12167 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
12172 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
12173 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
12177 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
12178 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
12181 } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12182 switch (cacheline_size) {
12186 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12187 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
12188 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
12194 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
12195 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
12199 switch (cacheline_size) {
12201 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12202 val |= (DMA_RWCTRL_READ_BNDRY_16 |
12203 DMA_RWCTRL_WRITE_BNDRY_16);
12208 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12209 val |= (DMA_RWCTRL_READ_BNDRY_32 |
12210 DMA_RWCTRL_WRITE_BNDRY_32);
12215 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12216 val |= (DMA_RWCTRL_READ_BNDRY_64 |
12217 DMA_RWCTRL_WRITE_BNDRY_64);
12222 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12223 val |= (DMA_RWCTRL_READ_BNDRY_128 |
12224 DMA_RWCTRL_WRITE_BNDRY_128);
12229 val |= (DMA_RWCTRL_READ_BNDRY_256 |
12230 DMA_RWCTRL_WRITE_BNDRY_256);
12233 val |= (DMA_RWCTRL_READ_BNDRY_512 |
12234 DMA_RWCTRL_WRITE_BNDRY_512);
12238 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
12239 DMA_RWCTRL_WRITE_BNDRY_1024);
12248 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
12250 struct tg3_internal_buffer_desc test_desc;
12251 u32 sram_dma_descs;
12254 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
12256 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
12257 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
12258 tw32(RDMAC_STATUS, 0);
12259 tw32(WDMAC_STATUS, 0);
12261 tw32(BUFMGR_MODE, 0);
12262 tw32(FTQ_RESET, 0);
12264 test_desc.addr_hi = ((u64) buf_dma) >> 32;
12265 test_desc.addr_lo = buf_dma & 0xffffffff;
12266 test_desc.nic_mbuf = 0x00002100;
12267 test_desc.len = size;
12270 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
12271 * the *second* time the tg3 driver was getting loaded after an
12274 * Broadcom tells me:
12275 * ...the DMA engine is connected to the GRC block and a DMA
12276 * reset may affect the GRC block in some unpredictable way...
12277 * The behavior of resets to individual blocks has not been tested.
12279 * Broadcom noted the GRC reset will also reset all sub-components.
12282 test_desc.cqid_sqid = (13 << 8) | 2;
12284 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
12287 test_desc.cqid_sqid = (16 << 8) | 7;
12289 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
12292 test_desc.flags = 0x00000005;
12294 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
12297 val = *(((u32 *)&test_desc) + i);
12298 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
12299 sram_dma_descs + (i * sizeof(u32)));
12300 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
12302 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
12305 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
12307 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
12311 for (i = 0; i < 40; i++) {
12315 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
12317 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
12318 if ((val & 0xffff) == sram_dma_descs) {
12329 #define TEST_BUFFER_SIZE 0x2000
12331 static int __devinit tg3_test_dma(struct tg3 *tp)
12333 dma_addr_t buf_dma;
12334 u32 *buf, saved_dma_rwctrl;
12337 buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
12343 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
12344 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
12346 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
12348 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12349 /* DMA read watermark not used on PCIE */
12350 tp->dma_rwctrl |= 0x00180000;
12351 } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
12352 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
12353 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
12354 tp->dma_rwctrl |= 0x003f0000;
12356 tp->dma_rwctrl |= 0x003f000f;
12358 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
12359 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
12360 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
12361 u32 read_water = 0x7;
12363 /* If the 5704 is behind the EPB bridge, we can
12364 * do the less restrictive ONE_DMA workaround for
12365 * better performance.
12367 if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
12368 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
12369 tp->dma_rwctrl |= 0x8000;
12370 else if (ccval == 0x6 || ccval == 0x7)
12371 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
12373 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
12375 /* Set bit 23 to enable PCIX hw bug fix */
12377 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
12378 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
12380 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
12381 /* 5780 always in PCIX mode */
12382 tp->dma_rwctrl |= 0x00144000;
12383 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
12384 /* 5714 always in PCIX mode */
12385 tp->dma_rwctrl |= 0x00148000;
12387 tp->dma_rwctrl |= 0x001b000f;
12391 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
12392 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
12393 tp->dma_rwctrl &= 0xfffffff0;
12395 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12396 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
12397 /* Remove this if it causes problems for some boards. */
12398 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
12400 /* On 5700/5701 chips, we need to set this bit.
12401 * Otherwise the chip will issue cacheline transactions
12402 * to streamable DMA memory with not all the byte
12403 * enables turned on. This is an error on several
12404 * RISC PCI controllers, in particular sparc64.
12406 * On 5703/5704 chips, this bit has been reassigned
12407 * a different meaning. In particular, it is used
12408 * on those chips to enable a PCI-X workaround.
12410 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
12413 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
12416 /* Unneeded, already done by tg3_get_invariants. */
12417 tg3_switch_clocks(tp);
12421 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
12422 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
12425 /* It is best to perform DMA test with maximum write burst size
12426 * to expose the 5700/5701 write DMA bug.
12428 saved_dma_rwctrl = tp->dma_rwctrl;
12429 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
12430 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
12435 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
12438 /* Send the buffer to the chip. */
12439 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
12441 printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
12446 /* validate data reached card RAM correctly. */
12447 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
12449 tg3_read_mem(tp, 0x2100 + (i*4), &val);
12450 if (le32_to_cpu(val) != p[i]) {
12451 printk(KERN_ERR " tg3_test_dma() Card buffer corrupted on write! (%d != %d)\n", val, i);
12452 /* ret = -ENODEV here? */
12457 /* Now read it back. */
12458 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
12460 printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
12466 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
12470 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
12471 DMA_RWCTRL_WRITE_BNDRY_16) {
12472 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
12473 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
12474 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
12477 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
12483 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
12489 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
12490 DMA_RWCTRL_WRITE_BNDRY_16) {
12491 static struct pci_device_id dma_wait_state_chipsets[] = {
12492 { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
12493 PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
12497 /* DMA test passed without adjusting DMA boundary,
12498 * now look for chipsets that are known to expose the
12499 * DMA bug without failing the test.
12501 if (pci_dev_present(dma_wait_state_chipsets)) {
12502 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
12503 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
12506 /* Safe to use the calculated DMA boundary. */
12507 tp->dma_rwctrl = saved_dma_rwctrl;
12509 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
12513 pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
12518 static void __devinit tg3_init_link_config(struct tg3 *tp)
12520 tp->link_config.advertising =
12521 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
12522 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
12523 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
12524 ADVERTISED_Autoneg | ADVERTISED_MII);
12525 tp->link_config.speed = SPEED_INVALID;
12526 tp->link_config.duplex = DUPLEX_INVALID;
12527 tp->link_config.autoneg = AUTONEG_ENABLE;
12528 tp->link_config.active_speed = SPEED_INVALID;
12529 tp->link_config.active_duplex = DUPLEX_INVALID;
12530 tp->link_config.phy_is_low_power = 0;
12531 tp->link_config.orig_speed = SPEED_INVALID;
12532 tp->link_config.orig_duplex = DUPLEX_INVALID;
12533 tp->link_config.orig_autoneg = AUTONEG_INVALID;
12536 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
12538 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
12539 tp->bufmgr_config.mbuf_read_dma_low_water =
12540 DEFAULT_MB_RDMA_LOW_WATER_5705;
12541 tp->bufmgr_config.mbuf_mac_rx_low_water =
12542 DEFAULT_MB_MACRX_LOW_WATER_5705;
12543 tp->bufmgr_config.mbuf_high_water =
12544 DEFAULT_MB_HIGH_WATER_5705;
12545 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12546 tp->bufmgr_config.mbuf_mac_rx_low_water =
12547 DEFAULT_MB_MACRX_LOW_WATER_5906;
12548 tp->bufmgr_config.mbuf_high_water =
12549 DEFAULT_MB_HIGH_WATER_5906;
12552 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
12553 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
12554 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
12555 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
12556 tp->bufmgr_config.mbuf_high_water_jumbo =
12557 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
12559 tp->bufmgr_config.mbuf_read_dma_low_water =
12560 DEFAULT_MB_RDMA_LOW_WATER;
12561 tp->bufmgr_config.mbuf_mac_rx_low_water =
12562 DEFAULT_MB_MACRX_LOW_WATER;
12563 tp->bufmgr_config.mbuf_high_water =
12564 DEFAULT_MB_HIGH_WATER;
12566 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
12567 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
12568 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
12569 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
12570 tp->bufmgr_config.mbuf_high_water_jumbo =
12571 DEFAULT_MB_HIGH_WATER_JUMBO;
12574 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
12575 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
12578 static char * __devinit tg3_phy_string(struct tg3 *tp)
12580 switch (tp->phy_id & PHY_ID_MASK) {
12581 case PHY_ID_BCM5400: return "5400";
12582 case PHY_ID_BCM5401: return "5401";
12583 case PHY_ID_BCM5411: return "5411";
12584 case PHY_ID_BCM5701: return "5701";
12585 case PHY_ID_BCM5703: return "5703";
12586 case PHY_ID_BCM5704: return "5704";
12587 case PHY_ID_BCM5705: return "5705";
12588 case PHY_ID_BCM5750: return "5750";
12589 case PHY_ID_BCM5752: return "5752";
12590 case PHY_ID_BCM5714: return "5714";
12591 case PHY_ID_BCM5780: return "5780";
12592 case PHY_ID_BCM5755: return "5755";
12593 case PHY_ID_BCM5787: return "5787";
12594 case PHY_ID_BCM5784: return "5784";
12595 case PHY_ID_BCM5756: return "5722/5756";
12596 case PHY_ID_BCM5906: return "5906";
12597 case PHY_ID_BCM5761: return "5761";
12598 case PHY_ID_BCM8002: return "8002/serdes";
12599 case 0: return "serdes";
12600 default: return "unknown";
12604 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
12606 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12607 strcpy(str, "PCI Express");
12609 } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
12610 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
12612 strcpy(str, "PCIX:");
12614 if ((clock_ctrl == 7) ||
12615 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
12616 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
12617 strcat(str, "133MHz");
12618 else if (clock_ctrl == 0)
12619 strcat(str, "33MHz");
12620 else if (clock_ctrl == 2)
12621 strcat(str, "50MHz");
12622 else if (clock_ctrl == 4)
12623 strcat(str, "66MHz");
12624 else if (clock_ctrl == 6)
12625 strcat(str, "100MHz");
12627 strcpy(str, "PCI:");
12628 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
12629 strcat(str, "66MHz");
12631 strcat(str, "33MHz");
12633 if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
12634 strcat(str, ":32-bit");
12636 strcat(str, ":64-bit");
12640 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
12642 struct pci_dev *peer;
12643 unsigned int func, devnr = tp->pdev->devfn & ~7;
12645 for (func = 0; func < 8; func++) {
12646 peer = pci_get_slot(tp->pdev->bus, devnr | func);
12647 if (peer && peer != tp->pdev)
12651 /* 5704 can be configured in single-port mode, set peer to
12652 * tp->pdev in that case.
12660 * We don't need to keep the refcount elevated; there's no way
12661 * to remove one half of this device without removing the other
12668 static void __devinit tg3_init_coal(struct tg3 *tp)
12670 struct ethtool_coalesce *ec = &tp->coal;
12672 memset(ec, 0, sizeof(*ec));
12673 ec->cmd = ETHTOOL_GCOALESCE;
12674 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
12675 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
12676 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
12677 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
12678 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
12679 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
12680 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
12681 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
12682 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
12684 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
12685 HOSTCC_MODE_CLRTICK_TXBD)) {
12686 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
12687 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
12688 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
12689 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
12692 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
12693 ec->rx_coalesce_usecs_irq = 0;
12694 ec->tx_coalesce_usecs_irq = 0;
12695 ec->stats_block_coalesce_usecs = 0;
12699 static int __devinit tg3_init_one(struct pci_dev *pdev,
12700 const struct pci_device_id *ent)
12702 static int tg3_version_printed = 0;
12703 resource_size_t tg3reg_base;
12704 unsigned long tg3reg_len;
12705 struct net_device *dev;
12709 u64 dma_mask, persist_dma_mask;
12710 DECLARE_MAC_BUF(mac);
12712 if (tg3_version_printed++ == 0)
12713 printk(KERN_INFO "%s", version);
12715 err = pci_enable_device(pdev);
12717 printk(KERN_ERR PFX "Cannot enable PCI device, "
12722 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
12723 printk(KERN_ERR PFX "Cannot find proper PCI device "
12724 "base address, aborting.\n");
12726 goto err_out_disable_pdev;
12729 err = pci_request_regions(pdev, DRV_MODULE_NAME);
12731 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
12733 goto err_out_disable_pdev;
12736 pci_set_master(pdev);
12738 /* Find power-management capability. */
12739 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
12741 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
12744 goto err_out_free_res;
12747 tg3reg_base = pci_resource_start(pdev, 0);
12748 tg3reg_len = pci_resource_len(pdev, 0);
12750 dev = alloc_etherdev(sizeof(*tp));
12752 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
12754 goto err_out_free_res;
12757 SET_NETDEV_DEV(dev, &pdev->dev);
12759 #if TG3_VLAN_TAG_USED
12760 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
12761 dev->vlan_rx_register = tg3_vlan_rx_register;
12764 tp = netdev_priv(dev);
12767 tp->pm_cap = pm_cap;
12768 tp->mac_mode = TG3_DEF_MAC_MODE;
12769 tp->rx_mode = TG3_DEF_RX_MODE;
12770 tp->tx_mode = TG3_DEF_TX_MODE;
12773 tp->msg_enable = tg3_debug;
12775 tp->msg_enable = TG3_DEF_MSG_ENABLE;
12777 /* The word/byte swap controls here control register access byte
12778 * swapping. DMA data byte swapping is controlled in the GRC_MODE
12781 tp->misc_host_ctrl =
12782 MISC_HOST_CTRL_MASK_PCI_INT |
12783 MISC_HOST_CTRL_WORD_SWAP |
12784 MISC_HOST_CTRL_INDIR_ACCESS |
12785 MISC_HOST_CTRL_PCISTATE_RW;
12787 /* The NONFRM (non-frame) byte/word swap controls take effect
12788 * on descriptor entries, anything which isn't packet data.
12790 * The StrongARM chips on the board (one for tx, one for rx)
12791 * are running in big-endian mode.
12793 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
12794 GRC_MODE_WSWAP_NONFRM_DATA);
12795 #ifdef __BIG_ENDIAN
12796 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
12798 spin_lock_init(&tp->lock);
12799 spin_lock_init(&tp->indirect_lock);
12800 INIT_WORK(&tp->reset_task, tg3_reset_task);
12802 tp->regs = ioremap_nocache(tg3reg_base, tg3reg_len);
12804 printk(KERN_ERR PFX "Cannot map device registers, "
12807 goto err_out_free_dev;
12810 tg3_init_link_config(tp);
12812 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
12813 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
12814 tp->tx_pending = TG3_DEF_TX_RING_PENDING;
12816 dev->open = tg3_open;
12817 dev->stop = tg3_close;
12818 dev->get_stats = tg3_get_stats;
12819 dev->set_multicast_list = tg3_set_rx_mode;
12820 dev->set_mac_address = tg3_set_mac_addr;
12821 dev->do_ioctl = tg3_ioctl;
12822 dev->tx_timeout = tg3_tx_timeout;
12823 netif_napi_add(dev, &tp->napi, tg3_poll, 64);
12824 dev->ethtool_ops = &tg3_ethtool_ops;
12825 dev->watchdog_timeo = TG3_TX_TIMEOUT;
12826 dev->change_mtu = tg3_change_mtu;
12827 dev->irq = pdev->irq;
12828 #ifdef CONFIG_NET_POLL_CONTROLLER
12829 dev->poll_controller = tg3_poll_controller;
12832 err = tg3_get_invariants(tp);
12834 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
12836 goto err_out_iounmap;
12839 /* The EPB bridge inside 5714, 5715, and 5780 and any
12840 * device behind the EPB cannot support DMA addresses > 40-bit.
12841 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
12842 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
12843 * do DMA address check in tg3_start_xmit().
12845 if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
12846 persist_dma_mask = dma_mask = DMA_32BIT_MASK;
12847 else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
12848 persist_dma_mask = dma_mask = DMA_40BIT_MASK;
12849 #ifdef CONFIG_HIGHMEM
12850 dma_mask = DMA_64BIT_MASK;
12853 persist_dma_mask = dma_mask = DMA_64BIT_MASK;
12855 /* Configure DMA attributes. */
12856 if (dma_mask > DMA_32BIT_MASK) {
12857 err = pci_set_dma_mask(pdev, dma_mask);
12859 dev->features |= NETIF_F_HIGHDMA;
12860 err = pci_set_consistent_dma_mask(pdev,
12863 printk(KERN_ERR PFX "Unable to obtain 64 bit "
12864 "DMA for consistent allocations\n");
12865 goto err_out_iounmap;
12869 if (err || dma_mask == DMA_32BIT_MASK) {
12870 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
12872 printk(KERN_ERR PFX "No usable DMA configuration, "
12874 goto err_out_iounmap;
12878 tg3_init_bufmgr_config(tp);
12880 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
12881 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
12883 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12884 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
12885 tp->pci_chip_rev_id == CHIPREV_ID_5705_A0 ||
12886 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
12887 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
12888 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
12890 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG;
12893 /* TSO is on by default on chips that support hardware TSO.
12894 * Firmware TSO on older chips gives lower performance, so it
12895 * is off by default, but can be enabled using ethtool.
12897 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
12898 dev->features |= NETIF_F_TSO;
12899 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) &&
12900 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906))
12901 dev->features |= NETIF_F_TSO6;
12902 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
12903 dev->features |= NETIF_F_TSO_ECN;
12907 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
12908 !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
12909 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
12910 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
12911 tp->rx_pending = 63;
12914 err = tg3_get_device_address(tp);
12916 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
12918 goto err_out_iounmap;
12921 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
12922 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
12923 printk(KERN_ERR PFX "Cannot find proper PCI device "
12924 "base address for APE, aborting.\n");
12926 goto err_out_iounmap;
12929 tg3reg_base = pci_resource_start(pdev, 2);
12930 tg3reg_len = pci_resource_len(pdev, 2);
12932 tp->aperegs = ioremap_nocache(tg3reg_base, tg3reg_len);
12933 if (!tp->aperegs) {
12934 printk(KERN_ERR PFX "Cannot map APE registers, "
12937 goto err_out_iounmap;
12940 tg3_ape_lock_init(tp);
12944 * Reset chip in case UNDI or EFI driver did not shutdown
12945 * DMA self test will enable WDMAC and we'll see (spurious)
12946 * pending DMA on the PCI bus at that point.
12948 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
12949 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
12950 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
12951 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
12954 err = tg3_test_dma(tp);
12956 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
12957 goto err_out_apeunmap;
12960 /* Tigon3 can do ipv4 only... and some chips have buggy
12963 if ((tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) == 0) {
12964 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
12965 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12966 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
12967 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12968 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
12969 dev->features |= NETIF_F_IPV6_CSUM;
12971 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
12973 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
12975 /* flow control autonegotiation is default behavior */
12976 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
12977 tp->link_config.flowctrl = TG3_FLOW_CTRL_TX | TG3_FLOW_CTRL_RX;
12981 pci_set_drvdata(pdev, dev);
12983 err = register_netdev(dev);
12985 printk(KERN_ERR PFX "Cannot register net device, "
12987 goto err_out_apeunmap;
12990 printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x PHY(%s)] "
12991 "(%s) %s Ethernet %s\n",
12993 tp->board_part_number,
12994 tp->pci_chip_rev_id,
12995 tg3_phy_string(tp),
12996 tg3_bus_string(tp, str),
12997 ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
12998 ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
12999 "10/100/1000Base-T")),
13000 print_mac(mac, dev->dev_addr));
13002 printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] "
13003 "MIirq[%d] ASF[%d] WireSpeed[%d] TSOcap[%d]\n",
13005 (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
13006 (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
13007 (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
13008 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
13009 (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0,
13010 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
13011 printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
13012 dev->name, tp->dma_rwctrl,
13013 (pdev->dma_mask == DMA_32BIT_MASK) ? 32 :
13014 (((u64) pdev->dma_mask == DMA_40BIT_MASK) ? 40 : 64));
13020 iounmap(tp->aperegs);
13021 tp->aperegs = NULL;
13034 pci_release_regions(pdev);
13036 err_out_disable_pdev:
13037 pci_disable_device(pdev);
13038 pci_set_drvdata(pdev, NULL);
13042 static void __devexit tg3_remove_one(struct pci_dev *pdev)
13044 struct net_device *dev = pci_get_drvdata(pdev);
13047 struct tg3 *tp = netdev_priv(dev);
13049 flush_scheduled_work();
13050 unregister_netdev(dev);
13052 iounmap(tp->aperegs);
13053 tp->aperegs = NULL;
13060 pci_release_regions(pdev);
13061 pci_disable_device(pdev);
13062 pci_set_drvdata(pdev, NULL);
13066 static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
13068 struct net_device *dev = pci_get_drvdata(pdev);
13069 struct tg3 *tp = netdev_priv(dev);
13072 /* PCI register 4 needs to be saved whether netif_running() or not.
13073 * MSI address and data need to be saved if using MSI and
13076 pci_save_state(pdev);
13078 if (!netif_running(dev))
13081 flush_scheduled_work();
13082 tg3_netif_stop(tp);
13084 del_timer_sync(&tp->timer);
13086 tg3_full_lock(tp, 1);
13087 tg3_disable_ints(tp);
13088 tg3_full_unlock(tp);
13090 netif_device_detach(dev);
13092 tg3_full_lock(tp, 0);
13093 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
13094 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
13095 tg3_full_unlock(tp);
13097 err = tg3_set_power_state(tp, pci_choose_state(pdev, state));
13099 tg3_full_lock(tp, 0);
13101 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
13102 if (tg3_restart_hw(tp, 1))
13105 tp->timer.expires = jiffies + tp->timer_offset;
13106 add_timer(&tp->timer);
13108 netif_device_attach(dev);
13109 tg3_netif_start(tp);
13112 tg3_full_unlock(tp);
13118 static int tg3_resume(struct pci_dev *pdev)
13120 struct net_device *dev = pci_get_drvdata(pdev);
13121 struct tg3 *tp = netdev_priv(dev);
13124 pci_restore_state(tp->pdev);
13126 if (!netif_running(dev))
13129 err = tg3_set_power_state(tp, PCI_D0);
13133 netif_device_attach(dev);
13135 tg3_full_lock(tp, 0);
13137 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
13138 err = tg3_restart_hw(tp, 1);
13142 tp->timer.expires = jiffies + tp->timer_offset;
13143 add_timer(&tp->timer);
13145 tg3_netif_start(tp);
13148 tg3_full_unlock(tp);
13153 static struct pci_driver tg3_driver = {
13154 .name = DRV_MODULE_NAME,
13155 .id_table = tg3_pci_tbl,
13156 .probe = tg3_init_one,
13157 .remove = __devexit_p(tg3_remove_one),
13158 .suspend = tg3_suspend,
13159 .resume = tg3_resume
13162 static int __init tg3_init(void)
13164 return pci_register_driver(&tg3_driver);
13167 static void __exit tg3_cleanup(void)
13169 pci_unregister_driver(&tg3_driver);
13172 module_init(tg3_init);
13173 module_exit(tg3_cleanup);