drivers/net/tg3.c

   1 /*
   2  * tg3.c: Broadcom Tigon3 ethernet driver.
   3  *
   4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
   5  * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
   6  * Copyright (C) 2004 Sun Microsystems Inc.
   7  * Copyright (C) 2005-2009 Broadcom Corporation.
   8  *
   9  * Firmware is:
  10  *      Derived from proprietary unpublished source code,
  11  *      Copyright (C) 2000-2003 Broadcom Corporation.
  12  *
  13  *      Permission is hereby granted for the distribution of this firmware
  14  *      data in hexadecimal or equivalent format, provided this copyright
  15  *      notice is accompanying it.
  16  */
  17
  18
  19 #include <linux/module.h>
  20 #include <linux/moduleparam.h>
  21 #include <linux/kernel.h>
  22 #include <linux/types.h>
  23 #include <linux/compiler.h>
  24 #include <linux/slab.h>
  25 #include <linux/delay.h>
  26 #include <linux/in.h>
  27 #include <linux/init.h>
  28 #include <linux/ioport.h>
  29 #include <linux/pci.h>
  30 #include <linux/netdevice.h>
  31 #include <linux/etherdevice.h>
  32 #include <linux/skbuff.h>
  33 #include <linux/ethtool.h>
  34 #include <linux/mii.h>
  35 #include <linux/phy.h>
  36 #include <linux/brcmphy.h>
  37 #include <linux/if_vlan.h>
  38 #include <linux/ip.h>
  39 #include <linux/tcp.h>
  40 #include <linux/workqueue.h>
  41 #include <linux/prefetch.h>
  42 #include <linux/dma-mapping.h>
  43 #include <linux/firmware.h>
  44
  45 #include <net/checksum.h>
  46 #include <net/ip.h>
  47
  48 #include <asm/system.h>
  49 #include <asm/io.h>
  50 #include <asm/byteorder.h>
  51 #include <asm/uaccess.h>
  52
  53 #ifdef CONFIG_SPARC
  54 #include <asm/idprom.h>
  55 #include <asm/prom.h>
  56 #endif
  57
  58 #define BAR_0   0
  59 #define BAR_2   2
  60
  61 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  62 #define TG3_VLAN_TAG_USED 1
  63 #else
  64 #define TG3_VLAN_TAG_USED 0
  65 #endif
  66
  67 #include "tg3.h"
  68
  69 #define DRV_MODULE_NAME         "tg3"
  70 #define PFX DRV_MODULE_NAME     ": "
  71 #define DRV_MODULE_VERSION      "3.105"
  72 #define DRV_MODULE_RELDATE      "December 2, 2009"
  73
  74 #define TG3_DEF_MAC_MODE        0
  75 #define TG3_DEF_RX_MODE         0
  76 #define TG3_DEF_TX_MODE         0
  77 #define TG3_DEF_MSG_ENABLE        \
  78         (NETIF_MSG_DRV          | \
  79          NETIF_MSG_PROBE        | \
  80          NETIF_MSG_LINK         | \
  81          NETIF_MSG_TIMER        | \
  82          NETIF_MSG_IFDOWN       | \
  83          NETIF_MSG_IFUP         | \
  84          NETIF_MSG_RX_ERR       | \
  85          NETIF_MSG_TX_ERR)
  86
  87 /* length of time before we decide the hardware is borked,
  88  * and dev->tx_timeout() should be called to fix the problem
  89  */
  90 #define TG3_TX_TIMEOUT                  (5 * HZ)
  91
  92 /* hardware minimum and maximum for a single frame's data payload */
  93 #define TG3_MIN_MTU                     60
  94 #define TG3_MAX_MTU(tp) \
  95         ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
  96
  97 /* These numbers seem to be hard coded in the NIC firmware somehow.
  98  * You can't change the ring sizes, but you can change where you place
  99  * them in the NIC onboard memory.
 100  */
 101 #define TG3_RX_RING_SIZE                512
 102 #define TG3_DEF_RX_RING_PENDING         200
 103 #define TG3_RX_JUMBO_RING_SIZE          256
 104 #define TG3_DEF_RX_JUMBO_RING_PENDING   100
 105 #define TG3_RSS_INDIR_TBL_SIZE 128
 106
 107 /* Do not place this n-ring entries value into the tp struct itself,
 108  * we really want to expose these constants to GCC so that modulo et
 109  * al.  operations are done with shifts and masks instead of with
 110  * hw multiply/modulo instructions.  Another solution would be to
 111  * replace things like '% foo' with '& (foo - 1)'.
 112  */
 113 #define TG3_RX_RCB_RING_SIZE(tp)        \
 114         (((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) && \
 115           !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) ? 1024 : 512)
 116
 117 #define TG3_TX_RING_SIZE                512
 118 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
 119
 120 #define TG3_RX_RING_BYTES       (sizeof(struct tg3_rx_buffer_desc) * \
 121                                  TG3_RX_RING_SIZE)
 122 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_ext_rx_buffer_desc) * \
 123                                  TG3_RX_JUMBO_RING_SIZE)
 124 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
 125                                  TG3_RX_RCB_RING_SIZE(tp))
 126 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * \
 127                                  TG3_TX_RING_SIZE)
 128 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
 129
 130 #define TG3_DMA_BYTE_ENAB               64
 131
 132 #define TG3_RX_STD_DMA_SZ               1536
 133 #define TG3_RX_JMB_DMA_SZ               9046
 134
 135 #define TG3_RX_DMA_TO_MAP_SZ(x)         ((x) + TG3_DMA_BYTE_ENAB)
 136
 137 #define TG3_RX_STD_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
 138 #define TG3_RX_JMB_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
 139
 140 #define TG3_RX_STD_BUFF_RING_SIZE \
 141         (sizeof(struct ring_info) * TG3_RX_RING_SIZE)
 142
 143 #define TG3_RX_JMB_BUFF_RING_SIZE \
 144         (sizeof(struct ring_info) * TG3_RX_JUMBO_RING_SIZE)
 145
 146 /* minimum number of free TX descriptors required to wake up TX process */
 147 #define TG3_TX_WAKEUP_THRESH(tnapi)             ((tnapi)->tx_pending / 4)
 148
 149 #define TG3_RAW_IP_ALIGN 2
 150
 151 /* number of ETHTOOL_GSTATS u64's */
 152 #define TG3_NUM_STATS           (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
 153
 154 #define TG3_NUM_TEST            6
 155
 156 #define FIRMWARE_TG3            "tigon/tg3.bin"
 157 #define FIRMWARE_TG3TSO         "tigon/tg3_tso.bin"
 158 #define FIRMWARE_TG3TSO5        "tigon/tg3_tso5.bin"
 159
 160 static char version[] __devinitdata =
 161         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
 162
 163 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
 164 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
 165 MODULE_LICENSE("GPL");
 166 MODULE_VERSION(DRV_MODULE_VERSION);
 167 MODULE_FIRMWARE(FIRMWARE_TG3);
 168 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
 169 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
 170
 171 #define TG3_RSS_MIN_NUM_MSIX_VECS       2
 172
 173 static int tg3_debug = -1;      /* -1 == use TG3_DEF_MSG_ENABLE as value */
 174 module_param(tg3_debug, int, 0);
 175 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
 176
 177 static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = {
 178         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
 179         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
 180         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
 181         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
 182         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
 183         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
 184         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
 185         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
 186         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
 187         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
 188         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
 189         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
 190         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
 191         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
 192         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
 193         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
 194         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
 195         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
 196         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
 197         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
 198         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
 199         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
 200         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
 201         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
 202         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
 203         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
 204         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
 205         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
 206         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
 207         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
 208         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
 209         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
 210         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
 211         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
 212         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
 213         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
 214         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
 215         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
 216         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
 217         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
 218         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
 219         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
 220         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
 221         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
 222         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
 223         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
 224         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
 225         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
 226         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
 227         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
 228         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
 229         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
 230         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
 231         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
 232         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
 233         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
 234         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
 235         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
 236         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
 237         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
 238         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
 239         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
 240         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
 241         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
 242         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
 243         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
 244         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
 245         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
 246         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5724)},
 247         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
 248         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
 249         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
 250         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
 251         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791)},
 252         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795)},
 253         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
 254         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
 255         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
 256         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
 257         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
 258         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
 259         {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
 260         {}
 261 };
 262
 263 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
 264
 265 static const struct {
 266         const char string[ETH_GSTRING_LEN];
 267 } ethtool_stats_keys[TG3_NUM_STATS] = {
 268         { "rx_octets" },
 269         { "rx_fragments" },
 270         { "rx_ucast_packets" },
 271         { "rx_mcast_packets" },
 272         { "rx_bcast_packets" },
 273         { "rx_fcs_errors" },
 274         { "rx_align_errors" },
 275         { "rx_xon_pause_rcvd" },
 276         { "rx_xoff_pause_rcvd" },
 277         { "rx_mac_ctrl_rcvd" },
 278         { "rx_xoff_entered" },
 279         { "rx_frame_too_long_errors" },
 280         { "rx_jabbers" },
 281         { "rx_undersize_packets" },
 282         { "rx_in_length_errors" },
 283         { "rx_out_length_errors" },
 284         { "rx_64_or_less_octet_packets" },
 285         { "rx_65_to_127_octet_packets" },
 286         { "rx_128_to_255_octet_packets" },
 287         { "rx_256_to_511_octet_packets" },
 288         { "rx_512_to_1023_octet_packets" },
 289         { "rx_1024_to_1522_octet_packets" },
 290         { "rx_1523_to_2047_octet_packets" },
 291         { "rx_2048_to_4095_octet_packets" },
 292         { "rx_4096_to_8191_octet_packets" },
 293         { "rx_8192_to_9022_octet_packets" },
 294
 295         { "tx_octets" },
 296         { "tx_collisions" },
 297
 298         { "tx_xon_sent" },
 299         { "tx_xoff_sent" },
 300         { "tx_flow_control" },
 301         { "tx_mac_errors" },
 302         { "tx_single_collisions" },
 303         { "tx_mult_collisions" },
 304         { "tx_deferred" },
 305         { "tx_excessive_collisions" },
 306         { "tx_late_collisions" },
 307         { "tx_collide_2times" },
 308         { "tx_collide_3times" },
 309         { "tx_collide_4times" },
 310         { "tx_collide_5times" },
 311         { "tx_collide_6times" },
 312         { "tx_collide_7times" },
 313         { "tx_collide_8times" },
 314         { "tx_collide_9times" },
 315         { "tx_collide_10times" },
 316         { "tx_collide_11times" },
 317         { "tx_collide_12times" },
 318         { "tx_collide_13times" },
 319         { "tx_collide_14times" },
 320         { "tx_collide_15times" },
 321         { "tx_ucast_packets" },
 322         { "tx_mcast_packets" },
 323         { "tx_bcast_packets" },
 324         { "tx_carrier_sense_errors" },
 325         { "tx_discards" },
 326         { "tx_errors" },
 327
 328         { "dma_writeq_full" },
 329         { "dma_write_prioq_full" },
 330         { "rxbds_empty" },
 331         { "rx_discards" },
 332         { "rx_errors" },
 333         { "rx_threshold_hit" },
 334
 335         { "dma_readq_full" },
 336         { "dma_read_prioq_full" },
 337         { "tx_comp_queue_full" },
 338
 339         { "ring_set_send_prod_index" },
 340         { "ring_status_update" },
 341         { "nic_irqs" },
 342         { "nic_avoided_irqs" },
 343         { "nic_tx_threshold_hit" }
 344 };
 345
 346 static const struct {
 347         const char string[ETH_GSTRING_LEN];
 348 } ethtool_test_keys[TG3_NUM_TEST] = {
 349         { "nvram test     (online) " },
 350         { "link test      (online) " },
 351         { "register test  (offline)" },
 352         { "memory test    (offline)" },
 353         { "loopback test  (offline)" },
 354         { "interrupt test (offline)" },
 355 };
 356
 357 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
 358 {
 359         writel(val, tp->regs + off);
 360 }
 361
 362 static u32 tg3_read32(struct tg3 *tp, u32 off)
 363 {
 364         return (readl(tp->regs + off));
 365 }
 366
 367 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
 368 {
 369         writel(val, tp->aperegs + off);
 370 }
 371
 372 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
 373 {
 374         return (readl(tp->aperegs + off));
 375 }
 376
 377 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
 378 {
 379         unsigned long flags;
 380
 381         spin_lock_irqsave(&tp->indirect_lock, flags);
 382         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 383         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 384         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 385 }
 386
 387 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
 388 {
 389         writel(val, tp->regs + off);
 390         readl(tp->regs + off);
 391 }
 392
 393 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
 394 {
 395         unsigned long flags;
 396         u32 val;
 397
 398         spin_lock_irqsave(&tp->indirect_lock, flags);
 399         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 400         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 401         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 402         return val;
 403 }
 404
 405 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
 406 {
 407         unsigned long flags;
 408
 409         if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
 410                 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
 411                                        TG3_64BIT_REG_LOW, val);
 412                 return;
 413         }
 414         if (off == TG3_RX_STD_PROD_IDX_REG) {
 415                 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
 416                                        TG3_64BIT_REG_LOW, val);
 417                 return;
 418         }
 419
 420         spin_lock_irqsave(&tp->indirect_lock, flags);
 421         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 422         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 423         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 424
 425         /* In indirect mode when disabling interrupts, we also need
 426          * to clear the interrupt bit in the GRC local ctrl register.
 427          */
 428         if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
 429             (val == 0x1)) {
 430                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
 431                                        tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
 432         }
 433 }
 434
 435 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
 436 {
 437         unsigned long flags;
 438         u32 val;
 439
 440         spin_lock_irqsave(&tp->indirect_lock, flags);
 441         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 442         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 443         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 444         return val;
 445 }
 446
 447 /* usec_wait specifies the wait time in usec when writing to certain registers
 448  * where it is unsafe to read back the register without some delay.
 449  * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
 450  * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
 451  */
 452 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
 453 {
 454         if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
 455             (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 456                 /* Non-posted methods */
 457                 tp->write32(tp, off, val);
 458         else {
 459                 /* Posted method */
 460                 tg3_write32(tp, off, val);
 461                 if (usec_wait)
 462                         udelay(usec_wait);
 463                 tp->read32(tp, off);
 464         }
 465         /* Wait again after the read for the posted method to guarantee that
 466          * the wait time is met.
 467          */
 468         if (usec_wait)
 469                 udelay(usec_wait);
 470 }
 471
 472 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
 473 {
 474         tp->write32_mbox(tp, off, val);
 475         if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
 476             !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 477                 tp->read32_mbox(tp, off);
 478 }
 479
 480 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
 481 {
 482         void __iomem *mbox = tp->regs + off;
 483         writel(val, mbox);
 484         if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
 485                 writel(val, mbox);
 486         if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
 487                 readl(mbox);
 488 }
 489
 490 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
 491 {
 492         return (readl(tp->regs + off + GRCMBOX_BASE));
 493 }
 494
 495 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
 496 {
 497         writel(val, tp->regs + off + GRCMBOX_BASE);
 498 }
 499
 500 #define tw32_mailbox(reg, val)  tp->write32_mbox(tp, reg, val)
 501 #define tw32_mailbox_f(reg, val)        tw32_mailbox_flush(tp, (reg), (val))
 502 #define tw32_rx_mbox(reg, val)  tp->write32_rx_mbox(tp, reg, val)
 503 #define tw32_tx_mbox(reg, val)  tp->write32_tx_mbox(tp, reg, val)
 504 #define tr32_mailbox(reg)       tp->read32_mbox(tp, reg)
 505
 506 #define tw32(reg,val)           tp->write32(tp, reg, val)
 507 #define tw32_f(reg,val)         _tw32_flush(tp,(reg),(val), 0)
 508 #define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
 509 #define tr32(reg)               tp->read32(tp, reg)
 510
 511 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
 512 {
 513         unsigned long flags;
 514
 515         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 516             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
 517                 return;
 518
 519         spin_lock_irqsave(&tp->indirect_lock, flags);
 520         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 521                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 522                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 523
 524                 /* Always leave this as zero. */
 525                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 526         } else {
 527                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 528                 tw32_f(TG3PCI_MEM_WIN_DATA, val);
 529
 530                 /* Always leave this as zero. */
 531                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 532         }
 533         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 534 }
 535
 536 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
 537 {
 538         unsigned long flags;
 539
 540         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 541             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
 542                 *val = 0;
 543                 return;
 544         }
 545
 546         spin_lock_irqsave(&tp->indirect_lock, flags);
 547         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 548                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 549                 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 550
 551                 /* Always leave this as zero. */
 552                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 553         } else {
 554                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 555                 *val = tr32(TG3PCI_MEM_WIN_DATA);
 556
 557                 /* Always leave this as zero. */
 558                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 559         }
 560         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 561 }
 562
 563 static void tg3_ape_lock_init(struct tg3 *tp)
 564 {
 565         int i;
 566
 567         /* Make sure the driver hasn't any stale locks. */
 568         for (i = 0; i < 8; i++)
 569                 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + 4 * i,
 570                                 APE_LOCK_GRANT_DRIVER);
 571 }
 572
 573 static int tg3_ape_lock(struct tg3 *tp, int locknum)
 574 {
 575         int i, off;
 576         int ret = 0;
 577         u32 status;
 578
 579         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
 580                 return 0;
 581
 582         switch (locknum) {
 583                 case TG3_APE_LOCK_GRC:
 584                 case TG3_APE_LOCK_MEM:
 585                         break;
 586                 default:
 587                         return -EINVAL;
 588         }
 589
 590         off = 4 * locknum;
 591
 592         tg3_ape_write32(tp, TG3_APE_LOCK_REQ + off, APE_LOCK_REQ_DRIVER);
 593
 594         /* Wait for up to 1 millisecond to acquire lock. */
 595         for (i = 0; i < 100; i++) {
 596                 status = tg3_ape_read32(tp, TG3_APE_LOCK_GRANT + off);
 597                 if (status == APE_LOCK_GRANT_DRIVER)
 598                         break;
 599                 udelay(10);
 600         }
 601
 602         if (status != APE_LOCK_GRANT_DRIVER) {
 603                 /* Revoke the lock request. */
 604                 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off,
 605                                 APE_LOCK_GRANT_DRIVER);
 606
 607                 ret = -EBUSY;
 608         }
 609
 610         return ret;
 611 }
 612
 613 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
 614 {
 615         int off;
 616
 617         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
 618                 return;
 619
 620         switch (locknum) {
 621                 case TG3_APE_LOCK_GRC:
 622                 case TG3_APE_LOCK_MEM:
 623                         break;
 624                 default:
 625                         return;
 626         }
 627
 628         off = 4 * locknum;
 629         tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off, APE_LOCK_GRANT_DRIVER);
 630 }
 631
 632 static void tg3_disable_ints(struct tg3 *tp)
 633 {
 634         int i;
 635
 636         tw32(TG3PCI_MISC_HOST_CTRL,
 637              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
 638         for (i = 0; i < tp->irq_max; i++)
 639                 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
 640 }
 641
 642 static void tg3_enable_ints(struct tg3 *tp)
 643 {
 644         int i;
 645         u32 coal_now = 0;
 646
 647         tp->irq_sync = 0;
 648         wmb();
 649
 650         tw32(TG3PCI_MISC_HOST_CTRL,
 651              (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
 652
 653         for (i = 0; i < tp->irq_cnt; i++) {
 654                 struct tg3_napi *tnapi = &tp->napi[i];
 655                 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
 656                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
 657                         tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
 658
 659                 coal_now |= tnapi->coal_now;
 660         }
 661
 662         /* Force an initial interrupt */
 663         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 664             (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
 665                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
 666         else
 667                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 668                      HOSTCC_MODE_ENABLE | coal_now);
 669 }
 670
 671 static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
 672 {
 673         struct tg3 *tp = tnapi->tp;
 674         struct tg3_hw_status *sblk = tnapi->hw_status;
 675         unsigned int work_exists = 0;
 676
 677         /* check for phy events */
 678         if (!(tp->tg3_flags &
 679               (TG3_FLAG_USE_LINKCHG_REG |
 680                TG3_FLAG_POLL_SERDES))) {
 681                 if (sblk->status & SD_STATUS_LINK_CHG)
 682                         work_exists = 1;
 683         }
 684         /* check for RX/TX work to do */
 685         if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
 686             *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
 687                 work_exists = 1;
 688
 689         return work_exists;
 690 }
 691
 692 /* tg3_int_reenable
 693  *  similar to tg3_enable_ints, but it accurately determines whether there
 694  *  is new work pending and can return without flushing the PIO write
 695  *  which reenables interrupts
 696  */
 697 static void tg3_int_reenable(struct tg3_napi *tnapi)
 698 {
 699         struct tg3 *tp = tnapi->tp;
 700
 701         tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
 702         mmiowb();
 703
 704         /* When doing tagged status, this work check is unnecessary.
 705          * The last_tag we write above tells the chip which piece of
 706          * work we've completed.
 707          */
 708         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 709             tg3_has_work(tnapi))
 710                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 711                      HOSTCC_MODE_ENABLE | tnapi->coal_now);
 712 }
 713
 714 static void tg3_napi_disable(struct tg3 *tp)
 715 {
 716         int i;
 717
 718         for (i = tp->irq_cnt - 1; i >= 0; i--)
 719                 napi_disable(&tp->napi[i].napi);
 720 }
 721
 722 static void tg3_napi_enable(struct tg3 *tp)
 723 {
 724         int i;
 725
 726         for (i = 0; i < tp->irq_cnt; i++)
 727                 napi_enable(&tp->napi[i].napi);
 728 }
 729
 730 static inline void tg3_netif_stop(struct tg3 *tp)
 731 {
 732         tp->dev->trans_start = jiffies; /* prevent tx timeout */
 733         tg3_napi_disable(tp);
 734         netif_tx_disable(tp->dev);
 735 }
 736
 737 static inline void tg3_netif_start(struct tg3 *tp)
 738 {
 739         /* NOTE: unconditional netif_tx_wake_all_queues is only
 740          * appropriate so long as all callers are assured to
 741          * have free tx slots (such as after tg3_init_hw)
 742          */
 743         netif_tx_wake_all_queues(tp->dev);
 744
 745         tg3_napi_enable(tp);
 746         tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
 747         tg3_enable_ints(tp);
 748 }
 749
 750 static void tg3_switch_clocks(struct tg3 *tp)
 751 {
 752         u32 clock_ctrl;
 753         u32 orig_clock_ctrl;
 754
 755         if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
 756             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
 757                 return;
 758
 759         clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
 760
 761         orig_clock_ctrl = clock_ctrl;
 762         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
 763                        CLOCK_CTRL_CLKRUN_OENABLE |
 764                        0x1f);
 765         tp->pci_clock_ctrl = clock_ctrl;
 766
 767         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
 768                 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
 769                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
 770                                     clock_ctrl | CLOCK_CTRL_625_CORE, 40);
 771                 }
 772         } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
 773                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 774                             clock_ctrl |
 775                             (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
 776                             40);
 777                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 778                             clock_ctrl | (CLOCK_CTRL_ALTCLK),
 779                             40);
 780         }
 781         tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
 782 }
 783
 784 #define PHY_BUSY_LOOPS  5000
 785
 786 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
 787 {
 788         u32 frame_val;
 789         unsigned int loops;
 790         int ret;
 791
 792         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 793                 tw32_f(MAC_MI_MODE,
 794                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 795                 udelay(80);
 796         }
 797
 798         *val = 0x0;
 799
 800         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
 801                       MI_COM_PHY_ADDR_MASK);
 802         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 803                       MI_COM_REG_ADDR_MASK);
 804         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
 805
 806         tw32_f(MAC_MI_COM, frame_val);
 807
 808         loops = PHY_BUSY_LOOPS;
 809         while (loops != 0) {
 810                 udelay(10);
 811                 frame_val = tr32(MAC_MI_COM);
 812
 813                 if ((frame_val & MI_COM_BUSY) == 0) {
 814                         udelay(5);
 815                         frame_val = tr32(MAC_MI_COM);
 816                         break;
 817                 }
 818                 loops -= 1;
 819         }
 820
 821         ret = -EBUSY;
 822         if (loops != 0) {
 823                 *val = frame_val & MI_COM_DATA_MASK;
 824                 ret = 0;
 825         }
 826
 827         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 828                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 829                 udelay(80);
 830         }
 831
 832         return ret;
 833 }
 834
 835 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
 836 {
 837         u32 frame_val;
 838         unsigned int loops;
 839         int ret;
 840
 841         if ((tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
 842             (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
 843                 return 0;
 844
 845         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 846                 tw32_f(MAC_MI_MODE,
 847                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 848                 udelay(80);
 849         }
 850
 851         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
 852                       MI_COM_PHY_ADDR_MASK);
 853         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 854                       MI_COM_REG_ADDR_MASK);
 855         frame_val |= (val & MI_COM_DATA_MASK);
 856         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
 857
 858         tw32_f(MAC_MI_COM, frame_val);
 859
 860         loops = PHY_BUSY_LOOPS;
 861         while (loops != 0) {
 862                 udelay(10);
 863                 frame_val = tr32(MAC_MI_COM);
 864                 if ((frame_val & MI_COM_BUSY) == 0) {
 865                         udelay(5);
 866                         frame_val = tr32(MAC_MI_COM);
 867                         break;
 868                 }
 869                 loops -= 1;
 870         }
 871
 872         ret = -EBUSY;
 873         if (loops != 0)
 874                 ret = 0;
 875
 876         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 877                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 878                 udelay(80);
 879         }
 880
 881         return ret;
 882 }
 883
 884 static int tg3_bmcr_reset(struct tg3 *tp)
 885 {
 886         u32 phy_control;
 887         int limit, err;
 888
 889         /* OK, reset it, and poll the BMCR_RESET bit until it
 890          * clears or we time out.
 891          */
 892         phy_control = BMCR_RESET;
 893         err = tg3_writephy(tp, MII_BMCR, phy_control);
 894         if (err != 0)
 895                 return -EBUSY;
 896
 897         limit = 5000;
 898         while (limit--) {
 899                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
 900                 if (err != 0)
 901                         return -EBUSY;
 902
 903                 if ((phy_control & BMCR_RESET) == 0) {
 904                         udelay(40);
 905                         break;
 906                 }
 907                 udelay(10);
 908         }
 909         if (limit < 0)
 910                 return -EBUSY;
 911
 912         return 0;
 913 }
 914
 915 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
 916 {
 917         struct tg3 *tp = bp->priv;
 918         u32 val;
 919
 920         spin_lock_bh(&tp->lock);
 921
 922         if (tg3_readphy(tp, reg, &val))
 923                 val = -EIO;
 924
 925         spin_unlock_bh(&tp->lock);
 926
 927         return val;
 928 }
 929
 930 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
 931 {
 932         struct tg3 *tp = bp->priv;
 933         u32 ret = 0;
 934
 935         spin_lock_bh(&tp->lock);
 936
 937         if (tg3_writephy(tp, reg, val))
 938                 ret = -EIO;
 939
 940         spin_unlock_bh(&tp->lock);
 941
 942         return ret;
 943 }
 944
 945 static int tg3_mdio_reset(struct mii_bus *bp)
 946 {
 947         return 0;
 948 }
 949
 950 static void tg3_mdio_config_5785(struct tg3 *tp)
 951 {
 952         u32 val;
 953         struct phy_device *phydev;
 954
 955         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
 956         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
 957         case TG3_PHY_ID_BCM50610:
 958         case TG3_PHY_ID_BCM50610M:
 959                 val = MAC_PHYCFG2_50610_LED_MODES;
 960                 break;
 961         case TG3_PHY_ID_BCMAC131:
 962                 val = MAC_PHYCFG2_AC131_LED_MODES;
 963                 break;
 964         case TG3_PHY_ID_RTL8211C:
 965                 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
 966                 break;
 967         case TG3_PHY_ID_RTL8201E:
 968                 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
 969                 break;
 970         default:
 971                 return;
 972         }
 973
 974         if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
 975                 tw32(MAC_PHYCFG2, val);
 976
 977                 val = tr32(MAC_PHYCFG1);
 978                 val &= ~(MAC_PHYCFG1_RGMII_INT |
 979                          MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
 980                 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
 981                 tw32(MAC_PHYCFG1, val);
 982
 983                 return;
 984         }
 985
 986         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE))
 987                 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
 988                        MAC_PHYCFG2_FMODE_MASK_MASK |
 989                        MAC_PHYCFG2_GMODE_MASK_MASK |
 990                        MAC_PHYCFG2_ACT_MASK_MASK   |
 991                        MAC_PHYCFG2_QUAL_MASK_MASK |
 992                        MAC_PHYCFG2_INBAND_ENABLE;
 993
 994         tw32(MAC_PHYCFG2, val);
 995
 996         val = tr32(MAC_PHYCFG1);
 997         val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
 998                  MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
 999         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
1000                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1001                         val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
1002                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1003                         val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
1004         }
1005         val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1006                MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1007         tw32(MAC_PHYCFG1, val);
1008
1009         val = tr32(MAC_EXT_RGMII_MODE);
1010         val &= ~(MAC_RGMII_MODE_RX_INT_B |
1011                  MAC_RGMII_MODE_RX_QUALITY |
1012                  MAC_RGMII_MODE_RX_ACTIVITY |
1013                  MAC_RGMII_MODE_RX_ENG_DET |
1014                  MAC_RGMII_MODE_TX_ENABLE |
1015                  MAC_RGMII_MODE_TX_LOWPWR |
1016                  MAC_RGMII_MODE_TX_RESET);
1017         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
1018                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1019                         val |= MAC_RGMII_MODE_RX_INT_B |
1020                                MAC_RGMII_MODE_RX_QUALITY |
1021                                MAC_RGMII_MODE_RX_ACTIVITY |
1022                                MAC_RGMII_MODE_RX_ENG_DET;
1023                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1024                         val |= MAC_RGMII_MODE_TX_ENABLE |
1025                                MAC_RGMII_MODE_TX_LOWPWR |
1026                                MAC_RGMII_MODE_TX_RESET;
1027         }
1028         tw32(MAC_EXT_RGMII_MODE, val);
1029 }
1030
1031 static void tg3_mdio_start(struct tg3 *tp)
1032 {
1033         tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1034         tw32_f(MAC_MI_MODE, tp->mi_mode);
1035         udelay(80);
1036
1037         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
1038                 u32 funcnum, is_serdes;
1039
1040                 funcnum = tr32(TG3_CPMU_STATUS) & TG3_CPMU_STATUS_PCIE_FUNC;
1041                 if (funcnum)
1042                         tp->phy_addr = 2;
1043                 else
1044                         tp->phy_addr = 1;
1045
1046                 is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1047                 if (is_serdes)
1048                         tp->phy_addr += 7;
1049         } else
1050                 tp->phy_addr = TG3_PHY_MII_ADDR;
1051
1052         if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
1053             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1054                 tg3_mdio_config_5785(tp);
1055 }
1056
1057 static int tg3_mdio_init(struct tg3 *tp)
1058 {
1059         int i;
1060         u32 reg;
1061         struct phy_device *phydev;
1062
1063         tg3_mdio_start(tp);
1064
1065         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1066             (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1067                 return 0;
1068
1069         tp->mdio_bus = mdiobus_alloc();
1070         if (tp->mdio_bus == NULL)
1071                 return -ENOMEM;
1072
1073         tp->mdio_bus->name     = "tg3 mdio bus";
1074         snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1075                  (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1076         tp->mdio_bus->priv     = tp;
1077         tp->mdio_bus->parent   = &tp->pdev->dev;
1078         tp->mdio_bus->read     = &tg3_mdio_read;
1079         tp->mdio_bus->write    = &tg3_mdio_write;
1080         tp->mdio_bus->reset    = &tg3_mdio_reset;
1081         tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
1082         tp->mdio_bus->irq      = &tp->mdio_irq[0];
1083
1084         for (i = 0; i < PHY_MAX_ADDR; i++)
1085                 tp->mdio_bus->irq[i] = PHY_POLL;
1086
1087         /* The bus registration will look for all the PHYs on the mdio bus.
1088          * Unfortunately, it does not ensure the PHY is powered up before
1089          * accessing the PHY ID registers.  A chip reset is the
1090          * quickest way to bring the device back to an operational state..
1091          */
1092         if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1093                 tg3_bmcr_reset(tp);
1094
1095         i = mdiobus_register(tp->mdio_bus);
1096         if (i) {
1097                 printk(KERN_WARNING "%s: mdiobus_reg failed (0x%x)\n",
1098                         tp->dev->name, i);
1099                 mdiobus_free(tp->mdio_bus);
1100                 return i;
1101         }
1102
1103         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1104
1105         if (!phydev || !phydev->drv) {
1106                 printk(KERN_WARNING "%s: No PHY devices\n", tp->dev->name);
1107                 mdiobus_unregister(tp->mdio_bus);
1108                 mdiobus_free(tp->mdio_bus);
1109                 return -ENODEV;
1110         }
1111
1112         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1113         case TG3_PHY_ID_BCM57780:
1114                 phydev->interface = PHY_INTERFACE_MODE_GMII;
1115                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1116                 break;
1117         case TG3_PHY_ID_BCM50610:
1118         case TG3_PHY_ID_BCM50610M:
1119                 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
1120                                      PHY_BRCM_RX_REFCLK_UNUSED |
1121                                      PHY_BRCM_DIS_TXCRXC_NOENRGY |
1122                                      PHY_BRCM_AUTO_PWRDWN_ENABLE;
1123                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)
1124                         phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1125                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1126                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1127                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1128                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1129                 /* fallthru */
1130         case TG3_PHY_ID_RTL8211C:
1131                 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1132                 break;
1133         case TG3_PHY_ID_RTL8201E:
1134         case TG3_PHY_ID_BCMAC131:
1135                 phydev->interface = PHY_INTERFACE_MODE_MII;
1136                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1137                 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
1138                 break;
1139         }
1140
1141         tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1142
1143         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1144                 tg3_mdio_config_5785(tp);
1145
1146         return 0;
1147 }
1148
1149 static void tg3_mdio_fini(struct tg3 *tp)
1150 {
1151         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1152                 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
1153                 mdiobus_unregister(tp->mdio_bus);
1154                 mdiobus_free(tp->mdio_bus);
1155         }
1156 }
1157
1158 /* tp->lock is held. */
1159 static inline void tg3_generate_fw_event(struct tg3 *tp)
1160 {
1161         u32 val;
1162
1163         val = tr32(GRC_RX_CPU_EVENT);
1164         val |= GRC_RX_CPU_DRIVER_EVENT;
1165         tw32_f(GRC_RX_CPU_EVENT, val);
1166
1167         tp->last_event_jiffies = jiffies;
1168 }
1169
1170 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1171
1172 /* tp->lock is held. */
1173 static void tg3_wait_for_event_ack(struct tg3 *tp)
1174 {
1175         int i;
1176         unsigned int delay_cnt;
1177         long time_remain;
1178
1179         /* If enough time has passed, no wait is necessary. */
1180         time_remain = (long)(tp->last_event_jiffies + 1 +
1181                       usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1182                       (long)jiffies;
1183         if (time_remain < 0)
1184                 return;
1185
1186         /* Check if we can shorten the wait time. */
1187         delay_cnt = jiffies_to_usecs(time_remain);
1188         if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1189                 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1190         delay_cnt = (delay_cnt >> 3) + 1;
1191
1192         for (i = 0; i < delay_cnt; i++) {
1193                 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1194                         break;
1195                 udelay(8);
1196         }
1197 }
1198
1199 /* tp->lock is held. */
1200 static void tg3_ump_link_report(struct tg3 *tp)
1201 {
1202         u32 reg;
1203         u32 val;
1204
1205         if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1206             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
1207                 return;
1208
1209         tg3_wait_for_event_ack(tp);
1210
1211         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1212
1213         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1214
1215         val = 0;
1216         if (!tg3_readphy(tp, MII_BMCR, &reg))
1217                 val = reg << 16;
1218         if (!tg3_readphy(tp, MII_BMSR, &reg))
1219                 val |= (reg & 0xffff);
1220         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1221
1222         val = 0;
1223         if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1224                 val = reg << 16;
1225         if (!tg3_readphy(tp, MII_LPA, &reg))
1226                 val |= (reg & 0xffff);
1227         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1228
1229         val = 0;
1230         if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) {
1231                 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1232                         val = reg << 16;
1233                 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1234                         val |= (reg & 0xffff);
1235         }
1236         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1237
1238         if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1239                 val = reg << 16;
1240         else
1241                 val = 0;
1242         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1243
1244         tg3_generate_fw_event(tp);
1245 }
1246
1247 static void tg3_link_report(struct tg3 *tp)
1248 {
1249         if (!netif_carrier_ok(tp->dev)) {
1250                 if (netif_msg_link(tp))
1251                         printk(KERN_INFO PFX "%s: Link is down.\n",
1252                                tp->dev->name);
1253                 tg3_ump_link_report(tp);
1254         } else if (netif_msg_link(tp)) {
1255                 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1256                        tp->dev->name,
1257                        (tp->link_config.active_speed == SPEED_1000 ?
1258                         1000 :
1259                         (tp->link_config.active_speed == SPEED_100 ?
1260                          100 : 10)),
1261                        (tp->link_config.active_duplex == DUPLEX_FULL ?
1262                         "full" : "half"));
1263
1264                 printk(KERN_INFO PFX
1265                        "%s: Flow control is %s for TX and %s for RX.\n",
1266                        tp->dev->name,
1267                        (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1268                        "on" : "off",
1269                        (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1270                        "on" : "off");
1271                 tg3_ump_link_report(tp);
1272         }
1273 }
1274
1275 static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1276 {
1277         u16 miireg;
1278
1279         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1280                 miireg = ADVERTISE_PAUSE_CAP;
1281         else if (flow_ctrl & FLOW_CTRL_TX)
1282                 miireg = ADVERTISE_PAUSE_ASYM;
1283         else if (flow_ctrl & FLOW_CTRL_RX)
1284                 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1285         else
1286                 miireg = 0;
1287
1288         return miireg;
1289 }
1290
1291 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1292 {
1293         u16 miireg;
1294
1295         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1296                 miireg = ADVERTISE_1000XPAUSE;
1297         else if (flow_ctrl & FLOW_CTRL_TX)
1298                 miireg = ADVERTISE_1000XPSE_ASYM;
1299         else if (flow_ctrl & FLOW_CTRL_RX)
1300                 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1301         else
1302                 miireg = 0;
1303
1304         return miireg;
1305 }
1306
1307 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1308 {
1309         u8 cap = 0;
1310
1311         if (lcladv & ADVERTISE_1000XPAUSE) {
1312                 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1313                         if (rmtadv & LPA_1000XPAUSE)
1314                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1315                         else if (rmtadv & LPA_1000XPAUSE_ASYM)
1316                                 cap = FLOW_CTRL_RX;
1317                 } else {
1318                         if (rmtadv & LPA_1000XPAUSE)
1319                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1320                 }
1321         } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1322                 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1323                         cap = FLOW_CTRL_TX;
1324         }
1325
1326         return cap;
1327 }
1328
1329 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1330 {
1331         u8 autoneg;
1332         u8 flowctrl = 0;
1333         u32 old_rx_mode = tp->rx_mode;
1334         u32 old_tx_mode = tp->tx_mode;
1335
1336         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
1337                 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
1338         else
1339                 autoneg = tp->link_config.autoneg;
1340
1341         if (autoneg == AUTONEG_ENABLE &&
1342             (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1343                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1344                         flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1345                 else
1346                         flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1347         } else
1348                 flowctrl = tp->link_config.flowctrl;
1349
1350         tp->link_config.active_flowctrl = flowctrl;
1351
1352         if (flowctrl & FLOW_CTRL_RX)
1353                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1354         else
1355                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1356
1357         if (old_rx_mode != tp->rx_mode)
1358                 tw32_f(MAC_RX_MODE, tp->rx_mode);
1359
1360         if (flowctrl & FLOW_CTRL_TX)
1361                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1362         else
1363                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1364
1365         if (old_tx_mode != tp->tx_mode)
1366                 tw32_f(MAC_TX_MODE, tp->tx_mode);
1367 }
1368
1369 static void tg3_adjust_link(struct net_device *dev)
1370 {
1371         u8 oldflowctrl, linkmesg = 0;
1372         u32 mac_mode, lcl_adv, rmt_adv;
1373         struct tg3 *tp = netdev_priv(dev);
1374         struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1375
1376         spin_lock_bh(&tp->lock);
1377
1378         mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1379                                     MAC_MODE_HALF_DUPLEX);
1380
1381         oldflowctrl = tp->link_config.active_flowctrl;
1382
1383         if (phydev->link) {
1384                 lcl_adv = 0;
1385                 rmt_adv = 0;
1386
1387                 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1388                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1389                 else if (phydev->speed == SPEED_1000 ||
1390                          GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
1391                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
1392                 else
1393                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1394
1395                 if (phydev->duplex == DUPLEX_HALF)
1396                         mac_mode |= MAC_MODE_HALF_DUPLEX;
1397                 else {
1398                         lcl_adv = tg3_advert_flowctrl_1000T(
1399                                   tp->link_config.flowctrl);
1400
1401                         if (phydev->pause)
1402                                 rmt_adv = LPA_PAUSE_CAP;
1403                         if (phydev->asym_pause)
1404                                 rmt_adv |= LPA_PAUSE_ASYM;
1405                 }
1406
1407                 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1408         } else
1409                 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1410
1411         if (mac_mode != tp->mac_mode) {
1412                 tp->mac_mode = mac_mode;
1413                 tw32_f(MAC_MODE, tp->mac_mode);
1414                 udelay(40);
1415         }
1416
1417         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1418                 if (phydev->speed == SPEED_10)
1419                         tw32(MAC_MI_STAT,
1420                              MAC_MI_STAT_10MBPS_MODE |
1421                              MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1422                 else
1423                         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1424         }
1425
1426         if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1427                 tw32(MAC_TX_LENGTHS,
1428                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1429                       (6 << TX_LENGTHS_IPG_SHIFT) |
1430                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1431         else
1432                 tw32(MAC_TX_LENGTHS,
1433                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1434                       (6 << TX_LENGTHS_IPG_SHIFT) |
1435                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1436
1437         if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1438             (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1439             phydev->speed != tp->link_config.active_speed ||
1440             phydev->duplex != tp->link_config.active_duplex ||
1441             oldflowctrl != tp->link_config.active_flowctrl)
1442             linkmesg = 1;
1443
1444         tp->link_config.active_speed = phydev->speed;
1445         tp->link_config.active_duplex = phydev->duplex;
1446
1447         spin_unlock_bh(&tp->lock);
1448
1449         if (linkmesg)
1450                 tg3_link_report(tp);
1451 }
1452
1453 static int tg3_phy_init(struct tg3 *tp)
1454 {
1455         struct phy_device *phydev;
1456
1457         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
1458                 return 0;
1459
1460         /* Bring the PHY back to a known state. */
1461         tg3_bmcr_reset(tp);
1462
1463         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1464
1465         /* Attach the MAC to the PHY. */
1466         phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
1467                              phydev->dev_flags, phydev->interface);
1468         if (IS_ERR(phydev)) {
1469                 printk(KERN_ERR "%s: Could not attach to PHY\n", tp->dev->name);
1470                 return PTR_ERR(phydev);
1471         }
1472
1473         /* Mask with MAC supported features. */
1474         switch (phydev->interface) {
1475         case PHY_INTERFACE_MODE_GMII:
1476         case PHY_INTERFACE_MODE_RGMII:
1477                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1478                         phydev->supported &= (PHY_GBIT_FEATURES |
1479                                               SUPPORTED_Pause |
1480                                               SUPPORTED_Asym_Pause);
1481                         break;
1482                 }
1483                 /* fallthru */
1484         case PHY_INTERFACE_MODE_MII:
1485                 phydev->supported &= (PHY_BASIC_FEATURES |
1486                                       SUPPORTED_Pause |
1487                                       SUPPORTED_Asym_Pause);
1488                 break;
1489         default:
1490                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1491                 return -EINVAL;
1492         }
1493
1494         tp->tg3_flags3 |= TG3_FLG3_PHY_CONNECTED;
1495
1496         phydev->advertising = phydev->supported;
1497
1498         return 0;
1499 }
1500
1501 static void tg3_phy_start(struct tg3 *tp)
1502 {
1503         struct phy_device *phydev;
1504
1505         if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1506                 return;
1507
1508         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1509
1510         if (tp->link_config.phy_is_low_power) {
1511                 tp->link_config.phy_is_low_power = 0;
1512                 phydev->speed = tp->link_config.orig_speed;
1513                 phydev->duplex = tp->link_config.orig_duplex;
1514                 phydev->autoneg = tp->link_config.orig_autoneg;
1515                 phydev->advertising = tp->link_config.orig_advertising;
1516         }
1517
1518         phy_start(phydev);
1519
1520         phy_start_aneg(phydev);
1521 }
1522
1523 static void tg3_phy_stop(struct tg3 *tp)
1524 {
1525         if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1526                 return;
1527
1528         phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1529 }
1530
1531 static void tg3_phy_fini(struct tg3 *tp)
1532 {
1533         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
1534                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1535                 tp->tg3_flags3 &= ~TG3_FLG3_PHY_CONNECTED;
1536         }
1537 }
1538
1539 static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1540 {
1541         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1542         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1543 }
1544
1545 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1546 {
1547         u32 phytest;
1548
1549         if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1550                 u32 phy;
1551
1552                 tg3_writephy(tp, MII_TG3_FET_TEST,
1553                              phytest | MII_TG3_FET_SHADOW_EN);
1554                 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1555                         if (enable)
1556                                 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1557                         else
1558                                 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1559                         tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1560                 }
1561                 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1562         }
1563 }
1564
1565 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1566 {
1567         u32 reg;
1568
1569         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1570                 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
1571              (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
1572                 return;
1573
1574         if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1575                 tg3_phy_fet_toggle_apd(tp, enable);
1576                 return;
1577         }
1578
1579         reg = MII_TG3_MISC_SHDW_WREN |
1580               MII_TG3_MISC_SHDW_SCR5_SEL |
1581               MII_TG3_MISC_SHDW_SCR5_LPED |
1582               MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1583               MII_TG3_MISC_SHDW_SCR5_SDTL |
1584               MII_TG3_MISC_SHDW_SCR5_C125OE;
1585         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1586                 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1587
1588         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1589
1590
1591         reg = MII_TG3_MISC_SHDW_WREN |
1592               MII_TG3_MISC_SHDW_APD_SEL |
1593               MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1594         if (enable)
1595                 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1596
1597         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1598 }
1599
1600 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1601 {
1602         u32 phy;
1603
1604         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1605             (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1606                 return;
1607
1608         if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1609                 u32 ephy;
1610
1611                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1612                         u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1613
1614                         tg3_writephy(tp, MII_TG3_FET_TEST,
1615                                      ephy | MII_TG3_FET_SHADOW_EN);
1616                         if (!tg3_readphy(tp, reg, &phy)) {
1617                                 if (enable)
1618                                         phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1619                                 else
1620                                         phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1621                                 tg3_writephy(tp, reg, phy);
1622                         }
1623                         tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
1624                 }
1625         } else {
1626                 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1627                       MII_TG3_AUXCTL_SHDWSEL_MISC;
1628                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1629                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1630                         if (enable)
1631                                 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1632                         else
1633                                 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1634                         phy |= MII_TG3_AUXCTL_MISC_WREN;
1635                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1636                 }
1637         }
1638 }
1639
1640 static void tg3_phy_set_wirespeed(struct tg3 *tp)
1641 {
1642         u32 val;
1643
1644         if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
1645                 return;
1646
1647         if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1648             !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1649                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1650                              (val | (1 << 15) | (1 << 4)));
1651 }
1652
1653 static void tg3_phy_apply_otp(struct tg3 *tp)
1654 {
1655         u32 otp, phy;
1656
1657         if (!tp->phy_otp)
1658                 return;
1659
1660         otp = tp->phy_otp;
1661
1662         /* Enable SM_DSP clock and tx 6dB coding. */
1663         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1664               MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1665               MII_TG3_AUXCTL_ACTL_TX_6DB;
1666         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1667
1668         phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1669         phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1670         tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1671
1672         phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1673               ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1674         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1675
1676         phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1677         phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1678         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1679
1680         phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1681         tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1682
1683         phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1684         tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1685
1686         phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1687               ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1688         tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1689
1690         /* Turn off SM_DSP clock. */
1691         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1692               MII_TG3_AUXCTL_ACTL_TX_6DB;
1693         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1694 }
1695
1696 static int tg3_wait_macro_done(struct tg3 *tp)
1697 {
1698         int limit = 100;
1699
1700         while (limit--) {
1701                 u32 tmp32;
1702
1703                 if (!tg3_readphy(tp, 0x16, &tmp32)) {
1704                         if ((tmp32 & 0x1000) == 0)
1705                                 break;
1706                 }
1707         }
1708         if (limit < 0)
1709                 return -EBUSY;
1710
1711         return 0;
1712 }
1713
1714 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1715 {
1716         static const u32 test_pat[4][6] = {
1717         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1718         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1719         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1720         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1721         };
1722         int chan;
1723
1724         for (chan = 0; chan < 4; chan++) {
1725                 int i;
1726
1727                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1728                              (chan * 0x2000) | 0x0200);
1729                 tg3_writephy(tp, 0x16, 0x0002);
1730
1731                 for (i = 0; i < 6; i++)
1732                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1733                                      test_pat[chan][i]);
1734
1735                 tg3_writephy(tp, 0x16, 0x0202);
1736                 if (tg3_wait_macro_done(tp)) {
1737                         *resetp = 1;
1738                         return -EBUSY;
1739                 }
1740
1741                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1742                              (chan * 0x2000) | 0x0200);
1743                 tg3_writephy(tp, 0x16, 0x0082);
1744                 if (tg3_wait_macro_done(tp)) {
1745                         *resetp = 1;
1746                         return -EBUSY;
1747                 }
1748
1749                 tg3_writephy(tp, 0x16, 0x0802);
1750                 if (tg3_wait_macro_done(tp)) {
1751                         *resetp = 1;
1752                         return -EBUSY;
1753                 }
1754
1755                 for (i = 0; i < 6; i += 2) {
1756                         u32 low, high;
1757
1758                         if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1759                             tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1760                             tg3_wait_macro_done(tp)) {
1761                                 *resetp = 1;
1762                                 return -EBUSY;
1763                         }
1764                         low &= 0x7fff;
1765                         high &= 0x000f;
1766                         if (low != test_pat[chan][i] ||
1767                             high != test_pat[chan][i+1]) {
1768                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1769                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1770                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1771
1772                                 return -EBUSY;
1773                         }
1774                 }
1775         }
1776
1777         return 0;
1778 }
1779
1780 static int tg3_phy_reset_chanpat(struct tg3 *tp)
1781 {
1782         int chan;
1783
1784         for (chan = 0; chan < 4; chan++) {
1785                 int i;
1786
1787                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1788                              (chan * 0x2000) | 0x0200);
1789                 tg3_writephy(tp, 0x16, 0x0002);
1790                 for (i = 0; i < 6; i++)
1791                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1792                 tg3_writephy(tp, 0x16, 0x0202);
1793                 if (tg3_wait_macro_done(tp))
1794                         return -EBUSY;
1795         }
1796
1797         return 0;
1798 }
1799
1800 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1801 {
1802         u32 reg32, phy9_orig;
1803         int retries, do_phy_reset, err;
1804
1805         retries = 10;
1806         do_phy_reset = 1;
1807         do {
1808                 if (do_phy_reset) {
1809                         err = tg3_bmcr_reset(tp);
1810                         if (err)
1811                                 return err;
1812                         do_phy_reset = 0;
1813                 }
1814
1815                 /* Disable transmitter and interrupt.  */
1816                 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1817                         continue;
1818
1819                 reg32 |= 0x3000;
1820                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1821
1822                 /* Set full-duplex, 1000 mbps.  */
1823                 tg3_writephy(tp, MII_BMCR,
1824                              BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1825
1826                 /* Set to master mode.  */
1827                 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1828                         continue;
1829
1830                 tg3_writephy(tp, MII_TG3_CTRL,
1831                              (MII_TG3_CTRL_AS_MASTER |
1832                               MII_TG3_CTRL_ENABLE_AS_MASTER));
1833
1834                 /* Enable SM_DSP_CLOCK and 6dB.  */
1835                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1836
1837                 /* Block the PHY control access.  */
1838                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1839                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
1840
1841                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1842                 if (!err)
1843                         break;
1844         } while (--retries);
1845
1846         err = tg3_phy_reset_chanpat(tp);
1847         if (err)
1848                 return err;
1849
1850         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1851         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
1852
1853         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1854         tg3_writephy(tp, 0x16, 0x0000);
1855
1856         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1857             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1858                 /* Set Extended packet length bit for jumbo frames */
1859                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1860         }
1861         else {
1862                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1863         }
1864
1865         tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1866
1867         if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1868                 reg32 &= ~0x3000;
1869                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1870         } else if (!err)
1871                 err = -EBUSY;
1872
1873         return err;
1874 }
1875
1876 /* This will reset the tigon3 PHY if there is no valid
1877  * link unless the FORCE argument is non-zero.
1878  */
1879 static int tg3_phy_reset(struct tg3 *tp)
1880 {
1881         u32 cpmuctrl;
1882         u32 phy_status;
1883         int err;
1884
1885         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1886                 u32 val;
1887
1888                 val = tr32(GRC_MISC_CFG);
1889                 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1890                 udelay(40);
1891         }
1892         err  = tg3_readphy(tp, MII_BMSR, &phy_status);
1893         err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1894         if (err != 0)
1895                 return -EBUSY;
1896
1897         if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1898                 netif_carrier_off(tp->dev);
1899                 tg3_link_report(tp);
1900         }
1901
1902         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1903             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1904             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1905                 err = tg3_phy_reset_5703_4_5(tp);
1906                 if (err)
1907                         return err;
1908                 goto out;
1909         }
1910
1911         cpmuctrl = 0;
1912         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1913             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1914                 cpmuctrl = tr32(TG3_CPMU_CTRL);
1915                 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1916                         tw32(TG3_CPMU_CTRL,
1917                              cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1918         }
1919
1920         err = tg3_bmcr_reset(tp);
1921         if (err)
1922                 return err;
1923
1924         if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1925                 u32 phy;
1926
1927                 phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1928                 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy);
1929
1930                 tw32(TG3_CPMU_CTRL, cpmuctrl);
1931         }
1932
1933         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
1934             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
1935                 u32 val;
1936
1937                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1938                 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1939                     CPMU_LSPD_1000MB_MACCLK_12_5) {
1940                         val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1941                         udelay(40);
1942                         tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1943                 }
1944         }
1945
1946         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
1947             (tp->tg3_flags2 & TG3_FLG2_MII_SERDES))
1948                 return 0;
1949
1950         tg3_phy_apply_otp(tp);
1951
1952         if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
1953                 tg3_phy_toggle_apd(tp, true);
1954         else
1955                 tg3_phy_toggle_apd(tp, false);
1956
1957 out:
1958         if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1959                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1960                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1961                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1962                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1963                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
1964                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1965         }
1966         if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
1967                 tg3_writephy(tp, 0x1c, 0x8d68);
1968                 tg3_writephy(tp, 0x1c, 0x8d68);
1969         }
1970         if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1971                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1972                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1973                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1974                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1975                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1976                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1977                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1978                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1979         }
1980         else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1981                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1982                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1983                 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1984                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1985                         tg3_writephy(tp, MII_TG3_TEST1,
1986                                      MII_TG3_TEST1_TRIM_EN | 0x4);
1987                 } else
1988                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
1989                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1990         }
1991         /* Set Extended packet length bit (bit 14) on all chips that */
1992         /* support jumbo frames */
1993         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1994                 /* Cannot do read-modify-write on 5401 */
1995                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1996         } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1997                 u32 phy_reg;
1998
1999                 /* Set bit 14 with read-modify-write to preserve other bits */
2000                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
2001                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
2002                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
2003         }
2004
2005         /* Set phy register 0x10 bit 0 to high fifo elasticity to support
2006          * jumbo frames transmission.
2007          */
2008         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2009                 u32 phy_reg;
2010
2011                 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
2012                     tg3_writephy(tp, MII_TG3_EXT_CTRL,
2013                                  phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
2014         }
2015
2016         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2017                 /* adjust output voltage */
2018                 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
2019         }
2020
2021         tg3_phy_toggle_automdix(tp, 1);
2022         tg3_phy_set_wirespeed(tp);
2023         return 0;
2024 }
2025
2026 static void tg3_frob_aux_power(struct tg3 *tp)
2027 {
2028         struct tg3 *tp_peer = tp;
2029
2030         /* The GPIOs do something completely different on 57765. */
2031         if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0 ||
2032             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
2033                 return;
2034
2035         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2036             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
2037             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
2038                 struct net_device *dev_peer;
2039
2040                 dev_peer = pci_get_drvdata(tp->pdev_peer);
2041                 /* remove_one() may have been run on the peer. */
2042                 if (!dev_peer)
2043                         tp_peer = tp;
2044                 else
2045                         tp_peer = netdev_priv(dev_peer);
2046         }
2047
2048         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2049             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
2050             (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2051             (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
2052                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2053                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2054                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2055                                     (GRC_LCLCTRL_GPIO_OE0 |
2056                                      GRC_LCLCTRL_GPIO_OE1 |
2057                                      GRC_LCLCTRL_GPIO_OE2 |
2058                                      GRC_LCLCTRL_GPIO_OUTPUT0 |
2059                                      GRC_LCLCTRL_GPIO_OUTPUT1),
2060                                     100);
2061                 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2062                            tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2063                         /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2064                         u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2065                                              GRC_LCLCTRL_GPIO_OE1 |
2066                                              GRC_LCLCTRL_GPIO_OE2 |
2067                                              GRC_LCLCTRL_GPIO_OUTPUT0 |
2068                                              GRC_LCLCTRL_GPIO_OUTPUT1 |
2069                                              tp->grc_local_ctrl;
2070                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2071
2072                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2073                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2074
2075                         grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2076                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2077                 } else {
2078                         u32 no_gpio2;
2079                         u32 grc_local_ctrl = 0;
2080
2081                         if (tp_peer != tp &&
2082                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2083                                 return;
2084
2085                         /* Workaround to prevent overdrawing Amps. */
2086                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2087                             ASIC_REV_5714) {
2088                                 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2089                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2090                                             grc_local_ctrl, 100);
2091                         }
2092
2093                         /* On 5753 and variants, GPIO2 cannot be used. */
2094                         no_gpio2 = tp->nic_sram_data_cfg &
2095                                     NIC_SRAM_DATA_CFG_NO_GPIO2;
2096
2097                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2098                                          GRC_LCLCTRL_GPIO_OE1 |
2099                                          GRC_LCLCTRL_GPIO_OE2 |
2100                                          GRC_LCLCTRL_GPIO_OUTPUT1 |
2101                                          GRC_LCLCTRL_GPIO_OUTPUT2;
2102                         if (no_gpio2) {
2103                                 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2104                                                     GRC_LCLCTRL_GPIO_OUTPUT2);
2105                         }
2106                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2107                                                     grc_local_ctrl, 100);
2108
2109                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2110
2111                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2112                                                     grc_local_ctrl, 100);
2113
2114                         if (!no_gpio2) {
2115                                 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2116                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2117                                             grc_local_ctrl, 100);
2118                         }
2119                 }
2120         } else {
2121                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2122                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2123                         if (tp_peer != tp &&
2124                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2125                                 return;
2126
2127                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2128                                     (GRC_LCLCTRL_GPIO_OE1 |
2129                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2130
2131                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2132                                     GRC_LCLCTRL_GPIO_OE1, 100);
2133
2134                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2135                                     (GRC_LCLCTRL_GPIO_OE1 |
2136                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2137                 }
2138         }
2139 }
2140
2141 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2142 {
2143         if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2144                 return 1;
2145         else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411) {
2146                 if (speed != SPEED_10)
2147                         return 1;
2148         } else if (speed == SPEED_10)
2149                 return 1;
2150
2151         return 0;
2152 }
2153
2154 static int tg3_setup_phy(struct tg3 *, int);
2155
2156 #define RESET_KIND_SHUTDOWN     0
2157 #define RESET_KIND_INIT         1
2158 #define RESET_KIND_SUSPEND      2
2159
2160 static void tg3_write_sig_post_reset(struct tg3 *, int);
2161 static int tg3_halt_cpu(struct tg3 *, u32);
2162
2163 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2164 {
2165         u32 val;
2166
2167         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2168                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2169                         u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2170                         u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2171
2172                         sg_dig_ctrl |=
2173                                 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2174                         tw32(SG_DIG_CTRL, sg_dig_ctrl);
2175                         tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2176                 }
2177                 return;
2178         }
2179
2180         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2181                 tg3_bmcr_reset(tp);
2182                 val = tr32(GRC_MISC_CFG);
2183                 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2184                 udelay(40);
2185                 return;
2186         } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
2187                 u32 phytest;
2188                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2189                         u32 phy;
2190
2191                         tg3_writephy(tp, MII_ADVERTISE, 0);
2192                         tg3_writephy(tp, MII_BMCR,
2193                                      BMCR_ANENABLE | BMCR_ANRESTART);
2194
2195                         tg3_writephy(tp, MII_TG3_FET_TEST,
2196                                      phytest | MII_TG3_FET_SHADOW_EN);
2197                         if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
2198                                 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
2199                                 tg3_writephy(tp,
2200                                              MII_TG3_FET_SHDW_AUXMODE4,
2201                                              phy);
2202                         }
2203                         tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2204                 }
2205                 return;
2206         } else if (do_low_power) {
2207                 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2208                              MII_TG3_EXT_CTRL_FORCE_LED_OFF);
2209
2210                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2211                              MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2212                              MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2213                              MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2214                              MII_TG3_AUXCTL_PCTL_VREG_11V);
2215         }
2216
2217         /* The PHY should not be powered down on some chips because
2218          * of bugs.
2219          */
2220         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2221             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2222             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2223              (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
2224                 return;
2225
2226         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2227             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2228                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2229                 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2230                 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2231                 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2232         }
2233
2234         tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2235 }
2236
2237 /* tp->lock is held. */
2238 static int tg3_nvram_lock(struct tg3 *tp)
2239 {
2240         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2241                 int i;
2242
2243                 if (tp->nvram_lock_cnt == 0) {
2244                         tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2245                         for (i = 0; i < 8000; i++) {
2246                                 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2247                                         break;
2248                                 udelay(20);
2249                         }
2250                         if (i == 8000) {
2251                                 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2252                                 return -ENODEV;
2253                         }
2254                 }
2255                 tp->nvram_lock_cnt++;
2256         }
2257         return 0;
2258 }
2259
2260 /* tp->lock is held. */
2261 static void tg3_nvram_unlock(struct tg3 *tp)
2262 {
2263         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2264                 if (tp->nvram_lock_cnt > 0)
2265                         tp->nvram_lock_cnt--;
2266                 if (tp->nvram_lock_cnt == 0)
2267                         tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2268         }
2269 }
2270
2271 /* tp->lock is held. */
2272 static void tg3_enable_nvram_access(struct tg3 *tp)
2273 {
2274         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2275             !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2276                 u32 nvaccess = tr32(NVRAM_ACCESS);
2277
2278                 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2279         }
2280 }
2281
2282 /* tp->lock is held. */
2283 static void tg3_disable_nvram_access(struct tg3 *tp)
2284 {
2285         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2286             !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2287                 u32 nvaccess = tr32(NVRAM_ACCESS);
2288
2289                 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2290         }
2291 }
2292
2293 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2294                                         u32 offset, u32 *val)
2295 {
2296         u32 tmp;
2297         int i;
2298
2299         if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2300                 return -EINVAL;
2301
2302         tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2303                                         EEPROM_ADDR_DEVID_MASK |
2304                                         EEPROM_ADDR_READ);
2305         tw32(GRC_EEPROM_ADDR,
2306              tmp |
2307              (0 << EEPROM_ADDR_DEVID_SHIFT) |
2308              ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2309               EEPROM_ADDR_ADDR_MASK) |
2310              EEPROM_ADDR_READ | EEPROM_ADDR_START);
2311
2312         for (i = 0; i < 1000; i++) {
2313                 tmp = tr32(GRC_EEPROM_ADDR);
2314
2315                 if (tmp & EEPROM_ADDR_COMPLETE)
2316                         break;
2317                 msleep(1);
2318         }
2319         if (!(tmp & EEPROM_ADDR_COMPLETE))
2320                 return -EBUSY;
2321
2322         tmp = tr32(GRC_EEPROM_DATA);
2323
2324         /*
2325          * The data will always be opposite the native endian
2326          * format.  Perform a blind byteswap to compensate.
2327          */
2328         *val = swab32(tmp);
2329
2330         return 0;
2331 }
2332
2333 #define NVRAM_CMD_TIMEOUT 10000
2334
2335 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2336 {
2337         int i;
2338
2339         tw32(NVRAM_CMD, nvram_cmd);
2340         for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2341                 udelay(10);
2342                 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2343                         udelay(10);
2344                         break;
2345                 }
2346         }
2347
2348         if (i == NVRAM_CMD_TIMEOUT)
2349                 return -EBUSY;
2350
2351         return 0;
2352 }
2353
2354 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2355 {
2356         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2357             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2358             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2359            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2360             (tp->nvram_jedecnum == JEDEC_ATMEL))
2361
2362                 addr = ((addr / tp->nvram_pagesize) <<
2363                         ATMEL_AT45DB0X1B_PAGE_POS) +
2364                        (addr % tp->nvram_pagesize);
2365
2366         return addr;
2367 }
2368
2369 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2370 {
2371         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2372             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2373             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2374            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2375             (tp->nvram_jedecnum == JEDEC_ATMEL))
2376
2377                 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2378                         tp->nvram_pagesize) +
2379                        (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2380
2381         return addr;
2382 }
2383
2384 /* NOTE: Data read in from NVRAM is byteswapped according to
2385  * the byteswapping settings for all other register accesses.
2386  * tg3 devices are BE devices, so on a BE machine, the data
2387  * returned will be exactly as it is seen in NVRAM.  On a LE
2388  * machine, the 32-bit value will be byteswapped.
2389  */
2390 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2391 {
2392         int ret;
2393
2394         if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2395                 return tg3_nvram_read_using_eeprom(tp, offset, val);
2396
2397         offset = tg3_nvram_phys_addr(tp, offset);
2398
2399         if (offset > NVRAM_ADDR_MSK)
2400                 return -EINVAL;
2401
2402         ret = tg3_nvram_lock(tp);
2403         if (ret)
2404                 return ret;
2405
2406         tg3_enable_nvram_access(tp);
2407
2408         tw32(NVRAM_ADDR, offset);
2409         ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2410                 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2411
2412         if (ret == 0)
2413                 *val = tr32(NVRAM_RDDATA);
2414
2415         tg3_disable_nvram_access(tp);
2416
2417         tg3_nvram_unlock(tp);
2418
2419         return ret;
2420 }
2421
2422 /* Ensures NVRAM data is in bytestream format. */
2423 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
2424 {
2425         u32 v;
2426         int res = tg3_nvram_read(tp, offset, &v);
2427         if (!res)
2428                 *val = cpu_to_be32(v);
2429         return res;
2430 }
2431
2432 /* tp->lock is held. */
2433 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2434 {
2435         u32 addr_high, addr_low;
2436         int i;
2437
2438         addr_high = ((tp->dev->dev_addr[0] << 8) |
2439                      tp->dev->dev_addr[1]);
2440         addr_low = ((tp->dev->dev_addr[2] << 24) |
2441                     (tp->dev->dev_addr[3] << 16) |
2442                     (tp->dev->dev_addr[4] <<  8) |
2443                     (tp->dev->dev_addr[5] <<  0));
2444         for (i = 0; i < 4; i++) {
2445                 if (i == 1 && skip_mac_1)
2446                         continue;
2447                 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2448                 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2449         }
2450
2451         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2452             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2453                 for (i = 0; i < 12; i++) {
2454                         tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2455                         tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2456                 }
2457         }
2458
2459         addr_high = (tp->dev->dev_addr[0] +
2460                      tp->dev->dev_addr[1] +
2461                      tp->dev->dev_addr[2] +
2462                      tp->dev->dev_addr[3] +
2463                      tp->dev->dev_addr[4] +
2464                      tp->dev->dev_addr[5]) &
2465                 TX_BACKOFF_SEED_MASK;
2466         tw32(MAC_TX_BACKOFF_SEED, addr_high);
2467 }
2468
2469 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
2470 {
2471         u32 misc_host_ctrl;
2472         bool device_should_wake, do_low_power;
2473
2474         /* Make sure register accesses (indirect or otherwise)
2475          * will function correctly.
2476          */
2477         pci_write_config_dword(tp->pdev,
2478                                TG3PCI_MISC_HOST_CTRL,
2479                                tp->misc_host_ctrl);
2480
2481         switch (state) {
2482         case PCI_D0:
2483                 pci_enable_wake(tp->pdev, state, false);
2484                 pci_set_power_state(tp->pdev, PCI_D0);
2485
2486                 /* Switch out of Vaux if it is a NIC */
2487                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
2488                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
2489
2490                 return 0;
2491
2492         case PCI_D1:
2493         case PCI_D2:
2494         case PCI_D3hot:
2495                 break;
2496
2497         default:
2498                 printk(KERN_ERR PFX "%s: Invalid power state (D%d) requested\n",
2499                         tp->dev->name, state);
2500                 return -EINVAL;
2501         }
2502
2503         /* Restore the CLKREQ setting. */
2504         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2505                 u16 lnkctl;
2506
2507                 pci_read_config_word(tp->pdev,
2508                                      tp->pcie_cap + PCI_EXP_LNKCTL,
2509                                      &lnkctl);
2510                 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2511                 pci_write_config_word(tp->pdev,
2512                                       tp->pcie_cap + PCI_EXP_LNKCTL,
2513                                       lnkctl);
2514         }
2515
2516         misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2517         tw32(TG3PCI_MISC_HOST_CTRL,
2518              misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2519
2520         device_should_wake = pci_pme_capable(tp->pdev, state) &&
2521                              device_may_wakeup(&tp->pdev->dev) &&
2522                              (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2523
2524         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
2525                 do_low_power = false;
2526                 if ((tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) &&
2527                     !tp->link_config.phy_is_low_power) {
2528                         struct phy_device *phydev;
2529                         u32 phyid, advertising;
2530
2531                         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
2532
2533                         tp->link_config.phy_is_low_power = 1;
2534
2535                         tp->link_config.orig_speed = phydev->speed;
2536                         tp->link_config.orig_duplex = phydev->duplex;
2537                         tp->link_config.orig_autoneg = phydev->autoneg;
2538                         tp->link_config.orig_advertising = phydev->advertising;
2539
2540                         advertising = ADVERTISED_TP |
2541                                       ADVERTISED_Pause |
2542                                       ADVERTISED_Autoneg |
2543                                       ADVERTISED_10baseT_Half;
2544
2545                         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2546                             device_should_wake) {
2547                                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2548                                         advertising |=
2549                                                 ADVERTISED_100baseT_Half |
2550                                                 ADVERTISED_100baseT_Full |
2551                                                 ADVERTISED_10baseT_Full;
2552                                 else
2553                                         advertising |= ADVERTISED_10baseT_Full;
2554                         }
2555
2556                         phydev->advertising = advertising;
2557
2558                         phy_start_aneg(phydev);
2559
2560                         phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2561                         if (phyid != TG3_PHY_ID_BCMAC131) {
2562                                 phyid &= TG3_PHY_OUI_MASK;
2563                                 if (phyid == TG3_PHY_OUI_1 ||
2564                                     phyid == TG3_PHY_OUI_2 ||
2565                                     phyid == TG3_PHY_OUI_3)
2566                                         do_low_power = true;
2567                         }
2568                 }
2569         } else {
2570                 do_low_power = true;
2571
2572                 if (tp->link_config.phy_is_low_power == 0) {
2573                         tp->link_config.phy_is_low_power = 1;
2574                         tp->link_config.orig_speed = tp->link_config.speed;
2575                         tp->link_config.orig_duplex = tp->link_config.duplex;
2576                         tp->link_config.orig_autoneg = tp->link_config.autoneg;
2577                 }
2578
2579                 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
2580                         tp->link_config.speed = SPEED_10;
2581                         tp->link_config.duplex = DUPLEX_HALF;
2582                         tp->link_config.autoneg = AUTONEG_ENABLE;
2583                         tg3_setup_phy(tp, 0);
2584                 }
2585         }
2586
2587         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2588                 u32 val;
2589
2590                 val = tr32(GRC_VCPU_EXT_CTRL);
2591                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2592         } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2593                 int i;
2594                 u32 val;
2595
2596                 for (i = 0; i < 200; i++) {
2597                         tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2598                         if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2599                                 break;
2600                         msleep(1);
2601                 }
2602         }
2603         if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2604                 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2605                                                      WOL_DRV_STATE_SHUTDOWN |
2606                                                      WOL_DRV_WOL |
2607                                                      WOL_SET_MAGIC_PKT);
2608
2609         if (device_should_wake) {
2610                 u32 mac_mode;
2611
2612                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
2613                         if (do_low_power) {
2614                                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2615                                 udelay(40);
2616                         }
2617
2618                         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
2619                                 mac_mode = MAC_MODE_PORT_MODE_GMII;
2620                         else
2621                                 mac_mode = MAC_MODE_PORT_MODE_MII;
2622
2623                         mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2624                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2625                             ASIC_REV_5700) {
2626                                 u32 speed = (tp->tg3_flags &
2627                                              TG3_FLAG_WOL_SPEED_100MB) ?
2628                                              SPEED_100 : SPEED_10;
2629                                 if (tg3_5700_link_polarity(tp, speed))
2630                                         mac_mode |= MAC_MODE_LINK_POLARITY;
2631                                 else
2632                                         mac_mode &= ~MAC_MODE_LINK_POLARITY;
2633                         }
2634                 } else {
2635                         mac_mode = MAC_MODE_PORT_MODE_TBI;
2636                 }
2637
2638                 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
2639                         tw32(MAC_LED_CTRL, tp->led_ctrl);
2640
2641                 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2642                 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2643                     !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2644                     ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2645                      (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2646                         mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
2647
2648                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2649                         mac_mode |= tp->mac_mode &
2650                                     (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
2651                         if (mac_mode & MAC_MODE_APE_TX_EN)
2652                                 mac_mode |= MAC_MODE_TDE_ENABLE;
2653                 }
2654
2655                 tw32_f(MAC_MODE, mac_mode);
2656                 udelay(100);
2657
2658                 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2659                 udelay(10);
2660         }
2661
2662         if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2663             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2664              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2665                 u32 base_val;
2666
2667                 base_val = tp->pci_clock_ctrl;
2668                 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2669                              CLOCK_CTRL_TXCLK_DISABLE);
2670
2671                 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2672                             CLOCK_CTRL_PWRDOWN_PLL133, 40);
2673         } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
2674                    (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
2675                    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
2676                 /* do nothing */
2677         } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2678                      (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2679                 u32 newbits1, newbits2;
2680
2681                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2682                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2683                         newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2684                                     CLOCK_CTRL_TXCLK_DISABLE |
2685                                     CLOCK_CTRL_ALTCLK);
2686                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2687                 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2688                         newbits1 = CLOCK_CTRL_625_CORE;
2689                         newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2690                 } else {
2691                         newbits1 = CLOCK_CTRL_ALTCLK;
2692                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2693                 }
2694
2695                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2696                             40);
2697
2698                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2699                             40);
2700
2701                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2702                         u32 newbits3;
2703
2704                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2705                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2706                                 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2707                                             CLOCK_CTRL_TXCLK_DISABLE |
2708                                             CLOCK_CTRL_44MHZ_CORE);
2709                         } else {
2710                                 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2711                         }
2712
2713                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
2714                                     tp->pci_clock_ctrl | newbits3, 40);
2715                 }
2716         }
2717
2718         if (!(device_should_wake) &&
2719             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
2720                 tg3_power_down_phy(tp, do_low_power);
2721
2722         tg3_frob_aux_power(tp);
2723
2724         /* Workaround for unstable PLL clock */
2725         if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2726             (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2727                 u32 val = tr32(0x7d00);
2728
2729                 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2730                 tw32(0x7d00, val);
2731                 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2732                         int err;
2733
2734                         err = tg3_nvram_lock(tp);
2735                         tg3_halt_cpu(tp, RX_CPU_BASE);
2736                         if (!err)
2737                                 tg3_nvram_unlock(tp);
2738                 }
2739         }
2740
2741         tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2742
2743         if (device_should_wake)
2744                 pci_enable_wake(tp->pdev, state, true);
2745
2746         /* Finally, set the new power state. */
2747         pci_set_power_state(tp->pdev, state);
2748
2749         return 0;
2750 }
2751
2752 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2753 {
2754         switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2755         case MII_TG3_AUX_STAT_10HALF:
2756                 *speed = SPEED_10;
2757                 *duplex = DUPLEX_HALF;
2758                 break;
2759
2760         case MII_TG3_AUX_STAT_10FULL:
2761                 *speed = SPEED_10;
2762                 *duplex = DUPLEX_FULL;
2763                 break;
2764
2765         case MII_TG3_AUX_STAT_100HALF:
2766                 *speed = SPEED_100;
2767                 *duplex = DUPLEX_HALF;
2768                 break;
2769
2770         case MII_TG3_AUX_STAT_100FULL:
2771                 *speed = SPEED_100;
2772                 *duplex = DUPLEX_FULL;
2773                 break;
2774
2775         case MII_TG3_AUX_STAT_1000HALF:
2776                 *speed = SPEED_1000;
2777                 *duplex = DUPLEX_HALF;
2778                 break;
2779
2780         case MII_TG3_AUX_STAT_1000FULL:
2781                 *speed = SPEED_1000;
2782                 *duplex = DUPLEX_FULL;
2783                 break;
2784
2785         default:
2786                 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
2787                         *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2788                                  SPEED_10;
2789                         *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2790                                   DUPLEX_HALF;
2791                         break;
2792                 }
2793                 *speed = SPEED_INVALID;
2794                 *duplex = DUPLEX_INVALID;
2795                 break;
2796         }
2797 }
2798
2799 static void tg3_phy_copper_begin(struct tg3 *tp)
2800 {
2801         u32 new_adv;
2802         int i;
2803
2804         if (tp->link_config.phy_is_low_power) {
2805                 /* Entering low power mode.  Disable gigabit and
2806                  * 100baseT advertisements.
2807                  */
2808                 tg3_writephy(tp, MII_TG3_CTRL, 0);
2809
2810                 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2811                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2812                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2813                         new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2814
2815                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2816         } else if (tp->link_config.speed == SPEED_INVALID) {
2817                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
2818                         tp->link_config.advertising &=
2819                                 ~(ADVERTISED_1000baseT_Half |
2820                                   ADVERTISED_1000baseT_Full);
2821
2822                 new_adv = ADVERTISE_CSMA;
2823                 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2824                         new_adv |= ADVERTISE_10HALF;
2825                 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2826                         new_adv |= ADVERTISE_10FULL;
2827                 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2828                         new_adv |= ADVERTISE_100HALF;
2829                 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2830                         new_adv |= ADVERTISE_100FULL;
2831
2832                 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2833
2834                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2835
2836                 if (tp->link_config.advertising &
2837                     (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2838                         new_adv = 0;
2839                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2840                                 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2841                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2842                                 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2843                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
2844                             (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2845                              tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2846                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2847                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2848                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2849                 } else {
2850                         tg3_writephy(tp, MII_TG3_CTRL, 0);
2851                 }
2852         } else {
2853                 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2854                 new_adv |= ADVERTISE_CSMA;
2855
2856                 /* Asking for a specific link mode. */
2857                 if (tp->link_config.speed == SPEED_1000) {
2858                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2859
2860                         if (tp->link_config.duplex == DUPLEX_FULL)
2861                                 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2862                         else
2863                                 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2864                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2865                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2866                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2867                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2868                 } else {
2869                         if (tp->link_config.speed == SPEED_100) {
2870                                 if (tp->link_config.duplex == DUPLEX_FULL)
2871                                         new_adv |= ADVERTISE_100FULL;
2872                                 else
2873                                         new_adv |= ADVERTISE_100HALF;
2874                         } else {
2875                                 if (tp->link_config.duplex == DUPLEX_FULL)
2876                                         new_adv |= ADVERTISE_10FULL;
2877                                 else
2878                                         new_adv |= ADVERTISE_10HALF;
2879                         }
2880                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2881
2882                         new_adv = 0;
2883                 }
2884
2885                 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2886         }
2887
2888         if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2889             tp->link_config.speed != SPEED_INVALID) {
2890                 u32 bmcr, orig_bmcr;
2891
2892                 tp->link_config.active_speed = tp->link_config.speed;
2893                 tp->link_config.active_duplex = tp->link_config.duplex;
2894
2895                 bmcr = 0;
2896                 switch (tp->link_config.speed) {
2897                 default:
2898                 case SPEED_10:
2899                         break;
2900
2901                 case SPEED_100:
2902                         bmcr |= BMCR_SPEED100;
2903                         break;
2904
2905                 case SPEED_1000:
2906                         bmcr |= TG3_BMCR_SPEED1000;
2907                         break;
2908                 }
2909
2910                 if (tp->link_config.duplex == DUPLEX_FULL)
2911                         bmcr |= BMCR_FULLDPLX;
2912
2913                 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2914                     (bmcr != orig_bmcr)) {
2915                         tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2916                         for (i = 0; i < 1500; i++) {
2917                                 u32 tmp;
2918
2919                                 udelay(10);
2920                                 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2921                                     tg3_readphy(tp, MII_BMSR, &tmp))
2922                                         continue;
2923                                 if (!(tmp & BMSR_LSTATUS)) {
2924                                         udelay(40);
2925                                         break;
2926                                 }
2927                         }
2928                         tg3_writephy(tp, MII_BMCR, bmcr);
2929                         udelay(40);
2930                 }
2931         } else {
2932                 tg3_writephy(tp, MII_BMCR,
2933                              BMCR_ANENABLE | BMCR_ANRESTART);
2934         }
2935 }
2936
2937 static int tg3_init_5401phy_dsp(struct tg3 *tp)
2938 {
2939         int err;
2940
2941         /* Turn off tap power management. */
2942         /* Set Extended packet length bit */
2943         err  = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2944
2945         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
2946         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
2947
2948         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
2949         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
2950
2951         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2952         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
2953
2954         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2955         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
2956
2957         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2958         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
2959
2960         udelay(40);
2961
2962         return err;
2963 }
2964
2965 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
2966 {
2967         u32 adv_reg, all_mask = 0;
2968
2969         if (mask & ADVERTISED_10baseT_Half)
2970                 all_mask |= ADVERTISE_10HALF;
2971         if (mask & ADVERTISED_10baseT_Full)
2972                 all_mask |= ADVERTISE_10FULL;
2973         if (mask & ADVERTISED_100baseT_Half)
2974                 all_mask |= ADVERTISE_100HALF;
2975         if (mask & ADVERTISED_100baseT_Full)
2976                 all_mask |= ADVERTISE_100FULL;
2977
2978         if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
2979                 return 0;
2980
2981         if ((adv_reg & all_mask) != all_mask)
2982                 return 0;
2983         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
2984                 u32 tg3_ctrl;
2985
2986                 all_mask = 0;
2987                 if (mask & ADVERTISED_1000baseT_Half)
2988                         all_mask |= ADVERTISE_1000HALF;
2989                 if (mask & ADVERTISED_1000baseT_Full)
2990                         all_mask |= ADVERTISE_1000FULL;
2991
2992                 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
2993                         return 0;
2994
2995                 if ((tg3_ctrl & all_mask) != all_mask)
2996                         return 0;
2997         }
2998         return 1;
2999 }
3000
3001 static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
3002 {
3003         u32 curadv, reqadv;
3004
3005         if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
3006                 return 1;
3007
3008         curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3009         reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
3010
3011         if (tp->link_config.active_duplex == DUPLEX_FULL) {
3012                 if (curadv != reqadv)
3013                         return 0;
3014
3015                 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
3016                         tg3_readphy(tp, MII_LPA, rmtadv);
3017         } else {
3018                 /* Reprogram the advertisement register, even if it
3019                  * does not affect the current link.  If the link
3020                  * gets renegotiated in the future, we can save an
3021                  * additional renegotiation cycle by advertising
3022                  * it correctly in the first place.
3023                  */
3024                 if (curadv != reqadv) {
3025                         *lcladv &= ~(ADVERTISE_PAUSE_CAP |
3026                                      ADVERTISE_PAUSE_ASYM);
3027                         tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
3028                 }
3029         }
3030
3031         return 1;
3032 }
3033
3034 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
3035 {
3036         int current_link_up;
3037         u32 bmsr, dummy;
3038         u32 lcl_adv, rmt_adv;
3039         u16 current_speed;
3040         u8 current_duplex;
3041         int i, err;
3042
3043         tw32(MAC_EVENT, 0);
3044
3045         tw32_f(MAC_STATUS,
3046              (MAC_STATUS_SYNC_CHANGED |
3047               MAC_STATUS_CFG_CHANGED |
3048               MAC_STATUS_MI_COMPLETION |
3049               MAC_STATUS_LNKSTATE_CHANGED));
3050         udelay(40);
3051
3052         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
3053                 tw32_f(MAC_MI_MODE,
3054                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
3055                 udelay(80);
3056         }
3057
3058         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
3059
3060         /* Some third-party PHYs need to be reset on link going
3061          * down.
3062          */
3063         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3064              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
3065              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
3066             netif_carrier_ok(tp->dev)) {
3067                 tg3_readphy(tp, MII_BMSR, &bmsr);
3068                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3069                     !(bmsr & BMSR_LSTATUS))
3070                         force_reset = 1;
3071         }
3072         if (force_reset)
3073                 tg3_phy_reset(tp);
3074
3075         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
3076                 tg3_readphy(tp, MII_BMSR, &bmsr);
3077                 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
3078                     !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
3079                         bmsr = 0;
3080
3081                 if (!(bmsr & BMSR_LSTATUS)) {
3082                         err = tg3_init_5401phy_dsp(tp);
3083                         if (err)
3084                                 return err;
3085
3086                         tg3_readphy(tp, MII_BMSR, &bmsr);
3087                         for (i = 0; i < 1000; i++) {
3088                                 udelay(10);
3089                                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3090                                     (bmsr & BMSR_LSTATUS)) {
3091                                         udelay(40);
3092                                         break;
3093                                 }
3094                         }
3095
3096                         if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
3097                             !(bmsr & BMSR_LSTATUS) &&
3098                             tp->link_config.active_speed == SPEED_1000) {
3099                                 err = tg3_phy_reset(tp);
3100                                 if (!err)
3101                                         err = tg3_init_5401phy_dsp(tp);
3102                                 if (err)
3103                                         return err;
3104                         }
3105                 }
3106         } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3107                    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3108                 /* 5701 {A0,B0} CRC bug workaround */
3109                 tg3_writephy(tp, 0x15, 0x0a75);
3110                 tg3_writephy(tp, 0x1c, 0x8c68);
3111                 tg3_writephy(tp, 0x1c, 0x8d68);
3112                 tg3_writephy(tp, 0x1c, 0x8c68);
3113         }
3114
3115         /* Clear pending interrupts... */
3116         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3117         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3118
3119         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
3120                 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
3121         else if (!(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
3122                 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3123
3124         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3125             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3126                 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3127                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
3128                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3129                 else
3130                         tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3131         }
3132
3133         current_link_up = 0;
3134         current_speed = SPEED_INVALID;
3135         current_duplex = DUPLEX_INVALID;
3136
3137         if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
3138                 u32 val;
3139
3140                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3141                 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3142                 if (!(val & (1 << 10))) {
3143                         val |= (1 << 10);
3144                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3145                         goto relink;
3146                 }
3147         }
3148
3149         bmsr = 0;
3150         for (i = 0; i < 100; i++) {
3151                 tg3_readphy(tp, MII_BMSR, &bmsr);
3152                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3153                     (bmsr & BMSR_LSTATUS))
3154                         break;
3155                 udelay(40);
3156         }
3157
3158         if (bmsr & BMSR_LSTATUS) {
3159                 u32 aux_stat, bmcr;
3160
3161                 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3162                 for (i = 0; i < 2000; i++) {
3163                         udelay(10);
3164                         if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3165                             aux_stat)
3166                                 break;
3167                 }
3168
3169                 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3170                                              &current_speed,
3171                                              &current_duplex);
3172
3173                 bmcr = 0;
3174                 for (i = 0; i < 200; i++) {
3175                         tg3_readphy(tp, MII_BMCR, &bmcr);
3176                         if (tg3_readphy(tp, MII_BMCR, &bmcr))
3177                                 continue;
3178                         if (bmcr && bmcr != 0x7fff)
3179                                 break;
3180                         udelay(10);
3181                 }
3182
3183                 lcl_adv = 0;
3184                 rmt_adv = 0;
3185
3186                 tp->link_config.active_speed = current_speed;
3187                 tp->link_config.active_duplex = current_duplex;
3188
3189                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3190                         if ((bmcr & BMCR_ANENABLE) &&
3191                             tg3_copper_is_advertising_all(tp,
3192                                                 tp->link_config.advertising)) {
3193                                 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3194                                                                   &rmt_adv))
3195                                         current_link_up = 1;
3196                         }
3197                 } else {
3198                         if (!(bmcr & BMCR_ANENABLE) &&
3199                             tp->link_config.speed == current_speed &&
3200                             tp->link_config.duplex == current_duplex &&
3201                             tp->link_config.flowctrl ==
3202                             tp->link_config.active_flowctrl) {
3203                                 current_link_up = 1;
3204                         }
3205                 }
3206
3207                 if (current_link_up == 1 &&
3208                     tp->link_config.active_duplex == DUPLEX_FULL)
3209                         tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
3210         }
3211
3212 relink:
3213         if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
3214                 u32 tmp;
3215
3216                 tg3_phy_copper_begin(tp);
3217
3218                 tg3_readphy(tp, MII_BMSR, &tmp);
3219                 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
3220                     (tmp & BMSR_LSTATUS))
3221                         current_link_up = 1;
3222         }
3223
3224         tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3225         if (current_link_up == 1) {
3226                 if (tp->link_config.active_speed == SPEED_100 ||
3227                     tp->link_config.active_speed == SPEED_10)
3228                         tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3229                 else
3230                         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3231         } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)
3232                 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3233         else
3234                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3235
3236         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3237         if (tp->link_config.active_duplex == DUPLEX_HALF)
3238                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3239
3240         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
3241                 if (current_link_up == 1 &&
3242                     tg3_5700_link_polarity(tp, tp->link_config.active_speed))
3243                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
3244                 else
3245                         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
3246         }
3247
3248         /* ??? Without this setting Netgear GA302T PHY does not
3249          * ??? send/receive packets...
3250          */
3251         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
3252             tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3253                 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3254                 tw32_f(MAC_MI_MODE, tp->mi_mode);
3255                 udelay(80);
3256         }
3257
3258         tw32_f(MAC_MODE, tp->mac_mode);
3259         udelay(40);
3260
3261         if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3262                 /* Polled via timer. */
3263                 tw32_f(MAC_EVENT, 0);
3264         } else {
3265                 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3266         }
3267         udelay(40);
3268
3269         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3270             current_link_up == 1 &&
3271             tp->link_config.active_speed == SPEED_1000 &&
3272             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3273              (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3274                 udelay(120);
3275                 tw32_f(MAC_STATUS,
3276                      (MAC_STATUS_SYNC_CHANGED |
3277                       MAC_STATUS_CFG_CHANGED));
3278                 udelay(40);
3279                 tg3_write_mem(tp,
3280                               NIC_SRAM_FIRMWARE_MBOX,
3281                               NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3282         }
3283
3284         /* Prevent send BD corruption. */
3285         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3286                 u16 oldlnkctl, newlnkctl;
3287
3288                 pci_read_config_word(tp->pdev,
3289                                      tp->pcie_cap + PCI_EXP_LNKCTL,
3290                                      &oldlnkctl);
3291                 if (tp->link_config.active_speed == SPEED_100 ||
3292                     tp->link_config.active_speed == SPEED_10)
3293                         newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3294                 else
3295                         newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3296                 if (newlnkctl != oldlnkctl)
3297                         pci_write_config_word(tp->pdev,
3298                                               tp->pcie_cap + PCI_EXP_LNKCTL,
3299                                               newlnkctl);
3300         }
3301
3302         if (current_link_up != netif_carrier_ok(tp->dev)) {
3303                 if (current_link_up)
3304                         netif_carrier_on(tp->dev);
3305                 else
3306                         netif_carrier_off(tp->dev);
3307                 tg3_link_report(tp);
3308         }
3309
3310         return 0;
3311 }
3312
3313 struct tg3_fiber_aneginfo {
3314         int state;
3315 #define ANEG_STATE_UNKNOWN              0
3316 #define ANEG_STATE_AN_ENABLE            1
3317 #define ANEG_STATE_RESTART_INIT         2
3318 #define ANEG_STATE_RESTART              3
3319 #define ANEG_STATE_DISABLE_LINK_OK      4
3320 #define ANEG_STATE_ABILITY_DETECT_INIT  5
3321 #define ANEG_STATE_ABILITY_DETECT       6
3322 #define ANEG_STATE_ACK_DETECT_INIT      7
3323 #define ANEG_STATE_ACK_DETECT           8
3324 #define ANEG_STATE_COMPLETE_ACK_INIT    9
3325 #define ANEG_STATE_COMPLETE_ACK         10
3326 #define ANEG_STATE_IDLE_DETECT_INIT     11
3327 #define ANEG_STATE_IDLE_DETECT          12
3328 #define ANEG_STATE_LINK_OK              13
3329 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT  14
3330 #define ANEG_STATE_NEXT_PAGE_WAIT       15
3331
3332         u32 flags;
3333 #define MR_AN_ENABLE            0x00000001
3334 #define MR_RESTART_AN           0x00000002
3335 #define MR_AN_COMPLETE          0x00000004
3336 #define MR_PAGE_RX              0x00000008
3337 #define MR_NP_LOADED            0x00000010
3338 #define MR_TOGGLE_TX            0x00000020
3339 #define MR_LP_ADV_FULL_DUPLEX   0x00000040
3340 #define MR_LP_ADV_HALF_DUPLEX   0x00000080
3341 #define MR_LP_ADV_SYM_PAUSE     0x00000100
3342 #define MR_LP_ADV_ASYM_PAUSE    0x00000200
3343 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3344 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3345 #define MR_LP_ADV_NEXT_PAGE     0x00001000
3346 #define MR_TOGGLE_RX            0x00002000
3347 #define MR_NP_RX                0x00004000
3348
3349 #define MR_LINK_OK              0x80000000
3350
3351         unsigned long link_time, cur_time;
3352
3353         u32 ability_match_cfg;
3354         int ability_match_count;
3355
3356         char ability_match, idle_match, ack_match;
3357
3358         u32 txconfig, rxconfig;
3359 #define ANEG_CFG_NP             0x00000080
3360 #define ANEG_CFG_ACK            0x00000040
3361 #define ANEG_CFG_RF2            0x00000020
3362 #define ANEG_CFG_RF1            0x00000010
3363 #define ANEG_CFG_PS2            0x00000001
3364 #define ANEG_CFG_PS1            0x00008000
3365 #define ANEG_CFG_HD             0x00004000
3366 #define ANEG_CFG_FD             0x00002000
3367 #define ANEG_CFG_INVAL          0x00001f06
3368
3369 };
3370 #define ANEG_OK         0
3371 #define ANEG_DONE       1
3372 #define ANEG_TIMER_ENAB 2
3373 #define ANEG_FAILED     -1
3374
3375 #define ANEG_STATE_SETTLE_TIME  10000
3376
3377 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3378                                    struct tg3_fiber_aneginfo *ap)
3379 {
3380         u16 flowctrl;
3381         unsigned long delta;
3382         u32 rx_cfg_reg;
3383         int ret;
3384
3385         if (ap->state == ANEG_STATE_UNKNOWN) {
3386                 ap->rxconfig = 0;
3387                 ap->link_time = 0;
3388                 ap->cur_time = 0;
3389                 ap->ability_match_cfg = 0;
3390                 ap->ability_match_count = 0;
3391                 ap->ability_match = 0;
3392                 ap->idle_match = 0;
3393                 ap->ack_match = 0;
3394         }
3395         ap->cur_time++;
3396
3397         if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3398                 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3399
3400                 if (rx_cfg_reg != ap->ability_match_cfg) {
3401                         ap->ability_match_cfg = rx_cfg_reg;
3402                         ap->ability_match = 0;
3403                         ap->ability_match_count = 0;
3404                 } else {
3405                         if (++ap->ability_match_count > 1) {
3406                                 ap->ability_match = 1;
3407                                 ap->ability_match_cfg = rx_cfg_reg;
3408                         }
3409                 }
3410                 if (rx_cfg_reg & ANEG_CFG_ACK)
3411                         ap->ack_match = 1;
3412                 else
3413                         ap->ack_match = 0;
3414
3415                 ap->idle_match = 0;
3416         } else {
3417                 ap->idle_match = 1;
3418                 ap->ability_match_cfg = 0;
3419                 ap->ability_match_count = 0;
3420                 ap->ability_match = 0;
3421                 ap->ack_match = 0;
3422
3423                 rx_cfg_reg = 0;
3424         }
3425
3426         ap->rxconfig = rx_cfg_reg;
3427         ret = ANEG_OK;
3428
3429         switch(ap->state) {
3430         case ANEG_STATE_UNKNOWN:
3431                 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3432                         ap->state = ANEG_STATE_AN_ENABLE;
3433
3434                 /* fallthru */
3435         case ANEG_STATE_AN_ENABLE:
3436                 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3437                 if (ap->flags & MR_AN_ENABLE) {
3438                         ap->link_time = 0;
3439                         ap->cur_time = 0;
3440                         ap->ability_match_cfg = 0;
3441                         ap->ability_match_count = 0;
3442                         ap->ability_match = 0;
3443                         ap->idle_match = 0;
3444                         ap->ack_match = 0;
3445
3446                         ap->state = ANEG_STATE_RESTART_INIT;
3447                 } else {
3448                         ap->state = ANEG_STATE_DISABLE_LINK_OK;
3449                 }
3450                 break;
3451
3452         case ANEG_STATE_RESTART_INIT:
3453                 ap->link_time = ap->cur_time;
3454                 ap->flags &= ~(MR_NP_LOADED);
3455                 ap->txconfig = 0;
3456                 tw32(MAC_TX_AUTO_NEG, 0);
3457                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3458                 tw32_f(MAC_MODE, tp->mac_mode);
3459                 udelay(40);
3460
3461                 ret = ANEG_TIMER_ENAB;
3462                 ap->state = ANEG_STATE_RESTART;
3463
3464                 /* fallthru */
3465         case ANEG_STATE_RESTART:
3466                 delta = ap->cur_time - ap->link_time;
3467                 if (delta > ANEG_STATE_SETTLE_TIME) {
3468                         ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3469                 } else {
3470                         ret = ANEG_TIMER_ENAB;
3471                 }
3472                 break;
3473
3474         case ANEG_STATE_DISABLE_LINK_OK:
3475                 ret = ANEG_DONE;
3476                 break;
3477
3478         case ANEG_STATE_ABILITY_DETECT_INIT:
3479                 ap->flags &= ~(MR_TOGGLE_TX);
3480                 ap->txconfig = ANEG_CFG_FD;
3481                 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3482                 if (flowctrl & ADVERTISE_1000XPAUSE)
3483                         ap->txconfig |= ANEG_CFG_PS1;
3484                 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3485                         ap->txconfig |= ANEG_CFG_PS2;
3486                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3487                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3488                 tw32_f(MAC_MODE, tp->mac_mode);
3489                 udelay(40);
3490
3491                 ap->state = ANEG_STATE_ABILITY_DETECT;
3492                 break;
3493
3494         case ANEG_STATE_ABILITY_DETECT:
3495                 if (ap->ability_match != 0 && ap->rxconfig != 0) {
3496                         ap->state = ANEG_STATE_ACK_DETECT_INIT;
3497                 }
3498                 break;
3499
3500         case ANEG_STATE_ACK_DETECT_INIT:
3501                 ap->txconfig |= ANEG_CFG_ACK;
3502                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3503                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3504                 tw32_f(MAC_MODE, tp->mac_mode);
3505                 udelay(40);
3506
3507                 ap->state = ANEG_STATE_ACK_DETECT;
3508
3509                 /* fallthru */
3510         case ANEG_STATE_ACK_DETECT:
3511                 if (ap->ack_match != 0) {
3512                         if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3513                             (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3514                                 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3515                         } else {
3516                                 ap->state = ANEG_STATE_AN_ENABLE;
3517                         }
3518                 } else if (ap->ability_match != 0 &&
3519                            ap->rxconfig == 0) {
3520                         ap->state = ANEG_STATE_AN_ENABLE;
3521                 }
3522                 break;
3523
3524         case ANEG_STATE_COMPLETE_ACK_INIT:
3525                 if (ap->rxconfig & ANEG_CFG_INVAL) {
3526                         ret = ANEG_FAILED;
3527                         break;
3528                 }
3529                 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3530                                MR_LP_ADV_HALF_DUPLEX |
3531                                MR_LP_ADV_SYM_PAUSE |
3532                                MR_LP_ADV_ASYM_PAUSE |
3533                                MR_LP_ADV_REMOTE_FAULT1 |
3534                                MR_LP_ADV_REMOTE_FAULT2 |
3535                                MR_LP_ADV_NEXT_PAGE |
3536                                MR_TOGGLE_RX |
3537                                MR_NP_RX);
3538                 if (ap->rxconfig & ANEG_CFG_FD)
3539                         ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3540                 if (ap->rxconfig & ANEG_CFG_HD)
3541                         ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3542                 if (ap->rxconfig & ANEG_CFG_PS1)
3543                         ap->flags |= MR_LP_ADV_SYM_PAUSE;
3544                 if (ap->rxconfig & ANEG_CFG_PS2)
3545                         ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3546                 if (ap->rxconfig & ANEG_CFG_RF1)
3547                         ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3548                 if (ap->rxconfig & ANEG_CFG_RF2)
3549                         ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3550                 if (ap->rxconfig & ANEG_CFG_NP)
3551                         ap->flags |= MR_LP_ADV_NEXT_PAGE;
3552
3553                 ap->link_time = ap->cur_time;
3554
3555                 ap->flags ^= (MR_TOGGLE_TX);
3556                 if (ap->rxconfig & 0x0008)
3557                         ap->flags |= MR_TOGGLE_RX;
3558                 if (ap->rxconfig & ANEG_CFG_NP)
3559                         ap->flags |= MR_NP_RX;
3560                 ap->flags |= MR_PAGE_RX;
3561
3562                 ap->state = ANEG_STATE_COMPLETE_ACK;
3563                 ret = ANEG_TIMER_ENAB;
3564                 break;
3565
3566         case ANEG_STATE_COMPLETE_ACK:
3567                 if (ap->ability_match != 0 &&
3568                     ap->rxconfig == 0) {
3569                         ap->state = ANEG_STATE_AN_ENABLE;
3570                         break;
3571                 }
3572                 delta = ap->cur_time - ap->link_time;
3573                 if (delta > ANEG_STATE_SETTLE_TIME) {
3574                         if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3575                                 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3576                         } else {
3577                                 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3578                                     !(ap->flags & MR_NP_RX)) {
3579                                         ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3580                                 } else {
3581                                         ret = ANEG_FAILED;
3582                                 }
3583                         }
3584                 }
3585                 break;
3586
3587         case ANEG_STATE_IDLE_DETECT_INIT:
3588                 ap->link_time = ap->cur_time;
3589                 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3590                 tw32_f(MAC_MODE, tp->mac_mode);
3591                 udelay(40);
3592
3593                 ap->state = ANEG_STATE_IDLE_DETECT;
3594                 ret = ANEG_TIMER_ENAB;
3595                 break;
3596
3597         case ANEG_STATE_IDLE_DETECT:
3598                 if (ap->ability_match != 0 &&
3599                     ap->rxconfig == 0) {
3600                         ap->state = ANEG_STATE_AN_ENABLE;
3601                         break;
3602                 }
3603                 delta = ap->cur_time - ap->link_time;
3604                 if (delta > ANEG_STATE_SETTLE_TIME) {
3605                         /* XXX another gem from the Broadcom driver :( */
3606                         ap->state = ANEG_STATE_LINK_OK;
3607                 }
3608                 break;
3609
3610         case ANEG_STATE_LINK_OK:
3611                 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3612                 ret = ANEG_DONE;
3613                 break;
3614
3615         case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3616                 /* ??? unimplemented */
3617                 break;
3618
3619         case ANEG_STATE_NEXT_PAGE_WAIT:
3620                 /* ??? unimplemented */
3621                 break;
3622
3623         default:
3624                 ret = ANEG_FAILED;
3625                 break;
3626         }
3627
3628         return ret;
3629 }
3630
3631 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
3632 {
3633         int res = 0;
3634         struct tg3_fiber_aneginfo aninfo;
3635         int status = ANEG_FAILED;
3636         unsigned int tick;
3637         u32 tmp;
3638
3639         tw32_f(MAC_TX_AUTO_NEG, 0);
3640
3641         tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3642         tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3643         udelay(40);
3644
3645         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3646         udelay(40);
3647
3648         memset(&aninfo, 0, sizeof(aninfo));
3649         aninfo.flags |= MR_AN_ENABLE;
3650         aninfo.state = ANEG_STATE_UNKNOWN;
3651         aninfo.cur_time = 0;
3652         tick = 0;
3653         while (++tick < 195000) {
3654                 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3655                 if (status == ANEG_DONE || status == ANEG_FAILED)
3656                         break;
3657
3658                 udelay(1);
3659         }
3660
3661         tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3662         tw32_f(MAC_MODE, tp->mac_mode);
3663         udelay(40);
3664
3665         *txflags = aninfo.txconfig;
3666         *rxflags = aninfo.flags;
3667
3668         if (status == ANEG_DONE &&
3669             (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3670                              MR_LP_ADV_FULL_DUPLEX)))
3671                 res = 1;
3672
3673         return res;
3674 }
3675
3676 static void tg3_init_bcm8002(struct tg3 *tp)
3677 {
3678         u32 mac_status = tr32(MAC_STATUS);
3679         int i;
3680
3681         /* Reset when initting first time or we have a link. */
3682         if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3683             !(mac_status & MAC_STATUS_PCS_SYNCED))
3684                 return;
3685
3686         /* Set PLL lock range. */
3687         tg3_writephy(tp, 0x16, 0x8007);
3688
3689         /* SW reset */
3690         tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3691
3692         /* Wait for reset to complete. */
3693         /* XXX schedule_timeout() ... */
3694         for (i = 0; i < 500; i++)
3695                 udelay(10);
3696
3697         /* Config mode; select PMA/Ch 1 regs. */
3698         tg3_writephy(tp, 0x10, 0x8411);
3699
3700         /* Enable auto-lock and comdet, select txclk for tx. */
3701         tg3_writephy(tp, 0x11, 0x0a10);
3702
3703         tg3_writephy(tp, 0x18, 0x00a0);
3704         tg3_writephy(tp, 0x16, 0x41ff);
3705
3706         /* Assert and deassert POR. */
3707         tg3_writephy(tp, 0x13, 0x0400);
3708         udelay(40);
3709         tg3_writephy(tp, 0x13, 0x0000);
3710
3711         tg3_writephy(tp, 0x11, 0x0a50);
3712         udelay(40);
3713         tg3_writephy(tp, 0x11, 0x0a10);
3714
3715         /* Wait for signal to stabilize */
3716         /* XXX schedule_timeout() ... */
3717         for (i = 0; i < 15000; i++)
3718                 udelay(10);
3719
3720         /* Deselect the channel register so we can read the PHYID
3721          * later.
3722          */
3723         tg3_writephy(tp, 0x10, 0x8011);
3724 }
3725
3726 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3727 {
3728         u16 flowctrl;
3729         u32 sg_dig_ctrl, sg_dig_status;
3730         u32 serdes_cfg, expected_sg_dig_ctrl;
3731         int workaround, port_a;
3732         int current_link_up;
3733
3734         serdes_cfg = 0;
3735         expected_sg_dig_ctrl = 0;
3736         workaround = 0;
3737         port_a = 1;
3738         current_link_up = 0;
3739
3740         if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3741             tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3742                 workaround = 1;
3743                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3744                         port_a = 0;
3745
3746                 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3747                 /* preserve bits 20-23 for voltage regulator */
3748                 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3749         }
3750
3751         sg_dig_ctrl = tr32(SG_DIG_CTRL);
3752
3753         if (tp->link_config.autoneg != AUTONEG_ENABLE) {
3754                 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
3755                         if (workaround) {
3756                                 u32 val = serdes_cfg;
3757
3758                                 if (port_a)
3759                                         val |= 0xc010000;
3760                                 else
3761                                         val |= 0x4010000;
3762                                 tw32_f(MAC_SERDES_CFG, val);
3763                         }
3764
3765                         tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3766                 }
3767                 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3768                         tg3_setup_flow_control(tp, 0, 0);
3769                         current_link_up = 1;
3770                 }
3771                 goto out;
3772         }
3773
3774         /* Want auto-negotiation.  */
3775         expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
3776
3777         flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3778         if (flowctrl & ADVERTISE_1000XPAUSE)
3779                 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3780         if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3781                 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
3782
3783         if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3784                 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
3785                     tp->serdes_counter &&
3786                     ((mac_status & (MAC_STATUS_PCS_SYNCED |
3787                                     MAC_STATUS_RCVD_CFG)) ==
3788                      MAC_STATUS_PCS_SYNCED)) {
3789                         tp->serdes_counter--;
3790                         current_link_up = 1;
3791                         goto out;
3792                 }
3793 restart_autoneg:
3794                 if (workaround)
3795                         tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
3796                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
3797                 udelay(5);
3798                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3799
3800                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3801                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3802         } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3803                                  MAC_STATUS_SIGNAL_DET)) {
3804                 sg_dig_status = tr32(SG_DIG_STATUS);
3805                 mac_status = tr32(MAC_STATUS);
3806
3807                 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
3808                     (mac_status & MAC_STATUS_PCS_SYNCED)) {
3809                         u32 local_adv = 0, remote_adv = 0;
3810
3811                         if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3812                                 local_adv |= ADVERTISE_1000XPAUSE;
3813                         if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3814                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3815
3816                         if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
3817                                 remote_adv |= LPA_1000XPAUSE;
3818                         if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
3819                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3820
3821                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3822                         current_link_up = 1;
3823                         tp->serdes_counter = 0;
3824                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3825                 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3826                         if (tp->serdes_counter)
3827                                 tp->serdes_counter--;
3828                         else {
3829                                 if (workaround) {
3830                                         u32 val = serdes_cfg;
3831
3832                                         if (port_a)
3833                                                 val |= 0xc010000;
3834                                         else
3835                                                 val |= 0x4010000;
3836
3837                                         tw32_f(MAC_SERDES_CFG, val);
3838                                 }
3839
3840                                 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3841                                 udelay(40);
3842
3843                                 /* Link parallel detection - link is up */
3844                                 /* only if we have PCS_SYNC and not */
3845                                 /* receiving config code words */
3846                                 mac_status = tr32(MAC_STATUS);
3847                                 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3848                                     !(mac_status & MAC_STATUS_RCVD_CFG)) {
3849                                         tg3_setup_flow_control(tp, 0, 0);
3850                                         current_link_up = 1;
3851                                         tp->tg3_flags2 |=
3852                                                 TG3_FLG2_PARALLEL_DETECT;
3853                                         tp->serdes_counter =
3854                                                 SERDES_PARALLEL_DET_TIMEOUT;
3855                                 } else
3856                                         goto restart_autoneg;
3857                         }
3858                 }
3859         } else {
3860                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3861                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3862         }
3863
3864 out:
3865         return current_link_up;
3866 }
3867
3868 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3869 {
3870         int current_link_up = 0;
3871
3872         if (!(mac_status & MAC_STATUS_PCS_SYNCED))
3873                 goto out;
3874
3875         if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3876                 u32 txflags, rxflags;
3877                 int i;
3878
3879                 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3880                         u32 local_adv = 0, remote_adv = 0;
3881
3882                         if (txflags & ANEG_CFG_PS1)
3883                                 local_adv |= ADVERTISE_1000XPAUSE;
3884                         if (txflags & ANEG_CFG_PS2)
3885                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3886
3887                         if (rxflags & MR_LP_ADV_SYM_PAUSE)
3888                                 remote_adv |= LPA_1000XPAUSE;
3889                         if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3890                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3891
3892                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3893
3894                         current_link_up = 1;
3895                 }
3896                 for (i = 0; i < 30; i++) {
3897                         udelay(20);
3898                         tw32_f(MAC_STATUS,
3899                                (MAC_STATUS_SYNC_CHANGED |
3900                                 MAC_STATUS_CFG_CHANGED));
3901                         udelay(40);
3902                         if ((tr32(MAC_STATUS) &
3903                              (MAC_STATUS_SYNC_CHANGED |
3904                               MAC_STATUS_CFG_CHANGED)) == 0)
3905                                 break;
3906                 }
3907
3908                 mac_status = tr32(MAC_STATUS);
3909                 if (current_link_up == 0 &&
3910                     (mac_status & MAC_STATUS_PCS_SYNCED) &&
3911                     !(mac_status & MAC_STATUS_RCVD_CFG))
3912                         current_link_up = 1;
3913         } else {
3914                 tg3_setup_flow_control(tp, 0, 0);
3915
3916                 /* Forcing 1000FD link up. */
3917                 current_link_up = 1;
3918
3919                 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3920                 udelay(40);
3921
3922                 tw32_f(MAC_MODE, tp->mac_mode);
3923                 udelay(40);
3924         }
3925
3926 out:
3927         return current_link_up;
3928 }
3929
3930 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3931 {
3932         u32 orig_pause_cfg;
3933         u16 orig_active_speed;
3934         u8 orig_active_duplex;
3935         u32 mac_status;
3936         int current_link_up;
3937         int i;
3938
3939         orig_pause_cfg = tp->link_config.active_flowctrl;
3940         orig_active_speed = tp->link_config.active_speed;
3941         orig_active_duplex = tp->link_config.active_duplex;
3942
3943         if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3944             netif_carrier_ok(tp->dev) &&
3945             (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3946                 mac_status = tr32(MAC_STATUS);
3947                 mac_status &= (MAC_STATUS_PCS_SYNCED |
3948                                MAC_STATUS_SIGNAL_DET |
3949                                MAC_STATUS_CFG_CHANGED |
3950                                MAC_STATUS_RCVD_CFG);
3951                 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3952                                    MAC_STATUS_SIGNAL_DET)) {
3953                         tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3954                                             MAC_STATUS_CFG_CHANGED));
3955                         return 0;
3956                 }
3957         }
3958
3959         tw32_f(MAC_TX_AUTO_NEG, 0);
3960
3961         tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
3962         tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
3963         tw32_f(MAC_MODE, tp->mac_mode);
3964         udelay(40);
3965
3966         if (tp->phy_id == PHY_ID_BCM8002)
3967                 tg3_init_bcm8002(tp);
3968
3969         /* Enable link change event even when serdes polling.  */
3970         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3971         udelay(40);
3972
3973         current_link_up = 0;
3974         mac_status = tr32(MAC_STATUS);
3975
3976         if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
3977                 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
3978         else
3979                 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
3980
3981         tp->napi[0].hw_status->status =
3982                 (SD_STATUS_UPDATED |
3983                  (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
3984
3985         for (i = 0; i < 100; i++) {
3986                 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3987                                     MAC_STATUS_CFG_CHANGED));
3988                 udelay(5);
3989                 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3990                                          MAC_STATUS_CFG_CHANGED |
3991                                          MAC_STATUS_LNKSTATE_CHANGED)) == 0)
3992                         break;
3993         }
3994
3995         mac_status = tr32(MAC_STATUS);
3996         if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
3997                 current_link_up = 0;
3998                 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
3999                     tp->serdes_counter == 0) {
4000                         tw32_f(MAC_MODE, (tp->mac_mode |
4001                                           MAC_MODE_SEND_CONFIGS));
4002                         udelay(1);
4003                         tw32_f(MAC_MODE, tp->mac_mode);
4004                 }
4005         }
4006
4007         if (current_link_up == 1) {
4008                 tp->link_config.active_speed = SPEED_1000;
4009                 tp->link_config.active_duplex = DUPLEX_FULL;
4010                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4011                                     LED_CTRL_LNKLED_OVERRIDE |
4012                                     LED_CTRL_1000MBPS_ON));
4013         } else {
4014                 tp->link_config.active_speed = SPEED_INVALID;
4015                 tp->link_config.active_duplex = DUPLEX_INVALID;
4016                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4017                                     LED_CTRL_LNKLED_OVERRIDE |
4018                                     LED_CTRL_TRAFFIC_OVERRIDE));
4019         }
4020
4021         if (current_link_up != netif_carrier_ok(tp->dev)) {
4022                 if (current_link_up)
4023                         netif_carrier_on(tp->dev);
4024                 else
4025                         netif_carrier_off(tp->dev);
4026                 tg3_link_report(tp);
4027         } else {
4028                 u32 now_pause_cfg = tp->link_config.active_flowctrl;
4029                 if (orig_pause_cfg != now_pause_cfg ||
4030                     orig_active_speed != tp->link_config.active_speed ||
4031                     orig_active_duplex != tp->link_config.active_duplex)
4032                         tg3_link_report(tp);
4033         }
4034
4035         return 0;
4036 }
4037
4038 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
4039 {
4040         int current_link_up, err = 0;
4041         u32 bmsr, bmcr;
4042         u16 current_speed;
4043         u8 current_duplex;
4044         u32 local_adv, remote_adv;
4045
4046         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4047         tw32_f(MAC_MODE, tp->mac_mode);
4048         udelay(40);
4049
4050         tw32(MAC_EVENT, 0);
4051
4052         tw32_f(MAC_STATUS,
4053              (MAC_STATUS_SYNC_CHANGED |
4054               MAC_STATUS_CFG_CHANGED |
4055               MAC_STATUS_MI_COMPLETION |
4056               MAC_STATUS_LNKSTATE_CHANGED));
4057         udelay(40);
4058
4059         if (force_reset)
4060                 tg3_phy_reset(tp);
4061
4062         current_link_up = 0;
4063         current_speed = SPEED_INVALID;
4064         current_duplex = DUPLEX_INVALID;
4065
4066         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4067         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4068         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
4069                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4070                         bmsr |= BMSR_LSTATUS;
4071                 else
4072                         bmsr &= ~BMSR_LSTATUS;
4073         }
4074
4075         err |= tg3_readphy(tp, MII_BMCR, &bmcr);
4076
4077         if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
4078             (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4079                 /* do nothing, just check for link up at the end */
4080         } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4081                 u32 adv, new_adv;
4082
4083                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4084                 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4085                                   ADVERTISE_1000XPAUSE |
4086                                   ADVERTISE_1000XPSE_ASYM |
4087                                   ADVERTISE_SLCT);
4088
4089                 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4090
4091                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4092                         new_adv |= ADVERTISE_1000XHALF;
4093                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4094                         new_adv |= ADVERTISE_1000XFULL;
4095
4096                 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4097                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
4098                         bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4099                         tg3_writephy(tp, MII_BMCR, bmcr);
4100
4101                         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4102                         tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
4103                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4104
4105                         return err;
4106                 }
4107         } else {
4108                 u32 new_bmcr;
4109
4110                 bmcr &= ~BMCR_SPEED1000;
4111                 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4112
4113                 if (tp->link_config.duplex == DUPLEX_FULL)
4114                         new_bmcr |= BMCR_FULLDPLX;
4115
4116                 if (new_bmcr != bmcr) {
4117                         /* BMCR_SPEED1000 is a reserved bit that needs
4118                          * to be set on write.
4119                          */
4120                         new_bmcr |= BMCR_SPEED1000;
4121
4122                         /* Force a linkdown */
4123                         if (netif_carrier_ok(tp->dev)) {
4124                                 u32 adv;
4125
4126                                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4127                                 adv &= ~(ADVERTISE_1000XFULL |
4128                                          ADVERTISE_1000XHALF |
4129                                          ADVERTISE_SLCT);
4130                                 tg3_writephy(tp, MII_ADVERTISE, adv);
4131                                 tg3_writephy(tp, MII_BMCR, bmcr |
4132                                                            BMCR_ANRESTART |
4133                                                            BMCR_ANENABLE);
4134                                 udelay(10);
4135                                 netif_carrier_off(tp->dev);
4136                         }
4137                         tg3_writephy(tp, MII_BMCR, new_bmcr);
4138                         bmcr = new_bmcr;
4139                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4140                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4141                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4142                             ASIC_REV_5714) {
4143                                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4144                                         bmsr |= BMSR_LSTATUS;
4145                                 else
4146                                         bmsr &= ~BMSR_LSTATUS;
4147                         }
4148                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4149                 }
4150         }
4151
4152         if (bmsr & BMSR_LSTATUS) {
4153                 current_speed = SPEED_1000;
4154                 current_link_up = 1;
4155                 if (bmcr & BMCR_FULLDPLX)
4156                         current_duplex = DUPLEX_FULL;
4157                 else
4158                         current_duplex = DUPLEX_HALF;
4159
4160                 local_adv = 0;
4161                 remote_adv = 0;
4162
4163                 if (bmcr & BMCR_ANENABLE) {
4164                         u32 common;
4165
4166                         err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4167                         err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4168                         common = local_adv & remote_adv;
4169                         if (common & (ADVERTISE_1000XHALF |
4170                                       ADVERTISE_1000XFULL)) {
4171                                 if (common & ADVERTISE_1000XFULL)
4172                                         current_duplex = DUPLEX_FULL;
4173                                 else
4174                                         current_duplex = DUPLEX_HALF;
4175                         }
4176                         else
4177                                 current_link_up = 0;
4178                 }
4179         }
4180
4181         if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4182                 tg3_setup_flow_control(tp, local_adv, remote_adv);
4183
4184         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4185         if (tp->link_config.active_duplex == DUPLEX_HALF)
4186                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4187
4188         tw32_f(MAC_MODE, tp->mac_mode);
4189         udelay(40);
4190
4191         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4192
4193         tp->link_config.active_speed = current_speed;
4194         tp->link_config.active_duplex = current_duplex;
4195
4196         if (current_link_up != netif_carrier_ok(tp->dev)) {
4197                 if (current_link_up)
4198                         netif_carrier_on(tp->dev);
4199                 else {
4200                         netif_carrier_off(tp->dev);
4201                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4202                 }
4203                 tg3_link_report(tp);
4204         }
4205         return err;
4206 }
4207
4208 static void tg3_serdes_parallel_detect(struct tg3 *tp)
4209 {
4210         if (tp->serdes_counter) {
4211                 /* Give autoneg time to complete. */
4212                 tp->serdes_counter--;
4213                 return;
4214         }
4215         if (!netif_carrier_ok(tp->dev) &&
4216             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4217                 u32 bmcr;
4218
4219                 tg3_readphy(tp, MII_BMCR, &bmcr);
4220                 if (bmcr & BMCR_ANENABLE) {
4221                         u32 phy1, phy2;
4222
4223                         /* Select shadow register 0x1f */
4224                         tg3_writephy(tp, 0x1c, 0x7c00);
4225                         tg3_readphy(tp, 0x1c, &phy1);
4226
4227                         /* Select expansion interrupt status register */
4228                         tg3_writephy(tp, 0x17, 0x0f01);
4229                         tg3_readphy(tp, 0x15, &phy2);
4230                         tg3_readphy(tp, 0x15, &phy2);
4231
4232                         if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4233                                 /* We have signal detect and not receiving
4234                                  * config code words, link is up by parallel
4235                                  * detection.
4236                                  */
4237
4238                                 bmcr &= ~BMCR_ANENABLE;
4239                                 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4240                                 tg3_writephy(tp, MII_BMCR, bmcr);
4241                                 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
4242                         }
4243                 }
4244         }
4245         else if (netif_carrier_ok(tp->dev) &&
4246                  (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4247                  (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4248                 u32 phy2;
4249
4250                 /* Select expansion interrupt status register */
4251                 tg3_writephy(tp, 0x17, 0x0f01);
4252                 tg3_readphy(tp, 0x15, &phy2);
4253                 if (phy2 & 0x20) {
4254                         u32 bmcr;
4255
4256                         /* Config code words received, turn on autoneg. */
4257                         tg3_readphy(tp, MII_BMCR, &bmcr);
4258                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4259
4260                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4261
4262                 }
4263         }
4264 }
4265
4266 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4267 {
4268         int err;
4269
4270         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
4271                 err = tg3_setup_fiber_phy(tp, force_reset);
4272         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
4273                 err = tg3_setup_fiber_mii_phy(tp, force_reset);
4274         } else {
4275                 err = tg3_setup_copper_phy(tp, force_reset);
4276         }
4277
4278         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
4279                 u32 val, scale;
4280
4281                 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4282                 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4283                         scale = 65;
4284                 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4285                         scale = 6;
4286                 else
4287                         scale = 12;
4288
4289                 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4290                 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4291                 tw32(GRC_MISC_CFG, val);
4292         }
4293
4294         if (tp->link_config.active_speed == SPEED_1000 &&
4295             tp->link_config.active_duplex == DUPLEX_HALF)
4296                 tw32(MAC_TX_LENGTHS,
4297                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4298                       (6 << TX_LENGTHS_IPG_SHIFT) |
4299                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
4300         else
4301                 tw32(MAC_TX_LENGTHS,
4302                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4303                       (6 << TX_LENGTHS_IPG_SHIFT) |
4304                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
4305
4306         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4307                 if (netif_carrier_ok(tp->dev)) {
4308                         tw32(HOSTCC_STAT_COAL_TICKS,
4309                              tp->coal.stats_block_coalesce_usecs);
4310                 } else {
4311                         tw32(HOSTCC_STAT_COAL_TICKS, 0);
4312                 }
4313         }
4314
4315         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4316                 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
4317                 if (!netif_carrier_ok(tp->dev))
4318                         val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4319                               tp->pwrmgmt_thresh;
4320                 else
4321                         val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4322                 tw32(PCIE_PWR_MGMT_THRESH, val);
4323         }
4324
4325         return err;
4326 }
4327
4328 /* This is called whenever we suspect that the system chipset is re-
4329  * ordering the sequence of MMIO to the tx send mailbox. The symptom
4330  * is bogus tx completions. We try to recover by setting the
4331  * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4332  * in the workqueue.
4333  */
4334 static void tg3_tx_recover(struct tg3 *tp)
4335 {
4336         BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4337                tp->write32_tx_mbox == tg3_write_indirect_mbox);
4338
4339         printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
4340                "mapped I/O cycles to the network device, attempting to "
4341                "recover. Please report the problem to the driver maintainer "
4342                "and include system chipset information.\n", tp->dev->name);
4343
4344         spin_lock(&tp->lock);
4345         tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
4346         spin_unlock(&tp->lock);
4347 }
4348
4349 static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
4350 {
4351         smp_mb();
4352         return tnapi->tx_pending -
4353                ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
4354 }
4355
4356 /* Tigon3 never reports partial packet sends.  So we do not
4357  * need special logic to handle SKBs that have not had all
4358  * of their frags sent yet, like SunGEM does.
4359  */
4360 static void tg3_tx(struct tg3_napi *tnapi)
4361 {
4362         struct tg3 *tp = tnapi->tp;
4363         u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
4364         u32 sw_idx = tnapi->tx_cons;
4365         struct netdev_queue *txq;
4366         int index = tnapi - tp->napi;
4367
4368         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
4369                 index--;
4370
4371         txq = netdev_get_tx_queue(tp->dev, index);
4372
4373         while (sw_idx != hw_idx) {
4374                 struct ring_info *ri = &tnapi->tx_buffers[sw_idx];
4375                 struct sk_buff *skb = ri->skb;
4376                 int i, tx_bug = 0;
4377
4378                 if (unlikely(skb == NULL)) {
4379                         tg3_tx_recover(tp);
4380                         return;
4381                 }
4382
4383                 pci_unmap_single(tp->pdev,
4384                                  pci_unmap_addr(ri, mapping),
4385                                  skb_headlen(skb),
4386                                  PCI_DMA_TODEVICE);
4387
4388                 ri->skb = NULL;
4389
4390                 sw_idx = NEXT_TX(sw_idx);
4391
4392                 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
4393                         ri = &tnapi->tx_buffers[sw_idx];
4394                         if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4395                                 tx_bug = 1;
4396
4397                         pci_unmap_page(tp->pdev,
4398                                        pci_unmap_addr(ri, mapping),
4399                                        skb_shinfo(skb)->frags[i].size,
4400                                        PCI_DMA_TODEVICE);
4401                         sw_idx = NEXT_TX(sw_idx);
4402                 }
4403
4404                 dev_kfree_skb(skb);
4405
4406                 if (unlikely(tx_bug)) {
4407                         tg3_tx_recover(tp);
4408                         return;
4409                 }
4410         }
4411
4412         tnapi->tx_cons = sw_idx;
4413
4414         /* Need to make the tx_cons update visible to tg3_start_xmit()
4415          * before checking for netif_queue_stopped().  Without the
4416          * memory barrier, there is a small possibility that tg3_start_xmit()
4417          * will miss it and cause the queue to be stopped forever.
4418          */
4419         smp_mb();
4420
4421         if (unlikely(netif_tx_queue_stopped(txq) &&
4422                      (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
4423                 __netif_tx_lock(txq, smp_processor_id());
4424                 if (netif_tx_queue_stopped(txq) &&
4425                     (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
4426                         netif_tx_wake_queue(txq);
4427                 __netif_tx_unlock(txq);
4428         }
4429 }
4430
4431 static void tg3_rx_skb_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
4432 {
4433         if (!ri->skb)
4434                 return;
4435
4436         pci_unmap_single(tp->pdev, pci_unmap_addr(ri, mapping),
4437                          map_sz, PCI_DMA_FROMDEVICE);
4438         dev_kfree_skb_any(ri->skb);
4439         ri->skb = NULL;
4440 }
4441
4442 /* Returns size of skb allocated or < 0 on error.
4443  *
4444  * We only need to fill in the address because the other members
4445  * of the RX descriptor are invariant, see tg3_init_rings.
4446  *
4447  * Note the purposeful assymetry of cpu vs. chip accesses.  For
4448  * posting buffers we only dirty the first cache line of the RX
4449  * descriptor (containing the address).  Whereas for the RX status
4450  * buffers the cpu only reads the last cacheline of the RX descriptor
4451  * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4452  */
4453 static int tg3_alloc_rx_skb(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
4454                             u32 opaque_key, u32 dest_idx_unmasked)
4455 {
4456         struct tg3_rx_buffer_desc *desc;
4457         struct ring_info *map, *src_map;
4458         struct sk_buff *skb;
4459         dma_addr_t mapping;
4460         int skb_size, dest_idx;
4461
4462         src_map = NULL;
4463         switch (opaque_key) {
4464         case RXD_OPAQUE_RING_STD:
4465                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4466                 desc = &tpr->rx_std[dest_idx];
4467                 map = &tpr->rx_std_buffers[dest_idx];
4468                 skb_size = tp->rx_pkt_map_sz;
4469                 break;
4470
4471         case RXD_OPAQUE_RING_JUMBO:
4472                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4473                 desc = &tpr->rx_jmb[dest_idx].std;
4474                 map = &tpr->rx_jmb_buffers[dest_idx];
4475                 skb_size = TG3_RX_JMB_MAP_SZ;
4476                 break;
4477
4478         default:
4479                 return -EINVAL;
4480         }
4481
4482         /* Do not overwrite any of the map or rp information
4483          * until we are sure we can commit to a new buffer.
4484          *
4485          * Callers depend upon this behavior and assume that
4486          * we leave everything unchanged if we fail.
4487          */
4488         skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset);
4489         if (skb == NULL)
4490                 return -ENOMEM;
4491
4492         skb_reserve(skb, tp->rx_offset);
4493
4494         mapping = pci_map_single(tp->pdev, skb->data, skb_size,
4495                                  PCI_DMA_FROMDEVICE);
4496         if (pci_dma_mapping_error(tp->pdev, mapping)) {
4497                 dev_kfree_skb(skb);
4498                 return -EIO;
4499         }
4500
4501         map->skb = skb;
4502         pci_unmap_addr_set(map, mapping, mapping);
4503
4504         desc->addr_hi = ((u64)mapping >> 32);
4505         desc->addr_lo = ((u64)mapping & 0xffffffff);
4506
4507         return skb_size;
4508 }
4509
4510 /* We only need to move over in the address because the other
4511  * members of the RX descriptor are invariant.  See notes above
4512  * tg3_alloc_rx_skb for full details.
4513  */
4514 static void tg3_recycle_rx(struct tg3_napi *tnapi,
4515                            struct tg3_rx_prodring_set *dpr,
4516                            u32 opaque_key, int src_idx,
4517                            u32 dest_idx_unmasked)
4518 {
4519         struct tg3 *tp = tnapi->tp;
4520         struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4521         struct ring_info *src_map, *dest_map;
4522         int dest_idx;
4523         struct tg3_rx_prodring_set *spr = &tp->prodring[0];
4524
4525         switch (opaque_key) {
4526         case RXD_OPAQUE_RING_STD:
4527                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4528                 dest_desc = &dpr->rx_std[dest_idx];
4529                 dest_map = &dpr->rx_std_buffers[dest_idx];
4530                 src_desc = &spr->rx_std[src_idx];
4531                 src_map = &spr->rx_std_buffers[src_idx];
4532                 break;
4533
4534         case RXD_OPAQUE_RING_JUMBO:
4535                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4536                 dest_desc = &dpr->rx_jmb[dest_idx].std;
4537                 dest_map = &dpr->rx_jmb_buffers[dest_idx];
4538                 src_desc = &spr->rx_jmb[src_idx].std;
4539                 src_map = &spr->rx_jmb_buffers[src_idx];
4540                 break;
4541
4542         default:
4543                 return;
4544         }
4545
4546         dest_map->skb = src_map->skb;
4547         pci_unmap_addr_set(dest_map, mapping,
4548                            pci_unmap_addr(src_map, mapping));
4549         dest_desc->addr_hi = src_desc->addr_hi;
4550         dest_desc->addr_lo = src_desc->addr_lo;
4551         src_map->skb = NULL;
4552 }
4553
4554 /* The RX ring scheme is composed of multiple rings which post fresh
4555  * buffers to the chip, and one special ring the chip uses to report
4556  * status back to the host.
4557  *
4558  * The special ring reports the status of received packets to the
4559  * host.  The chip does not write into the original descriptor the
4560  * RX buffer was obtained from.  The chip simply takes the original
4561  * descriptor as provided by the host, updates the status and length
4562  * field, then writes this into the next status ring entry.
4563  *
4564  * Each ring the host uses to post buffers to the chip is described
4565  * by a TG3_BDINFO entry in the chips SRAM area.  When a packet arrives,
4566  * it is first placed into the on-chip ram.  When the packet's length
4567  * is known, it walks down the TG3_BDINFO entries to select the ring.
4568  * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4569  * which is within the range of the new packet's length is chosen.
4570  *
4571  * The "separate ring for rx status" scheme may sound queer, but it makes
4572  * sense from a cache coherency perspective.  If only the host writes
4573  * to the buffer post rings, and only the chip writes to the rx status
4574  * rings, then cache lines never move beyond shared-modified state.
4575  * If both the host and chip were to write into the same ring, cache line
4576  * eviction could occur since both entities want it in an exclusive state.
4577  */
4578 static int tg3_rx(struct tg3_napi *tnapi, int budget)
4579 {
4580         struct tg3 *tp = tnapi->tp;
4581         u32 work_mask, rx_std_posted = 0;
4582         u32 std_prod_idx, jmb_prod_idx;
4583         u32 sw_idx = tnapi->rx_rcb_ptr;
4584         u16 hw_idx;
4585         int received;
4586         struct tg3_rx_prodring_set *tpr = tnapi->prodring;
4587
4588         hw_idx = *(tnapi->rx_rcb_prod_idx);
4589         /*
4590          * We need to order the read of hw_idx and the read of
4591          * the opaque cookie.
4592          */
4593         rmb();
4594         work_mask = 0;
4595         received = 0;
4596         std_prod_idx = tpr->rx_std_prod_idx;
4597         jmb_prod_idx = tpr->rx_jmb_prod_idx;
4598         while (sw_idx != hw_idx && budget > 0) {
4599                 struct ring_info *ri;
4600                 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
4601                 unsigned int len;
4602                 struct sk_buff *skb;
4603                 dma_addr_t dma_addr;
4604                 u32 opaque_key, desc_idx, *post_ptr;
4605
4606                 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4607                 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4608                 if (opaque_key == RXD_OPAQUE_RING_STD) {
4609                         ri = &tp->prodring[0].rx_std_buffers[desc_idx];
4610                         dma_addr = pci_unmap_addr(ri, mapping);
4611                         skb = ri->skb;
4612                         post_ptr = &std_prod_idx;
4613                         rx_std_posted++;
4614                 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
4615                         ri = &tp->prodring[0].rx_jmb_buffers[desc_idx];
4616                         dma_addr = pci_unmap_addr(ri, mapping);
4617                         skb = ri->skb;
4618                         post_ptr = &jmb_prod_idx;
4619                 } else
4620                         goto next_pkt_nopost;
4621
4622                 work_mask |= opaque_key;
4623
4624                 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4625                     (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4626                 drop_it:
4627                         tg3_recycle_rx(tnapi, tpr, opaque_key,
4628                                        desc_idx, *post_ptr);
4629                 drop_it_no_recycle:
4630                         /* Other statistics kept track of by card. */
4631                         tp->net_stats.rx_dropped++;
4632                         goto next_pkt;
4633                 }
4634
4635                 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4636                       ETH_FCS_LEN;
4637
4638                 if (len > RX_COPY_THRESHOLD &&
4639                     tp->rx_offset == NET_IP_ALIGN) {
4640                     /* rx_offset will likely not equal NET_IP_ALIGN
4641                      * if this is a 5701 card running in PCI-X mode
4642                      * [see tg3_get_invariants()]
4643                      */
4644                         int skb_size;
4645
4646                         skb_size = tg3_alloc_rx_skb(tp, tpr, opaque_key,
4647                                                     *post_ptr);
4648                         if (skb_size < 0)
4649                                 goto drop_it;
4650
4651                         ri->skb = NULL;
4652
4653                         pci_unmap_single(tp->pdev, dma_addr, skb_size,
4654                                          PCI_DMA_FROMDEVICE);
4655
4656                         skb_put(skb, len);
4657                 } else {
4658                         struct sk_buff *copy_skb;
4659
4660                         tg3_recycle_rx(tnapi, tpr, opaque_key,
4661                                        desc_idx, *post_ptr);
4662
4663                         copy_skb = netdev_alloc_skb(tp->dev,
4664                                                     len + TG3_RAW_IP_ALIGN);
4665                         if (copy_skb == NULL)
4666                                 goto drop_it_no_recycle;
4667
4668                         skb_reserve(copy_skb, TG3_RAW_IP_ALIGN);
4669                         skb_put(copy_skb, len);
4670                         pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4671                         skb_copy_from_linear_data(skb, copy_skb->data, len);
4672                         pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4673
4674                         /* We'll reuse the original ring buffer. */
4675                         skb = copy_skb;
4676                 }
4677
4678                 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4679                     (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4680                     (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4681                       >> RXD_TCPCSUM_SHIFT) == 0xffff))
4682                         skb->ip_summed = CHECKSUM_UNNECESSARY;
4683                 else
4684                         skb->ip_summed = CHECKSUM_NONE;
4685
4686                 skb->protocol = eth_type_trans(skb, tp->dev);
4687
4688                 if (len > (tp->dev->mtu + ETH_HLEN) &&
4689                     skb->protocol != htons(ETH_P_8021Q)) {
4690                         dev_kfree_skb(skb);
4691                         goto next_pkt;
4692                 }
4693
4694 #if TG3_VLAN_TAG_USED
4695                 if (tp->vlgrp != NULL &&
4696                     desc->type_flags & RXD_FLAG_VLAN) {
4697                         vlan_gro_receive(&tnapi->napi, tp->vlgrp,
4698                                          desc->err_vlan & RXD_VLAN_MASK, skb);
4699                 } else
4700 #endif
4701                         napi_gro_receive(&tnapi->napi, skb);
4702
4703                 received++;
4704                 budget--;
4705
4706 next_pkt:
4707                 (*post_ptr)++;
4708
4709                 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4710                         u32 idx = *post_ptr % TG3_RX_RING_SIZE;
4711                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, idx);
4712                         work_mask &= ~RXD_OPAQUE_RING_STD;
4713                         rx_std_posted = 0;
4714                 }
4715 next_pkt_nopost:
4716                 sw_idx++;
4717                 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
4718
4719                 /* Refresh hw_idx to see if there is new work */
4720                 if (sw_idx == hw_idx) {
4721                         hw_idx = *(tnapi->rx_rcb_prod_idx);
4722                         rmb();
4723                 }
4724         }
4725
4726         /* ACK the status ring. */
4727         tnapi->rx_rcb_ptr = sw_idx;
4728         tw32_rx_mbox(tnapi->consmbox, sw_idx);
4729
4730         /* Refill RX ring(s). */
4731         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) || tnapi == &tp->napi[1]) {
4732                 if (work_mask & RXD_OPAQUE_RING_STD) {
4733                         tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4734                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4735                                      tpr->rx_std_prod_idx);
4736                 }
4737                 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4738                         tpr->rx_jmb_prod_idx = jmb_prod_idx %
4739                                                TG3_RX_JUMBO_RING_SIZE;
4740                         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
4741                                      tpr->rx_jmb_prod_idx);
4742                 }
4743                 mmiowb();
4744         } else if (work_mask) {
4745                 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
4746                  * updated before the producer indices can be updated.
4747                  */
4748                 smp_wmb();
4749
4750                 tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4751                 tpr->rx_jmb_prod_idx = jmb_prod_idx % TG3_RX_JUMBO_RING_SIZE;
4752
4753                 napi_schedule(&tp->napi[1].napi);
4754         }
4755
4756         return received;
4757 }
4758
4759 static void tg3_poll_link(struct tg3 *tp)
4760 {
4761         /* handle link change and other phy events */
4762         if (!(tp->tg3_flags &
4763               (TG3_FLAG_USE_LINKCHG_REG |
4764                TG3_FLAG_POLL_SERDES))) {
4765                 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
4766
4767                 if (sblk->status & SD_STATUS_LINK_CHG) {
4768                         sblk->status = SD_STATUS_UPDATED |
4769                                        (sblk->status & ~SD_STATUS_LINK_CHG);
4770                         spin_lock(&tp->lock);
4771                         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4772                                 tw32_f(MAC_STATUS,
4773                                      (MAC_STATUS_SYNC_CHANGED |
4774                                       MAC_STATUS_CFG_CHANGED |
4775                                       MAC_STATUS_MI_COMPLETION |
4776                                       MAC_STATUS_LNKSTATE_CHANGED));
4777                                 udelay(40);
4778                         } else
4779                                 tg3_setup_phy(tp, 0);
4780                         spin_unlock(&tp->lock);
4781                 }
4782         }
4783 }
4784
4785 static void tg3_rx_prodring_xfer(struct tg3 *tp,
4786                                  struct tg3_rx_prodring_set *dpr,
4787                                  struct tg3_rx_prodring_set *spr)
4788 {
4789         u32 si, di, cpycnt, src_prod_idx;
4790         int i;
4791
4792         while (1) {
4793                 src_prod_idx = spr->rx_std_prod_idx;
4794
4795                 /* Make sure updates to the rx_std_buffers[] entries and the
4796                  * standard producer index are seen in the correct order.
4797                  */
4798                 smp_rmb();
4799
4800                 if (spr->rx_std_cons_idx == src_prod_idx)
4801                         break;
4802
4803                 if (spr->rx_std_cons_idx < src_prod_idx)
4804                         cpycnt = src_prod_idx - spr->rx_std_cons_idx;
4805                 else
4806                         cpycnt = TG3_RX_RING_SIZE - spr->rx_std_cons_idx;
4807
4808                 cpycnt = min(cpycnt, TG3_RX_RING_SIZE - dpr->rx_std_prod_idx);
4809
4810                 si = spr->rx_std_cons_idx;
4811                 di = dpr->rx_std_prod_idx;
4812
4813                 memcpy(&dpr->rx_std_buffers[di],
4814                        &spr->rx_std_buffers[si],
4815                        cpycnt * sizeof(struct ring_info));
4816
4817                 for (i = 0; i < cpycnt; i++, di++, si++) {
4818                         struct tg3_rx_buffer_desc *sbd, *dbd;
4819                         sbd = &spr->rx_std[si];
4820                         dbd = &dpr->rx_std[di];
4821                         dbd->addr_hi = sbd->addr_hi;
4822                         dbd->addr_lo = sbd->addr_lo;
4823                 }
4824
4825                 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) %
4826                                        TG3_RX_RING_SIZE;
4827                 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) %
4828                                        TG3_RX_RING_SIZE;
4829         }
4830
4831         while (1) {
4832                 src_prod_idx = spr->rx_jmb_prod_idx;
4833
4834                 /* Make sure updates to the rx_jmb_buffers[] entries and
4835                  * the jumbo producer index are seen in the correct order.
4836                  */
4837                 smp_rmb();
4838
4839                 if (spr->rx_jmb_cons_idx == src_prod_idx)
4840                         break;
4841
4842                 if (spr->rx_jmb_cons_idx < src_prod_idx)
4843                         cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
4844                 else
4845                         cpycnt = TG3_RX_JUMBO_RING_SIZE - spr->rx_jmb_cons_idx;
4846
4847                 cpycnt = min(cpycnt,
4848                              TG3_RX_JUMBO_RING_SIZE - dpr->rx_jmb_prod_idx);
4849
4850                 si = spr->rx_jmb_cons_idx;
4851                 di = dpr->rx_jmb_prod_idx;
4852
4853                 memcpy(&dpr->rx_jmb_buffers[di],
4854                        &spr->rx_jmb_buffers[si],
4855                        cpycnt * sizeof(struct ring_info));
4856
4857                 for (i = 0; i < cpycnt; i++, di++, si++) {
4858                         struct tg3_rx_buffer_desc *sbd, *dbd;
4859                         sbd = &spr->rx_jmb[si].std;
4860                         dbd = &dpr->rx_jmb[di].std;
4861                         dbd->addr_hi = sbd->addr_hi;
4862                         dbd->addr_lo = sbd->addr_lo;
4863                 }
4864
4865                 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) %
4866                                        TG3_RX_JUMBO_RING_SIZE;
4867                 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) %
4868                                        TG3_RX_JUMBO_RING_SIZE;
4869         }
4870 }
4871
4872 static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
4873 {
4874         struct tg3 *tp = tnapi->tp;
4875
4876         /* run TX completion thread */
4877         if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
4878                 tg3_tx(tnapi);
4879                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4880                         return work_done;
4881         }
4882
4883         /* run RX thread, within the bounds set by NAPI.
4884          * All RX "locking" is done by ensuring outside
4885          * code synchronizes with tg3->napi.poll()
4886          */
4887         if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
4888                 work_done += tg3_rx(tnapi, budget - work_done);
4889
4890         if ((tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) && tnapi == &tp->napi[1]) {
4891                 int i;
4892                 u32 std_prod_idx = tp->prodring[0].rx_std_prod_idx;
4893                 u32 jmb_prod_idx = tp->prodring[0].rx_jmb_prod_idx;
4894
4895                 for (i = 2; i < tp->irq_cnt; i++)
4896                         tg3_rx_prodring_xfer(tp, tnapi->prodring,
4897                                              tp->napi[i].prodring);
4898
4899                 wmb();
4900
4901                 if (std_prod_idx != tp->prodring[0].rx_std_prod_idx) {
4902                         u32 mbox = TG3_RX_STD_PROD_IDX_REG;
4903                         tw32_rx_mbox(mbox, tp->prodring[0].rx_std_prod_idx);
4904                 }
4905
4906                 if (jmb_prod_idx != tp->prodring[0].rx_jmb_prod_idx) {
4907                         u32 mbox = TG3_RX_JMB_PROD_IDX_REG;
4908                         tw32_rx_mbox(mbox, tp->prodring[0].rx_jmb_prod_idx);
4909                 }
4910
4911                 mmiowb();
4912         }
4913
4914         return work_done;
4915 }
4916
4917 static int tg3_poll_msix(struct napi_struct *napi, int budget)
4918 {
4919         struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
4920         struct tg3 *tp = tnapi->tp;
4921         int work_done = 0;
4922         struct tg3_hw_status *sblk = tnapi->hw_status;
4923
4924         while (1) {
4925                 work_done = tg3_poll_work(tnapi, work_done, budget);
4926
4927                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4928                         goto tx_recovery;
4929
4930                 if (unlikely(work_done >= budget))
4931                         break;
4932
4933                 /* tp->last_tag is used in tg3_restart_ints() below
4934                  * to tell the hw how much work has been processed,
4935                  * so we must read it before checking for more work.
4936                  */
4937                 tnapi->last_tag = sblk->status_tag;
4938                 tnapi->last_irq_tag = tnapi->last_tag;
4939                 rmb();
4940
4941                 /* check for RX/TX work to do */
4942                 if (sblk->idx[0].tx_consumer == tnapi->tx_cons &&
4943                     *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr) {
4944                         napi_complete(napi);
4945                         /* Reenable interrupts. */
4946                         tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
4947                         mmiowb();
4948                         break;
4949                 }
4950         }
4951
4952         return work_done;
4953
4954 tx_recovery:
4955         /* work_done is guaranteed to be less than budget. */
4956         napi_complete(napi);
4957         schedule_work(&tp->reset_task);
4958         return work_done;
4959 }
4960
4961 static int tg3_poll(struct napi_struct *napi, int budget)
4962 {
4963         struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
4964         struct tg3 *tp = tnapi->tp;
4965         int work_done = 0;
4966         struct tg3_hw_status *sblk = tnapi->hw_status;
4967
4968         while (1) {
4969                 tg3_poll_link(tp);
4970
4971                 work_done = tg3_poll_work(tnapi, work_done, budget);
4972
4973                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4974                         goto tx_recovery;
4975
4976                 if (unlikely(work_done >= budget))
4977                         break;
4978
4979                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
4980                         /* tp->last_tag is used in tg3_int_reenable() below
4981                          * to tell the hw how much work has been processed,
4982                          * so we must read it before checking for more work.
4983                          */
4984                         tnapi->last_tag = sblk->status_tag;
4985                         tnapi->last_irq_tag = tnapi->last_tag;
4986                         rmb();
4987                 } else
4988                         sblk->status &= ~SD_STATUS_UPDATED;
4989
4990                 if (likely(!tg3_has_work(tnapi))) {
4991                         napi_complete(napi);
4992                         tg3_int_reenable(tnapi);
4993                         break;
4994                 }
4995         }
4996
4997         return work_done;
4998
4999 tx_recovery:
5000         /* work_done is guaranteed to be less than budget. */
5001         napi_complete(napi);
5002         schedule_work(&tp->reset_task);
5003         return work_done;
5004 }
5005
5006 static void tg3_irq_quiesce(struct tg3 *tp)
5007 {
5008         int i;
5009
5010         BUG_ON(tp->irq_sync);
5011
5012         tp->irq_sync = 1;
5013         smp_mb();
5014
5015         for (i = 0; i < tp->irq_cnt; i++)
5016                 synchronize_irq(tp->napi[i].irq_vec);
5017 }
5018
5019 static inline int tg3_irq_sync(struct tg3 *tp)
5020 {
5021         return tp->irq_sync;
5022 }
5023
5024 /* Fully shutdown all tg3 driver activity elsewhere in the system.
5025  * If irq_sync is non-zero, then the IRQ handler must be synchronized
5026  * with as well.  Most of the time, this is not necessary except when
5027  * shutting down the device.
5028  */
5029 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
5030 {
5031         spin_lock_bh(&tp->lock);
5032         if (irq_sync)
5033                 tg3_irq_quiesce(tp);
5034 }
5035
5036 static inline void tg3_full_unlock(struct tg3 *tp)
5037 {
5038         spin_unlock_bh(&tp->lock);
5039 }
5040
5041 /* One-shot MSI handler - Chip automatically disables interrupt
5042  * after sending MSI so driver doesn't have to do it.
5043  */
5044 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
5045 {
5046         struct tg3_napi *tnapi = dev_id;
5047         struct tg3 *tp = tnapi->tp;
5048
5049         prefetch(tnapi->hw_status);
5050         if (tnapi->rx_rcb)
5051                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5052
5053         if (likely(!tg3_irq_sync(tp)))
5054                 napi_schedule(&tnapi->napi);
5055
5056         return IRQ_HANDLED;
5057 }
5058
5059 /* MSI ISR - No need to check for interrupt sharing and no need to
5060  * flush status block and interrupt mailbox. PCI ordering rules
5061  * guarantee that MSI will arrive after the status block.
5062  */
5063 static irqreturn_t tg3_msi(int irq, void *dev_id)
5064 {
5065         struct tg3_napi *tnapi = dev_id;
5066         struct tg3 *tp = tnapi->tp;
5067
5068         prefetch(tnapi->hw_status);
5069         if (tnapi->rx_rcb)
5070                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5071         /*
5072          * Writing any value to intr-mbox-0 clears PCI INTA# and
5073          * chip-internal interrupt pending events.
5074          * Writing non-zero to intr-mbox-0 additional tells the
5075          * NIC to stop sending us irqs, engaging "in-intr-handler"
5076          * event coalescing.
5077          */
5078         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5079         if (likely(!tg3_irq_sync(tp)))
5080                 napi_schedule(&tnapi->napi);
5081
5082         return IRQ_RETVAL(1);
5083 }
5084
5085 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
5086 {
5087         struct tg3_napi *tnapi = dev_id;
5088         struct tg3 *tp = tnapi->tp;
5089         struct tg3_hw_status *sblk = tnapi->hw_status;
5090         unsigned int handled = 1;
5091
5092         /* In INTx mode, it is possible for the interrupt to arrive at
5093          * the CPU before the status block posted prior to the interrupt.
5094          * Reading the PCI State register will confirm whether the
5095          * interrupt is ours and will flush the status block.
5096          */
5097         if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
5098                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5099                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5100                         handled = 0;
5101                         goto out;
5102                 }
5103         }
5104
5105         /*
5106          * Writing any value to intr-mbox-0 clears PCI INTA# and
5107          * chip-internal interrupt pending events.
5108          * Writing non-zero to intr-mbox-0 additional tells the
5109          * NIC to stop sending us irqs, engaging "in-intr-handler"
5110          * event coalescing.
5111          *
5112          * Flush the mailbox to de-assert the IRQ immediately to prevent
5113          * spurious interrupts.  The flush impacts performance but
5114          * excessive spurious interrupts can be worse in some cases.
5115          */
5116         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5117         if (tg3_irq_sync(tp))
5118                 goto out;
5119         sblk->status &= ~SD_STATUS_UPDATED;
5120         if (likely(tg3_has_work(tnapi))) {
5121                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5122                 napi_schedule(&tnapi->napi);
5123         } else {
5124                 /* No work, shared interrupt perhaps?  re-enable
5125                  * interrupts, and flush that PCI write
5126                  */
5127                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
5128                                0x00000000);
5129         }
5130 out:
5131         return IRQ_RETVAL(handled);
5132 }
5133
5134 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
5135 {
5136         struct tg3_napi *tnapi = dev_id;
5137         struct tg3 *tp = tnapi->tp;
5138         struct tg3_hw_status *sblk = tnapi->hw_status;
5139         unsigned int handled = 1;
5140
5141         /* In INTx mode, it is possible for the interrupt to arrive at
5142          * the CPU before the status block posted prior to the interrupt.
5143          * Reading the PCI State register will confirm whether the
5144          * interrupt is ours and will flush the status block.
5145          */
5146         if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
5147                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5148                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5149                         handled = 0;
5150                         goto out;
5151                 }
5152         }
5153
5154         /*
5155          * writing any value to intr-mbox-0 clears PCI INTA# and
5156          * chip-internal interrupt pending events.
5157          * writing non-zero to intr-mbox-0 additional tells the
5158          * NIC to stop sending us irqs, engaging "in-intr-handler"
5159          * event coalescing.
5160          *
5161          * Flush the mailbox to de-assert the IRQ immediately to prevent
5162          * spurious interrupts.  The flush impacts performance but
5163          * excessive spurious interrupts can be worse in some cases.
5164          */
5165         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5166
5167         /*
5168          * In a shared interrupt configuration, sometimes other devices'
5169          * interrupts will scream.  We record the current status tag here
5170          * so that the above check can report that the screaming interrupts
5171          * are unhandled.  Eventually they will be silenced.
5172          */
5173         tnapi->last_irq_tag = sblk->status_tag;
5174
5175         if (tg3_irq_sync(tp))
5176                 goto out;
5177
5178         prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5179
5180         napi_schedule(&tnapi->napi);
5181
5182 out:
5183         return IRQ_RETVAL(handled);
5184 }
5185
5186 /* ISR for interrupt test */
5187 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
5188 {
5189         struct tg3_napi *tnapi = dev_id;
5190         struct tg3 *tp = tnapi->tp;
5191         struct tg3_hw_status *sblk = tnapi->hw_status;
5192
5193         if ((sblk->status & SD_STATUS_UPDATED) ||
5194             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5195                 tg3_disable_ints(tp);
5196                 return IRQ_RETVAL(1);
5197         }
5198         return IRQ_RETVAL(0);
5199 }
5200
5201 static int tg3_init_hw(struct tg3 *, int);
5202 static int tg3_halt(struct tg3 *, int, int);
5203
5204 /* Restart hardware after configuration changes, self-test, etc.
5205  * Invoked with tp->lock held.
5206  */
5207 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
5208         __releases(tp->lock)
5209         __acquires(tp->lock)
5210 {
5211         int err;
5212
5213         err = tg3_init_hw(tp, reset_phy);
5214         if (err) {
5215                 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
5216                        "aborting.\n", tp->dev->name);
5217                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5218                 tg3_full_unlock(tp);
5219                 del_timer_sync(&tp->timer);
5220                 tp->irq_sync = 0;
5221                 tg3_napi_enable(tp);
5222                 dev_close(tp->dev);
5223                 tg3_full_lock(tp, 0);
5224         }
5225         return err;
5226 }
5227
5228 #ifdef CONFIG_NET_POLL_CONTROLLER
5229 static void tg3_poll_controller(struct net_device *dev)
5230 {
5231         int i;
5232         struct tg3 *tp = netdev_priv(dev);
5233
5234         for (i = 0; i < tp->irq_cnt; i++)
5235                 tg3_interrupt(tp->napi[i].irq_vec, dev);
5236 }
5237 #endif
5238
5239 static void tg3_reset_task(struct work_struct *work)
5240 {
5241         struct tg3 *tp = container_of(work, struct tg3, reset_task);
5242         int err;
5243         unsigned int restart_timer;
5244
5245         tg3_full_lock(tp, 0);
5246
5247         if (!netif_running(tp->dev)) {
5248                 tg3_full_unlock(tp);
5249                 return;
5250         }
5251
5252         tg3_full_unlock(tp);
5253
5254         tg3_phy_stop(tp);
5255
5256         tg3_netif_stop(tp);
5257
5258         tg3_full_lock(tp, 1);
5259
5260         restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
5261         tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
5262
5263         if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
5264                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
5265                 tp->write32_rx_mbox = tg3_write_flush_reg32;
5266                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
5267                 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
5268         }
5269
5270         tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
5271         err = tg3_init_hw(tp, 1);
5272         if (err)
5273                 goto out;
5274
5275         tg3_netif_start(tp);
5276
5277         if (restart_timer)
5278                 mod_timer(&tp->timer, jiffies + 1);
5279
5280 out:
5281         tg3_full_unlock(tp);
5282
5283         if (!err)
5284                 tg3_phy_start(tp);
5285 }
5286
5287 static void tg3_dump_short_state(struct tg3 *tp)
5288 {
5289         printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
5290                tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
5291         printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
5292                tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
5293 }
5294
5295 static void tg3_tx_timeout(struct net_device *dev)
5296 {
5297         struct tg3 *tp = netdev_priv(dev);
5298
5299         if (netif_msg_tx_err(tp)) {
5300                 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
5301                        dev->name);
5302                 tg3_dump_short_state(tp);
5303         }
5304
5305         schedule_work(&tp->reset_task);
5306 }
5307
5308 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5309 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
5310 {
5311         u32 base = (u32) mapping & 0xffffffff;
5312
5313         return ((base > 0xffffdcc0) &&
5314                 (base + len + 8 < base));
5315 }
5316
5317 /* Test for DMA addresses > 40-bit */
5318 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
5319                                           int len)
5320 {
5321 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
5322         if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
5323                 return (((u64) mapping + len) > DMA_BIT_MASK(40));
5324         return 0;
5325 #else
5326         return 0;
5327 #endif
5328 }
5329
5330 static void tg3_set_txd(struct tg3_napi *, int, dma_addr_t, int, u32, u32);
5331
5332 /* Workaround 4GB and 40-bit hardware DMA bugs. */
5333 static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
5334                                        struct sk_buff *skb, u32 last_plus_one,
5335                                        u32 *start, u32 base_flags, u32 mss)
5336 {
5337         struct tg3 *tp = tnapi->tp;
5338         struct sk_buff *new_skb;
5339         dma_addr_t new_addr = 0;
5340         u32 entry = *start;
5341         int i, ret = 0;
5342
5343         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5344                 new_skb = skb_copy(skb, GFP_ATOMIC);
5345         else {
5346                 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5347
5348                 new_skb = skb_copy_expand(skb,
5349                                           skb_headroom(skb) + more_headroom,
5350                                           skb_tailroom(skb), GFP_ATOMIC);
5351         }
5352
5353         if (!new_skb) {
5354                 ret = -1;
5355         } else {
5356                 /* New SKB is guaranteed to be linear. */
5357                 entry = *start;
5358                 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
5359                                           PCI_DMA_TODEVICE);
5360                 /* Make sure the mapping succeeded */
5361                 if (pci_dma_mapping_error(tp->pdev, new_addr)) {
5362                         ret = -1;
5363                         dev_kfree_skb(new_skb);
5364                         new_skb = NULL;
5365
5366                 /* Make sure new skb does not cross any 4G boundaries.
5367                  * Drop the packet if it does.
5368                  */
5369                 } else if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5370                             tg3_4g_overflow_test(new_addr, new_skb->len)) {
5371                         pci_unmap_single(tp->pdev, new_addr, new_skb->len,
5372                                          PCI_DMA_TODEVICE);
5373                         ret = -1;
5374                         dev_kfree_skb(new_skb);
5375                         new_skb = NULL;
5376                 } else {
5377                         tg3_set_txd(tnapi, entry, new_addr, new_skb->len,
5378                                     base_flags, 1 | (mss << 1));
5379                         *start = NEXT_TX(entry);
5380                 }
5381         }
5382
5383         /* Now clean up the sw ring entries. */
5384         i = 0;
5385         while (entry != last_plus_one) {
5386                 int len;
5387
5388                 if (i == 0)
5389                         len = skb_headlen(skb);
5390                 else
5391                         len = skb_shinfo(skb)->frags[i-1].size;
5392
5393                 pci_unmap_single(tp->pdev,
5394                                  pci_unmap_addr(&tnapi->tx_buffers[entry],
5395                                                 mapping),
5396                                  len, PCI_DMA_TODEVICE);
5397                 if (i == 0) {
5398                         tnapi->tx_buffers[entry].skb = new_skb;
5399                         pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5400                                            new_addr);
5401                 } else {
5402                         tnapi->tx_buffers[entry].skb = NULL;
5403                 }
5404                 entry = NEXT_TX(entry);
5405                 i++;
5406         }
5407
5408         dev_kfree_skb(skb);
5409
5410         return ret;
5411 }
5412
5413 static void tg3_set_txd(struct tg3_napi *tnapi, int entry,
5414                         dma_addr_t mapping, int len, u32 flags,
5415                         u32 mss_and_is_end)
5416 {
5417         struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry];
5418         int is_end = (mss_and_is_end & 0x1);
5419         u32 mss = (mss_and_is_end >> 1);
5420         u32 vlan_tag = 0;
5421
5422         if (is_end)
5423                 flags |= TXD_FLAG_END;
5424         if (flags & TXD_FLAG_VLAN) {
5425                 vlan_tag = flags >> 16;
5426                 flags &= 0xffff;
5427         }
5428         vlan_tag |= (mss << TXD_MSS_SHIFT);
5429
5430         txd->addr_hi = ((u64) mapping >> 32);
5431         txd->addr_lo = ((u64) mapping & 0xffffffff);
5432         txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5433         txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5434 }
5435
5436 /* hard_start_xmit for devices that don't have any bugs and
5437  * support TG3_FLG2_HW_TSO_2 and TG3_FLG2_HW_TSO_3 only.
5438  */
5439 static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
5440                                   struct net_device *dev)
5441 {
5442         struct tg3 *tp = netdev_priv(dev);
5443         u32 len, entry, base_flags, mss;
5444         dma_addr_t mapping;
5445         struct tg3_napi *tnapi;
5446         struct netdev_queue *txq;
5447         unsigned int i, last;
5448
5449
5450         txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5451         tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5452         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
5453                 tnapi++;
5454
5455         /* We are running in BH disabled context with netif_tx_lock
5456          * and TX reclaim runs via tp->napi.poll inside of a software
5457          * interrupt.  Furthermore, IRQ processing runs lockless so we have
5458          * no IRQ context deadlocks to worry about either.  Rejoice!
5459          */
5460         if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5461                 if (!netif_tx_queue_stopped(txq)) {
5462                         netif_tx_stop_queue(txq);
5463
5464                         /* This is a hard error, log it. */
5465                         printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5466                                "queue awake!\n", dev->name);
5467                 }
5468                 return NETDEV_TX_BUSY;
5469         }
5470
5471         entry = tnapi->tx_prod;
5472         base_flags = 0;
5473         mss = 0;
5474         if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5475                 int tcp_opt_len, ip_tcp_len;
5476                 u32 hdrlen;
5477
5478                 if (skb_header_cloned(skb) &&
5479                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5480                         dev_kfree_skb(skb);
5481                         goto out_unlock;
5482                 }
5483
5484                 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
5485                         hdrlen = skb_headlen(skb) - ETH_HLEN;
5486                 else {
5487                         struct iphdr *iph = ip_hdr(skb);
5488
5489                         tcp_opt_len = tcp_optlen(skb);
5490                         ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5491
5492                         iph->check = 0;
5493                         iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
5494                         hdrlen = ip_tcp_len + tcp_opt_len;
5495                 }
5496
5497                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5498                         mss |= (hdrlen & 0xc) << 12;
5499                         if (hdrlen & 0x10)
5500                                 base_flags |= 0x00000010;
5501                         base_flags |= (hdrlen & 0x3e0) << 5;
5502                 } else
5503                         mss |= hdrlen << 9;
5504
5505                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5506                                TXD_FLAG_CPU_POST_DMA);
5507
5508                 tcp_hdr(skb)->check = 0;
5509
5510         }
5511         else if (skb->ip_summed == CHECKSUM_PARTIAL)
5512                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5513 #if TG3_VLAN_TAG_USED
5514         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5515                 base_flags |= (TXD_FLAG_VLAN |
5516                                (vlan_tx_tag_get(skb) << 16));
5517 #endif
5518
5519         len = skb_headlen(skb);
5520
5521         /* Queue skb data, a.k.a. the main skb fragment. */
5522         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5523         if (pci_dma_mapping_error(tp->pdev, mapping)) {
5524                 dev_kfree_skb(skb);
5525                 goto out_unlock;
5526         }
5527
5528         tnapi->tx_buffers[entry].skb = skb;
5529         pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
5530
5531         if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
5532             !mss && skb->len > ETH_DATA_LEN)
5533                 base_flags |= TXD_FLAG_JMB_PKT;
5534
5535         tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5536                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5537
5538         entry = NEXT_TX(entry);
5539
5540         /* Now loop through additional data fragments, and queue them. */
5541         if (skb_shinfo(skb)->nr_frags > 0) {
5542                 last = skb_shinfo(skb)->nr_frags - 1;
5543                 for (i = 0; i <= last; i++) {
5544                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5545
5546                         len = frag->size;
5547                         mapping = pci_map_page(tp->pdev,
5548                                                frag->page,
5549                                                frag->page_offset,
5550                                                len, PCI_DMA_TODEVICE);
5551                         if (pci_dma_mapping_error(tp->pdev, mapping))
5552                                 goto dma_error;
5553
5554                         tnapi->tx_buffers[entry].skb = NULL;
5555                         pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5556                                            mapping);
5557
5558                         tg3_set_txd(tnapi, entry, mapping, len,
5559                                     base_flags, (i == last) | (mss << 1));
5560
5561                         entry = NEXT_TX(entry);
5562                 }
5563         }
5564
5565         /* Packets are ready, update Tx producer idx local and on card. */
5566         tw32_tx_mbox(tnapi->prodmbox, entry);
5567
5568         tnapi->tx_prod = entry;
5569         if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5570                 netif_tx_stop_queue(txq);
5571                 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5572                         netif_tx_wake_queue(txq);
5573         }
5574
5575 out_unlock:
5576         mmiowb();
5577
5578         return NETDEV_TX_OK;
5579
5580 dma_error:
5581         last = i;
5582         entry = tnapi->tx_prod;
5583         tnapi->tx_buffers[entry].skb = NULL;
5584         pci_unmap_single(tp->pdev,
5585                          pci_unmap_addr(&tnapi->tx_buffers[entry], mapping),
5586                          skb_headlen(skb),
5587                          PCI_DMA_TODEVICE);
5588         for (i = 0; i <= last; i++) {
5589                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5590                 entry = NEXT_TX(entry);
5591
5592                 pci_unmap_page(tp->pdev,
5593                                pci_unmap_addr(&tnapi->tx_buffers[entry],
5594                                               mapping),
5595                                frag->size, PCI_DMA_TODEVICE);
5596         }
5597
5598         dev_kfree_skb(skb);
5599         return NETDEV_TX_OK;
5600 }
5601
5602 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *,
5603                                           struct net_device *);
5604
5605 /* Use GSO to workaround a rare TSO bug that may be triggered when the
5606  * TSO header is greater than 80 bytes.
5607  */
5608 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5609 {
5610         struct sk_buff *segs, *nskb;
5611         u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
5612
5613         /* Estimate the number of fragments in the worst case */
5614         if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
5615                 netif_stop_queue(tp->dev);
5616                 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
5617                         return NETDEV_TX_BUSY;
5618
5619                 netif_wake_queue(tp->dev);
5620         }
5621
5622         segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
5623         if (IS_ERR(segs))
5624                 goto tg3_tso_bug_end;
5625
5626         do {
5627                 nskb = segs;
5628                 segs = segs->next;
5629                 nskb->next = NULL;
5630                 tg3_start_xmit_dma_bug(nskb, tp->dev);
5631         } while (segs);
5632
5633 tg3_tso_bug_end:
5634         dev_kfree_skb(skb);
5635
5636         return NETDEV_TX_OK;
5637 }
5638
5639 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5640  * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5641  */
5642 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
5643                                           struct net_device *dev)
5644 {
5645         struct tg3 *tp = netdev_priv(dev);
5646         u32 len, entry, base_flags, mss;
5647         int would_hit_hwbug;
5648         dma_addr_t mapping;
5649         struct tg3_napi *tnapi;
5650         struct netdev_queue *txq;
5651         unsigned int i, last;
5652
5653
5654         txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5655         tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5656         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
5657                 tnapi++;
5658
5659         /* We are running in BH disabled context with netif_tx_lock
5660          * and TX reclaim runs via tp->napi.poll inside of a software
5661          * interrupt.  Furthermore, IRQ processing runs lockless so we have
5662          * no IRQ context deadlocks to worry about either.  Rejoice!
5663          */
5664         if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5665                 if (!netif_tx_queue_stopped(txq)) {
5666                         netif_tx_stop_queue(txq);
5667
5668                         /* This is a hard error, log it. */
5669                         printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5670                                "queue awake!\n", dev->name);
5671                 }
5672                 return NETDEV_TX_BUSY;
5673         }
5674
5675         entry = tnapi->tx_prod;
5676         base_flags = 0;
5677         if (skb->ip_summed == CHECKSUM_PARTIAL)
5678                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5679
5680         if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5681                 struct iphdr *iph;
5682                 u32 tcp_opt_len, ip_tcp_len, hdr_len;
5683
5684                 if (skb_header_cloned(skb) &&
5685                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5686                         dev_kfree_skb(skb);
5687                         goto out_unlock;
5688                 }
5689
5690                 tcp_opt_len = tcp_optlen(skb);
5691                 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5692
5693                 hdr_len = ip_tcp_len + tcp_opt_len;
5694                 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
5695                              (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
5696                         return (tg3_tso_bug(tp, skb));
5697
5698                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5699                                TXD_FLAG_CPU_POST_DMA);
5700
5701                 iph = ip_hdr(skb);
5702                 iph->check = 0;
5703                 iph->tot_len = htons(mss + hdr_len);
5704                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
5705                         tcp_hdr(skb)->check = 0;
5706                         base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
5707                 } else
5708                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5709                                                                  iph->daddr, 0,
5710                                                                  IPPROTO_TCP,
5711                                                                  0);
5712
5713                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5714                         mss |= (hdr_len & 0xc) << 12;
5715                         if (hdr_len & 0x10)
5716                                 base_flags |= 0x00000010;
5717                         base_flags |= (hdr_len & 0x3e0) << 5;
5718                 } else if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)
5719                         mss |= hdr_len << 9;
5720                 else if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_1) ||
5721                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
5722                         if (tcp_opt_len || iph->ihl > 5) {
5723                                 int tsflags;
5724
5725                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5726                                 mss |= (tsflags << 11);
5727                         }
5728                 } else {
5729                         if (tcp_opt_len || iph->ihl > 5) {
5730                                 int tsflags;
5731
5732                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5733                                 base_flags |= tsflags << 12;
5734                         }
5735                 }
5736         }
5737 #if TG3_VLAN_TAG_USED
5738         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5739                 base_flags |= (TXD_FLAG_VLAN |
5740                                (vlan_tx_tag_get(skb) << 16));
5741 #endif
5742
5743         if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
5744             !mss && skb->len > ETH_DATA_LEN)
5745                 base_flags |= TXD_FLAG_JMB_PKT;
5746
5747         len = skb_headlen(skb);
5748
5749         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5750         if (pci_dma_mapping_error(tp->pdev, mapping)) {
5751                 dev_kfree_skb(skb);
5752                 goto out_unlock;
5753         }
5754
5755         tnapi->tx_buffers[entry].skb = skb;
5756         pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
5757
5758         would_hit_hwbug = 0;
5759
5760         if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) && len <= 8)
5761                 would_hit_hwbug = 1;
5762
5763         if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5764             tg3_4g_overflow_test(mapping, len))
5765                 would_hit_hwbug = 1;
5766
5767         if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5768             tg3_40bit_overflow_test(tp, mapping, len))
5769                 would_hit_hwbug = 1;
5770
5771         if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
5772                 would_hit_hwbug = 1;
5773
5774         tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5775                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5776
5777         entry = NEXT_TX(entry);
5778
5779         /* Now loop through additional data fragments, and queue them. */
5780         if (skb_shinfo(skb)->nr_frags > 0) {
5781                 last = skb_shinfo(skb)->nr_frags - 1;
5782                 for (i = 0; i <= last; i++) {
5783                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5784
5785                         len = frag->size;
5786                         mapping = pci_map_page(tp->pdev,
5787                                                frag->page,
5788                                                frag->page_offset,
5789                                                len, PCI_DMA_TODEVICE);
5790
5791                         tnapi->tx_buffers[entry].skb = NULL;
5792                         pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5793                                            mapping);
5794                         if (pci_dma_mapping_error(tp->pdev, mapping))
5795                                 goto dma_error;
5796
5797                         if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) &&
5798                             len <= 8)
5799                                 would_hit_hwbug = 1;
5800
5801                         if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5802                             tg3_4g_overflow_test(mapping, len))
5803                                 would_hit_hwbug = 1;
5804
5805                         if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5806                             tg3_40bit_overflow_test(tp, mapping, len))
5807                                 would_hit_hwbug = 1;
5808
5809                         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5810                                 tg3_set_txd(tnapi, entry, mapping, len,
5811                                             base_flags, (i == last)|(mss << 1));
5812                         else
5813                                 tg3_set_txd(tnapi, entry, mapping, len,
5814                                             base_flags, (i == last));
5815
5816                         entry = NEXT_TX(entry);
5817                 }
5818         }
5819
5820         if (would_hit_hwbug) {
5821                 u32 last_plus_one = entry;
5822                 u32 start;
5823
5824                 start = entry - 1 - skb_shinfo(skb)->nr_frags;
5825                 start &= (TG3_TX_RING_SIZE - 1);
5826
5827                 /* If the workaround fails due to memory/mapping
5828                  * failure, silently drop this packet.
5829                  */
5830                 if (tigon3_dma_hwbug_workaround(tnapi, skb, last_plus_one,
5831                                                 &start, base_flags, mss))
5832                         goto out_unlock;
5833
5834                 entry = start;
5835         }
5836
5837         /* Packets are ready, update Tx producer idx local and on card. */
5838         tw32_tx_mbox(tnapi->prodmbox, entry);
5839
5840         tnapi->tx_prod = entry;
5841         if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5842                 netif_tx_stop_queue(txq);
5843                 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5844                         netif_tx_wake_queue(txq);
5845         }
5846
5847 out_unlock:
5848         mmiowb();
5849
5850         return NETDEV_TX_OK;
5851
5852 dma_error:
5853         last = i;
5854         entry = tnapi->tx_prod;
5855         tnapi->tx_buffers[entry].skb = NULL;
5856         pci_unmap_single(tp->pdev,
5857                          pci_unmap_addr(&tnapi->tx_buffers[entry], mapping),
5858                          skb_headlen(skb),
5859                          PCI_DMA_TODEVICE);
5860         for (i = 0; i <= last; i++) {
5861                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5862                 entry = NEXT_TX(entry);
5863
5864                 pci_unmap_page(tp->pdev,
5865                                pci_unmap_addr(&tnapi->tx_buffers[entry],
5866                                               mapping),
5867                                frag->size, PCI_DMA_TODEVICE);
5868         }
5869
5870         dev_kfree_skb(skb);
5871         return NETDEV_TX_OK;
5872 }
5873
5874 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
5875                                int new_mtu)
5876 {
5877         dev->mtu = new_mtu;
5878
5879         if (new_mtu > ETH_DATA_LEN) {
5880                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
5881                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
5882                         ethtool_op_set_tso(dev, 0);
5883                 }
5884                 else
5885                         tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
5886         } else {
5887                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
5888                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
5889                 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
5890         }
5891 }
5892
5893 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
5894 {
5895         struct tg3 *tp = netdev_priv(dev);
5896         int err;
5897
5898         if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
5899                 return -EINVAL;
5900
5901         if (!netif_running(dev)) {
5902                 /* We'll just catch it later when the
5903                  * device is up'd.
5904                  */
5905                 tg3_set_mtu(dev, tp, new_mtu);
5906                 return 0;
5907         }
5908
5909         tg3_phy_stop(tp);
5910
5911         tg3_netif_stop(tp);
5912
5913         tg3_full_lock(tp, 1);
5914
5915         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5916
5917         tg3_set_mtu(dev, tp, new_mtu);
5918
5919         err = tg3_restart_hw(tp, 0);
5920
5921         if (!err)
5922                 tg3_netif_start(tp);
5923
5924         tg3_full_unlock(tp);
5925
5926         if (!err)
5927                 tg3_phy_start(tp);
5928
5929         return err;
5930 }
5931
5932 static void tg3_rx_prodring_free(struct tg3 *tp,
5933                                  struct tg3_rx_prodring_set *tpr)
5934 {
5935         int i;
5936
5937         if (tpr != &tp->prodring[0]) {
5938                 for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx;
5939                      i = (i + 1) % TG3_RX_RING_SIZE)
5940                         tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
5941                                         tp->rx_pkt_map_sz);
5942
5943                 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
5944                         for (i = tpr->rx_jmb_cons_idx;
5945                              i != tpr->rx_jmb_prod_idx;
5946                              i = (i + 1) % TG3_RX_JUMBO_RING_SIZE) {
5947                                 tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
5948                                                 TG3_RX_JMB_MAP_SZ);
5949                         }
5950                 }
5951
5952                 return;
5953         }
5954
5955         for (i = 0; i < TG3_RX_RING_SIZE; i++)
5956                 tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
5957                                 tp->rx_pkt_map_sz);
5958
5959         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
5960                 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++)
5961                         tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
5962                                         TG3_RX_JMB_MAP_SZ);
5963         }
5964 }
5965
5966 /* Initialize tx/rx rings for packet processing.
5967  *
5968  * The chip has been shut down and the driver detached from
5969  * the networking, so no interrupts or new tx packets will
5970  * end up in the driver.  tp->{tx,}lock are held and thus
5971  * we may not sleep.
5972  */
5973 static int tg3_rx_prodring_alloc(struct tg3 *tp,
5974                                  struct tg3_rx_prodring_set *tpr)
5975 {
5976         u32 i, rx_pkt_dma_sz;
5977
5978         tpr->rx_std_cons_idx = 0;
5979         tpr->rx_std_prod_idx = 0;
5980         tpr->rx_jmb_cons_idx = 0;
5981         tpr->rx_jmb_prod_idx = 0;
5982
5983         if (tpr != &tp->prodring[0]) {
5984                 memset(&tpr->rx_std_buffers[0], 0, TG3_RX_STD_BUFF_RING_SIZE);
5985                 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE)
5986                         memset(&tpr->rx_jmb_buffers[0], 0,
5987                                TG3_RX_JMB_BUFF_RING_SIZE);
5988                 goto done;
5989         }
5990
5991         /* Zero out all descriptors. */
5992         memset(tpr->rx_std, 0, TG3_RX_RING_BYTES);
5993
5994         rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
5995         if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
5996             tp->dev->mtu > ETH_DATA_LEN)
5997                 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
5998         tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
5999
6000         /* Initialize invariants of the rings, we only set this
6001          * stuff once.  This works because the card does not
6002          * write into the rx buffer posting rings.
6003          */
6004         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
6005                 struct tg3_rx_buffer_desc *rxd;
6006
6007                 rxd = &tpr->rx_std[i];
6008                 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
6009                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
6010                 rxd->opaque = (RXD_OPAQUE_RING_STD |
6011                                (i << RXD_OPAQUE_INDEX_SHIFT));
6012         }
6013
6014         /* Now allocate fresh SKBs for each rx ring. */
6015         for (i = 0; i < tp->rx_pending; i++) {
6016                 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_STD, i) < 0) {
6017                         printk(KERN_WARNING PFX
6018                                "%s: Using a smaller RX standard ring, "
6019                                "only %d out of %d buffers were allocated "
6020                                "successfully.\n",
6021                                tp->dev->name, i, tp->rx_pending);
6022                         if (i == 0)
6023                                 goto initfail;
6024                         tp->rx_pending = i;
6025                         break;
6026                 }
6027         }
6028
6029         if (!(tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE))
6030                 goto done;
6031
6032         memset(tpr->rx_jmb, 0, TG3_RX_JUMBO_RING_BYTES);
6033
6034         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
6035                 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
6036                         struct tg3_rx_buffer_desc *rxd;
6037
6038                         rxd = &tpr->rx_jmb[i].std;
6039                         rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
6040                         rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
6041                                 RXD_FLAG_JUMBO;
6042                         rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
6043                                (i << RXD_OPAQUE_INDEX_SHIFT));
6044                 }
6045
6046                 for (i = 0; i < tp->rx_jumbo_pending; i++) {
6047                         if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_JUMBO,
6048                                              i) < 0) {
6049                                 printk(KERN_WARNING PFX
6050                                        "%s: Using a smaller RX jumbo ring, "
6051                                        "only %d out of %d buffers were "
6052                                        "allocated successfully.\n",
6053                                        tp->dev->name, i, tp->rx_jumbo_pending);
6054                                 if (i == 0)
6055                                         goto initfail;
6056                                 tp->rx_jumbo_pending = i;
6057                                 break;
6058                         }
6059                 }
6060         }
6061
6062 done:
6063         return 0;
6064
6065 initfail:
6066         tg3_rx_prodring_free(tp, tpr);
6067         return -ENOMEM;
6068 }
6069
6070 static void tg3_rx_prodring_fini(struct tg3 *tp,
6071                                  struct tg3_rx_prodring_set *tpr)
6072 {
6073         kfree(tpr->rx_std_buffers);
6074         tpr->rx_std_buffers = NULL;
6075         kfree(tpr->rx_jmb_buffers);
6076         tpr->rx_jmb_buffers = NULL;
6077         if (tpr->rx_std) {
6078                 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
6079                                     tpr->rx_std, tpr->rx_std_mapping);
6080                 tpr->rx_std = NULL;
6081         }
6082         if (tpr->rx_jmb) {
6083                 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
6084                                     tpr->rx_jmb, tpr->rx_jmb_mapping);
6085                 tpr->rx_jmb = NULL;
6086         }
6087 }
6088
6089 static int tg3_rx_prodring_init(struct tg3 *tp,
6090                                 struct tg3_rx_prodring_set *tpr)
6091 {
6092         tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE, GFP_KERNEL);
6093         if (!tpr->rx_std_buffers)
6094                 return -ENOMEM;
6095
6096         tpr->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
6097                                            &tpr->rx_std_mapping);
6098         if (!tpr->rx_std)
6099                 goto err_out;
6100
6101         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
6102                 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE,
6103                                               GFP_KERNEL);
6104                 if (!tpr->rx_jmb_buffers)
6105                         goto err_out;
6106
6107                 tpr->rx_jmb = pci_alloc_consistent(tp->pdev,
6108                                                    TG3_RX_JUMBO_RING_BYTES,
6109                                                    &tpr->rx_jmb_mapping);
6110                 if (!tpr->rx_jmb)
6111                         goto err_out;
6112         }
6113
6114         return 0;
6115
6116 err_out:
6117         tg3_rx_prodring_fini(tp, tpr);
6118         return -ENOMEM;
6119 }
6120
6121 /* Free up pending packets in all rx/tx rings.
6122  *
6123  * The chip has been shut down and the driver detached from
6124  * the networking, so no interrupts or new tx packets will
6125  * end up in the driver.  tp->{tx,}lock is not held and we are not
6126  * in an interrupt context and thus may sleep.
6127  */
6128 static void tg3_free_rings(struct tg3 *tp)
6129 {
6130         int i, j;
6131
6132         for (j = 0; j < tp->irq_cnt; j++) {
6133                 struct tg3_napi *tnapi = &tp->napi[j];
6134
6135                 if (!tnapi->tx_buffers)
6136                         continue;
6137
6138                 for (i = 0; i < TG3_TX_RING_SIZE; ) {
6139                         struct ring_info *txp;
6140                         struct sk_buff *skb;
6141                         unsigned int k;
6142
6143                         txp = &tnapi->tx_buffers[i];
6144                         skb = txp->skb;
6145
6146                         if (skb == NULL) {
6147                                 i++;
6148                                 continue;
6149                         }
6150
6151                         pci_unmap_single(tp->pdev,
6152                                          pci_unmap_addr(txp, mapping),
6153                                          skb_headlen(skb),
6154                                          PCI_DMA_TODEVICE);
6155                         txp->skb = NULL;
6156
6157                         i++;
6158
6159                         for (k = 0; k < skb_shinfo(skb)->nr_frags; k++) {
6160                                 txp = &tnapi->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
6161                                 pci_unmap_page(tp->pdev,
6162                                                pci_unmap_addr(txp, mapping),
6163                                                skb_shinfo(skb)->frags[k].size,
6164                                                PCI_DMA_TODEVICE);
6165                                 i++;
6166                         }
6167
6168                         dev_kfree_skb_any(skb);
6169                 }
6170
6171                 if (tp->irq_cnt == 1 || j != tp->irq_cnt - 1)
6172                         tg3_rx_prodring_free(tp, &tp->prodring[j]);
6173         }
6174 }
6175
6176 /* Initialize tx/rx rings for packet processing.
6177  *
6178  * The chip has been shut down and the driver detached from
6179  * the networking, so no interrupts or new tx packets will
6180  * end up in the driver.  tp->{tx,}lock are held and thus
6181  * we may not sleep.
6182  */
6183 static int tg3_init_rings(struct tg3 *tp)
6184 {
6185         int i;
6186
6187         /* Free up all the SKBs. */
6188         tg3_free_rings(tp);
6189
6190         for (i = 0; i < tp->irq_cnt; i++) {
6191                 struct tg3_napi *tnapi = &tp->napi[i];
6192
6193                 tnapi->last_tag = 0;
6194                 tnapi->last_irq_tag = 0;
6195                 tnapi->hw_status->status = 0;
6196                 tnapi->hw_status->status_tag = 0;
6197                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6198
6199                 tnapi->tx_prod = 0;
6200                 tnapi->tx_cons = 0;
6201                 if (tnapi->tx_ring)
6202                         memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
6203
6204                 tnapi->rx_rcb_ptr = 0;
6205                 if (tnapi->rx_rcb)
6206                         memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
6207
6208                 if ((tp->irq_cnt == 1 || i != tp->irq_cnt - 1) &&
6209                         tg3_rx_prodring_alloc(tp, &tp->prodring[i]))
6210                         return -ENOMEM;
6211         }
6212
6213         return 0;
6214 }
6215
6216 /*
6217  * Must not be invoked with interrupt sources disabled and
6218  * the hardware shutdown down.
6219  */
6220 static void tg3_free_consistent(struct tg3 *tp)
6221 {
6222         int i;
6223
6224         for (i = 0; i < tp->irq_cnt; i++) {
6225                 struct tg3_napi *tnapi = &tp->napi[i];
6226
6227                 if (tnapi->tx_ring) {
6228                         pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
6229                                 tnapi->tx_ring, tnapi->tx_desc_mapping);
6230                         tnapi->tx_ring = NULL;
6231                 }
6232
6233                 kfree(tnapi->tx_buffers);
6234                 tnapi->tx_buffers = NULL;
6235
6236                 if (tnapi->rx_rcb) {
6237                         pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
6238                                             tnapi->rx_rcb,
6239                                             tnapi->rx_rcb_mapping);
6240                         tnapi->rx_rcb = NULL;
6241                 }
6242
6243                 if (tnapi->hw_status) {
6244                         pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
6245                                             tnapi->hw_status,
6246                                             tnapi->status_mapping);
6247                         tnapi->hw_status = NULL;
6248                 }
6249         }
6250
6251         if (tp->hw_stats) {
6252                 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
6253                                     tp->hw_stats, tp->stats_mapping);
6254                 tp->hw_stats = NULL;
6255         }
6256
6257         for (i = 0; i < (tp->irq_cnt == 1 ? 1 : tp->irq_cnt - 1); i++)
6258                 tg3_rx_prodring_fini(tp, &tp->prodring[i]);
6259 }
6260
6261 /*
6262  * Must not be invoked with interrupt sources disabled and
6263  * the hardware shutdown down.  Can sleep.
6264  */
6265 static int tg3_alloc_consistent(struct tg3 *tp)
6266 {
6267         int i;
6268
6269         for (i = 0; i < (tp->irq_cnt == 1 ? 1 : tp->irq_cnt - 1); i++) {
6270                 if (tg3_rx_prodring_init(tp, &tp->prodring[i]))
6271                         goto err_out;
6272         }
6273
6274         tp->hw_stats = pci_alloc_consistent(tp->pdev,
6275                                             sizeof(struct tg3_hw_stats),
6276                                             &tp->stats_mapping);
6277         if (!tp->hw_stats)
6278                 goto err_out;
6279
6280         memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6281
6282         for (i = 0; i < tp->irq_cnt; i++) {
6283                 struct tg3_napi *tnapi = &tp->napi[i];
6284                 struct tg3_hw_status *sblk;
6285
6286                 tnapi->hw_status = pci_alloc_consistent(tp->pdev,
6287                                                         TG3_HW_STATUS_SIZE,
6288                                                         &tnapi->status_mapping);
6289                 if (!tnapi->hw_status)
6290                         goto err_out;
6291
6292                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6293                 sblk = tnapi->hw_status;
6294
6295                 /* If multivector TSS is enabled, vector 0 does not handle
6296                  * tx interrupts.  Don't allocate any resources for it.
6297                  */
6298                 if ((!i && !(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) ||
6299                     (i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))) {
6300                         tnapi->tx_buffers = kzalloc(sizeof(struct ring_info) *
6301                                                     TG3_TX_RING_SIZE,
6302                                                     GFP_KERNEL);
6303                         if (!tnapi->tx_buffers)
6304                                 goto err_out;
6305
6306                         tnapi->tx_ring = pci_alloc_consistent(tp->pdev,
6307                                                               TG3_TX_RING_BYTES,
6308                                                        &tnapi->tx_desc_mapping);
6309                         if (!tnapi->tx_ring)
6310                                 goto err_out;
6311                 }
6312
6313                 /*
6314                  * When RSS is enabled, the status block format changes
6315                  * slightly.  The "rx_jumbo_consumer", "reserved",
6316                  * and "rx_mini_consumer" members get mapped to the
6317                  * other three rx return ring producer indexes.
6318                  */
6319                 switch (i) {
6320                 default:
6321                         tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
6322                         break;
6323                 case 2:
6324                         tnapi->rx_rcb_prod_idx = &sblk->rx_jumbo_consumer;
6325                         break;
6326                 case 3:
6327                         tnapi->rx_rcb_prod_idx = &sblk->reserved;
6328                         break;
6329                 case 4:
6330                         tnapi->rx_rcb_prod_idx = &sblk->rx_mini_consumer;
6331                         break;
6332                 }
6333
6334                 if (tp->irq_cnt == 1)
6335                         tnapi->prodring = &tp->prodring[0];
6336                 else if (i)
6337                         tnapi->prodring = &tp->prodring[i - 1];
6338
6339                 /*
6340                  * If multivector RSS is enabled, vector 0 does not handle
6341                  * rx or tx interrupts.  Don't allocate any resources for it.
6342                  */
6343                 if (!i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS))
6344                         continue;
6345
6346                 tnapi->rx_rcb = pci_alloc_consistent(tp->pdev,
6347                                                      TG3_RX_RCB_RING_BYTES(tp),
6348                                                      &tnapi->rx_rcb_mapping);
6349                 if (!tnapi->rx_rcb)
6350                         goto err_out;
6351
6352                 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
6353         }
6354
6355         return 0;
6356
6357 err_out:
6358         tg3_free_consistent(tp);
6359         return -ENOMEM;
6360 }
6361
6362 #define MAX_WAIT_CNT 1000
6363
6364 /* To stop a block, clear the enable bit and poll till it
6365  * clears.  tp->lock is held.
6366  */
6367 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
6368 {
6369         unsigned int i;
6370         u32 val;
6371
6372         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6373                 switch (ofs) {
6374                 case RCVLSC_MODE:
6375                 case DMAC_MODE:
6376                 case MBFREE_MODE:
6377                 case BUFMGR_MODE:
6378                 case MEMARB_MODE:
6379                         /* We can't enable/disable these bits of the
6380                          * 5705/5750, just say success.
6381                          */
6382                         return 0;
6383
6384                 default:
6385                         break;
6386                 }
6387         }
6388
6389         val = tr32(ofs);
6390         val &= ~enable_bit;
6391         tw32_f(ofs, val);
6392
6393         for (i = 0; i < MAX_WAIT_CNT; i++) {
6394                 udelay(100);
6395                 val = tr32(ofs);
6396                 if ((val & enable_bit) == 0)
6397                         break;
6398         }
6399
6400         if (i == MAX_WAIT_CNT && !silent) {
6401                 printk(KERN_ERR PFX "tg3_stop_block timed out, "
6402                        "ofs=%lx enable_bit=%x\n",
6403                        ofs, enable_bit);
6404                 return -ENODEV;
6405         }
6406
6407         return 0;
6408 }
6409
6410 /* tp->lock is held. */
6411 static int tg3_abort_hw(struct tg3 *tp, int silent)
6412 {
6413         int i, err;
6414
6415         tg3_disable_ints(tp);
6416
6417         tp->rx_mode &= ~RX_MODE_ENABLE;
6418         tw32_f(MAC_RX_MODE, tp->rx_mode);
6419         udelay(10);
6420
6421         err  = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
6422         err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
6423         err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
6424         err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
6425         err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
6426         err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
6427
6428         err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
6429         err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
6430         err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
6431         err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
6432         err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
6433         err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
6434         err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
6435
6436         tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
6437         tw32_f(MAC_MODE, tp->mac_mode);
6438         udelay(40);
6439
6440         tp->tx_mode &= ~TX_MODE_ENABLE;
6441         tw32_f(MAC_TX_MODE, tp->tx_mode);
6442
6443         for (i = 0; i < MAX_WAIT_CNT; i++) {
6444                 udelay(100);
6445                 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
6446                         break;
6447         }
6448         if (i >= MAX_WAIT_CNT) {
6449                 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
6450                        "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
6451                        tp->dev->name, tr32(MAC_TX_MODE));
6452                 err |= -ENODEV;
6453         }
6454
6455         err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
6456         err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
6457         err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
6458
6459         tw32(FTQ_RESET, 0xffffffff);
6460         tw32(FTQ_RESET, 0x00000000);
6461
6462         err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
6463         err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
6464
6465         for (i = 0; i < tp->irq_cnt; i++) {
6466                 struct tg3_napi *tnapi = &tp->napi[i];
6467                 if (tnapi->hw_status)
6468                         memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6469         }
6470         if (tp->hw_stats)
6471                 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6472
6473         return err;
6474 }
6475
6476 static void tg3_ape_send_event(struct tg3 *tp, u32 event)
6477 {
6478         int i;
6479         u32 apedata;
6480
6481         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
6482         if (apedata != APE_SEG_SIG_MAGIC)
6483                 return;
6484
6485         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
6486         if (!(apedata & APE_FW_STATUS_READY))
6487                 return;
6488
6489         /* Wait for up to 1 millisecond for APE to service previous event. */
6490         for (i = 0; i < 10; i++) {
6491                 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
6492                         return;
6493
6494                 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
6495
6496                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6497                         tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
6498                                         event | APE_EVENT_STATUS_EVENT_PENDING);
6499
6500                 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
6501
6502                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6503                         break;
6504
6505                 udelay(100);
6506         }
6507
6508         if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6509                 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
6510 }
6511
6512 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
6513 {
6514         u32 event;
6515         u32 apedata;
6516
6517         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
6518                 return;
6519
6520         switch (kind) {
6521                 case RESET_KIND_INIT:
6522                         tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
6523                                         APE_HOST_SEG_SIG_MAGIC);
6524                         tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
6525                                         APE_HOST_SEG_LEN_MAGIC);
6526                         apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
6527                         tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
6528                         tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
6529                                         APE_HOST_DRIVER_ID_MAGIC);
6530                         tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
6531                                         APE_HOST_BEHAV_NO_PHYLOCK);
6532
6533                         event = APE_EVENT_STATUS_STATE_START;
6534                         break;
6535                 case RESET_KIND_SHUTDOWN:
6536                         /* With the interface we are currently using,
6537                          * APE does not track driver state.  Wiping
6538                          * out the HOST SEGMENT SIGNATURE forces
6539                          * the APE to assume OS absent status.
6540                          */
6541                         tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
6542
6543                         event = APE_EVENT_STATUS_STATE_UNLOAD;
6544                         break;
6545                 case RESET_KIND_SUSPEND:
6546                         event = APE_EVENT_STATUS_STATE_SUSPEND;
6547                         break;
6548                 default:
6549                         return;
6550         }
6551
6552         event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
6553
6554         tg3_ape_send_event(tp, event);
6555 }
6556
6557 /* tp->lock is held. */
6558 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
6559 {
6560         tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
6561                       NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
6562
6563         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6564                 switch (kind) {
6565                 case RESET_KIND_INIT:
6566                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6567                                       DRV_STATE_START);
6568                         break;
6569
6570                 case RESET_KIND_SHUTDOWN:
6571                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6572                                       DRV_STATE_UNLOAD);
6573                         break;
6574
6575                 case RESET_KIND_SUSPEND:
6576                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6577                                       DRV_STATE_SUSPEND);
6578                         break;
6579
6580                 default:
6581                         break;
6582                 }
6583         }
6584
6585         if (kind == RESET_KIND_INIT ||
6586             kind == RESET_KIND_SUSPEND)
6587                 tg3_ape_driver_state_change(tp, kind);
6588 }
6589
6590 /* tp->lock is held. */
6591 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
6592 {
6593         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6594                 switch (kind) {
6595                 case RESET_KIND_INIT:
6596                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6597                                       DRV_STATE_START_DONE);
6598                         break;
6599
6600                 case RESET_KIND_SHUTDOWN:
6601                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6602                                       DRV_STATE_UNLOAD_DONE);
6603                         break;
6604
6605                 default:
6606                         break;
6607                 }
6608         }
6609
6610         if (kind == RESET_KIND_SHUTDOWN)
6611                 tg3_ape_driver_state_change(tp, kind);
6612 }
6613
6614 /* tp->lock is held. */
6615 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
6616 {
6617         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6618                 switch (kind) {
6619                 case RESET_KIND_INIT:
6620                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6621                                       DRV_STATE_START);
6622                         break;
6623
6624                 case RESET_KIND_SHUTDOWN:
6625                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6626                                       DRV_STATE_UNLOAD);
6627                         break;
6628
6629                 case RESET_KIND_SUSPEND:
6630                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6631                                       DRV_STATE_SUSPEND);
6632                         break;
6633
6634                 default:
6635                         break;
6636                 }
6637         }
6638 }
6639
6640 static int tg3_poll_fw(struct tg3 *tp)
6641 {
6642         int i;
6643         u32 val;
6644
6645         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6646                 /* Wait up to 20ms for init done. */
6647                 for (i = 0; i < 200; i++) {
6648                         if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
6649                                 return 0;
6650                         udelay(100);
6651                 }
6652                 return -ENODEV;
6653         }
6654
6655         /* Wait for firmware initialization to complete. */
6656         for (i = 0; i < 100000; i++) {
6657                 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
6658                 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
6659                         break;
6660                 udelay(10);
6661         }
6662
6663         /* Chip might not be fitted with firmware.  Some Sun onboard
6664          * parts are configured like that.  So don't signal the timeout
6665          * of the above loop as an error, but do report the lack of
6666          * running firmware once.
6667          */
6668         if (i >= 100000 &&
6669             !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
6670                 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
6671
6672                 printk(KERN_INFO PFX "%s: No firmware running.\n",
6673                        tp->dev->name);
6674         }
6675
6676         return 0;
6677 }
6678
6679 /* Save PCI command register before chip reset */
6680 static void tg3_save_pci_state(struct tg3 *tp)
6681 {
6682         pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
6683 }
6684
6685 /* Restore PCI state after chip reset */
6686 static void tg3_restore_pci_state(struct tg3 *tp)
6687 {
6688         u32 val;
6689
6690         /* Re-enable indirect register accesses. */
6691         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
6692                                tp->misc_host_ctrl);
6693
6694         /* Set MAX PCI retry to zero. */
6695         val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
6696         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6697             (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
6698                 val |= PCISTATE_RETRY_SAME_DMA;
6699         /* Allow reads and writes to the APE register and memory space. */
6700         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
6701                 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6702                        PCISTATE_ALLOW_APE_SHMEM_WR;
6703         pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
6704
6705         pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
6706
6707         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
6708                 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6709                         pcie_set_readrq(tp->pdev, 4096);
6710                 else {
6711                         pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
6712                                               tp->pci_cacheline_sz);
6713                         pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
6714                                               tp->pci_lat_timer);
6715                 }
6716         }
6717
6718         /* Make sure PCI-X relaxed ordering bit is clear. */
6719         if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
6720                 u16 pcix_cmd;
6721
6722                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6723                                      &pcix_cmd);
6724                 pcix_cmd &= ~PCI_X_CMD_ERO;
6725                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6726                                       pcix_cmd);
6727         }
6728
6729         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
6730
6731                 /* Chip reset on 5780 will reset MSI enable bit,
6732                  * so need to restore it.
6733                  */
6734                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6735                         u16 ctrl;
6736
6737                         pci_read_config_word(tp->pdev,
6738                                              tp->msi_cap + PCI_MSI_FLAGS,
6739                                              &ctrl);
6740                         pci_write_config_word(tp->pdev,
6741                                               tp->msi_cap + PCI_MSI_FLAGS,
6742                                               ctrl | PCI_MSI_FLAGS_ENABLE);
6743                         val = tr32(MSGINT_MODE);
6744                         tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
6745                 }
6746         }
6747 }
6748
6749 static void tg3_stop_fw(struct tg3 *);
6750
6751 /* tp->lock is held. */
6752 static int tg3_chip_reset(struct tg3 *tp)
6753 {
6754         u32 val;
6755         void (*write_op)(struct tg3 *, u32, u32);
6756         int i, err;
6757
6758         tg3_nvram_lock(tp);
6759
6760         tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
6761
6762         /* No matching tg3_nvram_unlock() after this because
6763          * chip reset below will undo the nvram lock.
6764          */
6765         tp->nvram_lock_cnt = 0;
6766
6767         /* GRC_MISC_CFG core clock reset will clear the memory
6768          * enable bit in PCI register 4 and the MSI enable bit
6769          * on some chips, so we save relevant registers here.
6770          */
6771         tg3_save_pci_state(tp);
6772
6773         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
6774             (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
6775                 tw32(GRC_FASTBOOT_PC, 0);
6776
6777         /*
6778          * We must avoid the readl() that normally takes place.
6779          * It locks machines, causes machine checks, and other
6780          * fun things.  So, temporarily disable the 5701
6781          * hardware workaround, while we do the reset.
6782          */
6783         write_op = tp->write32;
6784         if (write_op == tg3_write_flush_reg32)
6785                 tp->write32 = tg3_write32;
6786
6787         /* Prevent the irq handler from reading or writing PCI registers
6788          * during chip reset when the memory enable bit in the PCI command
6789          * register may be cleared.  The chip does not generate interrupt
6790          * at this time, but the irq handler may still be called due to irq
6791          * sharing or irqpoll.
6792          */
6793         tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
6794         for (i = 0; i < tp->irq_cnt; i++) {
6795                 struct tg3_napi *tnapi = &tp->napi[i];
6796                 if (tnapi->hw_status) {
6797                         tnapi->hw_status->status = 0;
6798                         tnapi->hw_status->status_tag = 0;
6799                 }
6800                 tnapi->last_tag = 0;
6801                 tnapi->last_irq_tag = 0;
6802         }
6803         smp_mb();
6804
6805         for (i = 0; i < tp->irq_cnt; i++)
6806                 synchronize_irq(tp->napi[i].irq_vec);
6807
6808         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6809                 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
6810                 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
6811         }
6812
6813         /* do the reset */
6814         val = GRC_MISC_CFG_CORECLK_RESET;
6815
6816         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
6817                 if (tr32(0x7e2c) == 0x60) {
6818                         tw32(0x7e2c, 0x20);
6819                 }
6820                 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
6821                         tw32(GRC_MISC_CFG, (1 << 29));
6822                         val |= (1 << 29);
6823                 }
6824         }
6825
6826         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6827                 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
6828                 tw32(GRC_VCPU_EXT_CTRL,
6829                      tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
6830         }
6831
6832         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6833                 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
6834         tw32(GRC_MISC_CFG, val);
6835
6836         /* restore 5701 hardware bug workaround write method */
6837         tp->write32 = write_op;
6838
6839         /* Unfortunately, we have to delay before the PCI read back.
6840          * Some 575X chips even will not respond to a PCI cfg access
6841          * when the reset command is given to the chip.
6842          *
6843          * How do these hardware designers expect things to work
6844          * properly if the PCI write is posted for a long period
6845          * of time?  It is always necessary to have some method by
6846          * which a register read back can occur to push the write
6847          * out which does the reset.
6848          *
6849          * For most tg3 variants the trick below was working.
6850          * Ho hum...
6851          */
6852         udelay(120);
6853
6854         /* Flush PCI posted writes.  The normal MMIO registers
6855          * are inaccessible at this time so this is the only
6856          * way to make this reliably (actually, this is no longer
6857          * the case, see above).  I tried to use indirect
6858          * register read/write but this upset some 5701 variants.
6859          */
6860         pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
6861
6862         udelay(120);
6863
6864         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
6865                 u16 val16;
6866
6867                 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
6868                         int i;
6869                         u32 cfg_val;
6870
6871                         /* Wait for link training to complete.  */
6872                         for (i = 0; i < 5000; i++)
6873                                 udelay(100);
6874
6875                         pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
6876                         pci_write_config_dword(tp->pdev, 0xc4,
6877                                                cfg_val | (1 << 15));
6878                 }
6879
6880                 /* Clear the "no snoop" and "relaxed ordering" bits. */
6881                 pci_read_config_word(tp->pdev,
6882                                      tp->pcie_cap + PCI_EXP_DEVCTL,
6883                                      &val16);
6884                 val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
6885                            PCI_EXP_DEVCTL_NOSNOOP_EN);
6886                 /*
6887                  * Older PCIe devices only support the 128 byte
6888                  * MPS setting.  Enforce the restriction.
6889                  */
6890                 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
6891                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784))
6892                         val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
6893                 pci_write_config_word(tp->pdev,
6894                                       tp->pcie_cap + PCI_EXP_DEVCTL,
6895                                       val16);
6896
6897                 pcie_set_readrq(tp->pdev, 4096);
6898
6899                 /* Clear error status */
6900                 pci_write_config_word(tp->pdev,
6901                                       tp->pcie_cap + PCI_EXP_DEVSTA,
6902                                       PCI_EXP_DEVSTA_CED |
6903                                       PCI_EXP_DEVSTA_NFED |
6904                                       PCI_EXP_DEVSTA_FED |
6905                                       PCI_EXP_DEVSTA_URD);
6906         }
6907
6908         tg3_restore_pci_state(tp);
6909
6910         tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
6911
6912         val = 0;
6913         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
6914                 val = tr32(MEMARB_MODE);
6915         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
6916
6917         if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
6918                 tg3_stop_fw(tp);
6919                 tw32(0x5000, 0x400);
6920         }
6921
6922         tw32(GRC_MODE, tp->grc_mode);
6923
6924         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
6925                 val = tr32(0xc4);
6926
6927                 tw32(0xc4, val | (1 << 15));
6928         }
6929
6930         if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
6931             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6932                 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
6933                 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
6934                         tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
6935                 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6936         }
6937
6938         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6939                 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
6940                 tw32_f(MAC_MODE, tp->mac_mode);
6941         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
6942                 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
6943                 tw32_f(MAC_MODE, tp->mac_mode);
6944         } else if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
6945                 tp->mac_mode &= (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
6946                 if (tp->mac_mode & MAC_MODE_APE_TX_EN)
6947                         tp->mac_mode |= MAC_MODE_TDE_ENABLE;
6948                 tw32_f(MAC_MODE, tp->mac_mode);
6949         } else
6950                 tw32_f(MAC_MODE, 0);
6951         udelay(40);
6952
6953         tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
6954
6955         err = tg3_poll_fw(tp);
6956         if (err)
6957                 return err;
6958
6959         tg3_mdio_start(tp);
6960
6961         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6962                 u8 phy_addr;
6963
6964                 phy_addr = tp->phy_addr;
6965                 tp->phy_addr = TG3_PHY_PCIE_ADDR;
6966
6967                 tg3_writephy(tp, TG3_PCIEPHY_BLOCK_ADDR,
6968                              TG3_PCIEPHY_TXB_BLK << TG3_PCIEPHY_BLOCK_SHIFT);
6969                 val = TG3_PCIEPHY_TX0CTRL1_TXOCM | TG3_PCIEPHY_TX0CTRL1_RDCTL |
6970                       TG3_PCIEPHY_TX0CTRL1_TXCMV | TG3_PCIEPHY_TX0CTRL1_TKSEL |
6971                       TG3_PCIEPHY_TX0CTRL1_NB_EN;
6972                 tg3_writephy(tp, TG3_PCIEPHY_TX0CTRL1, val);
6973                 udelay(10);
6974
6975                 tg3_writephy(tp, TG3_PCIEPHY_BLOCK_ADDR,
6976                              TG3_PCIEPHY_XGXS_BLK1 << TG3_PCIEPHY_BLOCK_SHIFT);
6977                 val = TG3_PCIEPHY_PWRMGMT4_LOWPWR_EN |
6978                       TG3_PCIEPHY_PWRMGMT4_L1PLLPD_EN;
6979                 tg3_writephy(tp, TG3_PCIEPHY_PWRMGMT4, val);
6980                 udelay(10);
6981
6982                 tp->phy_addr = phy_addr;
6983         }
6984
6985         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
6986             tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
6987             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
6988             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
6989             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765) {
6990                 val = tr32(0x7c00);
6991
6992                 tw32(0x7c00, val | (1 << 25));
6993         }
6994
6995         /* Reprobe ASF enable state.  */
6996         tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
6997         tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
6998         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
6999         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
7000                 u32 nic_cfg;
7001
7002                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
7003                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
7004                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
7005                         tp->last_event_jiffies = jiffies;
7006                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
7007                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
7008                 }
7009         }
7010
7011         return 0;
7012 }
7013
7014 /* tp->lock is held. */
7015 static void tg3_stop_fw(struct tg3 *tp)
7016 {
7017         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
7018            !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7019                 /* Wait for RX cpu to ACK the previous event. */
7020                 tg3_wait_for_event_ack(tp);
7021
7022                 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
7023
7024                 tg3_generate_fw_event(tp);
7025
7026                 /* Wait for RX cpu to ACK this event. */
7027                 tg3_wait_for_event_ack(tp);
7028         }
7029 }
7030
7031 /* tp->lock is held. */
7032 static int tg3_halt(struct tg3 *tp, int kind, int silent)
7033 {
7034         int err;
7035
7036         tg3_stop_fw(tp);
7037
7038         tg3_write_sig_pre_reset(tp, kind);
7039
7040         tg3_abort_hw(tp, silent);
7041         err = tg3_chip_reset(tp);
7042
7043         __tg3_set_mac_addr(tp, 0);
7044
7045         tg3_write_sig_legacy(tp, kind);
7046         tg3_write_sig_post_reset(tp, kind);
7047
7048         if (err)
7049                 return err;
7050
7051         return 0;
7052 }
7053
7054 #define RX_CPU_SCRATCH_BASE     0x30000
7055 #define RX_CPU_SCRATCH_SIZE     0x04000
7056 #define TX_CPU_SCRATCH_BASE     0x34000
7057 #define TX_CPU_SCRATCH_SIZE     0x04000
7058
7059 /* tp->lock is held. */
7060 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
7061 {
7062         int i;
7063
7064         BUG_ON(offset == TX_CPU_BASE &&
7065             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
7066
7067         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7068                 u32 val = tr32(GRC_VCPU_EXT_CTRL);
7069
7070                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
7071                 return 0;
7072         }
7073         if (offset == RX_CPU_BASE) {
7074                 for (i = 0; i < 10000; i++) {
7075                         tw32(offset + CPU_STATE, 0xffffffff);
7076                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
7077                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7078                                 break;
7079                 }
7080
7081                 tw32(offset + CPU_STATE, 0xffffffff);
7082                 tw32_f(offset + CPU_MODE,  CPU_MODE_HALT);
7083                 udelay(10);
7084         } else {
7085                 for (i = 0; i < 10000; i++) {
7086                         tw32(offset + CPU_STATE, 0xffffffff);
7087                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
7088                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7089                                 break;
7090                 }
7091         }
7092
7093         if (i >= 10000) {
7094                 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
7095                        "and %s CPU\n",
7096                        tp->dev->name,
7097                        (offset == RX_CPU_BASE ? "RX" : "TX"));
7098                 return -ENODEV;
7099         }
7100
7101         /* Clear firmware's nvram arbitration. */
7102         if (tp->tg3_flags & TG3_FLAG_NVRAM)
7103                 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
7104         return 0;
7105 }
7106
7107 struct fw_info {
7108         unsigned int fw_base;
7109         unsigned int fw_len;
7110         const __be32 *fw_data;
7111 };
7112
7113 /* tp->lock is held. */
7114 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
7115                                  int cpu_scratch_size, struct fw_info *info)
7116 {
7117         int err, lock_err, i;
7118         void (*write_op)(struct tg3 *, u32, u32);
7119
7120         if (cpu_base == TX_CPU_BASE &&
7121             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7122                 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
7123                        "TX cpu firmware on %s which is 5705.\n",
7124                        tp->dev->name);
7125                 return -EINVAL;
7126         }
7127
7128         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7129                 write_op = tg3_write_mem;
7130         else
7131                 write_op = tg3_write_indirect_reg32;
7132
7133         /* It is possible that bootcode is still loading at this point.
7134          * Get the nvram lock first before halting the cpu.
7135          */
7136         lock_err = tg3_nvram_lock(tp);
7137         err = tg3_halt_cpu(tp, cpu_base);
7138         if (!lock_err)
7139                 tg3_nvram_unlock(tp);
7140         if (err)
7141                 goto out;
7142
7143         for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
7144                 write_op(tp, cpu_scratch_base + i, 0);
7145         tw32(cpu_base + CPU_STATE, 0xffffffff);
7146         tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
7147         for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
7148                 write_op(tp, (cpu_scratch_base +
7149                               (info->fw_base & 0xffff) +
7150                               (i * sizeof(u32))),
7151                               be32_to_cpu(info->fw_data[i]));
7152
7153         err = 0;
7154
7155 out:
7156         return err;
7157 }
7158
7159 /* tp->lock is held. */
7160 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
7161 {
7162         struct fw_info info;
7163         const __be32 *fw_data;
7164         int err, i;
7165
7166         fw_data = (void *)tp->fw->data;
7167
7168         /* Firmware blob starts with version numbers, followed by
7169            start address and length. We are setting complete length.
7170            length = end_address_of_bss - start_address_of_text.
7171            Remainder is the blob to be loaded contiguously
7172            from start address. */
7173
7174         info.fw_base = be32_to_cpu(fw_data[1]);
7175         info.fw_len = tp->fw->size - 12;
7176         info.fw_data = &fw_data[3];
7177
7178         err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
7179                                     RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
7180                                     &info);
7181         if (err)
7182                 return err;
7183
7184         err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
7185                                     TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
7186                                     &info);
7187         if (err)
7188                 return err;
7189
7190         /* Now startup only the RX cpu. */
7191         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7192         tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
7193
7194         for (i = 0; i < 5; i++) {
7195                 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
7196                         break;
7197                 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7198                 tw32(RX_CPU_BASE + CPU_MODE,  CPU_MODE_HALT);
7199                 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
7200                 udelay(1000);
7201         }
7202         if (i >= 5) {
7203                 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
7204                        "to set RX CPU PC, is %08x should be %08x\n",
7205                        tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
7206                        info.fw_base);
7207                 return -ENODEV;
7208         }
7209         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7210         tw32_f(RX_CPU_BASE + CPU_MODE,  0x00000000);
7211
7212         return 0;
7213 }
7214
7215 /* 5705 needs a special version of the TSO firmware.  */
7216
7217 /* tp->lock is held. */
7218 static int tg3_load_tso_firmware(struct tg3 *tp)
7219 {
7220         struct fw_info info;
7221         const __be32 *fw_data;
7222         unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
7223         int err, i;
7224
7225         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7226                 return 0;
7227
7228         fw_data = (void *)tp->fw->data;
7229
7230         /* Firmware blob starts with version numbers, followed by
7231            start address and length. We are setting complete length.
7232            length = end_address_of_bss - start_address_of_text.
7233            Remainder is the blob to be loaded contiguously
7234            from start address. */
7235
7236         info.fw_base = be32_to_cpu(fw_data[1]);
7237         cpu_scratch_size = tp->fw_len;
7238         info.fw_len = tp->fw->size - 12;
7239         info.fw_data = &fw_data[3];
7240
7241         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7242                 cpu_base = RX_CPU_BASE;
7243                 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
7244         } else {
7245                 cpu_base = TX_CPU_BASE;
7246                 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
7247                 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
7248         }
7249
7250         err = tg3_load_firmware_cpu(tp, cpu_base,
7251                                     cpu_scratch_base, cpu_scratch_size,
7252                                     &info);
7253         if (err)
7254                 return err;
7255
7256         /* Now startup the cpu. */
7257         tw32(cpu_base + CPU_STATE, 0xffffffff);
7258         tw32_f(cpu_base + CPU_PC, info.fw_base);
7259
7260         for (i = 0; i < 5; i++) {
7261                 if (tr32(cpu_base + CPU_PC) == info.fw_base)
7262                         break;
7263                 tw32(cpu_base + CPU_STATE, 0xffffffff);
7264                 tw32(cpu_base + CPU_MODE,  CPU_MODE_HALT);
7265                 tw32_f(cpu_base + CPU_PC, info.fw_base);
7266                 udelay(1000);
7267         }
7268         if (i >= 5) {
7269                 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
7270                        "to set CPU PC, is %08x should be %08x\n",
7271                        tp->dev->name, tr32(cpu_base + CPU_PC),
7272                        info.fw_base);
7273                 return -ENODEV;
7274         }
7275         tw32(cpu_base + CPU_STATE, 0xffffffff);
7276         tw32_f(cpu_base + CPU_MODE,  0x00000000);
7277         return 0;
7278 }
7279
7280
7281 static int tg3_set_mac_addr(struct net_device *dev, void *p)
7282 {
7283         struct tg3 *tp = netdev_priv(dev);
7284         struct sockaddr *addr = p;
7285         int err = 0, skip_mac_1 = 0;
7286
7287         if (!is_valid_ether_addr(addr->sa_data))
7288                 return -EINVAL;
7289
7290         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
7291
7292         if (!netif_running(dev))
7293                 return 0;
7294
7295         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
7296                 u32 addr0_high, addr0_low, addr1_high, addr1_low;
7297
7298                 addr0_high = tr32(MAC_ADDR_0_HIGH);
7299                 addr0_low = tr32(MAC_ADDR_0_LOW);
7300                 addr1_high = tr32(MAC_ADDR_1_HIGH);
7301                 addr1_low = tr32(MAC_ADDR_1_LOW);
7302
7303                 /* Skip MAC addr 1 if ASF is using it. */
7304                 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
7305                     !(addr1_high == 0 && addr1_low == 0))
7306                         skip_mac_1 = 1;
7307         }
7308         spin_lock_bh(&tp->lock);
7309         __tg3_set_mac_addr(tp, skip_mac_1);
7310         spin_unlock_bh(&tp->lock);
7311
7312         return err;
7313 }
7314
7315 /* tp->lock is held. */
7316 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
7317                            dma_addr_t mapping, u32 maxlen_flags,
7318                            u32 nic_addr)
7319 {
7320         tg3_write_mem(tp,
7321                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
7322                       ((u64) mapping >> 32));
7323         tg3_write_mem(tp,
7324                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
7325                       ((u64) mapping & 0xffffffff));
7326         tg3_write_mem(tp,
7327                       (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
7328                        maxlen_flags);
7329
7330         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7331                 tg3_write_mem(tp,
7332                               (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
7333                               nic_addr);
7334 }
7335
7336 static void __tg3_set_rx_mode(struct net_device *);
7337 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
7338 {
7339         int i;
7340
7341         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) {
7342                 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
7343                 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
7344                 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
7345         } else {
7346                 tw32(HOSTCC_TXCOL_TICKS, 0);
7347                 tw32(HOSTCC_TXMAX_FRAMES, 0);
7348                 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
7349         }
7350
7351         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
7352                 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
7353                 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
7354                 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
7355         } else {
7356                 tw32(HOSTCC_RXCOL_TICKS, 0);
7357                 tw32(HOSTCC_RXMAX_FRAMES, 0);
7358                 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
7359         }
7360
7361         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7362                 u32 val = ec->stats_block_coalesce_usecs;
7363
7364                 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
7365                 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
7366
7367                 if (!netif_carrier_ok(tp->dev))
7368                         val = 0;
7369
7370                 tw32(HOSTCC_STAT_COAL_TICKS, val);
7371         }
7372
7373         for (i = 0; i < tp->irq_cnt - 1; i++) {
7374                 u32 reg;
7375
7376                 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
7377                 tw32(reg, ec->rx_coalesce_usecs);
7378                 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
7379                 tw32(reg, ec->rx_max_coalesced_frames);
7380                 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
7381                 tw32(reg, ec->rx_max_coalesced_frames_irq);
7382
7383                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7384                         reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
7385                         tw32(reg, ec->tx_coalesce_usecs);
7386                         reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
7387                         tw32(reg, ec->tx_max_coalesced_frames);
7388                         reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
7389                         tw32(reg, ec->tx_max_coalesced_frames_irq);
7390                 }
7391         }
7392
7393         for (; i < tp->irq_max - 1; i++) {
7394                 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
7395                 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
7396                 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7397
7398                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7399                         tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
7400                         tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
7401                         tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7402                 }
7403         }
7404 }
7405
7406 /* tp->lock is held. */
7407 static void tg3_rings_reset(struct tg3 *tp)
7408 {
7409         int i;
7410         u32 stblk, txrcb, rxrcb, limit;
7411         struct tg3_napi *tnapi = &tp->napi[0];
7412
7413         /* Disable all transmit rings but the first. */
7414         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7415                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
7416         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7417                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2;
7418         else
7419                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7420
7421         for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7422              txrcb < limit; txrcb += TG3_BDINFO_SIZE)
7423                 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
7424                               BDINFO_FLAGS_DISABLED);
7425
7426
7427         /* Disable all receive return rings but the first. */
7428         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
7429                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
7430         else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7431                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
7432         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
7433                  GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7434                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
7435         else
7436                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7437
7438         for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7439              rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
7440                 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
7441                               BDINFO_FLAGS_DISABLED);
7442
7443         /* Disable interrupts */
7444         tw32_mailbox_f(tp->napi[0].int_mbox, 1);
7445
7446         /* Zero mailbox registers. */
7447         if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) {
7448                 for (i = 1; i < TG3_IRQ_MAX_VECS; i++) {
7449                         tp->napi[i].tx_prod = 0;
7450                         tp->napi[i].tx_cons = 0;
7451                         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
7452                                 tw32_mailbox(tp->napi[i].prodmbox, 0);
7453                         tw32_rx_mbox(tp->napi[i].consmbox, 0);
7454                         tw32_mailbox_f(tp->napi[i].int_mbox, 1);
7455                 }
7456                 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))
7457                         tw32_mailbox(tp->napi[0].prodmbox, 0);
7458         } else {
7459                 tp->napi[0].tx_prod = 0;
7460                 tp->napi[0].tx_cons = 0;
7461                 tw32_mailbox(tp->napi[0].prodmbox, 0);
7462                 tw32_rx_mbox(tp->napi[0].consmbox, 0);
7463         }
7464
7465         /* Make sure the NIC-based send BD rings are disabled. */
7466         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7467                 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
7468                 for (i = 0; i < 16; i++)
7469                         tw32_tx_mbox(mbox + i * 8, 0);
7470         }
7471
7472         txrcb = NIC_SRAM_SEND_RCB;
7473         rxrcb = NIC_SRAM_RCV_RET_RCB;
7474
7475         /* Clear status block in ram. */
7476         memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7477
7478         /* Set status block DMA address */
7479         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7480              ((u64) tnapi->status_mapping >> 32));
7481         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7482              ((u64) tnapi->status_mapping & 0xffffffff));
7483
7484         if (tnapi->tx_ring) {
7485                 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7486                                (TG3_TX_RING_SIZE <<
7487                                 BDINFO_FLAGS_MAXLEN_SHIFT),
7488                                NIC_SRAM_TX_BUFFER_DESC);
7489                 txrcb += TG3_BDINFO_SIZE;
7490         }
7491
7492         if (tnapi->rx_rcb) {
7493                 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7494                                (TG3_RX_RCB_RING_SIZE(tp) <<
7495                                 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7496                 rxrcb += TG3_BDINFO_SIZE;
7497         }
7498
7499         stblk = HOSTCC_STATBLCK_RING1;
7500
7501         for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
7502                 u64 mapping = (u64)tnapi->status_mapping;
7503                 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
7504                 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
7505
7506                 /* Clear status block in ram. */
7507                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7508
7509                 if (tnapi->tx_ring) {
7510                         tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7511                                        (TG3_TX_RING_SIZE <<
7512                                         BDINFO_FLAGS_MAXLEN_SHIFT),
7513                                        NIC_SRAM_TX_BUFFER_DESC);
7514                         txrcb += TG3_BDINFO_SIZE;
7515                 }
7516
7517                 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7518                                (TG3_RX_RCB_RING_SIZE(tp) <<
7519                                 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7520
7521                 stblk += 8;
7522                 rxrcb += TG3_BDINFO_SIZE;
7523         }
7524 }
7525
7526 /* tp->lock is held. */
7527 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
7528 {
7529         u32 val, rdmac_mode;
7530         int i, err, limit;
7531         struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
7532
7533         tg3_disable_ints(tp);
7534
7535         tg3_stop_fw(tp);
7536
7537         tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
7538
7539         if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
7540                 tg3_abort_hw(tp, 1);
7541         }
7542
7543         if (reset_phy &&
7544             !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB))
7545                 tg3_phy_reset(tp);
7546
7547         err = tg3_chip_reset(tp);
7548         if (err)
7549                 return err;
7550
7551         tg3_write_sig_legacy(tp, RESET_KIND_INIT);
7552
7553         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
7554                 val = tr32(TG3_CPMU_CTRL);
7555                 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
7556                 tw32(TG3_CPMU_CTRL, val);
7557
7558                 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7559                 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7560                 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7561                 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7562
7563                 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
7564                 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
7565                 val |= CPMU_LNK_AWARE_MACCLK_6_25;
7566                 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
7567
7568                 val = tr32(TG3_CPMU_HST_ACC);
7569                 val &= ~CPMU_HST_ACC_MACCLK_MASK;
7570                 val |= CPMU_HST_ACC_MACCLK_6_25;
7571                 tw32(TG3_CPMU_HST_ACC, val);
7572         }
7573
7574         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7575                 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
7576                 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
7577                        PCIE_PWR_MGMT_L1_THRESH_4MS;
7578                 tw32(PCIE_PWR_MGMT_THRESH, val);
7579
7580                 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
7581                 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
7582
7583                 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
7584
7585                 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
7586                 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
7587         }
7588
7589         if (tp->tg3_flags3 & TG3_FLG3_L1PLLPD_EN) {
7590                 u32 grc_mode = tr32(GRC_MODE);
7591
7592                 /* Access the lower 1K of PL PCIE block registers. */
7593                 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
7594                 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
7595
7596                 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1);
7597                 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1,
7598                      val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN);
7599
7600                 tw32(GRC_MODE, grc_mode);
7601         }
7602
7603         /* This works around an issue with Athlon chipsets on
7604          * B3 tigon3 silicon.  This bit has no effect on any
7605          * other revision.  But do not set this on PCI Express
7606          * chips and don't even touch the clocks if the CPMU is present.
7607          */
7608         if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
7609                 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
7610                         tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
7611                 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7612         }
7613
7614         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
7615             (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
7616                 val = tr32(TG3PCI_PCISTATE);
7617                 val |= PCISTATE_RETRY_SAME_DMA;
7618                 tw32(TG3PCI_PCISTATE, val);
7619         }
7620
7621         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
7622                 /* Allow reads and writes to the
7623                  * APE register and memory space.
7624                  */
7625                 val = tr32(TG3PCI_PCISTATE);
7626                 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
7627                        PCISTATE_ALLOW_APE_SHMEM_WR;
7628                 tw32(TG3PCI_PCISTATE, val);
7629         }
7630
7631         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
7632                 /* Enable some hw fixes.  */
7633                 val = tr32(TG3PCI_MSI_DATA);
7634                 val |= (1 << 26) | (1 << 28) | (1 << 29);
7635                 tw32(TG3PCI_MSI_DATA, val);
7636         }
7637
7638         /* Descriptor ring init may make accesses to the
7639          * NIC SRAM area to setup the TX descriptors, so we
7640          * can only do this after the hardware has been
7641          * successfully reset.
7642          */
7643         err = tg3_init_rings(tp);
7644         if (err)
7645                 return err;
7646
7647         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7648             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
7649                 val = tr32(TG3PCI_DMA_RW_CTRL) &
7650                       ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
7651                 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
7652         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
7653                    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
7654                 /* This value is determined during the probe time DMA
7655                  * engine test, tg3_test_dma.
7656                  */
7657                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
7658         }
7659
7660         tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
7661                           GRC_MODE_4X_NIC_SEND_RINGS |
7662                           GRC_MODE_NO_TX_PHDR_CSUM |
7663                           GRC_MODE_NO_RX_PHDR_CSUM);
7664         tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
7665
7666         /* Pseudo-header checksum is done by hardware logic and not
7667          * the offload processers, so make the chip do the pseudo-
7668          * header checksums on receive.  For transmit it is more
7669          * convenient to do the pseudo-header checksum in software
7670          * as Linux does that on transmit for us in all cases.
7671          */
7672         tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
7673
7674         tw32(GRC_MODE,
7675              tp->grc_mode |
7676              (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
7677
7678         /* Setup the timer prescalar register.  Clock is always 66Mhz. */
7679         val = tr32(GRC_MISC_CFG);
7680         val &= ~0xff;
7681         val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
7682         tw32(GRC_MISC_CFG, val);
7683
7684         /* Initialize MBUF/DESC pool. */
7685         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7686                 /* Do nothing.  */
7687         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
7688                 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
7689                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
7690                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
7691                 else
7692                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
7693                 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
7694                 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
7695         }
7696         else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7697                 int fw_len;
7698
7699                 fw_len = tp->fw_len;
7700                 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
7701                 tw32(BUFMGR_MB_POOL_ADDR,
7702                      NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
7703                 tw32(BUFMGR_MB_POOL_SIZE,
7704                      NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
7705         }
7706
7707         if (tp->dev->mtu <= ETH_DATA_LEN) {
7708                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7709                      tp->bufmgr_config.mbuf_read_dma_low_water);
7710                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7711                      tp->bufmgr_config.mbuf_mac_rx_low_water);
7712                 tw32(BUFMGR_MB_HIGH_WATER,
7713                      tp->bufmgr_config.mbuf_high_water);
7714         } else {
7715                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7716                      tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
7717                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7718                      tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
7719                 tw32(BUFMGR_MB_HIGH_WATER,
7720                      tp->bufmgr_config.mbuf_high_water_jumbo);
7721         }
7722         tw32(BUFMGR_DMA_LOW_WATER,
7723              tp->bufmgr_config.dma_low_water);
7724         tw32(BUFMGR_DMA_HIGH_WATER,
7725              tp->bufmgr_config.dma_high_water);
7726
7727         tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
7728         for (i = 0; i < 2000; i++) {
7729                 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
7730                         break;
7731                 udelay(10);
7732         }
7733         if (i >= 2000) {
7734                 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
7735                        tp->dev->name);
7736                 return -ENODEV;
7737         }
7738
7739         /* Setup replenish threshold. */
7740         val = tp->rx_pending / 8;
7741         if (val == 0)
7742                 val = 1;
7743         else if (val > tp->rx_std_max_post)
7744                 val = tp->rx_std_max_post;
7745         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7746                 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
7747                         tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
7748
7749                 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
7750                         val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
7751         }
7752
7753         tw32(RCVBDI_STD_THRESH, val);
7754
7755         /* Initialize TG3_BDINFO's at:
7756          *  RCVDBDI_STD_BD:     standard eth size rx ring
7757          *  RCVDBDI_JUMBO_BD:   jumbo frame rx ring
7758          *  RCVDBDI_MINI_BD:    small frame rx ring (??? does not work)
7759          *
7760          * like so:
7761          *  TG3_BDINFO_HOST_ADDR:       high/low parts of DMA address of ring
7762          *  TG3_BDINFO_MAXLEN_FLAGS:    (rx max buffer size << 16) |
7763          *                              ring attribute flags
7764          *  TG3_BDINFO_NIC_ADDR:        location of descriptors in nic SRAM
7765          *
7766          * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
7767          * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
7768          *
7769          * The size of each ring is fixed in the firmware, but the location is
7770          * configurable.
7771          */
7772         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7773              ((u64) tpr->rx_std_mapping >> 32));
7774         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7775              ((u64) tpr->rx_std_mapping & 0xffffffff));
7776         if (!(tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
7777                 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
7778                      NIC_SRAM_RX_BUFFER_DESC);
7779
7780         /* Disable the mini ring */
7781         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7782                 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
7783                      BDINFO_FLAGS_DISABLED);
7784
7785         /* Program the jumbo buffer descriptor ring control
7786          * blocks on those devices that have them.
7787          */
7788         if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
7789             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
7790                 /* Setup replenish threshold. */
7791                 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
7792
7793                 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
7794                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7795                              ((u64) tpr->rx_jmb_mapping >> 32));
7796                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7797                              ((u64) tpr->rx_jmb_mapping & 0xffffffff));
7798                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7799                              (RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT) |
7800                              BDINFO_FLAGS_USE_EXT_RECV);
7801                         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717)
7802                                 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
7803                                      NIC_SRAM_RX_JUMBO_BUFFER_DESC);
7804                 } else {
7805                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7806                              BDINFO_FLAGS_DISABLED);
7807                 }
7808
7809                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7810                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7811                         val = (RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT) |
7812                               (RX_STD_MAX_SIZE << 2);
7813                 else
7814                         val = RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT;
7815         } else
7816                 val = RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT;
7817
7818         tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
7819
7820         tpr->rx_std_prod_idx = tp->rx_pending;
7821         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx);
7822
7823         tpr->rx_jmb_prod_idx = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
7824                           tp->rx_jumbo_pending : 0;
7825         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx);
7826
7827         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7828             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
7829                 tw32(STD_REPLENISH_LWM, 32);
7830                 tw32(JMB_REPLENISH_LWM, 16);
7831         }
7832
7833         tg3_rings_reset(tp);
7834
7835         /* Initialize MAC address and backoff seed. */
7836         __tg3_set_mac_addr(tp, 0);
7837
7838         /* MTU + ethernet header + FCS + optional VLAN tag */
7839         tw32(MAC_RX_MTU_SIZE,
7840              tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
7841
7842         /* The slot time is changed by tg3_setup_phy if we
7843          * run at gigabit with half duplex.
7844          */
7845         tw32(MAC_TX_LENGTHS,
7846              (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
7847              (6 << TX_LENGTHS_IPG_SHIFT) |
7848              (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
7849
7850         /* Receive rules. */
7851         tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
7852         tw32(RCVLPC_CONFIG, 0x0181);
7853
7854         /* Calculate RDMAC_MODE setting early, we need it to determine
7855          * the RCVLPC_STATE_ENABLE mask.
7856          */
7857         rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
7858                       RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
7859                       RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
7860                       RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
7861                       RDMAC_MODE_LNGREAD_ENAB);
7862
7863         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
7864             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7865             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7866                 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
7867                               RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
7868                               RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
7869
7870         /* If statement applies to 5705 and 5750 PCI devices only */
7871         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7872              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7873             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
7874                 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
7875                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7876                         rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
7877                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7878                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
7879                         rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7880                 }
7881         }
7882
7883         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
7884                 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7885
7886         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7887                 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
7888
7889         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
7890             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7891             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7892                 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
7893
7894         /* Receive/send statistics. */
7895         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7896                 val = tr32(RCVLPC_STATS_ENABLE);
7897                 val &= ~RCVLPC_STATSENAB_DACK_FIX;
7898                 tw32(RCVLPC_STATS_ENABLE, val);
7899         } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
7900                    (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
7901                 val = tr32(RCVLPC_STATS_ENABLE);
7902                 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
7903                 tw32(RCVLPC_STATS_ENABLE, val);
7904         } else {
7905                 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
7906         }
7907         tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
7908         tw32(SNDDATAI_STATSENAB, 0xffffff);
7909         tw32(SNDDATAI_STATSCTRL,
7910              (SNDDATAI_SCTRL_ENABLE |
7911               SNDDATAI_SCTRL_FASTUPD));
7912
7913         /* Setup host coalescing engine. */
7914         tw32(HOSTCC_MODE, 0);
7915         for (i = 0; i < 2000; i++) {
7916                 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
7917                         break;
7918                 udelay(10);
7919         }
7920
7921         __tg3_set_coalesce(tp, &tp->coal);
7922
7923         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7924                 /* Status/statistics block address.  See tg3_timer,
7925                  * the tg3_periodic_fetch_stats call there, and
7926                  * tg3_get_stats to see how this works for 5705/5750 chips.
7927                  */
7928                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7929                      ((u64) tp->stats_mapping >> 32));
7930                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7931                      ((u64) tp->stats_mapping & 0xffffffff));
7932                 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
7933
7934                 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
7935
7936                 /* Clear statistics and status block memory areas */
7937                 for (i = NIC_SRAM_STATS_BLK;
7938                      i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
7939                      i += sizeof(u32)) {
7940                         tg3_write_mem(tp, i, 0);
7941                         udelay(40);
7942                 }
7943         }
7944
7945         tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
7946
7947         tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
7948         tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
7949         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7950                 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
7951
7952         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
7953                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
7954                 /* reset to prevent losing 1st rx packet intermittently */
7955                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7956                 udelay(10);
7957         }
7958
7959         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7960                 tp->mac_mode &= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
7961         else
7962                 tp->mac_mode = 0;
7963         tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
7964                 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
7965         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7966             !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7967             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
7968                 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
7969         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
7970         udelay(40);
7971
7972         /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
7973          * If TG3_FLG2_IS_NIC is zero, we should read the
7974          * register to preserve the GPIO settings for LOMs. The GPIOs,
7975          * whether used as inputs or outputs, are set by boot code after
7976          * reset.
7977          */
7978         if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
7979                 u32 gpio_mask;
7980
7981                 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
7982                             GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
7983                             GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
7984
7985                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
7986                         gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
7987                                      GRC_LCLCTRL_GPIO_OUTPUT3;
7988
7989                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
7990                         gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
7991
7992                 tp->grc_local_ctrl &= ~gpio_mask;
7993                 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
7994
7995                 /* GPIO1 must be driven high for eeprom write protect */
7996                 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
7997                         tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
7998                                                GRC_LCLCTRL_GPIO_OUTPUT1);
7999         }
8000         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8001         udelay(100);
8002
8003         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX) {
8004                 val = tr32(MSGINT_MODE);
8005                 val |= MSGINT_MODE_MULTIVEC_EN | MSGINT_MODE_ENABLE;
8006                 tw32(MSGINT_MODE, val);
8007         }
8008
8009         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
8010                 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
8011                 udelay(40);
8012         }
8013
8014         val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
8015                WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
8016                WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
8017                WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
8018                WDMAC_MODE_LNGREAD_ENAB);
8019
8020         /* If statement applies to 5705 and 5750 PCI devices only */
8021         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
8022              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
8023             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
8024                 if ((tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
8025                     (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
8026                      tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
8027                         /* nothing */
8028                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
8029                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
8030                            !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
8031                         val |= WDMAC_MODE_RX_ACCEL;
8032                 }
8033         }
8034
8035         /* Enable host coalescing bug fix */
8036         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
8037                 val |= WDMAC_MODE_STATUS_TAG_FIX;
8038
8039         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
8040                 val |= WDMAC_MODE_BURST_ALL_DATA;
8041
8042         tw32_f(WDMAC_MODE, val);
8043         udelay(40);
8044
8045         if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
8046                 u16 pcix_cmd;
8047
8048                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8049                                      &pcix_cmd);
8050                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
8051                         pcix_cmd &= ~PCI_X_CMD_MAX_READ;
8052                         pcix_cmd |= PCI_X_CMD_READ_2K;
8053                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
8054                         pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
8055                         pcix_cmd |= PCI_X_CMD_READ_2K;
8056                 }
8057                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8058                                       pcix_cmd);
8059         }
8060
8061         tw32_f(RDMAC_MODE, rdmac_mode);
8062         udelay(40);
8063
8064         tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
8065         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8066                 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
8067
8068         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
8069                 tw32(SNDDATAC_MODE,
8070                      SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
8071         else
8072                 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
8073
8074         tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
8075         tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
8076         tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
8077         tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
8078         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
8079                 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
8080         val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
8081         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
8082                 val |= SNDBDI_MODE_MULTI_TXQ_EN;
8083         tw32(SNDBDI_MODE, val);
8084         tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
8085
8086         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8087                 err = tg3_load_5701_a0_firmware_fix(tp);
8088                 if (err)
8089                         return err;
8090         }
8091
8092         if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
8093                 err = tg3_load_tso_firmware(tp);
8094                 if (err)
8095                         return err;
8096         }
8097
8098         tp->tx_mode = TX_MODE_ENABLE;
8099         tw32_f(MAC_TX_MODE, tp->tx_mode);
8100         udelay(100);
8101
8102         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) {
8103                 u32 reg = MAC_RSS_INDIR_TBL_0;
8104                 u8 *ent = (u8 *)&val;
8105
8106                 /* Setup the indirection table */
8107                 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
8108                         int idx = i % sizeof(val);
8109
8110                         ent[idx] = i % (tp->irq_cnt - 1);
8111                         if (idx == sizeof(val) - 1) {
8112                                 tw32(reg, val);
8113                                 reg += 4;
8114                         }
8115                 }
8116
8117                 /* Setup the "secret" hash key. */
8118                 tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
8119                 tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
8120                 tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
8121                 tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
8122                 tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
8123                 tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
8124                 tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
8125                 tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
8126                 tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
8127                 tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
8128         }
8129
8130         tp->rx_mode = RX_MODE_ENABLE;
8131         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
8132                 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
8133
8134         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)
8135                 tp->rx_mode |= RX_MODE_RSS_ENABLE |
8136                                RX_MODE_RSS_ITBL_HASH_BITS_7 |
8137                                RX_MODE_RSS_IPV6_HASH_EN |
8138                                RX_MODE_RSS_TCP_IPV6_HASH_EN |
8139                                RX_MODE_RSS_IPV4_HASH_EN |
8140                                RX_MODE_RSS_TCP_IPV4_HASH_EN;
8141
8142         tw32_f(MAC_RX_MODE, tp->rx_mode);
8143         udelay(10);
8144
8145         tw32(MAC_LED_CTRL, tp->led_ctrl);
8146
8147         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
8148         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
8149                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8150                 udelay(10);
8151         }
8152         tw32_f(MAC_RX_MODE, tp->rx_mode);
8153         udelay(10);
8154
8155         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
8156                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
8157                         !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
8158                         /* Set drive transmission level to 1.2V  */
8159                         /* only if the signal pre-emphasis bit is not set  */
8160                         val = tr32(MAC_SERDES_CFG);
8161                         val &= 0xfffff000;
8162                         val |= 0x880;
8163                         tw32(MAC_SERDES_CFG, val);
8164                 }
8165                 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
8166                         tw32(MAC_SERDES_CFG, 0x616000);
8167         }
8168
8169         /* Prevent chip from dropping frames when flow control
8170          * is enabled.
8171          */
8172         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
8173                 val = 1;
8174         else
8175                 val = 2;
8176         tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val);
8177
8178         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
8179             (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
8180                 /* Use hardware link auto-negotiation */
8181                 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
8182         }
8183
8184         if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
8185             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
8186                 u32 tmp;
8187
8188                 tmp = tr32(SERDES_RX_CTRL);
8189                 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
8190                 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
8191                 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
8192                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8193         }
8194
8195         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
8196                 if (tp->link_config.phy_is_low_power) {
8197                         tp->link_config.phy_is_low_power = 0;
8198                         tp->link_config.speed = tp->link_config.orig_speed;
8199                         tp->link_config.duplex = tp->link_config.orig_duplex;
8200                         tp->link_config.autoneg = tp->link_config.orig_autoneg;
8201                 }
8202
8203                 err = tg3_setup_phy(tp, 0);
8204                 if (err)
8205                         return err;
8206
8207                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
8208                     !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)) {
8209                         u32 tmp;
8210
8211                         /* Clear CRC stats. */
8212                         if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
8213                                 tg3_writephy(tp, MII_TG3_TEST1,
8214                                              tmp | MII_TG3_TEST1_CRC_EN);
8215                                 tg3_readphy(tp, 0x14, &tmp);
8216                         }
8217                 }
8218         }
8219
8220         __tg3_set_rx_mode(tp->dev);
8221
8222         /* Initialize receive rules. */
8223         tw32(MAC_RCV_RULE_0,  0xc2000000 & RCV_RULE_DISABLE_MASK);
8224         tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
8225         tw32(MAC_RCV_RULE_1,  0x86000004 & RCV_RULE_DISABLE_MASK);
8226         tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
8227
8228         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
8229             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
8230                 limit = 8;
8231         else
8232                 limit = 16;
8233         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
8234                 limit -= 4;
8235         switch (limit) {
8236         case 16:
8237                 tw32(MAC_RCV_RULE_15,  0); tw32(MAC_RCV_VALUE_15,  0);
8238         case 15:
8239                 tw32(MAC_RCV_RULE_14,  0); tw32(MAC_RCV_VALUE_14,  0);
8240         case 14:
8241                 tw32(MAC_RCV_RULE_13,  0); tw32(MAC_RCV_VALUE_13,  0);
8242         case 13:
8243                 tw32(MAC_RCV_RULE_12,  0); tw32(MAC_RCV_VALUE_12,  0);
8244         case 12:
8245                 tw32(MAC_RCV_RULE_11,  0); tw32(MAC_RCV_VALUE_11,  0);
8246         case 11:
8247                 tw32(MAC_RCV_RULE_10,  0); tw32(MAC_RCV_VALUE_10,  0);
8248         case 10:
8249                 tw32(MAC_RCV_RULE_9,  0); tw32(MAC_RCV_VALUE_9,  0);
8250         case 9:
8251                 tw32(MAC_RCV_RULE_8,  0); tw32(MAC_RCV_VALUE_8,  0);
8252         case 8:
8253                 tw32(MAC_RCV_RULE_7,  0); tw32(MAC_RCV_VALUE_7,  0);
8254         case 7:
8255                 tw32(MAC_RCV_RULE_6,  0); tw32(MAC_RCV_VALUE_6,  0);
8256         case 6:
8257                 tw32(MAC_RCV_RULE_5,  0); tw32(MAC_RCV_VALUE_5,  0);
8258         case 5:
8259                 tw32(MAC_RCV_RULE_4,  0); tw32(MAC_RCV_VALUE_4,  0);
8260         case 4:
8261                 /* tw32(MAC_RCV_RULE_3,  0); tw32(MAC_RCV_VALUE_3,  0); */
8262         case 3:
8263                 /* tw32(MAC_RCV_RULE_2,  0); tw32(MAC_RCV_VALUE_2,  0); */
8264         case 2:
8265         case 1:
8266
8267         default:
8268                 break;
8269         }
8270
8271         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
8272                 /* Write our heartbeat update interval to APE. */
8273                 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
8274                                 APE_HOST_HEARTBEAT_INT_DISABLE);
8275
8276         tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
8277
8278         return 0;
8279 }
8280
8281 /* Called at device open time to get the chip ready for
8282  * packet processing.  Invoked with tp->lock held.
8283  */
8284 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
8285 {
8286         tg3_switch_clocks(tp);
8287
8288         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
8289
8290         return tg3_reset_hw(tp, reset_phy);
8291 }
8292
8293 #define TG3_STAT_ADD32(PSTAT, REG) \
8294 do {    u32 __val = tr32(REG); \
8295         (PSTAT)->low += __val; \
8296         if ((PSTAT)->low < __val) \
8297                 (PSTAT)->high += 1; \
8298 } while (0)
8299
8300 static void tg3_periodic_fetch_stats(struct tg3 *tp)
8301 {
8302         struct tg3_hw_stats *sp = tp->hw_stats;
8303
8304         if (!netif_carrier_ok(tp->dev))
8305                 return;
8306
8307         TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
8308         TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
8309         TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
8310         TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
8311         TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
8312         TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
8313         TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
8314         TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
8315         TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
8316         TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
8317         TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
8318         TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
8319         TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
8320
8321         TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
8322         TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
8323         TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
8324         TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
8325         TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
8326         TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
8327         TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
8328         TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
8329         TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
8330         TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
8331         TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
8332         TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
8333         TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
8334         TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
8335
8336         TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
8337         TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
8338         TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
8339 }
8340
8341 static void tg3_timer(unsigned long __opaque)
8342 {
8343         struct tg3 *tp = (struct tg3 *) __opaque;
8344
8345         if (tp->irq_sync)
8346                 goto restart_timer;
8347
8348         spin_lock(&tp->lock);
8349
8350         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8351                 /* All of this garbage is because when using non-tagged
8352                  * IRQ status the mailbox/status_block protocol the chip
8353                  * uses with the cpu is race prone.
8354                  */
8355                 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
8356                         tw32(GRC_LOCAL_CTRL,
8357                              tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
8358                 } else {
8359                         tw32(HOSTCC_MODE, tp->coalesce_mode |
8360                              HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
8361                 }
8362
8363                 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
8364                         tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
8365                         spin_unlock(&tp->lock);
8366                         schedule_work(&tp->reset_task);
8367                         return;
8368                 }
8369         }
8370
8371         /* This part only runs once per second. */
8372         if (!--tp->timer_counter) {
8373                 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
8374                         tg3_periodic_fetch_stats(tp);
8375
8376                 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
8377                         u32 mac_stat;
8378                         int phy_event;
8379
8380                         mac_stat = tr32(MAC_STATUS);
8381
8382                         phy_event = 0;
8383                         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
8384                                 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
8385                                         phy_event = 1;
8386                         } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
8387                                 phy_event = 1;
8388
8389                         if (phy_event)
8390                                 tg3_setup_phy(tp, 0);
8391                 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
8392                         u32 mac_stat = tr32(MAC_STATUS);
8393                         int need_setup = 0;
8394
8395                         if (netif_carrier_ok(tp->dev) &&
8396                             (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
8397                                 need_setup = 1;
8398                         }
8399                         if (! netif_carrier_ok(tp->dev) &&
8400                             (mac_stat & (MAC_STATUS_PCS_SYNCED |
8401                                          MAC_STATUS_SIGNAL_DET))) {
8402                                 need_setup = 1;
8403                         }
8404                         if (need_setup) {
8405                                 if (!tp->serdes_counter) {
8406                                         tw32_f(MAC_MODE,
8407                                              (tp->mac_mode &
8408                                               ~MAC_MODE_PORT_MODE_MASK));
8409                                         udelay(40);
8410                                         tw32_f(MAC_MODE, tp->mac_mode);
8411                                         udelay(40);
8412                                 }
8413                                 tg3_setup_phy(tp, 0);
8414                         }
8415                 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
8416                         tg3_serdes_parallel_detect(tp);
8417
8418                 tp->timer_counter = tp->timer_multiplier;
8419         }
8420
8421         /* Heartbeat is only sent once every 2 seconds.
8422          *
8423          * The heartbeat is to tell the ASF firmware that the host
8424          * driver is still alive.  In the event that the OS crashes,
8425          * ASF needs to reset the hardware to free up the FIFO space
8426          * that may be filled with rx packets destined for the host.
8427          * If the FIFO is full, ASF will no longer function properly.
8428          *
8429          * Unintended resets have been reported on real time kernels
8430          * where the timer doesn't run on time.  Netpoll will also have
8431          * same problem.
8432          *
8433          * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
8434          * to check the ring condition when the heartbeat is expiring
8435          * before doing the reset.  This will prevent most unintended
8436          * resets.
8437          */
8438         if (!--tp->asf_counter) {
8439                 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
8440                     !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
8441                         tg3_wait_for_event_ack(tp);
8442
8443                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
8444                                       FWCMD_NICDRV_ALIVE3);
8445                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
8446                         /* 5 seconds timeout */
8447                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
8448
8449                         tg3_generate_fw_event(tp);
8450                 }
8451                 tp->asf_counter = tp->asf_multiplier;
8452         }
8453
8454         spin_unlock(&tp->lock);
8455
8456 restart_timer:
8457         tp->timer.expires = jiffies + tp->timer_offset;
8458         add_timer(&tp->timer);
8459 }
8460
8461 static int tg3_request_irq(struct tg3 *tp, int irq_num)
8462 {
8463         irq_handler_t fn;
8464         unsigned long flags;
8465         char *name;
8466         struct tg3_napi *tnapi = &tp->napi[irq_num];
8467
8468         if (tp->irq_cnt == 1)
8469                 name = tp->dev->name;
8470         else {
8471                 name = &tnapi->irq_lbl[0];
8472                 snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num);
8473                 name[IFNAMSIZ-1] = 0;
8474         }
8475
8476         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8477                 fn = tg3_msi;
8478                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
8479                         fn = tg3_msi_1shot;
8480                 flags = IRQF_SAMPLE_RANDOM;
8481         } else {
8482                 fn = tg3_interrupt;
8483                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8484                         fn = tg3_interrupt_tagged;
8485                 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
8486         }
8487
8488         return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
8489 }
8490
8491 static int tg3_test_interrupt(struct tg3 *tp)
8492 {
8493         struct tg3_napi *tnapi = &tp->napi[0];
8494         struct net_device *dev = tp->dev;
8495         int err, i, intr_ok = 0;
8496         u32 val;
8497
8498         if (!netif_running(dev))
8499                 return -ENODEV;
8500
8501         tg3_disable_ints(tp);
8502
8503         free_irq(tnapi->irq_vec, tnapi);
8504
8505         /*
8506          * Turn off MSI one shot mode.  Otherwise this test has no
8507          * observable way to know whether the interrupt was delivered.
8508          */
8509         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
8510              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) &&
8511             (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8512                 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
8513                 tw32(MSGINT_MODE, val);
8514         }
8515
8516         err = request_irq(tnapi->irq_vec, tg3_test_isr,
8517                           IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi);
8518         if (err)
8519                 return err;
8520
8521         tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
8522         tg3_enable_ints(tp);
8523
8524         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8525                tnapi->coal_now);
8526
8527         for (i = 0; i < 5; i++) {
8528                 u32 int_mbox, misc_host_ctrl;
8529
8530                 int_mbox = tr32_mailbox(tnapi->int_mbox);
8531                 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
8532
8533                 if ((int_mbox != 0) ||
8534                     (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
8535                         intr_ok = 1;
8536                         break;
8537                 }
8538
8539                 msleep(10);
8540         }
8541
8542         tg3_disable_ints(tp);
8543
8544         free_irq(tnapi->irq_vec, tnapi);
8545
8546         err = tg3_request_irq(tp, 0);
8547
8548         if (err)
8549                 return err;
8550
8551         if (intr_ok) {
8552                 /* Reenable MSI one shot mode. */
8553                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
8554                      GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) &&
8555                     (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8556                         val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
8557                         tw32(MSGINT_MODE, val);
8558                 }
8559                 return 0;
8560         }
8561
8562         return -EIO;
8563 }
8564
8565 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
8566  * successfully restored
8567  */
8568 static int tg3_test_msi(struct tg3 *tp)
8569 {
8570         int err;
8571         u16 pci_cmd;
8572
8573         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
8574                 return 0;
8575
8576         /* Turn off SERR reporting in case MSI terminates with Master
8577          * Abort.
8578          */
8579         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
8580         pci_write_config_word(tp->pdev, PCI_COMMAND,
8581                               pci_cmd & ~PCI_COMMAND_SERR);
8582
8583         err = tg3_test_interrupt(tp);
8584
8585         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
8586
8587         if (!err)
8588                 return 0;
8589
8590         /* other failures */
8591         if (err != -EIO)
8592                 return err;
8593
8594         /* MSI test failed, go back to INTx mode */
8595         printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
8596                "switching to INTx mode. Please report this failure to "
8597                "the PCI maintainer and include system chipset information.\n",
8598                        tp->dev->name);
8599
8600         free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8601
8602         pci_disable_msi(tp->pdev);
8603
8604         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8605
8606         err = tg3_request_irq(tp, 0);
8607         if (err)
8608                 return err;
8609
8610         /* Need to reset the chip because the MSI cycle may have terminated
8611          * with Master Abort.
8612          */
8613         tg3_full_lock(tp, 1);
8614
8615         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8616         err = tg3_init_hw(tp, 1);
8617
8618         tg3_full_unlock(tp);
8619
8620         if (err)
8621                 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8622
8623         return err;
8624 }
8625
8626 static int tg3_request_firmware(struct tg3 *tp)
8627 {
8628         const __be32 *fw_data;
8629
8630         if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
8631                 printk(KERN_ERR "%s: Failed to load firmware \"%s\"\n",
8632                        tp->dev->name, tp->fw_needed);
8633                 return -ENOENT;
8634         }
8635
8636         fw_data = (void *)tp->fw->data;
8637
8638         /* Firmware blob starts with version numbers, followed by
8639          * start address and _full_ length including BSS sections
8640          * (which must be longer than the actual data, of course
8641          */
8642
8643         tp->fw_len = be32_to_cpu(fw_data[2]);   /* includes bss */
8644         if (tp->fw_len < (tp->fw->size - 12)) {
8645                 printk(KERN_ERR "%s: bogus length %d in \"%s\"\n",
8646                        tp->dev->name, tp->fw_len, tp->fw_needed);
8647                 release_firmware(tp->fw);
8648                 tp->fw = NULL;
8649                 return -EINVAL;
8650         }
8651
8652         /* We no longer need firmware; we have it. */
8653         tp->fw_needed = NULL;
8654         return 0;
8655 }
8656
8657 static bool tg3_enable_msix(struct tg3 *tp)
8658 {
8659         int i, rc, cpus = num_online_cpus();
8660         struct msix_entry msix_ent[tp->irq_max];
8661
8662         if (cpus == 1)
8663                 /* Just fallback to the simpler MSI mode. */
8664                 return false;
8665
8666         /*
8667          * We want as many rx rings enabled as there are cpus.
8668          * The first MSIX vector only deals with link interrupts, etc,
8669          * so we add one to the number of vectors we are requesting.
8670          */
8671         tp->irq_cnt = min_t(unsigned, cpus + 1, tp->irq_max);
8672
8673         for (i = 0; i < tp->irq_max; i++) {
8674                 msix_ent[i].entry  = i;
8675                 msix_ent[i].vector = 0;
8676         }
8677
8678         rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
8679         if (rc != 0) {
8680                 if (rc < TG3_RSS_MIN_NUM_MSIX_VECS)
8681                         return false;
8682                 if (pci_enable_msix(tp->pdev, msix_ent, rc))
8683                         return false;
8684                 printk(KERN_NOTICE
8685                        "%s: Requested %d MSI-X vectors, received %d\n",
8686                        tp->dev->name, tp->irq_cnt, rc);
8687                 tp->irq_cnt = rc;
8688         }
8689
8690         tp->tg3_flags3 |= TG3_FLG3_ENABLE_RSS;
8691
8692         for (i = 0; i < tp->irq_max; i++)
8693                 tp->napi[i].irq_vec = msix_ent[i].vector;
8694
8695         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
8696                 tp->tg3_flags3 |= TG3_FLG3_ENABLE_TSS;
8697                 tp->dev->real_num_tx_queues = tp->irq_cnt - 1;
8698         } else
8699                 tp->dev->real_num_tx_queues = 1;
8700
8701         return true;
8702 }
8703
8704 static void tg3_ints_init(struct tg3 *tp)
8705 {
8706         if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI_OR_MSIX) &&
8707             !(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8708                 /* All MSI supporting chips should support tagged
8709                  * status.  Assert that this is the case.
8710                  */
8711                 printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
8712                        "Not using MSI.\n", tp->dev->name);
8713                 goto defcfg;
8714         }
8715
8716         if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) && tg3_enable_msix(tp))
8717                 tp->tg3_flags2 |= TG3_FLG2_USING_MSIX;
8718         else if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) &&
8719                  pci_enable_msi(tp->pdev) == 0)
8720                 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
8721
8722         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8723                 u32 msi_mode = tr32(MSGINT_MODE);
8724                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8725                         msi_mode |= MSGINT_MODE_MULTIVEC_EN;
8726                 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
8727         }
8728 defcfg:
8729         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
8730                 tp->irq_cnt = 1;
8731                 tp->napi[0].irq_vec = tp->pdev->irq;
8732                 tp->dev->real_num_tx_queues = 1;
8733         }
8734 }
8735
8736 static void tg3_ints_fini(struct tg3 *tp)
8737 {
8738         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8739                 pci_disable_msix(tp->pdev);
8740         else if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
8741                 pci_disable_msi(tp->pdev);
8742         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI_OR_MSIX;
8743         tp->tg3_flags3 &= ~TG3_FLG3_ENABLE_RSS;
8744 }
8745
8746 static int tg3_open(struct net_device *dev)
8747 {
8748         struct tg3 *tp = netdev_priv(dev);
8749         int i, err;
8750
8751         if (tp->fw_needed) {
8752                 err = tg3_request_firmware(tp);
8753                 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8754                         if (err)
8755                                 return err;
8756                 } else if (err) {
8757                         printk(KERN_WARNING "%s: TSO capability disabled.\n",
8758                                tp->dev->name);
8759                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
8760                 } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8761                         printk(KERN_NOTICE "%s: TSO capability restored.\n",
8762                                tp->dev->name);
8763                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
8764                 }
8765         }
8766
8767         netif_carrier_off(tp->dev);
8768
8769         err = tg3_set_power_state(tp, PCI_D0);
8770         if (err)
8771                 return err;
8772
8773         tg3_full_lock(tp, 0);
8774
8775         tg3_disable_ints(tp);
8776         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
8777
8778         tg3_full_unlock(tp);
8779
8780         /*
8781          * Setup interrupts first so we know how
8782          * many NAPI resources to allocate
8783          */
8784         tg3_ints_init(tp);
8785
8786         /* The placement of this call is tied
8787          * to the setup and use of Host TX descriptors.
8788          */
8789         err = tg3_alloc_consistent(tp);
8790         if (err)
8791                 goto err_out1;
8792
8793         tg3_napi_enable(tp);
8794
8795         for (i = 0; i < tp->irq_cnt; i++) {
8796                 struct tg3_napi *tnapi = &tp->napi[i];
8797                 err = tg3_request_irq(tp, i);
8798                 if (err) {
8799                         for (i--; i >= 0; i--)
8800                                 free_irq(tnapi->irq_vec, tnapi);
8801                         break;
8802                 }
8803         }
8804
8805         if (err)
8806                 goto err_out2;
8807
8808         tg3_full_lock(tp, 0);
8809
8810         err = tg3_init_hw(tp, 1);
8811         if (err) {
8812                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8813                 tg3_free_rings(tp);
8814         } else {
8815                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8816                         tp->timer_offset = HZ;
8817                 else
8818                         tp->timer_offset = HZ / 10;
8819
8820                 BUG_ON(tp->timer_offset > HZ);
8821                 tp->timer_counter = tp->timer_multiplier =
8822                         (HZ / tp->timer_offset);
8823                 tp->asf_counter = tp->asf_multiplier =
8824                         ((HZ / tp->timer_offset) * 2);
8825
8826                 init_timer(&tp->timer);
8827                 tp->timer.expires = jiffies + tp->timer_offset;
8828                 tp->timer.data = (unsigned long) tp;
8829                 tp->timer.function = tg3_timer;
8830         }
8831
8832         tg3_full_unlock(tp);
8833
8834         if (err)
8835                 goto err_out3;
8836
8837         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8838                 err = tg3_test_msi(tp);
8839
8840                 if (err) {
8841                         tg3_full_lock(tp, 0);
8842                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8843                         tg3_free_rings(tp);
8844                         tg3_full_unlock(tp);
8845
8846                         goto err_out2;
8847                 }
8848
8849                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
8850                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765 &&
8851                     (tp->tg3_flags2 & TG3_FLG2_USING_MSI) &&
8852                     (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)) {
8853                         u32 val = tr32(PCIE_TRANSACTION_CFG);
8854
8855                         tw32(PCIE_TRANSACTION_CFG,
8856                              val | PCIE_TRANS_CFG_1SHOT_MSI);
8857                 }
8858         }
8859
8860         tg3_phy_start(tp);
8861
8862         tg3_full_lock(tp, 0);
8863
8864         add_timer(&tp->timer);
8865         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
8866         tg3_enable_ints(tp);
8867
8868         tg3_full_unlock(tp);
8869
8870         netif_tx_start_all_queues(dev);
8871
8872         return 0;
8873
8874 err_out3:
8875         for (i = tp->irq_cnt - 1; i >= 0; i--) {
8876                 struct tg3_napi *tnapi = &tp->napi[i];
8877                 free_irq(tnapi->irq_vec, tnapi);
8878         }
8879
8880 err_out2:
8881         tg3_napi_disable(tp);
8882         tg3_free_consistent(tp);
8883
8884 err_out1:
8885         tg3_ints_fini(tp);
8886         return err;
8887 }
8888
8889 #if 0
8890 /*static*/ void tg3_dump_state(struct tg3 *tp)
8891 {
8892         u32 val32, val32_2, val32_3, val32_4, val32_5;
8893         u16 val16;
8894         int i;
8895         struct tg3_hw_status *sblk = tp->napi[0]->hw_status;
8896
8897         pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
8898         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
8899         printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
8900                val16, val32);
8901
8902         /* MAC block */
8903         printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
8904                tr32(MAC_MODE), tr32(MAC_STATUS));
8905         printk("       MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
8906                tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
8907         printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
8908                tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
8909         printk("       MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
8910                tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
8911
8912         /* Send data initiator control block */
8913         printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
8914                tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
8915         printk("       SNDDATAI_STATSCTRL[%08x]\n",
8916                tr32(SNDDATAI_STATSCTRL));
8917
8918         /* Send data completion control block */
8919         printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
8920
8921         /* Send BD ring selector block */
8922         printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
8923                tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
8924
8925         /* Send BD initiator control block */
8926         printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
8927                tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
8928
8929         /* Send BD completion control block */
8930         printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
8931
8932         /* Receive list placement control block */
8933         printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
8934                tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
8935         printk("       RCVLPC_STATSCTRL[%08x]\n",
8936                tr32(RCVLPC_STATSCTRL));
8937
8938         /* Receive data and receive BD initiator control block */
8939         printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
8940                tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
8941
8942         /* Receive data completion control block */
8943         printk("DEBUG: RCVDCC_MODE[%08x]\n",
8944                tr32(RCVDCC_MODE));
8945
8946         /* Receive BD initiator control block */
8947         printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
8948                tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
8949
8950         /* Receive BD completion control block */
8951         printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
8952                tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
8953
8954         /* Receive list selector control block */
8955         printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
8956                tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
8957
8958         /* Mbuf cluster free block */
8959         printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
8960                tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
8961
8962         /* Host coalescing control block */
8963         printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
8964                tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
8965         printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
8966                tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8967                tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8968         printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
8969                tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8970                tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8971         printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
8972                tr32(HOSTCC_STATS_BLK_NIC_ADDR));
8973         printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
8974                tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
8975
8976         /* Memory arbiter control block */
8977         printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
8978                tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
8979
8980         /* Buffer manager control block */
8981         printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
8982                tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
8983         printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
8984                tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
8985         printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
8986                "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
8987                tr32(BUFMGR_DMA_DESC_POOL_ADDR),
8988                tr32(BUFMGR_DMA_DESC_POOL_SIZE));
8989
8990         /* Read DMA control block */
8991         printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
8992                tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
8993
8994         /* Write DMA control block */
8995         printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
8996                tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
8997
8998         /* DMA completion block */
8999         printk("DEBUG: DMAC_MODE[%08x]\n",
9000                tr32(DMAC_MODE));
9001
9002         /* GRC block */
9003         printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
9004                tr32(GRC_MODE), tr32(GRC_MISC_CFG));
9005         printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
9006                tr32(GRC_LOCAL_CTRL));
9007
9008         /* TG3_BDINFOs */
9009         printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
9010                tr32(RCVDBDI_JUMBO_BD + 0x0),
9011                tr32(RCVDBDI_JUMBO_BD + 0x4),
9012                tr32(RCVDBDI_JUMBO_BD + 0x8),
9013                tr32(RCVDBDI_JUMBO_BD + 0xc));
9014         printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
9015                tr32(RCVDBDI_STD_BD + 0x0),
9016                tr32(RCVDBDI_STD_BD + 0x4),
9017                tr32(RCVDBDI_STD_BD + 0x8),
9018                tr32(RCVDBDI_STD_BD + 0xc));
9019         printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
9020                tr32(RCVDBDI_MINI_BD + 0x0),
9021                tr32(RCVDBDI_MINI_BD + 0x4),
9022                tr32(RCVDBDI_MINI_BD + 0x8),
9023                tr32(RCVDBDI_MINI_BD + 0xc));
9024
9025         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
9026         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
9027         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
9028         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
9029         printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
9030                val32, val32_2, val32_3, val32_4);
9031
9032         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
9033         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
9034         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
9035         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
9036         printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
9037                val32, val32_2, val32_3, val32_4);
9038
9039         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
9040         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
9041         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
9042         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
9043         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
9044         printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
9045                val32, val32_2, val32_3, val32_4, val32_5);
9046
9047         /* SW status block */
9048         printk(KERN_DEBUG
9049          "Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
9050                sblk->status,
9051                sblk->status_tag,
9052                sblk->rx_jumbo_consumer,
9053                sblk->rx_consumer,
9054                sblk->rx_mini_consumer,
9055                sblk->idx[0].rx_producer,
9056                sblk->idx[0].tx_consumer);
9057
9058         /* SW statistics block */
9059         printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
9060                ((u32 *)tp->hw_stats)[0],
9061                ((u32 *)tp->hw_stats)[1],
9062                ((u32 *)tp->hw_stats)[2],
9063                ((u32 *)tp->hw_stats)[3]);
9064
9065         /* Mailboxes */
9066         printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
9067                tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
9068                tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
9069                tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
9070                tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
9071
9072         /* NIC side send descriptors. */
9073         for (i = 0; i < 6; i++) {
9074                 unsigned long txd;
9075
9076                 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
9077                         + (i * sizeof(struct tg3_tx_buffer_desc));
9078                 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
9079                        i,
9080                        readl(txd + 0x0), readl(txd + 0x4),
9081                        readl(txd + 0x8), readl(txd + 0xc));
9082         }
9083
9084         /* NIC side RX descriptors. */
9085         for (i = 0; i < 6; i++) {
9086                 unsigned long rxd;
9087
9088                 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
9089                         + (i * sizeof(struct tg3_rx_buffer_desc));
9090                 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
9091                        i,
9092                        readl(rxd + 0x0), readl(rxd + 0x4),
9093                        readl(rxd + 0x8), readl(rxd + 0xc));
9094                 rxd += (4 * sizeof(u32));
9095                 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
9096                        i,
9097                        readl(rxd + 0x0), readl(rxd + 0x4),
9098                        readl(rxd + 0x8), readl(rxd + 0xc));
9099         }
9100
9101         for (i = 0; i < 6; i++) {
9102                 unsigned long rxd;
9103
9104                 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
9105                         + (i * sizeof(struct tg3_rx_buffer_desc));
9106                 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
9107                        i,
9108                        readl(rxd + 0x0), readl(rxd + 0x4),
9109                        readl(rxd + 0x8), readl(rxd + 0xc));
9110                 rxd += (4 * sizeof(u32));
9111                 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
9112                        i,
9113                        readl(rxd + 0x0), readl(rxd + 0x4),
9114                        readl(rxd + 0x8), readl(rxd + 0xc));
9115         }
9116 }
9117 #endif
9118
9119 static struct net_device_stats *tg3_get_stats(struct net_device *);
9120 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
9121
9122 static int tg3_close(struct net_device *dev)
9123 {
9124         int i;
9125         struct tg3 *tp = netdev_priv(dev);
9126
9127         tg3_napi_disable(tp);
9128         cancel_work_sync(&tp->reset_task);
9129
9130         netif_tx_stop_all_queues(dev);
9131
9132         del_timer_sync(&tp->timer);
9133
9134         tg3_phy_stop(tp);
9135
9136         tg3_full_lock(tp, 1);
9137 #if 0
9138         tg3_dump_state(tp);
9139 #endif
9140
9141         tg3_disable_ints(tp);
9142
9143         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9144         tg3_free_rings(tp);
9145         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
9146
9147         tg3_full_unlock(tp);
9148
9149         for (i = tp->irq_cnt - 1; i >= 0; i--) {
9150                 struct tg3_napi *tnapi = &tp->napi[i];
9151                 free_irq(tnapi->irq_vec, tnapi);
9152         }
9153
9154         tg3_ints_fini(tp);
9155
9156         memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
9157                sizeof(tp->net_stats_prev));
9158         memcpy(&tp->estats_prev, tg3_get_estats(tp),
9159                sizeof(tp->estats_prev));
9160
9161         tg3_free_consistent(tp);
9162
9163         tg3_set_power_state(tp, PCI_D3hot);
9164
9165         netif_carrier_off(tp->dev);
9166
9167         return 0;
9168 }
9169
9170 static inline unsigned long get_stat64(tg3_stat64_t *val)
9171 {
9172         unsigned long ret;
9173
9174 #if (BITS_PER_LONG == 32)
9175         ret = val->low;
9176 #else
9177         ret = ((u64)val->high << 32) | ((u64)val->low);
9178 #endif
9179         return ret;
9180 }
9181
9182 static inline u64 get_estat64(tg3_stat64_t *val)
9183 {
9184        return ((u64)val->high << 32) | ((u64)val->low);
9185 }
9186
9187 static unsigned long calc_crc_errors(struct tg3 *tp)
9188 {
9189         struct tg3_hw_stats *hw_stats = tp->hw_stats;
9190
9191         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
9192             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
9193              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
9194                 u32 val;
9195
9196                 spin_lock_bh(&tp->lock);
9197                 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
9198                         tg3_writephy(tp, MII_TG3_TEST1,
9199                                      val | MII_TG3_TEST1_CRC_EN);
9200                         tg3_readphy(tp, 0x14, &val);
9201                 } else
9202                         val = 0;
9203                 spin_unlock_bh(&tp->lock);
9204
9205                 tp->phy_crc_errors += val;
9206
9207                 return tp->phy_crc_errors;
9208         }
9209
9210         return get_stat64(&hw_stats->rx_fcs_errors);
9211 }
9212
9213 #define ESTAT_ADD(member) \
9214         estats->member =        old_estats->member + \
9215                                 get_estat64(&hw_stats->member)
9216
9217 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
9218 {
9219         struct tg3_ethtool_stats *estats = &tp->estats;
9220         struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
9221         struct tg3_hw_stats *hw_stats = tp->hw_stats;
9222
9223         if (!hw_stats)
9224                 return old_estats;
9225
9226         ESTAT_ADD(rx_octets);
9227         ESTAT_ADD(rx_fragments);
9228         ESTAT_ADD(rx_ucast_packets);
9229         ESTAT_ADD(rx_mcast_packets);
9230         ESTAT_ADD(rx_bcast_packets);
9231         ESTAT_ADD(rx_fcs_errors);
9232         ESTAT_ADD(rx_align_errors);
9233         ESTAT_ADD(rx_xon_pause_rcvd);
9234         ESTAT_ADD(rx_xoff_pause_rcvd);
9235         ESTAT_ADD(rx_mac_ctrl_rcvd);
9236         ESTAT_ADD(rx_xoff_entered);
9237         ESTAT_ADD(rx_frame_too_long_errors);
9238         ESTAT_ADD(rx_jabbers);
9239         ESTAT_ADD(rx_undersize_packets);
9240         ESTAT_ADD(rx_in_length_errors);
9241         ESTAT_ADD(rx_out_length_errors);
9242         ESTAT_ADD(rx_64_or_less_octet_packets);
9243         ESTAT_ADD(rx_65_to_127_octet_packets);
9244         ESTAT_ADD(rx_128_to_255_octet_packets);
9245         ESTAT_ADD(rx_256_to_511_octet_packets);
9246         ESTAT_ADD(rx_512_to_1023_octet_packets);
9247         ESTAT_ADD(rx_1024_to_1522_octet_packets);
9248         ESTAT_ADD(rx_1523_to_2047_octet_packets);
9249         ESTAT_ADD(rx_2048_to_4095_octet_packets);
9250         ESTAT_ADD(rx_4096_to_8191_octet_packets);
9251         ESTAT_ADD(rx_8192_to_9022_octet_packets);
9252
9253         ESTAT_ADD(tx_octets);
9254         ESTAT_ADD(tx_collisions);
9255         ESTAT_ADD(tx_xon_sent);
9256         ESTAT_ADD(tx_xoff_sent);
9257         ESTAT_ADD(tx_flow_control);
9258         ESTAT_ADD(tx_mac_errors);
9259         ESTAT_ADD(tx_single_collisions);
9260         ESTAT_ADD(tx_mult_collisions);
9261         ESTAT_ADD(tx_deferred);
9262         ESTAT_ADD(tx_excessive_collisions);
9263         ESTAT_ADD(tx_late_collisions);
9264         ESTAT_ADD(tx_collide_2times);
9265         ESTAT_ADD(tx_collide_3times);
9266         ESTAT_ADD(tx_collide_4times);
9267         ESTAT_ADD(tx_collide_5times);
9268         ESTAT_ADD(tx_collide_6times);
9269         ESTAT_ADD(tx_collide_7times);
9270         ESTAT_ADD(tx_collide_8times);
9271         ESTAT_ADD(tx_collide_9times);
9272         ESTAT_ADD(tx_collide_10times);
9273         ESTAT_ADD(tx_collide_11times);
9274         ESTAT_ADD(tx_collide_12times);
9275         ESTAT_ADD(tx_collide_13times);
9276         ESTAT_ADD(tx_collide_14times);
9277         ESTAT_ADD(tx_collide_15times);
9278         ESTAT_ADD(tx_ucast_packets);
9279         ESTAT_ADD(tx_mcast_packets);
9280         ESTAT_ADD(tx_bcast_packets);
9281         ESTAT_ADD(tx_carrier_sense_errors);
9282         ESTAT_ADD(tx_discards);
9283         ESTAT_ADD(tx_errors);
9284
9285         ESTAT_ADD(dma_writeq_full);
9286         ESTAT_ADD(dma_write_prioq_full);
9287         ESTAT_ADD(rxbds_empty);
9288         ESTAT_ADD(rx_discards);
9289         ESTAT_ADD(rx_errors);
9290         ESTAT_ADD(rx_threshold_hit);
9291
9292         ESTAT_ADD(dma_readq_full);
9293         ESTAT_ADD(dma_read_prioq_full);
9294         ESTAT_ADD(tx_comp_queue_full);
9295
9296         ESTAT_ADD(ring_set_send_prod_index);
9297         ESTAT_ADD(ring_status_update);
9298         ESTAT_ADD(nic_irqs);
9299         ESTAT_ADD(nic_avoided_irqs);
9300         ESTAT_ADD(nic_tx_threshold_hit);
9301
9302         return estats;
9303 }
9304
9305 static struct net_device_stats *tg3_get_stats(struct net_device *dev)
9306 {
9307         struct tg3 *tp = netdev_priv(dev);
9308         struct net_device_stats *stats = &tp->net_stats;
9309         struct net_device_stats *old_stats = &tp->net_stats_prev;
9310         struct tg3_hw_stats *hw_stats = tp->hw_stats;
9311
9312         if (!hw_stats)
9313                 return old_stats;
9314
9315         stats->rx_packets = old_stats->rx_packets +
9316                 get_stat64(&hw_stats->rx_ucast_packets) +
9317                 get_stat64(&hw_stats->rx_mcast_packets) +
9318                 get_stat64(&hw_stats->rx_bcast_packets);
9319
9320         stats->tx_packets = old_stats->tx_packets +
9321                 get_stat64(&hw_stats->tx_ucast_packets) +
9322                 get_stat64(&hw_stats->tx_mcast_packets) +
9323                 get_stat64(&hw_stats->tx_bcast_packets);
9324
9325         stats->rx_bytes = old_stats->rx_bytes +
9326                 get_stat64(&hw_stats->rx_octets);
9327         stats->tx_bytes = old_stats->tx_bytes +
9328                 get_stat64(&hw_stats->tx_octets);
9329
9330         stats->rx_errors = old_stats->rx_errors +
9331                 get_stat64(&hw_stats->rx_errors);
9332         stats->tx_errors = old_stats->tx_errors +
9333                 get_stat64(&hw_stats->tx_errors) +
9334                 get_stat64(&hw_stats->tx_mac_errors) +
9335                 get_stat64(&hw_stats->tx_carrier_sense_errors) +
9336                 get_stat64(&hw_stats->tx_discards);
9337
9338         stats->multicast = old_stats->multicast +
9339                 get_stat64(&hw_stats->rx_mcast_packets);
9340         stats->collisions = old_stats->collisions +
9341                 get_stat64(&hw_stats->tx_collisions);
9342
9343         stats->rx_length_errors = old_stats->rx_length_errors +
9344                 get_stat64(&hw_stats->rx_frame_too_long_errors) +
9345                 get_stat64(&hw_stats->rx_undersize_packets);
9346
9347         stats->rx_over_errors = old_stats->rx_over_errors +
9348                 get_stat64(&hw_stats->rxbds_empty);
9349         stats->rx_frame_errors = old_stats->rx_frame_errors +
9350                 get_stat64(&hw_stats->rx_align_errors);
9351         stats->tx_aborted_errors = old_stats->tx_aborted_errors +
9352                 get_stat64(&hw_stats->tx_discards);
9353         stats->tx_carrier_errors = old_stats->tx_carrier_errors +
9354                 get_stat64(&hw_stats->tx_carrier_sense_errors);
9355
9356         stats->rx_crc_errors = old_stats->rx_crc_errors +
9357                 calc_crc_errors(tp);
9358
9359         stats->rx_missed_errors = old_stats->rx_missed_errors +
9360                 get_stat64(&hw_stats->rx_discards);
9361
9362         return stats;
9363 }
9364
9365 static inline u32 calc_crc(unsigned char *buf, int len)
9366 {
9367         u32 reg;
9368         u32 tmp;
9369         int j, k;
9370
9371         reg = 0xffffffff;
9372
9373         for (j = 0; j < len; j++) {
9374                 reg ^= buf[j];
9375
9376                 for (k = 0; k < 8; k++) {
9377                         tmp = reg & 0x01;
9378
9379                         reg >>= 1;
9380
9381                         if (tmp) {
9382                                 reg ^= 0xedb88320;
9383                         }
9384                 }
9385         }
9386
9387         return ~reg;
9388 }
9389
9390 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
9391 {
9392         /* accept or reject all multicast frames */
9393         tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
9394         tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
9395         tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
9396         tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
9397 }
9398
9399 static void __tg3_set_rx_mode(struct net_device *dev)
9400 {
9401         struct tg3 *tp = netdev_priv(dev);
9402         u32 rx_mode;
9403
9404         rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
9405                                   RX_MODE_KEEP_VLAN_TAG);
9406
9407         /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
9408          * flag clear.
9409          */
9410 #if TG3_VLAN_TAG_USED
9411         if (!tp->vlgrp &&
9412             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9413                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9414 #else
9415         /* By definition, VLAN is disabled always in this
9416          * case.
9417          */
9418         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9419                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9420 #endif
9421
9422         if (dev->flags & IFF_PROMISC) {
9423                 /* Promiscuous mode. */
9424                 rx_mode |= RX_MODE_PROMISC;
9425         } else if (dev->flags & IFF_ALLMULTI) {
9426                 /* Accept all multicast. */
9427                 tg3_set_multi (tp, 1);
9428         } else if (dev->mc_count < 1) {
9429                 /* Reject all multicast. */
9430                 tg3_set_multi (tp, 0);
9431         } else {
9432                 /* Accept one or more multicast(s). */
9433                 struct dev_mc_list *mclist;
9434                 unsigned int i;
9435                 u32 mc_filter[4] = { 0, };
9436                 u32 regidx;
9437                 u32 bit;
9438                 u32 crc;
9439
9440                 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
9441                      i++, mclist = mclist->next) {
9442
9443                         crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
9444                         bit = ~crc & 0x7f;
9445                         regidx = (bit & 0x60) >> 5;
9446                         bit &= 0x1f;
9447                         mc_filter[regidx] |= (1 << bit);
9448                 }
9449
9450                 tw32(MAC_HASH_REG_0, mc_filter[0]);
9451                 tw32(MAC_HASH_REG_1, mc_filter[1]);
9452                 tw32(MAC_HASH_REG_2, mc_filter[2]);
9453                 tw32(MAC_HASH_REG_3, mc_filter[3]);
9454         }
9455
9456         if (rx_mode != tp->rx_mode) {
9457                 tp->rx_mode = rx_mode;
9458                 tw32_f(MAC_RX_MODE, rx_mode);
9459                 udelay(10);
9460         }
9461 }
9462
9463 static void tg3_set_rx_mode(struct net_device *dev)
9464 {
9465         struct tg3 *tp = netdev_priv(dev);
9466
9467         if (!netif_running(dev))
9468                 return;
9469
9470         tg3_full_lock(tp, 0);
9471         __tg3_set_rx_mode(dev);
9472         tg3_full_unlock(tp);
9473 }
9474
9475 #define TG3_REGDUMP_LEN         (32 * 1024)
9476
9477 static int tg3_get_regs_len(struct net_device *dev)
9478 {
9479         return TG3_REGDUMP_LEN;
9480 }
9481
9482 static void tg3_get_regs(struct net_device *dev,
9483                 struct ethtool_regs *regs, void *_p)
9484 {
9485         u32 *p = _p;
9486         struct tg3 *tp = netdev_priv(dev);
9487         u8 *orig_p = _p;
9488         int i;
9489
9490         regs->version = 0;
9491
9492         memset(p, 0, TG3_REGDUMP_LEN);
9493
9494         if (tp->link_config.phy_is_low_power)
9495                 return;
9496
9497         tg3_full_lock(tp, 0);
9498
9499 #define __GET_REG32(reg)        (*(p)++ = tr32(reg))
9500 #define GET_REG32_LOOP(base,len)                \
9501 do {    p = (u32 *)(orig_p + (base));           \
9502         for (i = 0; i < len; i += 4)            \
9503                 __GET_REG32((base) + i);        \
9504 } while (0)
9505 #define GET_REG32_1(reg)                        \
9506 do {    p = (u32 *)(orig_p + (reg));            \
9507         __GET_REG32((reg));                     \
9508 } while (0)
9509
9510         GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
9511         GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
9512         GET_REG32_LOOP(MAC_MODE, 0x4f0);
9513         GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
9514         GET_REG32_1(SNDDATAC_MODE);
9515         GET_REG32_LOOP(SNDBDS_MODE, 0x80);
9516         GET_REG32_LOOP(SNDBDI_MODE, 0x48);
9517         GET_REG32_1(SNDBDC_MODE);
9518         GET_REG32_LOOP(RCVLPC_MODE, 0x20);
9519         GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
9520         GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
9521         GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
9522         GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
9523         GET_REG32_1(RCVDCC_MODE);
9524         GET_REG32_LOOP(RCVBDI_MODE, 0x20);
9525         GET_REG32_LOOP(RCVCC_MODE, 0x14);
9526         GET_REG32_LOOP(RCVLSC_MODE, 0x08);
9527         GET_REG32_1(MBFREE_MODE);
9528         GET_REG32_LOOP(HOSTCC_MODE, 0x100);
9529         GET_REG32_LOOP(MEMARB_MODE, 0x10);
9530         GET_REG32_LOOP(BUFMGR_MODE, 0x58);
9531         GET_REG32_LOOP(RDMAC_MODE, 0x08);
9532         GET_REG32_LOOP(WDMAC_MODE, 0x08);
9533         GET_REG32_1(RX_CPU_MODE);
9534         GET_REG32_1(RX_CPU_STATE);
9535         GET_REG32_1(RX_CPU_PGMCTR);
9536         GET_REG32_1(RX_CPU_HWBKPT);
9537         GET_REG32_1(TX_CPU_MODE);
9538         GET_REG32_1(TX_CPU_STATE);
9539         GET_REG32_1(TX_CPU_PGMCTR);
9540         GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
9541         GET_REG32_LOOP(FTQ_RESET, 0x120);
9542         GET_REG32_LOOP(MSGINT_MODE, 0x0c);
9543         GET_REG32_1(DMAC_MODE);
9544         GET_REG32_LOOP(GRC_MODE, 0x4c);
9545         if (tp->tg3_flags & TG3_FLAG_NVRAM)
9546                 GET_REG32_LOOP(NVRAM_CMD, 0x24);
9547
9548 #undef __GET_REG32
9549 #undef GET_REG32_LOOP
9550 #undef GET_REG32_1
9551
9552         tg3_full_unlock(tp);
9553 }
9554
9555 static int tg3_get_eeprom_len(struct net_device *dev)
9556 {
9557         struct tg3 *tp = netdev_priv(dev);
9558
9559         return tp->nvram_size;
9560 }
9561
9562 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9563 {
9564         struct tg3 *tp = netdev_priv(dev);
9565         int ret;
9566         u8  *pd;
9567         u32 i, offset, len, b_offset, b_count;
9568         __be32 val;
9569
9570         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9571                 return -EINVAL;
9572
9573         if (tp->link_config.phy_is_low_power)
9574                 return -EAGAIN;
9575
9576         offset = eeprom->offset;
9577         len = eeprom->len;
9578         eeprom->len = 0;
9579
9580         eeprom->magic = TG3_EEPROM_MAGIC;
9581
9582         if (offset & 3) {
9583                 /* adjustments to start on required 4 byte boundary */
9584                 b_offset = offset & 3;
9585                 b_count = 4 - b_offset;
9586                 if (b_count > len) {
9587                         /* i.e. offset=1 len=2 */
9588                         b_count = len;
9589                 }
9590                 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
9591                 if (ret)
9592                         return ret;
9593                 memcpy(data, ((char*)&val) + b_offset, b_count);
9594                 len -= b_count;
9595                 offset += b_count;
9596                 eeprom->len += b_count;
9597         }
9598
9599         /* read bytes upto the last 4 byte boundary */
9600         pd = &data[eeprom->len];
9601         for (i = 0; i < (len - (len & 3)); i += 4) {
9602                 ret = tg3_nvram_read_be32(tp, offset + i, &val);
9603                 if (ret) {
9604                         eeprom->len += i;
9605                         return ret;
9606                 }
9607                 memcpy(pd + i, &val, 4);
9608         }
9609         eeprom->len += i;
9610
9611         if (len & 3) {
9612                 /* read last bytes not ending on 4 byte boundary */
9613                 pd = &data[eeprom->len];
9614                 b_count = len & 3;
9615                 b_offset = offset + len - b_count;
9616                 ret = tg3_nvram_read_be32(tp, b_offset, &val);
9617                 if (ret)
9618                         return ret;
9619                 memcpy(pd, &val, b_count);
9620                 eeprom->len += b_count;
9621         }
9622         return 0;
9623 }
9624
9625 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
9626
9627 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9628 {
9629         struct tg3 *tp = netdev_priv(dev);
9630         int ret;
9631         u32 offset, len, b_offset, odd_len;
9632         u8 *buf;
9633         __be32 start, end;
9634
9635         if (tp->link_config.phy_is_low_power)
9636                 return -EAGAIN;
9637
9638         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
9639             eeprom->magic != TG3_EEPROM_MAGIC)
9640                 return -EINVAL;
9641
9642         offset = eeprom->offset;
9643         len = eeprom->len;
9644
9645         if ((b_offset = (offset & 3))) {
9646                 /* adjustments to start on required 4 byte boundary */
9647                 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
9648                 if (ret)
9649                         return ret;
9650                 len += b_offset;
9651                 offset &= ~3;
9652                 if (len < 4)
9653                         len = 4;
9654         }
9655
9656         odd_len = 0;
9657         if (len & 3) {
9658                 /* adjustments to end on required 4 byte boundary */
9659                 odd_len = 1;
9660                 len = (len + 3) & ~3;
9661                 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
9662                 if (ret)
9663                         return ret;
9664         }
9665
9666         buf = data;
9667         if (b_offset || odd_len) {
9668                 buf = kmalloc(len, GFP_KERNEL);
9669                 if (!buf)
9670                         return -ENOMEM;
9671                 if (b_offset)
9672                         memcpy(buf, &start, 4);
9673                 if (odd_len)
9674                         memcpy(buf+len-4, &end, 4);
9675                 memcpy(buf + b_offset, data, eeprom->len);
9676         }
9677
9678         ret = tg3_nvram_write_block(tp, offset, len, buf);
9679
9680         if (buf != data)
9681                 kfree(buf);
9682
9683         return ret;
9684 }
9685
9686 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9687 {
9688         struct tg3 *tp = netdev_priv(dev);
9689
9690         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9691                 struct phy_device *phydev;
9692                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9693                         return -EAGAIN;
9694                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9695                 return phy_ethtool_gset(phydev, cmd);
9696         }
9697
9698         cmd->supported = (SUPPORTED_Autoneg);
9699
9700         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
9701                 cmd->supported |= (SUPPORTED_1000baseT_Half |
9702                                    SUPPORTED_1000baseT_Full);
9703
9704         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
9705                 cmd->supported |= (SUPPORTED_100baseT_Half |
9706                                   SUPPORTED_100baseT_Full |
9707                                   SUPPORTED_10baseT_Half |
9708                                   SUPPORTED_10baseT_Full |
9709                                   SUPPORTED_TP);
9710                 cmd->port = PORT_TP;
9711         } else {
9712                 cmd->supported |= SUPPORTED_FIBRE;
9713                 cmd->port = PORT_FIBRE;
9714         }
9715
9716         cmd->advertising = tp->link_config.advertising;
9717         if (netif_running(dev)) {
9718                 cmd->speed = tp->link_config.active_speed;
9719                 cmd->duplex = tp->link_config.active_duplex;
9720         }
9721         cmd->phy_address = tp->phy_addr;
9722         cmd->transceiver = XCVR_INTERNAL;
9723         cmd->autoneg = tp->link_config.autoneg;
9724         cmd->maxtxpkt = 0;
9725         cmd->maxrxpkt = 0;
9726         return 0;
9727 }
9728
9729 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9730 {
9731         struct tg3 *tp = netdev_priv(dev);
9732
9733         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9734                 struct phy_device *phydev;
9735                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9736                         return -EAGAIN;
9737                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9738                 return phy_ethtool_sset(phydev, cmd);
9739         }
9740
9741         if (cmd->autoneg != AUTONEG_ENABLE &&
9742             cmd->autoneg != AUTONEG_DISABLE)
9743                 return -EINVAL;
9744
9745         if (cmd->autoneg == AUTONEG_DISABLE &&
9746             cmd->duplex != DUPLEX_FULL &&
9747             cmd->duplex != DUPLEX_HALF)
9748                 return -EINVAL;
9749
9750         if (cmd->autoneg == AUTONEG_ENABLE) {
9751                 u32 mask = ADVERTISED_Autoneg |
9752                            ADVERTISED_Pause |
9753                            ADVERTISED_Asym_Pause;
9754
9755                 if (!(tp->tg3_flags2 & TG3_FLAG_10_100_ONLY))
9756                         mask |= ADVERTISED_1000baseT_Half |
9757                                 ADVERTISED_1000baseT_Full;
9758
9759                 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
9760                         mask |= ADVERTISED_100baseT_Half |
9761                                 ADVERTISED_100baseT_Full |
9762                                 ADVERTISED_10baseT_Half |
9763                                 ADVERTISED_10baseT_Full |
9764                                 ADVERTISED_TP;
9765                 else
9766                         mask |= ADVERTISED_FIBRE;
9767
9768                 if (cmd->advertising & ~mask)
9769                         return -EINVAL;
9770
9771                 mask &= (ADVERTISED_1000baseT_Half |
9772                          ADVERTISED_1000baseT_Full |
9773                          ADVERTISED_100baseT_Half |
9774                          ADVERTISED_100baseT_Full |
9775                          ADVERTISED_10baseT_Half |
9776                          ADVERTISED_10baseT_Full);
9777
9778                 cmd->advertising &= mask;
9779         } else {
9780                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
9781                         if (cmd->speed != SPEED_1000)
9782                                 return -EINVAL;
9783
9784                         if (cmd->duplex != DUPLEX_FULL)
9785                                 return -EINVAL;
9786                 } else {
9787                         if (cmd->speed != SPEED_100 &&
9788                             cmd->speed != SPEED_10)
9789                                 return -EINVAL;
9790                 }
9791         }
9792
9793         tg3_full_lock(tp, 0);
9794
9795         tp->link_config.autoneg = cmd->autoneg;
9796         if (cmd->autoneg == AUTONEG_ENABLE) {
9797                 tp->link_config.advertising = (cmd->advertising |
9798                                               ADVERTISED_Autoneg);
9799                 tp->link_config.speed = SPEED_INVALID;
9800                 tp->link_config.duplex = DUPLEX_INVALID;
9801         } else {
9802                 tp->link_config.advertising = 0;
9803                 tp->link_config.speed = cmd->speed;
9804                 tp->link_config.duplex = cmd->duplex;
9805         }
9806
9807         tp->link_config.orig_speed = tp->link_config.speed;
9808         tp->link_config.orig_duplex = tp->link_config.duplex;
9809         tp->link_config.orig_autoneg = tp->link_config.autoneg;
9810
9811         if (netif_running(dev))
9812                 tg3_setup_phy(tp, 1);
9813
9814         tg3_full_unlock(tp);
9815
9816         return 0;
9817 }
9818
9819 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
9820 {
9821         struct tg3 *tp = netdev_priv(dev);
9822
9823         strcpy(info->driver, DRV_MODULE_NAME);
9824         strcpy(info->version, DRV_MODULE_VERSION);
9825         strcpy(info->fw_version, tp->fw_ver);
9826         strcpy(info->bus_info, pci_name(tp->pdev));
9827 }
9828
9829 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9830 {
9831         struct tg3 *tp = netdev_priv(dev);
9832
9833         if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
9834             device_can_wakeup(&tp->pdev->dev))
9835                 wol->supported = WAKE_MAGIC;
9836         else
9837                 wol->supported = 0;
9838         wol->wolopts = 0;
9839         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
9840             device_can_wakeup(&tp->pdev->dev))
9841                 wol->wolopts = WAKE_MAGIC;
9842         memset(&wol->sopass, 0, sizeof(wol->sopass));
9843 }
9844
9845 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9846 {
9847         struct tg3 *tp = netdev_priv(dev);
9848         struct device *dp = &tp->pdev->dev;
9849
9850         if (wol->wolopts & ~WAKE_MAGIC)
9851                 return -EINVAL;
9852         if ((wol->wolopts & WAKE_MAGIC) &&
9853             !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
9854                 return -EINVAL;
9855
9856         spin_lock_bh(&tp->lock);
9857         if (wol->wolopts & WAKE_MAGIC) {
9858                 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
9859                 device_set_wakeup_enable(dp, true);
9860         } else {
9861                 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
9862                 device_set_wakeup_enable(dp, false);
9863         }
9864         spin_unlock_bh(&tp->lock);
9865
9866         return 0;
9867 }
9868
9869 static u32 tg3_get_msglevel(struct net_device *dev)
9870 {
9871         struct tg3 *tp = netdev_priv(dev);
9872         return tp->msg_enable;
9873 }
9874
9875 static void tg3_set_msglevel(struct net_device *dev, u32 value)
9876 {
9877         struct tg3 *tp = netdev_priv(dev);
9878         tp->msg_enable = value;
9879 }
9880
9881 static int tg3_set_tso(struct net_device *dev, u32 value)
9882 {
9883         struct tg3 *tp = netdev_priv(dev);
9884
9885         if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
9886                 if (value)
9887                         return -EINVAL;
9888                 return 0;
9889         }
9890         if ((dev->features & NETIF_F_IPV6_CSUM) &&
9891             ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
9892              (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3))) {
9893                 if (value) {
9894                         dev->features |= NETIF_F_TSO6;
9895                         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
9896                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9897                             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
9898                              GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
9899                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
9900                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
9901                                 dev->features |= NETIF_F_TSO_ECN;
9902                 } else
9903                         dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
9904         }
9905         return ethtool_op_set_tso(dev, value);
9906 }
9907
9908 static int tg3_nway_reset(struct net_device *dev)
9909 {
9910         struct tg3 *tp = netdev_priv(dev);
9911         int r;
9912
9913         if (!netif_running(dev))
9914                 return -EAGAIN;
9915
9916         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9917                 return -EINVAL;
9918
9919         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9920                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9921                         return -EAGAIN;
9922                 r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
9923         } else {
9924                 u32 bmcr;
9925
9926                 spin_lock_bh(&tp->lock);
9927                 r = -EINVAL;
9928                 tg3_readphy(tp, MII_BMCR, &bmcr);
9929                 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
9930                     ((bmcr & BMCR_ANENABLE) ||
9931                      (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
9932                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
9933                                                    BMCR_ANENABLE);
9934                         r = 0;
9935                 }
9936                 spin_unlock_bh(&tp->lock);
9937         }
9938
9939         return r;
9940 }
9941
9942 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9943 {
9944         struct tg3 *tp = netdev_priv(dev);
9945
9946         ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
9947         ering->rx_mini_max_pending = 0;
9948         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9949                 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
9950         else
9951                 ering->rx_jumbo_max_pending = 0;
9952
9953         ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
9954
9955         ering->rx_pending = tp->rx_pending;
9956         ering->rx_mini_pending = 0;
9957         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9958                 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
9959         else
9960                 ering->rx_jumbo_pending = 0;
9961
9962         ering->tx_pending = tp->napi[0].tx_pending;
9963 }
9964
9965 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9966 {
9967         struct tg3 *tp = netdev_priv(dev);
9968         int i, irq_sync = 0, err = 0;
9969
9970         if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
9971             (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
9972             (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
9973             (ering->tx_pending <= MAX_SKB_FRAGS) ||
9974             ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
9975              (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
9976                 return -EINVAL;
9977
9978         if (netif_running(dev)) {
9979                 tg3_phy_stop(tp);
9980                 tg3_netif_stop(tp);
9981                 irq_sync = 1;
9982         }
9983
9984         tg3_full_lock(tp, irq_sync);
9985
9986         tp->rx_pending = ering->rx_pending;
9987
9988         if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
9989             tp->rx_pending > 63)
9990                 tp->rx_pending = 63;
9991         tp->rx_jumbo_pending = ering->rx_jumbo_pending;
9992
9993         for (i = 0; i < TG3_IRQ_MAX_VECS; i++)
9994                 tp->napi[i].tx_pending = ering->tx_pending;
9995
9996         if (netif_running(dev)) {
9997                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9998                 err = tg3_restart_hw(tp, 1);
9999                 if (!err)
10000                         tg3_netif_start(tp);
10001         }
10002
10003         tg3_full_unlock(tp);
10004
10005         if (irq_sync && !err)
10006                 tg3_phy_start(tp);
10007
10008         return err;
10009 }
10010
10011 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
10012 {
10013         struct tg3 *tp = netdev_priv(dev);
10014
10015         epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
10016
10017         if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
10018                 epause->rx_pause = 1;
10019         else
10020                 epause->rx_pause = 0;
10021
10022         if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
10023                 epause->tx_pause = 1;
10024         else
10025                 epause->tx_pause = 0;
10026 }
10027
10028 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
10029 {
10030         struct tg3 *tp = netdev_priv(dev);
10031         int err = 0;
10032
10033         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
10034                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
10035                         return -EAGAIN;
10036
10037                 if (epause->autoneg) {
10038                         u32 newadv;
10039                         struct phy_device *phydev;
10040
10041                         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
10042
10043                         if (epause->rx_pause) {
10044                                 if (epause->tx_pause)
10045                                         newadv = ADVERTISED_Pause;
10046                                 else
10047                                         newadv = ADVERTISED_Pause |
10048                                                  ADVERTISED_Asym_Pause;
10049                         } else if (epause->tx_pause) {
10050                                 newadv = ADVERTISED_Asym_Pause;
10051                         } else
10052                                 newadv = 0;
10053
10054                         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
10055                                 u32 oldadv = phydev->advertising &
10056                                              (ADVERTISED_Pause |
10057                                               ADVERTISED_Asym_Pause);
10058                                 if (oldadv != newadv) {
10059                                         phydev->advertising &=
10060                                                 ~(ADVERTISED_Pause |
10061                                                   ADVERTISED_Asym_Pause);
10062                                         phydev->advertising |= newadv;
10063                                         err = phy_start_aneg(phydev);
10064                                 }
10065                         } else {
10066                                 tp->link_config.advertising &=
10067                                                 ~(ADVERTISED_Pause |
10068                                                   ADVERTISED_Asym_Pause);
10069                                 tp->link_config.advertising |= newadv;
10070                         }
10071                 } else {
10072                         if (epause->rx_pause)
10073                                 tp->link_config.flowctrl |= FLOW_CTRL_RX;
10074                         else
10075                                 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
10076
10077                         if (epause->tx_pause)
10078                                 tp->link_config.flowctrl |= FLOW_CTRL_TX;
10079                         else
10080                                 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
10081
10082                         if (netif_running(dev))
10083                                 tg3_setup_flow_control(tp, 0, 0);
10084                 }
10085         } else {
10086                 int irq_sync = 0;
10087
10088                 if (netif_running(dev)) {
10089                         tg3_netif_stop(tp);
10090                         irq_sync = 1;
10091                 }
10092
10093                 tg3_full_lock(tp, irq_sync);
10094
10095                 if (epause->autoneg)
10096                         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
10097                 else
10098                         tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
10099                 if (epause->rx_pause)
10100                         tp->link_config.flowctrl |= FLOW_CTRL_RX;
10101                 else
10102                         tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
10103                 if (epause->tx_pause)
10104                         tp->link_config.flowctrl |= FLOW_CTRL_TX;
10105                 else
10106                         tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
10107
10108                 if (netif_running(dev)) {
10109                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10110                         err = tg3_restart_hw(tp, 1);
10111                         if (!err)
10112                                 tg3_netif_start(tp);
10113                 }
10114
10115                 tg3_full_unlock(tp);
10116         }
10117
10118         return err;
10119 }
10120
10121 static u32 tg3_get_rx_csum(struct net_device *dev)
10122 {
10123         struct tg3 *tp = netdev_priv(dev);
10124         return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
10125 }
10126
10127 static int tg3_set_rx_csum(struct net_device *dev, u32 data)
10128 {
10129         struct tg3 *tp = netdev_priv(dev);
10130
10131         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
10132                 if (data != 0)
10133                         return -EINVAL;
10134                 return 0;
10135         }
10136
10137         spin_lock_bh(&tp->lock);
10138         if (data)
10139                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
10140         else
10141                 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
10142         spin_unlock_bh(&tp->lock);
10143
10144         return 0;
10145 }
10146
10147 static int tg3_set_tx_csum(struct net_device *dev, u32 data)
10148 {
10149         struct tg3 *tp = netdev_priv(dev);
10150
10151         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
10152                 if (data != 0)
10153                         return -EINVAL;
10154                 return 0;
10155         }
10156
10157         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10158                 ethtool_op_set_tx_ipv6_csum(dev, data);
10159         else
10160                 ethtool_op_set_tx_csum(dev, data);
10161
10162         return 0;
10163 }
10164
10165 static int tg3_get_sset_count (struct net_device *dev, int sset)
10166 {
10167         switch (sset) {
10168         case ETH_SS_TEST:
10169                 return TG3_NUM_TEST;
10170         case ETH_SS_STATS:
10171                 return TG3_NUM_STATS;
10172         default:
10173                 return -EOPNOTSUPP;
10174         }
10175 }
10176
10177 static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
10178 {
10179         switch (stringset) {
10180         case ETH_SS_STATS:
10181                 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
10182                 break;
10183         case ETH_SS_TEST:
10184                 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
10185                 break;
10186         default:
10187                 WARN_ON(1);     /* we need a WARN() */
10188                 break;
10189         }
10190 }
10191
10192 static int tg3_phys_id(struct net_device *dev, u32 data)
10193 {
10194         struct tg3 *tp = netdev_priv(dev);
10195         int i;
10196
10197         if (!netif_running(tp->dev))
10198                 return -EAGAIN;
10199
10200         if (data == 0)
10201                 data = UINT_MAX / 2;
10202
10203         for (i = 0; i < (data * 2); i++) {
10204                 if ((i % 2) == 0)
10205                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10206                                            LED_CTRL_1000MBPS_ON |
10207                                            LED_CTRL_100MBPS_ON |
10208                                            LED_CTRL_10MBPS_ON |
10209                                            LED_CTRL_TRAFFIC_OVERRIDE |
10210                                            LED_CTRL_TRAFFIC_BLINK |
10211                                            LED_CTRL_TRAFFIC_LED);
10212
10213                 else
10214                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10215                                            LED_CTRL_TRAFFIC_OVERRIDE);
10216
10217                 if (msleep_interruptible(500))
10218                         break;
10219         }
10220         tw32(MAC_LED_CTRL, tp->led_ctrl);
10221         return 0;
10222 }
10223
10224 static void tg3_get_ethtool_stats (struct net_device *dev,
10225                                    struct ethtool_stats *estats, u64 *tmp_stats)
10226 {
10227         struct tg3 *tp = netdev_priv(dev);
10228         memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
10229 }
10230
10231 #define NVRAM_TEST_SIZE 0x100
10232 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE   0x14
10233 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE   0x18
10234 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE   0x1c
10235 #define NVRAM_SELFBOOT_HW_SIZE 0x20
10236 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
10237
10238 static int tg3_test_nvram(struct tg3 *tp)
10239 {
10240         u32 csum, magic;
10241         __be32 *buf;
10242         int i, j, k, err = 0, size;
10243
10244         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
10245                 return 0;
10246
10247         if (tg3_nvram_read(tp, 0, &magic) != 0)
10248                 return -EIO;
10249
10250         if (magic == TG3_EEPROM_MAGIC)
10251                 size = NVRAM_TEST_SIZE;
10252         else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
10253                 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
10254                     TG3_EEPROM_SB_FORMAT_1) {
10255                         switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
10256                         case TG3_EEPROM_SB_REVISION_0:
10257                                 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
10258                                 break;
10259                         case TG3_EEPROM_SB_REVISION_2:
10260                                 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
10261                                 break;
10262                         case TG3_EEPROM_SB_REVISION_3:
10263                                 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
10264                                 break;
10265                         default:
10266                                 return 0;
10267                         }
10268                 } else
10269                         return 0;
10270         } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
10271                 size = NVRAM_SELFBOOT_HW_SIZE;
10272         else
10273                 return -EIO;
10274
10275         buf = kmalloc(size, GFP_KERNEL);
10276         if (buf == NULL)
10277                 return -ENOMEM;
10278
10279         err = -EIO;
10280         for (i = 0, j = 0; i < size; i += 4, j++) {
10281                 err = tg3_nvram_read_be32(tp, i, &buf[j]);
10282                 if (err)
10283                         break;
10284         }
10285         if (i < size)
10286                 goto out;
10287
10288         /* Selfboot format */
10289         magic = be32_to_cpu(buf[0]);
10290         if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
10291             TG3_EEPROM_MAGIC_FW) {
10292                 u8 *buf8 = (u8 *) buf, csum8 = 0;
10293
10294                 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
10295                     TG3_EEPROM_SB_REVISION_2) {
10296                         /* For rev 2, the csum doesn't include the MBA. */
10297                         for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
10298                                 csum8 += buf8[i];
10299                         for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
10300                                 csum8 += buf8[i];
10301                 } else {
10302                         for (i = 0; i < size; i++)
10303                                 csum8 += buf8[i];
10304                 }
10305
10306                 if (csum8 == 0) {
10307                         err = 0;
10308                         goto out;
10309                 }
10310
10311                 err = -EIO;
10312                 goto out;
10313         }
10314
10315         if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
10316             TG3_EEPROM_MAGIC_HW) {
10317                 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
10318                 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
10319                 u8 *buf8 = (u8 *) buf;
10320
10321                 /* Separate the parity bits and the data bytes.  */
10322                 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
10323                         if ((i == 0) || (i == 8)) {
10324                                 int l;
10325                                 u8 msk;
10326
10327                                 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
10328                                         parity[k++] = buf8[i] & msk;
10329                                 i++;
10330                         }
10331                         else if (i == 16) {
10332                                 int l;
10333                                 u8 msk;
10334
10335                                 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
10336                                         parity[k++] = buf8[i] & msk;
10337                                 i++;
10338
10339                                 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
10340                                         parity[k++] = buf8[i] & msk;
10341                                 i++;
10342                         }
10343                         data[j++] = buf8[i];
10344                 }
10345
10346                 err = -EIO;
10347                 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
10348                         u8 hw8 = hweight8(data[i]);
10349
10350                         if ((hw8 & 0x1) && parity[i])
10351                                 goto out;
10352                         else if (!(hw8 & 0x1) && !parity[i])
10353                                 goto out;
10354                 }
10355                 err = 0;
10356                 goto out;
10357         }
10358
10359         /* Bootstrap checksum at offset 0x10 */
10360         csum = calc_crc((unsigned char *) buf, 0x10);
10361         if (csum != be32_to_cpu(buf[0x10/4]))
10362                 goto out;
10363
10364         /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
10365         csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
10366         if (csum != be32_to_cpu(buf[0xfc/4]))
10367                 goto out;
10368
10369         err = 0;
10370
10371 out:
10372         kfree(buf);
10373         return err;
10374 }
10375
10376 #define TG3_SERDES_TIMEOUT_SEC  2
10377 #define TG3_COPPER_TIMEOUT_SEC  6
10378
10379 static int tg3_test_link(struct tg3 *tp)
10380 {
10381         int i, max;
10382
10383         if (!netif_running(tp->dev))
10384                 return -ENODEV;
10385
10386         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
10387                 max = TG3_SERDES_TIMEOUT_SEC;
10388         else
10389                 max = TG3_COPPER_TIMEOUT_SEC;
10390
10391         for (i = 0; i < max; i++) {
10392                 if (netif_carrier_ok(tp->dev))
10393                         return 0;
10394
10395                 if (msleep_interruptible(1000))
10396                         break;
10397         }
10398
10399         return -EIO;
10400 }
10401
10402 /* Only test the commonly used registers */
10403 static int tg3_test_registers(struct tg3 *tp)
10404 {
10405         int i, is_5705, is_5750;
10406         u32 offset, read_mask, write_mask, val, save_val, read_val;
10407         static struct {
10408                 u16 offset;
10409                 u16 flags;
10410 #define TG3_FL_5705     0x1
10411 #define TG3_FL_NOT_5705 0x2
10412 #define TG3_FL_NOT_5788 0x4
10413 #define TG3_FL_NOT_5750 0x8
10414                 u32 read_mask;
10415                 u32 write_mask;
10416         } reg_tbl[] = {
10417                 /* MAC Control Registers */
10418                 { MAC_MODE, TG3_FL_NOT_5705,
10419                         0x00000000, 0x00ef6f8c },
10420                 { MAC_MODE, TG3_FL_5705,
10421                         0x00000000, 0x01ef6b8c },
10422                 { MAC_STATUS, TG3_FL_NOT_5705,
10423                         0x03800107, 0x00000000 },
10424                 { MAC_STATUS, TG3_FL_5705,
10425                         0x03800100, 0x00000000 },
10426                 { MAC_ADDR_0_HIGH, 0x0000,
10427                         0x00000000, 0x0000ffff },
10428                 { MAC_ADDR_0_LOW, 0x0000,
10429                         0x00000000, 0xffffffff },
10430                 { MAC_RX_MTU_SIZE, 0x0000,
10431                         0x00000000, 0x0000ffff },
10432                 { MAC_TX_MODE, 0x0000,
10433                         0x00000000, 0x00000070 },
10434                 { MAC_TX_LENGTHS, 0x0000,
10435                         0x00000000, 0x00003fff },
10436                 { MAC_RX_MODE, TG3_FL_NOT_5705,
10437                         0x00000000, 0x000007fc },
10438                 { MAC_RX_MODE, TG3_FL_5705,
10439                         0x00000000, 0x000007dc },
10440                 { MAC_HASH_REG_0, 0x0000,
10441                         0x00000000, 0xffffffff },
10442                 { MAC_HASH_REG_1, 0x0000,
10443                         0x00000000, 0xffffffff },
10444                 { MAC_HASH_REG_2, 0x0000,
10445                         0x00000000, 0xffffffff },
10446                 { MAC_HASH_REG_3, 0x0000,
10447                         0x00000000, 0xffffffff },
10448
10449                 /* Receive Data and Receive BD Initiator Control Registers. */
10450                 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
10451                         0x00000000, 0xffffffff },
10452                 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
10453                         0x00000000, 0xffffffff },
10454                 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
10455                         0x00000000, 0x00000003 },
10456                 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
10457                         0x00000000, 0xffffffff },
10458                 { RCVDBDI_STD_BD+0, 0x0000,
10459                         0x00000000, 0xffffffff },
10460                 { RCVDBDI_STD_BD+4, 0x0000,
10461                         0x00000000, 0xffffffff },
10462                 { RCVDBDI_STD_BD+8, 0x0000,
10463                         0x00000000, 0xffff0002 },
10464                 { RCVDBDI_STD_BD+0xc, 0x0000,
10465                         0x00000000, 0xffffffff },
10466
10467                 /* Receive BD Initiator Control Registers. */
10468                 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
10469                         0x00000000, 0xffffffff },
10470                 { RCVBDI_STD_THRESH, TG3_FL_5705,
10471                         0x00000000, 0x000003ff },
10472                 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
10473                         0x00000000, 0xffffffff },
10474
10475                 /* Host Coalescing Control Registers. */
10476                 { HOSTCC_MODE, TG3_FL_NOT_5705,
10477                         0x00000000, 0x00000004 },
10478                 { HOSTCC_MODE, TG3_FL_5705,
10479                         0x00000000, 0x000000f6 },
10480                 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
10481                         0x00000000, 0xffffffff },
10482                 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
10483                         0x00000000, 0x000003ff },
10484                 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
10485                         0x00000000, 0xffffffff },
10486                 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
10487                         0x00000000, 0x000003ff },
10488                 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
10489                         0x00000000, 0xffffffff },
10490                 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10491                         0x00000000, 0x000000ff },
10492                 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
10493                         0x00000000, 0xffffffff },
10494                 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10495                         0x00000000, 0x000000ff },
10496                 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
10497                         0x00000000, 0xffffffff },
10498                 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
10499                         0x00000000, 0xffffffff },
10500                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10501                         0x00000000, 0xffffffff },
10502                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10503                         0x00000000, 0x000000ff },
10504                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10505                         0x00000000, 0xffffffff },
10506                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10507                         0x00000000, 0x000000ff },
10508                 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
10509                         0x00000000, 0xffffffff },
10510                 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
10511                         0x00000000, 0xffffffff },
10512                 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
10513                         0x00000000, 0xffffffff },
10514                 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
10515                         0x00000000, 0xffffffff },
10516                 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
10517                         0x00000000, 0xffffffff },
10518                 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
10519                         0xffffffff, 0x00000000 },
10520                 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
10521                         0xffffffff, 0x00000000 },
10522
10523                 /* Buffer Manager Control Registers. */
10524                 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
10525                         0x00000000, 0x007fff80 },
10526                 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
10527                         0x00000000, 0x007fffff },
10528                 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
10529                         0x00000000, 0x0000003f },
10530                 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
10531                         0x00000000, 0x000001ff },
10532                 { BUFMGR_MB_HIGH_WATER, 0x0000,
10533                         0x00000000, 0x000001ff },
10534                 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
10535                         0xffffffff, 0x00000000 },
10536                 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
10537                         0xffffffff, 0x00000000 },
10538
10539                 /* Mailbox Registers */
10540                 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
10541                         0x00000000, 0x000001ff },
10542                 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
10543                         0x00000000, 0x000001ff },
10544                 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
10545                         0x00000000, 0x000007ff },
10546                 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
10547                         0x00000000, 0x000001ff },
10548
10549                 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
10550         };
10551
10552         is_5705 = is_5750 = 0;
10553         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
10554                 is_5705 = 1;
10555                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10556                         is_5750 = 1;
10557         }
10558
10559         for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
10560                 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
10561                         continue;
10562
10563                 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
10564                         continue;
10565
10566                 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
10567                     (reg_tbl[i].flags & TG3_FL_NOT_5788))
10568                         continue;
10569
10570                 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
10571                         continue;
10572
10573                 offset = (u32) reg_tbl[i].offset;
10574                 read_mask = reg_tbl[i].read_mask;
10575                 write_mask = reg_tbl[i].write_mask;
10576
10577                 /* Save the original register content */
10578                 save_val = tr32(offset);
10579
10580                 /* Determine the read-only value. */
10581                 read_val = save_val & read_mask;
10582
10583                 /* Write zero to the register, then make sure the read-only bits
10584                  * are not changed and the read/write bits are all zeros.
10585                  */
10586                 tw32(offset, 0);
10587
10588                 val = tr32(offset);
10589
10590                 /* Test the read-only and read/write bits. */
10591                 if (((val & read_mask) != read_val) || (val & write_mask))
10592                         goto out;
10593
10594                 /* Write ones to all the bits defined by RdMask and WrMask, then
10595                  * make sure the read-only bits are not changed and the
10596                  * read/write bits are all ones.
10597                  */
10598                 tw32(offset, read_mask | write_mask);
10599
10600                 val = tr32(offset);
10601
10602                 /* Test the read-only bits. */
10603                 if ((val & read_mask) != read_val)
10604                         goto out;
10605
10606                 /* Test the read/write bits. */
10607                 if ((val & write_mask) != write_mask)
10608                         goto out;
10609
10610                 tw32(offset, save_val);
10611         }
10612
10613         return 0;
10614
10615 out:
10616         if (netif_msg_hw(tp))
10617                 printk(KERN_ERR PFX "Register test failed at offset %x\n",
10618                        offset);
10619         tw32(offset, save_val);
10620         return -EIO;
10621 }
10622
10623 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
10624 {
10625         static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
10626         int i;
10627         u32 j;
10628
10629         for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
10630                 for (j = 0; j < len; j += 4) {
10631                         u32 val;
10632
10633                         tg3_write_mem(tp, offset + j, test_pattern[i]);
10634                         tg3_read_mem(tp, offset + j, &val);
10635                         if (val != test_pattern[i])
10636                                 return -EIO;
10637                 }
10638         }
10639         return 0;
10640 }
10641
10642 static int tg3_test_memory(struct tg3 *tp)
10643 {
10644         static struct mem_entry {
10645                 u32 offset;
10646                 u32 len;
10647         } mem_tbl_570x[] = {
10648                 { 0x00000000, 0x00b50},
10649                 { 0x00002000, 0x1c000},
10650                 { 0xffffffff, 0x00000}
10651         }, mem_tbl_5705[] = {
10652                 { 0x00000100, 0x0000c},
10653                 { 0x00000200, 0x00008},
10654                 { 0x00004000, 0x00800},
10655                 { 0x00006000, 0x01000},
10656                 { 0x00008000, 0x02000},
10657                 { 0x00010000, 0x0e000},
10658                 { 0xffffffff, 0x00000}
10659         }, mem_tbl_5755[] = {
10660                 { 0x00000200, 0x00008},
10661                 { 0x00004000, 0x00800},
10662                 { 0x00006000, 0x00800},
10663                 { 0x00008000, 0x02000},
10664                 { 0x00010000, 0x0c000},
10665                 { 0xffffffff, 0x00000}
10666         }, mem_tbl_5906[] = {
10667                 { 0x00000200, 0x00008},
10668                 { 0x00004000, 0x00400},
10669                 { 0x00006000, 0x00400},
10670                 { 0x00008000, 0x01000},
10671                 { 0x00010000, 0x01000},
10672                 { 0xffffffff, 0x00000}
10673         }, mem_tbl_5717[] = {
10674                 { 0x00000200, 0x00008},
10675                 { 0x00010000, 0x0a000},
10676                 { 0x00020000, 0x13c00},
10677                 { 0xffffffff, 0x00000}
10678         }, mem_tbl_57765[] = {
10679                 { 0x00000200, 0x00008},
10680                 { 0x00004000, 0x00800},
10681                 { 0x00006000, 0x09800},
10682                 { 0x00010000, 0x0a000},
10683                 { 0xffffffff, 0x00000}
10684         };
10685         struct mem_entry *mem_tbl;
10686         int err = 0;
10687         int i;
10688
10689         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
10690                 mem_tbl = mem_tbl_5717;
10691         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
10692                 mem_tbl = mem_tbl_57765;
10693         else if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10694                 mem_tbl = mem_tbl_5755;
10695         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10696                 mem_tbl = mem_tbl_5906;
10697         else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
10698                 mem_tbl = mem_tbl_5705;
10699         else
10700                 mem_tbl = mem_tbl_570x;
10701
10702         for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
10703                 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
10704                     mem_tbl[i].len)) != 0)
10705                         break;
10706         }
10707
10708         return err;
10709 }
10710
10711 #define TG3_MAC_LOOPBACK        0
10712 #define TG3_PHY_LOOPBACK        1
10713
10714 static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
10715 {
10716         u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
10717         u32 desc_idx, coal_now;
10718         struct sk_buff *skb, *rx_skb;
10719         u8 *tx_data;
10720         dma_addr_t map;
10721         int num_pkts, tx_len, rx_len, i, err;
10722         struct tg3_rx_buffer_desc *desc;
10723         struct tg3_napi *tnapi, *rnapi;
10724         struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
10725
10726         if (tp->irq_cnt > 1) {
10727                 tnapi = &tp->napi[1];
10728                 rnapi = &tp->napi[1];
10729         } else {
10730                 tnapi = &tp->napi[0];
10731                 rnapi = &tp->napi[0];
10732         }
10733         coal_now = tnapi->coal_now | rnapi->coal_now;
10734
10735         if (loopback_mode == TG3_MAC_LOOPBACK) {
10736                 /* HW errata - mac loopback fails in some cases on 5780.
10737                  * Normal traffic and PHY loopback are not affected by
10738                  * errata.
10739                  */
10740                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
10741                         return 0;
10742
10743                 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
10744                            MAC_MODE_PORT_INT_LPBACK;
10745                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10746                         mac_mode |= MAC_MODE_LINK_POLARITY;
10747                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
10748                         mac_mode |= MAC_MODE_PORT_MODE_MII;
10749                 else
10750                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
10751                 tw32(MAC_MODE, mac_mode);
10752         } else if (loopback_mode == TG3_PHY_LOOPBACK) {
10753                 u32 val;
10754
10755                 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
10756                         tg3_phy_fet_toggle_apd(tp, false);
10757                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
10758                 } else
10759                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
10760
10761                 tg3_phy_toggle_automdix(tp, 0);
10762
10763                 tg3_writephy(tp, MII_BMCR, val);
10764                 udelay(40);
10765
10766                 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
10767                 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
10768                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10769                                 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x1800);
10770                         mac_mode |= MAC_MODE_PORT_MODE_MII;
10771                 } else
10772                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
10773
10774                 /* reset to prevent losing 1st rx packet intermittently */
10775                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
10776                         tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10777                         udelay(10);
10778                         tw32_f(MAC_RX_MODE, tp->rx_mode);
10779                 }
10780                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
10781                         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)
10782                                 mac_mode &= ~MAC_MODE_LINK_POLARITY;
10783                         else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411)
10784                                 mac_mode |= MAC_MODE_LINK_POLARITY;
10785                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
10786                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
10787                 }
10788                 tw32(MAC_MODE, mac_mode);
10789         }
10790         else
10791                 return -EINVAL;
10792
10793         err = -EIO;
10794
10795         tx_len = 1514;
10796         skb = netdev_alloc_skb(tp->dev, tx_len);
10797         if (!skb)
10798                 return -ENOMEM;
10799
10800         tx_data = skb_put(skb, tx_len);
10801         memcpy(tx_data, tp->dev->dev_addr, 6);
10802         memset(tx_data + 6, 0x0, 8);
10803
10804         tw32(MAC_RX_MTU_SIZE, tx_len + 4);
10805
10806         for (i = 14; i < tx_len; i++)
10807                 tx_data[i] = (u8) (i & 0xff);
10808
10809         map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
10810         if (pci_dma_mapping_error(tp->pdev, map)) {
10811                 dev_kfree_skb(skb);
10812                 return -EIO;
10813         }
10814
10815         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10816                rnapi->coal_now);
10817
10818         udelay(10);
10819
10820         rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
10821
10822         num_pkts = 0;
10823
10824         tg3_set_txd(tnapi, tnapi->tx_prod, map, tx_len, 0, 1);
10825
10826         tnapi->tx_prod++;
10827         num_pkts++;
10828
10829         tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
10830         tr32_mailbox(tnapi->prodmbox);
10831
10832         udelay(10);
10833
10834         /* 350 usec to allow enough time on some 10/100 Mbps devices.  */
10835         for (i = 0; i < 35; i++) {
10836                 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10837                        coal_now);
10838
10839                 udelay(10);
10840
10841                 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
10842                 rx_idx = rnapi->hw_status->idx[0].rx_producer;
10843                 if ((tx_idx == tnapi->tx_prod) &&
10844                     (rx_idx == (rx_start_idx + num_pkts)))
10845                         break;
10846         }
10847
10848         pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
10849         dev_kfree_skb(skb);
10850
10851         if (tx_idx != tnapi->tx_prod)
10852                 goto out;
10853
10854         if (rx_idx != rx_start_idx + num_pkts)
10855                 goto out;
10856
10857         desc = &rnapi->rx_rcb[rx_start_idx];
10858         desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
10859         opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
10860         if (opaque_key != RXD_OPAQUE_RING_STD)
10861                 goto out;
10862
10863         if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
10864             (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
10865                 goto out;
10866
10867         rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
10868         if (rx_len != tx_len)
10869                 goto out;
10870
10871         rx_skb = tpr->rx_std_buffers[desc_idx].skb;
10872
10873         map = pci_unmap_addr(&tpr->rx_std_buffers[desc_idx], mapping);
10874         pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
10875
10876         for (i = 14; i < tx_len; i++) {
10877                 if (*(rx_skb->data + i) != (u8) (i & 0xff))
10878                         goto out;
10879         }
10880         err = 0;
10881
10882         /* tg3_free_rings will unmap and free the rx_skb */
10883 out:
10884         return err;
10885 }
10886
10887 #define TG3_MAC_LOOPBACK_FAILED         1
10888 #define TG3_PHY_LOOPBACK_FAILED         2
10889 #define TG3_LOOPBACK_FAILED             (TG3_MAC_LOOPBACK_FAILED |      \
10890                                          TG3_PHY_LOOPBACK_FAILED)
10891
10892 static int tg3_test_loopback(struct tg3 *tp)
10893 {
10894         int err = 0;
10895         u32 cpmuctrl = 0;
10896
10897         if (!netif_running(tp->dev))
10898                 return TG3_LOOPBACK_FAILED;
10899
10900         err = tg3_reset_hw(tp, 1);
10901         if (err)
10902                 return TG3_LOOPBACK_FAILED;
10903
10904         /* Turn off gphy autopowerdown. */
10905         if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10906                 tg3_phy_toggle_apd(tp, false);
10907
10908         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
10909                 int i;
10910                 u32 status;
10911
10912                 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
10913
10914                 /* Wait for up to 40 microseconds to acquire lock. */
10915                 for (i = 0; i < 4; i++) {
10916                         status = tr32(TG3_CPMU_MUTEX_GNT);
10917                         if (status == CPMU_MUTEX_GNT_DRIVER)
10918                                 break;
10919                         udelay(10);
10920                 }
10921
10922                 if (status != CPMU_MUTEX_GNT_DRIVER)
10923                         return TG3_LOOPBACK_FAILED;
10924
10925                 /* Turn off link-based power management. */
10926                 cpmuctrl = tr32(TG3_CPMU_CTRL);
10927                 tw32(TG3_CPMU_CTRL,
10928                      cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
10929                                   CPMU_CTRL_LINK_AWARE_MODE));
10930         }
10931
10932         if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
10933                 err |= TG3_MAC_LOOPBACK_FAILED;
10934
10935         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
10936                 tw32(TG3_CPMU_CTRL, cpmuctrl);
10937
10938                 /* Release the mutex */
10939                 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
10940         }
10941
10942         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
10943             !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
10944                 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
10945                         err |= TG3_PHY_LOOPBACK_FAILED;
10946         }
10947
10948         /* Re-enable gphy autopowerdown. */
10949         if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10950                 tg3_phy_toggle_apd(tp, true);
10951
10952         return err;
10953 }
10954
10955 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
10956                           u64 *data)
10957 {
10958         struct tg3 *tp = netdev_priv(dev);
10959
10960         if (tp->link_config.phy_is_low_power)
10961                 tg3_set_power_state(tp, PCI_D0);
10962
10963         memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
10964
10965         if (tg3_test_nvram(tp) != 0) {
10966                 etest->flags |= ETH_TEST_FL_FAILED;
10967                 data[0] = 1;
10968         }
10969         if (tg3_test_link(tp) != 0) {
10970                 etest->flags |= ETH_TEST_FL_FAILED;
10971                 data[1] = 1;
10972         }
10973         if (etest->flags & ETH_TEST_FL_OFFLINE) {
10974                 int err, err2 = 0, irq_sync = 0;
10975
10976                 if (netif_running(dev)) {
10977                         tg3_phy_stop(tp);
10978                         tg3_netif_stop(tp);
10979                         irq_sync = 1;
10980                 }
10981
10982                 tg3_full_lock(tp, irq_sync);
10983
10984                 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
10985                 err = tg3_nvram_lock(tp);
10986                 tg3_halt_cpu(tp, RX_CPU_BASE);
10987                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10988                         tg3_halt_cpu(tp, TX_CPU_BASE);
10989                 if (!err)
10990                         tg3_nvram_unlock(tp);
10991
10992                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
10993                         tg3_phy_reset(tp);
10994
10995                 if (tg3_test_registers(tp) != 0) {
10996                         etest->flags |= ETH_TEST_FL_FAILED;
10997                         data[2] = 1;
10998                 }
10999                 if (tg3_test_memory(tp) != 0) {
11000                         etest->flags |= ETH_TEST_FL_FAILED;
11001                         data[3] = 1;
11002                 }
11003                 if ((data[4] = tg3_test_loopback(tp)) != 0)
11004                         etest->flags |= ETH_TEST_FL_FAILED;
11005
11006                 tg3_full_unlock(tp);
11007
11008                 if (tg3_test_interrupt(tp) != 0) {
11009                         etest->flags |= ETH_TEST_FL_FAILED;
11010                         data[5] = 1;
11011                 }
11012
11013                 tg3_full_lock(tp, 0);
11014
11015                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11016                 if (netif_running(dev)) {
11017                         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
11018                         err2 = tg3_restart_hw(tp, 1);
11019                         if (!err2)
11020                                 tg3_netif_start(tp);
11021                 }
11022
11023                 tg3_full_unlock(tp);
11024
11025                 if (irq_sync && !err2)
11026                         tg3_phy_start(tp);
11027         }
11028         if (tp->link_config.phy_is_low_power)
11029                 tg3_set_power_state(tp, PCI_D3hot);
11030
11031 }
11032
11033 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
11034 {
11035         struct mii_ioctl_data *data = if_mii(ifr);
11036         struct tg3 *tp = netdev_priv(dev);
11037         int err;
11038
11039         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
11040                 struct phy_device *phydev;
11041                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
11042                         return -EAGAIN;
11043                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
11044                 return phy_mii_ioctl(phydev, data, cmd);
11045         }
11046
11047         switch(cmd) {
11048         case SIOCGMIIPHY:
11049                 data->phy_id = tp->phy_addr;
11050
11051                 /* fallthru */
11052         case SIOCGMIIREG: {
11053                 u32 mii_regval;
11054
11055                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
11056                         break;                  /* We have no PHY */
11057
11058                 if (tp->link_config.phy_is_low_power)
11059                         return -EAGAIN;
11060
11061                 spin_lock_bh(&tp->lock);
11062                 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
11063                 spin_unlock_bh(&tp->lock);
11064
11065                 data->val_out = mii_regval;
11066
11067                 return err;
11068         }
11069
11070         case SIOCSMIIREG:
11071                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
11072                         break;                  /* We have no PHY */
11073
11074                 if (tp->link_config.phy_is_low_power)
11075                         return -EAGAIN;
11076
11077                 spin_lock_bh(&tp->lock);
11078                 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
11079                 spin_unlock_bh(&tp->lock);
11080
11081                 return err;
11082
11083         default:
11084                 /* do nothing */
11085                 break;
11086         }
11087         return -EOPNOTSUPP;
11088 }
11089
11090 #if TG3_VLAN_TAG_USED
11091 static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
11092 {
11093         struct tg3 *tp = netdev_priv(dev);
11094
11095         if (!netif_running(dev)) {
11096                 tp->vlgrp = grp;
11097                 return;
11098         }
11099
11100         tg3_netif_stop(tp);
11101
11102         tg3_full_lock(tp, 0);
11103
11104         tp->vlgrp = grp;
11105
11106         /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
11107         __tg3_set_rx_mode(dev);
11108
11109         tg3_netif_start(tp);
11110
11111         tg3_full_unlock(tp);
11112 }
11113 #endif
11114
11115 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11116 {
11117         struct tg3 *tp = netdev_priv(dev);
11118
11119         memcpy(ec, &tp->coal, sizeof(*ec));
11120         return 0;
11121 }
11122
11123 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11124 {
11125         struct tg3 *tp = netdev_priv(dev);
11126         u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
11127         u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
11128
11129         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
11130                 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
11131                 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
11132                 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
11133                 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
11134         }
11135
11136         if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
11137             (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
11138             (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
11139             (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
11140             (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
11141             (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
11142             (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
11143             (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
11144             (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
11145             (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
11146                 return -EINVAL;
11147
11148         /* No rx interrupts will be generated if both are zero */
11149         if ((ec->rx_coalesce_usecs == 0) &&
11150             (ec->rx_max_coalesced_frames == 0))
11151                 return -EINVAL;
11152
11153         /* No tx interrupts will be generated if both are zero */
11154         if ((ec->tx_coalesce_usecs == 0) &&
11155             (ec->tx_max_coalesced_frames == 0))
11156                 return -EINVAL;
11157
11158         /* Only copy relevant parameters, ignore all others. */
11159         tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
11160         tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
11161         tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
11162         tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
11163         tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
11164         tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
11165         tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
11166         tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
11167         tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
11168
11169         if (netif_running(dev)) {
11170                 tg3_full_lock(tp, 0);
11171                 __tg3_set_coalesce(tp, &tp->coal);
11172                 tg3_full_unlock(tp);
11173         }
11174         return 0;
11175 }
11176
11177 static const struct ethtool_ops tg3_ethtool_ops = {
11178         .get_settings           = tg3_get_settings,
11179         .set_settings           = tg3_set_settings,
11180         .get_drvinfo            = tg3_get_drvinfo,
11181         .get_regs_len           = tg3_get_regs_len,
11182         .get_regs               = tg3_get_regs,
11183         .get_wol                = tg3_get_wol,
11184         .set_wol                = tg3_set_wol,
11185         .get_msglevel           = tg3_get_msglevel,
11186         .set_msglevel           = tg3_set_msglevel,
11187         .nway_reset             = tg3_nway_reset,
11188         .get_link               = ethtool_op_get_link,
11189         .get_eeprom_len         = tg3_get_eeprom_len,
11190         .get_eeprom             = tg3_get_eeprom,
11191         .set_eeprom             = tg3_set_eeprom,
11192         .get_ringparam          = tg3_get_ringparam,
11193         .set_ringparam          = tg3_set_ringparam,
11194         .get_pauseparam         = tg3_get_pauseparam,
11195         .set_pauseparam         = tg3_set_pauseparam,
11196         .get_rx_csum            = tg3_get_rx_csum,
11197         .set_rx_csum            = tg3_set_rx_csum,
11198         .set_tx_csum            = tg3_set_tx_csum,
11199         .set_sg                 = ethtool_op_set_sg,
11200         .set_tso                = tg3_set_tso,
11201         .self_test              = tg3_self_test,
11202         .get_strings            = tg3_get_strings,
11203         .phys_id                = tg3_phys_id,
11204         .get_ethtool_stats      = tg3_get_ethtool_stats,
11205         .get_coalesce           = tg3_get_coalesce,
11206         .set_coalesce           = tg3_set_coalesce,
11207         .get_sset_count         = tg3_get_sset_count,
11208 };
11209
11210 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
11211 {
11212         u32 cursize, val, magic;
11213
11214         tp->nvram_size = EEPROM_CHIP_SIZE;
11215
11216         if (tg3_nvram_read(tp, 0, &magic) != 0)
11217                 return;
11218
11219         if ((magic != TG3_EEPROM_MAGIC) &&
11220             ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
11221             ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
11222                 return;
11223
11224         /*
11225          * Size the chip by reading offsets at increasing powers of two.
11226          * When we encounter our validation signature, we know the addressing
11227          * has wrapped around, and thus have our chip size.
11228          */
11229         cursize = 0x10;
11230
11231         while (cursize < tp->nvram_size) {
11232                 if (tg3_nvram_read(tp, cursize, &val) != 0)
11233                         return;
11234
11235                 if (val == magic)
11236                         break;
11237
11238                 cursize <<= 1;
11239         }
11240
11241         tp->nvram_size = cursize;
11242 }
11243
11244 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
11245 {
11246         u32 val;
11247
11248         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
11249             tg3_nvram_read(tp, 0, &val) != 0)
11250                 return;
11251
11252         /* Selfboot format */
11253         if (val != TG3_EEPROM_MAGIC) {
11254                 tg3_get_eeprom_size(tp);
11255                 return;
11256         }
11257
11258         if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
11259                 if (val != 0) {
11260                         /* This is confusing.  We want to operate on the
11261                          * 16-bit value at offset 0xf2.  The tg3_nvram_read()
11262                          * call will read from NVRAM and byteswap the data
11263                          * according to the byteswapping settings for all
11264                          * other register accesses.  This ensures the data we
11265                          * want will always reside in the lower 16-bits.
11266                          * However, the data in NVRAM is in LE format, which
11267                          * means the data from the NVRAM read will always be
11268                          * opposite the endianness of the CPU.  The 16-bit
11269                          * byteswap then brings the data to CPU endianness.
11270                          */
11271                         tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
11272                         return;
11273                 }
11274         }
11275         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11276 }
11277
11278 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
11279 {
11280         u32 nvcfg1;
11281
11282         nvcfg1 = tr32(NVRAM_CFG1);
11283         if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
11284                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11285         } else {
11286                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11287                 tw32(NVRAM_CFG1, nvcfg1);
11288         }
11289
11290         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
11291             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
11292                 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
11293                 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
11294                         tp->nvram_jedecnum = JEDEC_ATMEL;
11295                         tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11296                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11297                         break;
11298                 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
11299                         tp->nvram_jedecnum = JEDEC_ATMEL;
11300                         tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
11301                         break;
11302                 case FLASH_VENDOR_ATMEL_EEPROM:
11303                         tp->nvram_jedecnum = JEDEC_ATMEL;
11304                         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11305                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11306                         break;
11307                 case FLASH_VENDOR_ST:
11308                         tp->nvram_jedecnum = JEDEC_ST;
11309                         tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
11310                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11311                         break;
11312                 case FLASH_VENDOR_SAIFUN:
11313                         tp->nvram_jedecnum = JEDEC_SAIFUN;
11314                         tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
11315                         break;
11316                 case FLASH_VENDOR_SST_SMALL:
11317                 case FLASH_VENDOR_SST_LARGE:
11318                         tp->nvram_jedecnum = JEDEC_SST;
11319                         tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
11320                         break;
11321                 }
11322         } else {
11323                 tp->nvram_jedecnum = JEDEC_ATMEL;
11324                 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11325                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11326         }
11327 }
11328
11329 static void __devinit tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
11330 {
11331         switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
11332         case FLASH_5752PAGE_SIZE_256:
11333                 tp->nvram_pagesize = 256;
11334                 break;
11335         case FLASH_5752PAGE_SIZE_512:
11336                 tp->nvram_pagesize = 512;
11337                 break;
11338         case FLASH_5752PAGE_SIZE_1K:
11339                 tp->nvram_pagesize = 1024;
11340                 break;
11341         case FLASH_5752PAGE_SIZE_2K:
11342                 tp->nvram_pagesize = 2048;
11343                 break;
11344         case FLASH_5752PAGE_SIZE_4K:
11345                 tp->nvram_pagesize = 4096;
11346                 break;
11347         case FLASH_5752PAGE_SIZE_264:
11348                 tp->nvram_pagesize = 264;
11349                 break;
11350         case FLASH_5752PAGE_SIZE_528:
11351                 tp->nvram_pagesize = 528;
11352                 break;
11353         }
11354 }
11355
11356 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
11357 {
11358         u32 nvcfg1;
11359
11360         nvcfg1 = tr32(NVRAM_CFG1);
11361
11362         /* NVRAM protection for TPM */
11363         if (nvcfg1 & (1 << 27))
11364                 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11365
11366         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11367         case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
11368         case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
11369                 tp->nvram_jedecnum = JEDEC_ATMEL;
11370                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11371                 break;
11372         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11373                 tp->nvram_jedecnum = JEDEC_ATMEL;
11374                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11375                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11376                 break;
11377         case FLASH_5752VENDOR_ST_M45PE10:
11378         case FLASH_5752VENDOR_ST_M45PE20:
11379         case FLASH_5752VENDOR_ST_M45PE40:
11380                 tp->nvram_jedecnum = JEDEC_ST;
11381                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11382                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11383                 break;
11384         }
11385
11386         if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
11387                 tg3_nvram_get_pagesize(tp, nvcfg1);
11388         } else {
11389                 /* For eeprom, set pagesize to maximum eeprom size */
11390                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11391
11392                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11393                 tw32(NVRAM_CFG1, nvcfg1);
11394         }
11395 }
11396
11397 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
11398 {
11399         u32 nvcfg1, protect = 0;
11400
11401         nvcfg1 = tr32(NVRAM_CFG1);
11402
11403         /* NVRAM protection for TPM */
11404         if (nvcfg1 & (1 << 27)) {
11405                 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11406                 protect = 1;
11407         }
11408
11409         nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11410         switch (nvcfg1) {
11411         case FLASH_5755VENDOR_ATMEL_FLASH_1:
11412         case FLASH_5755VENDOR_ATMEL_FLASH_2:
11413         case FLASH_5755VENDOR_ATMEL_FLASH_3:
11414         case FLASH_5755VENDOR_ATMEL_FLASH_5:
11415                 tp->nvram_jedecnum = JEDEC_ATMEL;
11416                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11417                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11418                 tp->nvram_pagesize = 264;
11419                 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
11420                     nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
11421                         tp->nvram_size = (protect ? 0x3e200 :
11422                                           TG3_NVRAM_SIZE_512KB);
11423                 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
11424                         tp->nvram_size = (protect ? 0x1f200 :
11425                                           TG3_NVRAM_SIZE_256KB);
11426                 else
11427                         tp->nvram_size = (protect ? 0x1f200 :
11428                                           TG3_NVRAM_SIZE_128KB);
11429                 break;
11430         case FLASH_5752VENDOR_ST_M45PE10:
11431         case FLASH_5752VENDOR_ST_M45PE20:
11432         case FLASH_5752VENDOR_ST_M45PE40:
11433                 tp->nvram_jedecnum = JEDEC_ST;
11434                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11435                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11436                 tp->nvram_pagesize = 256;
11437                 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
11438                         tp->nvram_size = (protect ?
11439                                           TG3_NVRAM_SIZE_64KB :
11440                                           TG3_NVRAM_SIZE_128KB);
11441                 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
11442                         tp->nvram_size = (protect ?
11443                                           TG3_NVRAM_SIZE_64KB :
11444                                           TG3_NVRAM_SIZE_256KB);
11445                 else
11446                         tp->nvram_size = (protect ?
11447                                           TG3_NVRAM_SIZE_128KB :
11448                                           TG3_NVRAM_SIZE_512KB);
11449                 break;
11450         }
11451 }
11452
11453 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
11454 {
11455         u32 nvcfg1;
11456
11457         nvcfg1 = tr32(NVRAM_CFG1);
11458
11459         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11460         case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
11461         case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11462         case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
11463         case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11464                 tp->nvram_jedecnum = JEDEC_ATMEL;
11465                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11466                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11467
11468                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11469                 tw32(NVRAM_CFG1, nvcfg1);
11470                 break;
11471         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11472         case FLASH_5755VENDOR_ATMEL_FLASH_1:
11473         case FLASH_5755VENDOR_ATMEL_FLASH_2:
11474         case FLASH_5755VENDOR_ATMEL_FLASH_3:
11475                 tp->nvram_jedecnum = JEDEC_ATMEL;
11476                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11477                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11478                 tp->nvram_pagesize = 264;
11479                 break;
11480         case FLASH_5752VENDOR_ST_M45PE10:
11481         case FLASH_5752VENDOR_ST_M45PE20:
11482         case FLASH_5752VENDOR_ST_M45PE40:
11483                 tp->nvram_jedecnum = JEDEC_ST;
11484                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11485                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11486                 tp->nvram_pagesize = 256;
11487                 break;
11488         }
11489 }
11490
11491 static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
11492 {
11493         u32 nvcfg1, protect = 0;
11494
11495         nvcfg1 = tr32(NVRAM_CFG1);
11496
11497         /* NVRAM protection for TPM */
11498         if (nvcfg1 & (1 << 27)) {
11499                 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11500                 protect = 1;
11501         }
11502
11503         nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11504         switch (nvcfg1) {
11505         case FLASH_5761VENDOR_ATMEL_ADB021D:
11506         case FLASH_5761VENDOR_ATMEL_ADB041D:
11507         case FLASH_5761VENDOR_ATMEL_ADB081D:
11508         case FLASH_5761VENDOR_ATMEL_ADB161D:
11509         case FLASH_5761VENDOR_ATMEL_MDB021D:
11510         case FLASH_5761VENDOR_ATMEL_MDB041D:
11511         case FLASH_5761VENDOR_ATMEL_MDB081D:
11512         case FLASH_5761VENDOR_ATMEL_MDB161D:
11513                 tp->nvram_jedecnum = JEDEC_ATMEL;
11514                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11515                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11516                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11517                 tp->nvram_pagesize = 256;
11518                 break;
11519         case FLASH_5761VENDOR_ST_A_M45PE20:
11520         case FLASH_5761VENDOR_ST_A_M45PE40:
11521         case FLASH_5761VENDOR_ST_A_M45PE80:
11522         case FLASH_5761VENDOR_ST_A_M45PE16:
11523         case FLASH_5761VENDOR_ST_M_M45PE20:
11524         case FLASH_5761VENDOR_ST_M_M45PE40:
11525         case FLASH_5761VENDOR_ST_M_M45PE80:
11526         case FLASH_5761VENDOR_ST_M_M45PE16:
11527                 tp->nvram_jedecnum = JEDEC_ST;
11528                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11529                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11530                 tp->nvram_pagesize = 256;
11531                 break;
11532         }
11533
11534         if (protect) {
11535                 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
11536         } else {
11537                 switch (nvcfg1) {
11538                 case FLASH_5761VENDOR_ATMEL_ADB161D:
11539                 case FLASH_5761VENDOR_ATMEL_MDB161D:
11540                 case FLASH_5761VENDOR_ST_A_M45PE16:
11541                 case FLASH_5761VENDOR_ST_M_M45PE16:
11542                         tp->nvram_size = TG3_NVRAM_SIZE_2MB;
11543                         break;
11544                 case FLASH_5761VENDOR_ATMEL_ADB081D:
11545                 case FLASH_5761VENDOR_ATMEL_MDB081D:
11546                 case FLASH_5761VENDOR_ST_A_M45PE80:
11547                 case FLASH_5761VENDOR_ST_M_M45PE80:
11548                         tp->nvram_size = TG3_NVRAM_SIZE_1MB;
11549                         break;
11550                 case FLASH_5761VENDOR_ATMEL_ADB041D:
11551                 case FLASH_5761VENDOR_ATMEL_MDB041D:
11552                 case FLASH_5761VENDOR_ST_A_M45PE40:
11553                 case FLASH_5761VENDOR_ST_M_M45PE40:
11554                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11555                         break;
11556                 case FLASH_5761VENDOR_ATMEL_ADB021D:
11557                 case FLASH_5761VENDOR_ATMEL_MDB021D:
11558                 case FLASH_5761VENDOR_ST_A_M45PE20:
11559                 case FLASH_5761VENDOR_ST_M_M45PE20:
11560                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11561                         break;
11562                 }
11563         }
11564 }
11565
11566 static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
11567 {
11568         tp->nvram_jedecnum = JEDEC_ATMEL;
11569         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11570         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11571 }
11572
11573 static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
11574 {
11575         u32 nvcfg1;
11576
11577         nvcfg1 = tr32(NVRAM_CFG1);
11578
11579         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11580         case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11581         case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11582                 tp->nvram_jedecnum = JEDEC_ATMEL;
11583                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11584                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11585
11586                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11587                 tw32(NVRAM_CFG1, nvcfg1);
11588                 return;
11589         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11590         case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11591         case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11592         case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11593         case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11594         case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11595         case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11596                 tp->nvram_jedecnum = JEDEC_ATMEL;
11597                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11598                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11599
11600                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11601                 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11602                 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11603                 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11604                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11605                         break;
11606                 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11607                 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11608                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11609                         break;
11610                 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11611                 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11612                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11613                         break;
11614                 }
11615                 break;
11616         case FLASH_5752VENDOR_ST_M45PE10:
11617         case FLASH_5752VENDOR_ST_M45PE20:
11618         case FLASH_5752VENDOR_ST_M45PE40:
11619                 tp->nvram_jedecnum = JEDEC_ST;
11620                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11621                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11622
11623                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11624                 case FLASH_5752VENDOR_ST_M45PE10:
11625                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11626                         break;
11627                 case FLASH_5752VENDOR_ST_M45PE20:
11628                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11629                         break;
11630                 case FLASH_5752VENDOR_ST_M45PE40:
11631                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11632                         break;
11633                 }
11634                 break;
11635         default:
11636                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11637                 return;
11638         }
11639
11640         tg3_nvram_get_pagesize(tp, nvcfg1);
11641         if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11642                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11643 }
11644
11645
11646 static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp)
11647 {
11648         u32 nvcfg1;
11649
11650         nvcfg1 = tr32(NVRAM_CFG1);
11651
11652         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11653         case FLASH_5717VENDOR_ATMEL_EEPROM:
11654         case FLASH_5717VENDOR_MICRO_EEPROM:
11655                 tp->nvram_jedecnum = JEDEC_ATMEL;
11656                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11657                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11658
11659                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11660                 tw32(NVRAM_CFG1, nvcfg1);
11661                 return;
11662         case FLASH_5717VENDOR_ATMEL_MDB011D:
11663         case FLASH_5717VENDOR_ATMEL_ADB011B:
11664         case FLASH_5717VENDOR_ATMEL_ADB011D:
11665         case FLASH_5717VENDOR_ATMEL_MDB021D:
11666         case FLASH_5717VENDOR_ATMEL_ADB021B:
11667         case FLASH_5717VENDOR_ATMEL_ADB021D:
11668         case FLASH_5717VENDOR_ATMEL_45USPT:
11669                 tp->nvram_jedecnum = JEDEC_ATMEL;
11670                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11671                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11672
11673                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11674                 case FLASH_5717VENDOR_ATMEL_MDB021D:
11675                 case FLASH_5717VENDOR_ATMEL_ADB021B:
11676                 case FLASH_5717VENDOR_ATMEL_ADB021D:
11677                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11678                         break;
11679                 default:
11680                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11681                         break;
11682                 }
11683                 break;
11684         case FLASH_5717VENDOR_ST_M_M25PE10:
11685         case FLASH_5717VENDOR_ST_A_M25PE10:
11686         case FLASH_5717VENDOR_ST_M_M45PE10:
11687         case FLASH_5717VENDOR_ST_A_M45PE10:
11688         case FLASH_5717VENDOR_ST_M_M25PE20:
11689         case FLASH_5717VENDOR_ST_A_M25PE20:
11690         case FLASH_5717VENDOR_ST_M_M45PE20:
11691         case FLASH_5717VENDOR_ST_A_M45PE20:
11692         case FLASH_5717VENDOR_ST_25USPT:
11693         case FLASH_5717VENDOR_ST_45USPT:
11694                 tp->nvram_jedecnum = JEDEC_ST;
11695                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11696                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11697
11698                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11699                 case FLASH_5717VENDOR_ST_M_M25PE20:
11700                 case FLASH_5717VENDOR_ST_A_M25PE20:
11701                 case FLASH_5717VENDOR_ST_M_M45PE20:
11702                 case FLASH_5717VENDOR_ST_A_M45PE20:
11703                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11704                         break;
11705                 default:
11706                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11707                         break;
11708                 }
11709                 break;
11710         default:
11711                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11712                 return;
11713         }
11714
11715         tg3_nvram_get_pagesize(tp, nvcfg1);
11716         if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11717                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11718 }
11719
11720 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
11721 static void __devinit tg3_nvram_init(struct tg3 *tp)
11722 {
11723         tw32_f(GRC_EEPROM_ADDR,
11724              (EEPROM_ADDR_FSM_RESET |
11725               (EEPROM_DEFAULT_CLOCK_PERIOD <<
11726                EEPROM_ADDR_CLKPERD_SHIFT)));
11727
11728         msleep(1);
11729
11730         /* Enable seeprom accesses. */
11731         tw32_f(GRC_LOCAL_CTRL,
11732              tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
11733         udelay(100);
11734
11735         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11736             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
11737                 tp->tg3_flags |= TG3_FLAG_NVRAM;
11738
11739                 if (tg3_nvram_lock(tp)) {
11740                         printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
11741                                "tg3_nvram_init failed.\n", tp->dev->name);
11742                         return;
11743                 }
11744                 tg3_enable_nvram_access(tp);
11745
11746                 tp->nvram_size = 0;
11747
11748                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
11749                         tg3_get_5752_nvram_info(tp);
11750                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
11751                         tg3_get_5755_nvram_info(tp);
11752                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
11753                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11754                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11755                         tg3_get_5787_nvram_info(tp);
11756                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
11757                         tg3_get_5761_nvram_info(tp);
11758                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11759                         tg3_get_5906_nvram_info(tp);
11760                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
11761                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
11762                         tg3_get_57780_nvram_info(tp);
11763                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
11764                         tg3_get_5717_nvram_info(tp);
11765                 else
11766                         tg3_get_nvram_info(tp);
11767
11768                 if (tp->nvram_size == 0)
11769                         tg3_get_nvram_size(tp);
11770
11771                 tg3_disable_nvram_access(tp);
11772                 tg3_nvram_unlock(tp);
11773
11774         } else {
11775                 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
11776
11777                 tg3_get_eeprom_size(tp);
11778         }
11779 }
11780
11781 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
11782                                     u32 offset, u32 len, u8 *buf)
11783 {
11784         int i, j, rc = 0;
11785         u32 val;
11786
11787         for (i = 0; i < len; i += 4) {
11788                 u32 addr;
11789                 __be32 data;
11790
11791                 addr = offset + i;
11792
11793                 memcpy(&data, buf + i, 4);
11794
11795                 /*
11796                  * The SEEPROM interface expects the data to always be opposite
11797                  * the native endian format.  We accomplish this by reversing
11798                  * all the operations that would have been performed on the
11799                  * data from a call to tg3_nvram_read_be32().
11800                  */
11801                 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
11802
11803                 val = tr32(GRC_EEPROM_ADDR);
11804                 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
11805
11806                 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
11807                         EEPROM_ADDR_READ);
11808                 tw32(GRC_EEPROM_ADDR, val |
11809                         (0 << EEPROM_ADDR_DEVID_SHIFT) |
11810                         (addr & EEPROM_ADDR_ADDR_MASK) |
11811                         EEPROM_ADDR_START |
11812                         EEPROM_ADDR_WRITE);
11813
11814                 for (j = 0; j < 1000; j++) {
11815                         val = tr32(GRC_EEPROM_ADDR);
11816
11817                         if (val & EEPROM_ADDR_COMPLETE)
11818                                 break;
11819                         msleep(1);
11820                 }
11821                 if (!(val & EEPROM_ADDR_COMPLETE)) {
11822                         rc = -EBUSY;
11823                         break;
11824                 }
11825         }
11826
11827         return rc;
11828 }
11829
11830 /* offset and length are dword aligned */
11831 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
11832                 u8 *buf)
11833 {
11834         int ret = 0;
11835         u32 pagesize = tp->nvram_pagesize;
11836         u32 pagemask = pagesize - 1;
11837         u32 nvram_cmd;
11838         u8 *tmp;
11839
11840         tmp = kmalloc(pagesize, GFP_KERNEL);
11841         if (tmp == NULL)
11842                 return -ENOMEM;
11843
11844         while (len) {
11845                 int j;
11846                 u32 phy_addr, page_off, size;
11847
11848                 phy_addr = offset & ~pagemask;
11849
11850                 for (j = 0; j < pagesize; j += 4) {
11851                         ret = tg3_nvram_read_be32(tp, phy_addr + j,
11852                                                   (__be32 *) (tmp + j));
11853                         if (ret)
11854                                 break;
11855                 }
11856                 if (ret)
11857                         break;
11858
11859                 page_off = offset & pagemask;
11860                 size = pagesize;
11861                 if (len < size)
11862                         size = len;
11863
11864                 len -= size;
11865
11866                 memcpy(tmp + page_off, buf, size);
11867
11868                 offset = offset + (pagesize - page_off);
11869
11870                 tg3_enable_nvram_access(tp);
11871
11872                 /*
11873                  * Before we can erase the flash page, we need
11874                  * to issue a special "write enable" command.
11875                  */
11876                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11877
11878                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11879                         break;
11880
11881                 /* Erase the target page */
11882                 tw32(NVRAM_ADDR, phy_addr);
11883
11884                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
11885                         NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
11886
11887                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11888                         break;
11889
11890                 /* Issue another write enable to start the write. */
11891                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11892
11893                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11894                         break;
11895
11896                 for (j = 0; j < pagesize; j += 4) {
11897                         __be32 data;
11898
11899                         data = *((__be32 *) (tmp + j));
11900
11901                         tw32(NVRAM_WRDATA, be32_to_cpu(data));
11902
11903                         tw32(NVRAM_ADDR, phy_addr + j);
11904
11905                         nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
11906                                 NVRAM_CMD_WR;
11907
11908                         if (j == 0)
11909                                 nvram_cmd |= NVRAM_CMD_FIRST;
11910                         else if (j == (pagesize - 4))
11911                                 nvram_cmd |= NVRAM_CMD_LAST;
11912
11913                         if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11914                                 break;
11915                 }
11916                 if (ret)
11917                         break;
11918         }
11919
11920         nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11921         tg3_nvram_exec_cmd(tp, nvram_cmd);
11922
11923         kfree(tmp);
11924
11925         return ret;
11926 }
11927
11928 /* offset and length are dword aligned */
11929 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
11930                 u8 *buf)
11931 {
11932         int i, ret = 0;
11933
11934         for (i = 0; i < len; i += 4, offset += 4) {
11935                 u32 page_off, phy_addr, nvram_cmd;
11936                 __be32 data;
11937
11938                 memcpy(&data, buf + i, 4);
11939                 tw32(NVRAM_WRDATA, be32_to_cpu(data));
11940
11941                 page_off = offset % tp->nvram_pagesize;
11942
11943                 phy_addr = tg3_nvram_phys_addr(tp, offset);
11944
11945                 tw32(NVRAM_ADDR, phy_addr);
11946
11947                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
11948
11949                 if ((page_off == 0) || (i == 0))
11950                         nvram_cmd |= NVRAM_CMD_FIRST;
11951                 if (page_off == (tp->nvram_pagesize - 4))
11952                         nvram_cmd |= NVRAM_CMD_LAST;
11953
11954                 if (i == (len - 4))
11955                         nvram_cmd |= NVRAM_CMD_LAST;
11956
11957                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
11958                     !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
11959                     (tp->nvram_jedecnum == JEDEC_ST) &&
11960                     (nvram_cmd & NVRAM_CMD_FIRST)) {
11961
11962                         if ((ret = tg3_nvram_exec_cmd(tp,
11963                                 NVRAM_CMD_WREN | NVRAM_CMD_GO |
11964                                 NVRAM_CMD_DONE)))
11965
11966                                 break;
11967                 }
11968                 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11969                         /* We always do complete word writes to eeprom. */
11970                         nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
11971                 }
11972
11973                 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11974                         break;
11975         }
11976         return ret;
11977 }
11978
11979 /* offset and length are dword aligned */
11980 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
11981 {
11982         int ret;
11983
11984         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
11985                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
11986                        ~GRC_LCLCTRL_GPIO_OUTPUT1);
11987                 udelay(40);
11988         }
11989
11990         if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
11991                 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
11992         }
11993         else {
11994                 u32 grc_mode;
11995
11996                 ret = tg3_nvram_lock(tp);
11997                 if (ret)
11998                         return ret;
11999
12000                 tg3_enable_nvram_access(tp);
12001                 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
12002                     !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM))
12003                         tw32(NVRAM_WRITE1, 0x406);
12004
12005                 grc_mode = tr32(GRC_MODE);
12006                 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
12007
12008                 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
12009                         !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
12010
12011                         ret = tg3_nvram_write_block_buffered(tp, offset, len,
12012                                 buf);
12013                 }
12014                 else {
12015                         ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
12016                                 buf);
12017                 }
12018
12019                 grc_mode = tr32(GRC_MODE);
12020                 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
12021
12022                 tg3_disable_nvram_access(tp);
12023                 tg3_nvram_unlock(tp);
12024         }
12025
12026         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
12027                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
12028                 udelay(40);
12029         }
12030
12031         return ret;
12032 }
12033
12034 struct subsys_tbl_ent {
12035         u16 subsys_vendor, subsys_devid;
12036         u32 phy_id;
12037 };
12038
12039 static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
12040         /* Broadcom boards. */
12041         { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
12042         { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
12043         { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
12044         { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 },              /* BCM95700A9 */
12045         { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
12046         { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
12047         { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 },              /* BCM95701A7 */
12048         { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
12049         { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
12050         { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
12051         { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
12052
12053         /* 3com boards. */
12054         { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
12055         { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
12056         { PCI_VENDOR_ID_3COM, 0x1004, 0 },              /* 3C996SX */
12057         { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
12058         { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
12059
12060         /* DELL boards. */
12061         { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
12062         { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
12063         { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
12064         { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
12065
12066         /* Compaq boards. */
12067         { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
12068         { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
12069         { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 },              /* CHANGELING */
12070         { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
12071         { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
12072
12073         /* IBM boards. */
12074         { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
12075 };
12076
12077 static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
12078 {
12079         int i;
12080
12081         for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
12082                 if ((subsys_id_to_phy_id[i].subsys_vendor ==
12083                      tp->pdev->subsystem_vendor) &&
12084                     (subsys_id_to_phy_id[i].subsys_devid ==
12085                      tp->pdev->subsystem_device))
12086                         return &subsys_id_to_phy_id[i];
12087         }
12088         return NULL;
12089 }
12090
12091 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
12092 {
12093         u32 val;
12094         u16 pmcsr;
12095
12096         /* On some early chips the SRAM cannot be accessed in D3hot state,
12097          * so need make sure we're in D0.
12098          */
12099         pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
12100         pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
12101         pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
12102         msleep(1);
12103
12104         /* Make sure register accesses (indirect or otherwise)
12105          * will function correctly.
12106          */
12107         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12108                                tp->misc_host_ctrl);
12109
12110         /* The memory arbiter has to be enabled in order for SRAM accesses
12111          * to succeed.  Normally on powerup the tg3 chip firmware will make
12112          * sure it is enabled, but other entities such as system netboot
12113          * code might disable it.
12114          */
12115         val = tr32(MEMARB_MODE);
12116         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
12117
12118         tp->phy_id = PHY_ID_INVALID;
12119         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12120
12121         /* Assume an onboard device and WOL capable by default.  */
12122         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
12123
12124         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12125                 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
12126                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12127                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12128                 }
12129                 val = tr32(VCPU_CFGSHDW);
12130                 if (val & VCPU_CFGSHDW_ASPM_DBNC)
12131                         tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
12132                 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
12133                     (val & VCPU_CFGSHDW_WOL_MAGPKT))
12134                         tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12135                 goto done;
12136         }
12137
12138         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
12139         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
12140                 u32 nic_cfg, led_cfg;
12141                 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
12142                 int eeprom_phy_serdes = 0;
12143
12144                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
12145                 tp->nic_sram_data_cfg = nic_cfg;
12146
12147                 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
12148                 ver >>= NIC_SRAM_DATA_VER_SHIFT;
12149                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
12150                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
12151                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
12152                     (ver > 0) && (ver < 0x100))
12153                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
12154
12155                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
12156                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
12157
12158                 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
12159                     NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
12160                         eeprom_phy_serdes = 1;
12161
12162                 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
12163                 if (nic_phy_id != 0) {
12164                         u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
12165                         u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
12166
12167                         eeprom_phy_id  = (id1 >> 16) << 10;
12168                         eeprom_phy_id |= (id2 & 0xfc00) << 16;
12169                         eeprom_phy_id |= (id2 & 0x03ff) <<  0;
12170                 } else
12171                         eeprom_phy_id = 0;
12172
12173                 tp->phy_id = eeprom_phy_id;
12174                 if (eeprom_phy_serdes) {
12175                         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
12176                                 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
12177                         else
12178                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
12179                 }
12180
12181                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
12182                         led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
12183                                     SHASTA_EXT_LED_MODE_MASK);
12184                 else
12185                         led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
12186
12187                 switch (led_cfg) {
12188                 default:
12189                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
12190                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12191                         break;
12192
12193                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
12194                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12195                         break;
12196
12197                 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
12198                         tp->led_ctrl = LED_CTRL_MODE_MAC;
12199
12200                         /* Default to PHY_1_MODE if 0 (MAC_MODE) is
12201                          * read on some older 5700/5701 bootcode.
12202                          */
12203                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
12204                             ASIC_REV_5700 ||
12205                             GET_ASIC_REV(tp->pci_chip_rev_id) ==
12206                             ASIC_REV_5701)
12207                                 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12208
12209                         break;
12210
12211                 case SHASTA_EXT_LED_SHARED:
12212                         tp->led_ctrl = LED_CTRL_MODE_SHARED;
12213                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
12214                             tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
12215                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12216                                                  LED_CTRL_MODE_PHY_2);
12217                         break;
12218
12219                 case SHASTA_EXT_LED_MAC:
12220                         tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
12221                         break;
12222
12223                 case SHASTA_EXT_LED_COMBO:
12224                         tp->led_ctrl = LED_CTRL_MODE_COMBO;
12225                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
12226                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12227                                                  LED_CTRL_MODE_PHY_2);
12228                         break;
12229
12230                 }
12231
12232                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12233                      GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
12234                     tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
12235                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12236
12237                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
12238                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12239
12240                 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
12241                         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
12242                         if ((tp->pdev->subsystem_vendor ==
12243                              PCI_VENDOR_ID_ARIMA) &&
12244                             (tp->pdev->subsystem_device == 0x205a ||
12245                              tp->pdev->subsystem_device == 0x2063))
12246                                 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12247                 } else {
12248                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12249                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12250                 }
12251
12252                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
12253                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
12254                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
12255                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
12256                 }
12257
12258                 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
12259                         (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
12260                         tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
12261
12262                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
12263                     !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
12264                         tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
12265
12266                 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
12267                     (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
12268                         tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12269
12270                 if (cfg2 & (1 << 17))
12271                         tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
12272
12273                 /* serdes signal pre-emphasis in register 0x590 set by */
12274                 /* bootcode if bit 18 is set */
12275                 if (cfg2 & (1 << 18))
12276                         tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
12277
12278                 if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
12279                       GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
12280                     (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
12281                         tp->tg3_flags3 |= TG3_FLG3_PHY_ENABLE_APD;
12282
12283                 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12284                         u32 cfg3;
12285
12286                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
12287                         if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
12288                                 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
12289                 }
12290
12291                 if (cfg4 & NIC_SRAM_RGMII_STD_IBND_DISABLE)
12292                         tp->tg3_flags3 |= TG3_FLG3_RGMII_STD_IBND_DISABLE;
12293                 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
12294                         tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
12295                 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
12296                         tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
12297         }
12298 done:
12299         device_init_wakeup(&tp->pdev->dev, tp->tg3_flags & TG3_FLAG_WOL_CAP);
12300         device_set_wakeup_enable(&tp->pdev->dev,
12301                                  tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
12302 }
12303
12304 static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
12305 {
12306         int i;
12307         u32 val;
12308
12309         tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
12310         tw32(OTP_CTRL, cmd);
12311
12312         /* Wait for up to 1 ms for command to execute. */
12313         for (i = 0; i < 100; i++) {
12314                 val = tr32(OTP_STATUS);
12315                 if (val & OTP_STATUS_CMD_DONE)
12316                         break;
12317                 udelay(10);
12318         }
12319
12320         return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
12321 }
12322
12323 /* Read the gphy configuration from the OTP region of the chip.  The gphy
12324  * configuration is a 32-bit value that straddles the alignment boundary.
12325  * We do two 32-bit reads and then shift and merge the results.
12326  */
12327 static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
12328 {
12329         u32 bhalf_otp, thalf_otp;
12330
12331         tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
12332
12333         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
12334                 return 0;
12335
12336         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
12337
12338         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12339                 return 0;
12340
12341         thalf_otp = tr32(OTP_READ_DATA);
12342
12343         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
12344
12345         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12346                 return 0;
12347
12348         bhalf_otp = tr32(OTP_READ_DATA);
12349
12350         return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
12351 }
12352
12353 static int __devinit tg3_phy_probe(struct tg3 *tp)
12354 {
12355         u32 hw_phy_id_1, hw_phy_id_2;
12356         u32 hw_phy_id, hw_phy_id_masked;
12357         int err;
12358
12359         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
12360                 return tg3_phy_init(tp);
12361
12362         /* Reading the PHY ID register can conflict with ASF
12363          * firmware access to the PHY hardware.
12364          */
12365         err = 0;
12366         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12367             (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
12368                 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
12369         } else {
12370                 /* Now read the physical PHY_ID from the chip and verify
12371                  * that it is sane.  If it doesn't look good, we fall back
12372                  * to either the hard-coded table based PHY_ID and failing
12373                  * that the value found in the eeprom area.
12374                  */
12375                 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
12376                 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
12377
12378                 hw_phy_id  = (hw_phy_id_1 & 0xffff) << 10;
12379                 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
12380                 hw_phy_id |= (hw_phy_id_2 & 0x03ff) <<  0;
12381
12382                 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
12383         }
12384
12385         if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
12386                 tp->phy_id = hw_phy_id;
12387                 if (hw_phy_id_masked == PHY_ID_BCM8002)
12388                         tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
12389                 else
12390                         tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
12391         } else {
12392                 if (tp->phy_id != PHY_ID_INVALID) {
12393                         /* Do nothing, phy ID already set up in
12394                          * tg3_get_eeprom_hw_cfg().
12395                          */
12396                 } else {
12397                         struct subsys_tbl_ent *p;
12398
12399                         /* No eeprom signature?  Try the hardcoded
12400                          * subsys device table.
12401                          */
12402                         p = lookup_by_subsys(tp);
12403                         if (!p)
12404                                 return -ENODEV;
12405
12406                         tp->phy_id = p->phy_id;
12407                         if (!tp->phy_id ||
12408                             tp->phy_id == PHY_ID_BCM8002)
12409                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
12410                 }
12411         }
12412
12413         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
12414             !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
12415             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
12416                 u32 bmsr, adv_reg, tg3_ctrl, mask;
12417
12418                 tg3_readphy(tp, MII_BMSR, &bmsr);
12419                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
12420                     (bmsr & BMSR_LSTATUS))
12421                         goto skip_phy_reset;
12422
12423                 err = tg3_phy_reset(tp);
12424                 if (err)
12425                         return err;
12426
12427                 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
12428                            ADVERTISE_100HALF | ADVERTISE_100FULL |
12429                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
12430                 tg3_ctrl = 0;
12431                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
12432                         tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
12433                                     MII_TG3_CTRL_ADV_1000_FULL);
12434                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12435                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
12436                                 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
12437                                              MII_TG3_CTRL_ENABLE_AS_MASTER);
12438                 }
12439
12440                 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
12441                         ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
12442                         ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
12443                 if (!tg3_copper_is_advertising_all(tp, mask)) {
12444                         tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12445
12446                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
12447                                 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12448
12449                         tg3_writephy(tp, MII_BMCR,
12450                                      BMCR_ANENABLE | BMCR_ANRESTART);
12451                 }
12452                 tg3_phy_set_wirespeed(tp);
12453
12454                 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12455                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
12456                         tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12457         }
12458
12459 skip_phy_reset:
12460         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
12461                 err = tg3_init_5401phy_dsp(tp);
12462                 if (err)
12463                         return err;
12464         }
12465
12466         if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
12467                 err = tg3_init_5401phy_dsp(tp);
12468         }
12469
12470         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
12471                 tp->link_config.advertising =
12472                         (ADVERTISED_1000baseT_Half |
12473                          ADVERTISED_1000baseT_Full |
12474                          ADVERTISED_Autoneg |
12475                          ADVERTISED_FIBRE);
12476         if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
12477                 tp->link_config.advertising &=
12478                         ~(ADVERTISED_1000baseT_Half |
12479                           ADVERTISED_1000baseT_Full);
12480
12481         return err;
12482 }
12483
12484 static void __devinit tg3_read_partno(struct tg3 *tp)
12485 {
12486         unsigned char vpd_data[TG3_NVM_VPD_LEN];   /* in little-endian format */
12487         unsigned int i;
12488         u32 magic;
12489
12490         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
12491             tg3_nvram_read(tp, 0x0, &magic))
12492                 goto out_not_found;
12493
12494         if (magic == TG3_EEPROM_MAGIC) {
12495                 for (i = 0; i < TG3_NVM_VPD_LEN; i += 4) {
12496                         u32 tmp;
12497
12498                         /* The data is in little-endian format in NVRAM.
12499                          * Use the big-endian read routines to preserve
12500                          * the byte order as it exists in NVRAM.
12501                          */
12502                         if (tg3_nvram_read_be32(tp, TG3_NVM_VPD_OFF + i, &tmp))
12503                                 goto out_not_found;
12504
12505                         memcpy(&vpd_data[i], &tmp, sizeof(tmp));
12506                 }
12507         } else {
12508                 ssize_t cnt;
12509                 unsigned int pos = 0, i = 0;
12510
12511                 for (; pos < TG3_NVM_VPD_LEN && i < 3; i++, pos += cnt) {
12512                         cnt = pci_read_vpd(tp->pdev, pos,
12513                                            TG3_NVM_VPD_LEN - pos,
12514                                            &vpd_data[pos]);
12515                         if (cnt == -ETIMEDOUT || -EINTR)
12516                                 cnt = 0;
12517                         else if (cnt < 0)
12518                                 goto out_not_found;
12519                 }
12520                 if (pos != TG3_NVM_VPD_LEN)
12521                         goto out_not_found;
12522         }
12523
12524         /* Now parse and find the part number. */
12525         for (i = 0; i < TG3_NVM_VPD_LEN - 2; ) {
12526                 unsigned char val = vpd_data[i];
12527                 unsigned int block_end;
12528
12529                 if (val == 0x82 || val == 0x91) {
12530                         i = (i + 3 +
12531                              (vpd_data[i + 1] +
12532                               (vpd_data[i + 2] << 8)));
12533                         continue;
12534                 }
12535
12536                 if (val != 0x90)
12537                         goto out_not_found;
12538
12539                 block_end = (i + 3 +
12540                              (vpd_data[i + 1] +
12541                               (vpd_data[i + 2] << 8)));
12542                 i += 3;
12543
12544                 if (block_end > TG3_NVM_VPD_LEN)
12545                         goto out_not_found;
12546
12547                 while (i < (block_end - 2)) {
12548                         if (vpd_data[i + 0] == 'P' &&
12549                             vpd_data[i + 1] == 'N') {
12550                                 int partno_len = vpd_data[i + 2];
12551
12552                                 i += 3;
12553                                 if (partno_len > TG3_BPN_SIZE ||
12554                                     (partno_len + i) > TG3_NVM_VPD_LEN)
12555                                         goto out_not_found;
12556
12557                                 memcpy(tp->board_part_number,
12558                                        &vpd_data[i], partno_len);
12559
12560                                 /* Success. */
12561                                 return;
12562                         }
12563                         i += 3 + vpd_data[i + 2];
12564                 }
12565
12566                 /* Part number not found. */
12567                 goto out_not_found;
12568         }
12569
12570 out_not_found:
12571         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12572                 strcpy(tp->board_part_number, "BCM95906");
12573         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12574                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
12575                 strcpy(tp->board_part_number, "BCM57780");
12576         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12577                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
12578                 strcpy(tp->board_part_number, "BCM57760");
12579         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12580                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
12581                 strcpy(tp->board_part_number, "BCM57790");
12582         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12583                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
12584                 strcpy(tp->board_part_number, "BCM57788");
12585         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
12586                 strcpy(tp->board_part_number, "BCM57765");
12587         else
12588                 strcpy(tp->board_part_number, "none");
12589 }
12590
12591 static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
12592 {
12593         u32 val;
12594
12595         if (tg3_nvram_read(tp, offset, &val) ||
12596             (val & 0xfc000000) != 0x0c000000 ||
12597             tg3_nvram_read(tp, offset + 4, &val) ||
12598             val != 0)
12599                 return 0;
12600
12601         return 1;
12602 }
12603
12604 static void __devinit tg3_read_bc_ver(struct tg3 *tp)
12605 {
12606         u32 val, offset, start, ver_offset;
12607         int i;
12608         bool newver = false;
12609
12610         if (tg3_nvram_read(tp, 0xc, &offset) ||
12611             tg3_nvram_read(tp, 0x4, &start))
12612                 return;
12613
12614         offset = tg3_nvram_logical_addr(tp, offset);
12615
12616         if (tg3_nvram_read(tp, offset, &val))
12617                 return;
12618
12619         if ((val & 0xfc000000) == 0x0c000000) {
12620                 if (tg3_nvram_read(tp, offset + 4, &val))
12621                         return;
12622
12623                 if (val == 0)
12624                         newver = true;
12625         }
12626
12627         if (newver) {
12628                 if (tg3_nvram_read(tp, offset + 8, &ver_offset))
12629                         return;
12630
12631                 offset = offset + ver_offset - start;
12632                 for (i = 0; i < 16; i += 4) {
12633                         __be32 v;
12634                         if (tg3_nvram_read_be32(tp, offset + i, &v))
12635                                 return;
12636
12637                         memcpy(tp->fw_ver + i, &v, sizeof(v));
12638                 }
12639         } else {
12640                 u32 major, minor;
12641
12642                 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
12643                         return;
12644
12645                 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
12646                         TG3_NVM_BCVER_MAJSFT;
12647                 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
12648                 snprintf(&tp->fw_ver[0], 32, "v%d.%02d", major, minor);
12649         }
12650 }
12651
12652 static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
12653 {
12654         u32 val, major, minor;
12655
12656         /* Use native endian representation */
12657         if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
12658                 return;
12659
12660         major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
12661                 TG3_NVM_HWSB_CFG1_MAJSFT;
12662         minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
12663                 TG3_NVM_HWSB_CFG1_MINSFT;
12664
12665         snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
12666 }
12667
12668 static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
12669 {
12670         u32 offset, major, minor, build;
12671
12672         tp->fw_ver[0] = 's';
12673         tp->fw_ver[1] = 'b';
12674         tp->fw_ver[2] = '\0';
12675
12676         if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
12677                 return;
12678
12679         switch (val & TG3_EEPROM_SB_REVISION_MASK) {
12680         case TG3_EEPROM_SB_REVISION_0:
12681                 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
12682                 break;
12683         case TG3_EEPROM_SB_REVISION_2:
12684                 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
12685                 break;
12686         case TG3_EEPROM_SB_REVISION_3:
12687                 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
12688                 break;
12689         default:
12690                 return;
12691         }
12692
12693         if (tg3_nvram_read(tp, offset, &val))
12694                 return;
12695
12696         build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
12697                 TG3_EEPROM_SB_EDH_BLD_SHFT;
12698         major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
12699                 TG3_EEPROM_SB_EDH_MAJ_SHFT;
12700         minor =  val & TG3_EEPROM_SB_EDH_MIN_MASK;
12701
12702         if (minor > 99 || build > 26)
12703                 return;
12704
12705         snprintf(&tp->fw_ver[2], 30, " v%d.%02d", major, minor);
12706
12707         if (build > 0) {
12708                 tp->fw_ver[8] = 'a' + build - 1;
12709                 tp->fw_ver[9] = '\0';
12710         }
12711 }
12712
12713 static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
12714 {
12715         u32 val, offset, start;
12716         int i, vlen;
12717
12718         for (offset = TG3_NVM_DIR_START;
12719              offset < TG3_NVM_DIR_END;
12720              offset += TG3_NVM_DIRENT_SIZE) {
12721                 if (tg3_nvram_read(tp, offset, &val))
12722                         return;
12723
12724                 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
12725                         break;
12726         }
12727
12728         if (offset == TG3_NVM_DIR_END)
12729                 return;
12730
12731         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
12732                 start = 0x08000000;
12733         else if (tg3_nvram_read(tp, offset - 4, &start))
12734                 return;
12735
12736         if (tg3_nvram_read(tp, offset + 4, &offset) ||
12737             !tg3_fw_img_is_valid(tp, offset) ||
12738             tg3_nvram_read(tp, offset + 8, &val))
12739                 return;
12740
12741         offset += val - start;
12742
12743         vlen = strlen(tp->fw_ver);
12744
12745         tp->fw_ver[vlen++] = ',';
12746         tp->fw_ver[vlen++] = ' ';
12747
12748         for (i = 0; i < 4; i++) {
12749                 __be32 v;
12750                 if (tg3_nvram_read_be32(tp, offset, &v))
12751                         return;
12752
12753                 offset += sizeof(v);
12754
12755                 if (vlen > TG3_VER_SIZE - sizeof(v)) {
12756                         memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
12757                         break;
12758                 }
12759
12760                 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
12761                 vlen += sizeof(v);
12762         }
12763 }
12764
12765 static void __devinit tg3_read_dash_ver(struct tg3 *tp)
12766 {
12767         int vlen;
12768         u32 apedata;
12769
12770         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) ||
12771             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
12772                 return;
12773
12774         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
12775         if (apedata != APE_SEG_SIG_MAGIC)
12776                 return;
12777
12778         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
12779         if (!(apedata & APE_FW_STATUS_READY))
12780                 return;
12781
12782         apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
12783
12784         vlen = strlen(tp->fw_ver);
12785
12786         snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " DASH v%d.%d.%d.%d",
12787                  (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
12788                  (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
12789                  (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
12790                  (apedata & APE_FW_VERSION_BLDMSK));
12791 }
12792
12793 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
12794 {
12795         u32 val;
12796
12797         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) {
12798                 tp->fw_ver[0] = 's';
12799                 tp->fw_ver[1] = 'b';
12800                 tp->fw_ver[2] = '\0';
12801
12802                 return;
12803         }
12804
12805         if (tg3_nvram_read(tp, 0, &val))
12806                 return;
12807
12808         if (val == TG3_EEPROM_MAGIC)
12809                 tg3_read_bc_ver(tp);
12810         else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
12811                 tg3_read_sb_ver(tp, val);
12812         else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
12813                 tg3_read_hwsb_ver(tp);
12814         else
12815                 return;
12816
12817         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12818              (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
12819                 return;
12820
12821         tg3_read_mgmtfw_ver(tp);
12822
12823         tp->fw_ver[TG3_VER_SIZE - 1] = 0;
12824 }
12825
12826 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
12827
12828 static int __devinit tg3_get_invariants(struct tg3 *tp)
12829 {
12830         static struct pci_device_id write_reorder_chipsets[] = {
12831                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12832                              PCI_DEVICE_ID_AMD_FE_GATE_700C) },
12833                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12834                              PCI_DEVICE_ID_AMD_8131_BRIDGE) },
12835                 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
12836                              PCI_DEVICE_ID_VIA_8385_0) },
12837                 { },
12838         };
12839         u32 misc_ctrl_reg;
12840         u32 pci_state_reg, grc_misc_cfg;
12841         u32 val;
12842         u16 pci_cmd;
12843         int err;
12844
12845         /* Force memory write invalidate off.  If we leave it on,
12846          * then on 5700_BX chips we have to enable a workaround.
12847          * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
12848          * to match the cacheline size.  The Broadcom driver have this
12849          * workaround but turns MWI off all the times so never uses
12850          * it.  This seems to suggest that the workaround is insufficient.
12851          */
12852         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12853         pci_cmd &= ~PCI_COMMAND_INVALIDATE;
12854         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12855
12856         /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
12857          * has the register indirect write enable bit set before
12858          * we try to access any of the MMIO registers.  It is also
12859          * critical that the PCI-X hw workaround situation is decided
12860          * before that as well.
12861          */
12862         pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12863                               &misc_ctrl_reg);
12864
12865         tp->pci_chip_rev_id = (misc_ctrl_reg >>
12866                                MISC_HOST_CTRL_CHIPREV_SHIFT);
12867         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
12868                 u32 prod_id_asic_rev;
12869
12870                 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
12871                     tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
12872                     tp->pdev->device == TG3PCI_DEVICE_TIGON3_5724)
12873                         pci_read_config_dword(tp->pdev,
12874                                               TG3PCI_GEN2_PRODID_ASICREV,
12875                                               &prod_id_asic_rev);
12876                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 ||
12877                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 ||
12878                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 ||
12879                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 ||
12880                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
12881                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
12882                         pci_read_config_dword(tp->pdev,
12883                                               TG3PCI_GEN15_PRODID_ASICREV,
12884                                               &prod_id_asic_rev);
12885                 else
12886                         pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
12887                                               &prod_id_asic_rev);
12888
12889                 tp->pci_chip_rev_id = prod_id_asic_rev;
12890         }
12891
12892         /* Wrong chip ID in 5752 A0. This code can be removed later
12893          * as A0 is not in production.
12894          */
12895         if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
12896                 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
12897
12898         /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
12899          * we need to disable memory and use config. cycles
12900          * only to access all registers. The 5702/03 chips
12901          * can mistakenly decode the special cycles from the
12902          * ICH chipsets as memory write cycles, causing corruption
12903          * of register and memory space. Only certain ICH bridges
12904          * will drive special cycles with non-zero data during the
12905          * address phase which can fall within the 5703's address
12906          * range. This is not an ICH bug as the PCI spec allows
12907          * non-zero address during special cycles. However, only
12908          * these ICH bridges are known to drive non-zero addresses
12909          * during special cycles.
12910          *
12911          * Since special cycles do not cross PCI bridges, we only
12912          * enable this workaround if the 5703 is on the secondary
12913          * bus of these ICH bridges.
12914          */
12915         if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
12916             (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
12917                 static struct tg3_dev_id {
12918                         u32     vendor;
12919                         u32     device;
12920                         u32     rev;
12921                 } ich_chipsets[] = {
12922                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
12923                           PCI_ANY_ID },
12924                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
12925                           PCI_ANY_ID },
12926                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
12927                           0xa },
12928                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
12929                           PCI_ANY_ID },
12930                         { },
12931                 };
12932                 struct tg3_dev_id *pci_id = &ich_chipsets[0];
12933                 struct pci_dev *bridge = NULL;
12934
12935                 while (pci_id->vendor != 0) {
12936                         bridge = pci_get_device(pci_id->vendor, pci_id->device,
12937                                                 bridge);
12938                         if (!bridge) {
12939                                 pci_id++;
12940                                 continue;
12941                         }
12942                         if (pci_id->rev != PCI_ANY_ID) {
12943                                 if (bridge->revision > pci_id->rev)
12944                                         continue;
12945                         }
12946                         if (bridge->subordinate &&
12947                             (bridge->subordinate->number ==
12948                              tp->pdev->bus->number)) {
12949
12950                                 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
12951                                 pci_dev_put(bridge);
12952                                 break;
12953                         }
12954                 }
12955         }
12956
12957         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
12958                 static struct tg3_dev_id {
12959                         u32     vendor;
12960                         u32     device;
12961                 } bridge_chipsets[] = {
12962                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
12963                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
12964                         { },
12965                 };
12966                 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
12967                 struct pci_dev *bridge = NULL;
12968
12969                 while (pci_id->vendor != 0) {
12970                         bridge = pci_get_device(pci_id->vendor,
12971                                                 pci_id->device,
12972                                                 bridge);
12973                         if (!bridge) {
12974                                 pci_id++;
12975                                 continue;
12976                         }
12977                         if (bridge->subordinate &&
12978                             (bridge->subordinate->number <=
12979                              tp->pdev->bus->number) &&
12980                             (bridge->subordinate->subordinate >=
12981                              tp->pdev->bus->number)) {
12982                                 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
12983                                 pci_dev_put(bridge);
12984                                 break;
12985                         }
12986                 }
12987         }
12988
12989         /* The EPB bridge inside 5714, 5715, and 5780 cannot support
12990          * DMA addresses > 40-bit. This bridge may have other additional
12991          * 57xx devices behind it in some 4-port NIC designs for example.
12992          * Any tg3 device found behind the bridge will also need the 40-bit
12993          * DMA workaround.
12994          */
12995         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
12996             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
12997                 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
12998                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
12999                 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
13000         }
13001         else {
13002                 struct pci_dev *bridge = NULL;
13003
13004                 do {
13005                         bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
13006                                                 PCI_DEVICE_ID_SERVERWORKS_EPB,
13007                                                 bridge);
13008                         if (bridge && bridge->subordinate &&
13009                             (bridge->subordinate->number <=
13010                              tp->pdev->bus->number) &&
13011                             (bridge->subordinate->subordinate >=
13012                              tp->pdev->bus->number)) {
13013                                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
13014                                 pci_dev_put(bridge);
13015                                 break;
13016                         }
13017                 } while (bridge);
13018         }
13019
13020         /* Initialize misc host control in PCI block. */
13021         tp->misc_host_ctrl |= (misc_ctrl_reg &
13022                                MISC_HOST_CTRL_CHIPREV);
13023         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13024                                tp->misc_host_ctrl);
13025
13026         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
13027             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
13028             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
13029                 tp->pdev_peer = tg3_find_peer(tp);
13030
13031         /* Intentionally exclude ASIC_REV_5906 */
13032         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13033             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
13034             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13035             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13036             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13037             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13038             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13039             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13040                 tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
13041
13042         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13043             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13044             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
13045             (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13046             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
13047                 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
13048
13049         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
13050             (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
13051                 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
13052
13053         /* 5700 B0 chips do not support checksumming correctly due
13054          * to hardware bugs.
13055          */
13056         if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
13057                 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
13058         else {
13059                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
13060                 tp->dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
13061                 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
13062                         tp->dev->features |= NETIF_F_IPV6_CSUM;
13063         }
13064
13065         /* Determine TSO capabilities */
13066         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13067             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13068                 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_3;
13069         else if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13070                  GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13071                 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
13072         else if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
13073                 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
13074                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 &&
13075                     tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
13076                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
13077         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13078                    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13079                    tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
13080                 tp->tg3_flags2 |= TG3_FLG2_TSO_BUG;
13081                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
13082                         tp->fw_needed = FIRMWARE_TG3TSO5;
13083                 else
13084                         tp->fw_needed = FIRMWARE_TG3TSO;
13085         }
13086
13087         tp->irq_max = 1;
13088
13089         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
13090                 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
13091                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
13092                     GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
13093                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
13094                      tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
13095                      tp->pdev_peer == tp->pdev))
13096                         tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
13097
13098                 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13099                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13100                         tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
13101                 }
13102
13103                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13104                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
13105                         tp->tg3_flags |= TG3_FLAG_SUPPORT_MSIX;
13106                         tp->irq_max = TG3_IRQ_MAX_VECS;
13107                 }
13108         }
13109
13110         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13111             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13112                 tp->tg3_flags3 |= TG3_FLG3_SHORT_DMA_BUG;
13113         else if (!(tp->tg3_flags3 & TG3_FLG3_5755_PLUS)) {
13114                 tp->tg3_flags3 |= TG3_FLG3_4G_DMA_BNDRY_BUG;
13115                 tp->tg3_flags3 |= TG3_FLG3_40BIT_DMA_LIMIT_BUG;
13116         }
13117
13118         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13119             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13120                 tp->tg3_flags3 |= TG3_FLG3_USE_JUMBO_BDFLAG;
13121
13122         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
13123              (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
13124                  (tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG))
13125                 tp->tg3_flags |= TG3_FLAG_JUMBO_CAPABLE;
13126
13127         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13128                               &pci_state_reg);
13129
13130         tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
13131         if (tp->pcie_cap != 0) {
13132                 u16 lnkctl;
13133
13134                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
13135
13136                 pcie_set_readrq(tp->pdev, 4096);
13137
13138                 pci_read_config_word(tp->pdev,
13139                                      tp->pcie_cap + PCI_EXP_LNKCTL,
13140                                      &lnkctl);
13141                 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
13142                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13143                                 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
13144                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13145                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13146                             tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
13147                             tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
13148                                 tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
13149                 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5717_A0) {
13150                         tp->tg3_flags3 |= TG3_FLG3_L1PLLPD_EN;
13151                 }
13152         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
13153                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
13154         } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
13155                    (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13156                 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
13157                 if (!tp->pcix_cap) {
13158                         printk(KERN_ERR PFX "Cannot find PCI-X "
13159                                             "capability, aborting.\n");
13160                         return -EIO;
13161                 }
13162
13163                 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
13164                         tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
13165         }
13166
13167         /* If we have an AMD 762 or VIA K8T800 chipset, write
13168          * reordering to the mailbox registers done by the host
13169          * controller can cause major troubles.  We read back from
13170          * every mailbox register write to force the writes to be
13171          * posted to the chip in order.
13172          */
13173         if (pci_dev_present(write_reorder_chipsets) &&
13174             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13175                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
13176
13177         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
13178                              &tp->pci_cacheline_sz);
13179         pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13180                              &tp->pci_lat_timer);
13181         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13182             tp->pci_lat_timer < 64) {
13183                 tp->pci_lat_timer = 64;
13184                 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13185                                       tp->pci_lat_timer);
13186         }
13187
13188         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
13189                 /* 5700 BX chips need to have their TX producer index
13190                  * mailboxes written twice to workaround a bug.
13191                  */
13192                 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
13193
13194                 /* If we are in PCI-X mode, enable register write workaround.
13195                  *
13196                  * The workaround is to use indirect register accesses
13197                  * for all chip writes not to mailbox registers.
13198                  */
13199                 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
13200                         u32 pm_reg;
13201
13202                         tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13203
13204                         /* The chip can have it's power management PCI config
13205                          * space registers clobbered due to this bug.
13206                          * So explicitly force the chip into D0 here.
13207                          */
13208                         pci_read_config_dword(tp->pdev,
13209                                               tp->pm_cap + PCI_PM_CTRL,
13210                                               &pm_reg);
13211                         pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
13212                         pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
13213                         pci_write_config_dword(tp->pdev,
13214                                                tp->pm_cap + PCI_PM_CTRL,
13215                                                pm_reg);
13216
13217                         /* Also, force SERR#/PERR# in PCI command. */
13218                         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13219                         pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
13220                         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13221                 }
13222         }
13223
13224         if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
13225                 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
13226         if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
13227                 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
13228
13229         /* Chip-specific fixup from Broadcom driver */
13230         if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
13231             (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
13232                 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
13233                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
13234         }
13235
13236         /* Default fast path register access methods */
13237         tp->read32 = tg3_read32;
13238         tp->write32 = tg3_write32;
13239         tp->read32_mbox = tg3_read32;
13240         tp->write32_mbox = tg3_write32;
13241         tp->write32_tx_mbox = tg3_write32;
13242         tp->write32_rx_mbox = tg3_write32;
13243
13244         /* Various workaround register access methods */
13245         if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
13246                 tp->write32 = tg3_write_indirect_reg32;
13247         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
13248                  ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
13249                   tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
13250                 /*
13251                  * Back to back register writes can cause problems on these
13252                  * chips, the workaround is to read back all reg writes
13253                  * except those to mailbox regs.
13254                  *
13255                  * See tg3_write_indirect_reg32().
13256                  */
13257                 tp->write32 = tg3_write_flush_reg32;
13258         }
13259
13260         if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
13261             (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
13262                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
13263                 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
13264                         tp->write32_rx_mbox = tg3_write_flush_reg32;
13265         }
13266
13267         if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
13268                 tp->read32 = tg3_read_indirect_reg32;
13269                 tp->write32 = tg3_write_indirect_reg32;
13270                 tp->read32_mbox = tg3_read_indirect_mbox;
13271                 tp->write32_mbox = tg3_write_indirect_mbox;
13272                 tp->write32_tx_mbox = tg3_write_indirect_mbox;
13273                 tp->write32_rx_mbox = tg3_write_indirect_mbox;
13274
13275                 iounmap(tp->regs);
13276                 tp->regs = NULL;
13277
13278                 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13279                 pci_cmd &= ~PCI_COMMAND_MEMORY;
13280                 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13281         }
13282         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13283                 tp->read32_mbox = tg3_read32_mbox_5906;
13284                 tp->write32_mbox = tg3_write32_mbox_5906;
13285                 tp->write32_tx_mbox = tg3_write32_mbox_5906;
13286                 tp->write32_rx_mbox = tg3_write32_mbox_5906;
13287         }
13288
13289         if (tp->write32 == tg3_write_indirect_reg32 ||
13290             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13291              (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13292               GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
13293                 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
13294
13295         /* Get eeprom hw config before calling tg3_set_power_state().
13296          * In particular, the TG3_FLG2_IS_NIC flag must be
13297          * determined before calling tg3_set_power_state() so that
13298          * we know whether or not to switch out of Vaux power.
13299          * When the flag is set, it means that GPIO1 is used for eeprom
13300          * write protect and also implies that it is a LOM where GPIOs
13301          * are not used to switch power.
13302          */
13303         tg3_get_eeprom_hw_cfg(tp);
13304
13305         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
13306                 /* Allow reads and writes to the
13307                  * APE register and memory space.
13308                  */
13309                 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
13310                                  PCISTATE_ALLOW_APE_SHMEM_WR;
13311                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
13312                                        pci_state_reg);
13313         }
13314
13315         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13316             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13317             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13318             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13319             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13320             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13321                 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
13322
13323         /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
13324          * GPIO1 driven high will bring 5700's external PHY out of reset.
13325          * It is also used as eeprom write protect on LOMs.
13326          */
13327         tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
13328         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13329             (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
13330                 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
13331                                        GRC_LCLCTRL_GPIO_OUTPUT1);
13332         /* Unused GPIO3 must be driven as output on 5752 because there
13333          * are no pull-up resistors on unused GPIO pins.
13334          */
13335         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
13336                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
13337
13338         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13339             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13340             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13341                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13342
13343         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
13344             tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
13345                 /* Turn off the debug UART. */
13346                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13347                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
13348                         /* Keep VMain power. */
13349                         tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
13350                                               GRC_LCLCTRL_GPIO_OUTPUT0;
13351         }
13352
13353         /* Force the chip into D0. */
13354         err = tg3_set_power_state(tp, PCI_D0);
13355         if (err) {
13356                 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
13357                        pci_name(tp->pdev));
13358                 return err;
13359         }
13360
13361         /* Derive initial jumbo mode from MTU assigned in
13362          * ether_setup() via the alloc_etherdev() call
13363          */
13364         if (tp->dev->mtu > ETH_DATA_LEN &&
13365             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
13366                 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
13367
13368         /* Determine WakeOnLan speed to use. */
13369         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13370             tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
13371             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
13372             tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
13373                 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
13374         } else {
13375                 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
13376         }
13377
13378         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13379                 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
13380
13381         /* A few boards don't want Ethernet@WireSpeed phy feature */
13382         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13383             ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
13384              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
13385              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
13386             (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) ||
13387             (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
13388                 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
13389
13390         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
13391             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
13392                 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
13393         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
13394                 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
13395
13396         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
13397             !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
13398             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
13399             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 &&
13400             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
13401             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765) {
13402                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13403                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
13404                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13405                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
13406                         if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
13407                             tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
13408                                 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
13409                         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
13410                                 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
13411                 } else
13412                         tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
13413         }
13414
13415         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13416             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
13417                 tp->phy_otp = tg3_read_otp_phycfg(tp);
13418                 if (tp->phy_otp == 0)
13419                         tp->phy_otp = TG3_OTP_DEFAULT;
13420         }
13421
13422         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
13423                 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
13424         else
13425                 tp->mi_mode = MAC_MI_MODE_BASE;
13426
13427         tp->coalesce_mode = 0;
13428         if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
13429             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
13430                 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
13431
13432         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13433             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
13434                 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
13435
13436         err = tg3_mdio_init(tp);
13437         if (err)
13438                 return err;
13439
13440         /* Initialize data/descriptor byte/word swapping. */
13441         val = tr32(GRC_MODE);
13442         val &= GRC_MODE_HOST_STACKUP;
13443         tw32(GRC_MODE, val | tp->grc_mode);
13444
13445         tg3_switch_clocks(tp);
13446
13447         /* Clear this out for sanity. */
13448         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
13449
13450         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13451                               &pci_state_reg);
13452         if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
13453             (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
13454                 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
13455
13456                 if (chiprevid == CHIPREV_ID_5701_A0 ||
13457                     chiprevid == CHIPREV_ID_5701_B0 ||
13458                     chiprevid == CHIPREV_ID_5701_B2 ||
13459                     chiprevid == CHIPREV_ID_5701_B5) {
13460                         void __iomem *sram_base;
13461
13462                         /* Write some dummy words into the SRAM status block
13463                          * area, see if it reads back correctly.  If the return
13464                          * value is bad, force enable the PCIX workaround.
13465                          */
13466                         sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
13467
13468                         writel(0x00000000, sram_base);
13469                         writel(0x00000000, sram_base + 4);
13470                         writel(0xffffffff, sram_base + 4);
13471                         if (readl(sram_base) != 0x00000000)
13472                                 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13473                 }
13474         }
13475
13476         udelay(50);
13477         tg3_nvram_init(tp);
13478
13479         grc_misc_cfg = tr32(GRC_MISC_CFG);
13480         grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
13481
13482         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13483             (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
13484              grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
13485                 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
13486
13487         if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
13488             (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
13489                 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
13490         if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
13491                 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
13492                                       HOSTCC_MODE_CLRTICK_TXBD);
13493
13494                 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
13495                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13496                                        tp->misc_host_ctrl);
13497         }
13498
13499         /* Preserve the APE MAC_MODE bits */
13500         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
13501                 tp->mac_mode = tr32(MAC_MODE) |
13502                                MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
13503         else
13504                 tp->mac_mode = TG3_DEF_MAC_MODE;
13505
13506         /* these are limited to 10/100 only */
13507         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13508              (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
13509             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13510              tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13511              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
13512               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
13513               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
13514             (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13515              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
13516               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
13517               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
13518             tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
13519             (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
13520                 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
13521
13522         err = tg3_phy_probe(tp);
13523         if (err) {
13524                 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
13525                        pci_name(tp->pdev), err);
13526                 /* ... but do not return immediately ... */
13527                 tg3_mdio_fini(tp);
13528         }
13529
13530         tg3_read_partno(tp);
13531         tg3_read_fw_ver(tp);
13532
13533         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
13534                 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
13535         } else {
13536                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13537                         tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
13538                 else
13539                         tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
13540         }
13541
13542         /* 5700 {AX,BX} chips have a broken status block link
13543          * change bit implementation, so we must use the
13544          * status register in those cases.
13545          */
13546         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13547                 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
13548         else
13549                 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
13550
13551         /* The led_ctrl is set during tg3_phy_probe, here we might
13552          * have to force the link status polling mechanism based
13553          * upon subsystem IDs.
13554          */
13555         if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
13556             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13557             !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
13558                 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
13559                                   TG3_FLAG_USE_LINKCHG_REG);
13560         }
13561
13562         /* For all SERDES we poll the MAC status register. */
13563         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
13564                 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
13565         else
13566                 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
13567
13568         tp->rx_offset = NET_IP_ALIGN;
13569         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13570             (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
13571                 tp->rx_offset = 0;
13572
13573         tp->rx_std_max_post = TG3_RX_RING_SIZE;
13574
13575         /* Increment the rx prod index on the rx std ring by at most
13576          * 8 for these chips to workaround hw errata.
13577          */
13578         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13579             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13580             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
13581                 tp->rx_std_max_post = 8;
13582
13583         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
13584                 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
13585                                      PCIE_PWR_MGMT_L1_THRESH_MSK;
13586
13587         return err;
13588 }
13589
13590 #ifdef CONFIG_SPARC
13591 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
13592 {
13593         struct net_device *dev = tp->dev;
13594         struct pci_dev *pdev = tp->pdev;
13595         struct device_node *dp = pci_device_to_OF_node(pdev);
13596         const unsigned char *addr;
13597         int len;
13598
13599         addr = of_get_property(dp, "local-mac-address", &len);
13600         if (addr && len == 6) {
13601                 memcpy(dev->dev_addr, addr, 6);
13602                 memcpy(dev->perm_addr, dev->dev_addr, 6);
13603                 return 0;
13604         }
13605         return -ENODEV;
13606 }
13607
13608 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
13609 {
13610         struct net_device *dev = tp->dev;
13611
13612         memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
13613         memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
13614         return 0;
13615 }
13616 #endif
13617
13618 static int __devinit tg3_get_device_address(struct tg3 *tp)
13619 {
13620         struct net_device *dev = tp->dev;
13621         u32 hi, lo, mac_offset;
13622         int addr_ok = 0;
13623
13624 #ifdef CONFIG_SPARC
13625         if (!tg3_get_macaddr_sparc(tp))
13626                 return 0;
13627 #endif
13628
13629         mac_offset = 0x7c;
13630         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
13631             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13632                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
13633                         mac_offset = 0xcc;
13634                 if (tg3_nvram_lock(tp))
13635                         tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
13636                 else
13637                         tg3_nvram_unlock(tp);
13638         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
13639                 if (tr32(TG3_CPMU_STATUS) & TG3_CPMU_STATUS_PCIE_FUNC)
13640                         mac_offset = 0xcc;
13641         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13642                 mac_offset = 0x10;
13643
13644         /* First try to get it from MAC address mailbox. */
13645         tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
13646         if ((hi >> 16) == 0x484b) {
13647                 dev->dev_addr[0] = (hi >>  8) & 0xff;
13648                 dev->dev_addr[1] = (hi >>  0) & 0xff;
13649
13650                 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
13651                 dev->dev_addr[2] = (lo >> 24) & 0xff;
13652                 dev->dev_addr[3] = (lo >> 16) & 0xff;
13653                 dev->dev_addr[4] = (lo >>  8) & 0xff;
13654                 dev->dev_addr[5] = (lo >>  0) & 0xff;
13655
13656                 /* Some old bootcode may report a 0 MAC address in SRAM */
13657                 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
13658         }
13659         if (!addr_ok) {
13660                 /* Next, try NVRAM. */
13661                 if (!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) &&
13662                     !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
13663                     !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
13664                         memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
13665                         memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
13666                 }
13667                 /* Finally just fetch it out of the MAC control regs. */
13668                 else {
13669                         hi = tr32(MAC_ADDR_0_HIGH);
13670                         lo = tr32(MAC_ADDR_0_LOW);
13671
13672                         dev->dev_addr[5] = lo & 0xff;
13673                         dev->dev_addr[4] = (lo >> 8) & 0xff;
13674                         dev->dev_addr[3] = (lo >> 16) & 0xff;
13675                         dev->dev_addr[2] = (lo >> 24) & 0xff;
13676                         dev->dev_addr[1] = hi & 0xff;
13677                         dev->dev_addr[0] = (hi >> 8) & 0xff;
13678                 }
13679         }
13680
13681         if (!is_valid_ether_addr(&dev->dev_addr[0])) {
13682 #ifdef CONFIG_SPARC
13683                 if (!tg3_get_default_macaddr_sparc(tp))
13684                         return 0;
13685 #endif
13686                 return -EINVAL;
13687         }
13688         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
13689         return 0;
13690 }
13691
13692 #define BOUNDARY_SINGLE_CACHELINE       1
13693 #define BOUNDARY_MULTI_CACHELINE        2
13694
13695 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
13696 {
13697         int cacheline_size;
13698         u8 byte;
13699         int goal;
13700
13701         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
13702         if (byte == 0)
13703                 cacheline_size = 1024;
13704         else
13705                 cacheline_size = (int) byte * 4;
13706
13707         /* On 5703 and later chips, the boundary bits have no
13708          * effect.
13709          */
13710         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13711             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13712             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13713                 goto out;
13714
13715 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
13716         goal = BOUNDARY_MULTI_CACHELINE;
13717 #else
13718 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
13719         goal = BOUNDARY_SINGLE_CACHELINE;
13720 #else
13721         goal = 0;
13722 #endif
13723 #endif
13724
13725         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13726             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
13727                 val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
13728                 goto out;
13729         }
13730
13731         if (!goal)
13732                 goto out;
13733
13734         /* PCI controllers on most RISC systems tend to disconnect
13735          * when a device tries to burst across a cache-line boundary.
13736          * Therefore, letting tg3 do so just wastes PCI bandwidth.
13737          *
13738          * Unfortunately, for PCI-E there are only limited
13739          * write-side controls for this, and thus for reads
13740          * we will still get the disconnects.  We'll also waste
13741          * these PCI cycles for both read and write for chips
13742          * other than 5700 and 5701 which do not implement the
13743          * boundary bits.
13744          */
13745         if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13746             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
13747                 switch (cacheline_size) {
13748                 case 16:
13749                 case 32:
13750                 case 64:
13751                 case 128:
13752                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13753                                 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
13754                                         DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
13755                         } else {
13756                                 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13757                                         DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13758                         }
13759                         break;
13760
13761                 case 256:
13762                         val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
13763                                 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
13764                         break;
13765
13766                 default:
13767                         val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13768                                 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13769                         break;
13770                 }
13771         } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13772                 switch (cacheline_size) {
13773                 case 16:
13774                 case 32:
13775                 case 64:
13776                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13777                                 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13778                                 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
13779                                 break;
13780                         }
13781                         /* fallthrough */
13782                 case 128:
13783                 default:
13784                         val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13785                         val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
13786                         break;
13787                 }
13788         } else {
13789                 switch (cacheline_size) {
13790                 case 16:
13791                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13792                                 val |= (DMA_RWCTRL_READ_BNDRY_16 |
13793                                         DMA_RWCTRL_WRITE_BNDRY_16);
13794                                 break;
13795                         }
13796                         /* fallthrough */
13797                 case 32:
13798                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13799                                 val |= (DMA_RWCTRL_READ_BNDRY_32 |
13800                                         DMA_RWCTRL_WRITE_BNDRY_32);
13801                                 break;
13802                         }
13803                         /* fallthrough */
13804                 case 64:
13805                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13806                                 val |= (DMA_RWCTRL_READ_BNDRY_64 |
13807                                         DMA_RWCTRL_WRITE_BNDRY_64);
13808                                 break;
13809                         }
13810                         /* fallthrough */
13811                 case 128:
13812                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13813                                 val |= (DMA_RWCTRL_READ_BNDRY_128 |
13814                                         DMA_RWCTRL_WRITE_BNDRY_128);
13815                                 break;
13816                         }
13817                         /* fallthrough */
13818                 case 256:
13819                         val |= (DMA_RWCTRL_READ_BNDRY_256 |
13820                                 DMA_RWCTRL_WRITE_BNDRY_256);
13821                         break;
13822                 case 512:
13823                         val |= (DMA_RWCTRL_READ_BNDRY_512 |
13824                                 DMA_RWCTRL_WRITE_BNDRY_512);
13825                         break;
13826                 case 1024:
13827                 default:
13828                         val |= (DMA_RWCTRL_READ_BNDRY_1024 |
13829                                 DMA_RWCTRL_WRITE_BNDRY_1024);
13830                         break;
13831                 }
13832         }
13833
13834 out:
13835         return val;
13836 }
13837
13838 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
13839 {
13840         struct tg3_internal_buffer_desc test_desc;
13841         u32 sram_dma_descs;
13842         int i, ret;
13843
13844         sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
13845
13846         tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
13847         tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
13848         tw32(RDMAC_STATUS, 0);
13849         tw32(WDMAC_STATUS, 0);
13850
13851         tw32(BUFMGR_MODE, 0);
13852         tw32(FTQ_RESET, 0);
13853
13854         test_desc.addr_hi = ((u64) buf_dma) >> 32;
13855         test_desc.addr_lo = buf_dma & 0xffffffff;
13856         test_desc.nic_mbuf = 0x00002100;
13857         test_desc.len = size;
13858
13859         /*
13860          * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
13861          * the *second* time the tg3 driver was getting loaded after an
13862          * initial scan.
13863          *
13864          * Broadcom tells me:
13865          *   ...the DMA engine is connected to the GRC block and a DMA
13866          *   reset may affect the GRC block in some unpredictable way...
13867          *   The behavior of resets to individual blocks has not been tested.
13868          *
13869          * Broadcom noted the GRC reset will also reset all sub-components.
13870          */
13871         if (to_device) {
13872                 test_desc.cqid_sqid = (13 << 8) | 2;
13873
13874                 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
13875                 udelay(40);
13876         } else {
13877                 test_desc.cqid_sqid = (16 << 8) | 7;
13878
13879                 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
13880                 udelay(40);
13881         }
13882         test_desc.flags = 0x00000005;
13883
13884         for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
13885                 u32 val;
13886
13887                 val = *(((u32 *)&test_desc) + i);
13888                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
13889                                        sram_dma_descs + (i * sizeof(u32)));
13890                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
13891         }
13892         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
13893
13894         if (to_device) {
13895                 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
13896         } else {
13897                 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
13898         }
13899
13900         ret = -ENODEV;
13901         for (i = 0; i < 40; i++) {
13902                 u32 val;
13903
13904                 if (to_device)
13905                         val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
13906                 else
13907                         val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
13908                 if ((val & 0xffff) == sram_dma_descs) {
13909                         ret = 0;
13910                         break;
13911                 }
13912
13913                 udelay(100);
13914         }
13915
13916         return ret;
13917 }
13918
13919 #define TEST_BUFFER_SIZE        0x2000
13920
13921 static int __devinit tg3_test_dma(struct tg3 *tp)
13922 {
13923         dma_addr_t buf_dma;
13924         u32 *buf, saved_dma_rwctrl;
13925         int ret = 0;
13926
13927         buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
13928         if (!buf) {
13929                 ret = -ENOMEM;
13930                 goto out_nofree;
13931         }
13932
13933         tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
13934                           (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
13935
13936         tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
13937
13938         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13939             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13940                 goto out;
13941
13942         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13943                 /* DMA read watermark not used on PCIE */
13944                 tp->dma_rwctrl |= 0x00180000;
13945         } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
13946                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
13947                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
13948                         tp->dma_rwctrl |= 0x003f0000;
13949                 else
13950                         tp->dma_rwctrl |= 0x003f000f;
13951         } else {
13952                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13953                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
13954                         u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
13955                         u32 read_water = 0x7;
13956
13957                         /* If the 5704 is behind the EPB bridge, we can
13958                          * do the less restrictive ONE_DMA workaround for
13959                          * better performance.
13960                          */
13961                         if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
13962                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13963                                 tp->dma_rwctrl |= 0x8000;
13964                         else if (ccval == 0x6 || ccval == 0x7)
13965                                 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
13966
13967                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
13968                                 read_water = 4;
13969                         /* Set bit 23 to enable PCIX hw bug fix */
13970                         tp->dma_rwctrl |=
13971                                 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
13972                                 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
13973                                 (1 << 23);
13974                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
13975                         /* 5780 always in PCIX mode */
13976                         tp->dma_rwctrl |= 0x00144000;
13977                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
13978                         /* 5714 always in PCIX mode */
13979                         tp->dma_rwctrl |= 0x00148000;
13980                 } else {
13981                         tp->dma_rwctrl |= 0x001b000f;
13982                 }
13983         }
13984
13985         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13986             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13987                 tp->dma_rwctrl &= 0xfffffff0;
13988
13989         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13990             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
13991                 /* Remove this if it causes problems for some boards. */
13992                 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
13993
13994                 /* On 5700/5701 chips, we need to set this bit.
13995                  * Otherwise the chip will issue cacheline transactions
13996                  * to streamable DMA memory with not all the byte
13997                  * enables turned on.  This is an error on several
13998                  * RISC PCI controllers, in particular sparc64.
13999                  *
14000                  * On 5703/5704 chips, this bit has been reassigned
14001                  * a different meaning.  In particular, it is used
14002                  * on those chips to enable a PCI-X workaround.
14003                  */
14004                 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
14005         }
14006
14007         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14008
14009 #if 0
14010         /* Unneeded, already done by tg3_get_invariants.  */
14011         tg3_switch_clocks(tp);
14012 #endif
14013
14014         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
14015             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
14016                 goto out;
14017
14018         /* It is best to perform DMA test with maximum write burst size
14019          * to expose the 5700/5701 write DMA bug.
14020          */
14021         saved_dma_rwctrl = tp->dma_rwctrl;
14022         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14023         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14024
14025         while (1) {
14026                 u32 *p = buf, i;
14027
14028                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
14029                         p[i] = i;
14030
14031                 /* Send the buffer to the chip. */
14032                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
14033                 if (ret) {
14034                         printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
14035                         break;
14036                 }
14037
14038 #if 0
14039                 /* validate data reached card RAM correctly. */
14040                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
14041                         u32 val;
14042                         tg3_read_mem(tp, 0x2100 + (i*4), &val);
14043                         if (le32_to_cpu(val) != p[i]) {
14044                                 printk(KERN_ERR "  tg3_test_dma()  Card buffer corrupted on write! (%d != %d)\n", val, i);
14045                                 /* ret = -ENODEV here? */
14046                         }
14047                         p[i] = 0;
14048                 }
14049 #endif
14050                 /* Now read it back. */
14051                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
14052                 if (ret) {
14053                         printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
14054
14055                         break;
14056                 }
14057
14058                 /* Verify it. */
14059                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
14060                         if (p[i] == i)
14061                                 continue;
14062
14063                         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
14064                             DMA_RWCTRL_WRITE_BNDRY_16) {
14065                                 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14066                                 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14067                                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14068                                 break;
14069                         } else {
14070                                 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
14071                                 ret = -ENODEV;
14072                                 goto out;
14073                         }
14074                 }
14075
14076                 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
14077                         /* Success. */
14078                         ret = 0;
14079                         break;
14080                 }
14081         }
14082         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
14083             DMA_RWCTRL_WRITE_BNDRY_16) {
14084                 static struct pci_device_id dma_wait_state_chipsets[] = {
14085                         { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
14086                                      PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
14087                         { },
14088                 };
14089
14090                 /* DMA test passed without adjusting DMA boundary,
14091                  * now look for chipsets that are known to expose the
14092                  * DMA bug without failing the test.
14093                  */
14094                 if (pci_dev_present(dma_wait_state_chipsets)) {
14095                         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14096                         tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14097                 }
14098                 else
14099                         /* Safe to use the calculated DMA boundary. */
14100                         tp->dma_rwctrl = saved_dma_rwctrl;
14101
14102                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14103         }
14104
14105 out:
14106         pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
14107 out_nofree:
14108         return ret;
14109 }
14110
14111 static void __devinit tg3_init_link_config(struct tg3 *tp)
14112 {
14113         tp->link_config.advertising =
14114                 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
14115                  ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
14116                  ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
14117                  ADVERTISED_Autoneg | ADVERTISED_MII);
14118         tp->link_config.speed = SPEED_INVALID;
14119         tp->link_config.duplex = DUPLEX_INVALID;
14120         tp->link_config.autoneg = AUTONEG_ENABLE;
14121         tp->link_config.active_speed = SPEED_INVALID;
14122         tp->link_config.active_duplex = DUPLEX_INVALID;
14123         tp->link_config.phy_is_low_power = 0;
14124         tp->link_config.orig_speed = SPEED_INVALID;
14125         tp->link_config.orig_duplex = DUPLEX_INVALID;
14126         tp->link_config.orig_autoneg = AUTONEG_INVALID;
14127 }
14128
14129 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
14130 {
14131         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
14132             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
14133                 tp->bufmgr_config.mbuf_read_dma_low_water =
14134                         DEFAULT_MB_RDMA_LOW_WATER_5705;
14135                 tp->bufmgr_config.mbuf_mac_rx_low_water =
14136                         DEFAULT_MB_MACRX_LOW_WATER_57765;
14137                 tp->bufmgr_config.mbuf_high_water =
14138                         DEFAULT_MB_HIGH_WATER_57765;
14139
14140                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14141                         DEFAULT_MB_RDMA_LOW_WATER_5705;
14142                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14143                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765;
14144                 tp->bufmgr_config.mbuf_high_water_jumbo =
14145                         DEFAULT_MB_HIGH_WATER_JUMBO_57765;
14146         } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
14147                 tp->bufmgr_config.mbuf_read_dma_low_water =
14148                         DEFAULT_MB_RDMA_LOW_WATER_5705;
14149                 tp->bufmgr_config.mbuf_mac_rx_low_water =
14150                         DEFAULT_MB_MACRX_LOW_WATER_5705;
14151                 tp->bufmgr_config.mbuf_high_water =
14152                         DEFAULT_MB_HIGH_WATER_5705;
14153                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
14154                         tp->bufmgr_config.mbuf_mac_rx_low_water =
14155                                 DEFAULT_MB_MACRX_LOW_WATER_5906;
14156                         tp->bufmgr_config.mbuf_high_water =
14157                                 DEFAULT_MB_HIGH_WATER_5906;
14158                 }
14159
14160                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14161                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
14162                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14163                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
14164                 tp->bufmgr_config.mbuf_high_water_jumbo =
14165                         DEFAULT_MB_HIGH_WATER_JUMBO_5780;
14166         } else {
14167                 tp->bufmgr_config.mbuf_read_dma_low_water =
14168                         DEFAULT_MB_RDMA_LOW_WATER;
14169                 tp->bufmgr_config.mbuf_mac_rx_low_water =
14170                         DEFAULT_MB_MACRX_LOW_WATER;
14171                 tp->bufmgr_config.mbuf_high_water =
14172                         DEFAULT_MB_HIGH_WATER;
14173
14174                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14175                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
14176                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14177                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
14178                 tp->bufmgr_config.mbuf_high_water_jumbo =
14179                         DEFAULT_MB_HIGH_WATER_JUMBO;
14180         }
14181
14182         tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
14183         tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
14184 }
14185
14186 static char * __devinit tg3_phy_string(struct tg3 *tp)
14187 {
14188         switch (tp->phy_id & PHY_ID_MASK) {
14189         case PHY_ID_BCM5400:    return "5400";
14190         case PHY_ID_BCM5401:    return "5401";
14191         case PHY_ID_BCM5411:    return "5411";
14192         case PHY_ID_BCM5701:    return "5701";
14193         case PHY_ID_BCM5703:    return "5703";
14194         case PHY_ID_BCM5704:    return "5704";
14195         case PHY_ID_BCM5705:    return "5705";
14196         case PHY_ID_BCM5750:    return "5750";
14197         case PHY_ID_BCM5752:    return "5752";
14198         case PHY_ID_BCM5714:    return "5714";
14199         case PHY_ID_BCM5780:    return "5780";
14200         case PHY_ID_BCM5755:    return "5755";
14201         case PHY_ID_BCM5787:    return "5787";
14202         case PHY_ID_BCM5784:    return "5784";
14203         case PHY_ID_BCM5756:    return "5722/5756";
14204         case PHY_ID_BCM5906:    return "5906";
14205         case PHY_ID_BCM5761:    return "5761";
14206         case PHY_ID_BCM5718C:   return "5718C";
14207         case PHY_ID_BCM5718S:   return "5718S";
14208         case PHY_ID_BCM57765:   return "57765";
14209         case PHY_ID_BCM8002:    return "8002/serdes";
14210         case 0:                 return "serdes";
14211         default:                return "unknown";
14212         }
14213 }
14214
14215 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
14216 {
14217         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
14218                 strcpy(str, "PCI Express");
14219                 return str;
14220         } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
14221                 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
14222
14223                 strcpy(str, "PCIX:");
14224
14225                 if ((clock_ctrl == 7) ||
14226                     ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
14227                      GRC_MISC_CFG_BOARD_ID_5704CIOBE))
14228                         strcat(str, "133MHz");
14229                 else if (clock_ctrl == 0)
14230                         strcat(str, "33MHz");
14231                 else if (clock_ctrl == 2)
14232                         strcat(str, "50MHz");
14233                 else if (clock_ctrl == 4)
14234                         strcat(str, "66MHz");
14235                 else if (clock_ctrl == 6)
14236                         strcat(str, "100MHz");
14237         } else {
14238                 strcpy(str, "PCI:");
14239                 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
14240                         strcat(str, "66MHz");
14241                 else
14242                         strcat(str, "33MHz");
14243         }
14244         if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
14245                 strcat(str, ":32-bit");
14246         else
14247                 strcat(str, ":64-bit");
14248         return str;
14249 }
14250
14251 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
14252 {
14253         struct pci_dev *peer;
14254         unsigned int func, devnr = tp->pdev->devfn & ~7;
14255
14256         for (func = 0; func < 8; func++) {
14257                 peer = pci_get_slot(tp->pdev->bus, devnr | func);
14258                 if (peer && peer != tp->pdev)
14259                         break;
14260                 pci_dev_put(peer);
14261         }
14262         /* 5704 can be configured in single-port mode, set peer to
14263          * tp->pdev in that case.
14264          */
14265         if (!peer) {
14266                 peer = tp->pdev;
14267                 return peer;
14268         }
14269
14270         /*
14271          * We don't need to keep the refcount elevated; there's no way
14272          * to remove one half of this device without removing the other
14273          */
14274         pci_dev_put(peer);
14275
14276         return peer;
14277 }
14278
14279 static void __devinit tg3_init_coal(struct tg3 *tp)
14280 {
14281         struct ethtool_coalesce *ec = &tp->coal;
14282
14283         memset(ec, 0, sizeof(*ec));
14284         ec->cmd = ETHTOOL_GCOALESCE;
14285         ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
14286         ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
14287         ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
14288         ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
14289         ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
14290         ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
14291         ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
14292         ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
14293         ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
14294
14295         if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
14296                                  HOSTCC_MODE_CLRTICK_TXBD)) {
14297                 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
14298                 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
14299                 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
14300                 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
14301         }
14302
14303         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
14304                 ec->rx_coalesce_usecs_irq = 0;
14305                 ec->tx_coalesce_usecs_irq = 0;
14306                 ec->stats_block_coalesce_usecs = 0;
14307         }
14308 }
14309
14310 static const struct net_device_ops tg3_netdev_ops = {
14311         .ndo_open               = tg3_open,
14312         .ndo_stop               = tg3_close,
14313         .ndo_start_xmit         = tg3_start_xmit,
14314         .ndo_get_stats          = tg3_get_stats,
14315         .ndo_validate_addr      = eth_validate_addr,
14316         .ndo_set_multicast_list = tg3_set_rx_mode,
14317         .ndo_set_mac_address    = tg3_set_mac_addr,
14318         .ndo_do_ioctl           = tg3_ioctl,
14319         .ndo_tx_timeout         = tg3_tx_timeout,
14320         .ndo_change_mtu         = tg3_change_mtu,
14321 #if TG3_VLAN_TAG_USED
14322         .ndo_vlan_rx_register   = tg3_vlan_rx_register,
14323 #endif
14324 #ifdef CONFIG_NET_POLL_CONTROLLER
14325         .ndo_poll_controller    = tg3_poll_controller,
14326 #endif
14327 };
14328
14329 static const struct net_device_ops tg3_netdev_ops_dma_bug = {
14330         .ndo_open               = tg3_open,
14331         .ndo_stop               = tg3_close,
14332         .ndo_start_xmit         = tg3_start_xmit_dma_bug,
14333         .ndo_get_stats          = tg3_get_stats,
14334         .ndo_validate_addr      = eth_validate_addr,
14335         .ndo_set_multicast_list = tg3_set_rx_mode,
14336         .ndo_set_mac_address    = tg3_set_mac_addr,
14337         .ndo_do_ioctl           = tg3_ioctl,
14338         .ndo_tx_timeout         = tg3_tx_timeout,
14339         .ndo_change_mtu         = tg3_change_mtu,
14340 #if TG3_VLAN_TAG_USED
14341         .ndo_vlan_rx_register   = tg3_vlan_rx_register,
14342 #endif
14343 #ifdef CONFIG_NET_POLL_CONTROLLER
14344         .ndo_poll_controller    = tg3_poll_controller,
14345 #endif
14346 };
14347
14348 static int __devinit tg3_init_one(struct pci_dev *pdev,
14349                                   const struct pci_device_id *ent)
14350 {
14351         static int tg3_version_printed = 0;
14352         struct net_device *dev;
14353         struct tg3 *tp;
14354         int i, err, pm_cap;
14355         u32 sndmbx, rcvmbx, intmbx;
14356         char str[40];
14357         u64 dma_mask, persist_dma_mask;
14358
14359         if (tg3_version_printed++ == 0)
14360                 printk(KERN_INFO "%s", version);
14361
14362         err = pci_enable_device(pdev);
14363         if (err) {
14364                 printk(KERN_ERR PFX "Cannot enable PCI device, "
14365                        "aborting.\n");
14366                 return err;
14367         }
14368
14369         err = pci_request_regions(pdev, DRV_MODULE_NAME);
14370         if (err) {
14371                 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
14372                        "aborting.\n");
14373                 goto err_out_disable_pdev;
14374         }
14375
14376         pci_set_master(pdev);
14377
14378         /* Find power-management capability. */
14379         pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
14380         if (pm_cap == 0) {
14381                 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
14382                        "aborting.\n");
14383                 err = -EIO;
14384                 goto err_out_free_res;
14385         }
14386
14387         dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
14388         if (!dev) {
14389                 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
14390                 err = -ENOMEM;
14391                 goto err_out_free_res;
14392         }
14393
14394         SET_NETDEV_DEV(dev, &pdev->dev);
14395
14396 #if TG3_VLAN_TAG_USED
14397         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
14398 #endif
14399
14400         tp = netdev_priv(dev);
14401         tp->pdev = pdev;
14402         tp->dev = dev;
14403         tp->pm_cap = pm_cap;
14404         tp->rx_mode = TG3_DEF_RX_MODE;
14405         tp->tx_mode = TG3_DEF_TX_MODE;
14406
14407         if (tg3_debug > 0)
14408                 tp->msg_enable = tg3_debug;
14409         else
14410                 tp->msg_enable = TG3_DEF_MSG_ENABLE;
14411
14412         /* The word/byte swap controls here control register access byte
14413          * swapping.  DMA data byte swapping is controlled in the GRC_MODE
14414          * setting below.
14415          */
14416         tp->misc_host_ctrl =
14417                 MISC_HOST_CTRL_MASK_PCI_INT |
14418                 MISC_HOST_CTRL_WORD_SWAP |
14419                 MISC_HOST_CTRL_INDIR_ACCESS |
14420                 MISC_HOST_CTRL_PCISTATE_RW;
14421
14422         /* The NONFRM (non-frame) byte/word swap controls take effect
14423          * on descriptor entries, anything which isn't packet data.
14424          *
14425          * The StrongARM chips on the board (one for tx, one for rx)
14426          * are running in big-endian mode.
14427          */
14428         tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
14429                         GRC_MODE_WSWAP_NONFRM_DATA);
14430 #ifdef __BIG_ENDIAN
14431         tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
14432 #endif
14433         spin_lock_init(&tp->lock);
14434         spin_lock_init(&tp->indirect_lock);
14435         INIT_WORK(&tp->reset_task, tg3_reset_task);
14436
14437         tp->regs = pci_ioremap_bar(pdev, BAR_0);
14438         if (!tp->regs) {
14439                 printk(KERN_ERR PFX "Cannot map device registers, "
14440                        "aborting.\n");
14441                 err = -ENOMEM;
14442                 goto err_out_free_dev;
14443         }
14444
14445         tg3_init_link_config(tp);
14446
14447         tp->rx_pending = TG3_DEF_RX_RING_PENDING;
14448         tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
14449
14450         dev->ethtool_ops = &tg3_ethtool_ops;
14451         dev->watchdog_timeo = TG3_TX_TIMEOUT;
14452         dev->irq = pdev->irq;
14453
14454         err = tg3_get_invariants(tp);
14455         if (err) {
14456                 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
14457                        "aborting.\n");
14458                 goto err_out_iounmap;
14459         }
14460
14461         if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
14462             tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
14463                 dev->netdev_ops = &tg3_netdev_ops;
14464         else
14465                 dev->netdev_ops = &tg3_netdev_ops_dma_bug;
14466
14467
14468         /* The EPB bridge inside 5714, 5715, and 5780 and any
14469          * device behind the EPB cannot support DMA addresses > 40-bit.
14470          * On 64-bit systems with IOMMU, use 40-bit dma_mask.
14471          * On 64-bit systems without IOMMU, use 64-bit dma_mask and
14472          * do DMA address check in tg3_start_xmit().
14473          */
14474         if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
14475                 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
14476         else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
14477                 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
14478 #ifdef CONFIG_HIGHMEM
14479                 dma_mask = DMA_BIT_MASK(64);
14480 #endif
14481         } else
14482                 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
14483
14484         /* Configure DMA attributes. */
14485         if (dma_mask > DMA_BIT_MASK(32)) {
14486                 err = pci_set_dma_mask(pdev, dma_mask);
14487                 if (!err) {
14488                         dev->features |= NETIF_F_HIGHDMA;
14489                         err = pci_set_consistent_dma_mask(pdev,
14490                                                           persist_dma_mask);
14491                         if (err < 0) {
14492                                 printk(KERN_ERR PFX "Unable to obtain 64 bit "
14493                                        "DMA for consistent allocations\n");
14494                                 goto err_out_iounmap;
14495                         }
14496                 }
14497         }
14498         if (err || dma_mask == DMA_BIT_MASK(32)) {
14499                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
14500                 if (err) {
14501                         printk(KERN_ERR PFX "No usable DMA configuration, "
14502                                "aborting.\n");
14503                         goto err_out_iounmap;
14504                 }
14505         }
14506
14507         tg3_init_bufmgr_config(tp);
14508
14509         /* Selectively allow TSO based on operating conditions */
14510         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
14511             (tp->fw_needed && !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)))
14512                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
14513         else {
14514                 tp->tg3_flags2 &= ~(TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG);
14515                 tp->fw_needed = NULL;
14516         }
14517
14518         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
14519                 tp->fw_needed = FIRMWARE_TG3;
14520
14521         /* TSO is on by default on chips that support hardware TSO.
14522          * Firmware TSO on older chips gives lower performance, so it
14523          * is off by default, but can be enabled using ethtool.
14524          */
14525         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) &&
14526             (dev->features & NETIF_F_IP_CSUM))
14527                 dev->features |= NETIF_F_TSO;
14528
14529         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
14530             (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3)) {
14531                 if (dev->features & NETIF_F_IPV6_CSUM)
14532                         dev->features |= NETIF_F_TSO6;
14533                 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
14534                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
14535                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
14536                      GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
14537                         GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
14538                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
14539                         dev->features |= NETIF_F_TSO_ECN;
14540         }
14541
14542         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
14543             !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
14544             !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
14545                 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
14546                 tp->rx_pending = 63;
14547         }
14548
14549         err = tg3_get_device_address(tp);
14550         if (err) {
14551                 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
14552                        "aborting.\n");
14553                 goto err_out_iounmap;
14554         }
14555
14556         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
14557                 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
14558                 if (!tp->aperegs) {
14559                         printk(KERN_ERR PFX "Cannot map APE registers, "
14560                                "aborting.\n");
14561                         err = -ENOMEM;
14562                         goto err_out_iounmap;
14563                 }
14564
14565                 tg3_ape_lock_init(tp);
14566
14567                 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
14568                         tg3_read_dash_ver(tp);
14569         }
14570
14571         /*
14572          * Reset chip in case UNDI or EFI driver did not shutdown
14573          * DMA self test will enable WDMAC and we'll see (spurious)
14574          * pending DMA on the PCI bus at that point.
14575          */
14576         if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
14577             (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
14578                 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
14579                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14580         }
14581
14582         err = tg3_test_dma(tp);
14583         if (err) {
14584                 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
14585                 goto err_out_apeunmap;
14586         }
14587
14588         /* flow control autonegotiation is default behavior */
14589         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
14590         tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
14591
14592         intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
14593         rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
14594         sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
14595         for (i = 0; i < TG3_IRQ_MAX_VECS; i++) {
14596                 struct tg3_napi *tnapi = &tp->napi[i];
14597
14598                 tnapi->tp = tp;
14599                 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
14600
14601                 tnapi->int_mbox = intmbx;
14602                 if (i < 4)
14603                         intmbx += 0x8;
14604                 else
14605                         intmbx += 0x4;
14606
14607                 tnapi->consmbox = rcvmbx;
14608                 tnapi->prodmbox = sndmbx;
14609
14610                 if (i) {
14611                         tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
14612                         netif_napi_add(dev, &tnapi->napi, tg3_poll_msix, 64);
14613                 } else {
14614                         tnapi->coal_now = HOSTCC_MODE_NOW;
14615                         netif_napi_add(dev, &tnapi->napi, tg3_poll, 64);
14616                 }
14617
14618                 if (!(tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX))
14619                         break;
14620
14621                 /*
14622                  * If we support MSIX, we'll be using RSS.  If we're using
14623                  * RSS, the first vector only handles link interrupts and the
14624                  * remaining vectors handle rx and tx interrupts.  Reuse the
14625                  * mailbox values for the next iteration.  The values we setup
14626                  * above are still useful for the single vectored mode.
14627                  */
14628                 if (!i)
14629                         continue;
14630
14631                 rcvmbx += 0x8;
14632
14633                 if (sndmbx & 0x4)
14634                         sndmbx -= 0x4;
14635                 else
14636                         sndmbx += 0xc;
14637         }
14638
14639         tg3_init_coal(tp);
14640
14641         pci_set_drvdata(pdev, dev);
14642
14643         err = register_netdev(dev);
14644         if (err) {
14645                 printk(KERN_ERR PFX "Cannot register net device, "
14646                        "aborting.\n");
14647                 goto err_out_apeunmap;
14648         }
14649
14650         printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
14651                dev->name,
14652                tp->board_part_number,
14653                tp->pci_chip_rev_id,
14654                tg3_bus_string(tp, str),
14655                dev->dev_addr);
14656
14657         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
14658                 struct phy_device *phydev;
14659                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
14660                 printk(KERN_INFO
14661                        "%s: attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
14662                        tp->dev->name, phydev->drv->name,
14663                        dev_name(&phydev->dev));
14664         } else
14665                 printk(KERN_INFO
14666                        "%s: attached PHY is %s (%s Ethernet) (WireSpeed[%d])\n",
14667                        tp->dev->name, tg3_phy_string(tp),
14668                        ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
14669                         ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
14670                          "10/100/1000Base-T")),
14671                        (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0);
14672
14673         printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
14674                dev->name,
14675                (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
14676                (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
14677                (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
14678                (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
14679                (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
14680         printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
14681                dev->name, tp->dma_rwctrl,
14682                (pdev->dma_mask == DMA_BIT_MASK(32)) ? 32 :
14683                 (((u64) pdev->dma_mask == DMA_BIT_MASK(40)) ? 40 : 64));
14684
14685         return 0;
14686
14687 err_out_apeunmap:
14688         if (tp->aperegs) {
14689                 iounmap(tp->aperegs);
14690                 tp->aperegs = NULL;
14691         }
14692
14693 err_out_iounmap:
14694         if (tp->regs) {
14695                 iounmap(tp->regs);
14696                 tp->regs = NULL;
14697         }
14698
14699 err_out_free_dev:
14700         free_netdev(dev);
14701
14702 err_out_free_res:
14703         pci_release_regions(pdev);
14704
14705 err_out_disable_pdev:
14706         pci_disable_device(pdev);
14707         pci_set_drvdata(pdev, NULL);
14708         return err;
14709 }
14710
14711 static void __devexit tg3_remove_one(struct pci_dev *pdev)
14712 {
14713         struct net_device *dev = pci_get_drvdata(pdev);
14714
14715         if (dev) {
14716                 struct tg3 *tp = netdev_priv(dev);
14717
14718                 if (tp->fw)
14719                         release_firmware(tp->fw);
14720
14721                 flush_scheduled_work();
14722
14723                 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
14724                         tg3_phy_fini(tp);
14725                         tg3_mdio_fini(tp);
14726                 }
14727
14728                 unregister_netdev(dev);
14729                 if (tp->aperegs) {
14730                         iounmap(tp->aperegs);
14731                         tp->aperegs = NULL;
14732                 }
14733                 if (tp->regs) {
14734                         iounmap(tp->regs);
14735                         tp->regs = NULL;
14736                 }
14737                 free_netdev(dev);
14738                 pci_release_regions(pdev);
14739                 pci_disable_device(pdev);
14740                 pci_set_drvdata(pdev, NULL);
14741         }
14742 }
14743
14744 static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
14745 {
14746         struct net_device *dev = pci_get_drvdata(pdev);
14747         struct tg3 *tp = netdev_priv(dev);
14748         pci_power_t target_state;
14749         int err;
14750
14751         /* PCI register 4 needs to be saved whether netif_running() or not.
14752          * MSI address and data need to be saved if using MSI and
14753          * netif_running().
14754          */
14755         pci_save_state(pdev);
14756
14757         if (!netif_running(dev))
14758                 return 0;
14759
14760         flush_scheduled_work();
14761         tg3_phy_stop(tp);
14762         tg3_netif_stop(tp);
14763
14764         del_timer_sync(&tp->timer);
14765
14766         tg3_full_lock(tp, 1);
14767         tg3_disable_ints(tp);
14768         tg3_full_unlock(tp);
14769
14770         netif_device_detach(dev);
14771
14772         tg3_full_lock(tp, 0);
14773         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14774         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
14775         tg3_full_unlock(tp);
14776
14777         target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot;
14778
14779         err = tg3_set_power_state(tp, target_state);
14780         if (err) {
14781                 int err2;
14782
14783                 tg3_full_lock(tp, 0);
14784
14785                 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
14786                 err2 = tg3_restart_hw(tp, 1);
14787                 if (err2)
14788                         goto out;
14789
14790                 tp->timer.expires = jiffies + tp->timer_offset;
14791                 add_timer(&tp->timer);
14792
14793                 netif_device_attach(dev);
14794                 tg3_netif_start(tp);
14795
14796 out:
14797                 tg3_full_unlock(tp);
14798
14799                 if (!err2)
14800                         tg3_phy_start(tp);
14801         }
14802
14803         return err;
14804 }
14805
14806 static int tg3_resume(struct pci_dev *pdev)
14807 {
14808         struct net_device *dev = pci_get_drvdata(pdev);
14809         struct tg3 *tp = netdev_priv(dev);
14810         int err;
14811
14812         pci_restore_state(tp->pdev);
14813
14814         if (!netif_running(dev))
14815                 return 0;
14816
14817         err = tg3_set_power_state(tp, PCI_D0);
14818         if (err)
14819                 return err;
14820
14821         netif_device_attach(dev);
14822
14823         tg3_full_lock(tp, 0);
14824
14825         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
14826         err = tg3_restart_hw(tp, 1);
14827         if (err)
14828                 goto out;
14829
14830         tp->timer.expires = jiffies + tp->timer_offset;
14831         add_timer(&tp->timer);
14832
14833         tg3_netif_start(tp);
14834
14835 out:
14836         tg3_full_unlock(tp);
14837
14838         if (!err)
14839                 tg3_phy_start(tp);
14840
14841         return err;
14842 }
14843
14844 static struct pci_driver tg3_driver = {
14845         .name           = DRV_MODULE_NAME,
14846         .id_table       = tg3_pci_tbl,
14847         .probe          = tg3_init_one,
14848         .remove         = __devexit_p(tg3_remove_one),
14849         .suspend        = tg3_suspend,
14850         .resume         = tg3_resume
14851 };
14852
14853 static int __init tg3_init(void)
14854 {
14855         return pci_register_driver(&tg3_driver);
14856 }
14857
14858 static void __exit tg3_cleanup(void)
14859 {
14860         pci_unregister_driver(&tg3_driver);
14861 }
14862
14863 module_init(tg3_init);
14864 module_exit(tg3_cleanup);