2 * tg3.c: Broadcom Tigon3 ethernet driver.
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
7 * Copyright (C) 2005-2010 Broadcom Corporation.
10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/stringify.h>
22 #include <linux/kernel.h>
23 #include <linux/types.h>
24 #include <linux/compiler.h>
25 #include <linux/slab.h>
26 #include <linux/delay.h>
28 #include <linux/init.h>
29 #include <linux/ioport.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/skbuff.h>
34 #include <linux/ethtool.h>
35 #include <linux/mdio.h>
36 #include <linux/mii.h>
37 #include <linux/phy.h>
38 #include <linux/brcmphy.h>
39 #include <linux/if_vlan.h>
41 #include <linux/tcp.h>
42 #include <linux/workqueue.h>
43 #include <linux/prefetch.h>
44 #include <linux/dma-mapping.h>
45 #include <linux/firmware.h>
47 #include <net/checksum.h>
50 #include <asm/system.h>
52 #include <asm/byteorder.h>
53 #include <asm/uaccess.h>
56 #include <asm/idprom.h>
63 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
64 #define TG3_VLAN_TAG_USED 1
66 #define TG3_VLAN_TAG_USED 0
71 #define DRV_MODULE_NAME "tg3"
73 #define TG3_MIN_NUM 115
74 #define DRV_MODULE_VERSION \
75 __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM)
76 #define DRV_MODULE_RELDATE "October 14, 2010"
78 #define TG3_DEF_MAC_MODE 0
79 #define TG3_DEF_RX_MODE 0
80 #define TG3_DEF_TX_MODE 0
81 #define TG3_DEF_MSG_ENABLE \
91 /* length of time before we decide the hardware is borked,
92 * and dev->tx_timeout() should be called to fix the problem
94 #define TG3_TX_TIMEOUT (5 * HZ)
96 /* hardware minimum and maximum for a single frame's data payload */
97 #define TG3_MIN_MTU 60
98 #define TG3_MAX_MTU(tp) \
99 ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
101 /* These numbers seem to be hard coded in the NIC firmware somehow.
102 * You can't change the ring sizes, but you can change where you place
103 * them in the NIC onboard memory.
105 #define TG3_RX_STD_RING_SIZE(tp) \
106 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || \
107 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) ? \
108 RX_STD_MAX_SIZE_5717 : 512)
109 #define TG3_DEF_RX_RING_PENDING 200
110 #define TG3_RX_JMB_RING_SIZE(tp) \
111 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || \
112 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) ? \
114 #define TG3_DEF_RX_JUMBO_RING_PENDING 100
115 #define TG3_RSS_INDIR_TBL_SIZE 128
117 /* Do not place this n-ring entries value into the tp struct itself,
118 * we really want to expose these constants to GCC so that modulo et
119 * al. operations are done with shifts and masks instead of with
120 * hw multiply/modulo instructions. Another solution would be to
121 * replace things like '% foo' with '& (foo - 1)'.
124 #define TG3_TX_RING_SIZE 512
125 #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
127 #define TG3_RX_STD_RING_BYTES(tp) \
128 (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_RING_SIZE(tp))
129 #define TG3_RX_JMB_RING_BYTES(tp) \
130 (sizeof(struct tg3_ext_rx_buffer_desc) * TG3_RX_JMB_RING_SIZE(tp))
131 #define TG3_RX_RCB_RING_BYTES(tp) \
132 (sizeof(struct tg3_rx_buffer_desc) * (tp->rx_ret_ring_mask + 1))
133 #define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
135 #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
137 #define TG3_RX_DMA_ALIGN 16
138 #define TG3_RX_HEADROOM ALIGN(VLAN_HLEN, TG3_RX_DMA_ALIGN)
140 #define TG3_DMA_BYTE_ENAB 64
142 #define TG3_RX_STD_DMA_SZ 1536
143 #define TG3_RX_JMB_DMA_SZ 9046
145 #define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB)
147 #define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
148 #define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
150 #define TG3_RX_STD_BUFF_RING_SIZE(tp) \
151 (sizeof(struct ring_info) * TG3_RX_STD_RING_SIZE(tp))
153 #define TG3_RX_JMB_BUFF_RING_SIZE(tp) \
154 (sizeof(struct ring_info) * TG3_RX_JMB_RING_SIZE(tp))
156 /* Due to a hardware bug, the 5701 can only DMA to memory addresses
157 * that are at least dword aligned when used in PCIX mode. The driver
158 * works around this bug by double copying the packet. This workaround
159 * is built into the normal double copy length check for efficiency.
161 * However, the double copy is only necessary on those architectures
162 * where unaligned memory accesses are inefficient. For those architectures
163 * where unaligned memory accesses incur little penalty, we can reintegrate
164 * the 5701 in the normal rx path. Doing so saves a device structure
165 * dereference by hardcoding the double copy threshold in place.
167 #define TG3_RX_COPY_THRESHOLD 256
168 #if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
169 #define TG3_RX_COPY_THRESH(tp) TG3_RX_COPY_THRESHOLD
171 #define TG3_RX_COPY_THRESH(tp) ((tp)->rx_copy_thresh)
174 /* minimum number of free TX descriptors required to wake up TX process */
175 #define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
177 #define TG3_RAW_IP_ALIGN 2
179 /* number of ETHTOOL_GSTATS u64's */
180 #define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
182 #define TG3_NUM_TEST 6
184 #define TG3_FW_UPDATE_TIMEOUT_SEC 5
186 #define FIRMWARE_TG3 "tigon/tg3.bin"
187 #define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
188 #define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
190 static char version[] __devinitdata =
191 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")";
193 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
194 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
195 MODULE_LICENSE("GPL");
196 MODULE_VERSION(DRV_MODULE_VERSION);
197 MODULE_FIRMWARE(FIRMWARE_TG3);
198 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
199 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
201 static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
202 module_param(tg3_debug, int, 0);
203 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
205 static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = {
206 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
207 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
208 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
209 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
210 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
211 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
212 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
213 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
214 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
215 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
216 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
217 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
218 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
219 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
220 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
221 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
222 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
223 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
224 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
225 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
226 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
227 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
228 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
229 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
230 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
231 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
232 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
233 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
234 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
235 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
236 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
237 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
238 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
239 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
240 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
241 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
242 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
243 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
244 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
245 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
246 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
247 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
248 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
249 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
250 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
251 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
252 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
253 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
254 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
255 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
256 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
257 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
258 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
259 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
260 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
261 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
262 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
263 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
264 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
265 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
266 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
267 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
268 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
269 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
270 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
271 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
272 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
273 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
274 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
275 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791)},
276 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795)},
277 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5719)},
278 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
279 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
280 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
281 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
282 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
283 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
284 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
288 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
290 static const struct {
291 const char string[ETH_GSTRING_LEN];
292 } ethtool_stats_keys[TG3_NUM_STATS] = {
295 { "rx_ucast_packets" },
296 { "rx_mcast_packets" },
297 { "rx_bcast_packets" },
299 { "rx_align_errors" },
300 { "rx_xon_pause_rcvd" },
301 { "rx_xoff_pause_rcvd" },
302 { "rx_mac_ctrl_rcvd" },
303 { "rx_xoff_entered" },
304 { "rx_frame_too_long_errors" },
306 { "rx_undersize_packets" },
307 { "rx_in_length_errors" },
308 { "rx_out_length_errors" },
309 { "rx_64_or_less_octet_packets" },
310 { "rx_65_to_127_octet_packets" },
311 { "rx_128_to_255_octet_packets" },
312 { "rx_256_to_511_octet_packets" },
313 { "rx_512_to_1023_octet_packets" },
314 { "rx_1024_to_1522_octet_packets" },
315 { "rx_1523_to_2047_octet_packets" },
316 { "rx_2048_to_4095_octet_packets" },
317 { "rx_4096_to_8191_octet_packets" },
318 { "rx_8192_to_9022_octet_packets" },
325 { "tx_flow_control" },
327 { "tx_single_collisions" },
328 { "tx_mult_collisions" },
330 { "tx_excessive_collisions" },
331 { "tx_late_collisions" },
332 { "tx_collide_2times" },
333 { "tx_collide_3times" },
334 { "tx_collide_4times" },
335 { "tx_collide_5times" },
336 { "tx_collide_6times" },
337 { "tx_collide_7times" },
338 { "tx_collide_8times" },
339 { "tx_collide_9times" },
340 { "tx_collide_10times" },
341 { "tx_collide_11times" },
342 { "tx_collide_12times" },
343 { "tx_collide_13times" },
344 { "tx_collide_14times" },
345 { "tx_collide_15times" },
346 { "tx_ucast_packets" },
347 { "tx_mcast_packets" },
348 { "tx_bcast_packets" },
349 { "tx_carrier_sense_errors" },
353 { "dma_writeq_full" },
354 { "dma_write_prioq_full" },
358 { "rx_threshold_hit" },
360 { "dma_readq_full" },
361 { "dma_read_prioq_full" },
362 { "tx_comp_queue_full" },
364 { "ring_set_send_prod_index" },
365 { "ring_status_update" },
367 { "nic_avoided_irqs" },
368 { "nic_tx_threshold_hit" }
371 static const struct {
372 const char string[ETH_GSTRING_LEN];
373 } ethtool_test_keys[TG3_NUM_TEST] = {
374 { "nvram test (online) " },
375 { "link test (online) " },
376 { "register test (offline)" },
377 { "memory test (offline)" },
378 { "loopback test (offline)" },
379 { "interrupt test (offline)" },
382 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
384 writel(val, tp->regs + off);
387 static u32 tg3_read32(struct tg3 *tp, u32 off)
389 return readl(tp->regs + off);
392 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
394 writel(val, tp->aperegs + off);
397 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
399 return readl(tp->aperegs + off);
402 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
406 spin_lock_irqsave(&tp->indirect_lock, flags);
407 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
408 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
409 spin_unlock_irqrestore(&tp->indirect_lock, flags);
412 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
414 writel(val, tp->regs + off);
415 readl(tp->regs + off);
418 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
423 spin_lock_irqsave(&tp->indirect_lock, flags);
424 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
425 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
426 spin_unlock_irqrestore(&tp->indirect_lock, flags);
430 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
434 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
435 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
436 TG3_64BIT_REG_LOW, val);
439 if (off == TG3_RX_STD_PROD_IDX_REG) {
440 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
441 TG3_64BIT_REG_LOW, val);
445 spin_lock_irqsave(&tp->indirect_lock, flags);
446 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
447 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
448 spin_unlock_irqrestore(&tp->indirect_lock, flags);
450 /* In indirect mode when disabling interrupts, we also need
451 * to clear the interrupt bit in the GRC local ctrl register.
453 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
455 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
456 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
460 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
465 spin_lock_irqsave(&tp->indirect_lock, flags);
466 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
467 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
468 spin_unlock_irqrestore(&tp->indirect_lock, flags);
472 /* usec_wait specifies the wait time in usec when writing to certain registers
473 * where it is unsafe to read back the register without some delay.
474 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
475 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
477 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
479 if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
480 (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
481 /* Non-posted methods */
482 tp->write32(tp, off, val);
485 tg3_write32(tp, off, val);
490 /* Wait again after the read for the posted method to guarantee that
491 * the wait time is met.
497 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
499 tp->write32_mbox(tp, off, val);
500 if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
501 !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
502 tp->read32_mbox(tp, off);
505 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
507 void __iomem *mbox = tp->regs + off;
509 if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
511 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
515 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
517 return readl(tp->regs + off + GRCMBOX_BASE);
520 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
522 writel(val, tp->regs + off + GRCMBOX_BASE);
525 #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
526 #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
527 #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
528 #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
529 #define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
531 #define tw32(reg, val) tp->write32(tp, reg, val)
532 #define tw32_f(reg, val) _tw32_flush(tp, (reg), (val), 0)
533 #define tw32_wait_f(reg, val, us) _tw32_flush(tp, (reg), (val), (us))
534 #define tr32(reg) tp->read32(tp, reg)
536 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
540 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
541 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
544 spin_lock_irqsave(&tp->indirect_lock, flags);
545 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
546 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
547 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
549 /* Always leave this as zero. */
550 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
552 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
553 tw32_f(TG3PCI_MEM_WIN_DATA, val);
555 /* Always leave this as zero. */
556 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
558 spin_unlock_irqrestore(&tp->indirect_lock, flags);
561 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
565 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
566 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
571 spin_lock_irqsave(&tp->indirect_lock, flags);
572 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
573 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
574 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
576 /* Always leave this as zero. */
577 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
579 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
580 *val = tr32(TG3PCI_MEM_WIN_DATA);
582 /* Always leave this as zero. */
583 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
585 spin_unlock_irqrestore(&tp->indirect_lock, flags);
588 static void tg3_ape_lock_init(struct tg3 *tp)
593 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
594 regbase = TG3_APE_LOCK_GRANT;
596 regbase = TG3_APE_PER_LOCK_GRANT;
598 /* Make sure the driver hasn't any stale locks. */
599 for (i = 0; i < 8; i++)
600 tg3_ape_write32(tp, regbase + 4 * i, APE_LOCK_GRANT_DRIVER);
603 static int tg3_ape_lock(struct tg3 *tp, int locknum)
607 u32 status, req, gnt;
609 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
613 case TG3_APE_LOCK_GRC:
614 case TG3_APE_LOCK_MEM:
620 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
621 req = TG3_APE_LOCK_REQ;
622 gnt = TG3_APE_LOCK_GRANT;
624 req = TG3_APE_PER_LOCK_REQ;
625 gnt = TG3_APE_PER_LOCK_GRANT;
630 tg3_ape_write32(tp, req + off, APE_LOCK_REQ_DRIVER);
632 /* Wait for up to 1 millisecond to acquire lock. */
633 for (i = 0; i < 100; i++) {
634 status = tg3_ape_read32(tp, gnt + off);
635 if (status == APE_LOCK_GRANT_DRIVER)
640 if (status != APE_LOCK_GRANT_DRIVER) {
641 /* Revoke the lock request. */
642 tg3_ape_write32(tp, gnt + off,
643 APE_LOCK_GRANT_DRIVER);
651 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
655 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
659 case TG3_APE_LOCK_GRC:
660 case TG3_APE_LOCK_MEM:
666 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
667 gnt = TG3_APE_LOCK_GRANT;
669 gnt = TG3_APE_PER_LOCK_GRANT;
671 tg3_ape_write32(tp, gnt + 4 * locknum, APE_LOCK_GRANT_DRIVER);
674 static void tg3_disable_ints(struct tg3 *tp)
678 tw32(TG3PCI_MISC_HOST_CTRL,
679 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
680 for (i = 0; i < tp->irq_max; i++)
681 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
684 static void tg3_enable_ints(struct tg3 *tp)
691 tw32(TG3PCI_MISC_HOST_CTRL,
692 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
694 tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
695 for (i = 0; i < tp->irq_cnt; i++) {
696 struct tg3_napi *tnapi = &tp->napi[i];
698 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
699 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
700 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
702 tp->coal_now |= tnapi->coal_now;
705 /* Force an initial interrupt */
706 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
707 (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
708 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
710 tw32(HOSTCC_MODE, tp->coal_now);
712 tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);
715 static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
717 struct tg3 *tp = tnapi->tp;
718 struct tg3_hw_status *sblk = tnapi->hw_status;
719 unsigned int work_exists = 0;
721 /* check for phy events */
722 if (!(tp->tg3_flags &
723 (TG3_FLAG_USE_LINKCHG_REG |
724 TG3_FLAG_POLL_SERDES))) {
725 if (sblk->status & SD_STATUS_LINK_CHG)
728 /* check for RX/TX work to do */
729 if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
730 *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
737 * similar to tg3_enable_ints, but it accurately determines whether there
738 * is new work pending and can return without flushing the PIO write
739 * which reenables interrupts
741 static void tg3_int_reenable(struct tg3_napi *tnapi)
743 struct tg3 *tp = tnapi->tp;
745 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
748 /* When doing tagged status, this work check is unnecessary.
749 * The last_tag we write above tells the chip which piece of
750 * work we've completed.
752 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
754 tw32(HOSTCC_MODE, tp->coalesce_mode |
755 HOSTCC_MODE_ENABLE | tnapi->coal_now);
758 static void tg3_switch_clocks(struct tg3 *tp)
763 if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
764 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
767 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
769 orig_clock_ctrl = clock_ctrl;
770 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
771 CLOCK_CTRL_CLKRUN_OENABLE |
773 tp->pci_clock_ctrl = clock_ctrl;
775 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
776 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
777 tw32_wait_f(TG3PCI_CLOCK_CTRL,
778 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
780 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
781 tw32_wait_f(TG3PCI_CLOCK_CTRL,
783 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
785 tw32_wait_f(TG3PCI_CLOCK_CTRL,
786 clock_ctrl | (CLOCK_CTRL_ALTCLK),
789 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
792 #define PHY_BUSY_LOOPS 5000
794 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
800 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
802 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
808 frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
809 MI_COM_PHY_ADDR_MASK);
810 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
811 MI_COM_REG_ADDR_MASK);
812 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
814 tw32_f(MAC_MI_COM, frame_val);
816 loops = PHY_BUSY_LOOPS;
819 frame_val = tr32(MAC_MI_COM);
821 if ((frame_val & MI_COM_BUSY) == 0) {
823 frame_val = tr32(MAC_MI_COM);
831 *val = frame_val & MI_COM_DATA_MASK;
835 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
836 tw32_f(MAC_MI_MODE, tp->mi_mode);
843 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
849 if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
850 (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
853 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
855 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
859 frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
860 MI_COM_PHY_ADDR_MASK);
861 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
862 MI_COM_REG_ADDR_MASK);
863 frame_val |= (val & MI_COM_DATA_MASK);
864 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
866 tw32_f(MAC_MI_COM, frame_val);
868 loops = PHY_BUSY_LOOPS;
871 frame_val = tr32(MAC_MI_COM);
872 if ((frame_val & MI_COM_BUSY) == 0) {
874 frame_val = tr32(MAC_MI_COM);
884 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
885 tw32_f(MAC_MI_MODE, tp->mi_mode);
892 static int tg3_bmcr_reset(struct tg3 *tp)
897 /* OK, reset it, and poll the BMCR_RESET bit until it
898 * clears or we time out.
900 phy_control = BMCR_RESET;
901 err = tg3_writephy(tp, MII_BMCR, phy_control);
907 err = tg3_readphy(tp, MII_BMCR, &phy_control);
911 if ((phy_control & BMCR_RESET) == 0) {
923 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
925 struct tg3 *tp = bp->priv;
928 spin_lock_bh(&tp->lock);
930 if (tg3_readphy(tp, reg, &val))
933 spin_unlock_bh(&tp->lock);
938 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
940 struct tg3 *tp = bp->priv;
943 spin_lock_bh(&tp->lock);
945 if (tg3_writephy(tp, reg, val))
948 spin_unlock_bh(&tp->lock);
953 static int tg3_mdio_reset(struct mii_bus *bp)
958 static void tg3_mdio_config_5785(struct tg3 *tp)
961 struct phy_device *phydev;
963 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
964 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
965 case PHY_ID_BCM50610:
966 case PHY_ID_BCM50610M:
967 val = MAC_PHYCFG2_50610_LED_MODES;
969 case PHY_ID_BCMAC131:
970 val = MAC_PHYCFG2_AC131_LED_MODES;
972 case PHY_ID_RTL8211C:
973 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
975 case PHY_ID_RTL8201E:
976 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
982 if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
983 tw32(MAC_PHYCFG2, val);
985 val = tr32(MAC_PHYCFG1);
986 val &= ~(MAC_PHYCFG1_RGMII_INT |
987 MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
988 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
989 tw32(MAC_PHYCFG1, val);
994 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE))
995 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
996 MAC_PHYCFG2_FMODE_MASK_MASK |
997 MAC_PHYCFG2_GMODE_MASK_MASK |
998 MAC_PHYCFG2_ACT_MASK_MASK |
999 MAC_PHYCFG2_QUAL_MASK_MASK |
1000 MAC_PHYCFG2_INBAND_ENABLE;
1002 tw32(MAC_PHYCFG2, val);
1004 val = tr32(MAC_PHYCFG1);
1005 val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
1006 MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
1007 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
1008 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1009 val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
1010 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1011 val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
1013 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1014 MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1015 tw32(MAC_PHYCFG1, val);
1017 val = tr32(MAC_EXT_RGMII_MODE);
1018 val &= ~(MAC_RGMII_MODE_RX_INT_B |
1019 MAC_RGMII_MODE_RX_QUALITY |
1020 MAC_RGMII_MODE_RX_ACTIVITY |
1021 MAC_RGMII_MODE_RX_ENG_DET |
1022 MAC_RGMII_MODE_TX_ENABLE |
1023 MAC_RGMII_MODE_TX_LOWPWR |
1024 MAC_RGMII_MODE_TX_RESET);
1025 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
1026 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1027 val |= MAC_RGMII_MODE_RX_INT_B |
1028 MAC_RGMII_MODE_RX_QUALITY |
1029 MAC_RGMII_MODE_RX_ACTIVITY |
1030 MAC_RGMII_MODE_RX_ENG_DET;
1031 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1032 val |= MAC_RGMII_MODE_TX_ENABLE |
1033 MAC_RGMII_MODE_TX_LOWPWR |
1034 MAC_RGMII_MODE_TX_RESET;
1036 tw32(MAC_EXT_RGMII_MODE, val);
1039 static void tg3_mdio_start(struct tg3 *tp)
1041 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1042 tw32_f(MAC_MI_MODE, tp->mi_mode);
1045 if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
1046 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1047 tg3_mdio_config_5785(tp);
1050 static int tg3_mdio_init(struct tg3 *tp)
1054 struct phy_device *phydev;
1056 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
1057 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
1060 tp->phy_addr = PCI_FUNC(tp->pdev->devfn) + 1;
1062 if (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
1063 is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1065 is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
1066 TG3_CPMU_PHY_STRAP_IS_SERDES;
1070 tp->phy_addr = TG3_PHY_MII_ADDR;
1074 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1075 (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1078 tp->mdio_bus = mdiobus_alloc();
1079 if (tp->mdio_bus == NULL)
1082 tp->mdio_bus->name = "tg3 mdio bus";
1083 snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1084 (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1085 tp->mdio_bus->priv = tp;
1086 tp->mdio_bus->parent = &tp->pdev->dev;
1087 tp->mdio_bus->read = &tg3_mdio_read;
1088 tp->mdio_bus->write = &tg3_mdio_write;
1089 tp->mdio_bus->reset = &tg3_mdio_reset;
1090 tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
1091 tp->mdio_bus->irq = &tp->mdio_irq[0];
1093 for (i = 0; i < PHY_MAX_ADDR; i++)
1094 tp->mdio_bus->irq[i] = PHY_POLL;
1096 /* The bus registration will look for all the PHYs on the mdio bus.
1097 * Unfortunately, it does not ensure the PHY is powered up before
1098 * accessing the PHY ID registers. A chip reset is the
1099 * quickest way to bring the device back to an operational state..
1101 if (tg3_readphy(tp, MII_BMCR, ®) || (reg & BMCR_PDOWN))
1104 i = mdiobus_register(tp->mdio_bus);
1106 dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i);
1107 mdiobus_free(tp->mdio_bus);
1111 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1113 if (!phydev || !phydev->drv) {
1114 dev_warn(&tp->pdev->dev, "No PHY devices\n");
1115 mdiobus_unregister(tp->mdio_bus);
1116 mdiobus_free(tp->mdio_bus);
1120 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1121 case PHY_ID_BCM57780:
1122 phydev->interface = PHY_INTERFACE_MODE_GMII;
1123 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1125 case PHY_ID_BCM50610:
1126 case PHY_ID_BCM50610M:
1127 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
1128 PHY_BRCM_RX_REFCLK_UNUSED |
1129 PHY_BRCM_DIS_TXCRXC_NOENRGY |
1130 PHY_BRCM_AUTO_PWRDWN_ENABLE;
1131 if (tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)
1132 phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1133 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1134 phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1135 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1136 phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1138 case PHY_ID_RTL8211C:
1139 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1141 case PHY_ID_RTL8201E:
1142 case PHY_ID_BCMAC131:
1143 phydev->interface = PHY_INTERFACE_MODE_MII;
1144 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1145 tp->phy_flags |= TG3_PHYFLG_IS_FET;
1149 tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1151 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1152 tg3_mdio_config_5785(tp);
1157 static void tg3_mdio_fini(struct tg3 *tp)
1159 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1160 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
1161 mdiobus_unregister(tp->mdio_bus);
1162 mdiobus_free(tp->mdio_bus);
1166 static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val)
1170 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1174 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1178 err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1179 MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1183 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val);
1189 static int tg3_phy_cl45_read(struct tg3 *tp, u32 devad, u32 addr, u32 *val)
1193 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1197 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1201 err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1202 MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1206 err = tg3_readphy(tp, MII_TG3_MMD_ADDRESS, val);
1212 /* tp->lock is held. */
1213 static inline void tg3_generate_fw_event(struct tg3 *tp)
1217 val = tr32(GRC_RX_CPU_EVENT);
1218 val |= GRC_RX_CPU_DRIVER_EVENT;
1219 tw32_f(GRC_RX_CPU_EVENT, val);
1221 tp->last_event_jiffies = jiffies;
1224 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1226 /* tp->lock is held. */
1227 static void tg3_wait_for_event_ack(struct tg3 *tp)
1230 unsigned int delay_cnt;
1233 /* If enough time has passed, no wait is necessary. */
1234 time_remain = (long)(tp->last_event_jiffies + 1 +
1235 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1237 if (time_remain < 0)
1240 /* Check if we can shorten the wait time. */
1241 delay_cnt = jiffies_to_usecs(time_remain);
1242 if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1243 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1244 delay_cnt = (delay_cnt >> 3) + 1;
1246 for (i = 0; i < delay_cnt; i++) {
1247 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1253 /* tp->lock is held. */
1254 static void tg3_ump_link_report(struct tg3 *tp)
1259 if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1260 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
1263 tg3_wait_for_event_ack(tp);
1265 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1267 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1270 if (!tg3_readphy(tp, MII_BMCR, ®))
1272 if (!tg3_readphy(tp, MII_BMSR, ®))
1273 val |= (reg & 0xffff);
1274 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1277 if (!tg3_readphy(tp, MII_ADVERTISE, ®))
1279 if (!tg3_readphy(tp, MII_LPA, ®))
1280 val |= (reg & 0xffff);
1281 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1284 if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) {
1285 if (!tg3_readphy(tp, MII_CTRL1000, ®))
1287 if (!tg3_readphy(tp, MII_STAT1000, ®))
1288 val |= (reg & 0xffff);
1290 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1292 if (!tg3_readphy(tp, MII_PHYADDR, ®))
1296 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1298 tg3_generate_fw_event(tp);
1301 static void tg3_link_report(struct tg3 *tp)
1303 if (!netif_carrier_ok(tp->dev)) {
1304 netif_info(tp, link, tp->dev, "Link is down\n");
1305 tg3_ump_link_report(tp);
1306 } else if (netif_msg_link(tp)) {
1307 netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n",
1308 (tp->link_config.active_speed == SPEED_1000 ?
1310 (tp->link_config.active_speed == SPEED_100 ?
1312 (tp->link_config.active_duplex == DUPLEX_FULL ?
1315 netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n",
1316 (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1318 (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1320 tg3_ump_link_report(tp);
1324 static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1328 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1329 miireg = ADVERTISE_PAUSE_CAP;
1330 else if (flow_ctrl & FLOW_CTRL_TX)
1331 miireg = ADVERTISE_PAUSE_ASYM;
1332 else if (flow_ctrl & FLOW_CTRL_RX)
1333 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1340 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1344 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1345 miireg = ADVERTISE_1000XPAUSE;
1346 else if (flow_ctrl & FLOW_CTRL_TX)
1347 miireg = ADVERTISE_1000XPSE_ASYM;
1348 else if (flow_ctrl & FLOW_CTRL_RX)
1349 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1356 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1360 if (lcladv & ADVERTISE_1000XPAUSE) {
1361 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1362 if (rmtadv & LPA_1000XPAUSE)
1363 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1364 else if (rmtadv & LPA_1000XPAUSE_ASYM)
1367 if (rmtadv & LPA_1000XPAUSE)
1368 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1370 } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1371 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1378 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1382 u32 old_rx_mode = tp->rx_mode;
1383 u32 old_tx_mode = tp->tx_mode;
1385 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
1386 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
1388 autoneg = tp->link_config.autoneg;
1390 if (autoneg == AUTONEG_ENABLE &&
1391 (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1392 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
1393 flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1395 flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1397 flowctrl = tp->link_config.flowctrl;
1399 tp->link_config.active_flowctrl = flowctrl;
1401 if (flowctrl & FLOW_CTRL_RX)
1402 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1404 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1406 if (old_rx_mode != tp->rx_mode)
1407 tw32_f(MAC_RX_MODE, tp->rx_mode);
1409 if (flowctrl & FLOW_CTRL_TX)
1410 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1412 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1414 if (old_tx_mode != tp->tx_mode)
1415 tw32_f(MAC_TX_MODE, tp->tx_mode);
1418 static void tg3_adjust_link(struct net_device *dev)
1420 u8 oldflowctrl, linkmesg = 0;
1421 u32 mac_mode, lcl_adv, rmt_adv;
1422 struct tg3 *tp = netdev_priv(dev);
1423 struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1425 spin_lock_bh(&tp->lock);
1427 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1428 MAC_MODE_HALF_DUPLEX);
1430 oldflowctrl = tp->link_config.active_flowctrl;
1436 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1437 mac_mode |= MAC_MODE_PORT_MODE_MII;
1438 else if (phydev->speed == SPEED_1000 ||
1439 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
1440 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1442 mac_mode |= MAC_MODE_PORT_MODE_MII;
1444 if (phydev->duplex == DUPLEX_HALF)
1445 mac_mode |= MAC_MODE_HALF_DUPLEX;
1447 lcl_adv = tg3_advert_flowctrl_1000T(
1448 tp->link_config.flowctrl);
1451 rmt_adv = LPA_PAUSE_CAP;
1452 if (phydev->asym_pause)
1453 rmt_adv |= LPA_PAUSE_ASYM;
1456 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1458 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1460 if (mac_mode != tp->mac_mode) {
1461 tp->mac_mode = mac_mode;
1462 tw32_f(MAC_MODE, tp->mac_mode);
1466 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1467 if (phydev->speed == SPEED_10)
1469 MAC_MI_STAT_10MBPS_MODE |
1470 MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1472 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1475 if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1476 tw32(MAC_TX_LENGTHS,
1477 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1478 (6 << TX_LENGTHS_IPG_SHIFT) |
1479 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1481 tw32(MAC_TX_LENGTHS,
1482 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1483 (6 << TX_LENGTHS_IPG_SHIFT) |
1484 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1486 if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1487 (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1488 phydev->speed != tp->link_config.active_speed ||
1489 phydev->duplex != tp->link_config.active_duplex ||
1490 oldflowctrl != tp->link_config.active_flowctrl)
1493 tp->link_config.active_speed = phydev->speed;
1494 tp->link_config.active_duplex = phydev->duplex;
1496 spin_unlock_bh(&tp->lock);
1499 tg3_link_report(tp);
1502 static int tg3_phy_init(struct tg3 *tp)
1504 struct phy_device *phydev;
1506 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)
1509 /* Bring the PHY back to a known state. */
1512 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1514 /* Attach the MAC to the PHY. */
1515 phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
1516 phydev->dev_flags, phydev->interface);
1517 if (IS_ERR(phydev)) {
1518 dev_err(&tp->pdev->dev, "Could not attach to PHY\n");
1519 return PTR_ERR(phydev);
1522 /* Mask with MAC supported features. */
1523 switch (phydev->interface) {
1524 case PHY_INTERFACE_MODE_GMII:
1525 case PHY_INTERFACE_MODE_RGMII:
1526 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
1527 phydev->supported &= (PHY_GBIT_FEATURES |
1529 SUPPORTED_Asym_Pause);
1533 case PHY_INTERFACE_MODE_MII:
1534 phydev->supported &= (PHY_BASIC_FEATURES |
1536 SUPPORTED_Asym_Pause);
1539 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1543 tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED;
1545 phydev->advertising = phydev->supported;
1550 static void tg3_phy_start(struct tg3 *tp)
1552 struct phy_device *phydev;
1554 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
1557 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1559 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
1560 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
1561 phydev->speed = tp->link_config.orig_speed;
1562 phydev->duplex = tp->link_config.orig_duplex;
1563 phydev->autoneg = tp->link_config.orig_autoneg;
1564 phydev->advertising = tp->link_config.orig_advertising;
1569 phy_start_aneg(phydev);
1572 static void tg3_phy_stop(struct tg3 *tp)
1574 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
1577 phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1580 static void tg3_phy_fini(struct tg3 *tp)
1582 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
1583 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1584 tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED;
1588 static int tg3_phydsp_read(struct tg3 *tp, u32 reg, u32 *val)
1592 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1594 err = tg3_readphy(tp, MII_TG3_DSP_RW_PORT, val);
1599 static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1603 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1605 err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1610 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1614 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1617 tg3_writephy(tp, MII_TG3_FET_TEST,
1618 phytest | MII_TG3_FET_SHADOW_EN);
1619 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1621 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1623 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1624 tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1626 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1630 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1634 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1635 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
1636 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) &&
1637 (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
1640 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
1641 tg3_phy_fet_toggle_apd(tp, enable);
1645 reg = MII_TG3_MISC_SHDW_WREN |
1646 MII_TG3_MISC_SHDW_SCR5_SEL |
1647 MII_TG3_MISC_SHDW_SCR5_LPED |
1648 MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1649 MII_TG3_MISC_SHDW_SCR5_SDTL |
1650 MII_TG3_MISC_SHDW_SCR5_C125OE;
1651 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1652 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1654 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1657 reg = MII_TG3_MISC_SHDW_WREN |
1658 MII_TG3_MISC_SHDW_APD_SEL |
1659 MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1661 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1663 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1666 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1670 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1671 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
1674 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
1677 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1678 u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1680 tg3_writephy(tp, MII_TG3_FET_TEST,
1681 ephy | MII_TG3_FET_SHADOW_EN);
1682 if (!tg3_readphy(tp, reg, &phy)) {
1684 phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1686 phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1687 tg3_writephy(tp, reg, phy);
1689 tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
1692 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1693 MII_TG3_AUXCTL_SHDWSEL_MISC;
1694 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1695 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1697 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1699 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1700 phy |= MII_TG3_AUXCTL_MISC_WREN;
1701 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1706 static void tg3_phy_set_wirespeed(struct tg3 *tp)
1710 if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED)
1713 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1714 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1715 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1716 (val | (1 << 15) | (1 << 4)));
1719 static void tg3_phy_apply_otp(struct tg3 *tp)
1728 /* Enable SM_DSP clock and tx 6dB coding. */
1729 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1730 MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1731 MII_TG3_AUXCTL_ACTL_TX_6DB;
1732 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1734 phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1735 phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1736 tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1738 phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1739 ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1740 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1742 phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1743 phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1744 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1746 phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1747 tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1749 phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1750 tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1752 phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1753 ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1754 tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1756 /* Turn off SM_DSP clock. */
1757 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1758 MII_TG3_AUXCTL_ACTL_TX_6DB;
1759 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1762 static void tg3_phy_eee_adjust(struct tg3 *tp, u32 current_link_up)
1766 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
1771 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
1772 current_link_up == 1 &&
1773 tp->link_config.active_duplex == DUPLEX_FULL &&
1774 (tp->link_config.active_speed == SPEED_100 ||
1775 tp->link_config.active_speed == SPEED_1000)) {
1778 if (tp->link_config.active_speed == SPEED_1000)
1779 eeectl = TG3_CPMU_EEE_CTRL_EXIT_16_5_US;
1781 eeectl = TG3_CPMU_EEE_CTRL_EXIT_36_US;
1783 tw32(TG3_CPMU_EEE_CTRL, eeectl);
1785 tg3_phy_cl45_read(tp, MDIO_MMD_AN,
1786 TG3_CL45_D7_EEERES_STAT, &val);
1788 if (val == TG3_CL45_D7_EEERES_STAT_LP_1000T ||
1789 val == TG3_CL45_D7_EEERES_STAT_LP_100TX)
1793 if (!tp->setlpicnt) {
1794 val = tr32(TG3_CPMU_EEE_MODE);
1795 tw32(TG3_CPMU_EEE_MODE, val & ~TG3_CPMU_EEEMD_LPI_ENABLE);
1799 static int tg3_wait_macro_done(struct tg3 *tp)
1806 if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) {
1807 if ((tmp32 & 0x1000) == 0)
1817 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1819 static const u32 test_pat[4][6] = {
1820 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1821 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1822 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1823 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1827 for (chan = 0; chan < 4; chan++) {
1830 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1831 (chan * 0x2000) | 0x0200);
1832 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
1834 for (i = 0; i < 6; i++)
1835 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1838 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
1839 if (tg3_wait_macro_done(tp)) {
1844 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1845 (chan * 0x2000) | 0x0200);
1846 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082);
1847 if (tg3_wait_macro_done(tp)) {
1852 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802);
1853 if (tg3_wait_macro_done(tp)) {
1858 for (i = 0; i < 6; i += 2) {
1861 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1862 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1863 tg3_wait_macro_done(tp)) {
1869 if (low != test_pat[chan][i] ||
1870 high != test_pat[chan][i+1]) {
1871 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1872 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1873 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1883 static int tg3_phy_reset_chanpat(struct tg3 *tp)
1887 for (chan = 0; chan < 4; chan++) {
1890 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1891 (chan * 0x2000) | 0x0200);
1892 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
1893 for (i = 0; i < 6; i++)
1894 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1895 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
1896 if (tg3_wait_macro_done(tp))
1903 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1905 u32 reg32, phy9_orig;
1906 int retries, do_phy_reset, err;
1912 err = tg3_bmcr_reset(tp);
1918 /* Disable transmitter and interrupt. */
1919 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32))
1923 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1925 /* Set full-duplex, 1000 mbps. */
1926 tg3_writephy(tp, MII_BMCR,
1927 BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1929 /* Set to master mode. */
1930 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1933 tg3_writephy(tp, MII_TG3_CTRL,
1934 (MII_TG3_CTRL_AS_MASTER |
1935 MII_TG3_CTRL_ENABLE_AS_MASTER));
1937 /* Enable SM_DSP_CLOCK and 6dB. */
1938 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1940 /* Block the PHY control access. */
1941 tg3_phydsp_write(tp, 0x8005, 0x0800);
1943 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1946 } while (--retries);
1948 err = tg3_phy_reset_chanpat(tp);
1952 tg3_phydsp_write(tp, 0x8005, 0x0000);
1954 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1955 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000);
1957 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1958 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1959 /* Set Extended packet length bit for jumbo frames */
1960 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1962 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1965 tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1967 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32)) {
1969 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1976 /* This will reset the tigon3 PHY if there is no valid
1977 * link unless the FORCE argument is non-zero.
1979 static int tg3_phy_reset(struct tg3 *tp)
1984 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1985 val = tr32(GRC_MISC_CFG);
1986 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1989 err = tg3_readphy(tp, MII_BMSR, &val);
1990 err |= tg3_readphy(tp, MII_BMSR, &val);
1994 if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1995 netif_carrier_off(tp->dev);
1996 tg3_link_report(tp);
1999 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2000 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2001 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
2002 err = tg3_phy_reset_5703_4_5(tp);
2009 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
2010 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
2011 cpmuctrl = tr32(TG3_CPMU_CTRL);
2012 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
2014 cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
2017 err = tg3_bmcr_reset(tp);
2021 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
2022 val = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
2023 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, val);
2025 tw32(TG3_CPMU_CTRL, cpmuctrl);
2028 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2029 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2030 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2031 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
2032 CPMU_LSPD_1000MB_MACCLK_12_5) {
2033 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2035 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2039 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2040 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) &&
2041 (tp->phy_flags & TG3_PHYFLG_MII_SERDES))
2044 tg3_phy_apply_otp(tp);
2046 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
2047 tg3_phy_toggle_apd(tp, true);
2049 tg3_phy_toggle_apd(tp, false);
2052 if (tp->phy_flags & TG3_PHYFLG_ADC_BUG) {
2053 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2054 tg3_phydsp_write(tp, 0x201f, 0x2aaa);
2055 tg3_phydsp_write(tp, 0x000a, 0x0323);
2056 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2058 if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) {
2059 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2060 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2062 if (tp->phy_flags & TG3_PHYFLG_BER_BUG) {
2063 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2064 tg3_phydsp_write(tp, 0x000a, 0x310b);
2065 tg3_phydsp_write(tp, 0x201f, 0x9506);
2066 tg3_phydsp_write(tp, 0x401f, 0x14e2);
2067 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2068 } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) {
2069 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2070 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
2071 if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) {
2072 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
2073 tg3_writephy(tp, MII_TG3_TEST1,
2074 MII_TG3_TEST1_TRIM_EN | 0x4);
2076 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
2077 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2079 /* Set Extended packet length bit (bit 14) on all chips that */
2080 /* support jumbo frames */
2081 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
2082 /* Cannot do read-modify-write on 5401 */
2083 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2084 } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2085 /* Set bit 14 with read-modify-write to preserve other bits */
2086 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
2087 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
2088 tg3_writephy(tp, MII_TG3_AUX_CTRL, val | 0x4000);
2091 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
2092 * jumbo frames transmission.
2094 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2095 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &val))
2096 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2097 val | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
2100 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2101 /* adjust output voltage */
2102 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
2105 tg3_phy_toggle_automdix(tp, 1);
2106 tg3_phy_set_wirespeed(tp);
2110 static void tg3_frob_aux_power(struct tg3 *tp)
2112 struct tg3 *tp_peer = tp;
2114 /* The GPIOs do something completely different on 57765. */
2115 if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0 ||
2116 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
2117 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
2120 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2121 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
2122 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
2123 struct net_device *dev_peer;
2125 dev_peer = pci_get_drvdata(tp->pdev_peer);
2126 /* remove_one() may have been run on the peer. */
2130 tp_peer = netdev_priv(dev_peer);
2133 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2134 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
2135 (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2136 (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
2137 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2138 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2139 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2140 (GRC_LCLCTRL_GPIO_OE0 |
2141 GRC_LCLCTRL_GPIO_OE1 |
2142 GRC_LCLCTRL_GPIO_OE2 |
2143 GRC_LCLCTRL_GPIO_OUTPUT0 |
2144 GRC_LCLCTRL_GPIO_OUTPUT1),
2146 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2147 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2148 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2149 u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2150 GRC_LCLCTRL_GPIO_OE1 |
2151 GRC_LCLCTRL_GPIO_OE2 |
2152 GRC_LCLCTRL_GPIO_OUTPUT0 |
2153 GRC_LCLCTRL_GPIO_OUTPUT1 |
2155 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2157 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2158 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2160 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2161 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2164 u32 grc_local_ctrl = 0;
2166 if (tp_peer != tp &&
2167 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2170 /* Workaround to prevent overdrawing Amps. */
2171 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2173 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2174 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2175 grc_local_ctrl, 100);
2178 /* On 5753 and variants, GPIO2 cannot be used. */
2179 no_gpio2 = tp->nic_sram_data_cfg &
2180 NIC_SRAM_DATA_CFG_NO_GPIO2;
2182 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2183 GRC_LCLCTRL_GPIO_OE1 |
2184 GRC_LCLCTRL_GPIO_OE2 |
2185 GRC_LCLCTRL_GPIO_OUTPUT1 |
2186 GRC_LCLCTRL_GPIO_OUTPUT2;
2188 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2189 GRC_LCLCTRL_GPIO_OUTPUT2);
2191 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2192 grc_local_ctrl, 100);
2194 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2196 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2197 grc_local_ctrl, 100);
2200 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2201 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2202 grc_local_ctrl, 100);
2206 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2207 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2208 if (tp_peer != tp &&
2209 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2212 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2213 (GRC_LCLCTRL_GPIO_OE1 |
2214 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2216 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2217 GRC_LCLCTRL_GPIO_OE1, 100);
2219 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2220 (GRC_LCLCTRL_GPIO_OE1 |
2221 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2226 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2228 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2230 else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {
2231 if (speed != SPEED_10)
2233 } else if (speed == SPEED_10)
2239 static int tg3_setup_phy(struct tg3 *, int);
2241 #define RESET_KIND_SHUTDOWN 0
2242 #define RESET_KIND_INIT 1
2243 #define RESET_KIND_SUSPEND 2
2245 static void tg3_write_sig_post_reset(struct tg3 *, int);
2246 static int tg3_halt_cpu(struct tg3 *, u32);
2248 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2252 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
2253 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2254 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2255 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2258 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2259 tw32(SG_DIG_CTRL, sg_dig_ctrl);
2260 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2265 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2267 val = tr32(GRC_MISC_CFG);
2268 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2271 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2273 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2276 tg3_writephy(tp, MII_ADVERTISE, 0);
2277 tg3_writephy(tp, MII_BMCR,
2278 BMCR_ANENABLE | BMCR_ANRESTART);
2280 tg3_writephy(tp, MII_TG3_FET_TEST,
2281 phytest | MII_TG3_FET_SHADOW_EN);
2282 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
2283 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
2285 MII_TG3_FET_SHDW_AUXMODE4,
2288 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2291 } else if (do_low_power) {
2292 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2293 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
2295 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2296 MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2297 MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2298 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2299 MII_TG3_AUXCTL_PCTL_VREG_11V);
2302 /* The PHY should not be powered down on some chips because
2305 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2306 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2307 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2308 (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
2311 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2312 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2313 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2314 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2315 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2316 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2319 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2322 /* tp->lock is held. */
2323 static int tg3_nvram_lock(struct tg3 *tp)
2325 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2328 if (tp->nvram_lock_cnt == 0) {
2329 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2330 for (i = 0; i < 8000; i++) {
2331 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2336 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2340 tp->nvram_lock_cnt++;
2345 /* tp->lock is held. */
2346 static void tg3_nvram_unlock(struct tg3 *tp)
2348 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2349 if (tp->nvram_lock_cnt > 0)
2350 tp->nvram_lock_cnt--;
2351 if (tp->nvram_lock_cnt == 0)
2352 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2356 /* tp->lock is held. */
2357 static void tg3_enable_nvram_access(struct tg3 *tp)
2359 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2360 !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2361 u32 nvaccess = tr32(NVRAM_ACCESS);
2363 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2367 /* tp->lock is held. */
2368 static void tg3_disable_nvram_access(struct tg3 *tp)
2370 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2371 !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2372 u32 nvaccess = tr32(NVRAM_ACCESS);
2374 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2378 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2379 u32 offset, u32 *val)
2384 if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2387 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2388 EEPROM_ADDR_DEVID_MASK |
2390 tw32(GRC_EEPROM_ADDR,
2392 (0 << EEPROM_ADDR_DEVID_SHIFT) |
2393 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2394 EEPROM_ADDR_ADDR_MASK) |
2395 EEPROM_ADDR_READ | EEPROM_ADDR_START);
2397 for (i = 0; i < 1000; i++) {
2398 tmp = tr32(GRC_EEPROM_ADDR);
2400 if (tmp & EEPROM_ADDR_COMPLETE)
2404 if (!(tmp & EEPROM_ADDR_COMPLETE))
2407 tmp = tr32(GRC_EEPROM_DATA);
2410 * The data will always be opposite the native endian
2411 * format. Perform a blind byteswap to compensate.
2418 #define NVRAM_CMD_TIMEOUT 10000
2420 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2424 tw32(NVRAM_CMD, nvram_cmd);
2425 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2427 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2433 if (i == NVRAM_CMD_TIMEOUT)
2439 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2441 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2442 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2443 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2444 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2445 (tp->nvram_jedecnum == JEDEC_ATMEL))
2447 addr = ((addr / tp->nvram_pagesize) <<
2448 ATMEL_AT45DB0X1B_PAGE_POS) +
2449 (addr % tp->nvram_pagesize);
2454 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2456 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2457 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2458 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2459 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2460 (tp->nvram_jedecnum == JEDEC_ATMEL))
2462 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2463 tp->nvram_pagesize) +
2464 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2469 /* NOTE: Data read in from NVRAM is byteswapped according to
2470 * the byteswapping settings for all other register accesses.
2471 * tg3 devices are BE devices, so on a BE machine, the data
2472 * returned will be exactly as it is seen in NVRAM. On a LE
2473 * machine, the 32-bit value will be byteswapped.
2475 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2479 if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2480 return tg3_nvram_read_using_eeprom(tp, offset, val);
2482 offset = tg3_nvram_phys_addr(tp, offset);
2484 if (offset > NVRAM_ADDR_MSK)
2487 ret = tg3_nvram_lock(tp);
2491 tg3_enable_nvram_access(tp);
2493 tw32(NVRAM_ADDR, offset);
2494 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2495 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2498 *val = tr32(NVRAM_RDDATA);
2500 tg3_disable_nvram_access(tp);
2502 tg3_nvram_unlock(tp);
2507 /* Ensures NVRAM data is in bytestream format. */
2508 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
2511 int res = tg3_nvram_read(tp, offset, &v);
2513 *val = cpu_to_be32(v);
2517 /* tp->lock is held. */
2518 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2520 u32 addr_high, addr_low;
2523 addr_high = ((tp->dev->dev_addr[0] << 8) |
2524 tp->dev->dev_addr[1]);
2525 addr_low = ((tp->dev->dev_addr[2] << 24) |
2526 (tp->dev->dev_addr[3] << 16) |
2527 (tp->dev->dev_addr[4] << 8) |
2528 (tp->dev->dev_addr[5] << 0));
2529 for (i = 0; i < 4; i++) {
2530 if (i == 1 && skip_mac_1)
2532 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2533 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2536 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2537 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2538 for (i = 0; i < 12; i++) {
2539 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2540 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2544 addr_high = (tp->dev->dev_addr[0] +
2545 tp->dev->dev_addr[1] +
2546 tp->dev->dev_addr[2] +
2547 tp->dev->dev_addr[3] +
2548 tp->dev->dev_addr[4] +
2549 tp->dev->dev_addr[5]) &
2550 TX_BACKOFF_SEED_MASK;
2551 tw32(MAC_TX_BACKOFF_SEED, addr_high);
2554 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
2557 bool device_should_wake, do_low_power;
2559 /* Make sure register accesses (indirect or otherwise)
2560 * will function correctly.
2562 pci_write_config_dword(tp->pdev,
2563 TG3PCI_MISC_HOST_CTRL,
2564 tp->misc_host_ctrl);
2568 pci_enable_wake(tp->pdev, state, false);
2569 pci_set_power_state(tp->pdev, PCI_D0);
2571 /* Switch out of Vaux if it is a NIC */
2572 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
2573 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
2583 netdev_err(tp->dev, "Invalid power state (D%d) requested\n",
2588 /* Restore the CLKREQ setting. */
2589 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2592 pci_read_config_word(tp->pdev,
2593 tp->pcie_cap + PCI_EXP_LNKCTL,
2595 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2596 pci_write_config_word(tp->pdev,
2597 tp->pcie_cap + PCI_EXP_LNKCTL,
2601 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2602 tw32(TG3PCI_MISC_HOST_CTRL,
2603 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2605 device_should_wake = pci_pme_capable(tp->pdev, state) &&
2606 device_may_wakeup(&tp->pdev->dev) &&
2607 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2609 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
2610 do_low_power = false;
2611 if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) &&
2612 !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
2613 struct phy_device *phydev;
2614 u32 phyid, advertising;
2616 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
2618 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
2620 tp->link_config.orig_speed = phydev->speed;
2621 tp->link_config.orig_duplex = phydev->duplex;
2622 tp->link_config.orig_autoneg = phydev->autoneg;
2623 tp->link_config.orig_advertising = phydev->advertising;
2625 advertising = ADVERTISED_TP |
2627 ADVERTISED_Autoneg |
2628 ADVERTISED_10baseT_Half;
2630 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2631 device_should_wake) {
2632 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2634 ADVERTISED_100baseT_Half |
2635 ADVERTISED_100baseT_Full |
2636 ADVERTISED_10baseT_Full;
2638 advertising |= ADVERTISED_10baseT_Full;
2641 phydev->advertising = advertising;
2643 phy_start_aneg(phydev);
2645 phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2646 if (phyid != PHY_ID_BCMAC131) {
2647 phyid &= PHY_BCM_OUI_MASK;
2648 if (phyid == PHY_BCM_OUI_1 ||
2649 phyid == PHY_BCM_OUI_2 ||
2650 phyid == PHY_BCM_OUI_3)
2651 do_low_power = true;
2655 do_low_power = true;
2657 if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
2658 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
2659 tp->link_config.orig_speed = tp->link_config.speed;
2660 tp->link_config.orig_duplex = tp->link_config.duplex;
2661 tp->link_config.orig_autoneg = tp->link_config.autoneg;
2664 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
2665 tp->link_config.speed = SPEED_10;
2666 tp->link_config.duplex = DUPLEX_HALF;
2667 tp->link_config.autoneg = AUTONEG_ENABLE;
2668 tg3_setup_phy(tp, 0);
2672 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2675 val = tr32(GRC_VCPU_EXT_CTRL);
2676 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2677 } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2681 for (i = 0; i < 200; i++) {
2682 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2683 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2688 if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2689 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2690 WOL_DRV_STATE_SHUTDOWN |
2694 if (device_should_wake) {
2697 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
2699 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2703 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
2704 mac_mode = MAC_MODE_PORT_MODE_GMII;
2706 mac_mode = MAC_MODE_PORT_MODE_MII;
2708 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2709 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2711 u32 speed = (tp->tg3_flags &
2712 TG3_FLAG_WOL_SPEED_100MB) ?
2713 SPEED_100 : SPEED_10;
2714 if (tg3_5700_link_polarity(tp, speed))
2715 mac_mode |= MAC_MODE_LINK_POLARITY;
2717 mac_mode &= ~MAC_MODE_LINK_POLARITY;
2720 mac_mode = MAC_MODE_PORT_MODE_TBI;
2723 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
2724 tw32(MAC_LED_CTRL, tp->led_ctrl);
2726 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2727 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2728 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2729 ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2730 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2731 mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
2733 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
2734 mac_mode |= MAC_MODE_APE_TX_EN |
2735 MAC_MODE_APE_RX_EN |
2736 MAC_MODE_TDE_ENABLE;
2738 tw32_f(MAC_MODE, mac_mode);
2741 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2745 if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2746 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2747 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2750 base_val = tp->pci_clock_ctrl;
2751 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2752 CLOCK_CTRL_TXCLK_DISABLE);
2754 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2755 CLOCK_CTRL_PWRDOWN_PLL133, 40);
2756 } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
2757 (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
2758 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
2760 } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2761 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2762 u32 newbits1, newbits2;
2764 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2765 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2766 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2767 CLOCK_CTRL_TXCLK_DISABLE |
2769 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2770 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2771 newbits1 = CLOCK_CTRL_625_CORE;
2772 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2774 newbits1 = CLOCK_CTRL_ALTCLK;
2775 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2778 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2781 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2784 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2787 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2788 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2789 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2790 CLOCK_CTRL_TXCLK_DISABLE |
2791 CLOCK_CTRL_44MHZ_CORE);
2793 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2796 tw32_wait_f(TG3PCI_CLOCK_CTRL,
2797 tp->pci_clock_ctrl | newbits3, 40);
2801 if (!(device_should_wake) &&
2802 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
2803 tg3_power_down_phy(tp, do_low_power);
2805 tg3_frob_aux_power(tp);
2807 /* Workaround for unstable PLL clock */
2808 if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2809 (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2810 u32 val = tr32(0x7d00);
2812 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2814 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2817 err = tg3_nvram_lock(tp);
2818 tg3_halt_cpu(tp, RX_CPU_BASE);
2820 tg3_nvram_unlock(tp);
2824 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2826 if (device_should_wake)
2827 pci_enable_wake(tp->pdev, state, true);
2829 /* Finally, set the new power state. */
2830 pci_set_power_state(tp->pdev, state);
2835 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2837 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2838 case MII_TG3_AUX_STAT_10HALF:
2840 *duplex = DUPLEX_HALF;
2843 case MII_TG3_AUX_STAT_10FULL:
2845 *duplex = DUPLEX_FULL;
2848 case MII_TG3_AUX_STAT_100HALF:
2850 *duplex = DUPLEX_HALF;
2853 case MII_TG3_AUX_STAT_100FULL:
2855 *duplex = DUPLEX_FULL;
2858 case MII_TG3_AUX_STAT_1000HALF:
2859 *speed = SPEED_1000;
2860 *duplex = DUPLEX_HALF;
2863 case MII_TG3_AUX_STAT_1000FULL:
2864 *speed = SPEED_1000;
2865 *duplex = DUPLEX_FULL;
2869 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2870 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2872 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2876 *speed = SPEED_INVALID;
2877 *duplex = DUPLEX_INVALID;
2882 static void tg3_phy_copper_begin(struct tg3 *tp)
2887 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
2888 /* Entering low power mode. Disable gigabit and
2889 * 100baseT advertisements.
2891 tg3_writephy(tp, MII_TG3_CTRL, 0);
2893 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2894 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2895 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2896 new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2898 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2899 } else if (tp->link_config.speed == SPEED_INVALID) {
2900 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
2901 tp->link_config.advertising &=
2902 ~(ADVERTISED_1000baseT_Half |
2903 ADVERTISED_1000baseT_Full);
2905 new_adv = ADVERTISE_CSMA;
2906 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2907 new_adv |= ADVERTISE_10HALF;
2908 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2909 new_adv |= ADVERTISE_10FULL;
2910 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2911 new_adv |= ADVERTISE_100HALF;
2912 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2913 new_adv |= ADVERTISE_100FULL;
2915 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2917 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2919 if (tp->link_config.advertising &
2920 (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2922 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2923 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2924 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2925 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2926 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY) &&
2927 (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2928 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2929 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2930 MII_TG3_CTRL_ENABLE_AS_MASTER);
2931 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2933 tg3_writephy(tp, MII_TG3_CTRL, 0);
2936 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2937 new_adv |= ADVERTISE_CSMA;
2939 /* Asking for a specific link mode. */
2940 if (tp->link_config.speed == SPEED_1000) {
2941 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2943 if (tp->link_config.duplex == DUPLEX_FULL)
2944 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2946 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2947 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2948 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2949 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2950 MII_TG3_CTRL_ENABLE_AS_MASTER);
2952 if (tp->link_config.speed == SPEED_100) {
2953 if (tp->link_config.duplex == DUPLEX_FULL)
2954 new_adv |= ADVERTISE_100FULL;
2956 new_adv |= ADVERTISE_100HALF;
2958 if (tp->link_config.duplex == DUPLEX_FULL)
2959 new_adv |= ADVERTISE_10FULL;
2961 new_adv |= ADVERTISE_10HALF;
2963 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2968 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2971 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) {
2974 tw32(TG3_CPMU_EEE_MODE,
2975 tr32(TG3_CPMU_EEE_MODE) & ~TG3_CPMU_EEEMD_LPI_ENABLE);
2977 /* Enable SM_DSP clock and tx 6dB coding. */
2978 val = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
2979 MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
2980 MII_TG3_AUXCTL_ACTL_TX_6DB;
2981 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
2983 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2984 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) &&
2985 !tg3_phydsp_read(tp, MII_TG3_DSP_CH34TP2, &val))
2986 tg3_phydsp_write(tp, MII_TG3_DSP_CH34TP2,
2987 val | MII_TG3_DSP_CH34TP2_HIBW01);
2990 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2991 /* Advertise 100-BaseTX EEE ability */
2992 if (tp->link_config.advertising &
2993 ADVERTISED_100baseT_Full)
2994 val |= MDIO_AN_EEE_ADV_100TX;
2995 /* Advertise 1000-BaseT EEE ability */
2996 if (tp->link_config.advertising &
2997 ADVERTISED_1000baseT_Full)
2998 val |= MDIO_AN_EEE_ADV_1000T;
3000 tg3_phy_cl45_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
3002 /* Turn off SM_DSP clock. */
3003 val = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
3004 MII_TG3_AUXCTL_ACTL_TX_6DB;
3005 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3008 if (tp->link_config.autoneg == AUTONEG_DISABLE &&
3009 tp->link_config.speed != SPEED_INVALID) {
3010 u32 bmcr, orig_bmcr;
3012 tp->link_config.active_speed = tp->link_config.speed;
3013 tp->link_config.active_duplex = tp->link_config.duplex;
3016 switch (tp->link_config.speed) {
3022 bmcr |= BMCR_SPEED100;
3026 bmcr |= TG3_BMCR_SPEED1000;
3030 if (tp->link_config.duplex == DUPLEX_FULL)
3031 bmcr |= BMCR_FULLDPLX;
3033 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
3034 (bmcr != orig_bmcr)) {
3035 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
3036 for (i = 0; i < 1500; i++) {
3040 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
3041 tg3_readphy(tp, MII_BMSR, &tmp))
3043 if (!(tmp & BMSR_LSTATUS)) {
3048 tg3_writephy(tp, MII_BMCR, bmcr);
3052 tg3_writephy(tp, MII_BMCR,
3053 BMCR_ANENABLE | BMCR_ANRESTART);
3057 static int tg3_init_5401phy_dsp(struct tg3 *tp)
3061 /* Turn off tap power management. */
3062 /* Set Extended packet length bit */
3063 err = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
3065 err |= tg3_phydsp_write(tp, 0x0012, 0x1804);
3066 err |= tg3_phydsp_write(tp, 0x0013, 0x1204);
3067 err |= tg3_phydsp_write(tp, 0x8006, 0x0132);
3068 err |= tg3_phydsp_write(tp, 0x8006, 0x0232);
3069 err |= tg3_phydsp_write(tp, 0x201f, 0x0a20);
3076 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
3078 u32 adv_reg, all_mask = 0;
3080 if (mask & ADVERTISED_10baseT_Half)
3081 all_mask |= ADVERTISE_10HALF;
3082 if (mask & ADVERTISED_10baseT_Full)
3083 all_mask |= ADVERTISE_10FULL;
3084 if (mask & ADVERTISED_100baseT_Half)
3085 all_mask |= ADVERTISE_100HALF;
3086 if (mask & ADVERTISED_100baseT_Full)
3087 all_mask |= ADVERTISE_100FULL;
3089 if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
3092 if ((adv_reg & all_mask) != all_mask)
3094 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
3098 if (mask & ADVERTISED_1000baseT_Half)
3099 all_mask |= ADVERTISE_1000HALF;
3100 if (mask & ADVERTISED_1000baseT_Full)
3101 all_mask |= ADVERTISE_1000FULL;
3103 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
3106 if ((tg3_ctrl & all_mask) != all_mask)
3112 static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
3116 if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
3119 curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3120 reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
3122 if (tp->link_config.active_duplex == DUPLEX_FULL) {
3123 if (curadv != reqadv)
3126 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
3127 tg3_readphy(tp, MII_LPA, rmtadv);
3129 /* Reprogram the advertisement register, even if it
3130 * does not affect the current link. If the link
3131 * gets renegotiated in the future, we can save an
3132 * additional renegotiation cycle by advertising
3133 * it correctly in the first place.
3135 if (curadv != reqadv) {
3136 *lcladv &= ~(ADVERTISE_PAUSE_CAP |
3137 ADVERTISE_PAUSE_ASYM);
3138 tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
3145 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
3147 int current_link_up;
3149 u32 lcl_adv, rmt_adv;
3157 (MAC_STATUS_SYNC_CHANGED |
3158 MAC_STATUS_CFG_CHANGED |
3159 MAC_STATUS_MI_COMPLETION |
3160 MAC_STATUS_LNKSTATE_CHANGED));
3163 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
3165 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
3169 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
3171 /* Some third-party PHYs need to be reset on link going
3174 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3175 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
3176 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
3177 netif_carrier_ok(tp->dev)) {
3178 tg3_readphy(tp, MII_BMSR, &bmsr);
3179 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3180 !(bmsr & BMSR_LSTATUS))
3186 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
3187 tg3_readphy(tp, MII_BMSR, &bmsr);
3188 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
3189 !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
3192 if (!(bmsr & BMSR_LSTATUS)) {
3193 err = tg3_init_5401phy_dsp(tp);
3197 tg3_readphy(tp, MII_BMSR, &bmsr);
3198 for (i = 0; i < 1000; i++) {
3200 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3201 (bmsr & BMSR_LSTATUS)) {
3207 if ((tp->phy_id & TG3_PHY_ID_REV_MASK) ==
3208 TG3_PHY_REV_BCM5401_B0 &&
3209 !(bmsr & BMSR_LSTATUS) &&
3210 tp->link_config.active_speed == SPEED_1000) {
3211 err = tg3_phy_reset(tp);
3213 err = tg3_init_5401phy_dsp(tp);
3218 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3219 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3220 /* 5701 {A0,B0} CRC bug workaround */
3221 tg3_writephy(tp, 0x15, 0x0a75);
3222 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
3223 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
3224 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
3227 /* Clear pending interrupts... */
3228 tg3_readphy(tp, MII_TG3_ISTAT, &val);
3229 tg3_readphy(tp, MII_TG3_ISTAT, &val);
3231 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT)
3232 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
3233 else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET))
3234 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3236 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3237 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3238 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3239 tg3_writephy(tp, MII_TG3_EXT_CTRL,
3240 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3242 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3245 current_link_up = 0;
3246 current_speed = SPEED_INVALID;
3247 current_duplex = DUPLEX_INVALID;
3249 if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) {
3250 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3251 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3252 if (!(val & (1 << 10))) {
3254 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3260 for (i = 0; i < 100; i++) {
3261 tg3_readphy(tp, MII_BMSR, &bmsr);
3262 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3263 (bmsr & BMSR_LSTATUS))
3268 if (bmsr & BMSR_LSTATUS) {
3271 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3272 for (i = 0; i < 2000; i++) {
3274 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3279 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3284 for (i = 0; i < 200; i++) {
3285 tg3_readphy(tp, MII_BMCR, &bmcr);
3286 if (tg3_readphy(tp, MII_BMCR, &bmcr))
3288 if (bmcr && bmcr != 0x7fff)
3296 tp->link_config.active_speed = current_speed;
3297 tp->link_config.active_duplex = current_duplex;
3299 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3300 if ((bmcr & BMCR_ANENABLE) &&
3301 tg3_copper_is_advertising_all(tp,
3302 tp->link_config.advertising)) {
3303 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3305 current_link_up = 1;
3308 if (!(bmcr & BMCR_ANENABLE) &&
3309 tp->link_config.speed == current_speed &&
3310 tp->link_config.duplex == current_duplex &&
3311 tp->link_config.flowctrl ==
3312 tp->link_config.active_flowctrl) {
3313 current_link_up = 1;
3317 if (current_link_up == 1 &&
3318 tp->link_config.active_duplex == DUPLEX_FULL)
3319 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
3323 if (current_link_up == 0 || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
3324 tg3_phy_copper_begin(tp);
3326 tg3_readphy(tp, MII_BMSR, &bmsr);
3327 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3328 (bmsr & BMSR_LSTATUS))
3329 current_link_up = 1;
3332 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3333 if (current_link_up == 1) {
3334 if (tp->link_config.active_speed == SPEED_100 ||
3335 tp->link_config.active_speed == SPEED_10)
3336 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3338 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3339 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET)
3340 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3342 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3344 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3345 if (tp->link_config.active_duplex == DUPLEX_HALF)
3346 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3348 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
3349 if (current_link_up == 1 &&
3350 tg3_5700_link_polarity(tp, tp->link_config.active_speed))
3351 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
3353 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
3356 /* ??? Without this setting Netgear GA302T PHY does not
3357 * ??? send/receive packets...
3359 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 &&
3360 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3361 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3362 tw32_f(MAC_MI_MODE, tp->mi_mode);
3366 tw32_f(MAC_MODE, tp->mac_mode);
3369 tg3_phy_eee_adjust(tp, current_link_up);
3371 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3372 /* Polled via timer. */
3373 tw32_f(MAC_EVENT, 0);
3375 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3379 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3380 current_link_up == 1 &&
3381 tp->link_config.active_speed == SPEED_1000 &&
3382 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3383 (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3386 (MAC_STATUS_SYNC_CHANGED |
3387 MAC_STATUS_CFG_CHANGED));
3390 NIC_SRAM_FIRMWARE_MBOX,
3391 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3394 /* Prevent send BD corruption. */
3395 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3396 u16 oldlnkctl, newlnkctl;
3398 pci_read_config_word(tp->pdev,
3399 tp->pcie_cap + PCI_EXP_LNKCTL,
3401 if (tp->link_config.active_speed == SPEED_100 ||
3402 tp->link_config.active_speed == SPEED_10)
3403 newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3405 newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3406 if (newlnkctl != oldlnkctl)
3407 pci_write_config_word(tp->pdev,
3408 tp->pcie_cap + PCI_EXP_LNKCTL,
3412 if (current_link_up != netif_carrier_ok(tp->dev)) {
3413 if (current_link_up)
3414 netif_carrier_on(tp->dev);
3416 netif_carrier_off(tp->dev);
3417 tg3_link_report(tp);
3423 struct tg3_fiber_aneginfo {
3425 #define ANEG_STATE_UNKNOWN 0
3426 #define ANEG_STATE_AN_ENABLE 1
3427 #define ANEG_STATE_RESTART_INIT 2
3428 #define ANEG_STATE_RESTART 3
3429 #define ANEG_STATE_DISABLE_LINK_OK 4
3430 #define ANEG_STATE_ABILITY_DETECT_INIT 5
3431 #define ANEG_STATE_ABILITY_DETECT 6
3432 #define ANEG_STATE_ACK_DETECT_INIT 7
3433 #define ANEG_STATE_ACK_DETECT 8
3434 #define ANEG_STATE_COMPLETE_ACK_INIT 9
3435 #define ANEG_STATE_COMPLETE_ACK 10
3436 #define ANEG_STATE_IDLE_DETECT_INIT 11
3437 #define ANEG_STATE_IDLE_DETECT 12
3438 #define ANEG_STATE_LINK_OK 13
3439 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
3440 #define ANEG_STATE_NEXT_PAGE_WAIT 15
3443 #define MR_AN_ENABLE 0x00000001
3444 #define MR_RESTART_AN 0x00000002
3445 #define MR_AN_COMPLETE 0x00000004
3446 #define MR_PAGE_RX 0x00000008
3447 #define MR_NP_LOADED 0x00000010
3448 #define MR_TOGGLE_TX 0x00000020
3449 #define MR_LP_ADV_FULL_DUPLEX 0x00000040
3450 #define MR_LP_ADV_HALF_DUPLEX 0x00000080
3451 #define MR_LP_ADV_SYM_PAUSE 0x00000100
3452 #define MR_LP_ADV_ASYM_PAUSE 0x00000200
3453 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3454 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3455 #define MR_LP_ADV_NEXT_PAGE 0x00001000
3456 #define MR_TOGGLE_RX 0x00002000
3457 #define MR_NP_RX 0x00004000
3459 #define MR_LINK_OK 0x80000000
3461 unsigned long link_time, cur_time;
3463 u32 ability_match_cfg;
3464 int ability_match_count;
3466 char ability_match, idle_match, ack_match;
3468 u32 txconfig, rxconfig;
3469 #define ANEG_CFG_NP 0x00000080
3470 #define ANEG_CFG_ACK 0x00000040
3471 #define ANEG_CFG_RF2 0x00000020
3472 #define ANEG_CFG_RF1 0x00000010
3473 #define ANEG_CFG_PS2 0x00000001
3474 #define ANEG_CFG_PS1 0x00008000
3475 #define ANEG_CFG_HD 0x00004000
3476 #define ANEG_CFG_FD 0x00002000
3477 #define ANEG_CFG_INVAL 0x00001f06
3482 #define ANEG_TIMER_ENAB 2
3483 #define ANEG_FAILED -1
3485 #define ANEG_STATE_SETTLE_TIME 10000
3487 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3488 struct tg3_fiber_aneginfo *ap)
3491 unsigned long delta;
3495 if (ap->state == ANEG_STATE_UNKNOWN) {
3499 ap->ability_match_cfg = 0;
3500 ap->ability_match_count = 0;
3501 ap->ability_match = 0;
3507 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3508 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3510 if (rx_cfg_reg != ap->ability_match_cfg) {
3511 ap->ability_match_cfg = rx_cfg_reg;
3512 ap->ability_match = 0;
3513 ap->ability_match_count = 0;
3515 if (++ap->ability_match_count > 1) {
3516 ap->ability_match = 1;
3517 ap->ability_match_cfg = rx_cfg_reg;
3520 if (rx_cfg_reg & ANEG_CFG_ACK)
3528 ap->ability_match_cfg = 0;
3529 ap->ability_match_count = 0;
3530 ap->ability_match = 0;
3536 ap->rxconfig = rx_cfg_reg;
3539 switch (ap->state) {
3540 case ANEG_STATE_UNKNOWN:
3541 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3542 ap->state = ANEG_STATE_AN_ENABLE;
3545 case ANEG_STATE_AN_ENABLE:
3546 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3547 if (ap->flags & MR_AN_ENABLE) {
3550 ap->ability_match_cfg = 0;
3551 ap->ability_match_count = 0;
3552 ap->ability_match = 0;
3556 ap->state = ANEG_STATE_RESTART_INIT;
3558 ap->state = ANEG_STATE_DISABLE_LINK_OK;
3562 case ANEG_STATE_RESTART_INIT:
3563 ap->link_time = ap->cur_time;
3564 ap->flags &= ~(MR_NP_LOADED);
3566 tw32(MAC_TX_AUTO_NEG, 0);
3567 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3568 tw32_f(MAC_MODE, tp->mac_mode);
3571 ret = ANEG_TIMER_ENAB;
3572 ap->state = ANEG_STATE_RESTART;
3575 case ANEG_STATE_RESTART:
3576 delta = ap->cur_time - ap->link_time;
3577 if (delta > ANEG_STATE_SETTLE_TIME)
3578 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3580 ret = ANEG_TIMER_ENAB;
3583 case ANEG_STATE_DISABLE_LINK_OK:
3587 case ANEG_STATE_ABILITY_DETECT_INIT:
3588 ap->flags &= ~(MR_TOGGLE_TX);
3589 ap->txconfig = ANEG_CFG_FD;
3590 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3591 if (flowctrl & ADVERTISE_1000XPAUSE)
3592 ap->txconfig |= ANEG_CFG_PS1;
3593 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3594 ap->txconfig |= ANEG_CFG_PS2;
3595 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3596 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3597 tw32_f(MAC_MODE, tp->mac_mode);
3600 ap->state = ANEG_STATE_ABILITY_DETECT;
3603 case ANEG_STATE_ABILITY_DETECT:
3604 if (ap->ability_match != 0 && ap->rxconfig != 0)
3605 ap->state = ANEG_STATE_ACK_DETECT_INIT;
3608 case ANEG_STATE_ACK_DETECT_INIT:
3609 ap->txconfig |= ANEG_CFG_ACK;
3610 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3611 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3612 tw32_f(MAC_MODE, tp->mac_mode);
3615 ap->state = ANEG_STATE_ACK_DETECT;
3618 case ANEG_STATE_ACK_DETECT:
3619 if (ap->ack_match != 0) {
3620 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3621 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3622 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3624 ap->state = ANEG_STATE_AN_ENABLE;
3626 } else if (ap->ability_match != 0 &&
3627 ap->rxconfig == 0) {
3628 ap->state = ANEG_STATE_AN_ENABLE;
3632 case ANEG_STATE_COMPLETE_ACK_INIT:
3633 if (ap->rxconfig & ANEG_CFG_INVAL) {
3637 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3638 MR_LP_ADV_HALF_DUPLEX |
3639 MR_LP_ADV_SYM_PAUSE |
3640 MR_LP_ADV_ASYM_PAUSE |
3641 MR_LP_ADV_REMOTE_FAULT1 |
3642 MR_LP_ADV_REMOTE_FAULT2 |
3643 MR_LP_ADV_NEXT_PAGE |
3646 if (ap->rxconfig & ANEG_CFG_FD)
3647 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3648 if (ap->rxconfig & ANEG_CFG_HD)
3649 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3650 if (ap->rxconfig & ANEG_CFG_PS1)
3651 ap->flags |= MR_LP_ADV_SYM_PAUSE;
3652 if (ap->rxconfig & ANEG_CFG_PS2)
3653 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3654 if (ap->rxconfig & ANEG_CFG_RF1)
3655 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3656 if (ap->rxconfig & ANEG_CFG_RF2)
3657 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3658 if (ap->rxconfig & ANEG_CFG_NP)
3659 ap->flags |= MR_LP_ADV_NEXT_PAGE;
3661 ap->link_time = ap->cur_time;
3663 ap->flags ^= (MR_TOGGLE_TX);
3664 if (ap->rxconfig & 0x0008)
3665 ap->flags |= MR_TOGGLE_RX;
3666 if (ap->rxconfig & ANEG_CFG_NP)
3667 ap->flags |= MR_NP_RX;
3668 ap->flags |= MR_PAGE_RX;
3670 ap->state = ANEG_STATE_COMPLETE_ACK;
3671 ret = ANEG_TIMER_ENAB;
3674 case ANEG_STATE_COMPLETE_ACK:
3675 if (ap->ability_match != 0 &&
3676 ap->rxconfig == 0) {
3677 ap->state = ANEG_STATE_AN_ENABLE;
3680 delta = ap->cur_time - ap->link_time;
3681 if (delta > ANEG_STATE_SETTLE_TIME) {
3682 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3683 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3685 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3686 !(ap->flags & MR_NP_RX)) {
3687 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3695 case ANEG_STATE_IDLE_DETECT_INIT:
3696 ap->link_time = ap->cur_time;
3697 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3698 tw32_f(MAC_MODE, tp->mac_mode);
3701 ap->state = ANEG_STATE_IDLE_DETECT;
3702 ret = ANEG_TIMER_ENAB;
3705 case ANEG_STATE_IDLE_DETECT:
3706 if (ap->ability_match != 0 &&
3707 ap->rxconfig == 0) {
3708 ap->state = ANEG_STATE_AN_ENABLE;
3711 delta = ap->cur_time - ap->link_time;
3712 if (delta > ANEG_STATE_SETTLE_TIME) {
3713 /* XXX another gem from the Broadcom driver :( */
3714 ap->state = ANEG_STATE_LINK_OK;
3718 case ANEG_STATE_LINK_OK:
3719 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3723 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3724 /* ??? unimplemented */
3727 case ANEG_STATE_NEXT_PAGE_WAIT:
3728 /* ??? unimplemented */
3739 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
3742 struct tg3_fiber_aneginfo aninfo;
3743 int status = ANEG_FAILED;
3747 tw32_f(MAC_TX_AUTO_NEG, 0);
3749 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3750 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3753 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3756 memset(&aninfo, 0, sizeof(aninfo));
3757 aninfo.flags |= MR_AN_ENABLE;
3758 aninfo.state = ANEG_STATE_UNKNOWN;
3759 aninfo.cur_time = 0;
3761 while (++tick < 195000) {
3762 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3763 if (status == ANEG_DONE || status == ANEG_FAILED)
3769 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3770 tw32_f(MAC_MODE, tp->mac_mode);
3773 *txflags = aninfo.txconfig;
3774 *rxflags = aninfo.flags;
3776 if (status == ANEG_DONE &&
3777 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3778 MR_LP_ADV_FULL_DUPLEX)))
3784 static void tg3_init_bcm8002(struct tg3 *tp)
3786 u32 mac_status = tr32(MAC_STATUS);
3789 /* Reset when initting first time or we have a link. */
3790 if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3791 !(mac_status & MAC_STATUS_PCS_SYNCED))
3794 /* Set PLL lock range. */
3795 tg3_writephy(tp, 0x16, 0x8007);
3798 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3800 /* Wait for reset to complete. */
3801 /* XXX schedule_timeout() ... */
3802 for (i = 0; i < 500; i++)
3805 /* Config mode; select PMA/Ch 1 regs. */
3806 tg3_writephy(tp, 0x10, 0x8411);
3808 /* Enable auto-lock and comdet, select txclk for tx. */
3809 tg3_writephy(tp, 0x11, 0x0a10);
3811 tg3_writephy(tp, 0x18, 0x00a0);
3812 tg3_writephy(tp, 0x16, 0x41ff);
3814 /* Assert and deassert POR. */
3815 tg3_writephy(tp, 0x13, 0x0400);
3817 tg3_writephy(tp, 0x13, 0x0000);
3819 tg3_writephy(tp, 0x11, 0x0a50);
3821 tg3_writephy(tp, 0x11, 0x0a10);
3823 /* Wait for signal to stabilize */
3824 /* XXX schedule_timeout() ... */
3825 for (i = 0; i < 15000; i++)
3828 /* Deselect the channel register so we can read the PHYID
3831 tg3_writephy(tp, 0x10, 0x8011);
3834 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3837 u32 sg_dig_ctrl, sg_dig_status;
3838 u32 serdes_cfg, expected_sg_dig_ctrl;
3839 int workaround, port_a;
3840 int current_link_up;
3843 expected_sg_dig_ctrl = 0;
3846 current_link_up = 0;
3848 if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3849 tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3851 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3854 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3855 /* preserve bits 20-23 for voltage regulator */
3856 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3859 sg_dig_ctrl = tr32(SG_DIG_CTRL);
3861 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
3862 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
3864 u32 val = serdes_cfg;
3870 tw32_f(MAC_SERDES_CFG, val);
3873 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3875 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3876 tg3_setup_flow_control(tp, 0, 0);
3877 current_link_up = 1;
3882 /* Want auto-negotiation. */
3883 expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
3885 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3886 if (flowctrl & ADVERTISE_1000XPAUSE)
3887 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3888 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3889 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
3891 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3892 if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) &&
3893 tp->serdes_counter &&
3894 ((mac_status & (MAC_STATUS_PCS_SYNCED |
3895 MAC_STATUS_RCVD_CFG)) ==
3896 MAC_STATUS_PCS_SYNCED)) {
3897 tp->serdes_counter--;
3898 current_link_up = 1;
3903 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
3904 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
3906 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3908 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3909 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
3910 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3911 MAC_STATUS_SIGNAL_DET)) {
3912 sg_dig_status = tr32(SG_DIG_STATUS);
3913 mac_status = tr32(MAC_STATUS);
3915 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
3916 (mac_status & MAC_STATUS_PCS_SYNCED)) {
3917 u32 local_adv = 0, remote_adv = 0;
3919 if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3920 local_adv |= ADVERTISE_1000XPAUSE;
3921 if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3922 local_adv |= ADVERTISE_1000XPSE_ASYM;
3924 if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
3925 remote_adv |= LPA_1000XPAUSE;
3926 if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
3927 remote_adv |= LPA_1000XPAUSE_ASYM;
3929 tg3_setup_flow_control(tp, local_adv, remote_adv);
3930 current_link_up = 1;
3931 tp->serdes_counter = 0;
3932 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
3933 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3934 if (tp->serdes_counter)
3935 tp->serdes_counter--;
3938 u32 val = serdes_cfg;
3945 tw32_f(MAC_SERDES_CFG, val);
3948 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3951 /* Link parallel detection - link is up */
3952 /* only if we have PCS_SYNC and not */
3953 /* receiving config code words */
3954 mac_status = tr32(MAC_STATUS);
3955 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3956 !(mac_status & MAC_STATUS_RCVD_CFG)) {
3957 tg3_setup_flow_control(tp, 0, 0);
3958 current_link_up = 1;
3960 TG3_PHYFLG_PARALLEL_DETECT;
3961 tp->serdes_counter =
3962 SERDES_PARALLEL_DET_TIMEOUT;
3964 goto restart_autoneg;
3968 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3969 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
3973 return current_link_up;
3976 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3978 int current_link_up = 0;
3980 if (!(mac_status & MAC_STATUS_PCS_SYNCED))
3983 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3984 u32 txflags, rxflags;
3987 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3988 u32 local_adv = 0, remote_adv = 0;
3990 if (txflags & ANEG_CFG_PS1)
3991 local_adv |= ADVERTISE_1000XPAUSE;
3992 if (txflags & ANEG_CFG_PS2)
3993 local_adv |= ADVERTISE_1000XPSE_ASYM;
3995 if (rxflags & MR_LP_ADV_SYM_PAUSE)
3996 remote_adv |= LPA_1000XPAUSE;
3997 if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3998 remote_adv |= LPA_1000XPAUSE_ASYM;
4000 tg3_setup_flow_control(tp, local_adv, remote_adv);
4002 current_link_up = 1;
4004 for (i = 0; i < 30; i++) {
4007 (MAC_STATUS_SYNC_CHANGED |
4008 MAC_STATUS_CFG_CHANGED));
4010 if ((tr32(MAC_STATUS) &
4011 (MAC_STATUS_SYNC_CHANGED |
4012 MAC_STATUS_CFG_CHANGED)) == 0)
4016 mac_status = tr32(MAC_STATUS);
4017 if (current_link_up == 0 &&
4018 (mac_status & MAC_STATUS_PCS_SYNCED) &&
4019 !(mac_status & MAC_STATUS_RCVD_CFG))
4020 current_link_up = 1;
4022 tg3_setup_flow_control(tp, 0, 0);
4024 /* Forcing 1000FD link up. */
4025 current_link_up = 1;
4027 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
4030 tw32_f(MAC_MODE, tp->mac_mode);
4035 return current_link_up;
4038 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
4041 u16 orig_active_speed;
4042 u8 orig_active_duplex;
4044 int current_link_up;
4047 orig_pause_cfg = tp->link_config.active_flowctrl;
4048 orig_active_speed = tp->link_config.active_speed;
4049 orig_active_duplex = tp->link_config.active_duplex;
4051 if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
4052 netif_carrier_ok(tp->dev) &&
4053 (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
4054 mac_status = tr32(MAC_STATUS);
4055 mac_status &= (MAC_STATUS_PCS_SYNCED |
4056 MAC_STATUS_SIGNAL_DET |
4057 MAC_STATUS_CFG_CHANGED |
4058 MAC_STATUS_RCVD_CFG);
4059 if (mac_status == (MAC_STATUS_PCS_SYNCED |
4060 MAC_STATUS_SIGNAL_DET)) {
4061 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
4062 MAC_STATUS_CFG_CHANGED));
4067 tw32_f(MAC_TX_AUTO_NEG, 0);
4069 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
4070 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
4071 tw32_f(MAC_MODE, tp->mac_mode);
4074 if (tp->phy_id == TG3_PHY_ID_BCM8002)
4075 tg3_init_bcm8002(tp);
4077 /* Enable link change event even when serdes polling. */
4078 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4081 current_link_up = 0;
4082 mac_status = tr32(MAC_STATUS);
4084 if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
4085 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
4087 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
4089 tp->napi[0].hw_status->status =
4090 (SD_STATUS_UPDATED |
4091 (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
4093 for (i = 0; i < 100; i++) {
4094 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
4095 MAC_STATUS_CFG_CHANGED));
4097 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
4098 MAC_STATUS_CFG_CHANGED |
4099 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
4103 mac_status = tr32(MAC_STATUS);
4104 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
4105 current_link_up = 0;
4106 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
4107 tp->serdes_counter == 0) {
4108 tw32_f(MAC_MODE, (tp->mac_mode |
4109 MAC_MODE_SEND_CONFIGS));
4111 tw32_f(MAC_MODE, tp->mac_mode);
4115 if (current_link_up == 1) {
4116 tp->link_config.active_speed = SPEED_1000;
4117 tp->link_config.active_duplex = DUPLEX_FULL;
4118 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4119 LED_CTRL_LNKLED_OVERRIDE |
4120 LED_CTRL_1000MBPS_ON));
4122 tp->link_config.active_speed = SPEED_INVALID;
4123 tp->link_config.active_duplex = DUPLEX_INVALID;
4124 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4125 LED_CTRL_LNKLED_OVERRIDE |
4126 LED_CTRL_TRAFFIC_OVERRIDE));
4129 if (current_link_up != netif_carrier_ok(tp->dev)) {
4130 if (current_link_up)
4131 netif_carrier_on(tp->dev);
4133 netif_carrier_off(tp->dev);
4134 tg3_link_report(tp);
4136 u32 now_pause_cfg = tp->link_config.active_flowctrl;
4137 if (orig_pause_cfg != now_pause_cfg ||
4138 orig_active_speed != tp->link_config.active_speed ||
4139 orig_active_duplex != tp->link_config.active_duplex)
4140 tg3_link_report(tp);
4146 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
4148 int current_link_up, err = 0;
4152 u32 local_adv, remote_adv;
4154 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4155 tw32_f(MAC_MODE, tp->mac_mode);
4161 (MAC_STATUS_SYNC_CHANGED |
4162 MAC_STATUS_CFG_CHANGED |
4163 MAC_STATUS_MI_COMPLETION |
4164 MAC_STATUS_LNKSTATE_CHANGED));
4170 current_link_up = 0;
4171 current_speed = SPEED_INVALID;
4172 current_duplex = DUPLEX_INVALID;
4174 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4175 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4176 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
4177 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4178 bmsr |= BMSR_LSTATUS;
4180 bmsr &= ~BMSR_LSTATUS;
4183 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
4185 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
4186 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
4187 /* do nothing, just check for link up at the end */
4188 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4191 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4192 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4193 ADVERTISE_1000XPAUSE |
4194 ADVERTISE_1000XPSE_ASYM |
4197 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4199 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4200 new_adv |= ADVERTISE_1000XHALF;
4201 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4202 new_adv |= ADVERTISE_1000XFULL;
4204 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4205 tg3_writephy(tp, MII_ADVERTISE, new_adv);
4206 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4207 tg3_writephy(tp, MII_BMCR, bmcr);
4209 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4210 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
4211 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4218 bmcr &= ~BMCR_SPEED1000;
4219 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4221 if (tp->link_config.duplex == DUPLEX_FULL)
4222 new_bmcr |= BMCR_FULLDPLX;
4224 if (new_bmcr != bmcr) {
4225 /* BMCR_SPEED1000 is a reserved bit that needs
4226 * to be set on write.
4228 new_bmcr |= BMCR_SPEED1000;
4230 /* Force a linkdown */
4231 if (netif_carrier_ok(tp->dev)) {
4234 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4235 adv &= ~(ADVERTISE_1000XFULL |
4236 ADVERTISE_1000XHALF |
4238 tg3_writephy(tp, MII_ADVERTISE, adv);
4239 tg3_writephy(tp, MII_BMCR, bmcr |
4243 netif_carrier_off(tp->dev);
4245 tg3_writephy(tp, MII_BMCR, new_bmcr);
4247 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4248 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4249 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4251 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4252 bmsr |= BMSR_LSTATUS;
4254 bmsr &= ~BMSR_LSTATUS;
4256 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4260 if (bmsr & BMSR_LSTATUS) {
4261 current_speed = SPEED_1000;
4262 current_link_up = 1;
4263 if (bmcr & BMCR_FULLDPLX)
4264 current_duplex = DUPLEX_FULL;
4266 current_duplex = DUPLEX_HALF;
4271 if (bmcr & BMCR_ANENABLE) {
4274 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4275 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4276 common = local_adv & remote_adv;
4277 if (common & (ADVERTISE_1000XHALF |
4278 ADVERTISE_1000XFULL)) {
4279 if (common & ADVERTISE_1000XFULL)
4280 current_duplex = DUPLEX_FULL;
4282 current_duplex = DUPLEX_HALF;
4283 } else if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
4284 /* Link is up via parallel detect */
4286 current_link_up = 0;
4291 if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4292 tg3_setup_flow_control(tp, local_adv, remote_adv);
4294 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4295 if (tp->link_config.active_duplex == DUPLEX_HALF)
4296 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4298 tw32_f(MAC_MODE, tp->mac_mode);
4301 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4303 tp->link_config.active_speed = current_speed;
4304 tp->link_config.active_duplex = current_duplex;
4306 if (current_link_up != netif_carrier_ok(tp->dev)) {
4307 if (current_link_up)
4308 netif_carrier_on(tp->dev);
4310 netif_carrier_off(tp->dev);
4311 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4313 tg3_link_report(tp);
4318 static void tg3_serdes_parallel_detect(struct tg3 *tp)
4320 if (tp->serdes_counter) {
4321 /* Give autoneg time to complete. */
4322 tp->serdes_counter--;
4326 if (!netif_carrier_ok(tp->dev) &&
4327 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4330 tg3_readphy(tp, MII_BMCR, &bmcr);
4331 if (bmcr & BMCR_ANENABLE) {
4334 /* Select shadow register 0x1f */
4335 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x7c00);
4336 tg3_readphy(tp, MII_TG3_MISC_SHDW, &phy1);
4338 /* Select expansion interrupt status register */
4339 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
4340 MII_TG3_DSP_EXP1_INT_STAT);
4341 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4342 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4344 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4345 /* We have signal detect and not receiving
4346 * config code words, link is up by parallel
4350 bmcr &= ~BMCR_ANENABLE;
4351 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4352 tg3_writephy(tp, MII_BMCR, bmcr);
4353 tp->phy_flags |= TG3_PHYFLG_PARALLEL_DETECT;
4356 } else if (netif_carrier_ok(tp->dev) &&
4357 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4358 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
4361 /* Select expansion interrupt status register */
4362 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
4363 MII_TG3_DSP_EXP1_INT_STAT);
4364 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4368 /* Config code words received, turn on autoneg. */
4369 tg3_readphy(tp, MII_BMCR, &bmcr);
4370 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4372 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4378 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4382 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
4383 err = tg3_setup_fiber_phy(tp, force_reset);
4384 else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
4385 err = tg3_setup_fiber_mii_phy(tp, force_reset);
4387 err = tg3_setup_copper_phy(tp, force_reset);
4389 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
4392 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4393 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4395 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4400 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4401 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4402 tw32(GRC_MISC_CFG, val);
4405 if (tp->link_config.active_speed == SPEED_1000 &&
4406 tp->link_config.active_duplex == DUPLEX_HALF)
4407 tw32(MAC_TX_LENGTHS,
4408 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4409 (6 << TX_LENGTHS_IPG_SHIFT) |
4410 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
4412 tw32(MAC_TX_LENGTHS,
4413 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4414 (6 << TX_LENGTHS_IPG_SHIFT) |
4415 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
4417 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4418 if (netif_carrier_ok(tp->dev)) {
4419 tw32(HOSTCC_STAT_COAL_TICKS,
4420 tp->coal.stats_block_coalesce_usecs);
4422 tw32(HOSTCC_STAT_COAL_TICKS, 0);
4426 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4427 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
4428 if (!netif_carrier_ok(tp->dev))
4429 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4432 val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4433 tw32(PCIE_PWR_MGMT_THRESH, val);
4439 static inline int tg3_irq_sync(struct tg3 *tp)
4441 return tp->irq_sync;
4444 /* This is called whenever we suspect that the system chipset is re-
4445 * ordering the sequence of MMIO to the tx send mailbox. The symptom
4446 * is bogus tx completions. We try to recover by setting the
4447 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4450 static void tg3_tx_recover(struct tg3 *tp)
4452 BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4453 tp->write32_tx_mbox == tg3_write_indirect_mbox);
4455 netdev_warn(tp->dev,
4456 "The system may be re-ordering memory-mapped I/O "
4457 "cycles to the network device, attempting to recover. "
4458 "Please report the problem to the driver maintainer "
4459 "and include system chipset information.\n");
4461 spin_lock(&tp->lock);
4462 tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
4463 spin_unlock(&tp->lock);
4466 static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
4468 /* Tell compiler to fetch tx indices from memory. */
4470 return tnapi->tx_pending -
4471 ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
4474 /* Tigon3 never reports partial packet sends. So we do not
4475 * need special logic to handle SKBs that have not had all
4476 * of their frags sent yet, like SunGEM does.
4478 static void tg3_tx(struct tg3_napi *tnapi)
4480 struct tg3 *tp = tnapi->tp;
4481 u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
4482 u32 sw_idx = tnapi->tx_cons;
4483 struct netdev_queue *txq;
4484 int index = tnapi - tp->napi;
4486 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
4489 txq = netdev_get_tx_queue(tp->dev, index);
4491 while (sw_idx != hw_idx) {
4492 struct ring_info *ri = &tnapi->tx_buffers[sw_idx];
4493 struct sk_buff *skb = ri->skb;
4496 if (unlikely(skb == NULL)) {
4501 pci_unmap_single(tp->pdev,
4502 dma_unmap_addr(ri, mapping),
4508 sw_idx = NEXT_TX(sw_idx);
4510 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
4511 ri = &tnapi->tx_buffers[sw_idx];
4512 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4515 pci_unmap_page(tp->pdev,
4516 dma_unmap_addr(ri, mapping),
4517 skb_shinfo(skb)->frags[i].size,
4519 sw_idx = NEXT_TX(sw_idx);
4524 if (unlikely(tx_bug)) {
4530 tnapi->tx_cons = sw_idx;
4532 /* Need to make the tx_cons update visible to tg3_start_xmit()
4533 * before checking for netif_queue_stopped(). Without the
4534 * memory barrier, there is a small possibility that tg3_start_xmit()
4535 * will miss it and cause the queue to be stopped forever.
4539 if (unlikely(netif_tx_queue_stopped(txq) &&
4540 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
4541 __netif_tx_lock(txq, smp_processor_id());
4542 if (netif_tx_queue_stopped(txq) &&
4543 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
4544 netif_tx_wake_queue(txq);
4545 __netif_tx_unlock(txq);
4549 static void tg3_rx_skb_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
4554 pci_unmap_single(tp->pdev, dma_unmap_addr(ri, mapping),
4555 map_sz, PCI_DMA_FROMDEVICE);
4556 dev_kfree_skb_any(ri->skb);
4560 /* Returns size of skb allocated or < 0 on error.
4562 * We only need to fill in the address because the other members
4563 * of the RX descriptor are invariant, see tg3_init_rings.
4565 * Note the purposeful assymetry of cpu vs. chip accesses. For
4566 * posting buffers we only dirty the first cache line of the RX
4567 * descriptor (containing the address). Whereas for the RX status
4568 * buffers the cpu only reads the last cacheline of the RX descriptor
4569 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4571 static int tg3_alloc_rx_skb(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
4572 u32 opaque_key, u32 dest_idx_unmasked)
4574 struct tg3_rx_buffer_desc *desc;
4575 struct ring_info *map;
4576 struct sk_buff *skb;
4578 int skb_size, dest_idx;
4580 switch (opaque_key) {
4581 case RXD_OPAQUE_RING_STD:
4582 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
4583 desc = &tpr->rx_std[dest_idx];
4584 map = &tpr->rx_std_buffers[dest_idx];
4585 skb_size = tp->rx_pkt_map_sz;
4588 case RXD_OPAQUE_RING_JUMBO:
4589 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
4590 desc = &tpr->rx_jmb[dest_idx].std;
4591 map = &tpr->rx_jmb_buffers[dest_idx];
4592 skb_size = TG3_RX_JMB_MAP_SZ;
4599 /* Do not overwrite any of the map or rp information
4600 * until we are sure we can commit to a new buffer.
4602 * Callers depend upon this behavior and assume that
4603 * we leave everything unchanged if we fail.
4605 skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset);
4609 skb_reserve(skb, tp->rx_offset);
4611 mapping = pci_map_single(tp->pdev, skb->data, skb_size,
4612 PCI_DMA_FROMDEVICE);
4613 if (pci_dma_mapping_error(tp->pdev, mapping)) {
4619 dma_unmap_addr_set(map, mapping, mapping);
4621 desc->addr_hi = ((u64)mapping >> 32);
4622 desc->addr_lo = ((u64)mapping & 0xffffffff);
4627 /* We only need to move over in the address because the other
4628 * members of the RX descriptor are invariant. See notes above
4629 * tg3_alloc_rx_skb for full details.
4631 static void tg3_recycle_rx(struct tg3_napi *tnapi,
4632 struct tg3_rx_prodring_set *dpr,
4633 u32 opaque_key, int src_idx,
4634 u32 dest_idx_unmasked)
4636 struct tg3 *tp = tnapi->tp;
4637 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4638 struct ring_info *src_map, *dest_map;
4639 struct tg3_rx_prodring_set *spr = &tp->napi[0].prodring;
4642 switch (opaque_key) {
4643 case RXD_OPAQUE_RING_STD:
4644 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
4645 dest_desc = &dpr->rx_std[dest_idx];
4646 dest_map = &dpr->rx_std_buffers[dest_idx];
4647 src_desc = &spr->rx_std[src_idx];
4648 src_map = &spr->rx_std_buffers[src_idx];
4651 case RXD_OPAQUE_RING_JUMBO:
4652 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
4653 dest_desc = &dpr->rx_jmb[dest_idx].std;
4654 dest_map = &dpr->rx_jmb_buffers[dest_idx];
4655 src_desc = &spr->rx_jmb[src_idx].std;
4656 src_map = &spr->rx_jmb_buffers[src_idx];
4663 dest_map->skb = src_map->skb;
4664 dma_unmap_addr_set(dest_map, mapping,
4665 dma_unmap_addr(src_map, mapping));
4666 dest_desc->addr_hi = src_desc->addr_hi;
4667 dest_desc->addr_lo = src_desc->addr_lo;
4669 /* Ensure that the update to the skb happens after the physical
4670 * addresses have been transferred to the new BD location.
4674 src_map->skb = NULL;
4677 /* The RX ring scheme is composed of multiple rings which post fresh
4678 * buffers to the chip, and one special ring the chip uses to report
4679 * status back to the host.
4681 * The special ring reports the status of received packets to the
4682 * host. The chip does not write into the original descriptor the
4683 * RX buffer was obtained from. The chip simply takes the original
4684 * descriptor as provided by the host, updates the status and length
4685 * field, then writes this into the next status ring entry.
4687 * Each ring the host uses to post buffers to the chip is described
4688 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
4689 * it is first placed into the on-chip ram. When the packet's length
4690 * is known, it walks down the TG3_BDINFO entries to select the ring.
4691 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4692 * which is within the range of the new packet's length is chosen.
4694 * The "separate ring for rx status" scheme may sound queer, but it makes
4695 * sense from a cache coherency perspective. If only the host writes
4696 * to the buffer post rings, and only the chip writes to the rx status
4697 * rings, then cache lines never move beyond shared-modified state.
4698 * If both the host and chip were to write into the same ring, cache line
4699 * eviction could occur since both entities want it in an exclusive state.
4701 static int tg3_rx(struct tg3_napi *tnapi, int budget)
4703 struct tg3 *tp = tnapi->tp;
4704 u32 work_mask, rx_std_posted = 0;
4705 u32 std_prod_idx, jmb_prod_idx;
4706 u32 sw_idx = tnapi->rx_rcb_ptr;
4709 struct tg3_rx_prodring_set *tpr = &tnapi->prodring;
4711 hw_idx = *(tnapi->rx_rcb_prod_idx);
4713 * We need to order the read of hw_idx and the read of
4714 * the opaque cookie.
4719 std_prod_idx = tpr->rx_std_prod_idx;
4720 jmb_prod_idx = tpr->rx_jmb_prod_idx;
4721 while (sw_idx != hw_idx && budget > 0) {
4722 struct ring_info *ri;
4723 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
4725 struct sk_buff *skb;
4726 dma_addr_t dma_addr;
4727 u32 opaque_key, desc_idx, *post_ptr;
4728 bool hw_vlan __maybe_unused = false;
4729 u16 vtag __maybe_unused = 0;
4731 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4732 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4733 if (opaque_key == RXD_OPAQUE_RING_STD) {
4734 ri = &tp->napi[0].prodring.rx_std_buffers[desc_idx];
4735 dma_addr = dma_unmap_addr(ri, mapping);
4737 post_ptr = &std_prod_idx;
4739 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
4740 ri = &tp->napi[0].prodring.rx_jmb_buffers[desc_idx];
4741 dma_addr = dma_unmap_addr(ri, mapping);
4743 post_ptr = &jmb_prod_idx;
4745 goto next_pkt_nopost;
4747 work_mask |= opaque_key;
4749 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4750 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4752 tg3_recycle_rx(tnapi, tpr, opaque_key,
4753 desc_idx, *post_ptr);
4755 /* Other statistics kept track of by card. */
4760 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4763 if (len > TG3_RX_COPY_THRESH(tp)) {
4766 skb_size = tg3_alloc_rx_skb(tp, tpr, opaque_key,
4771 pci_unmap_single(tp->pdev, dma_addr, skb_size,
4772 PCI_DMA_FROMDEVICE);
4774 /* Ensure that the update to the skb happens
4775 * after the usage of the old DMA mapping.
4783 struct sk_buff *copy_skb;
4785 tg3_recycle_rx(tnapi, tpr, opaque_key,
4786 desc_idx, *post_ptr);
4788 copy_skb = netdev_alloc_skb(tp->dev, len + VLAN_HLEN +
4790 if (copy_skb == NULL)
4791 goto drop_it_no_recycle;
4793 skb_reserve(copy_skb, TG3_RAW_IP_ALIGN + VLAN_HLEN);
4794 skb_put(copy_skb, len);
4795 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4796 skb_copy_from_linear_data(skb, copy_skb->data, len);
4797 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4799 /* We'll reuse the original ring buffer. */
4803 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4804 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4805 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4806 >> RXD_TCPCSUM_SHIFT) == 0xffff))
4807 skb->ip_summed = CHECKSUM_UNNECESSARY;
4809 skb_checksum_none_assert(skb);
4811 skb->protocol = eth_type_trans(skb, tp->dev);
4813 if (len > (tp->dev->mtu + ETH_HLEN) &&
4814 skb->protocol != htons(ETH_P_8021Q)) {
4816 goto drop_it_no_recycle;
4819 if (desc->type_flags & RXD_FLAG_VLAN &&
4820 !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG)) {
4821 vtag = desc->err_vlan & RXD_VLAN_MASK;
4822 #if TG3_VLAN_TAG_USED
4828 struct vlan_ethhdr *ve = (struct vlan_ethhdr *)
4829 __skb_push(skb, VLAN_HLEN);
4831 memmove(ve, skb->data + VLAN_HLEN,
4833 ve->h_vlan_proto = htons(ETH_P_8021Q);
4834 ve->h_vlan_TCI = htons(vtag);
4838 #if TG3_VLAN_TAG_USED
4840 vlan_gro_receive(&tnapi->napi, tp->vlgrp, vtag, skb);
4843 napi_gro_receive(&tnapi->napi, skb);
4851 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4852 tpr->rx_std_prod_idx = std_prod_idx &
4853 tp->rx_std_ring_mask;
4854 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4855 tpr->rx_std_prod_idx);
4856 work_mask &= ~RXD_OPAQUE_RING_STD;
4861 sw_idx &= tp->rx_ret_ring_mask;
4863 /* Refresh hw_idx to see if there is new work */
4864 if (sw_idx == hw_idx) {
4865 hw_idx = *(tnapi->rx_rcb_prod_idx);
4870 /* ACK the status ring. */
4871 tnapi->rx_rcb_ptr = sw_idx;
4872 tw32_rx_mbox(tnapi->consmbox, sw_idx);
4874 /* Refill RX ring(s). */
4875 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) {
4876 if (work_mask & RXD_OPAQUE_RING_STD) {
4877 tpr->rx_std_prod_idx = std_prod_idx &
4878 tp->rx_std_ring_mask;
4879 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4880 tpr->rx_std_prod_idx);
4882 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4883 tpr->rx_jmb_prod_idx = jmb_prod_idx &
4884 tp->rx_jmb_ring_mask;
4885 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
4886 tpr->rx_jmb_prod_idx);
4889 } else if (work_mask) {
4890 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
4891 * updated before the producer indices can be updated.
4895 tpr->rx_std_prod_idx = std_prod_idx & tp->rx_std_ring_mask;
4896 tpr->rx_jmb_prod_idx = jmb_prod_idx & tp->rx_jmb_ring_mask;
4898 if (tnapi != &tp->napi[1])
4899 napi_schedule(&tp->napi[1].napi);
4905 static void tg3_poll_link(struct tg3 *tp)
4907 /* handle link change and other phy events */
4908 if (!(tp->tg3_flags &
4909 (TG3_FLAG_USE_LINKCHG_REG |
4910 TG3_FLAG_POLL_SERDES))) {
4911 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
4913 if (sblk->status & SD_STATUS_LINK_CHG) {
4914 sblk->status = SD_STATUS_UPDATED |
4915 (sblk->status & ~SD_STATUS_LINK_CHG);
4916 spin_lock(&tp->lock);
4917 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4919 (MAC_STATUS_SYNC_CHANGED |
4920 MAC_STATUS_CFG_CHANGED |
4921 MAC_STATUS_MI_COMPLETION |
4922 MAC_STATUS_LNKSTATE_CHANGED));
4925 tg3_setup_phy(tp, 0);
4926 spin_unlock(&tp->lock);
4931 static int tg3_rx_prodring_xfer(struct tg3 *tp,
4932 struct tg3_rx_prodring_set *dpr,
4933 struct tg3_rx_prodring_set *spr)
4935 u32 si, di, cpycnt, src_prod_idx;
4939 src_prod_idx = spr->rx_std_prod_idx;
4941 /* Make sure updates to the rx_std_buffers[] entries and the
4942 * standard producer index are seen in the correct order.
4946 if (spr->rx_std_cons_idx == src_prod_idx)
4949 if (spr->rx_std_cons_idx < src_prod_idx)
4950 cpycnt = src_prod_idx - spr->rx_std_cons_idx;
4952 cpycnt = tp->rx_std_ring_mask + 1 -
4953 spr->rx_std_cons_idx;
4955 cpycnt = min(cpycnt,
4956 tp->rx_std_ring_mask + 1 - dpr->rx_std_prod_idx);
4958 si = spr->rx_std_cons_idx;
4959 di = dpr->rx_std_prod_idx;
4961 for (i = di; i < di + cpycnt; i++) {
4962 if (dpr->rx_std_buffers[i].skb) {
4972 /* Ensure that updates to the rx_std_buffers ring and the
4973 * shadowed hardware producer ring from tg3_recycle_skb() are
4974 * ordered correctly WRT the skb check above.
4978 memcpy(&dpr->rx_std_buffers[di],
4979 &spr->rx_std_buffers[si],
4980 cpycnt * sizeof(struct ring_info));
4982 for (i = 0; i < cpycnt; i++, di++, si++) {
4983 struct tg3_rx_buffer_desc *sbd, *dbd;
4984 sbd = &spr->rx_std[si];
4985 dbd = &dpr->rx_std[di];
4986 dbd->addr_hi = sbd->addr_hi;
4987 dbd->addr_lo = sbd->addr_lo;
4990 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) &
4991 tp->rx_std_ring_mask;
4992 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) &
4993 tp->rx_std_ring_mask;
4997 src_prod_idx = spr->rx_jmb_prod_idx;
4999 /* Make sure updates to the rx_jmb_buffers[] entries and
5000 * the jumbo producer index are seen in the correct order.
5004 if (spr->rx_jmb_cons_idx == src_prod_idx)
5007 if (spr->rx_jmb_cons_idx < src_prod_idx)
5008 cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
5010 cpycnt = tp->rx_jmb_ring_mask + 1 -
5011 spr->rx_jmb_cons_idx;
5013 cpycnt = min(cpycnt,
5014 tp->rx_jmb_ring_mask + 1 - dpr->rx_jmb_prod_idx);
5016 si = spr->rx_jmb_cons_idx;
5017 di = dpr->rx_jmb_prod_idx;
5019 for (i = di; i < di + cpycnt; i++) {
5020 if (dpr->rx_jmb_buffers[i].skb) {
5030 /* Ensure that updates to the rx_jmb_buffers ring and the
5031 * shadowed hardware producer ring from tg3_recycle_skb() are
5032 * ordered correctly WRT the skb check above.
5036 memcpy(&dpr->rx_jmb_buffers[di],
5037 &spr->rx_jmb_buffers[si],
5038 cpycnt * sizeof(struct ring_info));
5040 for (i = 0; i < cpycnt; i++, di++, si++) {
5041 struct tg3_rx_buffer_desc *sbd, *dbd;
5042 sbd = &spr->rx_jmb[si].std;
5043 dbd = &dpr->rx_jmb[di].std;
5044 dbd->addr_hi = sbd->addr_hi;
5045 dbd->addr_lo = sbd->addr_lo;
5048 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) &
5049 tp->rx_jmb_ring_mask;
5050 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) &
5051 tp->rx_jmb_ring_mask;
5057 static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
5059 struct tg3 *tp = tnapi->tp;
5061 /* run TX completion thread */
5062 if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
5064 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5068 /* run RX thread, within the bounds set by NAPI.
5069 * All RX "locking" is done by ensuring outside
5070 * code synchronizes with tg3->napi.poll()
5072 if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
5073 work_done += tg3_rx(tnapi, budget - work_done);
5075 if ((tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) && tnapi == &tp->napi[1]) {
5076 struct tg3_rx_prodring_set *dpr = &tp->napi[0].prodring;
5078 u32 std_prod_idx = dpr->rx_std_prod_idx;
5079 u32 jmb_prod_idx = dpr->rx_jmb_prod_idx;
5081 for (i = 1; i < tp->irq_cnt; i++)
5082 err |= tg3_rx_prodring_xfer(tp, dpr,
5083 &tp->napi[i].prodring);
5087 if (std_prod_idx != dpr->rx_std_prod_idx)
5088 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
5089 dpr->rx_std_prod_idx);
5091 if (jmb_prod_idx != dpr->rx_jmb_prod_idx)
5092 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
5093 dpr->rx_jmb_prod_idx);
5098 tw32_f(HOSTCC_MODE, tp->coal_now);
5104 static int tg3_poll_msix(struct napi_struct *napi, int budget)
5106 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
5107 struct tg3 *tp = tnapi->tp;
5109 struct tg3_hw_status *sblk = tnapi->hw_status;
5112 work_done = tg3_poll_work(tnapi, work_done, budget);
5114 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5117 if (unlikely(work_done >= budget))
5120 /* tp->last_tag is used in tg3_int_reenable() below
5121 * to tell the hw how much work has been processed,
5122 * so we must read it before checking for more work.
5124 tnapi->last_tag = sblk->status_tag;
5125 tnapi->last_irq_tag = tnapi->last_tag;
5128 /* check for RX/TX work to do */
5129 if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons &&
5130 *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) {
5131 napi_complete(napi);
5132 /* Reenable interrupts. */
5133 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
5142 /* work_done is guaranteed to be less than budget. */
5143 napi_complete(napi);
5144 schedule_work(&tp->reset_task);
5148 static int tg3_poll(struct napi_struct *napi, int budget)
5150 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
5151 struct tg3 *tp = tnapi->tp;
5153 struct tg3_hw_status *sblk = tnapi->hw_status;
5158 work_done = tg3_poll_work(tnapi, work_done, budget);
5160 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5163 if (unlikely(work_done >= budget))
5166 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
5167 /* tp->last_tag is used in tg3_int_reenable() below
5168 * to tell the hw how much work has been processed,
5169 * so we must read it before checking for more work.
5171 tnapi->last_tag = sblk->status_tag;
5172 tnapi->last_irq_tag = tnapi->last_tag;
5175 sblk->status &= ~SD_STATUS_UPDATED;
5177 if (likely(!tg3_has_work(tnapi))) {
5178 napi_complete(napi);
5179 tg3_int_reenable(tnapi);
5187 /* work_done is guaranteed to be less than budget. */
5188 napi_complete(napi);
5189 schedule_work(&tp->reset_task);
5193 static void tg3_napi_disable(struct tg3 *tp)
5197 for (i = tp->irq_cnt - 1; i >= 0; i--)
5198 napi_disable(&tp->napi[i].napi);
5201 static void tg3_napi_enable(struct tg3 *tp)
5205 for (i = 0; i < tp->irq_cnt; i++)
5206 napi_enable(&tp->napi[i].napi);
5209 static void tg3_napi_init(struct tg3 *tp)
5213 netif_napi_add(tp->dev, &tp->napi[0].napi, tg3_poll, 64);
5214 for (i = 1; i < tp->irq_cnt; i++)
5215 netif_napi_add(tp->dev, &tp->napi[i].napi, tg3_poll_msix, 64);
5218 static void tg3_napi_fini(struct tg3 *tp)
5222 for (i = 0; i < tp->irq_cnt; i++)
5223 netif_napi_del(&tp->napi[i].napi);
5226 static inline void tg3_netif_stop(struct tg3 *tp)
5228 tp->dev->trans_start = jiffies; /* prevent tx timeout */
5229 tg3_napi_disable(tp);
5230 netif_tx_disable(tp->dev);
5233 static inline void tg3_netif_start(struct tg3 *tp)
5235 /* NOTE: unconditional netif_tx_wake_all_queues is only
5236 * appropriate so long as all callers are assured to
5237 * have free tx slots (such as after tg3_init_hw)
5239 netif_tx_wake_all_queues(tp->dev);
5241 tg3_napi_enable(tp);
5242 tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
5243 tg3_enable_ints(tp);
5246 static void tg3_irq_quiesce(struct tg3 *tp)
5250 BUG_ON(tp->irq_sync);
5255 for (i = 0; i < tp->irq_cnt; i++)
5256 synchronize_irq(tp->napi[i].irq_vec);
5259 /* Fully shutdown all tg3 driver activity elsewhere in the system.
5260 * If irq_sync is non-zero, then the IRQ handler must be synchronized
5261 * with as well. Most of the time, this is not necessary except when
5262 * shutting down the device.
5264 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
5266 spin_lock_bh(&tp->lock);
5268 tg3_irq_quiesce(tp);
5271 static inline void tg3_full_unlock(struct tg3 *tp)
5273 spin_unlock_bh(&tp->lock);
5276 /* One-shot MSI handler - Chip automatically disables interrupt
5277 * after sending MSI so driver doesn't have to do it.
5279 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
5281 struct tg3_napi *tnapi = dev_id;
5282 struct tg3 *tp = tnapi->tp;
5284 prefetch(tnapi->hw_status);
5286 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5288 if (likely(!tg3_irq_sync(tp)))
5289 napi_schedule(&tnapi->napi);
5294 /* MSI ISR - No need to check for interrupt sharing and no need to
5295 * flush status block and interrupt mailbox. PCI ordering rules
5296 * guarantee that MSI will arrive after the status block.
5298 static irqreturn_t tg3_msi(int irq, void *dev_id)
5300 struct tg3_napi *tnapi = dev_id;
5301 struct tg3 *tp = tnapi->tp;
5303 prefetch(tnapi->hw_status);
5305 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5307 * Writing any value to intr-mbox-0 clears PCI INTA# and
5308 * chip-internal interrupt pending events.
5309 * Writing non-zero to intr-mbox-0 additional tells the
5310 * NIC to stop sending us irqs, engaging "in-intr-handler"
5313 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5314 if (likely(!tg3_irq_sync(tp)))
5315 napi_schedule(&tnapi->napi);
5317 return IRQ_RETVAL(1);
5320 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
5322 struct tg3_napi *tnapi = dev_id;
5323 struct tg3 *tp = tnapi->tp;
5324 struct tg3_hw_status *sblk = tnapi->hw_status;
5325 unsigned int handled = 1;
5327 /* In INTx mode, it is possible for the interrupt to arrive at
5328 * the CPU before the status block posted prior to the interrupt.
5329 * Reading the PCI State register will confirm whether the
5330 * interrupt is ours and will flush the status block.
5332 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
5333 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5334 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5341 * Writing any value to intr-mbox-0 clears PCI INTA# and
5342 * chip-internal interrupt pending events.
5343 * Writing non-zero to intr-mbox-0 additional tells the
5344 * NIC to stop sending us irqs, engaging "in-intr-handler"
5347 * Flush the mailbox to de-assert the IRQ immediately to prevent
5348 * spurious interrupts. The flush impacts performance but
5349 * excessive spurious interrupts can be worse in some cases.
5351 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5352 if (tg3_irq_sync(tp))
5354 sblk->status &= ~SD_STATUS_UPDATED;
5355 if (likely(tg3_has_work(tnapi))) {
5356 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5357 napi_schedule(&tnapi->napi);
5359 /* No work, shared interrupt perhaps? re-enable
5360 * interrupts, and flush that PCI write
5362 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
5366 return IRQ_RETVAL(handled);
5369 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
5371 struct tg3_napi *tnapi = dev_id;
5372 struct tg3 *tp = tnapi->tp;
5373 struct tg3_hw_status *sblk = tnapi->hw_status;
5374 unsigned int handled = 1;
5376 /* In INTx mode, it is possible for the interrupt to arrive at
5377 * the CPU before the status block posted prior to the interrupt.
5378 * Reading the PCI State register will confirm whether the
5379 * interrupt is ours and will flush the status block.
5381 if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
5382 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5383 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5390 * writing any value to intr-mbox-0 clears PCI INTA# and
5391 * chip-internal interrupt pending events.
5392 * writing non-zero to intr-mbox-0 additional tells the
5393 * NIC to stop sending us irqs, engaging "in-intr-handler"
5396 * Flush the mailbox to de-assert the IRQ immediately to prevent
5397 * spurious interrupts. The flush impacts performance but
5398 * excessive spurious interrupts can be worse in some cases.
5400 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5403 * In a shared interrupt configuration, sometimes other devices'
5404 * interrupts will scream. We record the current status tag here
5405 * so that the above check can report that the screaming interrupts
5406 * are unhandled. Eventually they will be silenced.
5408 tnapi->last_irq_tag = sblk->status_tag;
5410 if (tg3_irq_sync(tp))
5413 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5415 napi_schedule(&tnapi->napi);
5418 return IRQ_RETVAL(handled);
5421 /* ISR for interrupt test */
5422 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
5424 struct tg3_napi *tnapi = dev_id;
5425 struct tg3 *tp = tnapi->tp;
5426 struct tg3_hw_status *sblk = tnapi->hw_status;
5428 if ((sblk->status & SD_STATUS_UPDATED) ||
5429 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5430 tg3_disable_ints(tp);
5431 return IRQ_RETVAL(1);
5433 return IRQ_RETVAL(0);
5436 static int tg3_init_hw(struct tg3 *, int);
5437 static int tg3_halt(struct tg3 *, int, int);
5439 /* Restart hardware after configuration changes, self-test, etc.
5440 * Invoked with tp->lock held.
5442 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
5443 __releases(tp->lock)
5444 __acquires(tp->lock)
5448 err = tg3_init_hw(tp, reset_phy);
5451 "Failed to re-initialize device, aborting\n");
5452 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5453 tg3_full_unlock(tp);
5454 del_timer_sync(&tp->timer);
5456 tg3_napi_enable(tp);
5458 tg3_full_lock(tp, 0);
5463 #ifdef CONFIG_NET_POLL_CONTROLLER
5464 static void tg3_poll_controller(struct net_device *dev)
5467 struct tg3 *tp = netdev_priv(dev);
5469 for (i = 0; i < tp->irq_cnt; i++)
5470 tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]);
5474 static void tg3_reset_task(struct work_struct *work)
5476 struct tg3 *tp = container_of(work, struct tg3, reset_task);
5478 unsigned int restart_timer;
5480 tg3_full_lock(tp, 0);
5482 if (!netif_running(tp->dev)) {
5483 tg3_full_unlock(tp);
5487 tg3_full_unlock(tp);
5493 tg3_full_lock(tp, 1);
5495 restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
5496 tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
5498 if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
5499 tp->write32_tx_mbox = tg3_write32_tx_mbox;
5500 tp->write32_rx_mbox = tg3_write_flush_reg32;
5501 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
5502 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
5505 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
5506 err = tg3_init_hw(tp, 1);
5510 tg3_netif_start(tp);
5513 mod_timer(&tp->timer, jiffies + 1);
5516 tg3_full_unlock(tp);
5522 static void tg3_dump_short_state(struct tg3 *tp)
5524 netdev_err(tp->dev, "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
5525 tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
5526 netdev_err(tp->dev, "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
5527 tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
5530 static void tg3_tx_timeout(struct net_device *dev)
5532 struct tg3 *tp = netdev_priv(dev);
5534 if (netif_msg_tx_err(tp)) {
5535 netdev_err(dev, "transmit timed out, resetting\n");
5536 tg3_dump_short_state(tp);
5539 schedule_work(&tp->reset_task);
5542 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5543 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
5545 u32 base = (u32) mapping & 0xffffffff;
5547 return (base > 0xffffdcc0) && (base + len + 8 < base);
5550 /* Test for DMA addresses > 40-bit */
5551 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
5554 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
5555 if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
5556 return ((u64) mapping + len) > DMA_BIT_MASK(40);
5563 static void tg3_set_txd(struct tg3_napi *, int, dma_addr_t, int, u32, u32);
5565 /* Workaround 4GB and 40-bit hardware DMA bugs. */
5566 static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
5567 struct sk_buff *skb, u32 last_plus_one,
5568 u32 *start, u32 base_flags, u32 mss)
5570 struct tg3 *tp = tnapi->tp;
5571 struct sk_buff *new_skb;
5572 dma_addr_t new_addr = 0;
5576 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5577 new_skb = skb_copy(skb, GFP_ATOMIC);
5579 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5581 new_skb = skb_copy_expand(skb,
5582 skb_headroom(skb) + more_headroom,
5583 skb_tailroom(skb), GFP_ATOMIC);
5589 /* New SKB is guaranteed to be linear. */
5591 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
5593 /* Make sure the mapping succeeded */
5594 if (pci_dma_mapping_error(tp->pdev, new_addr)) {
5596 dev_kfree_skb(new_skb);
5599 /* Make sure new skb does not cross any 4G boundaries.
5600 * Drop the packet if it does.
5602 } else if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5603 tg3_4g_overflow_test(new_addr, new_skb->len)) {
5604 pci_unmap_single(tp->pdev, new_addr, new_skb->len,
5607 dev_kfree_skb(new_skb);
5610 tg3_set_txd(tnapi, entry, new_addr, new_skb->len,
5611 base_flags, 1 | (mss << 1));
5612 *start = NEXT_TX(entry);
5616 /* Now clean up the sw ring entries. */
5618 while (entry != last_plus_one) {
5622 len = skb_headlen(skb);
5624 len = skb_shinfo(skb)->frags[i-1].size;
5626 pci_unmap_single(tp->pdev,
5627 dma_unmap_addr(&tnapi->tx_buffers[entry],
5629 len, PCI_DMA_TODEVICE);
5631 tnapi->tx_buffers[entry].skb = new_skb;
5632 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5635 tnapi->tx_buffers[entry].skb = NULL;
5637 entry = NEXT_TX(entry);
5646 static void tg3_set_txd(struct tg3_napi *tnapi, int entry,
5647 dma_addr_t mapping, int len, u32 flags,
5650 struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry];
5651 int is_end = (mss_and_is_end & 0x1);
5652 u32 mss = (mss_and_is_end >> 1);
5656 flags |= TXD_FLAG_END;
5657 if (flags & TXD_FLAG_VLAN) {
5658 vlan_tag = flags >> 16;
5661 vlan_tag |= (mss << TXD_MSS_SHIFT);
5663 txd->addr_hi = ((u64) mapping >> 32);
5664 txd->addr_lo = ((u64) mapping & 0xffffffff);
5665 txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5666 txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5669 /* hard_start_xmit for devices that don't have any bugs and
5670 * support TG3_FLG2_HW_TSO_2 and TG3_FLG2_HW_TSO_3 only.
5672 static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
5673 struct net_device *dev)
5675 struct tg3 *tp = netdev_priv(dev);
5676 u32 len, entry, base_flags, mss;
5678 struct tg3_napi *tnapi;
5679 struct netdev_queue *txq;
5680 unsigned int i, last;
5682 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5683 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5684 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
5687 /* We are running in BH disabled context with netif_tx_lock
5688 * and TX reclaim runs via tp->napi.poll inside of a software
5689 * interrupt. Furthermore, IRQ processing runs lockless so we have
5690 * no IRQ context deadlocks to worry about either. Rejoice!
5692 if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5693 if (!netif_tx_queue_stopped(txq)) {
5694 netif_tx_stop_queue(txq);
5696 /* This is a hard error, log it. */
5698 "BUG! Tx Ring full when queue awake!\n");
5700 return NETDEV_TX_BUSY;
5703 entry = tnapi->tx_prod;
5705 mss = skb_shinfo(skb)->gso_size;
5707 int tcp_opt_len, ip_tcp_len;
5710 if (skb_header_cloned(skb) &&
5711 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5716 if (skb_is_gso_v6(skb)) {
5717 hdrlen = skb_headlen(skb) - ETH_HLEN;
5719 struct iphdr *iph = ip_hdr(skb);
5721 tcp_opt_len = tcp_optlen(skb);
5722 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5725 iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
5726 hdrlen = ip_tcp_len + tcp_opt_len;
5729 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5730 mss |= (hdrlen & 0xc) << 12;
5732 base_flags |= 0x00000010;
5733 base_flags |= (hdrlen & 0x3e0) << 5;
5737 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5738 TXD_FLAG_CPU_POST_DMA);
5740 tcp_hdr(skb)->check = 0;
5742 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5743 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5746 #if TG3_VLAN_TAG_USED
5747 if (vlan_tx_tag_present(skb))
5748 base_flags |= (TXD_FLAG_VLAN |
5749 (vlan_tx_tag_get(skb) << 16));
5752 len = skb_headlen(skb);
5754 /* Queue skb data, a.k.a. the main skb fragment. */
5755 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5756 if (pci_dma_mapping_error(tp->pdev, mapping)) {
5761 tnapi->tx_buffers[entry].skb = skb;
5762 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
5764 if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
5765 !mss && skb->len > VLAN_ETH_FRAME_LEN)
5766 base_flags |= TXD_FLAG_JMB_PKT;
5768 tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5769 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5771 entry = NEXT_TX(entry);
5773 /* Now loop through additional data fragments, and queue them. */
5774 if (skb_shinfo(skb)->nr_frags > 0) {
5775 last = skb_shinfo(skb)->nr_frags - 1;
5776 for (i = 0; i <= last; i++) {
5777 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5780 mapping = pci_map_page(tp->pdev,
5783 len, PCI_DMA_TODEVICE);
5784 if (pci_dma_mapping_error(tp->pdev, mapping))
5787 tnapi->tx_buffers[entry].skb = NULL;
5788 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5791 tg3_set_txd(tnapi, entry, mapping, len,
5792 base_flags, (i == last) | (mss << 1));
5794 entry = NEXT_TX(entry);
5798 /* Packets are ready, update Tx producer idx local and on card. */
5799 tw32_tx_mbox(tnapi->prodmbox, entry);
5801 tnapi->tx_prod = entry;
5802 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5803 netif_tx_stop_queue(txq);
5805 /* netif_tx_stop_queue() must be done before checking
5806 * checking tx index in tg3_tx_avail() below, because in
5807 * tg3_tx(), we update tx index before checking for
5808 * netif_tx_queue_stopped().
5811 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5812 netif_tx_wake_queue(txq);
5818 return NETDEV_TX_OK;
5822 entry = tnapi->tx_prod;
5823 tnapi->tx_buffers[entry].skb = NULL;
5824 pci_unmap_single(tp->pdev,
5825 dma_unmap_addr(&tnapi->tx_buffers[entry], mapping),
5828 for (i = 0; i <= last; i++) {
5829 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5830 entry = NEXT_TX(entry);
5832 pci_unmap_page(tp->pdev,
5833 dma_unmap_addr(&tnapi->tx_buffers[entry],
5835 frag->size, PCI_DMA_TODEVICE);
5839 return NETDEV_TX_OK;
5842 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *,
5843 struct net_device *);
5845 /* Use GSO to workaround a rare TSO bug that may be triggered when the
5846 * TSO header is greater than 80 bytes.
5848 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5850 struct sk_buff *segs, *nskb;
5851 u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
5853 /* Estimate the number of fragments in the worst case */
5854 if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
5855 netif_stop_queue(tp->dev);
5857 /* netif_tx_stop_queue() must be done before checking
5858 * checking tx index in tg3_tx_avail() below, because in
5859 * tg3_tx(), we update tx index before checking for
5860 * netif_tx_queue_stopped().
5863 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
5864 return NETDEV_TX_BUSY;
5866 netif_wake_queue(tp->dev);
5869 segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
5871 goto tg3_tso_bug_end;
5877 tg3_start_xmit_dma_bug(nskb, tp->dev);
5883 return NETDEV_TX_OK;
5886 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5887 * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5889 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
5890 struct net_device *dev)
5892 struct tg3 *tp = netdev_priv(dev);
5893 u32 len, entry, base_flags, mss;
5894 int would_hit_hwbug;
5896 struct tg3_napi *tnapi;
5897 struct netdev_queue *txq;
5898 unsigned int i, last;
5900 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5901 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5902 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
5905 /* We are running in BH disabled context with netif_tx_lock
5906 * and TX reclaim runs via tp->napi.poll inside of a software
5907 * interrupt. Furthermore, IRQ processing runs lockless so we have
5908 * no IRQ context deadlocks to worry about either. Rejoice!
5910 if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5911 if (!netif_tx_queue_stopped(txq)) {
5912 netif_tx_stop_queue(txq);
5914 /* This is a hard error, log it. */
5916 "BUG! Tx Ring full when queue awake!\n");
5918 return NETDEV_TX_BUSY;
5921 entry = tnapi->tx_prod;
5923 if (skb->ip_summed == CHECKSUM_PARTIAL)
5924 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5926 mss = skb_shinfo(skb)->gso_size;
5929 u32 tcp_opt_len, hdr_len;
5931 if (skb_header_cloned(skb) &&
5932 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5938 tcp_opt_len = tcp_optlen(skb);
5940 if (skb_is_gso_v6(skb)) {
5941 hdr_len = skb_headlen(skb) - ETH_HLEN;
5945 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5946 hdr_len = ip_tcp_len + tcp_opt_len;
5949 iph->tot_len = htons(mss + hdr_len);
5952 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
5953 (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
5954 return tg3_tso_bug(tp, skb);
5956 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5957 TXD_FLAG_CPU_POST_DMA);
5959 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
5960 tcp_hdr(skb)->check = 0;
5961 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
5963 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5968 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5969 mss |= (hdr_len & 0xc) << 12;
5971 base_flags |= 0x00000010;
5972 base_flags |= (hdr_len & 0x3e0) << 5;
5973 } else if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)
5974 mss |= hdr_len << 9;
5975 else if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_1) ||
5976 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
5977 if (tcp_opt_len || iph->ihl > 5) {
5980 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5981 mss |= (tsflags << 11);
5984 if (tcp_opt_len || iph->ihl > 5) {
5987 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5988 base_flags |= tsflags << 12;
5992 #if TG3_VLAN_TAG_USED
5993 if (vlan_tx_tag_present(skb))
5994 base_flags |= (TXD_FLAG_VLAN |
5995 (vlan_tx_tag_get(skb) << 16));
5998 if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
5999 !mss && skb->len > VLAN_ETH_FRAME_LEN)
6000 base_flags |= TXD_FLAG_JMB_PKT;
6002 len = skb_headlen(skb);
6004 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
6005 if (pci_dma_mapping_error(tp->pdev, mapping)) {
6010 tnapi->tx_buffers[entry].skb = skb;
6011 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
6013 would_hit_hwbug = 0;
6015 if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) && len <= 8)
6016 would_hit_hwbug = 1;
6018 if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
6019 tg3_4g_overflow_test(mapping, len))
6020 would_hit_hwbug = 1;
6022 if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
6023 tg3_40bit_overflow_test(tp, mapping, len))
6024 would_hit_hwbug = 1;
6026 if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
6027 would_hit_hwbug = 1;
6029 tg3_set_txd(tnapi, entry, mapping, len, base_flags,
6030 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
6032 entry = NEXT_TX(entry);
6034 /* Now loop through additional data fragments, and queue them. */
6035 if (skb_shinfo(skb)->nr_frags > 0) {
6036 last = skb_shinfo(skb)->nr_frags - 1;
6037 for (i = 0; i <= last; i++) {
6038 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6041 mapping = pci_map_page(tp->pdev,
6044 len, PCI_DMA_TODEVICE);
6046 tnapi->tx_buffers[entry].skb = NULL;
6047 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
6049 if (pci_dma_mapping_error(tp->pdev, mapping))
6052 if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) &&
6054 would_hit_hwbug = 1;
6056 if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
6057 tg3_4g_overflow_test(mapping, len))
6058 would_hit_hwbug = 1;
6060 if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
6061 tg3_40bit_overflow_test(tp, mapping, len))
6062 would_hit_hwbug = 1;
6064 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6065 tg3_set_txd(tnapi, entry, mapping, len,
6066 base_flags, (i == last)|(mss << 1));
6068 tg3_set_txd(tnapi, entry, mapping, len,
6069 base_flags, (i == last));
6071 entry = NEXT_TX(entry);
6075 if (would_hit_hwbug) {
6076 u32 last_plus_one = entry;
6079 start = entry - 1 - skb_shinfo(skb)->nr_frags;
6080 start &= (TG3_TX_RING_SIZE - 1);
6082 /* If the workaround fails due to memory/mapping
6083 * failure, silently drop this packet.
6085 if (tigon3_dma_hwbug_workaround(tnapi, skb, last_plus_one,
6086 &start, base_flags, mss))
6092 /* Packets are ready, update Tx producer idx local and on card. */
6093 tw32_tx_mbox(tnapi->prodmbox, entry);
6095 tnapi->tx_prod = entry;
6096 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
6097 netif_tx_stop_queue(txq);
6099 /* netif_tx_stop_queue() must be done before checking
6100 * checking tx index in tg3_tx_avail() below, because in
6101 * tg3_tx(), we update tx index before checking for
6102 * netif_tx_queue_stopped().
6105 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
6106 netif_tx_wake_queue(txq);
6112 return NETDEV_TX_OK;
6116 entry = tnapi->tx_prod;
6117 tnapi->tx_buffers[entry].skb = NULL;
6118 pci_unmap_single(tp->pdev,
6119 dma_unmap_addr(&tnapi->tx_buffers[entry], mapping),
6122 for (i = 0; i <= last; i++) {
6123 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6124 entry = NEXT_TX(entry);
6126 pci_unmap_page(tp->pdev,
6127 dma_unmap_addr(&tnapi->tx_buffers[entry],
6129 frag->size, PCI_DMA_TODEVICE);
6133 return NETDEV_TX_OK;
6136 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
6141 if (new_mtu > ETH_DATA_LEN) {
6142 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
6143 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
6144 ethtool_op_set_tso(dev, 0);
6146 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
6149 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
6150 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
6151 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
6155 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
6157 struct tg3 *tp = netdev_priv(dev);
6160 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
6163 if (!netif_running(dev)) {
6164 /* We'll just catch it later when the
6167 tg3_set_mtu(dev, tp, new_mtu);
6175 tg3_full_lock(tp, 1);
6177 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6179 tg3_set_mtu(dev, tp, new_mtu);
6181 err = tg3_restart_hw(tp, 0);
6184 tg3_netif_start(tp);
6186 tg3_full_unlock(tp);
6194 static void tg3_rx_prodring_free(struct tg3 *tp,
6195 struct tg3_rx_prodring_set *tpr)
6199 if (tpr != &tp->napi[0].prodring) {
6200 for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx;
6201 i = (i + 1) & tp->rx_std_ring_mask)
6202 tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
6205 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
6206 for (i = tpr->rx_jmb_cons_idx;
6207 i != tpr->rx_jmb_prod_idx;
6208 i = (i + 1) & tp->rx_jmb_ring_mask) {
6209 tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
6217 for (i = 0; i <= tp->rx_std_ring_mask; i++)
6218 tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
6221 if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
6222 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
6223 for (i = 0; i <= tp->rx_jmb_ring_mask; i++)
6224 tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
6229 /* Initialize rx rings for packet processing.
6231 * The chip has been shut down and the driver detached from
6232 * the networking, so no interrupts or new tx packets will
6233 * end up in the driver. tp->{tx,}lock are held and thus
6236 static int tg3_rx_prodring_alloc(struct tg3 *tp,
6237 struct tg3_rx_prodring_set *tpr)
6239 u32 i, rx_pkt_dma_sz;
6241 tpr->rx_std_cons_idx = 0;
6242 tpr->rx_std_prod_idx = 0;
6243 tpr->rx_jmb_cons_idx = 0;
6244 tpr->rx_jmb_prod_idx = 0;
6246 if (tpr != &tp->napi[0].prodring) {
6247 memset(&tpr->rx_std_buffers[0], 0,
6248 TG3_RX_STD_BUFF_RING_SIZE(tp));
6249 if (tpr->rx_jmb_buffers)
6250 memset(&tpr->rx_jmb_buffers[0], 0,
6251 TG3_RX_JMB_BUFF_RING_SIZE(tp));
6255 /* Zero out all descriptors. */
6256 memset(tpr->rx_std, 0, TG3_RX_STD_RING_BYTES(tp));
6258 rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
6259 if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
6260 tp->dev->mtu > ETH_DATA_LEN)
6261 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
6262 tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
6264 /* Initialize invariants of the rings, we only set this
6265 * stuff once. This works because the card does not
6266 * write into the rx buffer posting rings.
6268 for (i = 0; i <= tp->rx_std_ring_mask; i++) {
6269 struct tg3_rx_buffer_desc *rxd;
6271 rxd = &tpr->rx_std[i];
6272 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
6273 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
6274 rxd->opaque = (RXD_OPAQUE_RING_STD |
6275 (i << RXD_OPAQUE_INDEX_SHIFT));
6278 /* Now allocate fresh SKBs for each rx ring. */
6279 for (i = 0; i < tp->rx_pending; i++) {
6280 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_STD, i) < 0) {
6281 netdev_warn(tp->dev,
6282 "Using a smaller RX standard ring. Only "
6283 "%d out of %d buffers were allocated "
6284 "successfully\n", i, tp->rx_pending);
6292 if (!(tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ||
6293 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
6296 memset(tpr->rx_jmb, 0, TG3_RX_JMB_RING_BYTES(tp));
6298 if (!(tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE))
6301 for (i = 0; i <= tp->rx_jmb_ring_mask; i++) {
6302 struct tg3_rx_buffer_desc *rxd;
6304 rxd = &tpr->rx_jmb[i].std;
6305 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
6306 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
6308 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
6309 (i << RXD_OPAQUE_INDEX_SHIFT));
6312 for (i = 0; i < tp->rx_jumbo_pending; i++) {
6313 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_JUMBO, i) < 0) {
6314 netdev_warn(tp->dev,
6315 "Using a smaller RX jumbo ring. Only %d "
6316 "out of %d buffers were allocated "
6317 "successfully\n", i, tp->rx_jumbo_pending);
6320 tp->rx_jumbo_pending = i;
6329 tg3_rx_prodring_free(tp, tpr);
6333 static void tg3_rx_prodring_fini(struct tg3 *tp,
6334 struct tg3_rx_prodring_set *tpr)
6336 kfree(tpr->rx_std_buffers);
6337 tpr->rx_std_buffers = NULL;
6338 kfree(tpr->rx_jmb_buffers);
6339 tpr->rx_jmb_buffers = NULL;
6341 dma_free_coherent(&tp->pdev->dev, TG3_RX_STD_RING_BYTES(tp),
6342 tpr->rx_std, tpr->rx_std_mapping);
6346 dma_free_coherent(&tp->pdev->dev, TG3_RX_JMB_RING_BYTES(tp),
6347 tpr->rx_jmb, tpr->rx_jmb_mapping);
6352 static int tg3_rx_prodring_init(struct tg3 *tp,
6353 struct tg3_rx_prodring_set *tpr)
6355 tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE(tp),
6357 if (!tpr->rx_std_buffers)
6360 tpr->rx_std = dma_alloc_coherent(&tp->pdev->dev,
6361 TG3_RX_STD_RING_BYTES(tp),
6362 &tpr->rx_std_mapping,
6367 if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
6368 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
6369 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE(tp),
6371 if (!tpr->rx_jmb_buffers)
6374 tpr->rx_jmb = dma_alloc_coherent(&tp->pdev->dev,
6375 TG3_RX_JMB_RING_BYTES(tp),
6376 &tpr->rx_jmb_mapping,
6385 tg3_rx_prodring_fini(tp, tpr);
6389 /* Free up pending packets in all rx/tx rings.
6391 * The chip has been shut down and the driver detached from
6392 * the networking, so no interrupts or new tx packets will
6393 * end up in the driver. tp->{tx,}lock is not held and we are not
6394 * in an interrupt context and thus may sleep.
6396 static void tg3_free_rings(struct tg3 *tp)
6400 for (j = 0; j < tp->irq_cnt; j++) {
6401 struct tg3_napi *tnapi = &tp->napi[j];
6403 tg3_rx_prodring_free(tp, &tnapi->prodring);
6405 if (!tnapi->tx_buffers)
6408 for (i = 0; i < TG3_TX_RING_SIZE; ) {
6409 struct ring_info *txp;
6410 struct sk_buff *skb;
6413 txp = &tnapi->tx_buffers[i];
6421 pci_unmap_single(tp->pdev,
6422 dma_unmap_addr(txp, mapping),
6429 for (k = 0; k < skb_shinfo(skb)->nr_frags; k++) {
6430 txp = &tnapi->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
6431 pci_unmap_page(tp->pdev,
6432 dma_unmap_addr(txp, mapping),
6433 skb_shinfo(skb)->frags[k].size,
6438 dev_kfree_skb_any(skb);
6443 /* Initialize tx/rx rings for packet processing.
6445 * The chip has been shut down and the driver detached from
6446 * the networking, so no interrupts or new tx packets will
6447 * end up in the driver. tp->{tx,}lock are held and thus
6450 static int tg3_init_rings(struct tg3 *tp)
6454 /* Free up all the SKBs. */
6457 for (i = 0; i < tp->irq_cnt; i++) {
6458 struct tg3_napi *tnapi = &tp->napi[i];
6460 tnapi->last_tag = 0;
6461 tnapi->last_irq_tag = 0;
6462 tnapi->hw_status->status = 0;
6463 tnapi->hw_status->status_tag = 0;
6464 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6469 memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
6471 tnapi->rx_rcb_ptr = 0;
6473 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
6475 if (tg3_rx_prodring_alloc(tp, &tnapi->prodring)) {
6485 * Must not be invoked with interrupt sources disabled and
6486 * the hardware shutdown down.
6488 static void tg3_free_consistent(struct tg3 *tp)
6492 for (i = 0; i < tp->irq_cnt; i++) {
6493 struct tg3_napi *tnapi = &tp->napi[i];
6495 if (tnapi->tx_ring) {
6496 dma_free_coherent(&tp->pdev->dev, TG3_TX_RING_BYTES,
6497 tnapi->tx_ring, tnapi->tx_desc_mapping);
6498 tnapi->tx_ring = NULL;
6501 kfree(tnapi->tx_buffers);
6502 tnapi->tx_buffers = NULL;
6504 if (tnapi->rx_rcb) {
6505 dma_free_coherent(&tp->pdev->dev,
6506 TG3_RX_RCB_RING_BYTES(tp),
6508 tnapi->rx_rcb_mapping);
6509 tnapi->rx_rcb = NULL;
6512 tg3_rx_prodring_fini(tp, &tnapi->prodring);
6514 if (tnapi->hw_status) {
6515 dma_free_coherent(&tp->pdev->dev, TG3_HW_STATUS_SIZE,
6517 tnapi->status_mapping);
6518 tnapi->hw_status = NULL;
6523 dma_free_coherent(&tp->pdev->dev, sizeof(struct tg3_hw_stats),
6524 tp->hw_stats, tp->stats_mapping);
6525 tp->hw_stats = NULL;
6530 * Must not be invoked with interrupt sources disabled and
6531 * the hardware shutdown down. Can sleep.
6533 static int tg3_alloc_consistent(struct tg3 *tp)
6537 tp->hw_stats = dma_alloc_coherent(&tp->pdev->dev,
6538 sizeof(struct tg3_hw_stats),
6544 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6546 for (i = 0; i < tp->irq_cnt; i++) {
6547 struct tg3_napi *tnapi = &tp->napi[i];
6548 struct tg3_hw_status *sblk;
6550 tnapi->hw_status = dma_alloc_coherent(&tp->pdev->dev,
6552 &tnapi->status_mapping,
6554 if (!tnapi->hw_status)
6557 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6558 sblk = tnapi->hw_status;
6560 if (tg3_rx_prodring_init(tp, &tnapi->prodring))
6563 /* If multivector TSS is enabled, vector 0 does not handle
6564 * tx interrupts. Don't allocate any resources for it.
6566 if ((!i && !(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) ||
6567 (i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))) {
6568 tnapi->tx_buffers = kzalloc(sizeof(struct ring_info) *
6571 if (!tnapi->tx_buffers)
6574 tnapi->tx_ring = dma_alloc_coherent(&tp->pdev->dev,
6576 &tnapi->tx_desc_mapping,
6578 if (!tnapi->tx_ring)
6583 * When RSS is enabled, the status block format changes
6584 * slightly. The "rx_jumbo_consumer", "reserved",
6585 * and "rx_mini_consumer" members get mapped to the
6586 * other three rx return ring producer indexes.
6590 tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
6593 tnapi->rx_rcb_prod_idx = &sblk->rx_jumbo_consumer;
6596 tnapi->rx_rcb_prod_idx = &sblk->reserved;
6599 tnapi->rx_rcb_prod_idx = &sblk->rx_mini_consumer;
6604 * If multivector RSS is enabled, vector 0 does not handle
6605 * rx or tx interrupts. Don't allocate any resources for it.
6607 if (!i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS))
6610 tnapi->rx_rcb = dma_alloc_coherent(&tp->pdev->dev,
6611 TG3_RX_RCB_RING_BYTES(tp),
6612 &tnapi->rx_rcb_mapping,
6617 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
6623 tg3_free_consistent(tp);
6627 #define MAX_WAIT_CNT 1000
6629 /* To stop a block, clear the enable bit and poll till it
6630 * clears. tp->lock is held.
6632 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
6637 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6644 /* We can't enable/disable these bits of the
6645 * 5705/5750, just say success.
6658 for (i = 0; i < MAX_WAIT_CNT; i++) {
6661 if ((val & enable_bit) == 0)
6665 if (i == MAX_WAIT_CNT && !silent) {
6666 dev_err(&tp->pdev->dev,
6667 "tg3_stop_block timed out, ofs=%lx enable_bit=%x\n",
6675 /* tp->lock is held. */
6676 static int tg3_abort_hw(struct tg3 *tp, int silent)
6680 tg3_disable_ints(tp);
6682 tp->rx_mode &= ~RX_MODE_ENABLE;
6683 tw32_f(MAC_RX_MODE, tp->rx_mode);
6686 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
6687 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
6688 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
6689 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
6690 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
6691 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
6693 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
6694 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
6695 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
6696 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
6697 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
6698 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
6699 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
6701 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
6702 tw32_f(MAC_MODE, tp->mac_mode);
6705 tp->tx_mode &= ~TX_MODE_ENABLE;
6706 tw32_f(MAC_TX_MODE, tp->tx_mode);
6708 for (i = 0; i < MAX_WAIT_CNT; i++) {
6710 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
6713 if (i >= MAX_WAIT_CNT) {
6714 dev_err(&tp->pdev->dev,
6715 "%s timed out, TX_MODE_ENABLE will not clear "
6716 "MAC_TX_MODE=%08x\n", __func__, tr32(MAC_TX_MODE));
6720 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
6721 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
6722 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
6724 tw32(FTQ_RESET, 0xffffffff);
6725 tw32(FTQ_RESET, 0x00000000);
6727 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
6728 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
6730 for (i = 0; i < tp->irq_cnt; i++) {
6731 struct tg3_napi *tnapi = &tp->napi[i];
6732 if (tnapi->hw_status)
6733 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6736 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6741 static void tg3_ape_send_event(struct tg3 *tp, u32 event)
6746 /* NCSI does not support APE events */
6747 if (tp->tg3_flags3 & TG3_FLG3_APE_HAS_NCSI)
6750 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
6751 if (apedata != APE_SEG_SIG_MAGIC)
6754 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
6755 if (!(apedata & APE_FW_STATUS_READY))
6758 /* Wait for up to 1 millisecond for APE to service previous event. */
6759 for (i = 0; i < 10; i++) {
6760 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
6763 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
6765 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6766 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
6767 event | APE_EVENT_STATUS_EVENT_PENDING);
6769 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
6771 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6777 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6778 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
6781 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
6786 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
6790 case RESET_KIND_INIT:
6791 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
6792 APE_HOST_SEG_SIG_MAGIC);
6793 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
6794 APE_HOST_SEG_LEN_MAGIC);
6795 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
6796 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
6797 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
6798 APE_HOST_DRIVER_ID_MAGIC(TG3_MAJ_NUM, TG3_MIN_NUM));
6799 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
6800 APE_HOST_BEHAV_NO_PHYLOCK);
6801 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE,
6802 TG3_APE_HOST_DRVR_STATE_START);
6804 event = APE_EVENT_STATUS_STATE_START;
6806 case RESET_KIND_SHUTDOWN:
6807 /* With the interface we are currently using,
6808 * APE does not track driver state. Wiping
6809 * out the HOST SEGMENT SIGNATURE forces
6810 * the APE to assume OS absent status.
6812 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
6814 if (device_may_wakeup(&tp->pdev->dev) &&
6815 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)) {
6816 tg3_ape_write32(tp, TG3_APE_HOST_WOL_SPEED,
6817 TG3_APE_HOST_WOL_SPEED_AUTO);
6818 apedata = TG3_APE_HOST_DRVR_STATE_WOL;
6820 apedata = TG3_APE_HOST_DRVR_STATE_UNLOAD;
6822 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, apedata);
6824 event = APE_EVENT_STATUS_STATE_UNLOAD;
6826 case RESET_KIND_SUSPEND:
6827 event = APE_EVENT_STATUS_STATE_SUSPEND;
6833 event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
6835 tg3_ape_send_event(tp, event);
6838 /* tp->lock is held. */
6839 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
6841 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
6842 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
6844 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6846 case RESET_KIND_INIT:
6847 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6851 case RESET_KIND_SHUTDOWN:
6852 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6856 case RESET_KIND_SUSPEND:
6857 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6866 if (kind == RESET_KIND_INIT ||
6867 kind == RESET_KIND_SUSPEND)
6868 tg3_ape_driver_state_change(tp, kind);
6871 /* tp->lock is held. */
6872 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
6874 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6876 case RESET_KIND_INIT:
6877 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6878 DRV_STATE_START_DONE);
6881 case RESET_KIND_SHUTDOWN:
6882 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6883 DRV_STATE_UNLOAD_DONE);
6891 if (kind == RESET_KIND_SHUTDOWN)
6892 tg3_ape_driver_state_change(tp, kind);
6895 /* tp->lock is held. */
6896 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
6898 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6900 case RESET_KIND_INIT:
6901 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6905 case RESET_KIND_SHUTDOWN:
6906 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6910 case RESET_KIND_SUSPEND:
6911 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6921 static int tg3_poll_fw(struct tg3 *tp)
6926 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6927 /* Wait up to 20ms for init done. */
6928 for (i = 0; i < 200; i++) {
6929 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
6936 /* Wait for firmware initialization to complete. */
6937 for (i = 0; i < 100000; i++) {
6938 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
6939 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
6944 /* Chip might not be fitted with firmware. Some Sun onboard
6945 * parts are configured like that. So don't signal the timeout
6946 * of the above loop as an error, but do report the lack of
6947 * running firmware once.
6950 !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
6951 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
6953 netdev_info(tp->dev, "No firmware running\n");
6956 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
6957 /* The 57765 A0 needs a little more
6958 * time to do some important work.
6966 /* Save PCI command register before chip reset */
6967 static void tg3_save_pci_state(struct tg3 *tp)
6969 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
6972 /* Restore PCI state after chip reset */
6973 static void tg3_restore_pci_state(struct tg3 *tp)
6977 /* Re-enable indirect register accesses. */
6978 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
6979 tp->misc_host_ctrl);
6981 /* Set MAX PCI retry to zero. */
6982 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
6983 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6984 (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
6985 val |= PCISTATE_RETRY_SAME_DMA;
6986 /* Allow reads and writes to the APE register and memory space. */
6987 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
6988 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6989 PCISTATE_ALLOW_APE_SHMEM_WR |
6990 PCISTATE_ALLOW_APE_PSPACE_WR;
6991 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
6993 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
6995 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
6996 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6997 pcie_set_readrq(tp->pdev, tp->pcie_readrq);
6999 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
7000 tp->pci_cacheline_sz);
7001 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
7006 /* Make sure PCI-X relaxed ordering bit is clear. */
7007 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
7010 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7012 pcix_cmd &= ~PCI_X_CMD_ERO;
7013 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7017 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
7019 /* Chip reset on 5780 will reset MSI enable bit,
7020 * so need to restore it.
7022 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7025 pci_read_config_word(tp->pdev,
7026 tp->msi_cap + PCI_MSI_FLAGS,
7028 pci_write_config_word(tp->pdev,
7029 tp->msi_cap + PCI_MSI_FLAGS,
7030 ctrl | PCI_MSI_FLAGS_ENABLE);
7031 val = tr32(MSGINT_MODE);
7032 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
7037 static void tg3_stop_fw(struct tg3 *);
7039 /* tp->lock is held. */
7040 static int tg3_chip_reset(struct tg3 *tp)
7043 void (*write_op)(struct tg3 *, u32, u32);
7048 tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
7050 /* No matching tg3_nvram_unlock() after this because
7051 * chip reset below will undo the nvram lock.
7053 tp->nvram_lock_cnt = 0;
7055 /* GRC_MISC_CFG core clock reset will clear the memory
7056 * enable bit in PCI register 4 and the MSI enable bit
7057 * on some chips, so we save relevant registers here.
7059 tg3_save_pci_state(tp);
7061 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
7062 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
7063 tw32(GRC_FASTBOOT_PC, 0);
7066 * We must avoid the readl() that normally takes place.
7067 * It locks machines, causes machine checks, and other
7068 * fun things. So, temporarily disable the 5701
7069 * hardware workaround, while we do the reset.
7071 write_op = tp->write32;
7072 if (write_op == tg3_write_flush_reg32)
7073 tp->write32 = tg3_write32;
7075 /* Prevent the irq handler from reading or writing PCI registers
7076 * during chip reset when the memory enable bit in the PCI command
7077 * register may be cleared. The chip does not generate interrupt
7078 * at this time, but the irq handler may still be called due to irq
7079 * sharing or irqpoll.
7081 tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
7082 for (i = 0; i < tp->irq_cnt; i++) {
7083 struct tg3_napi *tnapi = &tp->napi[i];
7084 if (tnapi->hw_status) {
7085 tnapi->hw_status->status = 0;
7086 tnapi->hw_status->status_tag = 0;
7088 tnapi->last_tag = 0;
7089 tnapi->last_irq_tag = 0;
7093 for (i = 0; i < tp->irq_cnt; i++)
7094 synchronize_irq(tp->napi[i].irq_vec);
7096 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7097 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
7098 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
7102 val = GRC_MISC_CFG_CORECLK_RESET;
7104 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
7105 /* Force PCIe 1.0a mode */
7106 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
7107 !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
7108 tr32(TG3_PCIE_PHY_TSTCTL) ==
7109 (TG3_PCIE_PHY_TSTCTL_PCIE10 | TG3_PCIE_PHY_TSTCTL_PSCRAM))
7110 tw32(TG3_PCIE_PHY_TSTCTL, TG3_PCIE_PHY_TSTCTL_PSCRAM);
7112 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
7113 tw32(GRC_MISC_CFG, (1 << 29));
7118 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7119 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
7120 tw32(GRC_VCPU_EXT_CTRL,
7121 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
7124 /* Manage gphy power for all CPMU absent PCIe devices. */
7125 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7126 !(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT))
7127 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
7129 tw32(GRC_MISC_CFG, val);
7131 /* restore 5701 hardware bug workaround write method */
7132 tp->write32 = write_op;
7134 /* Unfortunately, we have to delay before the PCI read back.
7135 * Some 575X chips even will not respond to a PCI cfg access
7136 * when the reset command is given to the chip.
7138 * How do these hardware designers expect things to work
7139 * properly if the PCI write is posted for a long period
7140 * of time? It is always necessary to have some method by
7141 * which a register read back can occur to push the write
7142 * out which does the reset.
7144 * For most tg3 variants the trick below was working.
7149 /* Flush PCI posted writes. The normal MMIO registers
7150 * are inaccessible at this time so this is the only
7151 * way to make this reliably (actually, this is no longer
7152 * the case, see above). I tried to use indirect
7153 * register read/write but this upset some 5701 variants.
7155 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
7159 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
7162 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
7166 /* Wait for link training to complete. */
7167 for (i = 0; i < 5000; i++)
7170 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
7171 pci_write_config_dword(tp->pdev, 0xc4,
7172 cfg_val | (1 << 15));
7175 /* Clear the "no snoop" and "relaxed ordering" bits. */
7176 pci_read_config_word(tp->pdev,
7177 tp->pcie_cap + PCI_EXP_DEVCTL,
7179 val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
7180 PCI_EXP_DEVCTL_NOSNOOP_EN);
7182 * Older PCIe devices only support the 128 byte
7183 * MPS setting. Enforce the restriction.
7185 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT))
7186 val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
7187 pci_write_config_word(tp->pdev,
7188 tp->pcie_cap + PCI_EXP_DEVCTL,
7191 pcie_set_readrq(tp->pdev, tp->pcie_readrq);
7193 /* Clear error status */
7194 pci_write_config_word(tp->pdev,
7195 tp->pcie_cap + PCI_EXP_DEVSTA,
7196 PCI_EXP_DEVSTA_CED |
7197 PCI_EXP_DEVSTA_NFED |
7198 PCI_EXP_DEVSTA_FED |
7199 PCI_EXP_DEVSTA_URD);
7202 tg3_restore_pci_state(tp);
7204 tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
7207 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
7208 val = tr32(MEMARB_MODE);
7209 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
7211 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
7213 tw32(0x5000, 0x400);
7216 tw32(GRC_MODE, tp->grc_mode);
7218 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
7221 tw32(0xc4, val | (1 << 15));
7224 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
7225 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7226 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
7227 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
7228 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
7229 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7232 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7233 tp->mac_mode = MAC_MODE_APE_TX_EN |
7234 MAC_MODE_APE_RX_EN |
7235 MAC_MODE_TDE_ENABLE;
7237 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
7238 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
7240 } else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
7241 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
7246 tw32_f(MAC_MODE, val);
7249 tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
7251 err = tg3_poll_fw(tp);
7257 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
7258 tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
7259 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
7260 !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) {
7263 tw32(0x7c00, val | (1 << 25));
7266 /* Reprobe ASF enable state. */
7267 tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
7268 tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
7269 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
7270 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
7273 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
7274 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
7275 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
7276 tp->last_event_jiffies = jiffies;
7277 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
7278 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
7285 /* tp->lock is held. */
7286 static void tg3_stop_fw(struct tg3 *tp)
7288 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
7289 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7290 /* Wait for RX cpu to ACK the previous event. */
7291 tg3_wait_for_event_ack(tp);
7293 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
7295 tg3_generate_fw_event(tp);
7297 /* Wait for RX cpu to ACK this event. */
7298 tg3_wait_for_event_ack(tp);
7302 /* tp->lock is held. */
7303 static int tg3_halt(struct tg3 *tp, int kind, int silent)
7309 tg3_write_sig_pre_reset(tp, kind);
7311 tg3_abort_hw(tp, silent);
7312 err = tg3_chip_reset(tp);
7314 __tg3_set_mac_addr(tp, 0);
7316 tg3_write_sig_legacy(tp, kind);
7317 tg3_write_sig_post_reset(tp, kind);
7325 #define RX_CPU_SCRATCH_BASE 0x30000
7326 #define RX_CPU_SCRATCH_SIZE 0x04000
7327 #define TX_CPU_SCRATCH_BASE 0x34000
7328 #define TX_CPU_SCRATCH_SIZE 0x04000
7330 /* tp->lock is held. */
7331 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
7335 BUG_ON(offset == TX_CPU_BASE &&
7336 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
7338 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7339 u32 val = tr32(GRC_VCPU_EXT_CTRL);
7341 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
7344 if (offset == RX_CPU_BASE) {
7345 for (i = 0; i < 10000; i++) {
7346 tw32(offset + CPU_STATE, 0xffffffff);
7347 tw32(offset + CPU_MODE, CPU_MODE_HALT);
7348 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7352 tw32(offset + CPU_STATE, 0xffffffff);
7353 tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
7356 for (i = 0; i < 10000; i++) {
7357 tw32(offset + CPU_STATE, 0xffffffff);
7358 tw32(offset + CPU_MODE, CPU_MODE_HALT);
7359 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7365 netdev_err(tp->dev, "%s timed out, %s CPU\n",
7366 __func__, offset == RX_CPU_BASE ? "RX" : "TX");
7370 /* Clear firmware's nvram arbitration. */
7371 if (tp->tg3_flags & TG3_FLAG_NVRAM)
7372 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
7377 unsigned int fw_base;
7378 unsigned int fw_len;
7379 const __be32 *fw_data;
7382 /* tp->lock is held. */
7383 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
7384 int cpu_scratch_size, struct fw_info *info)
7386 int err, lock_err, i;
7387 void (*write_op)(struct tg3 *, u32, u32);
7389 if (cpu_base == TX_CPU_BASE &&
7390 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7392 "%s: Trying to load TX cpu firmware which is 5705\n",
7397 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7398 write_op = tg3_write_mem;
7400 write_op = tg3_write_indirect_reg32;
7402 /* It is possible that bootcode is still loading at this point.
7403 * Get the nvram lock first before halting the cpu.
7405 lock_err = tg3_nvram_lock(tp);
7406 err = tg3_halt_cpu(tp, cpu_base);
7408 tg3_nvram_unlock(tp);
7412 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
7413 write_op(tp, cpu_scratch_base + i, 0);
7414 tw32(cpu_base + CPU_STATE, 0xffffffff);
7415 tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
7416 for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
7417 write_op(tp, (cpu_scratch_base +
7418 (info->fw_base & 0xffff) +
7420 be32_to_cpu(info->fw_data[i]));
7428 /* tp->lock is held. */
7429 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
7431 struct fw_info info;
7432 const __be32 *fw_data;
7435 fw_data = (void *)tp->fw->data;
7437 /* Firmware blob starts with version numbers, followed by
7438 start address and length. We are setting complete length.
7439 length = end_address_of_bss - start_address_of_text.
7440 Remainder is the blob to be loaded contiguously
7441 from start address. */
7443 info.fw_base = be32_to_cpu(fw_data[1]);
7444 info.fw_len = tp->fw->size - 12;
7445 info.fw_data = &fw_data[3];
7447 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
7448 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
7453 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
7454 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
7459 /* Now startup only the RX cpu. */
7460 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7461 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
7463 for (i = 0; i < 5; i++) {
7464 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
7466 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7467 tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
7468 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
7472 netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x "
7473 "should be %08x\n", __func__,
7474 tr32(RX_CPU_BASE + CPU_PC), info.fw_base);
7477 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7478 tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
7483 /* 5705 needs a special version of the TSO firmware. */
7485 /* tp->lock is held. */
7486 static int tg3_load_tso_firmware(struct tg3 *tp)
7488 struct fw_info info;
7489 const __be32 *fw_data;
7490 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
7493 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7496 fw_data = (void *)tp->fw->data;
7498 /* Firmware blob starts with version numbers, followed by
7499 start address and length. We are setting complete length.
7500 length = end_address_of_bss - start_address_of_text.
7501 Remainder is the blob to be loaded contiguously
7502 from start address. */
7504 info.fw_base = be32_to_cpu(fw_data[1]);
7505 cpu_scratch_size = tp->fw_len;
7506 info.fw_len = tp->fw->size - 12;
7507 info.fw_data = &fw_data[3];
7509 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7510 cpu_base = RX_CPU_BASE;
7511 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
7513 cpu_base = TX_CPU_BASE;
7514 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
7515 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
7518 err = tg3_load_firmware_cpu(tp, cpu_base,
7519 cpu_scratch_base, cpu_scratch_size,
7524 /* Now startup the cpu. */
7525 tw32(cpu_base + CPU_STATE, 0xffffffff);
7526 tw32_f(cpu_base + CPU_PC, info.fw_base);
7528 for (i = 0; i < 5; i++) {
7529 if (tr32(cpu_base + CPU_PC) == info.fw_base)
7531 tw32(cpu_base + CPU_STATE, 0xffffffff);
7532 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
7533 tw32_f(cpu_base + CPU_PC, info.fw_base);
7538 "%s fails to set CPU PC, is %08x should be %08x\n",
7539 __func__, tr32(cpu_base + CPU_PC), info.fw_base);
7542 tw32(cpu_base + CPU_STATE, 0xffffffff);
7543 tw32_f(cpu_base + CPU_MODE, 0x00000000);
7548 static int tg3_set_mac_addr(struct net_device *dev, void *p)
7550 struct tg3 *tp = netdev_priv(dev);
7551 struct sockaddr *addr = p;
7552 int err = 0, skip_mac_1 = 0;
7554 if (!is_valid_ether_addr(addr->sa_data))
7557 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
7559 if (!netif_running(dev))
7562 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
7563 u32 addr0_high, addr0_low, addr1_high, addr1_low;
7565 addr0_high = tr32(MAC_ADDR_0_HIGH);
7566 addr0_low = tr32(MAC_ADDR_0_LOW);
7567 addr1_high = tr32(MAC_ADDR_1_HIGH);
7568 addr1_low = tr32(MAC_ADDR_1_LOW);
7570 /* Skip MAC addr 1 if ASF is using it. */
7571 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
7572 !(addr1_high == 0 && addr1_low == 0))
7575 spin_lock_bh(&tp->lock);
7576 __tg3_set_mac_addr(tp, skip_mac_1);
7577 spin_unlock_bh(&tp->lock);
7582 /* tp->lock is held. */
7583 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
7584 dma_addr_t mapping, u32 maxlen_flags,
7588 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
7589 ((u64) mapping >> 32));
7591 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
7592 ((u64) mapping & 0xffffffff));
7594 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
7597 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7599 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
7603 static void __tg3_set_rx_mode(struct net_device *);
7604 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
7608 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) {
7609 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
7610 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
7611 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
7613 tw32(HOSTCC_TXCOL_TICKS, 0);
7614 tw32(HOSTCC_TXMAX_FRAMES, 0);
7615 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
7618 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) {
7619 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
7620 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
7621 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
7623 tw32(HOSTCC_RXCOL_TICKS, 0);
7624 tw32(HOSTCC_RXMAX_FRAMES, 0);
7625 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
7628 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7629 u32 val = ec->stats_block_coalesce_usecs;
7631 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
7632 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
7634 if (!netif_carrier_ok(tp->dev))
7637 tw32(HOSTCC_STAT_COAL_TICKS, val);
7640 for (i = 0; i < tp->irq_cnt - 1; i++) {
7643 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
7644 tw32(reg, ec->rx_coalesce_usecs);
7645 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
7646 tw32(reg, ec->rx_max_coalesced_frames);
7647 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
7648 tw32(reg, ec->rx_max_coalesced_frames_irq);
7650 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7651 reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
7652 tw32(reg, ec->tx_coalesce_usecs);
7653 reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
7654 tw32(reg, ec->tx_max_coalesced_frames);
7655 reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
7656 tw32(reg, ec->tx_max_coalesced_frames_irq);
7660 for (; i < tp->irq_max - 1; i++) {
7661 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
7662 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
7663 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7665 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7666 tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
7667 tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
7668 tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7673 /* tp->lock is held. */
7674 static void tg3_rings_reset(struct tg3 *tp)
7677 u32 stblk, txrcb, rxrcb, limit;
7678 struct tg3_napi *tnapi = &tp->napi[0];
7680 /* Disable all transmit rings but the first. */
7681 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7682 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
7683 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7684 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
7685 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 4;
7686 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7687 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2;
7689 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7691 for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7692 txrcb < limit; txrcb += TG3_BDINFO_SIZE)
7693 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
7694 BDINFO_FLAGS_DISABLED);
7697 /* Disable all receive return rings but the first. */
7698 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7699 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
7700 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
7701 else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7702 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
7703 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
7704 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7705 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
7707 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7709 for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7710 rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
7711 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
7712 BDINFO_FLAGS_DISABLED);
7714 /* Disable interrupts */
7715 tw32_mailbox_f(tp->napi[0].int_mbox, 1);
7717 /* Zero mailbox registers. */
7718 if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) {
7719 for (i = 1; i < tp->irq_max; i++) {
7720 tp->napi[i].tx_prod = 0;
7721 tp->napi[i].tx_cons = 0;
7722 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
7723 tw32_mailbox(tp->napi[i].prodmbox, 0);
7724 tw32_rx_mbox(tp->napi[i].consmbox, 0);
7725 tw32_mailbox_f(tp->napi[i].int_mbox, 1);
7727 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))
7728 tw32_mailbox(tp->napi[0].prodmbox, 0);
7730 tp->napi[0].tx_prod = 0;
7731 tp->napi[0].tx_cons = 0;
7732 tw32_mailbox(tp->napi[0].prodmbox, 0);
7733 tw32_rx_mbox(tp->napi[0].consmbox, 0);
7736 /* Make sure the NIC-based send BD rings are disabled. */
7737 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7738 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
7739 for (i = 0; i < 16; i++)
7740 tw32_tx_mbox(mbox + i * 8, 0);
7743 txrcb = NIC_SRAM_SEND_RCB;
7744 rxrcb = NIC_SRAM_RCV_RET_RCB;
7746 /* Clear status block in ram. */
7747 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7749 /* Set status block DMA address */
7750 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7751 ((u64) tnapi->status_mapping >> 32));
7752 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7753 ((u64) tnapi->status_mapping & 0xffffffff));
7755 if (tnapi->tx_ring) {
7756 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7757 (TG3_TX_RING_SIZE <<
7758 BDINFO_FLAGS_MAXLEN_SHIFT),
7759 NIC_SRAM_TX_BUFFER_DESC);
7760 txrcb += TG3_BDINFO_SIZE;
7763 if (tnapi->rx_rcb) {
7764 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7765 (tp->rx_ret_ring_mask + 1) <<
7766 BDINFO_FLAGS_MAXLEN_SHIFT, 0);
7767 rxrcb += TG3_BDINFO_SIZE;
7770 stblk = HOSTCC_STATBLCK_RING1;
7772 for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
7773 u64 mapping = (u64)tnapi->status_mapping;
7774 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
7775 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
7777 /* Clear status block in ram. */
7778 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7780 if (tnapi->tx_ring) {
7781 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7782 (TG3_TX_RING_SIZE <<
7783 BDINFO_FLAGS_MAXLEN_SHIFT),
7784 NIC_SRAM_TX_BUFFER_DESC);
7785 txrcb += TG3_BDINFO_SIZE;
7788 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7789 ((tp->rx_ret_ring_mask + 1) <<
7790 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7793 rxrcb += TG3_BDINFO_SIZE;
7797 /* tp->lock is held. */
7798 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
7800 u32 val, rdmac_mode;
7802 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
7804 tg3_disable_ints(tp);
7808 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
7810 if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)
7811 tg3_abort_hw(tp, 1);
7813 /* Enable MAC control of LPI */
7814 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) {
7815 tw32_f(TG3_CPMU_EEE_LNKIDL_CTRL,
7816 TG3_CPMU_EEE_LNKIDL_PCIE_NL0 |
7817 TG3_CPMU_EEE_LNKIDL_UART_IDL);
7819 tw32_f(TG3_CPMU_EEE_CTRL,
7820 TG3_CPMU_EEE_CTRL_EXIT_20_1_US);
7822 val = TG3_CPMU_EEEMD_ERLY_L1_XIT_DET |
7823 TG3_CPMU_EEEMD_LPI_IN_TX |
7824 TG3_CPMU_EEEMD_LPI_IN_RX |
7825 TG3_CPMU_EEEMD_EEE_ENABLE;
7827 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717)
7828 val |= TG3_CPMU_EEEMD_SND_IDX_DET_EN;
7830 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7831 val |= TG3_CPMU_EEEMD_APE_TX_DET_EN;
7833 tw32_f(TG3_CPMU_EEE_MODE, val);
7835 tw32_f(TG3_CPMU_EEE_DBTMR1,
7836 TG3_CPMU_DBTMR1_PCIEXIT_2047US |
7837 TG3_CPMU_DBTMR1_LNKIDLE_2047US);
7839 tw32_f(TG3_CPMU_EEE_DBTMR2,
7840 TG3_CPMU_DBTMR1_APE_TX_2047US |
7841 TG3_CPMU_DBTMR2_TXIDXEQ_2047US);
7847 err = tg3_chip_reset(tp);
7851 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
7853 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
7854 val = tr32(TG3_CPMU_CTRL);
7855 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
7856 tw32(TG3_CPMU_CTRL, val);
7858 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7859 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7860 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7861 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7863 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
7864 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
7865 val |= CPMU_LNK_AWARE_MACCLK_6_25;
7866 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
7868 val = tr32(TG3_CPMU_HST_ACC);
7869 val &= ~CPMU_HST_ACC_MACCLK_MASK;
7870 val |= CPMU_HST_ACC_MACCLK_6_25;
7871 tw32(TG3_CPMU_HST_ACC, val);
7874 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7875 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
7876 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
7877 PCIE_PWR_MGMT_L1_THRESH_4MS;
7878 tw32(PCIE_PWR_MGMT_THRESH, val);
7880 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
7881 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
7883 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
7885 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
7886 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
7889 if (tp->tg3_flags3 & TG3_FLG3_L1PLLPD_EN) {
7890 u32 grc_mode = tr32(GRC_MODE);
7892 /* Access the lower 1K of PL PCIE block registers. */
7893 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
7894 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
7896 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1);
7897 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1,
7898 val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN);
7900 tw32(GRC_MODE, grc_mode);
7903 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
7904 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
7905 u32 grc_mode = tr32(GRC_MODE);
7907 /* Access the lower 1K of PL PCIE block registers. */
7908 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
7909 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
7911 val = tr32(TG3_PCIE_TLDLPL_PORT +
7912 TG3_PCIE_PL_LO_PHYCTL5);
7913 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5,
7914 val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ);
7916 tw32(GRC_MODE, grc_mode);
7919 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7920 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7921 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7922 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7925 /* This works around an issue with Athlon chipsets on
7926 * B3 tigon3 silicon. This bit has no effect on any
7927 * other revision. But do not set this on PCI Express
7928 * chips and don't even touch the clocks if the CPMU is present.
7930 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
7931 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
7932 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
7933 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7936 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
7937 (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
7938 val = tr32(TG3PCI_PCISTATE);
7939 val |= PCISTATE_RETRY_SAME_DMA;
7940 tw32(TG3PCI_PCISTATE, val);
7943 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
7944 /* Allow reads and writes to the
7945 * APE register and memory space.
7947 val = tr32(TG3PCI_PCISTATE);
7948 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
7949 PCISTATE_ALLOW_APE_SHMEM_WR |
7950 PCISTATE_ALLOW_APE_PSPACE_WR;
7951 tw32(TG3PCI_PCISTATE, val);
7954 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
7955 /* Enable some hw fixes. */
7956 val = tr32(TG3PCI_MSI_DATA);
7957 val |= (1 << 26) | (1 << 28) | (1 << 29);
7958 tw32(TG3PCI_MSI_DATA, val);
7961 /* Descriptor ring init may make accesses to the
7962 * NIC SRAM area to setup the TX descriptors, so we
7963 * can only do this after the hardware has been
7964 * successfully reset.
7966 err = tg3_init_rings(tp);
7970 if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
7971 val = tr32(TG3PCI_DMA_RW_CTRL) &
7972 ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
7973 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0)
7974 val &= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK;
7975 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
7976 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
7977 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
7978 /* This value is determined during the probe time DMA
7979 * engine test, tg3_test_dma.
7981 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
7984 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
7985 GRC_MODE_4X_NIC_SEND_RINGS |
7986 GRC_MODE_NO_TX_PHDR_CSUM |
7987 GRC_MODE_NO_RX_PHDR_CSUM);
7988 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
7990 /* Pseudo-header checksum is done by hardware logic and not
7991 * the offload processers, so make the chip do the pseudo-
7992 * header checksums on receive. For transmit it is more
7993 * convenient to do the pseudo-header checksum in software
7994 * as Linux does that on transmit for us in all cases.
7996 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
8000 (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
8002 /* Setup the timer prescalar register. Clock is always 66Mhz. */
8003 val = tr32(GRC_MISC_CFG);
8005 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
8006 tw32(GRC_MISC_CFG, val);
8008 /* Initialize MBUF/DESC pool. */
8009 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
8011 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
8012 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
8013 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
8014 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
8016 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
8017 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
8018 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
8019 } else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
8022 fw_len = tp->fw_len;
8023 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
8024 tw32(BUFMGR_MB_POOL_ADDR,
8025 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
8026 tw32(BUFMGR_MB_POOL_SIZE,
8027 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
8030 if (tp->dev->mtu <= ETH_DATA_LEN) {
8031 tw32(BUFMGR_MB_RDMA_LOW_WATER,
8032 tp->bufmgr_config.mbuf_read_dma_low_water);
8033 tw32(BUFMGR_MB_MACRX_LOW_WATER,
8034 tp->bufmgr_config.mbuf_mac_rx_low_water);
8035 tw32(BUFMGR_MB_HIGH_WATER,
8036 tp->bufmgr_config.mbuf_high_water);
8038 tw32(BUFMGR_MB_RDMA_LOW_WATER,
8039 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
8040 tw32(BUFMGR_MB_MACRX_LOW_WATER,
8041 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
8042 tw32(BUFMGR_MB_HIGH_WATER,
8043 tp->bufmgr_config.mbuf_high_water_jumbo);
8045 tw32(BUFMGR_DMA_LOW_WATER,
8046 tp->bufmgr_config.dma_low_water);
8047 tw32(BUFMGR_DMA_HIGH_WATER,
8048 tp->bufmgr_config.dma_high_water);
8050 val = BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE;
8051 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
8052 val |= BUFMGR_MODE_NO_TX_UNDERRUN;
8053 tw32(BUFMGR_MODE, val);
8054 for (i = 0; i < 2000; i++) {
8055 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
8060 netdev_err(tp->dev, "%s cannot enable BUFMGR\n", __func__);
8064 /* Setup replenish threshold. */
8065 val = tp->rx_pending / 8;
8068 else if (val > tp->rx_std_max_post)
8069 val = tp->rx_std_max_post;
8070 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
8071 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
8072 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
8074 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
8075 val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
8078 tw32(RCVBDI_STD_THRESH, val);
8080 /* Initialize TG3_BDINFO's at:
8081 * RCVDBDI_STD_BD: standard eth size rx ring
8082 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
8083 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
8086 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
8087 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
8088 * ring attribute flags
8089 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
8091 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
8092 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
8094 * The size of each ring is fixed in the firmware, but the location is
8097 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
8098 ((u64) tpr->rx_std_mapping >> 32));
8099 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
8100 ((u64) tpr->rx_std_mapping & 0xffffffff));
8101 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
8102 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5719)
8103 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
8104 NIC_SRAM_RX_BUFFER_DESC);
8106 /* Disable the mini ring */
8107 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8108 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
8109 BDINFO_FLAGS_DISABLED);
8111 /* Program the jumbo buffer descriptor ring control
8112 * blocks on those devices that have them.
8114 if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
8115 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
8116 /* Setup replenish threshold. */
8117 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
8119 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
8120 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
8121 ((u64) tpr->rx_jmb_mapping >> 32));
8122 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
8123 ((u64) tpr->rx_jmb_mapping & 0xffffffff));
8124 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
8125 (RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT) |
8126 BDINFO_FLAGS_USE_EXT_RECV);
8127 if (!(tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) ||
8128 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
8129 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
8130 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
8132 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
8133 BDINFO_FLAGS_DISABLED);
8136 if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
8137 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
8138 val = RX_STD_MAX_SIZE_5705;
8140 val = RX_STD_MAX_SIZE_5717;
8141 val <<= BDINFO_FLAGS_MAXLEN_SHIFT;
8142 val |= (TG3_RX_STD_DMA_SZ << 2);
8144 val = TG3_RX_STD_DMA_SZ << BDINFO_FLAGS_MAXLEN_SHIFT;
8146 val = RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT;
8148 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
8150 tpr->rx_std_prod_idx = tp->rx_pending;
8151 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx);
8153 tpr->rx_jmb_prod_idx = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
8154 tp->rx_jumbo_pending : 0;
8155 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx);
8157 if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
8158 tw32(STD_REPLENISH_LWM, 32);
8159 tw32(JMB_REPLENISH_LWM, 16);
8162 tg3_rings_reset(tp);
8164 /* Initialize MAC address and backoff seed. */
8165 __tg3_set_mac_addr(tp, 0);
8167 /* MTU + ethernet header + FCS + optional VLAN tag */
8168 tw32(MAC_RX_MTU_SIZE,
8169 tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
8171 /* The slot time is changed by tg3_setup_phy if we
8172 * run at gigabit with half duplex.
8174 tw32(MAC_TX_LENGTHS,
8175 (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
8176 (6 << TX_LENGTHS_IPG_SHIFT) |
8177 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
8179 /* Receive rules. */
8180 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
8181 tw32(RCVLPC_CONFIG, 0x0181);
8183 /* Calculate RDMAC_MODE setting early, we need it to determine
8184 * the RCVLPC_STATE_ENABLE mask.
8186 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
8187 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
8188 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
8189 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
8190 RDMAC_MODE_LNGREAD_ENAB);
8192 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
8193 rdmac_mode |= RDMAC_MODE_MULT_DMA_RD_DIS;
8195 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
8196 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8197 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
8198 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
8199 RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
8200 RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
8202 /* If statement applies to 5705 and 5750 PCI devices only */
8203 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
8204 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
8205 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
8206 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
8207 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
8208 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
8209 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
8210 !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
8211 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
8215 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
8216 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
8218 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
8219 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
8221 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
8222 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8223 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
8224 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
8226 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
8227 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
8228 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8229 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
8230 (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) {
8231 val = tr32(TG3_RDMA_RSRVCTRL_REG);
8232 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
8233 val &= ~TG3_RDMA_RSRVCTRL_TXMRGN_MASK;
8234 val |= TG3_RDMA_RSRVCTRL_TXMRGN_320B;
8236 tw32(TG3_RDMA_RSRVCTRL_REG,
8237 val | TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
8240 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
8241 val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);
8242 tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val |
8243 TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_BD_4K |
8244 TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_LSO_4K);
8247 /* Receive/send statistics. */
8248 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
8249 val = tr32(RCVLPC_STATS_ENABLE);
8250 val &= ~RCVLPC_STATSENAB_DACK_FIX;
8251 tw32(RCVLPC_STATS_ENABLE, val);
8252 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
8253 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8254 val = tr32(RCVLPC_STATS_ENABLE);
8255 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
8256 tw32(RCVLPC_STATS_ENABLE, val);
8258 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
8260 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
8261 tw32(SNDDATAI_STATSENAB, 0xffffff);
8262 tw32(SNDDATAI_STATSCTRL,
8263 (SNDDATAI_SCTRL_ENABLE |
8264 SNDDATAI_SCTRL_FASTUPD));
8266 /* Setup host coalescing engine. */
8267 tw32(HOSTCC_MODE, 0);
8268 for (i = 0; i < 2000; i++) {
8269 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
8274 __tg3_set_coalesce(tp, &tp->coal);
8276 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
8277 /* Status/statistics block address. See tg3_timer,
8278 * the tg3_periodic_fetch_stats call there, and
8279 * tg3_get_stats to see how this works for 5705/5750 chips.
8281 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
8282 ((u64) tp->stats_mapping >> 32));
8283 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
8284 ((u64) tp->stats_mapping & 0xffffffff));
8285 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
8287 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
8289 /* Clear statistics and status block memory areas */
8290 for (i = NIC_SRAM_STATS_BLK;
8291 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
8293 tg3_write_mem(tp, i, 0);
8298 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
8300 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
8301 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
8302 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8303 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
8305 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
8306 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
8307 /* reset to prevent losing 1st rx packet intermittently */
8308 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8312 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
8313 tp->mac_mode = MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
8316 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
8317 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
8318 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
8319 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
8320 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
8321 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
8322 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
8325 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
8326 * If TG3_FLG2_IS_NIC is zero, we should read the
8327 * register to preserve the GPIO settings for LOMs. The GPIOs,
8328 * whether used as inputs or outputs, are set by boot code after
8331 if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
8334 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
8335 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
8336 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
8338 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
8339 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
8340 GRC_LCLCTRL_GPIO_OUTPUT3;
8342 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
8343 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
8345 tp->grc_local_ctrl &= ~gpio_mask;
8346 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
8348 /* GPIO1 must be driven high for eeprom write protect */
8349 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
8350 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
8351 GRC_LCLCTRL_GPIO_OUTPUT1);
8353 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8356 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX) {
8357 val = tr32(MSGINT_MODE);
8358 val |= MSGINT_MODE_MULTIVEC_EN | MSGINT_MODE_ENABLE;
8359 tw32(MSGINT_MODE, val);
8362 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
8363 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
8367 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
8368 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
8369 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
8370 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
8371 WDMAC_MODE_LNGREAD_ENAB);
8373 /* If statement applies to 5705 and 5750 PCI devices only */
8374 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
8375 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
8376 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
8377 if ((tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
8378 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
8379 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
8381 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
8382 !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
8383 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
8384 val |= WDMAC_MODE_RX_ACCEL;
8388 /* Enable host coalescing bug fix */
8389 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
8390 val |= WDMAC_MODE_STATUS_TAG_FIX;
8392 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
8393 val |= WDMAC_MODE_BURST_ALL_DATA;
8395 tw32_f(WDMAC_MODE, val);
8398 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
8401 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8403 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
8404 pcix_cmd &= ~PCI_X_CMD_MAX_READ;
8405 pcix_cmd |= PCI_X_CMD_READ_2K;
8406 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
8407 pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
8408 pcix_cmd |= PCI_X_CMD_READ_2K;
8410 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8414 tw32_f(RDMAC_MODE, rdmac_mode);
8417 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
8418 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8419 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
8421 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
8423 SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
8425 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
8427 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
8428 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
8429 val = RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ;
8430 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
8431 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
8432 val |= RCVDBDI_MODE_LRG_RING_SZ;
8433 tw32(RCVDBDI_MODE, val);
8434 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
8435 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
8436 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
8437 val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
8438 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
8439 val |= SNDBDI_MODE_MULTI_TXQ_EN;
8440 tw32(SNDBDI_MODE, val);
8441 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
8443 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8444 err = tg3_load_5701_a0_firmware_fix(tp);
8449 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
8450 err = tg3_load_tso_firmware(tp);
8455 tp->tx_mode = TX_MODE_ENABLE;
8456 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
8457 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
8458 tp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX;
8459 tw32_f(MAC_TX_MODE, tp->tx_mode);
8462 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) {
8463 u32 reg = MAC_RSS_INDIR_TBL_0;
8464 u8 *ent = (u8 *)&val;
8466 /* Setup the indirection table */
8467 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
8468 int idx = i % sizeof(val);
8470 ent[idx] = i % (tp->irq_cnt - 1);
8471 if (idx == sizeof(val) - 1) {
8477 /* Setup the "secret" hash key. */
8478 tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
8479 tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
8480 tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
8481 tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
8482 tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
8483 tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
8484 tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
8485 tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
8486 tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
8487 tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
8490 tp->rx_mode = RX_MODE_ENABLE;
8491 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
8492 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
8494 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)
8495 tp->rx_mode |= RX_MODE_RSS_ENABLE |
8496 RX_MODE_RSS_ITBL_HASH_BITS_7 |
8497 RX_MODE_RSS_IPV6_HASH_EN |
8498 RX_MODE_RSS_TCP_IPV6_HASH_EN |
8499 RX_MODE_RSS_IPV4_HASH_EN |
8500 RX_MODE_RSS_TCP_IPV4_HASH_EN;
8502 tw32_f(MAC_RX_MODE, tp->rx_mode);
8505 tw32(MAC_LED_CTRL, tp->led_ctrl);
8507 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
8508 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
8509 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8512 tw32_f(MAC_RX_MODE, tp->rx_mode);
8515 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
8516 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
8517 !(tp->phy_flags & TG3_PHYFLG_SERDES_PREEMPHASIS)) {
8518 /* Set drive transmission level to 1.2V */
8519 /* only if the signal pre-emphasis bit is not set */
8520 val = tr32(MAC_SERDES_CFG);
8523 tw32(MAC_SERDES_CFG, val);
8525 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
8526 tw32(MAC_SERDES_CFG, 0x616000);
8529 /* Prevent chip from dropping frames when flow control
8532 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
8536 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val);
8538 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
8539 (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
8540 /* Use hardware link auto-negotiation */
8541 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
8544 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
8545 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
8548 tmp = tr32(SERDES_RX_CTRL);
8549 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
8550 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
8551 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
8552 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8555 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
8556 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
8557 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
8558 tp->link_config.speed = tp->link_config.orig_speed;
8559 tp->link_config.duplex = tp->link_config.orig_duplex;
8560 tp->link_config.autoneg = tp->link_config.orig_autoneg;
8563 err = tg3_setup_phy(tp, 0);
8567 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
8568 !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
8571 /* Clear CRC stats. */
8572 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
8573 tg3_writephy(tp, MII_TG3_TEST1,
8574 tmp | MII_TG3_TEST1_CRC_EN);
8575 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &tmp);
8580 __tg3_set_rx_mode(tp->dev);
8582 /* Initialize receive rules. */
8583 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
8584 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
8585 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
8586 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
8588 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
8589 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
8593 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
8597 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
8599 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
8601 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
8603 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
8605 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
8607 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
8609 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
8611 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
8613 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
8615 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
8617 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
8619 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
8621 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
8623 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
8631 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
8632 /* Write our heartbeat update interval to APE. */
8633 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
8634 APE_HOST_HEARTBEAT_INT_DISABLE);
8636 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
8641 /* Called at device open time to get the chip ready for
8642 * packet processing. Invoked with tp->lock held.
8644 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
8646 tg3_switch_clocks(tp);
8648 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
8650 return tg3_reset_hw(tp, reset_phy);
8653 #define TG3_STAT_ADD32(PSTAT, REG) \
8654 do { u32 __val = tr32(REG); \
8655 (PSTAT)->low += __val; \
8656 if ((PSTAT)->low < __val) \
8657 (PSTAT)->high += 1; \
8660 static void tg3_periodic_fetch_stats(struct tg3 *tp)
8662 struct tg3_hw_stats *sp = tp->hw_stats;
8664 if (!netif_carrier_ok(tp->dev))
8667 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
8668 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
8669 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
8670 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
8671 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
8672 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
8673 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
8674 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
8675 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
8676 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
8677 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
8678 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
8679 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
8681 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
8682 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
8683 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
8684 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
8685 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
8686 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
8687 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
8688 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
8689 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
8690 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
8691 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
8692 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
8693 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
8694 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
8696 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
8697 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
8698 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
8701 static void tg3_timer(unsigned long __opaque)
8703 struct tg3 *tp = (struct tg3 *) __opaque;
8708 spin_lock(&tp->lock);
8710 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8711 /* All of this garbage is because when using non-tagged
8712 * IRQ status the mailbox/status_block protocol the chip
8713 * uses with the cpu is race prone.
8715 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
8716 tw32(GRC_LOCAL_CTRL,
8717 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
8719 tw32(HOSTCC_MODE, tp->coalesce_mode |
8720 HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
8723 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
8724 tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
8725 spin_unlock(&tp->lock);
8726 schedule_work(&tp->reset_task);
8731 /* This part only runs once per second. */
8732 if (!--tp->timer_counter) {
8733 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
8734 tg3_periodic_fetch_stats(tp);
8736 if (tp->setlpicnt && !--tp->setlpicnt) {
8737 u32 val = tr32(TG3_CPMU_EEE_MODE);
8738 tw32(TG3_CPMU_EEE_MODE,
8739 val | TG3_CPMU_EEEMD_LPI_ENABLE);
8742 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
8746 mac_stat = tr32(MAC_STATUS);
8749 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) {
8750 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
8752 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
8756 tg3_setup_phy(tp, 0);
8757 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
8758 u32 mac_stat = tr32(MAC_STATUS);
8761 if (netif_carrier_ok(tp->dev) &&
8762 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
8765 if (!netif_carrier_ok(tp->dev) &&
8766 (mac_stat & (MAC_STATUS_PCS_SYNCED |
8767 MAC_STATUS_SIGNAL_DET))) {
8771 if (!tp->serdes_counter) {
8774 ~MAC_MODE_PORT_MODE_MASK));
8776 tw32_f(MAC_MODE, tp->mac_mode);
8779 tg3_setup_phy(tp, 0);
8781 } else if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
8782 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
8783 tg3_serdes_parallel_detect(tp);
8786 tp->timer_counter = tp->timer_multiplier;
8789 /* Heartbeat is only sent once every 2 seconds.
8791 * The heartbeat is to tell the ASF firmware that the host
8792 * driver is still alive. In the event that the OS crashes,
8793 * ASF needs to reset the hardware to free up the FIFO space
8794 * that may be filled with rx packets destined for the host.
8795 * If the FIFO is full, ASF will no longer function properly.
8797 * Unintended resets have been reported on real time kernels
8798 * where the timer doesn't run on time. Netpoll will also have
8801 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
8802 * to check the ring condition when the heartbeat is expiring
8803 * before doing the reset. This will prevent most unintended
8806 if (!--tp->asf_counter) {
8807 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
8808 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
8809 tg3_wait_for_event_ack(tp);
8811 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
8812 FWCMD_NICDRV_ALIVE3);
8813 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
8814 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX,
8815 TG3_FW_UPDATE_TIMEOUT_SEC);
8817 tg3_generate_fw_event(tp);
8819 tp->asf_counter = tp->asf_multiplier;
8822 spin_unlock(&tp->lock);
8825 tp->timer.expires = jiffies + tp->timer_offset;
8826 add_timer(&tp->timer);
8829 static int tg3_request_irq(struct tg3 *tp, int irq_num)
8832 unsigned long flags;
8834 struct tg3_napi *tnapi = &tp->napi[irq_num];
8836 if (tp->irq_cnt == 1)
8837 name = tp->dev->name;
8839 name = &tnapi->irq_lbl[0];
8840 snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num);
8841 name[IFNAMSIZ-1] = 0;
8844 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8846 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
8848 flags = IRQF_SAMPLE_RANDOM;
8851 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8852 fn = tg3_interrupt_tagged;
8853 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
8856 return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
8859 static int tg3_test_interrupt(struct tg3 *tp)
8861 struct tg3_napi *tnapi = &tp->napi[0];
8862 struct net_device *dev = tp->dev;
8863 int err, i, intr_ok = 0;
8866 if (!netif_running(dev))
8869 tg3_disable_ints(tp);
8871 free_irq(tnapi->irq_vec, tnapi);
8874 * Turn off MSI one shot mode. Otherwise this test has no
8875 * observable way to know whether the interrupt was delivered.
8877 if ((tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
8878 (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8879 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
8880 tw32(MSGINT_MODE, val);
8883 err = request_irq(tnapi->irq_vec, tg3_test_isr,
8884 IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi);
8888 tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
8889 tg3_enable_ints(tp);
8891 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8894 for (i = 0; i < 5; i++) {
8895 u32 int_mbox, misc_host_ctrl;
8897 int_mbox = tr32_mailbox(tnapi->int_mbox);
8898 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
8900 if ((int_mbox != 0) ||
8901 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
8909 tg3_disable_ints(tp);
8911 free_irq(tnapi->irq_vec, tnapi);
8913 err = tg3_request_irq(tp, 0);
8919 /* Reenable MSI one shot mode. */
8920 if ((tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
8921 (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8922 val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
8923 tw32(MSGINT_MODE, val);
8931 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
8932 * successfully restored
8934 static int tg3_test_msi(struct tg3 *tp)
8939 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
8942 /* Turn off SERR reporting in case MSI terminates with Master
8945 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
8946 pci_write_config_word(tp->pdev, PCI_COMMAND,
8947 pci_cmd & ~PCI_COMMAND_SERR);
8949 err = tg3_test_interrupt(tp);
8951 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
8956 /* other failures */
8960 /* MSI test failed, go back to INTx mode */
8961 netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching "
8962 "to INTx mode. Please report this failure to the PCI "
8963 "maintainer and include system chipset information\n");
8965 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8967 pci_disable_msi(tp->pdev);
8969 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8970 tp->napi[0].irq_vec = tp->pdev->irq;
8972 err = tg3_request_irq(tp, 0);
8976 /* Need to reset the chip because the MSI cycle may have terminated
8977 * with Master Abort.
8979 tg3_full_lock(tp, 1);
8981 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8982 err = tg3_init_hw(tp, 1);
8984 tg3_full_unlock(tp);
8987 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8992 static int tg3_request_firmware(struct tg3 *tp)
8994 const __be32 *fw_data;
8996 if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
8997 netdev_err(tp->dev, "Failed to load firmware \"%s\"\n",
9002 fw_data = (void *)tp->fw->data;
9004 /* Firmware blob starts with version numbers, followed by
9005 * start address and _full_ length including BSS sections
9006 * (which must be longer than the actual data, of course
9009 tp->fw_len = be32_to_cpu(fw_data[2]); /* includes bss */
9010 if (tp->fw_len < (tp->fw->size - 12)) {
9011 netdev_err(tp->dev, "bogus length %d in \"%s\"\n",
9012 tp->fw_len, tp->fw_needed);
9013 release_firmware(tp->fw);
9018 /* We no longer need firmware; we have it. */
9019 tp->fw_needed = NULL;
9023 static bool tg3_enable_msix(struct tg3 *tp)
9025 int i, rc, cpus = num_online_cpus();
9026 struct msix_entry msix_ent[tp->irq_max];
9029 /* Just fallback to the simpler MSI mode. */
9033 * We want as many rx rings enabled as there are cpus.
9034 * The first MSIX vector only deals with link interrupts, etc,
9035 * so we add one to the number of vectors we are requesting.
9037 tp->irq_cnt = min_t(unsigned, cpus + 1, tp->irq_max);
9039 for (i = 0; i < tp->irq_max; i++) {
9040 msix_ent[i].entry = i;
9041 msix_ent[i].vector = 0;
9044 rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
9047 } else if (rc != 0) {
9048 if (pci_enable_msix(tp->pdev, msix_ent, rc))
9050 netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n",
9055 for (i = 0; i < tp->irq_max; i++)
9056 tp->napi[i].irq_vec = msix_ent[i].vector;
9058 netif_set_real_num_tx_queues(tp->dev, 1);
9059 rc = tp->irq_cnt > 1 ? tp->irq_cnt - 1 : 1;
9060 if (netif_set_real_num_rx_queues(tp->dev, rc)) {
9061 pci_disable_msix(tp->pdev);
9065 if (tp->irq_cnt > 1) {
9066 tp->tg3_flags3 |= TG3_FLG3_ENABLE_RSS;
9067 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
9068 tp->tg3_flags3 |= TG3_FLG3_ENABLE_TSS;
9069 netif_set_real_num_tx_queues(tp->dev, tp->irq_cnt - 1);
9076 static void tg3_ints_init(struct tg3 *tp)
9078 if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI_OR_MSIX) &&
9079 !(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
9080 /* All MSI supporting chips should support tagged
9081 * status. Assert that this is the case.
9083 netdev_warn(tp->dev,
9084 "MSI without TAGGED_STATUS? Not using MSI\n");
9088 if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) && tg3_enable_msix(tp))
9089 tp->tg3_flags2 |= TG3_FLG2_USING_MSIX;
9090 else if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) &&
9091 pci_enable_msi(tp->pdev) == 0)
9092 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
9094 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
9095 u32 msi_mode = tr32(MSGINT_MODE);
9096 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
9097 msi_mode |= MSGINT_MODE_MULTIVEC_EN;
9098 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
9101 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
9103 tp->napi[0].irq_vec = tp->pdev->irq;
9104 netif_set_real_num_tx_queues(tp->dev, 1);
9105 netif_set_real_num_rx_queues(tp->dev, 1);
9109 static void tg3_ints_fini(struct tg3 *tp)
9111 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
9112 pci_disable_msix(tp->pdev);
9113 else if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
9114 pci_disable_msi(tp->pdev);
9115 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI_OR_MSIX;
9116 tp->tg3_flags3 &= ~(TG3_FLG3_ENABLE_RSS | TG3_FLG3_ENABLE_TSS);
9119 static int tg3_open(struct net_device *dev)
9121 struct tg3 *tp = netdev_priv(dev);
9124 if (tp->fw_needed) {
9125 err = tg3_request_firmware(tp);
9126 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
9130 netdev_warn(tp->dev, "TSO capability disabled\n");
9131 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
9132 } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
9133 netdev_notice(tp->dev, "TSO capability restored\n");
9134 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
9138 netif_carrier_off(tp->dev);
9140 err = tg3_set_power_state(tp, PCI_D0);
9144 tg3_full_lock(tp, 0);
9146 tg3_disable_ints(tp);
9147 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
9149 tg3_full_unlock(tp);
9152 * Setup interrupts first so we know how
9153 * many NAPI resources to allocate
9157 /* The placement of this call is tied
9158 * to the setup and use of Host TX descriptors.
9160 err = tg3_alloc_consistent(tp);
9166 tg3_napi_enable(tp);
9168 for (i = 0; i < tp->irq_cnt; i++) {
9169 struct tg3_napi *tnapi = &tp->napi[i];
9170 err = tg3_request_irq(tp, i);
9172 for (i--; i >= 0; i--)
9173 free_irq(tnapi->irq_vec, tnapi);
9181 tg3_full_lock(tp, 0);
9183 err = tg3_init_hw(tp, 1);
9185 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9188 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
9189 tp->timer_offset = HZ;
9191 tp->timer_offset = HZ / 10;
9193 BUG_ON(tp->timer_offset > HZ);
9194 tp->timer_counter = tp->timer_multiplier =
9195 (HZ / tp->timer_offset);
9196 tp->asf_counter = tp->asf_multiplier =
9197 ((HZ / tp->timer_offset) * 2);
9199 init_timer(&tp->timer);
9200 tp->timer.expires = jiffies + tp->timer_offset;
9201 tp->timer.data = (unsigned long) tp;
9202 tp->timer.function = tg3_timer;
9205 tg3_full_unlock(tp);
9210 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
9211 err = tg3_test_msi(tp);
9214 tg3_full_lock(tp, 0);
9215 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9217 tg3_full_unlock(tp);
9222 if (!(tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
9223 (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
9224 u32 val = tr32(PCIE_TRANSACTION_CFG);
9226 tw32(PCIE_TRANSACTION_CFG,
9227 val | PCIE_TRANS_CFG_1SHOT_MSI);
9233 tg3_full_lock(tp, 0);
9235 add_timer(&tp->timer);
9236 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
9237 tg3_enable_ints(tp);
9239 tg3_full_unlock(tp);
9241 netif_tx_start_all_queues(dev);
9246 for (i = tp->irq_cnt - 1; i >= 0; i--) {
9247 struct tg3_napi *tnapi = &tp->napi[i];
9248 free_irq(tnapi->irq_vec, tnapi);
9252 tg3_napi_disable(tp);
9254 tg3_free_consistent(tp);
9261 static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *,
9262 struct rtnl_link_stats64 *);
9263 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
9265 static int tg3_close(struct net_device *dev)
9268 struct tg3 *tp = netdev_priv(dev);
9270 tg3_napi_disable(tp);
9271 cancel_work_sync(&tp->reset_task);
9273 netif_tx_stop_all_queues(dev);
9275 del_timer_sync(&tp->timer);
9279 tg3_full_lock(tp, 1);
9281 tg3_disable_ints(tp);
9283 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9285 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
9287 tg3_full_unlock(tp);
9289 for (i = tp->irq_cnt - 1; i >= 0; i--) {
9290 struct tg3_napi *tnapi = &tp->napi[i];
9291 free_irq(tnapi->irq_vec, tnapi);
9296 tg3_get_stats64(tp->dev, &tp->net_stats_prev);
9298 memcpy(&tp->estats_prev, tg3_get_estats(tp),
9299 sizeof(tp->estats_prev));
9303 tg3_free_consistent(tp);
9305 tg3_set_power_state(tp, PCI_D3hot);
9307 netif_carrier_off(tp->dev);
9312 static inline u64 get_stat64(tg3_stat64_t *val)
9314 return ((u64)val->high << 32) | ((u64)val->low);
9317 static u64 calc_crc_errors(struct tg3 *tp)
9319 struct tg3_hw_stats *hw_stats = tp->hw_stats;
9321 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
9322 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
9323 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
9326 spin_lock_bh(&tp->lock);
9327 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
9328 tg3_writephy(tp, MII_TG3_TEST1,
9329 val | MII_TG3_TEST1_CRC_EN);
9330 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &val);
9333 spin_unlock_bh(&tp->lock);
9335 tp->phy_crc_errors += val;
9337 return tp->phy_crc_errors;
9340 return get_stat64(&hw_stats->rx_fcs_errors);
9343 #define ESTAT_ADD(member) \
9344 estats->member = old_estats->member + \
9345 get_stat64(&hw_stats->member)
9347 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
9349 struct tg3_ethtool_stats *estats = &tp->estats;
9350 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
9351 struct tg3_hw_stats *hw_stats = tp->hw_stats;
9356 ESTAT_ADD(rx_octets);
9357 ESTAT_ADD(rx_fragments);
9358 ESTAT_ADD(rx_ucast_packets);
9359 ESTAT_ADD(rx_mcast_packets);
9360 ESTAT_ADD(rx_bcast_packets);
9361 ESTAT_ADD(rx_fcs_errors);
9362 ESTAT_ADD(rx_align_errors);
9363 ESTAT_ADD(rx_xon_pause_rcvd);
9364 ESTAT_ADD(rx_xoff_pause_rcvd);
9365 ESTAT_ADD(rx_mac_ctrl_rcvd);
9366 ESTAT_ADD(rx_xoff_entered);
9367 ESTAT_ADD(rx_frame_too_long_errors);
9368 ESTAT_ADD(rx_jabbers);
9369 ESTAT_ADD(rx_undersize_packets);
9370 ESTAT_ADD(rx_in_length_errors);
9371 ESTAT_ADD(rx_out_length_errors);
9372 ESTAT_ADD(rx_64_or_less_octet_packets);
9373 ESTAT_ADD(rx_65_to_127_octet_packets);
9374 ESTAT_ADD(rx_128_to_255_octet_packets);
9375 ESTAT_ADD(rx_256_to_511_octet_packets);
9376 ESTAT_ADD(rx_512_to_1023_octet_packets);
9377 ESTAT_ADD(rx_1024_to_1522_octet_packets);
9378 ESTAT_ADD(rx_1523_to_2047_octet_packets);
9379 ESTAT_ADD(rx_2048_to_4095_octet_packets);
9380 ESTAT_ADD(rx_4096_to_8191_octet_packets);
9381 ESTAT_ADD(rx_8192_to_9022_octet_packets);
9383 ESTAT_ADD(tx_octets);
9384 ESTAT_ADD(tx_collisions);
9385 ESTAT_ADD(tx_xon_sent);
9386 ESTAT_ADD(tx_xoff_sent);
9387 ESTAT_ADD(tx_flow_control);
9388 ESTAT_ADD(tx_mac_errors);
9389 ESTAT_ADD(tx_single_collisions);
9390 ESTAT_ADD(tx_mult_collisions);
9391 ESTAT_ADD(tx_deferred);
9392 ESTAT_ADD(tx_excessive_collisions);
9393 ESTAT_ADD(tx_late_collisions);
9394 ESTAT_ADD(tx_collide_2times);
9395 ESTAT_ADD(tx_collide_3times);
9396 ESTAT_ADD(tx_collide_4times);
9397 ESTAT_ADD(tx_collide_5times);
9398 ESTAT_ADD(tx_collide_6times);
9399 ESTAT_ADD(tx_collide_7times);
9400 ESTAT_ADD(tx_collide_8times);
9401 ESTAT_ADD(tx_collide_9times);
9402 ESTAT_ADD(tx_collide_10times);
9403 ESTAT_ADD(tx_collide_11times);
9404 ESTAT_ADD(tx_collide_12times);
9405 ESTAT_ADD(tx_collide_13times);
9406 ESTAT_ADD(tx_collide_14times);
9407 ESTAT_ADD(tx_collide_15times);
9408 ESTAT_ADD(tx_ucast_packets);
9409 ESTAT_ADD(tx_mcast_packets);
9410 ESTAT_ADD(tx_bcast_packets);
9411 ESTAT_ADD(tx_carrier_sense_errors);
9412 ESTAT_ADD(tx_discards);
9413 ESTAT_ADD(tx_errors);
9415 ESTAT_ADD(dma_writeq_full);
9416 ESTAT_ADD(dma_write_prioq_full);
9417 ESTAT_ADD(rxbds_empty);
9418 ESTAT_ADD(rx_discards);
9419 ESTAT_ADD(rx_errors);
9420 ESTAT_ADD(rx_threshold_hit);
9422 ESTAT_ADD(dma_readq_full);
9423 ESTAT_ADD(dma_read_prioq_full);
9424 ESTAT_ADD(tx_comp_queue_full);
9426 ESTAT_ADD(ring_set_send_prod_index);
9427 ESTAT_ADD(ring_status_update);
9428 ESTAT_ADD(nic_irqs);
9429 ESTAT_ADD(nic_avoided_irqs);
9430 ESTAT_ADD(nic_tx_threshold_hit);
9435 static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *dev,
9436 struct rtnl_link_stats64 *stats)
9438 struct tg3 *tp = netdev_priv(dev);
9439 struct rtnl_link_stats64 *old_stats = &tp->net_stats_prev;
9440 struct tg3_hw_stats *hw_stats = tp->hw_stats;
9445 stats->rx_packets = old_stats->rx_packets +
9446 get_stat64(&hw_stats->rx_ucast_packets) +
9447 get_stat64(&hw_stats->rx_mcast_packets) +
9448 get_stat64(&hw_stats->rx_bcast_packets);
9450 stats->tx_packets = old_stats->tx_packets +
9451 get_stat64(&hw_stats->tx_ucast_packets) +
9452 get_stat64(&hw_stats->tx_mcast_packets) +
9453 get_stat64(&hw_stats->tx_bcast_packets);
9455 stats->rx_bytes = old_stats->rx_bytes +
9456 get_stat64(&hw_stats->rx_octets);
9457 stats->tx_bytes = old_stats->tx_bytes +
9458 get_stat64(&hw_stats->tx_octets);
9460 stats->rx_errors = old_stats->rx_errors +
9461 get_stat64(&hw_stats->rx_errors);
9462 stats->tx_errors = old_stats->tx_errors +
9463 get_stat64(&hw_stats->tx_errors) +
9464 get_stat64(&hw_stats->tx_mac_errors) +
9465 get_stat64(&hw_stats->tx_carrier_sense_errors) +
9466 get_stat64(&hw_stats->tx_discards);
9468 stats->multicast = old_stats->multicast +
9469 get_stat64(&hw_stats->rx_mcast_packets);
9470 stats->collisions = old_stats->collisions +
9471 get_stat64(&hw_stats->tx_collisions);
9473 stats->rx_length_errors = old_stats->rx_length_errors +
9474 get_stat64(&hw_stats->rx_frame_too_long_errors) +
9475 get_stat64(&hw_stats->rx_undersize_packets);
9477 stats->rx_over_errors = old_stats->rx_over_errors +
9478 get_stat64(&hw_stats->rxbds_empty);
9479 stats->rx_frame_errors = old_stats->rx_frame_errors +
9480 get_stat64(&hw_stats->rx_align_errors);
9481 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
9482 get_stat64(&hw_stats->tx_discards);
9483 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
9484 get_stat64(&hw_stats->tx_carrier_sense_errors);
9486 stats->rx_crc_errors = old_stats->rx_crc_errors +
9487 calc_crc_errors(tp);
9489 stats->rx_missed_errors = old_stats->rx_missed_errors +
9490 get_stat64(&hw_stats->rx_discards);
9492 stats->rx_dropped = tp->rx_dropped;
9497 static inline u32 calc_crc(unsigned char *buf, int len)
9505 for (j = 0; j < len; j++) {
9508 for (k = 0; k < 8; k++) {
9521 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
9523 /* accept or reject all multicast frames */
9524 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
9525 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
9526 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
9527 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
9530 static void __tg3_set_rx_mode(struct net_device *dev)
9532 struct tg3 *tp = netdev_priv(dev);
9535 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
9536 RX_MODE_KEEP_VLAN_TAG);
9538 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
9541 #if TG3_VLAN_TAG_USED
9543 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9544 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9546 /* By definition, VLAN is disabled always in this
9549 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9550 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9553 if (dev->flags & IFF_PROMISC) {
9554 /* Promiscuous mode. */
9555 rx_mode |= RX_MODE_PROMISC;
9556 } else if (dev->flags & IFF_ALLMULTI) {
9557 /* Accept all multicast. */
9558 tg3_set_multi(tp, 1);
9559 } else if (netdev_mc_empty(dev)) {
9560 /* Reject all multicast. */
9561 tg3_set_multi(tp, 0);
9563 /* Accept one or more multicast(s). */
9564 struct netdev_hw_addr *ha;
9565 u32 mc_filter[4] = { 0, };
9570 netdev_for_each_mc_addr(ha, dev) {
9571 crc = calc_crc(ha->addr, ETH_ALEN);
9573 regidx = (bit & 0x60) >> 5;
9575 mc_filter[regidx] |= (1 << bit);
9578 tw32(MAC_HASH_REG_0, mc_filter[0]);
9579 tw32(MAC_HASH_REG_1, mc_filter[1]);
9580 tw32(MAC_HASH_REG_2, mc_filter[2]);
9581 tw32(MAC_HASH_REG_3, mc_filter[3]);
9584 if (rx_mode != tp->rx_mode) {
9585 tp->rx_mode = rx_mode;
9586 tw32_f(MAC_RX_MODE, rx_mode);
9591 static void tg3_set_rx_mode(struct net_device *dev)
9593 struct tg3 *tp = netdev_priv(dev);
9595 if (!netif_running(dev))
9598 tg3_full_lock(tp, 0);
9599 __tg3_set_rx_mode(dev);
9600 tg3_full_unlock(tp);
9603 #define TG3_REGDUMP_LEN (32 * 1024)
9605 static int tg3_get_regs_len(struct net_device *dev)
9607 return TG3_REGDUMP_LEN;
9610 static void tg3_get_regs(struct net_device *dev,
9611 struct ethtool_regs *regs, void *_p)
9614 struct tg3 *tp = netdev_priv(dev);
9620 memset(p, 0, TG3_REGDUMP_LEN);
9622 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
9625 tg3_full_lock(tp, 0);
9627 #define __GET_REG32(reg) (*(p)++ = tr32(reg))
9628 #define GET_REG32_LOOP(base, len) \
9629 do { p = (u32 *)(orig_p + (base)); \
9630 for (i = 0; i < len; i += 4) \
9631 __GET_REG32((base) + i); \
9633 #define GET_REG32_1(reg) \
9634 do { p = (u32 *)(orig_p + (reg)); \
9635 __GET_REG32((reg)); \
9638 GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
9639 GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
9640 GET_REG32_LOOP(MAC_MODE, 0x4f0);
9641 GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
9642 GET_REG32_1(SNDDATAC_MODE);
9643 GET_REG32_LOOP(SNDBDS_MODE, 0x80);
9644 GET_REG32_LOOP(SNDBDI_MODE, 0x48);
9645 GET_REG32_1(SNDBDC_MODE);
9646 GET_REG32_LOOP(RCVLPC_MODE, 0x20);
9647 GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
9648 GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
9649 GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
9650 GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
9651 GET_REG32_1(RCVDCC_MODE);
9652 GET_REG32_LOOP(RCVBDI_MODE, 0x20);
9653 GET_REG32_LOOP(RCVCC_MODE, 0x14);
9654 GET_REG32_LOOP(RCVLSC_MODE, 0x08);
9655 GET_REG32_1(MBFREE_MODE);
9656 GET_REG32_LOOP(HOSTCC_MODE, 0x100);
9657 GET_REG32_LOOP(MEMARB_MODE, 0x10);
9658 GET_REG32_LOOP(BUFMGR_MODE, 0x58);
9659 GET_REG32_LOOP(RDMAC_MODE, 0x08);
9660 GET_REG32_LOOP(WDMAC_MODE, 0x08);
9661 GET_REG32_1(RX_CPU_MODE);
9662 GET_REG32_1(RX_CPU_STATE);
9663 GET_REG32_1(RX_CPU_PGMCTR);
9664 GET_REG32_1(RX_CPU_HWBKPT);
9665 GET_REG32_1(TX_CPU_MODE);
9666 GET_REG32_1(TX_CPU_STATE);
9667 GET_REG32_1(TX_CPU_PGMCTR);
9668 GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
9669 GET_REG32_LOOP(FTQ_RESET, 0x120);
9670 GET_REG32_LOOP(MSGINT_MODE, 0x0c);
9671 GET_REG32_1(DMAC_MODE);
9672 GET_REG32_LOOP(GRC_MODE, 0x4c);
9673 if (tp->tg3_flags & TG3_FLAG_NVRAM)
9674 GET_REG32_LOOP(NVRAM_CMD, 0x24);
9677 #undef GET_REG32_LOOP
9680 tg3_full_unlock(tp);
9683 static int tg3_get_eeprom_len(struct net_device *dev)
9685 struct tg3 *tp = netdev_priv(dev);
9687 return tp->nvram_size;
9690 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9692 struct tg3 *tp = netdev_priv(dev);
9695 u32 i, offset, len, b_offset, b_count;
9698 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9701 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
9704 offset = eeprom->offset;
9708 eeprom->magic = TG3_EEPROM_MAGIC;
9711 /* adjustments to start on required 4 byte boundary */
9712 b_offset = offset & 3;
9713 b_count = 4 - b_offset;
9714 if (b_count > len) {
9715 /* i.e. offset=1 len=2 */
9718 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
9721 memcpy(data, ((char *)&val) + b_offset, b_count);
9724 eeprom->len += b_count;
9727 /* read bytes upto the last 4 byte boundary */
9728 pd = &data[eeprom->len];
9729 for (i = 0; i < (len - (len & 3)); i += 4) {
9730 ret = tg3_nvram_read_be32(tp, offset + i, &val);
9735 memcpy(pd + i, &val, 4);
9740 /* read last bytes not ending on 4 byte boundary */
9741 pd = &data[eeprom->len];
9743 b_offset = offset + len - b_count;
9744 ret = tg3_nvram_read_be32(tp, b_offset, &val);
9747 memcpy(pd, &val, b_count);
9748 eeprom->len += b_count;
9753 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
9755 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9757 struct tg3 *tp = netdev_priv(dev);
9759 u32 offset, len, b_offset, odd_len;
9763 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
9766 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
9767 eeprom->magic != TG3_EEPROM_MAGIC)
9770 offset = eeprom->offset;
9773 if ((b_offset = (offset & 3))) {
9774 /* adjustments to start on required 4 byte boundary */
9775 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
9786 /* adjustments to end on required 4 byte boundary */
9788 len = (len + 3) & ~3;
9789 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
9795 if (b_offset || odd_len) {
9796 buf = kmalloc(len, GFP_KERNEL);
9800 memcpy(buf, &start, 4);
9802 memcpy(buf+len-4, &end, 4);
9803 memcpy(buf + b_offset, data, eeprom->len);
9806 ret = tg3_nvram_write_block(tp, offset, len, buf);
9814 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9816 struct tg3 *tp = netdev_priv(dev);
9818 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9819 struct phy_device *phydev;
9820 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
9822 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9823 return phy_ethtool_gset(phydev, cmd);
9826 cmd->supported = (SUPPORTED_Autoneg);
9828 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
9829 cmd->supported |= (SUPPORTED_1000baseT_Half |
9830 SUPPORTED_1000baseT_Full);
9832 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
9833 cmd->supported |= (SUPPORTED_100baseT_Half |
9834 SUPPORTED_100baseT_Full |
9835 SUPPORTED_10baseT_Half |
9836 SUPPORTED_10baseT_Full |
9838 cmd->port = PORT_TP;
9840 cmd->supported |= SUPPORTED_FIBRE;
9841 cmd->port = PORT_FIBRE;
9844 cmd->advertising = tp->link_config.advertising;
9845 if (netif_running(dev)) {
9846 cmd->speed = tp->link_config.active_speed;
9847 cmd->duplex = tp->link_config.active_duplex;
9849 cmd->speed = SPEED_INVALID;
9850 cmd->duplex = DUPLEX_INVALID;
9852 cmd->phy_address = tp->phy_addr;
9853 cmd->transceiver = XCVR_INTERNAL;
9854 cmd->autoneg = tp->link_config.autoneg;
9860 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9862 struct tg3 *tp = netdev_priv(dev);
9864 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9865 struct phy_device *phydev;
9866 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
9868 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9869 return phy_ethtool_sset(phydev, cmd);
9872 if (cmd->autoneg != AUTONEG_ENABLE &&
9873 cmd->autoneg != AUTONEG_DISABLE)
9876 if (cmd->autoneg == AUTONEG_DISABLE &&
9877 cmd->duplex != DUPLEX_FULL &&
9878 cmd->duplex != DUPLEX_HALF)
9881 if (cmd->autoneg == AUTONEG_ENABLE) {
9882 u32 mask = ADVERTISED_Autoneg |
9884 ADVERTISED_Asym_Pause;
9886 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
9887 mask |= ADVERTISED_1000baseT_Half |
9888 ADVERTISED_1000baseT_Full;
9890 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
9891 mask |= ADVERTISED_100baseT_Half |
9892 ADVERTISED_100baseT_Full |
9893 ADVERTISED_10baseT_Half |
9894 ADVERTISED_10baseT_Full |
9897 mask |= ADVERTISED_FIBRE;
9899 if (cmd->advertising & ~mask)
9902 mask &= (ADVERTISED_1000baseT_Half |
9903 ADVERTISED_1000baseT_Full |
9904 ADVERTISED_100baseT_Half |
9905 ADVERTISED_100baseT_Full |
9906 ADVERTISED_10baseT_Half |
9907 ADVERTISED_10baseT_Full);
9909 cmd->advertising &= mask;
9911 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) {
9912 if (cmd->speed != SPEED_1000)
9915 if (cmd->duplex != DUPLEX_FULL)
9918 if (cmd->speed != SPEED_100 &&
9919 cmd->speed != SPEED_10)
9924 tg3_full_lock(tp, 0);
9926 tp->link_config.autoneg = cmd->autoneg;
9927 if (cmd->autoneg == AUTONEG_ENABLE) {
9928 tp->link_config.advertising = (cmd->advertising |
9929 ADVERTISED_Autoneg);
9930 tp->link_config.speed = SPEED_INVALID;
9931 tp->link_config.duplex = DUPLEX_INVALID;
9933 tp->link_config.advertising = 0;
9934 tp->link_config.speed = cmd->speed;
9935 tp->link_config.duplex = cmd->duplex;
9938 tp->link_config.orig_speed = tp->link_config.speed;
9939 tp->link_config.orig_duplex = tp->link_config.duplex;
9940 tp->link_config.orig_autoneg = tp->link_config.autoneg;
9942 if (netif_running(dev))
9943 tg3_setup_phy(tp, 1);
9945 tg3_full_unlock(tp);
9950 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
9952 struct tg3 *tp = netdev_priv(dev);
9954 strcpy(info->driver, DRV_MODULE_NAME);
9955 strcpy(info->version, DRV_MODULE_VERSION);
9956 strcpy(info->fw_version, tp->fw_ver);
9957 strcpy(info->bus_info, pci_name(tp->pdev));
9960 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9962 struct tg3 *tp = netdev_priv(dev);
9964 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
9965 device_can_wakeup(&tp->pdev->dev))
9966 wol->supported = WAKE_MAGIC;
9970 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
9971 device_can_wakeup(&tp->pdev->dev))
9972 wol->wolopts = WAKE_MAGIC;
9973 memset(&wol->sopass, 0, sizeof(wol->sopass));
9976 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9978 struct tg3 *tp = netdev_priv(dev);
9979 struct device *dp = &tp->pdev->dev;
9981 if (wol->wolopts & ~WAKE_MAGIC)
9983 if ((wol->wolopts & WAKE_MAGIC) &&
9984 !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
9987 device_set_wakeup_enable(dp, wol->wolopts & WAKE_MAGIC);
9989 spin_lock_bh(&tp->lock);
9990 if (device_may_wakeup(dp))
9991 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
9993 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
9994 spin_unlock_bh(&tp->lock);
10000 static u32 tg3_get_msglevel(struct net_device *dev)
10002 struct tg3 *tp = netdev_priv(dev);
10003 return tp->msg_enable;
10006 static void tg3_set_msglevel(struct net_device *dev, u32 value)
10008 struct tg3 *tp = netdev_priv(dev);
10009 tp->msg_enable = value;
10012 static int tg3_set_tso(struct net_device *dev, u32 value)
10014 struct tg3 *tp = netdev_priv(dev);
10016 if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
10021 if ((dev->features & NETIF_F_IPV6_CSUM) &&
10022 ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
10023 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3))) {
10025 dev->features |= NETIF_F_TSO6;
10026 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
10027 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
10028 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
10029 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
10030 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
10031 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
10032 dev->features |= NETIF_F_TSO_ECN;
10034 dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
10036 return ethtool_op_set_tso(dev, value);
10039 static int tg3_nway_reset(struct net_device *dev)
10041 struct tg3 *tp = netdev_priv(dev);
10044 if (!netif_running(dev))
10047 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
10050 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
10051 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
10053 r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
10057 spin_lock_bh(&tp->lock);
10059 tg3_readphy(tp, MII_BMCR, &bmcr);
10060 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
10061 ((bmcr & BMCR_ANENABLE) ||
10062 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT))) {
10063 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
10067 spin_unlock_bh(&tp->lock);
10073 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
10075 struct tg3 *tp = netdev_priv(dev);
10077 ering->rx_max_pending = tp->rx_std_ring_mask;
10078 ering->rx_mini_max_pending = 0;
10079 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
10080 ering->rx_jumbo_max_pending = tp->rx_jmb_ring_mask;
10082 ering->rx_jumbo_max_pending = 0;
10084 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
10086 ering->rx_pending = tp->rx_pending;
10087 ering->rx_mini_pending = 0;
10088 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
10089 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
10091 ering->rx_jumbo_pending = 0;
10093 ering->tx_pending = tp->napi[0].tx_pending;
10096 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
10098 struct tg3 *tp = netdev_priv(dev);
10099 int i, irq_sync = 0, err = 0;
10101 if ((ering->rx_pending > tp->rx_std_ring_mask) ||
10102 (ering->rx_jumbo_pending > tp->rx_jmb_ring_mask) ||
10103 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
10104 (ering->tx_pending <= MAX_SKB_FRAGS) ||
10105 ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
10106 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
10109 if (netif_running(dev)) {
10111 tg3_netif_stop(tp);
10115 tg3_full_lock(tp, irq_sync);
10117 tp->rx_pending = ering->rx_pending;
10119 if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
10120 tp->rx_pending > 63)
10121 tp->rx_pending = 63;
10122 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
10124 for (i = 0; i < tp->irq_max; i++)
10125 tp->napi[i].tx_pending = ering->tx_pending;
10127 if (netif_running(dev)) {
10128 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10129 err = tg3_restart_hw(tp, 1);
10131 tg3_netif_start(tp);
10134 tg3_full_unlock(tp);
10136 if (irq_sync && !err)
10142 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
10144 struct tg3 *tp = netdev_priv(dev);
10146 epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
10148 if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
10149 epause->rx_pause = 1;
10151 epause->rx_pause = 0;
10153 if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
10154 epause->tx_pause = 1;
10156 epause->tx_pause = 0;
10159 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
10161 struct tg3 *tp = netdev_priv(dev);
10164 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
10166 struct phy_device *phydev;
10168 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
10170 if (!(phydev->supported & SUPPORTED_Pause) ||
10171 (!(phydev->supported & SUPPORTED_Asym_Pause) &&
10172 (epause->rx_pause != epause->tx_pause)))
10175 tp->link_config.flowctrl = 0;
10176 if (epause->rx_pause) {
10177 tp->link_config.flowctrl |= FLOW_CTRL_RX;
10179 if (epause->tx_pause) {
10180 tp->link_config.flowctrl |= FLOW_CTRL_TX;
10181 newadv = ADVERTISED_Pause;
10183 newadv = ADVERTISED_Pause |
10184 ADVERTISED_Asym_Pause;
10185 } else if (epause->tx_pause) {
10186 tp->link_config.flowctrl |= FLOW_CTRL_TX;
10187 newadv = ADVERTISED_Asym_Pause;
10191 if (epause->autoneg)
10192 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
10194 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
10196 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
10197 u32 oldadv = phydev->advertising &
10198 (ADVERTISED_Pause | ADVERTISED_Asym_Pause);
10199 if (oldadv != newadv) {
10200 phydev->advertising &=
10201 ~(ADVERTISED_Pause |
10202 ADVERTISED_Asym_Pause);
10203 phydev->advertising |= newadv;
10204 if (phydev->autoneg) {
10206 * Always renegotiate the link to
10207 * inform our link partner of our
10208 * flow control settings, even if the
10209 * flow control is forced. Let
10210 * tg3_adjust_link() do the final
10211 * flow control setup.
10213 return phy_start_aneg(phydev);
10217 if (!epause->autoneg)
10218 tg3_setup_flow_control(tp, 0, 0);
10220 tp->link_config.orig_advertising &=
10221 ~(ADVERTISED_Pause |
10222 ADVERTISED_Asym_Pause);
10223 tp->link_config.orig_advertising |= newadv;
10228 if (netif_running(dev)) {
10229 tg3_netif_stop(tp);
10233 tg3_full_lock(tp, irq_sync);
10235 if (epause->autoneg)
10236 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
10238 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
10239 if (epause->rx_pause)
10240 tp->link_config.flowctrl |= FLOW_CTRL_RX;
10242 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
10243 if (epause->tx_pause)
10244 tp->link_config.flowctrl |= FLOW_CTRL_TX;
10246 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
10248 if (netif_running(dev)) {
10249 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10250 err = tg3_restart_hw(tp, 1);
10252 tg3_netif_start(tp);
10255 tg3_full_unlock(tp);
10261 static u32 tg3_get_rx_csum(struct net_device *dev)
10263 struct tg3 *tp = netdev_priv(dev);
10264 return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
10267 static int tg3_set_rx_csum(struct net_device *dev, u32 data)
10269 struct tg3 *tp = netdev_priv(dev);
10271 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
10277 spin_lock_bh(&tp->lock);
10279 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
10281 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
10282 spin_unlock_bh(&tp->lock);
10287 static int tg3_set_tx_csum(struct net_device *dev, u32 data)
10289 struct tg3 *tp = netdev_priv(dev);
10291 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
10297 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10298 ethtool_op_set_tx_ipv6_csum(dev, data);
10300 ethtool_op_set_tx_csum(dev, data);
10305 static int tg3_get_sset_count(struct net_device *dev, int sset)
10309 return TG3_NUM_TEST;
10311 return TG3_NUM_STATS;
10313 return -EOPNOTSUPP;
10317 static void tg3_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
10319 switch (stringset) {
10321 memcpy(buf, ðtool_stats_keys, sizeof(ethtool_stats_keys));
10324 memcpy(buf, ðtool_test_keys, sizeof(ethtool_test_keys));
10327 WARN_ON(1); /* we need a WARN() */
10332 static int tg3_phys_id(struct net_device *dev, u32 data)
10334 struct tg3 *tp = netdev_priv(dev);
10337 if (!netif_running(tp->dev))
10341 data = UINT_MAX / 2;
10343 for (i = 0; i < (data * 2); i++) {
10345 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10346 LED_CTRL_1000MBPS_ON |
10347 LED_CTRL_100MBPS_ON |
10348 LED_CTRL_10MBPS_ON |
10349 LED_CTRL_TRAFFIC_OVERRIDE |
10350 LED_CTRL_TRAFFIC_BLINK |
10351 LED_CTRL_TRAFFIC_LED);
10354 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10355 LED_CTRL_TRAFFIC_OVERRIDE);
10357 if (msleep_interruptible(500))
10360 tw32(MAC_LED_CTRL, tp->led_ctrl);
10364 static void tg3_get_ethtool_stats(struct net_device *dev,
10365 struct ethtool_stats *estats, u64 *tmp_stats)
10367 struct tg3 *tp = netdev_priv(dev);
10368 memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
10371 #define NVRAM_TEST_SIZE 0x100
10372 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
10373 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
10374 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
10375 #define NVRAM_SELFBOOT_HW_SIZE 0x20
10376 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
10378 static int tg3_test_nvram(struct tg3 *tp)
10382 int i, j, k, err = 0, size;
10384 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
10387 if (tg3_nvram_read(tp, 0, &magic) != 0)
10390 if (magic == TG3_EEPROM_MAGIC)
10391 size = NVRAM_TEST_SIZE;
10392 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
10393 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
10394 TG3_EEPROM_SB_FORMAT_1) {
10395 switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
10396 case TG3_EEPROM_SB_REVISION_0:
10397 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
10399 case TG3_EEPROM_SB_REVISION_2:
10400 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
10402 case TG3_EEPROM_SB_REVISION_3:
10403 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
10410 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
10411 size = NVRAM_SELFBOOT_HW_SIZE;
10415 buf = kmalloc(size, GFP_KERNEL);
10420 for (i = 0, j = 0; i < size; i += 4, j++) {
10421 err = tg3_nvram_read_be32(tp, i, &buf[j]);
10428 /* Selfboot format */
10429 magic = be32_to_cpu(buf[0]);
10430 if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
10431 TG3_EEPROM_MAGIC_FW) {
10432 u8 *buf8 = (u8 *) buf, csum8 = 0;
10434 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
10435 TG3_EEPROM_SB_REVISION_2) {
10436 /* For rev 2, the csum doesn't include the MBA. */
10437 for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
10439 for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
10442 for (i = 0; i < size; i++)
10455 if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
10456 TG3_EEPROM_MAGIC_HW) {
10457 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
10458 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
10459 u8 *buf8 = (u8 *) buf;
10461 /* Separate the parity bits and the data bytes. */
10462 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
10463 if ((i == 0) || (i == 8)) {
10467 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
10468 parity[k++] = buf8[i] & msk;
10470 } else if (i == 16) {
10474 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
10475 parity[k++] = buf8[i] & msk;
10478 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
10479 parity[k++] = buf8[i] & msk;
10482 data[j++] = buf8[i];
10486 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
10487 u8 hw8 = hweight8(data[i]);
10489 if ((hw8 & 0x1) && parity[i])
10491 else if (!(hw8 & 0x1) && !parity[i])
10498 /* Bootstrap checksum at offset 0x10 */
10499 csum = calc_crc((unsigned char *) buf, 0x10);
10500 if (csum != be32_to_cpu(buf[0x10/4]))
10503 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
10504 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
10505 if (csum != be32_to_cpu(buf[0xfc/4]))
10515 #define TG3_SERDES_TIMEOUT_SEC 2
10516 #define TG3_COPPER_TIMEOUT_SEC 6
10518 static int tg3_test_link(struct tg3 *tp)
10522 if (!netif_running(tp->dev))
10525 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
10526 max = TG3_SERDES_TIMEOUT_SEC;
10528 max = TG3_COPPER_TIMEOUT_SEC;
10530 for (i = 0; i < max; i++) {
10531 if (netif_carrier_ok(tp->dev))
10534 if (msleep_interruptible(1000))
10541 /* Only test the commonly used registers */
10542 static int tg3_test_registers(struct tg3 *tp)
10544 int i, is_5705, is_5750;
10545 u32 offset, read_mask, write_mask, val, save_val, read_val;
10549 #define TG3_FL_5705 0x1
10550 #define TG3_FL_NOT_5705 0x2
10551 #define TG3_FL_NOT_5788 0x4
10552 #define TG3_FL_NOT_5750 0x8
10556 /* MAC Control Registers */
10557 { MAC_MODE, TG3_FL_NOT_5705,
10558 0x00000000, 0x00ef6f8c },
10559 { MAC_MODE, TG3_FL_5705,
10560 0x00000000, 0x01ef6b8c },
10561 { MAC_STATUS, TG3_FL_NOT_5705,
10562 0x03800107, 0x00000000 },
10563 { MAC_STATUS, TG3_FL_5705,
10564 0x03800100, 0x00000000 },
10565 { MAC_ADDR_0_HIGH, 0x0000,
10566 0x00000000, 0x0000ffff },
10567 { MAC_ADDR_0_LOW, 0x0000,
10568 0x00000000, 0xffffffff },
10569 { MAC_RX_MTU_SIZE, 0x0000,
10570 0x00000000, 0x0000ffff },
10571 { MAC_TX_MODE, 0x0000,
10572 0x00000000, 0x00000070 },
10573 { MAC_TX_LENGTHS, 0x0000,
10574 0x00000000, 0x00003fff },
10575 { MAC_RX_MODE, TG3_FL_NOT_5705,
10576 0x00000000, 0x000007fc },
10577 { MAC_RX_MODE, TG3_FL_5705,
10578 0x00000000, 0x000007dc },
10579 { MAC_HASH_REG_0, 0x0000,
10580 0x00000000, 0xffffffff },
10581 { MAC_HASH_REG_1, 0x0000,
10582 0x00000000, 0xffffffff },
10583 { MAC_HASH_REG_2, 0x0000,
10584 0x00000000, 0xffffffff },
10585 { MAC_HASH_REG_3, 0x0000,
10586 0x00000000, 0xffffffff },
10588 /* Receive Data and Receive BD Initiator Control Registers. */
10589 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
10590 0x00000000, 0xffffffff },
10591 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
10592 0x00000000, 0xffffffff },
10593 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
10594 0x00000000, 0x00000003 },
10595 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
10596 0x00000000, 0xffffffff },
10597 { RCVDBDI_STD_BD+0, 0x0000,
10598 0x00000000, 0xffffffff },
10599 { RCVDBDI_STD_BD+4, 0x0000,
10600 0x00000000, 0xffffffff },
10601 { RCVDBDI_STD_BD+8, 0x0000,
10602 0x00000000, 0xffff0002 },
10603 { RCVDBDI_STD_BD+0xc, 0x0000,
10604 0x00000000, 0xffffffff },
10606 /* Receive BD Initiator Control Registers. */
10607 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
10608 0x00000000, 0xffffffff },
10609 { RCVBDI_STD_THRESH, TG3_FL_5705,
10610 0x00000000, 0x000003ff },
10611 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
10612 0x00000000, 0xffffffff },
10614 /* Host Coalescing Control Registers. */
10615 { HOSTCC_MODE, TG3_FL_NOT_5705,
10616 0x00000000, 0x00000004 },
10617 { HOSTCC_MODE, TG3_FL_5705,
10618 0x00000000, 0x000000f6 },
10619 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
10620 0x00000000, 0xffffffff },
10621 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
10622 0x00000000, 0x000003ff },
10623 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
10624 0x00000000, 0xffffffff },
10625 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
10626 0x00000000, 0x000003ff },
10627 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
10628 0x00000000, 0xffffffff },
10629 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10630 0x00000000, 0x000000ff },
10631 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
10632 0x00000000, 0xffffffff },
10633 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10634 0x00000000, 0x000000ff },
10635 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
10636 0x00000000, 0xffffffff },
10637 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
10638 0x00000000, 0xffffffff },
10639 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10640 0x00000000, 0xffffffff },
10641 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10642 0x00000000, 0x000000ff },
10643 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10644 0x00000000, 0xffffffff },
10645 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10646 0x00000000, 0x000000ff },
10647 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
10648 0x00000000, 0xffffffff },
10649 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
10650 0x00000000, 0xffffffff },
10651 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
10652 0x00000000, 0xffffffff },
10653 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
10654 0x00000000, 0xffffffff },
10655 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
10656 0x00000000, 0xffffffff },
10657 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
10658 0xffffffff, 0x00000000 },
10659 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
10660 0xffffffff, 0x00000000 },
10662 /* Buffer Manager Control Registers. */
10663 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
10664 0x00000000, 0x007fff80 },
10665 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
10666 0x00000000, 0x007fffff },
10667 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
10668 0x00000000, 0x0000003f },
10669 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
10670 0x00000000, 0x000001ff },
10671 { BUFMGR_MB_HIGH_WATER, 0x0000,
10672 0x00000000, 0x000001ff },
10673 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
10674 0xffffffff, 0x00000000 },
10675 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
10676 0xffffffff, 0x00000000 },
10678 /* Mailbox Registers */
10679 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
10680 0x00000000, 0x000001ff },
10681 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
10682 0x00000000, 0x000001ff },
10683 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
10684 0x00000000, 0x000007ff },
10685 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
10686 0x00000000, 0x000001ff },
10688 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
10691 is_5705 = is_5750 = 0;
10692 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
10694 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10698 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
10699 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
10702 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
10705 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
10706 (reg_tbl[i].flags & TG3_FL_NOT_5788))
10709 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
10712 offset = (u32) reg_tbl[i].offset;
10713 read_mask = reg_tbl[i].read_mask;
10714 write_mask = reg_tbl[i].write_mask;
10716 /* Save the original register content */
10717 save_val = tr32(offset);
10719 /* Determine the read-only value. */
10720 read_val = save_val & read_mask;
10722 /* Write zero to the register, then make sure the read-only bits
10723 * are not changed and the read/write bits are all zeros.
10727 val = tr32(offset);
10729 /* Test the read-only and read/write bits. */
10730 if (((val & read_mask) != read_val) || (val & write_mask))
10733 /* Write ones to all the bits defined by RdMask and WrMask, then
10734 * make sure the read-only bits are not changed and the
10735 * read/write bits are all ones.
10737 tw32(offset, read_mask | write_mask);
10739 val = tr32(offset);
10741 /* Test the read-only bits. */
10742 if ((val & read_mask) != read_val)
10745 /* Test the read/write bits. */
10746 if ((val & write_mask) != write_mask)
10749 tw32(offset, save_val);
10755 if (netif_msg_hw(tp))
10756 netdev_err(tp->dev,
10757 "Register test failed at offset %x\n", offset);
10758 tw32(offset, save_val);
10762 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
10764 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
10768 for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
10769 for (j = 0; j < len; j += 4) {
10772 tg3_write_mem(tp, offset + j, test_pattern[i]);
10773 tg3_read_mem(tp, offset + j, &val);
10774 if (val != test_pattern[i])
10781 static int tg3_test_memory(struct tg3 *tp)
10783 static struct mem_entry {
10786 } mem_tbl_570x[] = {
10787 { 0x00000000, 0x00b50},
10788 { 0x00002000, 0x1c000},
10789 { 0xffffffff, 0x00000}
10790 }, mem_tbl_5705[] = {
10791 { 0x00000100, 0x0000c},
10792 { 0x00000200, 0x00008},
10793 { 0x00004000, 0x00800},
10794 { 0x00006000, 0x01000},
10795 { 0x00008000, 0x02000},
10796 { 0x00010000, 0x0e000},
10797 { 0xffffffff, 0x00000}
10798 }, mem_tbl_5755[] = {
10799 { 0x00000200, 0x00008},
10800 { 0x00004000, 0x00800},
10801 { 0x00006000, 0x00800},
10802 { 0x00008000, 0x02000},
10803 { 0x00010000, 0x0c000},
10804 { 0xffffffff, 0x00000}
10805 }, mem_tbl_5906[] = {
10806 { 0x00000200, 0x00008},
10807 { 0x00004000, 0x00400},
10808 { 0x00006000, 0x00400},
10809 { 0x00008000, 0x01000},
10810 { 0x00010000, 0x01000},
10811 { 0xffffffff, 0x00000}
10812 }, mem_tbl_5717[] = {
10813 { 0x00000200, 0x00008},
10814 { 0x00010000, 0x0a000},
10815 { 0x00020000, 0x13c00},
10816 { 0xffffffff, 0x00000}
10817 }, mem_tbl_57765[] = {
10818 { 0x00000200, 0x00008},
10819 { 0x00004000, 0x00800},
10820 { 0x00006000, 0x09800},
10821 { 0x00010000, 0x0a000},
10822 { 0xffffffff, 0x00000}
10824 struct mem_entry *mem_tbl;
10828 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
10829 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
10830 mem_tbl = mem_tbl_5717;
10831 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
10832 mem_tbl = mem_tbl_57765;
10833 else if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10834 mem_tbl = mem_tbl_5755;
10835 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10836 mem_tbl = mem_tbl_5906;
10837 else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
10838 mem_tbl = mem_tbl_5705;
10840 mem_tbl = mem_tbl_570x;
10842 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
10843 err = tg3_do_mem_test(tp, mem_tbl[i].offset, mem_tbl[i].len);
10851 #define TG3_MAC_LOOPBACK 0
10852 #define TG3_PHY_LOOPBACK 1
10854 static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
10856 u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
10857 u32 desc_idx, coal_now;
10858 struct sk_buff *skb, *rx_skb;
10861 int num_pkts, tx_len, rx_len, i, err;
10862 struct tg3_rx_buffer_desc *desc;
10863 struct tg3_napi *tnapi, *rnapi;
10864 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
10866 tnapi = &tp->napi[0];
10867 rnapi = &tp->napi[0];
10868 if (tp->irq_cnt > 1) {
10869 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)
10870 rnapi = &tp->napi[1];
10871 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
10872 tnapi = &tp->napi[1];
10874 coal_now = tnapi->coal_now | rnapi->coal_now;
10876 if (loopback_mode == TG3_MAC_LOOPBACK) {
10877 /* HW errata - mac loopback fails in some cases on 5780.
10878 * Normal traffic and PHY loopback are not affected by
10881 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
10884 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
10885 MAC_MODE_PORT_INT_LPBACK;
10886 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10887 mac_mode |= MAC_MODE_LINK_POLARITY;
10888 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
10889 mac_mode |= MAC_MODE_PORT_MODE_MII;
10891 mac_mode |= MAC_MODE_PORT_MODE_GMII;
10892 tw32(MAC_MODE, mac_mode);
10893 } else if (loopback_mode == TG3_PHY_LOOPBACK) {
10896 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
10897 tg3_phy_fet_toggle_apd(tp, false);
10898 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
10900 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
10902 tg3_phy_toggle_automdix(tp, 0);
10904 tg3_writephy(tp, MII_BMCR, val);
10907 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
10908 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
10909 tg3_writephy(tp, MII_TG3_FET_PTEST,
10910 MII_TG3_FET_PTEST_FRC_TX_LINK |
10911 MII_TG3_FET_PTEST_FRC_TX_LOCK);
10912 /* The write needs to be flushed for the AC131 */
10913 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
10914 tg3_readphy(tp, MII_TG3_FET_PTEST, &val);
10915 mac_mode |= MAC_MODE_PORT_MODE_MII;
10917 mac_mode |= MAC_MODE_PORT_MODE_GMII;
10919 /* reset to prevent losing 1st rx packet intermittently */
10920 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
10921 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10923 tw32_f(MAC_RX_MODE, tp->rx_mode);
10925 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
10926 u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK;
10927 if (masked_phy_id == TG3_PHY_ID_BCM5401)
10928 mac_mode &= ~MAC_MODE_LINK_POLARITY;
10929 else if (masked_phy_id == TG3_PHY_ID_BCM5411)
10930 mac_mode |= MAC_MODE_LINK_POLARITY;
10931 tg3_writephy(tp, MII_TG3_EXT_CTRL,
10932 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
10934 tw32(MAC_MODE, mac_mode);
10942 skb = netdev_alloc_skb(tp->dev, tx_len);
10946 tx_data = skb_put(skb, tx_len);
10947 memcpy(tx_data, tp->dev->dev_addr, 6);
10948 memset(tx_data + 6, 0x0, 8);
10950 tw32(MAC_RX_MTU_SIZE, tx_len + 4);
10952 for (i = 14; i < tx_len; i++)
10953 tx_data[i] = (u8) (i & 0xff);
10955 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
10956 if (pci_dma_mapping_error(tp->pdev, map)) {
10957 dev_kfree_skb(skb);
10961 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10966 rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
10970 tg3_set_txd(tnapi, tnapi->tx_prod, map, tx_len, 0, 1);
10975 tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
10976 tr32_mailbox(tnapi->prodmbox);
10980 /* 350 usec to allow enough time on some 10/100 Mbps devices. */
10981 for (i = 0; i < 35; i++) {
10982 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10987 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
10988 rx_idx = rnapi->hw_status->idx[0].rx_producer;
10989 if ((tx_idx == tnapi->tx_prod) &&
10990 (rx_idx == (rx_start_idx + num_pkts)))
10994 pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
10995 dev_kfree_skb(skb);
10997 if (tx_idx != tnapi->tx_prod)
11000 if (rx_idx != rx_start_idx + num_pkts)
11003 desc = &rnapi->rx_rcb[rx_start_idx];
11004 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
11005 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
11006 if (opaque_key != RXD_OPAQUE_RING_STD)
11009 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
11010 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
11013 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
11014 if (rx_len != tx_len)
11017 rx_skb = tpr->rx_std_buffers[desc_idx].skb;
11019 map = dma_unmap_addr(&tpr->rx_std_buffers[desc_idx], mapping);
11020 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
11022 for (i = 14; i < tx_len; i++) {
11023 if (*(rx_skb->data + i) != (u8) (i & 0xff))
11028 /* tg3_free_rings will unmap and free the rx_skb */
11033 #define TG3_MAC_LOOPBACK_FAILED 1
11034 #define TG3_PHY_LOOPBACK_FAILED 2
11035 #define TG3_LOOPBACK_FAILED (TG3_MAC_LOOPBACK_FAILED | \
11036 TG3_PHY_LOOPBACK_FAILED)
11038 static int tg3_test_loopback(struct tg3 *tp)
11043 if (!netif_running(tp->dev))
11044 return TG3_LOOPBACK_FAILED;
11046 err = tg3_reset_hw(tp, 1);
11048 return TG3_LOOPBACK_FAILED;
11050 /* Turn off gphy autopowerdown. */
11051 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
11052 tg3_phy_toggle_apd(tp, false);
11054 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
11058 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
11060 /* Wait for up to 40 microseconds to acquire lock. */
11061 for (i = 0; i < 4; i++) {
11062 status = tr32(TG3_CPMU_MUTEX_GNT);
11063 if (status == CPMU_MUTEX_GNT_DRIVER)
11068 if (status != CPMU_MUTEX_GNT_DRIVER)
11069 return TG3_LOOPBACK_FAILED;
11071 /* Turn off link-based power management. */
11072 cpmuctrl = tr32(TG3_CPMU_CTRL);
11073 tw32(TG3_CPMU_CTRL,
11074 cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
11075 CPMU_CTRL_LINK_AWARE_MODE));
11078 if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
11079 err |= TG3_MAC_LOOPBACK_FAILED;
11081 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
11082 tw32(TG3_CPMU_CTRL, cpmuctrl);
11084 /* Release the mutex */
11085 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
11088 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
11089 !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
11090 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
11091 err |= TG3_PHY_LOOPBACK_FAILED;
11094 /* Re-enable gphy autopowerdown. */
11095 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
11096 tg3_phy_toggle_apd(tp, true);
11101 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
11104 struct tg3 *tp = netdev_priv(dev);
11106 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
11107 tg3_set_power_state(tp, PCI_D0);
11109 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
11111 if (tg3_test_nvram(tp) != 0) {
11112 etest->flags |= ETH_TEST_FL_FAILED;
11115 if (tg3_test_link(tp) != 0) {
11116 etest->flags |= ETH_TEST_FL_FAILED;
11119 if (etest->flags & ETH_TEST_FL_OFFLINE) {
11120 int err, err2 = 0, irq_sync = 0;
11122 if (netif_running(dev)) {
11124 tg3_netif_stop(tp);
11128 tg3_full_lock(tp, irq_sync);
11130 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
11131 err = tg3_nvram_lock(tp);
11132 tg3_halt_cpu(tp, RX_CPU_BASE);
11133 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
11134 tg3_halt_cpu(tp, TX_CPU_BASE);
11136 tg3_nvram_unlock(tp);
11138 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
11141 if (tg3_test_registers(tp) != 0) {
11142 etest->flags |= ETH_TEST_FL_FAILED;
11145 if (tg3_test_memory(tp) != 0) {
11146 etest->flags |= ETH_TEST_FL_FAILED;
11149 if ((data[4] = tg3_test_loopback(tp)) != 0)
11150 etest->flags |= ETH_TEST_FL_FAILED;
11152 tg3_full_unlock(tp);
11154 if (tg3_test_interrupt(tp) != 0) {
11155 etest->flags |= ETH_TEST_FL_FAILED;
11159 tg3_full_lock(tp, 0);
11161 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11162 if (netif_running(dev)) {
11163 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
11164 err2 = tg3_restart_hw(tp, 1);
11166 tg3_netif_start(tp);
11169 tg3_full_unlock(tp);
11171 if (irq_sync && !err2)
11174 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
11175 tg3_set_power_state(tp, PCI_D3hot);
11179 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
11181 struct mii_ioctl_data *data = if_mii(ifr);
11182 struct tg3 *tp = netdev_priv(dev);
11185 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
11186 struct phy_device *phydev;
11187 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
11189 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
11190 return phy_mii_ioctl(phydev, ifr, cmd);
11195 data->phy_id = tp->phy_addr;
11198 case SIOCGMIIREG: {
11201 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
11202 break; /* We have no PHY */
11204 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
11207 spin_lock_bh(&tp->lock);
11208 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
11209 spin_unlock_bh(&tp->lock);
11211 data->val_out = mii_regval;
11217 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
11218 break; /* We have no PHY */
11220 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
11223 spin_lock_bh(&tp->lock);
11224 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
11225 spin_unlock_bh(&tp->lock);
11233 return -EOPNOTSUPP;
11236 #if TG3_VLAN_TAG_USED
11237 static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
11239 struct tg3 *tp = netdev_priv(dev);
11241 if (!netif_running(dev)) {
11246 tg3_netif_stop(tp);
11248 tg3_full_lock(tp, 0);
11252 /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
11253 __tg3_set_rx_mode(dev);
11255 tg3_netif_start(tp);
11257 tg3_full_unlock(tp);
11261 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11263 struct tg3 *tp = netdev_priv(dev);
11265 memcpy(ec, &tp->coal, sizeof(*ec));
11269 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11271 struct tg3 *tp = netdev_priv(dev);
11272 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
11273 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
11275 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
11276 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
11277 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
11278 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
11279 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
11282 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
11283 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
11284 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
11285 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
11286 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
11287 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
11288 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
11289 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
11290 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
11291 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
11294 /* No rx interrupts will be generated if both are zero */
11295 if ((ec->rx_coalesce_usecs == 0) &&
11296 (ec->rx_max_coalesced_frames == 0))
11299 /* No tx interrupts will be generated if both are zero */
11300 if ((ec->tx_coalesce_usecs == 0) &&
11301 (ec->tx_max_coalesced_frames == 0))
11304 /* Only copy relevant parameters, ignore all others. */
11305 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
11306 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
11307 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
11308 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
11309 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
11310 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
11311 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
11312 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
11313 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
11315 if (netif_running(dev)) {
11316 tg3_full_lock(tp, 0);
11317 __tg3_set_coalesce(tp, &tp->coal);
11318 tg3_full_unlock(tp);
11323 static const struct ethtool_ops tg3_ethtool_ops = {
11324 .get_settings = tg3_get_settings,
11325 .set_settings = tg3_set_settings,
11326 .get_drvinfo = tg3_get_drvinfo,
11327 .get_regs_len = tg3_get_regs_len,
11328 .get_regs = tg3_get_regs,
11329 .get_wol = tg3_get_wol,
11330 .set_wol = tg3_set_wol,
11331 .get_msglevel = tg3_get_msglevel,
11332 .set_msglevel = tg3_set_msglevel,
11333 .nway_reset = tg3_nway_reset,
11334 .get_link = ethtool_op_get_link,
11335 .get_eeprom_len = tg3_get_eeprom_len,
11336 .get_eeprom = tg3_get_eeprom,
11337 .set_eeprom = tg3_set_eeprom,
11338 .get_ringparam = tg3_get_ringparam,
11339 .set_ringparam = tg3_set_ringparam,
11340 .get_pauseparam = tg3_get_pauseparam,
11341 .set_pauseparam = tg3_set_pauseparam,
11342 .get_rx_csum = tg3_get_rx_csum,
11343 .set_rx_csum = tg3_set_rx_csum,
11344 .set_tx_csum = tg3_set_tx_csum,
11345 .set_sg = ethtool_op_set_sg,
11346 .set_tso = tg3_set_tso,
11347 .self_test = tg3_self_test,
11348 .get_strings = tg3_get_strings,
11349 .phys_id = tg3_phys_id,
11350 .get_ethtool_stats = tg3_get_ethtool_stats,
11351 .get_coalesce = tg3_get_coalesce,
11352 .set_coalesce = tg3_set_coalesce,
11353 .get_sset_count = tg3_get_sset_count,
11356 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
11358 u32 cursize, val, magic;
11360 tp->nvram_size = EEPROM_CHIP_SIZE;
11362 if (tg3_nvram_read(tp, 0, &magic) != 0)
11365 if ((magic != TG3_EEPROM_MAGIC) &&
11366 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
11367 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
11371 * Size the chip by reading offsets at increasing powers of two.
11372 * When we encounter our validation signature, we know the addressing
11373 * has wrapped around, and thus have our chip size.
11377 while (cursize < tp->nvram_size) {
11378 if (tg3_nvram_read(tp, cursize, &val) != 0)
11387 tp->nvram_size = cursize;
11390 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
11394 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
11395 tg3_nvram_read(tp, 0, &val) != 0)
11398 /* Selfboot format */
11399 if (val != TG3_EEPROM_MAGIC) {
11400 tg3_get_eeprom_size(tp);
11404 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
11406 /* This is confusing. We want to operate on the
11407 * 16-bit value at offset 0xf2. The tg3_nvram_read()
11408 * call will read from NVRAM and byteswap the data
11409 * according to the byteswapping settings for all
11410 * other register accesses. This ensures the data we
11411 * want will always reside in the lower 16-bits.
11412 * However, the data in NVRAM is in LE format, which
11413 * means the data from the NVRAM read will always be
11414 * opposite the endianness of the CPU. The 16-bit
11415 * byteswap then brings the data to CPU endianness.
11417 tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
11421 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11424 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
11428 nvcfg1 = tr32(NVRAM_CFG1);
11429 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
11430 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11432 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11433 tw32(NVRAM_CFG1, nvcfg1);
11436 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
11437 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
11438 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
11439 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
11440 tp->nvram_jedecnum = JEDEC_ATMEL;
11441 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11442 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11444 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
11445 tp->nvram_jedecnum = JEDEC_ATMEL;
11446 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
11448 case FLASH_VENDOR_ATMEL_EEPROM:
11449 tp->nvram_jedecnum = JEDEC_ATMEL;
11450 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11451 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11453 case FLASH_VENDOR_ST:
11454 tp->nvram_jedecnum = JEDEC_ST;
11455 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
11456 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11458 case FLASH_VENDOR_SAIFUN:
11459 tp->nvram_jedecnum = JEDEC_SAIFUN;
11460 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
11462 case FLASH_VENDOR_SST_SMALL:
11463 case FLASH_VENDOR_SST_LARGE:
11464 tp->nvram_jedecnum = JEDEC_SST;
11465 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
11469 tp->nvram_jedecnum = JEDEC_ATMEL;
11470 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11471 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11475 static void __devinit tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
11477 switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
11478 case FLASH_5752PAGE_SIZE_256:
11479 tp->nvram_pagesize = 256;
11481 case FLASH_5752PAGE_SIZE_512:
11482 tp->nvram_pagesize = 512;
11484 case FLASH_5752PAGE_SIZE_1K:
11485 tp->nvram_pagesize = 1024;
11487 case FLASH_5752PAGE_SIZE_2K:
11488 tp->nvram_pagesize = 2048;
11490 case FLASH_5752PAGE_SIZE_4K:
11491 tp->nvram_pagesize = 4096;
11493 case FLASH_5752PAGE_SIZE_264:
11494 tp->nvram_pagesize = 264;
11496 case FLASH_5752PAGE_SIZE_528:
11497 tp->nvram_pagesize = 528;
11502 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
11506 nvcfg1 = tr32(NVRAM_CFG1);
11508 /* NVRAM protection for TPM */
11509 if (nvcfg1 & (1 << 27))
11510 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11512 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11513 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
11514 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
11515 tp->nvram_jedecnum = JEDEC_ATMEL;
11516 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11518 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11519 tp->nvram_jedecnum = JEDEC_ATMEL;
11520 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11521 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11523 case FLASH_5752VENDOR_ST_M45PE10:
11524 case FLASH_5752VENDOR_ST_M45PE20:
11525 case FLASH_5752VENDOR_ST_M45PE40:
11526 tp->nvram_jedecnum = JEDEC_ST;
11527 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11528 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11532 if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
11533 tg3_nvram_get_pagesize(tp, nvcfg1);
11535 /* For eeprom, set pagesize to maximum eeprom size */
11536 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11538 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11539 tw32(NVRAM_CFG1, nvcfg1);
11543 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
11545 u32 nvcfg1, protect = 0;
11547 nvcfg1 = tr32(NVRAM_CFG1);
11549 /* NVRAM protection for TPM */
11550 if (nvcfg1 & (1 << 27)) {
11551 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11555 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11557 case FLASH_5755VENDOR_ATMEL_FLASH_1:
11558 case FLASH_5755VENDOR_ATMEL_FLASH_2:
11559 case FLASH_5755VENDOR_ATMEL_FLASH_3:
11560 case FLASH_5755VENDOR_ATMEL_FLASH_5:
11561 tp->nvram_jedecnum = JEDEC_ATMEL;
11562 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11563 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11564 tp->nvram_pagesize = 264;
11565 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
11566 nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
11567 tp->nvram_size = (protect ? 0x3e200 :
11568 TG3_NVRAM_SIZE_512KB);
11569 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
11570 tp->nvram_size = (protect ? 0x1f200 :
11571 TG3_NVRAM_SIZE_256KB);
11573 tp->nvram_size = (protect ? 0x1f200 :
11574 TG3_NVRAM_SIZE_128KB);
11576 case FLASH_5752VENDOR_ST_M45PE10:
11577 case FLASH_5752VENDOR_ST_M45PE20:
11578 case FLASH_5752VENDOR_ST_M45PE40:
11579 tp->nvram_jedecnum = JEDEC_ST;
11580 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11581 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11582 tp->nvram_pagesize = 256;
11583 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
11584 tp->nvram_size = (protect ?
11585 TG3_NVRAM_SIZE_64KB :
11586 TG3_NVRAM_SIZE_128KB);
11587 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
11588 tp->nvram_size = (protect ?
11589 TG3_NVRAM_SIZE_64KB :
11590 TG3_NVRAM_SIZE_256KB);
11592 tp->nvram_size = (protect ?
11593 TG3_NVRAM_SIZE_128KB :
11594 TG3_NVRAM_SIZE_512KB);
11599 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
11603 nvcfg1 = tr32(NVRAM_CFG1);
11605 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11606 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
11607 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11608 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
11609 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11610 tp->nvram_jedecnum = JEDEC_ATMEL;
11611 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11612 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11614 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11615 tw32(NVRAM_CFG1, nvcfg1);
11617 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11618 case FLASH_5755VENDOR_ATMEL_FLASH_1:
11619 case FLASH_5755VENDOR_ATMEL_FLASH_2:
11620 case FLASH_5755VENDOR_ATMEL_FLASH_3:
11621 tp->nvram_jedecnum = JEDEC_ATMEL;
11622 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11623 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11624 tp->nvram_pagesize = 264;
11626 case FLASH_5752VENDOR_ST_M45PE10:
11627 case FLASH_5752VENDOR_ST_M45PE20:
11628 case FLASH_5752VENDOR_ST_M45PE40:
11629 tp->nvram_jedecnum = JEDEC_ST;
11630 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11631 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11632 tp->nvram_pagesize = 256;
11637 static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
11639 u32 nvcfg1, protect = 0;
11641 nvcfg1 = tr32(NVRAM_CFG1);
11643 /* NVRAM protection for TPM */
11644 if (nvcfg1 & (1 << 27)) {
11645 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11649 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11651 case FLASH_5761VENDOR_ATMEL_ADB021D:
11652 case FLASH_5761VENDOR_ATMEL_ADB041D:
11653 case FLASH_5761VENDOR_ATMEL_ADB081D:
11654 case FLASH_5761VENDOR_ATMEL_ADB161D:
11655 case FLASH_5761VENDOR_ATMEL_MDB021D:
11656 case FLASH_5761VENDOR_ATMEL_MDB041D:
11657 case FLASH_5761VENDOR_ATMEL_MDB081D:
11658 case FLASH_5761VENDOR_ATMEL_MDB161D:
11659 tp->nvram_jedecnum = JEDEC_ATMEL;
11660 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11661 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11662 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11663 tp->nvram_pagesize = 256;
11665 case FLASH_5761VENDOR_ST_A_M45PE20:
11666 case FLASH_5761VENDOR_ST_A_M45PE40:
11667 case FLASH_5761VENDOR_ST_A_M45PE80:
11668 case FLASH_5761VENDOR_ST_A_M45PE16:
11669 case FLASH_5761VENDOR_ST_M_M45PE20:
11670 case FLASH_5761VENDOR_ST_M_M45PE40:
11671 case FLASH_5761VENDOR_ST_M_M45PE80:
11672 case FLASH_5761VENDOR_ST_M_M45PE16:
11673 tp->nvram_jedecnum = JEDEC_ST;
11674 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11675 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11676 tp->nvram_pagesize = 256;
11681 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
11684 case FLASH_5761VENDOR_ATMEL_ADB161D:
11685 case FLASH_5761VENDOR_ATMEL_MDB161D:
11686 case FLASH_5761VENDOR_ST_A_M45PE16:
11687 case FLASH_5761VENDOR_ST_M_M45PE16:
11688 tp->nvram_size = TG3_NVRAM_SIZE_2MB;
11690 case FLASH_5761VENDOR_ATMEL_ADB081D:
11691 case FLASH_5761VENDOR_ATMEL_MDB081D:
11692 case FLASH_5761VENDOR_ST_A_M45PE80:
11693 case FLASH_5761VENDOR_ST_M_M45PE80:
11694 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
11696 case FLASH_5761VENDOR_ATMEL_ADB041D:
11697 case FLASH_5761VENDOR_ATMEL_MDB041D:
11698 case FLASH_5761VENDOR_ST_A_M45PE40:
11699 case FLASH_5761VENDOR_ST_M_M45PE40:
11700 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11702 case FLASH_5761VENDOR_ATMEL_ADB021D:
11703 case FLASH_5761VENDOR_ATMEL_MDB021D:
11704 case FLASH_5761VENDOR_ST_A_M45PE20:
11705 case FLASH_5761VENDOR_ST_M_M45PE20:
11706 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11712 static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
11714 tp->nvram_jedecnum = JEDEC_ATMEL;
11715 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11716 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11719 static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
11723 nvcfg1 = tr32(NVRAM_CFG1);
11725 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11726 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11727 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11728 tp->nvram_jedecnum = JEDEC_ATMEL;
11729 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11730 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11732 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11733 tw32(NVRAM_CFG1, nvcfg1);
11735 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11736 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11737 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11738 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11739 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11740 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11741 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11742 tp->nvram_jedecnum = JEDEC_ATMEL;
11743 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11744 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11746 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11747 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11748 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11749 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11750 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11752 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11753 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11754 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11756 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11757 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11758 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11762 case FLASH_5752VENDOR_ST_M45PE10:
11763 case FLASH_5752VENDOR_ST_M45PE20:
11764 case FLASH_5752VENDOR_ST_M45PE40:
11765 tp->nvram_jedecnum = JEDEC_ST;
11766 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11767 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11769 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11770 case FLASH_5752VENDOR_ST_M45PE10:
11771 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11773 case FLASH_5752VENDOR_ST_M45PE20:
11774 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11776 case FLASH_5752VENDOR_ST_M45PE40:
11777 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11782 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11786 tg3_nvram_get_pagesize(tp, nvcfg1);
11787 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11788 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11792 static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp)
11796 nvcfg1 = tr32(NVRAM_CFG1);
11798 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11799 case FLASH_5717VENDOR_ATMEL_EEPROM:
11800 case FLASH_5717VENDOR_MICRO_EEPROM:
11801 tp->nvram_jedecnum = JEDEC_ATMEL;
11802 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11803 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11805 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11806 tw32(NVRAM_CFG1, nvcfg1);
11808 case FLASH_5717VENDOR_ATMEL_MDB011D:
11809 case FLASH_5717VENDOR_ATMEL_ADB011B:
11810 case FLASH_5717VENDOR_ATMEL_ADB011D:
11811 case FLASH_5717VENDOR_ATMEL_MDB021D:
11812 case FLASH_5717VENDOR_ATMEL_ADB021B:
11813 case FLASH_5717VENDOR_ATMEL_ADB021D:
11814 case FLASH_5717VENDOR_ATMEL_45USPT:
11815 tp->nvram_jedecnum = JEDEC_ATMEL;
11816 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11817 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11819 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11820 case FLASH_5717VENDOR_ATMEL_MDB021D:
11821 case FLASH_5717VENDOR_ATMEL_ADB021B:
11822 case FLASH_5717VENDOR_ATMEL_ADB021D:
11823 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11826 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11830 case FLASH_5717VENDOR_ST_M_M25PE10:
11831 case FLASH_5717VENDOR_ST_A_M25PE10:
11832 case FLASH_5717VENDOR_ST_M_M45PE10:
11833 case FLASH_5717VENDOR_ST_A_M45PE10:
11834 case FLASH_5717VENDOR_ST_M_M25PE20:
11835 case FLASH_5717VENDOR_ST_A_M25PE20:
11836 case FLASH_5717VENDOR_ST_M_M45PE20:
11837 case FLASH_5717VENDOR_ST_A_M45PE20:
11838 case FLASH_5717VENDOR_ST_25USPT:
11839 case FLASH_5717VENDOR_ST_45USPT:
11840 tp->nvram_jedecnum = JEDEC_ST;
11841 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11842 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11844 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11845 case FLASH_5717VENDOR_ST_M_M25PE20:
11846 case FLASH_5717VENDOR_ST_A_M25PE20:
11847 case FLASH_5717VENDOR_ST_M_M45PE20:
11848 case FLASH_5717VENDOR_ST_A_M45PE20:
11849 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11852 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11857 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11861 tg3_nvram_get_pagesize(tp, nvcfg1);
11862 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11863 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11866 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
11867 static void __devinit tg3_nvram_init(struct tg3 *tp)
11869 tw32_f(GRC_EEPROM_ADDR,
11870 (EEPROM_ADDR_FSM_RESET |
11871 (EEPROM_DEFAULT_CLOCK_PERIOD <<
11872 EEPROM_ADDR_CLKPERD_SHIFT)));
11876 /* Enable seeprom accesses. */
11877 tw32_f(GRC_LOCAL_CTRL,
11878 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
11881 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11882 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
11883 tp->tg3_flags |= TG3_FLAG_NVRAM;
11885 if (tg3_nvram_lock(tp)) {
11886 netdev_warn(tp->dev,
11887 "Cannot get nvram lock, %s failed\n",
11891 tg3_enable_nvram_access(tp);
11893 tp->nvram_size = 0;
11895 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
11896 tg3_get_5752_nvram_info(tp);
11897 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
11898 tg3_get_5755_nvram_info(tp);
11899 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
11900 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11901 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11902 tg3_get_5787_nvram_info(tp);
11903 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
11904 tg3_get_5761_nvram_info(tp);
11905 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11906 tg3_get_5906_nvram_info(tp);
11907 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
11908 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
11909 tg3_get_57780_nvram_info(tp);
11910 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
11911 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
11912 tg3_get_5717_nvram_info(tp);
11914 tg3_get_nvram_info(tp);
11916 if (tp->nvram_size == 0)
11917 tg3_get_nvram_size(tp);
11919 tg3_disable_nvram_access(tp);
11920 tg3_nvram_unlock(tp);
11923 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
11925 tg3_get_eeprom_size(tp);
11929 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
11930 u32 offset, u32 len, u8 *buf)
11935 for (i = 0; i < len; i += 4) {
11941 memcpy(&data, buf + i, 4);
11944 * The SEEPROM interface expects the data to always be opposite
11945 * the native endian format. We accomplish this by reversing
11946 * all the operations that would have been performed on the
11947 * data from a call to tg3_nvram_read_be32().
11949 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
11951 val = tr32(GRC_EEPROM_ADDR);
11952 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
11954 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
11956 tw32(GRC_EEPROM_ADDR, val |
11957 (0 << EEPROM_ADDR_DEVID_SHIFT) |
11958 (addr & EEPROM_ADDR_ADDR_MASK) |
11959 EEPROM_ADDR_START |
11960 EEPROM_ADDR_WRITE);
11962 for (j = 0; j < 1000; j++) {
11963 val = tr32(GRC_EEPROM_ADDR);
11965 if (val & EEPROM_ADDR_COMPLETE)
11969 if (!(val & EEPROM_ADDR_COMPLETE)) {
11978 /* offset and length are dword aligned */
11979 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
11983 u32 pagesize = tp->nvram_pagesize;
11984 u32 pagemask = pagesize - 1;
11988 tmp = kmalloc(pagesize, GFP_KERNEL);
11994 u32 phy_addr, page_off, size;
11996 phy_addr = offset & ~pagemask;
11998 for (j = 0; j < pagesize; j += 4) {
11999 ret = tg3_nvram_read_be32(tp, phy_addr + j,
12000 (__be32 *) (tmp + j));
12007 page_off = offset & pagemask;
12014 memcpy(tmp + page_off, buf, size);
12016 offset = offset + (pagesize - page_off);
12018 tg3_enable_nvram_access(tp);
12021 * Before we can erase the flash page, we need
12022 * to issue a special "write enable" command.
12024 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
12026 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
12029 /* Erase the target page */
12030 tw32(NVRAM_ADDR, phy_addr);
12032 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
12033 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
12035 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
12038 /* Issue another write enable to start the write. */
12039 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
12041 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
12044 for (j = 0; j < pagesize; j += 4) {
12047 data = *((__be32 *) (tmp + j));
12049 tw32(NVRAM_WRDATA, be32_to_cpu(data));
12051 tw32(NVRAM_ADDR, phy_addr + j);
12053 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
12057 nvram_cmd |= NVRAM_CMD_FIRST;
12058 else if (j == (pagesize - 4))
12059 nvram_cmd |= NVRAM_CMD_LAST;
12061 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
12068 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
12069 tg3_nvram_exec_cmd(tp, nvram_cmd);
12076 /* offset and length are dword aligned */
12077 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
12082 for (i = 0; i < len; i += 4, offset += 4) {
12083 u32 page_off, phy_addr, nvram_cmd;
12086 memcpy(&data, buf + i, 4);
12087 tw32(NVRAM_WRDATA, be32_to_cpu(data));
12089 page_off = offset % tp->nvram_pagesize;
12091 phy_addr = tg3_nvram_phys_addr(tp, offset);
12093 tw32(NVRAM_ADDR, phy_addr);
12095 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
12097 if (page_off == 0 || i == 0)
12098 nvram_cmd |= NVRAM_CMD_FIRST;
12099 if (page_off == (tp->nvram_pagesize - 4))
12100 nvram_cmd |= NVRAM_CMD_LAST;
12102 if (i == (len - 4))
12103 nvram_cmd |= NVRAM_CMD_LAST;
12105 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
12106 !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
12107 (tp->nvram_jedecnum == JEDEC_ST) &&
12108 (nvram_cmd & NVRAM_CMD_FIRST)) {
12110 if ((ret = tg3_nvram_exec_cmd(tp,
12111 NVRAM_CMD_WREN | NVRAM_CMD_GO |
12116 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
12117 /* We always do complete word writes to eeprom. */
12118 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
12121 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
12127 /* offset and length are dword aligned */
12128 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
12132 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
12133 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
12134 ~GRC_LCLCTRL_GPIO_OUTPUT1);
12138 if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
12139 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
12143 ret = tg3_nvram_lock(tp);
12147 tg3_enable_nvram_access(tp);
12148 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
12149 !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM))
12150 tw32(NVRAM_WRITE1, 0x406);
12152 grc_mode = tr32(GRC_MODE);
12153 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
12155 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
12156 !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
12158 ret = tg3_nvram_write_block_buffered(tp, offset, len,
12161 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
12165 grc_mode = tr32(GRC_MODE);
12166 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
12168 tg3_disable_nvram_access(tp);
12169 tg3_nvram_unlock(tp);
12172 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
12173 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
12180 struct subsys_tbl_ent {
12181 u16 subsys_vendor, subsys_devid;
12185 static struct subsys_tbl_ent subsys_id_to_phy_id[] __devinitdata = {
12186 /* Broadcom boards. */
12187 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12188 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6, TG3_PHY_ID_BCM5401 },
12189 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12190 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5, TG3_PHY_ID_BCM5701 },
12191 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12192 TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6, TG3_PHY_ID_BCM8002 },
12193 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12194 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9, 0 },
12195 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12196 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1, TG3_PHY_ID_BCM5701 },
12197 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12198 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8, TG3_PHY_ID_BCM5701 },
12199 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12200 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7, 0 },
12201 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12202 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10, TG3_PHY_ID_BCM5701 },
12203 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12204 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12, TG3_PHY_ID_BCM5701 },
12205 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12206 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1, TG3_PHY_ID_BCM5703 },
12207 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12208 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2, TG3_PHY_ID_BCM5703 },
12211 { TG3PCI_SUBVENDOR_ID_3COM,
12212 TG3PCI_SUBDEVICE_ID_3COM_3C996T, TG3_PHY_ID_BCM5401 },
12213 { TG3PCI_SUBVENDOR_ID_3COM,
12214 TG3PCI_SUBDEVICE_ID_3COM_3C996BT, TG3_PHY_ID_BCM5701 },
12215 { TG3PCI_SUBVENDOR_ID_3COM,
12216 TG3PCI_SUBDEVICE_ID_3COM_3C996SX, 0 },
12217 { TG3PCI_SUBVENDOR_ID_3COM,
12218 TG3PCI_SUBDEVICE_ID_3COM_3C1000T, TG3_PHY_ID_BCM5701 },
12219 { TG3PCI_SUBVENDOR_ID_3COM,
12220 TG3PCI_SUBDEVICE_ID_3COM_3C940BR01, TG3_PHY_ID_BCM5701 },
12223 { TG3PCI_SUBVENDOR_ID_DELL,
12224 TG3PCI_SUBDEVICE_ID_DELL_VIPER, TG3_PHY_ID_BCM5401 },
12225 { TG3PCI_SUBVENDOR_ID_DELL,
12226 TG3PCI_SUBDEVICE_ID_DELL_JAGUAR, TG3_PHY_ID_BCM5401 },
12227 { TG3PCI_SUBVENDOR_ID_DELL,
12228 TG3PCI_SUBDEVICE_ID_DELL_MERLOT, TG3_PHY_ID_BCM5411 },
12229 { TG3PCI_SUBVENDOR_ID_DELL,
12230 TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT, TG3_PHY_ID_BCM5411 },
12232 /* Compaq boards. */
12233 { TG3PCI_SUBVENDOR_ID_COMPAQ,
12234 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE, TG3_PHY_ID_BCM5701 },
12235 { TG3PCI_SUBVENDOR_ID_COMPAQ,
12236 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2, TG3_PHY_ID_BCM5701 },
12237 { TG3PCI_SUBVENDOR_ID_COMPAQ,
12238 TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING, 0 },
12239 { TG3PCI_SUBVENDOR_ID_COMPAQ,
12240 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780, TG3_PHY_ID_BCM5701 },
12241 { TG3PCI_SUBVENDOR_ID_COMPAQ,
12242 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2, TG3_PHY_ID_BCM5701 },
12245 { TG3PCI_SUBVENDOR_ID_IBM,
12246 TG3PCI_SUBDEVICE_ID_IBM_5703SAX2, 0 }
12249 static struct subsys_tbl_ent * __devinit tg3_lookup_by_subsys(struct tg3 *tp)
12253 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
12254 if ((subsys_id_to_phy_id[i].subsys_vendor ==
12255 tp->pdev->subsystem_vendor) &&
12256 (subsys_id_to_phy_id[i].subsys_devid ==
12257 tp->pdev->subsystem_device))
12258 return &subsys_id_to_phy_id[i];
12263 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
12268 /* On some early chips the SRAM cannot be accessed in D3hot state,
12269 * so need make sure we're in D0.
12271 pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
12272 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
12273 pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
12276 /* Make sure register accesses (indirect or otherwise)
12277 * will function correctly.
12279 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12280 tp->misc_host_ctrl);
12282 /* The memory arbiter has to be enabled in order for SRAM accesses
12283 * to succeed. Normally on powerup the tg3 chip firmware will make
12284 * sure it is enabled, but other entities such as system netboot
12285 * code might disable it.
12287 val = tr32(MEMARB_MODE);
12288 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
12290 tp->phy_id = TG3_PHY_ID_INVALID;
12291 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12293 /* Assume an onboard device and WOL capable by default. */
12294 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
12296 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12297 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
12298 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12299 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12301 val = tr32(VCPU_CFGSHDW);
12302 if (val & VCPU_CFGSHDW_ASPM_DBNC)
12303 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
12304 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
12305 (val & VCPU_CFGSHDW_WOL_MAGPKT))
12306 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12310 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
12311 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
12312 u32 nic_cfg, led_cfg;
12313 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
12314 int eeprom_phy_serdes = 0;
12316 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
12317 tp->nic_sram_data_cfg = nic_cfg;
12319 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
12320 ver >>= NIC_SRAM_DATA_VER_SHIFT;
12321 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
12322 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
12323 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
12324 (ver > 0) && (ver < 0x100))
12325 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
12327 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
12328 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
12330 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
12331 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
12332 eeprom_phy_serdes = 1;
12334 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
12335 if (nic_phy_id != 0) {
12336 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
12337 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
12339 eeprom_phy_id = (id1 >> 16) << 10;
12340 eeprom_phy_id |= (id2 & 0xfc00) << 16;
12341 eeprom_phy_id |= (id2 & 0x03ff) << 0;
12345 tp->phy_id = eeprom_phy_id;
12346 if (eeprom_phy_serdes) {
12347 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
12348 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
12350 tp->phy_flags |= TG3_PHYFLG_MII_SERDES;
12353 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
12354 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
12355 SHASTA_EXT_LED_MODE_MASK);
12357 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
12361 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
12362 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12365 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
12366 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12369 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
12370 tp->led_ctrl = LED_CTRL_MODE_MAC;
12372 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
12373 * read on some older 5700/5701 bootcode.
12375 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
12377 GET_ASIC_REV(tp->pci_chip_rev_id) ==
12379 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12383 case SHASTA_EXT_LED_SHARED:
12384 tp->led_ctrl = LED_CTRL_MODE_SHARED;
12385 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
12386 tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
12387 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12388 LED_CTRL_MODE_PHY_2);
12391 case SHASTA_EXT_LED_MAC:
12392 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
12395 case SHASTA_EXT_LED_COMBO:
12396 tp->led_ctrl = LED_CTRL_MODE_COMBO;
12397 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
12398 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12399 LED_CTRL_MODE_PHY_2);
12404 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12405 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
12406 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
12407 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12409 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
12410 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12412 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
12413 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
12414 if ((tp->pdev->subsystem_vendor ==
12415 PCI_VENDOR_ID_ARIMA) &&
12416 (tp->pdev->subsystem_device == 0x205a ||
12417 tp->pdev->subsystem_device == 0x2063))
12418 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12420 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12421 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12424 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
12425 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
12426 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
12427 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
12430 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
12431 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
12432 tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
12434 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES &&
12435 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
12436 tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
12438 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
12439 (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
12440 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12442 if (cfg2 & (1 << 17))
12443 tp->phy_flags |= TG3_PHYFLG_CAPACITIVE_COUPLING;
12445 /* serdes signal pre-emphasis in register 0x590 set by */
12446 /* bootcode if bit 18 is set */
12447 if (cfg2 & (1 << 18))
12448 tp->phy_flags |= TG3_PHYFLG_SERDES_PREEMPHASIS;
12450 if (((tp->tg3_flags3 & TG3_FLG3_5717_PLUS) ||
12451 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
12452 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX))) &&
12453 (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
12454 tp->phy_flags |= TG3_PHYFLG_ENABLE_APD;
12456 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
12457 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
12458 !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) {
12461 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
12462 if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
12463 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
12466 if (cfg4 & NIC_SRAM_RGMII_INBAND_DISABLE)
12467 tp->tg3_flags3 |= TG3_FLG3_RGMII_INBAND_DISABLE;
12468 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
12469 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
12470 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
12471 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
12474 device_init_wakeup(&tp->pdev->dev, tp->tg3_flags & TG3_FLAG_WOL_CAP);
12475 device_set_wakeup_enable(&tp->pdev->dev,
12476 tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
12479 static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
12484 tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
12485 tw32(OTP_CTRL, cmd);
12487 /* Wait for up to 1 ms for command to execute. */
12488 for (i = 0; i < 100; i++) {
12489 val = tr32(OTP_STATUS);
12490 if (val & OTP_STATUS_CMD_DONE)
12495 return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
12498 /* Read the gphy configuration from the OTP region of the chip. The gphy
12499 * configuration is a 32-bit value that straddles the alignment boundary.
12500 * We do two 32-bit reads and then shift and merge the results.
12502 static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
12504 u32 bhalf_otp, thalf_otp;
12506 tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
12508 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
12511 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
12513 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12516 thalf_otp = tr32(OTP_READ_DATA);
12518 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
12520 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12523 bhalf_otp = tr32(OTP_READ_DATA);
12525 return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
12528 static int __devinit tg3_phy_probe(struct tg3 *tp)
12530 u32 hw_phy_id_1, hw_phy_id_2;
12531 u32 hw_phy_id, hw_phy_id_masked;
12534 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
12535 return tg3_phy_init(tp);
12537 /* Reading the PHY ID register can conflict with ASF
12538 * firmware access to the PHY hardware.
12541 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12542 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
12543 hw_phy_id = hw_phy_id_masked = TG3_PHY_ID_INVALID;
12545 /* Now read the physical PHY_ID from the chip and verify
12546 * that it is sane. If it doesn't look good, we fall back
12547 * to either the hard-coded table based PHY_ID and failing
12548 * that the value found in the eeprom area.
12550 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
12551 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
12553 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
12554 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
12555 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
12557 hw_phy_id_masked = hw_phy_id & TG3_PHY_ID_MASK;
12560 if (!err && TG3_KNOWN_PHY_ID(hw_phy_id_masked)) {
12561 tp->phy_id = hw_phy_id;
12562 if (hw_phy_id_masked == TG3_PHY_ID_BCM8002)
12563 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
12565 tp->phy_flags &= ~TG3_PHYFLG_PHY_SERDES;
12567 if (tp->phy_id != TG3_PHY_ID_INVALID) {
12568 /* Do nothing, phy ID already set up in
12569 * tg3_get_eeprom_hw_cfg().
12572 struct subsys_tbl_ent *p;
12574 /* No eeprom signature? Try the hardcoded
12575 * subsys device table.
12577 p = tg3_lookup_by_subsys(tp);
12581 tp->phy_id = p->phy_id;
12583 tp->phy_id == TG3_PHY_ID_BCM8002)
12584 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
12588 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
12589 ((tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 &&
12590 tp->pci_chip_rev_id != CHIPREV_ID_5717_A0) ||
12591 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12592 tp->pci_chip_rev_id != CHIPREV_ID_57765_A0)))
12593 tp->phy_flags |= TG3_PHYFLG_EEE_CAP;
12595 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
12596 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
12597 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
12598 u32 bmsr, adv_reg, tg3_ctrl, mask;
12600 tg3_readphy(tp, MII_BMSR, &bmsr);
12601 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
12602 (bmsr & BMSR_LSTATUS))
12603 goto skip_phy_reset;
12605 err = tg3_phy_reset(tp);
12609 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
12610 ADVERTISE_100HALF | ADVERTISE_100FULL |
12611 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
12613 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
12614 tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
12615 MII_TG3_CTRL_ADV_1000_FULL);
12616 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12617 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
12618 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
12619 MII_TG3_CTRL_ENABLE_AS_MASTER);
12622 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
12623 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
12624 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
12625 if (!tg3_copper_is_advertising_all(tp, mask)) {
12626 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12628 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
12629 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12631 tg3_writephy(tp, MII_BMCR,
12632 BMCR_ANENABLE | BMCR_ANRESTART);
12634 tg3_phy_set_wirespeed(tp);
12636 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12637 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
12638 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12642 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
12643 err = tg3_init_5401phy_dsp(tp);
12647 err = tg3_init_5401phy_dsp(tp);
12650 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
12651 tp->link_config.advertising =
12652 (ADVERTISED_1000baseT_Half |
12653 ADVERTISED_1000baseT_Full |
12654 ADVERTISED_Autoneg |
12656 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
12657 tp->link_config.advertising &=
12658 ~(ADVERTISED_1000baseT_Half |
12659 ADVERTISED_1000baseT_Full);
12664 static void __devinit tg3_read_vpd(struct tg3 *tp)
12667 unsigned int block_end, rosize, len;
12671 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
12672 tg3_nvram_read(tp, 0x0, &magic))
12675 vpd_data = kmalloc(TG3_NVM_VPD_LEN, GFP_KERNEL);
12679 if (magic == TG3_EEPROM_MAGIC) {
12680 for (i = 0; i < TG3_NVM_VPD_LEN; i += 4) {
12683 /* The data is in little-endian format in NVRAM.
12684 * Use the big-endian read routines to preserve
12685 * the byte order as it exists in NVRAM.
12687 if (tg3_nvram_read_be32(tp, TG3_NVM_VPD_OFF + i, &tmp))
12688 goto out_not_found;
12690 memcpy(&vpd_data[i], &tmp, sizeof(tmp));
12694 unsigned int pos = 0;
12696 for (; pos < TG3_NVM_VPD_LEN && i < 3; i++, pos += cnt) {
12697 cnt = pci_read_vpd(tp->pdev, pos,
12698 TG3_NVM_VPD_LEN - pos,
12700 if (cnt == -ETIMEDOUT || -EINTR)
12703 goto out_not_found;
12705 if (pos != TG3_NVM_VPD_LEN)
12706 goto out_not_found;
12709 i = pci_vpd_find_tag(vpd_data, 0, TG3_NVM_VPD_LEN,
12710 PCI_VPD_LRDT_RO_DATA);
12712 goto out_not_found;
12714 rosize = pci_vpd_lrdt_size(&vpd_data[i]);
12715 block_end = i + PCI_VPD_LRDT_TAG_SIZE + rosize;
12716 i += PCI_VPD_LRDT_TAG_SIZE;
12718 if (block_end > TG3_NVM_VPD_LEN)
12719 goto out_not_found;
12721 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12722 PCI_VPD_RO_KEYWORD_MFR_ID);
12724 len = pci_vpd_info_field_size(&vpd_data[j]);
12726 j += PCI_VPD_INFO_FLD_HDR_SIZE;
12727 if (j + len > block_end || len != 4 ||
12728 memcmp(&vpd_data[j], "1028", 4))
12731 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12732 PCI_VPD_RO_KEYWORD_VENDOR0);
12736 len = pci_vpd_info_field_size(&vpd_data[j]);
12738 j += PCI_VPD_INFO_FLD_HDR_SIZE;
12739 if (j + len > block_end)
12742 memcpy(tp->fw_ver, &vpd_data[j], len);
12743 strncat(tp->fw_ver, " bc ", TG3_NVM_VPD_LEN - len - 1);
12747 i = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12748 PCI_VPD_RO_KEYWORD_PARTNO);
12750 goto out_not_found;
12752 len = pci_vpd_info_field_size(&vpd_data[i]);
12754 i += PCI_VPD_INFO_FLD_HDR_SIZE;
12755 if (len > TG3_BPN_SIZE ||
12756 (len + i) > TG3_NVM_VPD_LEN)
12757 goto out_not_found;
12759 memcpy(tp->board_part_number, &vpd_data[i], len);
12763 if (tp->board_part_number[0])
12767 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
12768 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717)
12769 strcpy(tp->board_part_number, "BCM5717");
12770 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718)
12771 strcpy(tp->board_part_number, "BCM5718");
12774 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
12775 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
12776 strcpy(tp->board_part_number, "BCM57780");
12777 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
12778 strcpy(tp->board_part_number, "BCM57760");
12779 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
12780 strcpy(tp->board_part_number, "BCM57790");
12781 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
12782 strcpy(tp->board_part_number, "BCM57788");
12785 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
12786 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761)
12787 strcpy(tp->board_part_number, "BCM57761");
12788 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765)
12789 strcpy(tp->board_part_number, "BCM57765");
12790 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781)
12791 strcpy(tp->board_part_number, "BCM57781");
12792 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785)
12793 strcpy(tp->board_part_number, "BCM57785");
12794 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791)
12795 strcpy(tp->board_part_number, "BCM57791");
12796 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
12797 strcpy(tp->board_part_number, "BCM57795");
12800 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12801 strcpy(tp->board_part_number, "BCM95906");
12804 strcpy(tp->board_part_number, "none");
12808 static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
12812 if (tg3_nvram_read(tp, offset, &val) ||
12813 (val & 0xfc000000) != 0x0c000000 ||
12814 tg3_nvram_read(tp, offset + 4, &val) ||
12821 static void __devinit tg3_read_bc_ver(struct tg3 *tp)
12823 u32 val, offset, start, ver_offset;
12825 bool newver = false;
12827 if (tg3_nvram_read(tp, 0xc, &offset) ||
12828 tg3_nvram_read(tp, 0x4, &start))
12831 offset = tg3_nvram_logical_addr(tp, offset);
12833 if (tg3_nvram_read(tp, offset, &val))
12836 if ((val & 0xfc000000) == 0x0c000000) {
12837 if (tg3_nvram_read(tp, offset + 4, &val))
12844 dst_off = strlen(tp->fw_ver);
12847 if (TG3_VER_SIZE - dst_off < 16 ||
12848 tg3_nvram_read(tp, offset + 8, &ver_offset))
12851 offset = offset + ver_offset - start;
12852 for (i = 0; i < 16; i += 4) {
12854 if (tg3_nvram_read_be32(tp, offset + i, &v))
12857 memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v));
12862 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
12865 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
12866 TG3_NVM_BCVER_MAJSFT;
12867 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
12868 snprintf(&tp->fw_ver[dst_off], TG3_VER_SIZE - dst_off,
12869 "v%d.%02d", major, minor);
12873 static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
12875 u32 val, major, minor;
12877 /* Use native endian representation */
12878 if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
12881 major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
12882 TG3_NVM_HWSB_CFG1_MAJSFT;
12883 minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
12884 TG3_NVM_HWSB_CFG1_MINSFT;
12886 snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
12889 static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
12891 u32 offset, major, minor, build;
12893 strncat(tp->fw_ver, "sb", TG3_VER_SIZE - strlen(tp->fw_ver) - 1);
12895 if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
12898 switch (val & TG3_EEPROM_SB_REVISION_MASK) {
12899 case TG3_EEPROM_SB_REVISION_0:
12900 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
12902 case TG3_EEPROM_SB_REVISION_2:
12903 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
12905 case TG3_EEPROM_SB_REVISION_3:
12906 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
12908 case TG3_EEPROM_SB_REVISION_4:
12909 offset = TG3_EEPROM_SB_F1R4_EDH_OFF;
12911 case TG3_EEPROM_SB_REVISION_5:
12912 offset = TG3_EEPROM_SB_F1R5_EDH_OFF;
12914 case TG3_EEPROM_SB_REVISION_6:
12915 offset = TG3_EEPROM_SB_F1R6_EDH_OFF;
12921 if (tg3_nvram_read(tp, offset, &val))
12924 build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
12925 TG3_EEPROM_SB_EDH_BLD_SHFT;
12926 major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
12927 TG3_EEPROM_SB_EDH_MAJ_SHFT;
12928 minor = val & TG3_EEPROM_SB_EDH_MIN_MASK;
12930 if (minor > 99 || build > 26)
12933 offset = strlen(tp->fw_ver);
12934 snprintf(&tp->fw_ver[offset], TG3_VER_SIZE - offset,
12935 " v%d.%02d", major, minor);
12938 offset = strlen(tp->fw_ver);
12939 if (offset < TG3_VER_SIZE - 1)
12940 tp->fw_ver[offset] = 'a' + build - 1;
12944 static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
12946 u32 val, offset, start;
12949 for (offset = TG3_NVM_DIR_START;
12950 offset < TG3_NVM_DIR_END;
12951 offset += TG3_NVM_DIRENT_SIZE) {
12952 if (tg3_nvram_read(tp, offset, &val))
12955 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
12959 if (offset == TG3_NVM_DIR_END)
12962 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
12963 start = 0x08000000;
12964 else if (tg3_nvram_read(tp, offset - 4, &start))
12967 if (tg3_nvram_read(tp, offset + 4, &offset) ||
12968 !tg3_fw_img_is_valid(tp, offset) ||
12969 tg3_nvram_read(tp, offset + 8, &val))
12972 offset += val - start;
12974 vlen = strlen(tp->fw_ver);
12976 tp->fw_ver[vlen++] = ',';
12977 tp->fw_ver[vlen++] = ' ';
12979 for (i = 0; i < 4; i++) {
12981 if (tg3_nvram_read_be32(tp, offset, &v))
12984 offset += sizeof(v);
12986 if (vlen > TG3_VER_SIZE - sizeof(v)) {
12987 memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
12991 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
12996 static void __devinit tg3_read_dash_ver(struct tg3 *tp)
13002 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) ||
13003 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
13006 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
13007 if (apedata != APE_SEG_SIG_MAGIC)
13010 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
13011 if (!(apedata & APE_FW_STATUS_READY))
13014 apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
13016 if (tg3_ape_read32(tp, TG3_APE_FW_FEATURES) & TG3_APE_FW_FEATURE_NCSI) {
13017 tp->tg3_flags3 |= TG3_FLG3_APE_HAS_NCSI;
13023 vlen = strlen(tp->fw_ver);
13025 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " %s v%d.%d.%d.%d",
13027 (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
13028 (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
13029 (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
13030 (apedata & APE_FW_VERSION_BLDMSK));
13033 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
13036 bool vpd_vers = false;
13038 if (tp->fw_ver[0] != 0)
13041 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) {
13042 strcat(tp->fw_ver, "sb");
13046 if (tg3_nvram_read(tp, 0, &val))
13049 if (val == TG3_EEPROM_MAGIC)
13050 tg3_read_bc_ver(tp);
13051 else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
13052 tg3_read_sb_ver(tp, val);
13053 else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
13054 tg3_read_hwsb_ver(tp);
13058 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
13059 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) || vpd_vers)
13062 tg3_read_mgmtfw_ver(tp);
13065 tp->fw_ver[TG3_VER_SIZE - 1] = 0;
13068 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
13070 static void inline vlan_features_add(struct net_device *dev, unsigned long flags)
13072 #if TG3_VLAN_TAG_USED
13073 dev->vlan_features |= flags;
13077 static inline u32 tg3_rx_ret_ring_size(struct tg3 *tp)
13079 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13080 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
13082 else if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
13083 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
13089 static int __devinit tg3_get_invariants(struct tg3 *tp)
13091 static struct pci_device_id write_reorder_chipsets[] = {
13092 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
13093 PCI_DEVICE_ID_AMD_FE_GATE_700C) },
13094 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
13095 PCI_DEVICE_ID_AMD_8131_BRIDGE) },
13096 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
13097 PCI_DEVICE_ID_VIA_8385_0) },
13101 u32 pci_state_reg, grc_misc_cfg;
13106 /* Force memory write invalidate off. If we leave it on,
13107 * then on 5700_BX chips we have to enable a workaround.
13108 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
13109 * to match the cacheline size. The Broadcom driver have this
13110 * workaround but turns MWI off all the times so never uses
13111 * it. This seems to suggest that the workaround is insufficient.
13113 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13114 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
13115 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13117 /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
13118 * has the register indirect write enable bit set before
13119 * we try to access any of the MMIO registers. It is also
13120 * critical that the PCI-X hw workaround situation is decided
13121 * before that as well.
13123 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13126 tp->pci_chip_rev_id = (misc_ctrl_reg >>
13127 MISC_HOST_CTRL_CHIPREV_SHIFT);
13128 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
13129 u32 prod_id_asic_rev;
13131 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
13132 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
13133 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719)
13134 pci_read_config_dword(tp->pdev,
13135 TG3PCI_GEN2_PRODID_ASICREV,
13136 &prod_id_asic_rev);
13137 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 ||
13138 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 ||
13139 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 ||
13140 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 ||
13141 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
13142 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
13143 pci_read_config_dword(tp->pdev,
13144 TG3PCI_GEN15_PRODID_ASICREV,
13145 &prod_id_asic_rev);
13147 pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
13148 &prod_id_asic_rev);
13150 tp->pci_chip_rev_id = prod_id_asic_rev;
13153 /* Wrong chip ID in 5752 A0. This code can be removed later
13154 * as A0 is not in production.
13156 if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
13157 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
13159 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
13160 * we need to disable memory and use config. cycles
13161 * only to access all registers. The 5702/03 chips
13162 * can mistakenly decode the special cycles from the
13163 * ICH chipsets as memory write cycles, causing corruption
13164 * of register and memory space. Only certain ICH bridges
13165 * will drive special cycles with non-zero data during the
13166 * address phase which can fall within the 5703's address
13167 * range. This is not an ICH bug as the PCI spec allows
13168 * non-zero address during special cycles. However, only
13169 * these ICH bridges are known to drive non-zero addresses
13170 * during special cycles.
13172 * Since special cycles do not cross PCI bridges, we only
13173 * enable this workaround if the 5703 is on the secondary
13174 * bus of these ICH bridges.
13176 if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
13177 (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
13178 static struct tg3_dev_id {
13182 } ich_chipsets[] = {
13183 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
13185 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
13187 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
13189 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
13193 struct tg3_dev_id *pci_id = &ich_chipsets[0];
13194 struct pci_dev *bridge = NULL;
13196 while (pci_id->vendor != 0) {
13197 bridge = pci_get_device(pci_id->vendor, pci_id->device,
13203 if (pci_id->rev != PCI_ANY_ID) {
13204 if (bridge->revision > pci_id->rev)
13207 if (bridge->subordinate &&
13208 (bridge->subordinate->number ==
13209 tp->pdev->bus->number)) {
13211 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
13212 pci_dev_put(bridge);
13218 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
13219 static struct tg3_dev_id {
13222 } bridge_chipsets[] = {
13223 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
13224 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
13227 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
13228 struct pci_dev *bridge = NULL;
13230 while (pci_id->vendor != 0) {
13231 bridge = pci_get_device(pci_id->vendor,
13238 if (bridge->subordinate &&
13239 (bridge->subordinate->number <=
13240 tp->pdev->bus->number) &&
13241 (bridge->subordinate->subordinate >=
13242 tp->pdev->bus->number)) {
13243 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
13244 pci_dev_put(bridge);
13250 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
13251 * DMA addresses > 40-bit. This bridge may have other additional
13252 * 57xx devices behind it in some 4-port NIC designs for example.
13253 * Any tg3 device found behind the bridge will also need the 40-bit
13256 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
13257 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
13258 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
13259 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
13260 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
13262 struct pci_dev *bridge = NULL;
13265 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
13266 PCI_DEVICE_ID_SERVERWORKS_EPB,
13268 if (bridge && bridge->subordinate &&
13269 (bridge->subordinate->number <=
13270 tp->pdev->bus->number) &&
13271 (bridge->subordinate->subordinate >=
13272 tp->pdev->bus->number)) {
13273 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
13274 pci_dev_put(bridge);
13280 /* Initialize misc host control in PCI block. */
13281 tp->misc_host_ctrl |= (misc_ctrl_reg &
13282 MISC_HOST_CTRL_CHIPREV);
13283 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13284 tp->misc_host_ctrl);
13286 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
13287 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
13288 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
13289 tp->pdev_peer = tg3_find_peer(tp);
13291 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13292 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
13293 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13294 tp->tg3_flags3 |= TG3_FLG3_5717_PLUS;
13296 /* Intentionally exclude ASIC_REV_5906 */
13297 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13298 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
13299 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13300 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13301 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13302 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13303 (tp->tg3_flags3 & TG3_FLG3_5717_PLUS))
13304 tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
13306 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13307 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13308 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
13309 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13310 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
13311 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
13313 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
13314 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
13315 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
13317 /* 5700 B0 chips do not support checksumming correctly due
13318 * to hardware bugs.
13320 if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
13321 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
13323 unsigned long features = NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_GRO;
13325 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
13326 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
13327 features |= NETIF_F_IPV6_CSUM;
13328 tp->dev->features |= features;
13329 vlan_features_add(tp->dev, features);
13332 /* Determine TSO capabilities */
13333 if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
13334 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_3;
13335 else if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13336 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13337 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
13338 else if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
13339 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
13340 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 &&
13341 tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
13342 tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
13343 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13344 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13345 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
13346 tp->tg3_flags2 |= TG3_FLG2_TSO_BUG;
13347 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
13348 tp->fw_needed = FIRMWARE_TG3TSO5;
13350 tp->fw_needed = FIRMWARE_TG3TSO;
13355 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
13356 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
13357 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
13358 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
13359 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
13360 tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
13361 tp->pdev_peer == tp->pdev))
13362 tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
13364 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13365 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13366 tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
13369 if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
13370 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSIX;
13371 tp->irq_max = TG3_IRQ_MAX_VECS;
13375 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13376 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
13377 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13378 tp->tg3_flags3 |= TG3_FLG3_SHORT_DMA_BUG;
13379 else if (!(tp->tg3_flags3 & TG3_FLG3_5755_PLUS)) {
13380 tp->tg3_flags3 |= TG3_FLG3_4G_DMA_BNDRY_BUG;
13381 tp->tg3_flags3 |= TG3_FLG3_40BIT_DMA_LIMIT_BUG;
13384 if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
13385 tp->tg3_flags3 |= TG3_FLG3_USE_JUMBO_BDFLAG;
13387 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
13388 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
13389 (tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG))
13390 tp->tg3_flags |= TG3_FLAG_JUMBO_CAPABLE;
13392 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13395 tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
13396 if (tp->pcie_cap != 0) {
13399 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
13401 tp->pcie_readrq = 4096;
13402 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
13405 pci_read_config_word(tp->pdev,
13406 tp->pcie_cap + PCI_EXP_LNKSTA,
13408 switch (word & PCI_EXP_LNKSTA_CLS) {
13409 case PCI_EXP_LNKSTA_CLS_2_5GB:
13410 word &= PCI_EXP_LNKSTA_NLW;
13411 word >>= PCI_EXP_LNKSTA_NLW_SHIFT;
13414 tp->pcie_readrq = 2048;
13417 tp->pcie_readrq = 1024;
13422 case PCI_EXP_LNKSTA_CLS_5_0GB:
13423 word &= PCI_EXP_LNKSTA_NLW;
13424 word >>= PCI_EXP_LNKSTA_NLW_SHIFT;
13427 tp->pcie_readrq = 2048;
13430 tp->pcie_readrq = 1024;
13433 tp->pcie_readrq = 512;
13439 pcie_set_readrq(tp->pdev, tp->pcie_readrq);
13441 pci_read_config_word(tp->pdev,
13442 tp->pcie_cap + PCI_EXP_LNKCTL,
13444 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
13445 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13446 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
13447 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13448 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13449 tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
13450 tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
13451 tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
13452 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5717_A0) {
13453 tp->tg3_flags3 |= TG3_FLG3_L1PLLPD_EN;
13455 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
13456 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
13457 } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
13458 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13459 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
13460 if (!tp->pcix_cap) {
13461 dev_err(&tp->pdev->dev,
13462 "Cannot find PCI-X capability, aborting\n");
13466 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
13467 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
13470 /* If we have an AMD 762 or VIA K8T800 chipset, write
13471 * reordering to the mailbox registers done by the host
13472 * controller can cause major troubles. We read back from
13473 * every mailbox register write to force the writes to be
13474 * posted to the chip in order.
13476 if (pci_dev_present(write_reorder_chipsets) &&
13477 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13478 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
13480 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
13481 &tp->pci_cacheline_sz);
13482 pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13483 &tp->pci_lat_timer);
13484 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13485 tp->pci_lat_timer < 64) {
13486 tp->pci_lat_timer = 64;
13487 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13488 tp->pci_lat_timer);
13491 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
13492 /* 5700 BX chips need to have their TX producer index
13493 * mailboxes written twice to workaround a bug.
13495 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
13497 /* If we are in PCI-X mode, enable register write workaround.
13499 * The workaround is to use indirect register accesses
13500 * for all chip writes not to mailbox registers.
13502 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
13505 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13507 /* The chip can have it's power management PCI config
13508 * space registers clobbered due to this bug.
13509 * So explicitly force the chip into D0 here.
13511 pci_read_config_dword(tp->pdev,
13512 tp->pm_cap + PCI_PM_CTRL,
13514 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
13515 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
13516 pci_write_config_dword(tp->pdev,
13517 tp->pm_cap + PCI_PM_CTRL,
13520 /* Also, force SERR#/PERR# in PCI command. */
13521 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13522 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
13523 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13527 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
13528 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
13529 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
13530 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
13532 /* Chip-specific fixup from Broadcom driver */
13533 if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
13534 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
13535 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
13536 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
13539 /* Default fast path register access methods */
13540 tp->read32 = tg3_read32;
13541 tp->write32 = tg3_write32;
13542 tp->read32_mbox = tg3_read32;
13543 tp->write32_mbox = tg3_write32;
13544 tp->write32_tx_mbox = tg3_write32;
13545 tp->write32_rx_mbox = tg3_write32;
13547 /* Various workaround register access methods */
13548 if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
13549 tp->write32 = tg3_write_indirect_reg32;
13550 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
13551 ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
13552 tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
13554 * Back to back register writes can cause problems on these
13555 * chips, the workaround is to read back all reg writes
13556 * except those to mailbox regs.
13558 * See tg3_write_indirect_reg32().
13560 tp->write32 = tg3_write_flush_reg32;
13563 if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
13564 (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
13565 tp->write32_tx_mbox = tg3_write32_tx_mbox;
13566 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
13567 tp->write32_rx_mbox = tg3_write_flush_reg32;
13570 if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
13571 tp->read32 = tg3_read_indirect_reg32;
13572 tp->write32 = tg3_write_indirect_reg32;
13573 tp->read32_mbox = tg3_read_indirect_mbox;
13574 tp->write32_mbox = tg3_write_indirect_mbox;
13575 tp->write32_tx_mbox = tg3_write_indirect_mbox;
13576 tp->write32_rx_mbox = tg3_write_indirect_mbox;
13581 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13582 pci_cmd &= ~PCI_COMMAND_MEMORY;
13583 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13585 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13586 tp->read32_mbox = tg3_read32_mbox_5906;
13587 tp->write32_mbox = tg3_write32_mbox_5906;
13588 tp->write32_tx_mbox = tg3_write32_mbox_5906;
13589 tp->write32_rx_mbox = tg3_write32_mbox_5906;
13592 if (tp->write32 == tg3_write_indirect_reg32 ||
13593 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13594 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13595 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
13596 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
13598 /* Get eeprom hw config before calling tg3_set_power_state().
13599 * In particular, the TG3_FLG2_IS_NIC flag must be
13600 * determined before calling tg3_set_power_state() so that
13601 * we know whether or not to switch out of Vaux power.
13602 * When the flag is set, it means that GPIO1 is used for eeprom
13603 * write protect and also implies that it is a LOM where GPIOs
13604 * are not used to switch power.
13606 tg3_get_eeprom_hw_cfg(tp);
13608 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
13609 /* Allow reads and writes to the
13610 * APE register and memory space.
13612 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
13613 PCISTATE_ALLOW_APE_SHMEM_WR |
13614 PCISTATE_ALLOW_APE_PSPACE_WR;
13615 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
13619 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13620 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13621 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13622 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13623 (tp->tg3_flags3 & TG3_FLG3_5717_PLUS))
13624 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
13626 /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
13627 * GPIO1 driven high will bring 5700's external PHY out of reset.
13628 * It is also used as eeprom write protect on LOMs.
13630 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
13631 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13632 (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
13633 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
13634 GRC_LCLCTRL_GPIO_OUTPUT1);
13635 /* Unused GPIO3 must be driven as output on 5752 because there
13636 * are no pull-up resistors on unused GPIO pins.
13638 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
13639 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
13641 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13642 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13643 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13644 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13646 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
13647 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
13648 /* Turn off the debug UART. */
13649 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13650 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
13651 /* Keep VMain power. */
13652 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
13653 GRC_LCLCTRL_GPIO_OUTPUT0;
13656 /* Force the chip into D0. */
13657 err = tg3_set_power_state(tp, PCI_D0);
13659 dev_err(&tp->pdev->dev, "Transition to D0 failed\n");
13663 /* Derive initial jumbo mode from MTU assigned in
13664 * ether_setup() via the alloc_etherdev() call
13666 if (tp->dev->mtu > ETH_DATA_LEN &&
13667 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
13668 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
13670 /* Determine WakeOnLan speed to use. */
13671 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13672 tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
13673 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
13674 tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
13675 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
13677 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
13680 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13681 tp->phy_flags |= TG3_PHYFLG_IS_FET;
13683 /* A few boards don't want Ethernet@WireSpeed phy feature */
13684 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13685 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
13686 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
13687 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
13688 (tp->phy_flags & TG3_PHYFLG_IS_FET) ||
13689 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
13690 tp->phy_flags |= TG3_PHYFLG_NO_ETH_WIRE_SPEED;
13692 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
13693 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
13694 tp->phy_flags |= TG3_PHYFLG_ADC_BUG;
13695 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
13696 tp->phy_flags |= TG3_PHYFLG_5704_A0_BUG;
13698 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
13699 !(tp->phy_flags & TG3_PHYFLG_IS_FET) &&
13700 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
13701 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 &&
13702 !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) {
13703 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13704 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
13705 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13706 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
13707 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
13708 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
13709 tp->phy_flags |= TG3_PHYFLG_JITTER_BUG;
13710 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
13711 tp->phy_flags |= TG3_PHYFLG_ADJUST_TRIM;
13713 tp->phy_flags |= TG3_PHYFLG_BER_BUG;
13716 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13717 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
13718 tp->phy_otp = tg3_read_otp_phycfg(tp);
13719 if (tp->phy_otp == 0)
13720 tp->phy_otp = TG3_OTP_DEFAULT;
13723 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
13724 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
13726 tp->mi_mode = MAC_MI_MODE_BASE;
13728 tp->coalesce_mode = 0;
13729 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
13730 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
13731 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
13733 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13734 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
13735 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
13737 err = tg3_mdio_init(tp);
13741 /* Initialize data/descriptor byte/word swapping. */
13742 val = tr32(GRC_MODE);
13743 val &= GRC_MODE_HOST_STACKUP;
13744 tw32(GRC_MODE, val | tp->grc_mode);
13746 tg3_switch_clocks(tp);
13748 /* Clear this out for sanity. */
13749 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
13751 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13753 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
13754 (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
13755 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
13757 if (chiprevid == CHIPREV_ID_5701_A0 ||
13758 chiprevid == CHIPREV_ID_5701_B0 ||
13759 chiprevid == CHIPREV_ID_5701_B2 ||
13760 chiprevid == CHIPREV_ID_5701_B5) {
13761 void __iomem *sram_base;
13763 /* Write some dummy words into the SRAM status block
13764 * area, see if it reads back correctly. If the return
13765 * value is bad, force enable the PCIX workaround.
13767 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
13769 writel(0x00000000, sram_base);
13770 writel(0x00000000, sram_base + 4);
13771 writel(0xffffffff, sram_base + 4);
13772 if (readl(sram_base) != 0x00000000)
13773 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13778 tg3_nvram_init(tp);
13780 grc_misc_cfg = tr32(GRC_MISC_CFG);
13781 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
13783 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13784 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
13785 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
13786 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
13788 if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
13789 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
13790 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
13791 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
13792 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
13793 HOSTCC_MODE_CLRTICK_TXBD);
13795 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
13796 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13797 tp->misc_host_ctrl);
13800 /* Preserve the APE MAC_MODE bits */
13801 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
13802 tp->mac_mode = MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
13804 tp->mac_mode = TG3_DEF_MAC_MODE;
13806 /* these are limited to 10/100 only */
13807 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13808 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
13809 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13810 tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13811 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
13812 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
13813 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
13814 (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13815 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
13816 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
13817 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
13818 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
13819 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
13820 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 ||
13821 (tp->phy_flags & TG3_PHYFLG_IS_FET))
13822 tp->phy_flags |= TG3_PHYFLG_10_100_ONLY;
13824 err = tg3_phy_probe(tp);
13826 dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err);
13827 /* ... but do not return immediately ... */
13832 tg3_read_fw_ver(tp);
13834 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
13835 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
13837 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13838 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
13840 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
13843 /* 5700 {AX,BX} chips have a broken status block link
13844 * change bit implementation, so we must use the
13845 * status register in those cases.
13847 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13848 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
13850 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
13852 /* The led_ctrl is set during tg3_phy_probe, here we might
13853 * have to force the link status polling mechanism based
13854 * upon subsystem IDs.
13856 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
13857 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13858 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
13859 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
13860 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
13863 /* For all SERDES we poll the MAC status register. */
13864 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
13865 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
13867 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
13869 tp->rx_offset = NET_IP_ALIGN + TG3_RX_HEADROOM;
13870 tp->rx_copy_thresh = TG3_RX_COPY_THRESHOLD;
13871 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13872 (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0) {
13873 tp->rx_offset -= NET_IP_ALIGN;
13874 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
13875 tp->rx_copy_thresh = ~(u16)0;
13879 tp->rx_std_ring_mask = TG3_RX_STD_RING_SIZE(tp) - 1;
13880 tp->rx_jmb_ring_mask = TG3_RX_JMB_RING_SIZE(tp) - 1;
13881 tp->rx_ret_ring_mask = tg3_rx_ret_ring_size(tp) - 1;
13883 tp->rx_std_max_post = tp->rx_std_ring_mask + 1;
13885 /* Increment the rx prod index on the rx std ring by at most
13886 * 8 for these chips to workaround hw errata.
13888 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13889 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13890 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
13891 tp->rx_std_max_post = 8;
13893 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
13894 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
13895 PCIE_PWR_MGMT_L1_THRESH_MSK;
13900 #ifdef CONFIG_SPARC
13901 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
13903 struct net_device *dev = tp->dev;
13904 struct pci_dev *pdev = tp->pdev;
13905 struct device_node *dp = pci_device_to_OF_node(pdev);
13906 const unsigned char *addr;
13909 addr = of_get_property(dp, "local-mac-address", &len);
13910 if (addr && len == 6) {
13911 memcpy(dev->dev_addr, addr, 6);
13912 memcpy(dev->perm_addr, dev->dev_addr, 6);
13918 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
13920 struct net_device *dev = tp->dev;
13922 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
13923 memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
13928 static int __devinit tg3_get_device_address(struct tg3 *tp)
13930 struct net_device *dev = tp->dev;
13931 u32 hi, lo, mac_offset;
13934 #ifdef CONFIG_SPARC
13935 if (!tg3_get_macaddr_sparc(tp))
13940 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
13941 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13942 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
13944 if (tg3_nvram_lock(tp))
13945 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
13947 tg3_nvram_unlock(tp);
13948 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13949 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
13950 if (PCI_FUNC(tp->pdev->devfn) & 1)
13952 if (PCI_FUNC(tp->pdev->devfn) > 1)
13953 mac_offset += 0x18c;
13954 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13957 /* First try to get it from MAC address mailbox. */
13958 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
13959 if ((hi >> 16) == 0x484b) {
13960 dev->dev_addr[0] = (hi >> 8) & 0xff;
13961 dev->dev_addr[1] = (hi >> 0) & 0xff;
13963 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
13964 dev->dev_addr[2] = (lo >> 24) & 0xff;
13965 dev->dev_addr[3] = (lo >> 16) & 0xff;
13966 dev->dev_addr[4] = (lo >> 8) & 0xff;
13967 dev->dev_addr[5] = (lo >> 0) & 0xff;
13969 /* Some old bootcode may report a 0 MAC address in SRAM */
13970 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
13973 /* Next, try NVRAM. */
13974 if (!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) &&
13975 !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
13976 !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
13977 memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
13978 memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
13980 /* Finally just fetch it out of the MAC control regs. */
13982 hi = tr32(MAC_ADDR_0_HIGH);
13983 lo = tr32(MAC_ADDR_0_LOW);
13985 dev->dev_addr[5] = lo & 0xff;
13986 dev->dev_addr[4] = (lo >> 8) & 0xff;
13987 dev->dev_addr[3] = (lo >> 16) & 0xff;
13988 dev->dev_addr[2] = (lo >> 24) & 0xff;
13989 dev->dev_addr[1] = hi & 0xff;
13990 dev->dev_addr[0] = (hi >> 8) & 0xff;
13994 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
13995 #ifdef CONFIG_SPARC
13996 if (!tg3_get_default_macaddr_sparc(tp))
14001 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
14005 #define BOUNDARY_SINGLE_CACHELINE 1
14006 #define BOUNDARY_MULTI_CACHELINE 2
14008 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
14010 int cacheline_size;
14014 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
14016 cacheline_size = 1024;
14018 cacheline_size = (int) byte * 4;
14020 /* On 5703 and later chips, the boundary bits have no
14023 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
14024 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
14025 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
14028 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
14029 goal = BOUNDARY_MULTI_CACHELINE;
14031 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
14032 goal = BOUNDARY_SINGLE_CACHELINE;
14038 if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
14039 val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
14046 /* PCI controllers on most RISC systems tend to disconnect
14047 * when a device tries to burst across a cache-line boundary.
14048 * Therefore, letting tg3 do so just wastes PCI bandwidth.
14050 * Unfortunately, for PCI-E there are only limited
14051 * write-side controls for this, and thus for reads
14052 * we will still get the disconnects. We'll also waste
14053 * these PCI cycles for both read and write for chips
14054 * other than 5700 and 5701 which do not implement the
14057 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
14058 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
14059 switch (cacheline_size) {
14064 if (goal == BOUNDARY_SINGLE_CACHELINE) {
14065 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
14066 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
14068 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
14069 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
14074 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
14075 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
14079 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
14080 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
14083 } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
14084 switch (cacheline_size) {
14088 if (goal == BOUNDARY_SINGLE_CACHELINE) {
14089 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
14090 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
14096 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
14097 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
14101 switch (cacheline_size) {
14103 if (goal == BOUNDARY_SINGLE_CACHELINE) {
14104 val |= (DMA_RWCTRL_READ_BNDRY_16 |
14105 DMA_RWCTRL_WRITE_BNDRY_16);
14110 if (goal == BOUNDARY_SINGLE_CACHELINE) {
14111 val |= (DMA_RWCTRL_READ_BNDRY_32 |
14112 DMA_RWCTRL_WRITE_BNDRY_32);
14117 if (goal == BOUNDARY_SINGLE_CACHELINE) {
14118 val |= (DMA_RWCTRL_READ_BNDRY_64 |
14119 DMA_RWCTRL_WRITE_BNDRY_64);
14124 if (goal == BOUNDARY_SINGLE_CACHELINE) {
14125 val |= (DMA_RWCTRL_READ_BNDRY_128 |
14126 DMA_RWCTRL_WRITE_BNDRY_128);
14131 val |= (DMA_RWCTRL_READ_BNDRY_256 |
14132 DMA_RWCTRL_WRITE_BNDRY_256);
14135 val |= (DMA_RWCTRL_READ_BNDRY_512 |
14136 DMA_RWCTRL_WRITE_BNDRY_512);
14140 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
14141 DMA_RWCTRL_WRITE_BNDRY_1024);
14150 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
14152 struct tg3_internal_buffer_desc test_desc;
14153 u32 sram_dma_descs;
14156 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
14158 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
14159 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
14160 tw32(RDMAC_STATUS, 0);
14161 tw32(WDMAC_STATUS, 0);
14163 tw32(BUFMGR_MODE, 0);
14164 tw32(FTQ_RESET, 0);
14166 test_desc.addr_hi = ((u64) buf_dma) >> 32;
14167 test_desc.addr_lo = buf_dma & 0xffffffff;
14168 test_desc.nic_mbuf = 0x00002100;
14169 test_desc.len = size;
14172 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
14173 * the *second* time the tg3 driver was getting loaded after an
14176 * Broadcom tells me:
14177 * ...the DMA engine is connected to the GRC block and a DMA
14178 * reset may affect the GRC block in some unpredictable way...
14179 * The behavior of resets to individual blocks has not been tested.
14181 * Broadcom noted the GRC reset will also reset all sub-components.
14184 test_desc.cqid_sqid = (13 << 8) | 2;
14186 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
14189 test_desc.cqid_sqid = (16 << 8) | 7;
14191 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
14194 test_desc.flags = 0x00000005;
14196 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
14199 val = *(((u32 *)&test_desc) + i);
14200 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
14201 sram_dma_descs + (i * sizeof(u32)));
14202 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
14204 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
14207 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
14209 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
14212 for (i = 0; i < 40; i++) {
14216 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
14218 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
14219 if ((val & 0xffff) == sram_dma_descs) {
14230 #define TEST_BUFFER_SIZE 0x2000
14232 static int __devinit tg3_test_dma(struct tg3 *tp)
14234 dma_addr_t buf_dma;
14235 u32 *buf, saved_dma_rwctrl;
14238 buf = dma_alloc_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE,
14239 &buf_dma, GFP_KERNEL);
14245 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
14246 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
14248 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
14250 if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
14253 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
14254 /* DMA read watermark not used on PCIE */
14255 tp->dma_rwctrl |= 0x00180000;
14256 } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
14257 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
14258 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
14259 tp->dma_rwctrl |= 0x003f0000;
14261 tp->dma_rwctrl |= 0x003f000f;
14263 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
14264 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
14265 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
14266 u32 read_water = 0x7;
14268 /* If the 5704 is behind the EPB bridge, we can
14269 * do the less restrictive ONE_DMA workaround for
14270 * better performance.
14272 if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
14273 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
14274 tp->dma_rwctrl |= 0x8000;
14275 else if (ccval == 0x6 || ccval == 0x7)
14276 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
14278 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
14280 /* Set bit 23 to enable PCIX hw bug fix */
14282 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
14283 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
14285 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
14286 /* 5780 always in PCIX mode */
14287 tp->dma_rwctrl |= 0x00144000;
14288 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
14289 /* 5714 always in PCIX mode */
14290 tp->dma_rwctrl |= 0x00148000;
14292 tp->dma_rwctrl |= 0x001b000f;
14296 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
14297 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
14298 tp->dma_rwctrl &= 0xfffffff0;
14300 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
14301 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
14302 /* Remove this if it causes problems for some boards. */
14303 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
14305 /* On 5700/5701 chips, we need to set this bit.
14306 * Otherwise the chip will issue cacheline transactions
14307 * to streamable DMA memory with not all the byte
14308 * enables turned on. This is an error on several
14309 * RISC PCI controllers, in particular sparc64.
14311 * On 5703/5704 chips, this bit has been reassigned
14312 * a different meaning. In particular, it is used
14313 * on those chips to enable a PCI-X workaround.
14315 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
14318 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14321 /* Unneeded, already done by tg3_get_invariants. */
14322 tg3_switch_clocks(tp);
14325 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
14326 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
14329 /* It is best to perform DMA test with maximum write burst size
14330 * to expose the 5700/5701 write DMA bug.
14332 saved_dma_rwctrl = tp->dma_rwctrl;
14333 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14334 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14339 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
14342 /* Send the buffer to the chip. */
14343 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
14345 dev_err(&tp->pdev->dev,
14346 "%s: Buffer write failed. err = %d\n",
14352 /* validate data reached card RAM correctly. */
14353 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
14355 tg3_read_mem(tp, 0x2100 + (i*4), &val);
14356 if (le32_to_cpu(val) != p[i]) {
14357 dev_err(&tp->pdev->dev,
14358 "%s: Buffer corrupted on device! "
14359 "(%d != %d)\n", __func__, val, i);
14360 /* ret = -ENODEV here? */
14365 /* Now read it back. */
14366 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
14368 dev_err(&tp->pdev->dev, "%s: Buffer read failed. "
14369 "err = %d\n", __func__, ret);
14374 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
14378 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
14379 DMA_RWCTRL_WRITE_BNDRY_16) {
14380 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14381 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14382 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14385 dev_err(&tp->pdev->dev,
14386 "%s: Buffer corrupted on read back! "
14387 "(%d != %d)\n", __func__, p[i], i);
14393 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
14399 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
14400 DMA_RWCTRL_WRITE_BNDRY_16) {
14401 static struct pci_device_id dma_wait_state_chipsets[] = {
14402 { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
14403 PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
14407 /* DMA test passed without adjusting DMA boundary,
14408 * now look for chipsets that are known to expose the
14409 * DMA bug without failing the test.
14411 if (pci_dev_present(dma_wait_state_chipsets)) {
14412 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14413 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14415 /* Safe to use the calculated DMA boundary. */
14416 tp->dma_rwctrl = saved_dma_rwctrl;
14419 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14423 dma_free_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE, buf, buf_dma);
14428 static void __devinit tg3_init_link_config(struct tg3 *tp)
14430 tp->link_config.advertising =
14431 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
14432 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
14433 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
14434 ADVERTISED_Autoneg | ADVERTISED_MII);
14435 tp->link_config.speed = SPEED_INVALID;
14436 tp->link_config.duplex = DUPLEX_INVALID;
14437 tp->link_config.autoneg = AUTONEG_ENABLE;
14438 tp->link_config.active_speed = SPEED_INVALID;
14439 tp->link_config.active_duplex = DUPLEX_INVALID;
14440 tp->link_config.orig_speed = SPEED_INVALID;
14441 tp->link_config.orig_duplex = DUPLEX_INVALID;
14442 tp->link_config.orig_autoneg = AUTONEG_INVALID;
14445 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
14447 if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
14448 tp->bufmgr_config.mbuf_read_dma_low_water =
14449 DEFAULT_MB_RDMA_LOW_WATER_5705;
14450 tp->bufmgr_config.mbuf_mac_rx_low_water =
14451 DEFAULT_MB_MACRX_LOW_WATER_57765;
14452 tp->bufmgr_config.mbuf_high_water =
14453 DEFAULT_MB_HIGH_WATER_57765;
14455 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14456 DEFAULT_MB_RDMA_LOW_WATER_5705;
14457 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14458 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765;
14459 tp->bufmgr_config.mbuf_high_water_jumbo =
14460 DEFAULT_MB_HIGH_WATER_JUMBO_57765;
14461 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
14462 tp->bufmgr_config.mbuf_read_dma_low_water =
14463 DEFAULT_MB_RDMA_LOW_WATER_5705;
14464 tp->bufmgr_config.mbuf_mac_rx_low_water =
14465 DEFAULT_MB_MACRX_LOW_WATER_5705;
14466 tp->bufmgr_config.mbuf_high_water =
14467 DEFAULT_MB_HIGH_WATER_5705;
14468 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
14469 tp->bufmgr_config.mbuf_mac_rx_low_water =
14470 DEFAULT_MB_MACRX_LOW_WATER_5906;
14471 tp->bufmgr_config.mbuf_high_water =
14472 DEFAULT_MB_HIGH_WATER_5906;
14475 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14476 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
14477 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14478 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
14479 tp->bufmgr_config.mbuf_high_water_jumbo =
14480 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
14482 tp->bufmgr_config.mbuf_read_dma_low_water =
14483 DEFAULT_MB_RDMA_LOW_WATER;
14484 tp->bufmgr_config.mbuf_mac_rx_low_water =
14485 DEFAULT_MB_MACRX_LOW_WATER;
14486 tp->bufmgr_config.mbuf_high_water =
14487 DEFAULT_MB_HIGH_WATER;
14489 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14490 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
14491 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14492 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
14493 tp->bufmgr_config.mbuf_high_water_jumbo =
14494 DEFAULT_MB_HIGH_WATER_JUMBO;
14497 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
14498 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
14501 static char * __devinit tg3_phy_string(struct tg3 *tp)
14503 switch (tp->phy_id & TG3_PHY_ID_MASK) {
14504 case TG3_PHY_ID_BCM5400: return "5400";
14505 case TG3_PHY_ID_BCM5401: return "5401";
14506 case TG3_PHY_ID_BCM5411: return "5411";
14507 case TG3_PHY_ID_BCM5701: return "5701";
14508 case TG3_PHY_ID_BCM5703: return "5703";
14509 case TG3_PHY_ID_BCM5704: return "5704";
14510 case TG3_PHY_ID_BCM5705: return "5705";
14511 case TG3_PHY_ID_BCM5750: return "5750";
14512 case TG3_PHY_ID_BCM5752: return "5752";
14513 case TG3_PHY_ID_BCM5714: return "5714";
14514 case TG3_PHY_ID_BCM5780: return "5780";
14515 case TG3_PHY_ID_BCM5755: return "5755";
14516 case TG3_PHY_ID_BCM5787: return "5787";
14517 case TG3_PHY_ID_BCM5784: return "5784";
14518 case TG3_PHY_ID_BCM5756: return "5722/5756";
14519 case TG3_PHY_ID_BCM5906: return "5906";
14520 case TG3_PHY_ID_BCM5761: return "5761";
14521 case TG3_PHY_ID_BCM5718C: return "5718C";
14522 case TG3_PHY_ID_BCM5718S: return "5718S";
14523 case TG3_PHY_ID_BCM57765: return "57765";
14524 case TG3_PHY_ID_BCM5719C: return "5719C";
14525 case TG3_PHY_ID_BCM8002: return "8002/serdes";
14526 case 0: return "serdes";
14527 default: return "unknown";
14531 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
14533 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
14534 strcpy(str, "PCI Express");
14536 } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
14537 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
14539 strcpy(str, "PCIX:");
14541 if ((clock_ctrl == 7) ||
14542 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
14543 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
14544 strcat(str, "133MHz");
14545 else if (clock_ctrl == 0)
14546 strcat(str, "33MHz");
14547 else if (clock_ctrl == 2)
14548 strcat(str, "50MHz");
14549 else if (clock_ctrl == 4)
14550 strcat(str, "66MHz");
14551 else if (clock_ctrl == 6)
14552 strcat(str, "100MHz");
14554 strcpy(str, "PCI:");
14555 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
14556 strcat(str, "66MHz");
14558 strcat(str, "33MHz");
14560 if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
14561 strcat(str, ":32-bit");
14563 strcat(str, ":64-bit");
14567 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
14569 struct pci_dev *peer;
14570 unsigned int func, devnr = tp->pdev->devfn & ~7;
14572 for (func = 0; func < 8; func++) {
14573 peer = pci_get_slot(tp->pdev->bus, devnr | func);
14574 if (peer && peer != tp->pdev)
14578 /* 5704 can be configured in single-port mode, set peer to
14579 * tp->pdev in that case.
14587 * We don't need to keep the refcount elevated; there's no way
14588 * to remove one half of this device without removing the other
14595 static void __devinit tg3_init_coal(struct tg3 *tp)
14597 struct ethtool_coalesce *ec = &tp->coal;
14599 memset(ec, 0, sizeof(*ec));
14600 ec->cmd = ETHTOOL_GCOALESCE;
14601 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
14602 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
14603 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
14604 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
14605 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
14606 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
14607 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
14608 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
14609 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
14611 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
14612 HOSTCC_MODE_CLRTICK_TXBD)) {
14613 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
14614 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
14615 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
14616 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
14619 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
14620 ec->rx_coalesce_usecs_irq = 0;
14621 ec->tx_coalesce_usecs_irq = 0;
14622 ec->stats_block_coalesce_usecs = 0;
14626 static const struct net_device_ops tg3_netdev_ops = {
14627 .ndo_open = tg3_open,
14628 .ndo_stop = tg3_close,
14629 .ndo_start_xmit = tg3_start_xmit,
14630 .ndo_get_stats64 = tg3_get_stats64,
14631 .ndo_validate_addr = eth_validate_addr,
14632 .ndo_set_multicast_list = tg3_set_rx_mode,
14633 .ndo_set_mac_address = tg3_set_mac_addr,
14634 .ndo_do_ioctl = tg3_ioctl,
14635 .ndo_tx_timeout = tg3_tx_timeout,
14636 .ndo_change_mtu = tg3_change_mtu,
14637 #if TG3_VLAN_TAG_USED
14638 .ndo_vlan_rx_register = tg3_vlan_rx_register,
14640 #ifdef CONFIG_NET_POLL_CONTROLLER
14641 .ndo_poll_controller = tg3_poll_controller,
14645 static const struct net_device_ops tg3_netdev_ops_dma_bug = {
14646 .ndo_open = tg3_open,
14647 .ndo_stop = tg3_close,
14648 .ndo_start_xmit = tg3_start_xmit_dma_bug,
14649 .ndo_get_stats64 = tg3_get_stats64,
14650 .ndo_validate_addr = eth_validate_addr,
14651 .ndo_set_multicast_list = tg3_set_rx_mode,
14652 .ndo_set_mac_address = tg3_set_mac_addr,
14653 .ndo_do_ioctl = tg3_ioctl,
14654 .ndo_tx_timeout = tg3_tx_timeout,
14655 .ndo_change_mtu = tg3_change_mtu,
14656 #if TG3_VLAN_TAG_USED
14657 .ndo_vlan_rx_register = tg3_vlan_rx_register,
14659 #ifdef CONFIG_NET_POLL_CONTROLLER
14660 .ndo_poll_controller = tg3_poll_controller,
14664 static int __devinit tg3_init_one(struct pci_dev *pdev,
14665 const struct pci_device_id *ent)
14667 struct net_device *dev;
14669 int i, err, pm_cap;
14670 u32 sndmbx, rcvmbx, intmbx;
14672 u64 dma_mask, persist_dma_mask;
14674 printk_once(KERN_INFO "%s\n", version);
14676 err = pci_enable_device(pdev);
14678 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
14682 err = pci_request_regions(pdev, DRV_MODULE_NAME);
14684 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
14685 goto err_out_disable_pdev;
14688 pci_set_master(pdev);
14690 /* Find power-management capability. */
14691 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
14693 dev_err(&pdev->dev,
14694 "Cannot find Power Management capability, aborting\n");
14696 goto err_out_free_res;
14699 dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
14701 dev_err(&pdev->dev, "Etherdev alloc failed, aborting\n");
14703 goto err_out_free_res;
14706 SET_NETDEV_DEV(dev, &pdev->dev);
14708 #if TG3_VLAN_TAG_USED
14709 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
14712 tp = netdev_priv(dev);
14715 tp->pm_cap = pm_cap;
14716 tp->rx_mode = TG3_DEF_RX_MODE;
14717 tp->tx_mode = TG3_DEF_TX_MODE;
14720 tp->msg_enable = tg3_debug;
14722 tp->msg_enable = TG3_DEF_MSG_ENABLE;
14724 /* The word/byte swap controls here control register access byte
14725 * swapping. DMA data byte swapping is controlled in the GRC_MODE
14728 tp->misc_host_ctrl =
14729 MISC_HOST_CTRL_MASK_PCI_INT |
14730 MISC_HOST_CTRL_WORD_SWAP |
14731 MISC_HOST_CTRL_INDIR_ACCESS |
14732 MISC_HOST_CTRL_PCISTATE_RW;
14734 /* The NONFRM (non-frame) byte/word swap controls take effect
14735 * on descriptor entries, anything which isn't packet data.
14737 * The StrongARM chips on the board (one for tx, one for rx)
14738 * are running in big-endian mode.
14740 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
14741 GRC_MODE_WSWAP_NONFRM_DATA);
14742 #ifdef __BIG_ENDIAN
14743 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
14745 spin_lock_init(&tp->lock);
14746 spin_lock_init(&tp->indirect_lock);
14747 INIT_WORK(&tp->reset_task, tg3_reset_task);
14749 tp->regs = pci_ioremap_bar(pdev, BAR_0);
14751 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
14753 goto err_out_free_dev;
14756 tg3_init_link_config(tp);
14758 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
14759 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
14761 dev->ethtool_ops = &tg3_ethtool_ops;
14762 dev->watchdog_timeo = TG3_TX_TIMEOUT;
14763 dev->irq = pdev->irq;
14765 err = tg3_get_invariants(tp);
14767 dev_err(&pdev->dev,
14768 "Problem fetching invariants of chip, aborting\n");
14769 goto err_out_iounmap;
14772 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
14773 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
14774 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5719)
14775 dev->netdev_ops = &tg3_netdev_ops;
14777 dev->netdev_ops = &tg3_netdev_ops_dma_bug;
14780 /* The EPB bridge inside 5714, 5715, and 5780 and any
14781 * device behind the EPB cannot support DMA addresses > 40-bit.
14782 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
14783 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
14784 * do DMA address check in tg3_start_xmit().
14786 if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
14787 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
14788 else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
14789 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
14790 #ifdef CONFIG_HIGHMEM
14791 dma_mask = DMA_BIT_MASK(64);
14794 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
14796 /* Configure DMA attributes. */
14797 if (dma_mask > DMA_BIT_MASK(32)) {
14798 err = pci_set_dma_mask(pdev, dma_mask);
14800 dev->features |= NETIF_F_HIGHDMA;
14801 err = pci_set_consistent_dma_mask(pdev,
14804 dev_err(&pdev->dev, "Unable to obtain 64 bit "
14805 "DMA for consistent allocations\n");
14806 goto err_out_iounmap;
14810 if (err || dma_mask == DMA_BIT_MASK(32)) {
14811 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
14813 dev_err(&pdev->dev,
14814 "No usable DMA configuration, aborting\n");
14815 goto err_out_iounmap;
14819 tg3_init_bufmgr_config(tp);
14821 /* Selectively allow TSO based on operating conditions */
14822 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
14823 (tp->fw_needed && !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)))
14824 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
14826 tp->tg3_flags2 &= ~(TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG);
14827 tp->fw_needed = NULL;
14830 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
14831 tp->fw_needed = FIRMWARE_TG3;
14833 /* TSO is on by default on chips that support hardware TSO.
14834 * Firmware TSO on older chips gives lower performance, so it
14835 * is off by default, but can be enabled using ethtool.
14837 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) &&
14838 (dev->features & NETIF_F_IP_CSUM)) {
14839 dev->features |= NETIF_F_TSO;
14840 vlan_features_add(dev, NETIF_F_TSO);
14842 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
14843 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3)) {
14844 if (dev->features & NETIF_F_IPV6_CSUM) {
14845 dev->features |= NETIF_F_TSO6;
14846 vlan_features_add(dev, NETIF_F_TSO6);
14848 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
14849 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
14850 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
14851 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
14852 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
14853 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
14854 dev->features |= NETIF_F_TSO_ECN;
14855 vlan_features_add(dev, NETIF_F_TSO_ECN);
14859 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
14860 !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
14861 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
14862 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
14863 tp->rx_pending = 63;
14866 err = tg3_get_device_address(tp);
14868 dev_err(&pdev->dev,
14869 "Could not obtain valid ethernet address, aborting\n");
14870 goto err_out_iounmap;
14873 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
14874 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
14875 if (!tp->aperegs) {
14876 dev_err(&pdev->dev,
14877 "Cannot map APE registers, aborting\n");
14879 goto err_out_iounmap;
14882 tg3_ape_lock_init(tp);
14884 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
14885 tg3_read_dash_ver(tp);
14889 * Reset chip in case UNDI or EFI driver did not shutdown
14890 * DMA self test will enable WDMAC and we'll see (spurious)
14891 * pending DMA on the PCI bus at that point.
14893 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
14894 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
14895 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
14896 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14899 err = tg3_test_dma(tp);
14901 dev_err(&pdev->dev, "DMA engine test failed, aborting\n");
14902 goto err_out_apeunmap;
14905 /* flow control autonegotiation is default behavior */
14906 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
14907 tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
14909 intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
14910 rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
14911 sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
14912 for (i = 0; i < tp->irq_max; i++) {
14913 struct tg3_napi *tnapi = &tp->napi[i];
14916 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
14918 tnapi->int_mbox = intmbx;
14924 tnapi->consmbox = rcvmbx;
14925 tnapi->prodmbox = sndmbx;
14928 tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
14930 tnapi->coal_now = HOSTCC_MODE_NOW;
14932 if (!(tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX))
14936 * If we support MSIX, we'll be using RSS. If we're using
14937 * RSS, the first vector only handles link interrupts and the
14938 * remaining vectors handle rx and tx interrupts. Reuse the
14939 * mailbox values for the next iteration. The values we setup
14940 * above are still useful for the single vectored mode.
14955 pci_set_drvdata(pdev, dev);
14957 err = register_netdev(dev);
14959 dev_err(&pdev->dev, "Cannot register net device, aborting\n");
14960 goto err_out_apeunmap;
14963 netdev_info(dev, "Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
14964 tp->board_part_number,
14965 tp->pci_chip_rev_id,
14966 tg3_bus_string(tp, str),
14969 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
14970 struct phy_device *phydev;
14971 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
14973 "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
14974 phydev->drv->name, dev_name(&phydev->dev));
14978 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
14979 ethtype = "10/100Base-TX";
14980 else if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
14981 ethtype = "1000Base-SX";
14983 ethtype = "10/100/1000Base-T";
14985 netdev_info(dev, "attached PHY is %s (%s Ethernet) "
14986 "(WireSpeed[%d])\n", tg3_phy_string(tp), ethtype,
14987 (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) == 0);
14990 netdev_info(dev, "RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
14991 (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
14992 (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
14993 (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) != 0,
14994 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
14995 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
14996 netdev_info(dev, "dma_rwctrl[%08x] dma_mask[%d-bit]\n",
14998 pdev->dma_mask == DMA_BIT_MASK(32) ? 32 :
14999 ((u64)pdev->dma_mask) == DMA_BIT_MASK(40) ? 40 : 64);
15005 iounmap(tp->aperegs);
15006 tp->aperegs = NULL;
15019 pci_release_regions(pdev);
15021 err_out_disable_pdev:
15022 pci_disable_device(pdev);
15023 pci_set_drvdata(pdev, NULL);
15027 static void __devexit tg3_remove_one(struct pci_dev *pdev)
15029 struct net_device *dev = pci_get_drvdata(pdev);
15032 struct tg3 *tp = netdev_priv(dev);
15035 release_firmware(tp->fw);
15037 flush_scheduled_work();
15039 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
15044 unregister_netdev(dev);
15046 iounmap(tp->aperegs);
15047 tp->aperegs = NULL;
15054 pci_release_regions(pdev);
15055 pci_disable_device(pdev);
15056 pci_set_drvdata(pdev, NULL);
15060 static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
15062 struct net_device *dev = pci_get_drvdata(pdev);
15063 struct tg3 *tp = netdev_priv(dev);
15064 pci_power_t target_state;
15067 /* PCI register 4 needs to be saved whether netif_running() or not.
15068 * MSI address and data need to be saved if using MSI and
15071 pci_save_state(pdev);
15073 if (!netif_running(dev))
15076 flush_scheduled_work();
15078 tg3_netif_stop(tp);
15080 del_timer_sync(&tp->timer);
15082 tg3_full_lock(tp, 1);
15083 tg3_disable_ints(tp);
15084 tg3_full_unlock(tp);
15086 netif_device_detach(dev);
15088 tg3_full_lock(tp, 0);
15089 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
15090 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
15091 tg3_full_unlock(tp);
15093 target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot;
15095 err = tg3_set_power_state(tp, target_state);
15099 tg3_full_lock(tp, 0);
15101 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
15102 err2 = tg3_restart_hw(tp, 1);
15106 tp->timer.expires = jiffies + tp->timer_offset;
15107 add_timer(&tp->timer);
15109 netif_device_attach(dev);
15110 tg3_netif_start(tp);
15113 tg3_full_unlock(tp);
15122 static int tg3_resume(struct pci_dev *pdev)
15124 struct net_device *dev = pci_get_drvdata(pdev);
15125 struct tg3 *tp = netdev_priv(dev);
15128 pci_restore_state(tp->pdev);
15130 if (!netif_running(dev))
15133 err = tg3_set_power_state(tp, PCI_D0);
15137 netif_device_attach(dev);
15139 tg3_full_lock(tp, 0);
15141 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
15142 err = tg3_restart_hw(tp, 1);
15146 tp->timer.expires = jiffies + tp->timer_offset;
15147 add_timer(&tp->timer);
15149 tg3_netif_start(tp);
15152 tg3_full_unlock(tp);
15160 static struct pci_driver tg3_driver = {
15161 .name = DRV_MODULE_NAME,
15162 .id_table = tg3_pci_tbl,
15163 .probe = tg3_init_one,
15164 .remove = __devexit_p(tg3_remove_one),
15165 .suspend = tg3_suspend,
15166 .resume = tg3_resume
15169 static int __init tg3_init(void)
15171 return pci_register_driver(&tg3_driver);
15174 static void __exit tg3_cleanup(void)
15176 pci_unregister_driver(&tg3_driver);
15179 module_init(tg3_init);
15180 module_exit(tg3_cleanup);