2 * Freescale Three Speed Ethernet Controller driver
4 * This software may be used and distributed according to the
5 * terms of the GNU Public License, Version 2, incorporated
8 * Copyright 2004-2009 Freescale Semiconductor, Inc.
9 * (C) Copyright 2003, Motorola, Inc.
20 #include <asm/errno.h>
24 DECLARE_GLOBAL_DATA_PTR;
28 static uint rxIdx; /* index of the current RX buffer */
29 static uint txIdx; /* index of the current TX buffer */
31 typedef volatile struct rtxbd {
32 txbd8_t txbd[TX_BUF_CNT];
33 rxbd8_t rxbd[PKTBUFSRX];
36 #define MAXCONTROLLERS (8)
38 static struct tsec_private *privlist[MAXCONTROLLERS];
39 static int num_tsecs = 0;
42 static RTXBD rtx __attribute__ ((aligned(8)));
44 #error "rtx must be 64-bit aligned"
47 static int tsec_send(struct eth_device *dev,
48 volatile void *packet, int length);
49 static int tsec_recv(struct eth_device *dev);
50 static int tsec_init(struct eth_device *dev, bd_t * bd);
51 static int tsec_initialize(bd_t * bis, struct tsec_info_struct *tsec_info);
52 static void tsec_halt(struct eth_device *dev);
53 static void init_registers(volatile tsec_t * regs);
54 static void startup_tsec(struct eth_device *dev);
55 static int init_phy(struct eth_device *dev);
56 void write_phy_reg(struct tsec_private *priv, uint regnum, uint value);
57 uint read_phy_reg(struct tsec_private *priv, uint regnum);
58 static struct phy_info *get_phy_info(struct eth_device *dev);
59 static void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd);
60 static void adjust_link(struct eth_device *dev);
61 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \
62 && !defined(BITBANGMII)
63 static int tsec_miiphy_write(char *devname, unsigned char addr,
64 unsigned char reg, unsigned short value);
65 static int tsec_miiphy_read(char *devname, unsigned char addr,
66 unsigned char reg, unsigned short *value);
68 #ifdef CONFIG_MCAST_TFTP
69 static int tsec_mcast_addr (struct eth_device *dev, u8 mcast_mac, u8 set);
72 /* Default initializations for TSEC controllers. */
74 static struct tsec_info_struct tsec_info[] = {
76 STD_TSEC_INFO(1), /* TSEC1 */
79 STD_TSEC_INFO(2), /* TSEC2 */
81 #ifdef CONFIG_MPC85XX_FEC
83 .regs = (tsec_t *)(TSEC_BASE_ADDR + 0x2000),
84 .miiregs = (tsec_mdio_t *)(MDIO_BASE_ADDR),
85 .devname = CONFIG_MPC85XX_FEC_NAME,
86 .phyaddr = FEC_PHY_ADDR,
91 STD_TSEC_INFO(3), /* TSEC3 */
94 STD_TSEC_INFO(4), /* TSEC4 */
98 int tsec_eth_init(bd_t *bis, struct tsec_info_struct *tsecs, int num)
102 for (i = 0; i < num; i++)
103 tsec_initialize(bis, &tsecs[i]);
108 int tsec_standard_init(bd_t *bis)
110 return tsec_eth_init(bis, tsec_info, ARRAY_SIZE(tsec_info));
113 /* Initialize device structure. Returns success if PHY
114 * initialization succeeded (i.e. if it recognizes the PHY)
116 static int tsec_initialize(bd_t * bis, struct tsec_info_struct *tsec_info)
118 struct eth_device *dev;
120 struct tsec_private *priv;
122 dev = (struct eth_device *)malloc(sizeof *dev);
127 memset(dev, 0, sizeof *dev);
129 priv = (struct tsec_private *)malloc(sizeof(*priv));
134 privlist[num_tsecs++] = priv;
135 priv->regs = tsec_info->regs;
136 priv->phyregs = tsec_info->miiregs;
137 priv->phyregs_sgmii = tsec_info->miiregs_sgmii;
139 priv->phyaddr = tsec_info->phyaddr;
140 priv->flags = tsec_info->flags;
142 sprintf(dev->name, tsec_info->devname);
145 dev->init = tsec_init;
146 dev->halt = tsec_halt;
147 dev->send = tsec_send;
148 dev->recv = tsec_recv;
149 #ifdef CONFIG_MCAST_TFTP
150 dev->mcast = tsec_mcast_addr;
153 /* Tell u-boot to get the addr from the env */
154 for (i = 0; i < 6; i++)
155 dev->enetaddr[i] = 0;
160 priv->regs->maccfg1 |= MACCFG1_SOFT_RESET;
161 udelay(2); /* Soft Reset must be asserted for 3 TX clocks */
162 priv->regs->maccfg1 &= ~(MACCFG1_SOFT_RESET);
164 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \
165 && !defined(BITBANGMII)
166 miiphy_register(dev->name, tsec_miiphy_read, tsec_miiphy_write);
169 /* Try to initialize PHY here, and return */
170 return init_phy(dev);
173 /* Initializes data structures and registers for the controller,
174 * and brings the interface up. Returns the link status, meaning
175 * that it returns success if the link is up, failure otherwise.
176 * This allows u-boot to find the first active controller.
178 static int tsec_init(struct eth_device *dev, bd_t * bd)
181 char tmpbuf[MAC_ADDR_LEN];
183 struct tsec_private *priv = (struct tsec_private *)dev->priv;
184 volatile tsec_t *regs = priv->regs;
186 /* Make sure the controller is stopped */
189 /* Init MACCFG2. Defaults to GMII */
190 regs->maccfg2 = MACCFG2_INIT_SETTINGS;
193 regs->ecntrl = ECNTRL_INIT_SETTINGS;
195 /* Copy the station address into the address registers.
196 * Backwards, because little endian MACS are dumb */
197 for (i = 0; i < MAC_ADDR_LEN; i++) {
198 tmpbuf[MAC_ADDR_LEN - 1 - i] = dev->enetaddr[i];
200 tempval = (tmpbuf[0] << 24) | (tmpbuf[1] << 16) | (tmpbuf[2] << 8) |
203 regs->macstnaddr1 = tempval;
205 tempval = *((uint *) (tmpbuf + 4));
207 regs->macstnaddr2 = tempval;
209 /* reset the indices to zero */
213 /* Clear out (for the most part) the other registers */
214 init_registers(regs);
216 /* Ready the device for tx/rx */
219 /* If there's no link, fail */
220 return (priv->link ? 0 : -1);
223 /* Writes the given phy's reg with value, using the specified MDIO regs */
224 static void tsec_local_mdio_write(volatile tsec_mdio_t *phyregs, uint addr,
225 uint reg, uint value)
227 int timeout = 1000000;
229 phyregs->miimadd = (addr << 8) | reg;
230 phyregs->miimcon = value;
234 while ((phyregs->miimind & MIIMIND_BUSY) && timeout--) ;
238 /* Provide the default behavior of writing the PHY of this ethernet device */
239 #define write_phy_reg(priv, regnum, value) \
240 tsec_local_mdio_write(priv->phyregs,priv->phyaddr,regnum,value)
242 /* Reads register regnum on the device's PHY through the
243 * specified registers. It lowers and raises the read
244 * command, and waits for the data to become valid (miimind
245 * notvalid bit cleared), and the bus to cease activity (miimind
246 * busy bit cleared), and then returns the value
248 static uint tsec_local_mdio_read(volatile tsec_mdio_t *phyregs,
249 uint phyid, uint regnum)
253 /* Put the address of the phy, and the register
254 * number into MIIMADD */
255 phyregs->miimadd = (phyid << 8) | regnum;
257 /* Clear the command register, and wait */
258 phyregs->miimcom = 0;
261 /* Initiate a read command, and wait */
262 phyregs->miimcom = MIIM_READ_COMMAND;
265 /* Wait for the the indication that the read is done */
266 while ((phyregs->miimind & (MIIMIND_NOTVALID | MIIMIND_BUSY))) ;
268 /* Grab the value read from the PHY */
269 value = phyregs->miimstat;
274 /* #define to provide old read_phy_reg functionality without duplicating code */
275 #define read_phy_reg(priv,regnum) \
276 tsec_local_mdio_read(priv->phyregs,priv->phyaddr,regnum)
278 #define TBIANA_SETTINGS ( \
279 TBIANA_ASYMMETRIC_PAUSE \
280 | TBIANA_SYMMETRIC_PAUSE \
281 | TBIANA_FULL_DUPLEX \
284 /* Force the TBI PHY into 1000Mbps full duplex when in SGMII mode */
285 #define TBICR_SETTINGS ( \
287 | TBICR_FULL_DUPLEX \
291 /* Configure the TBI for SGMII operation */
292 static void tsec_configure_serdes(struct tsec_private *priv)
294 /* Access TBI PHY registers at given TSEC register offset as opposed
295 * to the register offset used for external PHY accesses */
296 tsec_local_mdio_write(priv->phyregs_sgmii, priv->regs->tbipa, TBI_ANA,
298 tsec_local_mdio_write(priv->phyregs_sgmii, priv->regs->tbipa, TBI_TBICON,
300 tsec_local_mdio_write(priv->phyregs_sgmii, priv->regs->tbipa, TBI_CR,
304 /* Discover which PHY is attached to the device, and configure it
305 * properly. If the PHY is not recognized, then return 0
306 * (failure). Otherwise, return 1
308 static int init_phy(struct eth_device *dev)
310 struct tsec_private *priv = (struct tsec_private *)dev->priv;
311 struct phy_info *curphy;
312 volatile tsec_t *regs = priv->regs;
314 /* Assign a Physical address to the TBI */
315 regs->tbipa = CONFIG_SYS_TBIPA_VALUE;
318 /* Reset MII (due to new addresses) */
319 priv->phyregs->miimcfg = MIIMCFG_RESET;
321 priv->phyregs->miimcfg = MIIMCFG_INIT_VALUE;
323 while (priv->phyregs->miimind & MIIMIND_BUSY) ;
325 /* Get the cmd structure corresponding to the attached
327 curphy = get_phy_info(dev);
329 if (curphy == NULL) {
330 priv->phyinfo = NULL;
331 printf("%s: No PHY found\n", dev->name);
336 if (regs->ecntrl & ECNTRL_SGMII_MODE)
337 tsec_configure_serdes(priv);
339 priv->phyinfo = curphy;
341 phy_run_commands(priv, priv->phyinfo->config);
347 * Returns which value to write to the control register.
348 * For 10/100, the value is slightly different
350 static uint mii_cr_init(uint mii_reg, struct tsec_private * priv)
352 if (priv->flags & TSEC_GIGABIT)
353 return MIIM_CONTROL_INIT;
359 * Wait for auto-negotiation to complete, then determine link
361 static uint mii_parse_sr(uint mii_reg, struct tsec_private * priv)
364 * Wait if the link is up, and autonegotiation is in progress
365 * (ie - we're capable and it's not done)
367 mii_reg = read_phy_reg(priv, MIIM_STATUS);
368 if ((mii_reg & PHY_BMSR_AUTN_ABLE) && !(mii_reg & PHY_BMSR_AUTN_COMP)) {
371 puts("Waiting for PHY auto negotiation to complete");
372 while (!(mii_reg & PHY_BMSR_AUTN_COMP)) {
376 if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
377 puts(" TIMEOUT !\n");
383 puts("user interrupt!\n");
388 if ((i++ % 1000) == 0) {
391 udelay(1000); /* 1 ms */
392 mii_reg = read_phy_reg(priv, MIIM_STATUS);
396 /* Link status bit is latched low, read it again */
397 mii_reg = read_phy_reg(priv, MIIM_STATUS);
399 udelay(500000); /* another 500 ms (results in faster booting) */
402 priv->link = mii_reg & MIIM_STATUS_LINK ? 1 : 0;
407 /* Generic function which updates the speed and duplex. If
408 * autonegotiation is enabled, it uses the AND of the link
409 * partner's advertised capabilities and our advertised
410 * capabilities. If autonegotiation is disabled, we use the
411 * appropriate bits in the control register.
413 * Stolen from Linux's mii.c and phy_device.c
415 static uint mii_parse_link(uint mii_reg, struct tsec_private *priv)
417 /* We're using autonegotiation */
418 if (mii_reg & PHY_BMSR_AUTN_ABLE) {
422 /* Check for gigabit capability */
423 if (mii_reg & PHY_BMSR_EXT) {
424 /* We want a list of states supported by
425 * both PHYs in the link
427 gblpa = read_phy_reg(priv, PHY_1000BTSR);
428 gblpa &= read_phy_reg(priv, PHY_1000BTCR) << 2;
431 /* Set the baseline so we only have to set them
432 * if they're different
437 /* Check the gigabit fields */
438 if (gblpa & (PHY_1000BTSR_1000FD | PHY_1000BTSR_1000HD)) {
441 if (gblpa & PHY_1000BTSR_1000FD)
448 lpa = read_phy_reg(priv, PHY_ANAR);
449 lpa &= read_phy_reg(priv, PHY_ANLPAR);
451 if (lpa & (PHY_ANLPAR_TXFD | PHY_ANLPAR_TX)) {
454 if (lpa & PHY_ANLPAR_TXFD)
457 } else if (lpa & PHY_ANLPAR_10FD)
460 uint bmcr = read_phy_reg(priv, PHY_BMCR);
465 if (bmcr & PHY_BMCR_DPLX)
468 if (bmcr & PHY_BMCR_1000_MBPS)
470 else if (bmcr & PHY_BMCR_100_MBPS)
478 * "Ethernet@Wirespeed" needs to be enabled to achieve link in certain
479 * circumstances. eg a gigabit TSEC connected to a gigabit switch with
480 * a 4-wire ethernet cable. Both ends advertise gigabit, but can't
481 * link. "Ethernet@Wirespeed" reduces advertised speed until link
484 static uint mii_BCM54xx_wirespeed(uint mii_reg, struct tsec_private *priv)
486 return (read_phy_reg(priv, mii_reg) & 0x8FFF) | 0x8010;
490 * Parse the BCM54xx status register for speed and duplex information.
491 * The linux sungem_phy has this information, but in a table format.
493 static uint mii_parse_BCM54xx_sr(uint mii_reg, struct tsec_private *priv)
495 /* If there is no link, speed and duplex don't matter */
499 switch ((mii_reg & MIIM_BCM54xx_AUXSTATUS_LINKMODE_MASK) >>
500 MIIM_BCM54xx_AUXSTATUS_LINKMODE_SHIFT) {
526 printf("Auto-neg error, defaulting to 10BT/HD\n");
535 /* Parse the 88E1011's status register for speed and duplex
538 static uint mii_parse_88E1011_psr(uint mii_reg, struct tsec_private * priv)
542 mii_reg = read_phy_reg(priv, MIIM_88E1011_PHY_STATUS);
544 if ((mii_reg & MIIM_88E1011_PHYSTAT_LINK) &&
545 !(mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE)) {
548 puts("Waiting for PHY realtime link");
549 while (!(mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE)) {
550 /* Timeout reached ? */
551 if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
552 puts(" TIMEOUT !\n");
557 if ((i++ % 1000) == 0) {
560 udelay(1000); /* 1 ms */
561 mii_reg = read_phy_reg(priv, MIIM_88E1011_PHY_STATUS);
564 udelay(500000); /* another 500 ms (results in faster booting) */
566 if (mii_reg & MIIM_88E1011_PHYSTAT_LINK)
572 if (mii_reg & MIIM_88E1011_PHYSTAT_DUPLEX)
577 speed = (mii_reg & MIIM_88E1011_PHYSTAT_SPEED);
580 case MIIM_88E1011_PHYSTAT_GBIT:
583 case MIIM_88E1011_PHYSTAT_100:
593 /* Parse the RTL8211B's status register for speed and duplex
596 static uint mii_parse_RTL8211B_sr(uint mii_reg, struct tsec_private * priv)
600 mii_reg = read_phy_reg(priv, MIIM_RTL8211B_PHY_STATUS);
601 if (!(mii_reg & MIIM_RTL8211B_PHYSTAT_SPDDONE)) {
604 /* in case of timeout ->link is cleared */
606 puts("Waiting for PHY realtime link");
607 while (!(mii_reg & MIIM_RTL8211B_PHYSTAT_SPDDONE)) {
608 /* Timeout reached ? */
609 if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
610 puts(" TIMEOUT !\n");
615 if ((i++ % 1000) == 0) {
618 udelay(1000); /* 1 ms */
619 mii_reg = read_phy_reg(priv, MIIM_RTL8211B_PHY_STATUS);
622 udelay(500000); /* another 500 ms (results in faster booting) */
624 if (mii_reg & MIIM_RTL8211B_PHYSTAT_LINK)
630 if (mii_reg & MIIM_RTL8211B_PHYSTAT_DUPLEX)
635 speed = (mii_reg & MIIM_RTL8211B_PHYSTAT_SPEED);
638 case MIIM_RTL8211B_PHYSTAT_GBIT:
641 case MIIM_RTL8211B_PHYSTAT_100:
651 /* Parse the cis8201's status register for speed and duplex
654 static uint mii_parse_cis8201(uint mii_reg, struct tsec_private * priv)
658 if (mii_reg & MIIM_CIS8201_AUXCONSTAT_DUPLEX)
663 speed = mii_reg & MIIM_CIS8201_AUXCONSTAT_SPEED;
665 case MIIM_CIS8201_AUXCONSTAT_GBIT:
668 case MIIM_CIS8201_AUXCONSTAT_100:
679 /* Parse the vsc8244's status register for speed and duplex
682 static uint mii_parse_vsc8244(uint mii_reg, struct tsec_private * priv)
686 if (mii_reg & MIIM_VSC8244_AUXCONSTAT_DUPLEX)
691 speed = mii_reg & MIIM_VSC8244_AUXCONSTAT_SPEED;
693 case MIIM_VSC8244_AUXCONSTAT_GBIT:
696 case MIIM_VSC8244_AUXCONSTAT_100:
707 /* Parse the DM9161's status register for speed and duplex
710 static uint mii_parse_dm9161_scsr(uint mii_reg, struct tsec_private * priv)
712 if (mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_100H))
717 if (mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_10F))
726 * Hack to write all 4 PHYs with the LED values
728 static uint mii_cis8204_fixled(uint mii_reg, struct tsec_private * priv)
731 volatile tsec_mdio_t *regbase = priv->phyregs;
732 int timeout = 1000000;
734 for (phyid = 0; phyid < 4; phyid++) {
735 regbase->miimadd = (phyid << 8) | mii_reg;
736 regbase->miimcon = MIIM_CIS8204_SLEDCON_INIT;
740 while ((regbase->miimind & MIIMIND_BUSY) && timeout--) ;
743 return MIIM_CIS8204_SLEDCON_INIT;
746 static uint mii_cis8204_setmode(uint mii_reg, struct tsec_private * priv)
748 if (priv->flags & TSEC_REDUCED)
749 return MIIM_CIS8204_EPHYCON_INIT | MIIM_CIS8204_EPHYCON_RGMII;
751 return MIIM_CIS8204_EPHYCON_INIT;
754 static uint mii_m88e1111s_setmode(uint mii_reg, struct tsec_private *priv)
756 uint mii_data = read_phy_reg(priv, mii_reg);
758 if (priv->flags & TSEC_REDUCED)
759 mii_data = (mii_data & 0xfff0) | 0x000b;
763 /* Initialized required registers to appropriate values, zeroing
764 * those we don't care about (unless zero is bad, in which case,
765 * choose a more appropriate value)
767 static void init_registers(volatile tsec_t * regs)
770 regs->ievent = IEVENT_INIT_CLEAR;
772 regs->imask = IMASK_INIT_CLEAR;
774 regs->hash.iaddr0 = 0;
775 regs->hash.iaddr1 = 0;
776 regs->hash.iaddr2 = 0;
777 regs->hash.iaddr3 = 0;
778 regs->hash.iaddr4 = 0;
779 regs->hash.iaddr5 = 0;
780 regs->hash.iaddr6 = 0;
781 regs->hash.iaddr7 = 0;
783 regs->hash.gaddr0 = 0;
784 regs->hash.gaddr1 = 0;
785 regs->hash.gaddr2 = 0;
786 regs->hash.gaddr3 = 0;
787 regs->hash.gaddr4 = 0;
788 regs->hash.gaddr5 = 0;
789 regs->hash.gaddr6 = 0;
790 regs->hash.gaddr7 = 0;
792 regs->rctrl = 0x00000000;
794 /* Init RMON mib registers */
795 memset((void *)&(regs->rmon), 0, sizeof(rmon_mib_t));
797 regs->rmon.cam1 = 0xffffffff;
798 regs->rmon.cam2 = 0xffffffff;
800 regs->mrblr = MRBLR_INIT_SETTINGS;
802 regs->minflr = MINFLR_INIT_SETTINGS;
804 regs->attr = ATTR_INIT_SETTINGS;
805 regs->attreli = ATTRELI_INIT_SETTINGS;
809 /* Configure maccfg2 based on negotiated speed and duplex
810 * reported by PHY handling code
812 static void adjust_link(struct eth_device *dev)
814 struct tsec_private *priv = (struct tsec_private *)dev->priv;
815 volatile tsec_t *regs = priv->regs;
818 if (priv->duplexity != 0)
819 regs->maccfg2 |= MACCFG2_FULL_DUPLEX;
821 regs->maccfg2 &= ~(MACCFG2_FULL_DUPLEX);
823 switch (priv->speed) {
825 regs->maccfg2 = ((regs->maccfg2 & ~(MACCFG2_IF))
830 regs->maccfg2 = ((regs->maccfg2 & ~(MACCFG2_IF))
833 /* Set R100 bit in all modes although
834 * it is only used in RGMII mode
836 if (priv->speed == 100)
837 regs->ecntrl |= ECNTRL_R100;
839 regs->ecntrl &= ~(ECNTRL_R100);
842 printf("%s: Speed was bad\n", dev->name);
846 printf("Speed: %d, %s duplex\n", priv->speed,
847 (priv->duplexity) ? "full" : "half");
850 printf("%s: No link.\n", dev->name);
854 /* Set up the buffers and their descriptors, and bring up the
857 static void startup_tsec(struct eth_device *dev)
860 struct tsec_private *priv = (struct tsec_private *)dev->priv;
861 volatile tsec_t *regs = priv->regs;
863 /* Point to the buffer descriptors */
864 regs->tbase = (unsigned int)(&rtx.txbd[txIdx]);
865 regs->rbase = (unsigned int)(&rtx.rxbd[rxIdx]);
867 /* Initialize the Rx Buffer descriptors */
868 for (i = 0; i < PKTBUFSRX; i++) {
869 rtx.rxbd[i].status = RXBD_EMPTY;
870 rtx.rxbd[i].length = 0;
871 rtx.rxbd[i].bufPtr = (uint) NetRxPackets[i];
873 rtx.rxbd[PKTBUFSRX - 1].status |= RXBD_WRAP;
875 /* Initialize the TX Buffer Descriptors */
876 for (i = 0; i < TX_BUF_CNT; i++) {
877 rtx.txbd[i].status = 0;
878 rtx.txbd[i].length = 0;
879 rtx.txbd[i].bufPtr = 0;
881 rtx.txbd[TX_BUF_CNT - 1].status |= TXBD_WRAP;
883 /* Start up the PHY */
885 phy_run_commands(priv, priv->phyinfo->startup);
889 /* Enable Transmit and Receive */
890 regs->maccfg1 |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
892 /* Tell the DMA it is clear to go */
893 regs->dmactrl |= DMACTRL_INIT_SETTINGS;
894 regs->tstat = TSTAT_CLEAR_THALT;
895 regs->rstat = RSTAT_CLEAR_RHALT;
896 regs->dmactrl &= ~(DMACTRL_GRS | DMACTRL_GTS);
899 /* This returns the status bits of the device. The return value
900 * is never checked, and this is what the 8260 driver did, so we
901 * do the same. Presumably, this would be zero if there were no
904 static int tsec_send(struct eth_device *dev, volatile void *packet, int length)
908 struct tsec_private *priv = (struct tsec_private *)dev->priv;
909 volatile tsec_t *regs = priv->regs;
911 /* Find an empty buffer descriptor */
912 for (i = 0; rtx.txbd[txIdx].status & TXBD_READY; i++) {
913 if (i >= TOUT_LOOP) {
914 debug("%s: tsec: tx buffers full\n", dev->name);
919 rtx.txbd[txIdx].bufPtr = (uint) packet;
920 rtx.txbd[txIdx].length = length;
921 rtx.txbd[txIdx].status |=
922 (TXBD_READY | TXBD_LAST | TXBD_CRC | TXBD_INTERRUPT);
924 /* Tell the DMA to go */
925 regs->tstat = TSTAT_CLEAR_THALT;
927 /* Wait for buffer to be transmitted */
928 for (i = 0; rtx.txbd[txIdx].status & TXBD_READY; i++) {
929 if (i >= TOUT_LOOP) {
930 debug("%s: tsec: tx error\n", dev->name);
935 txIdx = (txIdx + 1) % TX_BUF_CNT;
936 result = rtx.txbd[txIdx].status & TXBD_STATS;
941 static int tsec_recv(struct eth_device *dev)
944 struct tsec_private *priv = (struct tsec_private *)dev->priv;
945 volatile tsec_t *regs = priv->regs;
947 while (!(rtx.rxbd[rxIdx].status & RXBD_EMPTY)) {
949 length = rtx.rxbd[rxIdx].length;
951 /* Send the packet up if there were no errors */
952 if (!(rtx.rxbd[rxIdx].status & RXBD_STATS)) {
953 NetReceive(NetRxPackets[rxIdx], length - 4);
955 printf("Got error %x\n",
956 (rtx.rxbd[rxIdx].status & RXBD_STATS));
959 rtx.rxbd[rxIdx].length = 0;
961 /* Set the wrap bit if this is the last element in the list */
962 rtx.rxbd[rxIdx].status =
963 RXBD_EMPTY | (((rxIdx + 1) == PKTBUFSRX) ? RXBD_WRAP : 0);
965 rxIdx = (rxIdx + 1) % PKTBUFSRX;
968 if (regs->ievent & IEVENT_BSY) {
969 regs->ievent = IEVENT_BSY;
970 regs->rstat = RSTAT_CLEAR_RHALT;
977 /* Stop the interface */
978 static void tsec_halt(struct eth_device *dev)
980 struct tsec_private *priv = (struct tsec_private *)dev->priv;
981 volatile tsec_t *regs = priv->regs;
983 regs->dmactrl &= ~(DMACTRL_GRS | DMACTRL_GTS);
984 regs->dmactrl |= (DMACTRL_GRS | DMACTRL_GTS);
986 while (!(regs->ievent & (IEVENT_GRSC | IEVENT_GTSC))) ;
988 regs->maccfg1 &= ~(MACCFG1_TX_EN | MACCFG1_RX_EN);
990 /* Shut down the PHY, as needed */
992 phy_run_commands(priv, priv->phyinfo->shutdown);
995 static struct phy_info phy_info_M88E1149S = {
999 (struct phy_cmd[]) { /* config */
1000 /* Reset and configure the PHY */
1001 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1003 {0x1e, 0x200c, NULL},
1006 {0x1e, 0x100, NULL},
1007 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
1008 {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
1009 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1010 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1013 (struct phy_cmd[]) { /* startup */
1014 /* Status is read once to clear old link state */
1015 {MIIM_STATUS, miim_read, NULL},
1016 /* Auto-negotiate */
1017 {MIIM_STATUS, miim_read, &mii_parse_sr},
1018 /* Read the status */
1019 {MIIM_88E1011_PHY_STATUS, miim_read, &mii_parse_88E1011_psr},
1022 (struct phy_cmd[]) { /* shutdown */
1027 /* The 5411 id is 0x206070, the 5421 is 0x2060e0 */
1028 static struct phy_info phy_info_BCM5461S = {
1029 0x02060c1, /* 5461 ID */
1030 "Broadcom BCM5461S",
1031 0, /* not clear to me what minor revisions we can shift away */
1032 (struct phy_cmd[]) { /* config */
1033 /* Reset and configure the PHY */
1034 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1035 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
1036 {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
1037 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1038 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1041 (struct phy_cmd[]) { /* startup */
1042 /* Status is read once to clear old link state */
1043 {MIIM_STATUS, miim_read, NULL},
1044 /* Auto-negotiate */
1045 {MIIM_STATUS, miim_read, &mii_parse_sr},
1046 /* Read the status */
1047 {MIIM_BCM54xx_AUXSTATUS, miim_read, &mii_parse_BCM54xx_sr},
1050 (struct phy_cmd[]) { /* shutdown */
1055 static struct phy_info phy_info_BCM5464S = {
1056 0x02060b1, /* 5464 ID */
1057 "Broadcom BCM5464S",
1058 0, /* not clear to me what minor revisions we can shift away */
1059 (struct phy_cmd[]) { /* config */
1060 /* Reset and configure the PHY */
1061 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1062 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
1063 {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
1064 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1065 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1068 (struct phy_cmd[]) { /* startup */
1069 /* Status is read once to clear old link state */
1070 {MIIM_STATUS, miim_read, NULL},
1071 /* Auto-negotiate */
1072 {MIIM_STATUS, miim_read, &mii_parse_sr},
1073 /* Read the status */
1074 {MIIM_BCM54xx_AUXSTATUS, miim_read, &mii_parse_BCM54xx_sr},
1077 (struct phy_cmd[]) { /* shutdown */
1082 static struct phy_info phy_info_BCM5482S = {
1084 "Broadcom BCM5482S",
1086 (struct phy_cmd[]) { /* config */
1087 /* Reset and configure the PHY */
1088 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1089 /* Setup read from auxilary control shadow register 7 */
1090 {MIIM_BCM54xx_AUXCNTL, MIIM_BCM54xx_AUXCNTL_ENCODE(7), NULL},
1091 /* Read Misc Control register and or in Ethernet@Wirespeed */
1092 {MIIM_BCM54xx_AUXCNTL, 0, &mii_BCM54xx_wirespeed},
1093 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1096 (struct phy_cmd[]) { /* startup */
1097 /* Status is read once to clear old link state */
1098 {MIIM_STATUS, miim_read, NULL},
1099 /* Auto-negotiate */
1100 {MIIM_STATUS, miim_read, &mii_parse_sr},
1101 /* Read the status */
1102 {MIIM_BCM54xx_AUXSTATUS, miim_read, &mii_parse_BCM54xx_sr},
1105 (struct phy_cmd[]) { /* shutdown */
1110 static struct phy_info phy_info_M88E1011S = {
1114 (struct phy_cmd[]) { /* config */
1115 /* Reset and configure the PHY */
1116 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1118 {0x1e, 0x200c, NULL},
1121 {0x1e, 0x100, NULL},
1122 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
1123 {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
1124 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1125 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1128 (struct phy_cmd[]) { /* startup */
1129 /* Status is read once to clear old link state */
1130 {MIIM_STATUS, miim_read, NULL},
1131 /* Auto-negotiate */
1132 {MIIM_STATUS, miim_read, &mii_parse_sr},
1133 /* Read the status */
1134 {MIIM_88E1011_PHY_STATUS, miim_read, &mii_parse_88E1011_psr},
1137 (struct phy_cmd[]) { /* shutdown */
1142 static struct phy_info phy_info_M88E1111S = {
1146 (struct phy_cmd[]) { /* config */
1147 /* Reset and configure the PHY */
1148 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1149 {0x1b, 0x848f, &mii_m88e1111s_setmode},
1150 {0x14, 0x0cd2, NULL}, /* Delay RGMII TX and RX */
1151 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
1152 {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
1153 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1154 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1157 (struct phy_cmd[]) { /* startup */
1158 /* Status is read once to clear old link state */
1159 {MIIM_STATUS, miim_read, NULL},
1160 /* Auto-negotiate */
1161 {MIIM_STATUS, miim_read, &mii_parse_sr},
1162 /* Read the status */
1163 {MIIM_88E1011_PHY_STATUS, miim_read, &mii_parse_88E1011_psr},
1166 (struct phy_cmd[]) { /* shutdown */
1171 static struct phy_info phy_info_M88E1118 = {
1175 (struct phy_cmd[]) { /* config */
1176 /* Reset and configure the PHY */
1177 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1178 {0x16, 0x0002, NULL}, /* Change Page Number */
1179 {0x15, 0x1070, NULL}, /* Delay RGMII TX and RX */
1180 {0x16, 0x0003, NULL}, /* Change Page Number */
1181 {0x10, 0x021e, NULL}, /* Adjust LED control */
1182 {0x16, 0x0000, NULL}, /* Change Page Number */
1183 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
1184 {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
1185 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1186 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1189 (struct phy_cmd[]) { /* startup */
1190 {0x16, 0x0000, NULL}, /* Change Page Number */
1191 /* Status is read once to clear old link state */
1192 {MIIM_STATUS, miim_read, NULL},
1193 /* Auto-negotiate */
1194 {MIIM_STATUS, miim_read, &mii_parse_sr},
1195 /* Read the status */
1196 {MIIM_88E1011_PHY_STATUS, miim_read,
1197 &mii_parse_88E1011_psr},
1200 (struct phy_cmd[]) { /* shutdown */
1206 * Since to access LED register we need do switch the page, we
1207 * do LED configuring in the miim_read-like function as follows
1209 static uint mii_88E1121_set_led (uint mii_reg, struct tsec_private *priv)
1213 /* Switch the page to access the led register */
1214 pg = read_phy_reg(priv, MIIM_88E1121_PHY_PAGE);
1215 write_phy_reg(priv, MIIM_88E1121_PHY_PAGE, MIIM_88E1121_PHY_LED_PAGE);
1217 /* Configure leds */
1218 write_phy_reg(priv, MIIM_88E1121_PHY_LED_CTRL,
1219 MIIM_88E1121_PHY_LED_DEF);
1221 /* Restore the page pointer */
1222 write_phy_reg(priv, MIIM_88E1121_PHY_PAGE, pg);
1226 static struct phy_info phy_info_M88E1121R = {
1230 (struct phy_cmd[]) { /* config */
1231 /* Reset and configure the PHY */
1232 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1233 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
1234 {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
1235 /* Configure leds */
1236 {MIIM_88E1121_PHY_LED_CTRL, miim_read, &mii_88E1121_set_led},
1237 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1238 /* Disable IRQs and de-assert interrupt */
1239 {MIIM_88E1121_PHY_IRQ_EN, 0, NULL},
1240 {MIIM_88E1121_PHY_IRQ_STATUS, miim_read, NULL},
1243 (struct phy_cmd[]) { /* startup */
1244 /* Status is read once to clear old link state */
1245 {MIIM_STATUS, miim_read, NULL},
1246 {MIIM_STATUS, miim_read, &mii_parse_sr},
1247 {MIIM_STATUS, miim_read, &mii_parse_link},
1250 (struct phy_cmd[]) { /* shutdown */
1255 static unsigned int m88e1145_setmode(uint mii_reg, struct tsec_private *priv)
1257 uint mii_data = read_phy_reg(priv, mii_reg);
1259 /* Setting MIIM_88E1145_PHY_EXT_CR */
1260 if (priv->flags & TSEC_REDUCED)
1262 MIIM_M88E1145_RGMII_RX_DELAY | MIIM_M88E1145_RGMII_TX_DELAY;
1267 static struct phy_info phy_info_M88E1145 = {
1271 (struct phy_cmd[]) { /* config */
1273 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1281 /* Configure the PHY */
1282 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
1283 {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
1284 {MIIM_88E1011_PHY_SCR, MIIM_88E1011_PHY_MDI_X_AUTO, NULL},
1285 {MIIM_88E1145_PHY_EXT_CR, 0, &m88e1145_setmode},
1286 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1287 {MIIM_CONTROL, MIIM_CONTROL_INIT, NULL},
1290 (struct phy_cmd[]) { /* startup */
1291 /* Status is read once to clear old link state */
1292 {MIIM_STATUS, miim_read, NULL},
1293 /* Auto-negotiate */
1294 {MIIM_STATUS, miim_read, &mii_parse_sr},
1295 {MIIM_88E1111_PHY_LED_CONTROL, MIIM_88E1111_PHY_LED_DIRECT, NULL},
1296 /* Read the Status */
1297 {MIIM_88E1011_PHY_STATUS, miim_read, &mii_parse_88E1011_psr},
1300 (struct phy_cmd[]) { /* shutdown */
1305 static struct phy_info phy_info_cis8204 = {
1309 (struct phy_cmd[]) { /* config */
1310 /* Override PHY config settings */
1311 {MIIM_CIS8201_AUX_CONSTAT, MIIM_CIS8201_AUXCONSTAT_INIT, NULL},
1312 /* Configure some basic stuff */
1313 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1314 {MIIM_CIS8204_SLED_CON, MIIM_CIS8204_SLEDCON_INIT,
1315 &mii_cis8204_fixled},
1316 {MIIM_CIS8204_EPHY_CON, MIIM_CIS8204_EPHYCON_INIT,
1317 &mii_cis8204_setmode},
1320 (struct phy_cmd[]) { /* startup */
1321 /* Read the Status (2x to make sure link is right) */
1322 {MIIM_STATUS, miim_read, NULL},
1323 /* Auto-negotiate */
1324 {MIIM_STATUS, miim_read, &mii_parse_sr},
1325 /* Read the status */
1326 {MIIM_CIS8201_AUX_CONSTAT, miim_read, &mii_parse_cis8201},
1329 (struct phy_cmd[]) { /* shutdown */
1335 static struct phy_info phy_info_cis8201 = {
1339 (struct phy_cmd[]) { /* config */
1340 /* Override PHY config settings */
1341 {MIIM_CIS8201_AUX_CONSTAT, MIIM_CIS8201_AUXCONSTAT_INIT, NULL},
1342 /* Set up the interface mode */
1343 {MIIM_CIS8201_EXT_CON1, MIIM_CIS8201_EXTCON1_INIT, NULL},
1344 /* Configure some basic stuff */
1345 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1348 (struct phy_cmd[]) { /* startup */
1349 /* Read the Status (2x to make sure link is right) */
1350 {MIIM_STATUS, miim_read, NULL},
1351 /* Auto-negotiate */
1352 {MIIM_STATUS, miim_read, &mii_parse_sr},
1353 /* Read the status */
1354 {MIIM_CIS8201_AUX_CONSTAT, miim_read, &mii_parse_cis8201},
1357 (struct phy_cmd[]) { /* shutdown */
1362 static struct phy_info phy_info_VSC8211 = {
1366 (struct phy_cmd[]) { /* config */
1367 /* Override PHY config settings */
1368 {MIIM_CIS8201_AUX_CONSTAT, MIIM_CIS8201_AUXCONSTAT_INIT, NULL},
1369 /* Set up the interface mode */
1370 {MIIM_CIS8201_EXT_CON1, MIIM_CIS8201_EXTCON1_INIT, NULL},
1371 /* Configure some basic stuff */
1372 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1375 (struct phy_cmd[]) { /* startup */
1376 /* Read the Status (2x to make sure link is right) */
1377 {MIIM_STATUS, miim_read, NULL},
1378 /* Auto-negotiate */
1379 {MIIM_STATUS, miim_read, &mii_parse_sr},
1380 /* Read the status */
1381 {MIIM_CIS8201_AUX_CONSTAT, miim_read, &mii_parse_cis8201},
1384 (struct phy_cmd[]) { /* shutdown */
1389 static struct phy_info phy_info_VSC8244 = {
1393 (struct phy_cmd[]) { /* config */
1394 /* Override PHY config settings */
1395 /* Configure some basic stuff */
1396 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1399 (struct phy_cmd[]) { /* startup */
1400 /* Read the Status (2x to make sure link is right) */
1401 {MIIM_STATUS, miim_read, NULL},
1402 /* Auto-negotiate */
1403 {MIIM_STATUS, miim_read, &mii_parse_sr},
1404 /* Read the status */
1405 {MIIM_VSC8244_AUX_CONSTAT, miim_read, &mii_parse_vsc8244},
1408 (struct phy_cmd[]) { /* shutdown */
1413 static struct phy_info phy_info_VSC8641 = {
1417 (struct phy_cmd[]) { /* config */
1418 /* Configure some basic stuff */
1419 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1422 (struct phy_cmd[]) { /* startup */
1423 /* Read the Status (2x to make sure link is right) */
1424 {MIIM_STATUS, miim_read, NULL},
1425 /* Auto-negotiate */
1426 {MIIM_STATUS, miim_read, &mii_parse_sr},
1427 /* Read the status */
1428 {MIIM_VSC8244_AUX_CONSTAT, miim_read, &mii_parse_vsc8244},
1431 (struct phy_cmd[]) { /* shutdown */
1436 static struct phy_info phy_info_VSC8221 = {
1440 (struct phy_cmd[]) { /* config */
1441 /* Configure some basic stuff */
1442 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1445 (struct phy_cmd[]) { /* startup */
1446 /* Read the Status (2x to make sure link is right) */
1447 {MIIM_STATUS, miim_read, NULL},
1448 /* Auto-negotiate */
1449 {MIIM_STATUS, miim_read, &mii_parse_sr},
1450 /* Read the status */
1451 {MIIM_VSC8244_AUX_CONSTAT, miim_read, &mii_parse_vsc8244},
1454 (struct phy_cmd[]) { /* shutdown */
1459 static struct phy_info phy_info_VSC8601 = {
1463 (struct phy_cmd[]) { /* config */
1464 /* Override PHY config settings */
1465 /* Configure some basic stuff */
1466 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1467 #ifdef CONFIG_SYS_VSC8601_SKEWFIX
1468 {MIIM_VSC8601_EPHY_CON,MIIM_VSC8601_EPHY_CON_INIT_SKEW,NULL},
1469 #if defined(CONFIG_SYS_VSC8601_SKEW_TX) && defined(CONFIG_SYS_VSC8601_SKEW_RX)
1470 {MIIM_EXT_PAGE_ACCESS,1,NULL},
1471 #define VSC8101_SKEW \
1472 (CONFIG_SYS_VSC8601_SKEW_TX << 14) | (CONFIG_SYS_VSC8601_SKEW_RX << 12)
1473 {MIIM_VSC8601_SKEW_CTRL,VSC8101_SKEW,NULL},
1474 {MIIM_EXT_PAGE_ACCESS,0,NULL},
1477 {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
1478 {MIIM_CONTROL, MIIM_CONTROL_RESTART, &mii_cr_init},
1481 (struct phy_cmd[]) { /* startup */
1482 /* Read the Status (2x to make sure link is right) */
1483 {MIIM_STATUS, miim_read, NULL},
1484 /* Auto-negotiate */
1485 {MIIM_STATUS, miim_read, &mii_parse_sr},
1486 /* Read the status */
1487 {MIIM_VSC8244_AUX_CONSTAT, miim_read, &mii_parse_vsc8244},
1490 (struct phy_cmd[]) { /* shutdown */
1495 static struct phy_info phy_info_dm9161 = {
1499 (struct phy_cmd[]) { /* config */
1500 {MIIM_CONTROL, MIIM_DM9161_CR_STOP, NULL},
1501 /* Do not bypass the scrambler/descrambler */
1502 {MIIM_DM9161_SCR, MIIM_DM9161_SCR_INIT, NULL},
1503 /* Clear 10BTCSR to default */
1504 {MIIM_DM9161_10BTCSR, MIIM_DM9161_10BTCSR_INIT, NULL},
1505 /* Configure some basic stuff */
1506 {MIIM_CONTROL, MIIM_CR_INIT, NULL},
1507 /* Restart Auto Negotiation */
1508 {MIIM_CONTROL, MIIM_DM9161_CR_RSTAN, NULL},
1511 (struct phy_cmd[]) { /* startup */
1512 /* Status is read once to clear old link state */
1513 {MIIM_STATUS, miim_read, NULL},
1514 /* Auto-negotiate */
1515 {MIIM_STATUS, miim_read, &mii_parse_sr},
1516 /* Read the status */
1517 {MIIM_DM9161_SCSR, miim_read, &mii_parse_dm9161_scsr},
1520 (struct phy_cmd[]) { /* shutdown */
1525 /* a generic flavor. */
1526 static struct phy_info phy_info_generic = {
1528 "Unknown/Generic PHY",
1530 (struct phy_cmd[]) { /* config */
1531 {PHY_BMCR, PHY_BMCR_RESET, NULL},
1532 {PHY_BMCR, PHY_BMCR_AUTON|PHY_BMCR_RST_NEG, NULL},
1535 (struct phy_cmd[]) { /* startup */
1536 {PHY_BMSR, miim_read, NULL},
1537 {PHY_BMSR, miim_read, &mii_parse_sr},
1538 {PHY_BMSR, miim_read, &mii_parse_link},
1541 (struct phy_cmd[]) { /* shutdown */
1546 static uint mii_parse_lxt971_sr2(uint mii_reg, struct tsec_private *priv)
1550 speed = mii_reg & MIIM_LXT971_SR2_SPEED_MASK;
1553 case MIIM_LXT971_SR2_10HDX:
1555 priv->duplexity = 0;
1557 case MIIM_LXT971_SR2_10FDX:
1559 priv->duplexity = 1;
1561 case MIIM_LXT971_SR2_100HDX:
1563 priv->duplexity = 0;
1567 priv->duplexity = 1;
1571 priv->duplexity = 0;
1577 static struct phy_info phy_info_lxt971 = {
1581 (struct phy_cmd[]) { /* config */
1582 {MIIM_CR, MIIM_CR_INIT, mii_cr_init}, /* autonegotiate */
1585 (struct phy_cmd[]) { /* startup - enable interrupts */
1586 /* { 0x12, 0x00f2, NULL }, */
1587 {MIIM_STATUS, miim_read, NULL},
1588 {MIIM_STATUS, miim_read, &mii_parse_sr},
1589 {MIIM_LXT971_SR2, miim_read, &mii_parse_lxt971_sr2},
1592 (struct phy_cmd[]) { /* shutdown - disable interrupts */
1597 /* Parse the DP83865's link and auto-neg status register for speed and duplex
1600 static uint mii_parse_dp83865_lanr(uint mii_reg, struct tsec_private *priv)
1602 switch (mii_reg & MIIM_DP83865_SPD_MASK) {
1604 case MIIM_DP83865_SPD_1000:
1608 case MIIM_DP83865_SPD_100:
1618 if (mii_reg & MIIM_DP83865_DPX_FULL)
1619 priv->duplexity = 1;
1621 priv->duplexity = 0;
1626 static struct phy_info phy_info_dp83865 = {
1630 (struct phy_cmd[]) { /* config */
1631 {MIIM_CONTROL, MIIM_DP83865_CR_INIT, NULL},
1634 (struct phy_cmd[]) { /* startup */
1635 /* Status is read once to clear old link state */
1636 {MIIM_STATUS, miim_read, NULL},
1637 /* Auto-negotiate */
1638 {MIIM_STATUS, miim_read, &mii_parse_sr},
1639 /* Read the link and auto-neg status */
1640 {MIIM_DP83865_LANR, miim_read, &mii_parse_dp83865_lanr},
1643 (struct phy_cmd[]) { /* shutdown */
1648 static struct phy_info phy_info_rtl8211b = {
1652 (struct phy_cmd[]) { /* config */
1653 /* Reset and configure the PHY */
1654 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1655 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
1656 {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
1657 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1658 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1661 (struct phy_cmd[]) { /* startup */
1662 /* Status is read once to clear old link state */
1663 {MIIM_STATUS, miim_read, NULL},
1664 /* Auto-negotiate */
1665 {MIIM_STATUS, miim_read, &mii_parse_sr},
1666 /* Read the status */
1667 {MIIM_RTL8211B_PHY_STATUS, miim_read, &mii_parse_RTL8211B_sr},
1670 (struct phy_cmd[]) { /* shutdown */
1675 static struct phy_info *phy_info[] = {
1681 &phy_info_M88E1011S,
1682 &phy_info_M88E1111S,
1684 &phy_info_M88E1121R,
1686 &phy_info_M88E1149S,
1696 &phy_info_generic, /* must be last; has ID 0 and 32 bit mask */
1700 /* Grab the identifier of the device's PHY, and search through
1701 * all of the known PHYs to see if one matches. If so, return
1702 * it, if not, return NULL
1704 static struct phy_info *get_phy_info(struct eth_device *dev)
1706 struct tsec_private *priv = (struct tsec_private *)dev->priv;
1707 uint phy_reg, phy_ID;
1709 struct phy_info *theInfo = NULL;
1711 /* Grab the bits from PHYIR1, and put them in the upper half */
1712 phy_reg = read_phy_reg(priv, MIIM_PHYIR1);
1713 phy_ID = (phy_reg & 0xffff) << 16;
1715 /* Grab the bits from PHYIR2, and put them in the lower half */
1716 phy_reg = read_phy_reg(priv, MIIM_PHYIR2);
1717 phy_ID |= (phy_reg & 0xffff);
1719 /* loop through all the known PHY types, and find one that */
1720 /* matches the ID we read from the PHY. */
1721 for (i = 0; phy_info[i]; i++) {
1722 if (phy_info[i]->id == (phy_ID >> phy_info[i]->shift)) {
1723 theInfo = phy_info[i];
1728 if (theInfo == &phy_info_generic) {
1729 printf("%s: No support for PHY id %x; assuming generic\n",
1732 debug("%s: PHY is %s (%x)\n", dev->name, theInfo->name, phy_ID);
1738 /* Execute the given series of commands on the given device's
1739 * PHY, running functions as necessary
1741 static void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd)
1745 volatile tsec_mdio_t *phyregs = priv->phyregs;
1747 phyregs->miimcfg = MIIMCFG_RESET;
1749 phyregs->miimcfg = MIIMCFG_INIT_VALUE;
1751 while (phyregs->miimind & MIIMIND_BUSY) ;
1753 for (i = 0; cmd->mii_reg != miim_end; i++) {
1754 if (cmd->mii_data == miim_read) {
1755 result = read_phy_reg(priv, cmd->mii_reg);
1757 if (cmd->funct != NULL)
1758 (*(cmd->funct)) (result, priv);
1761 if (cmd->funct != NULL)
1762 result = (*(cmd->funct)) (cmd->mii_reg, priv);
1764 result = cmd->mii_data;
1766 write_phy_reg(priv, cmd->mii_reg, result);
1773 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \
1774 && !defined(BITBANGMII)
1777 * Read a MII PHY register.
1782 static int tsec_miiphy_read(char *devname, unsigned char addr,
1783 unsigned char reg, unsigned short *value)
1786 struct tsec_private *priv = privlist[0];
1789 printf("Can't read PHY at address %d\n", addr);
1793 ret = (unsigned short)tsec_local_mdio_read(priv->phyregs, addr, reg);
1800 * Write a MII PHY register.
1805 static int tsec_miiphy_write(char *devname, unsigned char addr,
1806 unsigned char reg, unsigned short value)
1808 struct tsec_private *priv = privlist[0];
1811 printf("Can't write PHY at address %d\n", addr);
1815 tsec_local_mdio_write(priv->phyregs, addr, reg, value);
1822 #ifdef CONFIG_MCAST_TFTP
1824 /* CREDITS: linux gianfar driver, slightly adjusted... thanx. */
1826 /* Set the appropriate hash bit for the given addr */
1828 /* The algorithm works like so:
1829 * 1) Take the Destination Address (ie the multicast address), and
1830 * do a CRC on it (little endian), and reverse the bits of the
1832 * 2) Use the 8 most significant bits as a hash into a 256-entry
1833 * table. The table is controlled through 8 32-bit registers:
1834 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is
1835 * gaddr7. This means that the 3 most significant bits in the
1836 * hash index which gaddr register to use, and the 5 other bits
1837 * indicate which bit (assuming an IBM numbering scheme, which
1838 * for PowerPC (tm) is usually the case) in the tregister holds
1841 tsec_mcast_addr (struct eth_device *dev, u8 mcast_mac, u8 set)
1843 struct tsec_private *priv = privlist[1];
1844 volatile tsec_t *regs = priv->regs;
1845 volatile u32 *reg_array, value;
1846 u8 result, whichbit, whichreg;
1848 result = (u8)((ether_crc(MAC_ADDR_LEN,mcast_mac) >> 24) & 0xff);
1849 whichbit = result & 0x1f; /* the 5 LSB = which bit to set */
1850 whichreg = result >> 5; /* the 3 MSB = which reg to set it in */
1851 value = (1 << (31-whichbit));
1853 reg_array = &(regs->hash.gaddr0);
1856 reg_array[whichreg] |= value;
1858 reg_array[whichreg] &= ~value;
1862 #endif /* Multicast TFTP ? */