2 * Freescale Three Speed Ethernet Controller driver
4 * This software may be used and distributed according to the
5 * terms of the GNU Public License, Version 2, incorporated
8 * Copyright 2004-2009 Freescale Semiconductor, Inc.
9 * (C) Copyright 2003, Motorola, Inc.
20 #include <asm/errno.h>
24 DECLARE_GLOBAL_DATA_PTR;
28 static uint rxIdx; /* index of the current RX buffer */
29 static uint txIdx; /* index of the current TX buffer */
31 typedef volatile struct rtxbd {
32 txbd8_t txbd[TX_BUF_CNT];
33 rxbd8_t rxbd[PKTBUFSRX];
36 #define MAXCONTROLLERS (8)
38 static struct tsec_private *privlist[MAXCONTROLLERS];
39 static int num_tsecs = 0;
42 static RTXBD rtx __attribute__ ((aligned(8)));
44 #error "rtx must be 64-bit aligned"
47 static int tsec_send(struct eth_device *dev,
48 volatile void *packet, int length);
49 static int tsec_recv(struct eth_device *dev);
50 static int tsec_init(struct eth_device *dev, bd_t * bd);
51 static int tsec_initialize(bd_t * bis, struct tsec_info_struct *tsec_info);
52 static void tsec_halt(struct eth_device *dev);
53 static void init_registers(volatile tsec_t * regs);
54 static void startup_tsec(struct eth_device *dev);
55 static int init_phy(struct eth_device *dev);
56 void write_phy_reg(struct tsec_private *priv, uint regnum, uint value);
57 uint read_phy_reg(struct tsec_private *priv, uint regnum);
58 static struct phy_info *get_phy_info(struct eth_device *dev);
59 static void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd);
60 static void adjust_link(struct eth_device *dev);
61 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \
62 && !defined(BITBANGMII)
63 static int tsec_miiphy_write(char *devname, unsigned char addr,
64 unsigned char reg, unsigned short value);
65 static int tsec_miiphy_read(char *devname, unsigned char addr,
66 unsigned char reg, unsigned short *value);
68 #ifdef CONFIG_MCAST_TFTP
69 static int tsec_mcast_addr (struct eth_device *dev, u8 mcast_mac, u8 set);
72 /* Default initializations for TSEC controllers. */
74 static struct tsec_info_struct tsec_info[] = {
76 STD_TSEC_INFO(1), /* TSEC1 */
79 STD_TSEC_INFO(2), /* TSEC2 */
81 #ifdef CONFIG_MPC85XX_FEC
83 .regs = (tsec_t *)(TSEC_BASE_ADDR + 0x2000),
84 .miiregs = (tsec_mdio_t *)(MDIO_BASE_ADDR),
85 .devname = CONFIG_MPC85XX_FEC_NAME,
86 .phyaddr = FEC_PHY_ADDR,
91 STD_TSEC_INFO(3), /* TSEC3 */
94 STD_TSEC_INFO(4), /* TSEC4 */
98 int tsec_eth_init(bd_t *bis, struct tsec_info_struct *tsecs, int num)
102 for (i = 0; i < num; i++)
103 tsec_initialize(bis, &tsecs[i]);
108 int tsec_standard_init(bd_t *bis)
110 return tsec_eth_init(bis, tsec_info, ARRAY_SIZE(tsec_info));
113 /* Initialize device structure. Returns success if PHY
114 * initialization succeeded (i.e. if it recognizes the PHY)
116 static int tsec_initialize(bd_t * bis, struct tsec_info_struct *tsec_info)
118 struct eth_device *dev;
120 struct tsec_private *priv;
122 dev = (struct eth_device *)malloc(sizeof *dev);
127 memset(dev, 0, sizeof *dev);
129 priv = (struct tsec_private *)malloc(sizeof(*priv));
134 privlist[num_tsecs++] = priv;
135 priv->regs = tsec_info->regs;
136 priv->phyregs = tsec_info->miiregs;
137 priv->phyregs_sgmii = tsec_info->miiregs_sgmii;
139 priv->phyaddr = tsec_info->phyaddr;
140 priv->flags = tsec_info->flags;
142 sprintf(dev->name, tsec_info->devname);
145 dev->init = tsec_init;
146 dev->halt = tsec_halt;
147 dev->send = tsec_send;
148 dev->recv = tsec_recv;
149 #ifdef CONFIG_MCAST_TFTP
150 dev->mcast = tsec_mcast_addr;
153 /* Tell u-boot to get the addr from the env */
154 for (i = 0; i < 6; i++)
155 dev->enetaddr[i] = 0;
160 priv->regs->maccfg1 |= MACCFG1_SOFT_RESET;
161 udelay(2); /* Soft Reset must be asserted for 3 TX clocks */
162 priv->regs->maccfg1 &= ~(MACCFG1_SOFT_RESET);
164 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \
165 && !defined(BITBANGMII)
166 miiphy_register(dev->name, tsec_miiphy_read, tsec_miiphy_write);
169 /* Try to initialize PHY here, and return */
170 return init_phy(dev);
173 /* Initializes data structures and registers for the controller,
174 * and brings the interface up. Returns the link status, meaning
175 * that it returns success if the link is up, failure otherwise.
176 * This allows u-boot to find the first active controller.
178 static int tsec_init(struct eth_device *dev, bd_t * bd)
181 char tmpbuf[MAC_ADDR_LEN];
183 struct tsec_private *priv = (struct tsec_private *)dev->priv;
184 volatile tsec_t *regs = priv->regs;
186 /* Make sure the controller is stopped */
189 /* Init MACCFG2. Defaults to GMII */
190 regs->maccfg2 = MACCFG2_INIT_SETTINGS;
193 regs->ecntrl = ECNTRL_INIT_SETTINGS;
195 /* Copy the station address into the address registers.
196 * Backwards, because little endian MACS are dumb */
197 for (i = 0; i < MAC_ADDR_LEN; i++) {
198 tmpbuf[MAC_ADDR_LEN - 1 - i] = dev->enetaddr[i];
200 tempval = (tmpbuf[0] << 24) | (tmpbuf[1] << 16) | (tmpbuf[2] << 8) |
203 regs->macstnaddr1 = tempval;
205 tempval = *((uint *) (tmpbuf + 4));
207 regs->macstnaddr2 = tempval;
209 /* reset the indices to zero */
213 /* Clear out (for the most part) the other registers */
214 init_registers(regs);
216 /* Ready the device for tx/rx */
219 /* If there's no link, fail */
220 return (priv->link ? 0 : -1);
223 /* Writes the given phy's reg with value, using the specified MDIO regs */
224 static void tsec_local_mdio_write(volatile tsec_mdio_t *phyregs, uint addr,
225 uint reg, uint value)
227 int timeout = 1000000;
229 phyregs->miimadd = (addr << 8) | reg;
230 phyregs->miimcon = value;
234 while ((phyregs->miimind & MIIMIND_BUSY) && timeout--) ;
238 /* Provide the default behavior of writing the PHY of this ethernet device */
239 #define write_phy_reg(priv, regnum, value) \
240 tsec_local_mdio_write(priv->phyregs,priv->phyaddr,regnum,value)
242 /* Reads register regnum on the device's PHY through the
243 * specified registers. It lowers and raises the read
244 * command, and waits for the data to become valid (miimind
245 * notvalid bit cleared), and the bus to cease activity (miimind
246 * busy bit cleared), and then returns the value
248 static uint tsec_local_mdio_read(volatile tsec_mdio_t *phyregs,
249 uint phyid, uint regnum)
253 /* Put the address of the phy, and the register
254 * number into MIIMADD */
255 phyregs->miimadd = (phyid << 8) | regnum;
257 /* Clear the command register, and wait */
258 phyregs->miimcom = 0;
261 /* Initiate a read command, and wait */
262 phyregs->miimcom = MIIM_READ_COMMAND;
265 /* Wait for the the indication that the read is done */
266 while ((phyregs->miimind & (MIIMIND_NOTVALID | MIIMIND_BUSY))) ;
268 /* Grab the value read from the PHY */
269 value = phyregs->miimstat;
274 /* #define to provide old read_phy_reg functionality without duplicating code */
275 #define read_phy_reg(priv,regnum) \
276 tsec_local_mdio_read(priv->phyregs,priv->phyaddr,regnum)
278 #define TBIANA_SETTINGS ( \
279 TBIANA_ASYMMETRIC_PAUSE \
280 | TBIANA_SYMMETRIC_PAUSE \
281 | TBIANA_FULL_DUPLEX \
284 /* By default force the TBI PHY into 1000Mbps full duplex when in SGMII mode */
285 #ifndef CONFIG_TSEC_TBICR_SETTINGS
286 #define TBICR_SETTINGS ( \
288 | TBICR_FULL_DUPLEX \
292 #define TBICR_SETTINGS CONFIG_TSEC_TBICR_SETTINGS
293 #endif /* CONFIG_TSEC_TBICR_SETTINGS */
295 /* Configure the TBI for SGMII operation */
296 static void tsec_configure_serdes(struct tsec_private *priv)
298 /* Access TBI PHY registers at given TSEC register offset as opposed
299 * to the register offset used for external PHY accesses */
300 tsec_local_mdio_write(priv->phyregs_sgmii, priv->regs->tbipa, TBI_ANA,
302 tsec_local_mdio_write(priv->phyregs_sgmii, priv->regs->tbipa, TBI_TBICON,
304 tsec_local_mdio_write(priv->phyregs_sgmii, priv->regs->tbipa, TBI_CR,
308 /* Discover which PHY is attached to the device, and configure it
309 * properly. If the PHY is not recognized, then return 0
310 * (failure). Otherwise, return 1
312 static int init_phy(struct eth_device *dev)
314 struct tsec_private *priv = (struct tsec_private *)dev->priv;
315 struct phy_info *curphy;
316 volatile tsec_t *regs = priv->regs;
318 /* Assign a Physical address to the TBI */
319 regs->tbipa = CONFIG_SYS_TBIPA_VALUE;
322 /* Reset MII (due to new addresses) */
323 priv->phyregs->miimcfg = MIIMCFG_RESET;
325 priv->phyregs->miimcfg = MIIMCFG_INIT_VALUE;
327 while (priv->phyregs->miimind & MIIMIND_BUSY) ;
329 /* Get the cmd structure corresponding to the attached
331 curphy = get_phy_info(dev);
333 if (curphy == NULL) {
334 priv->phyinfo = NULL;
335 printf("%s: No PHY found\n", dev->name);
340 if (regs->ecntrl & ECNTRL_SGMII_MODE)
341 tsec_configure_serdes(priv);
343 priv->phyinfo = curphy;
345 phy_run_commands(priv, priv->phyinfo->config);
351 * Returns which value to write to the control register.
352 * For 10/100, the value is slightly different
354 static uint mii_cr_init(uint mii_reg, struct tsec_private * priv)
356 if (priv->flags & TSEC_GIGABIT)
357 return MIIM_CONTROL_INIT;
363 * Wait for auto-negotiation to complete, then determine link
365 static uint mii_parse_sr(uint mii_reg, struct tsec_private * priv)
368 * Wait if the link is up, and autonegotiation is in progress
369 * (ie - we're capable and it's not done)
371 mii_reg = read_phy_reg(priv, MIIM_STATUS);
372 if ((mii_reg & PHY_BMSR_AUTN_ABLE) && !(mii_reg & PHY_BMSR_AUTN_COMP)) {
375 puts("Waiting for PHY auto negotiation to complete");
376 while (!(mii_reg & PHY_BMSR_AUTN_COMP)) {
380 if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
381 puts(" TIMEOUT !\n");
387 puts("user interrupt!\n");
392 if ((i++ % 1000) == 0) {
395 udelay(1000); /* 1 ms */
396 mii_reg = read_phy_reg(priv, MIIM_STATUS);
400 /* Link status bit is latched low, read it again */
401 mii_reg = read_phy_reg(priv, MIIM_STATUS);
403 udelay(500000); /* another 500 ms (results in faster booting) */
406 priv->link = mii_reg & MIIM_STATUS_LINK ? 1 : 0;
411 /* Generic function which updates the speed and duplex. If
412 * autonegotiation is enabled, it uses the AND of the link
413 * partner's advertised capabilities and our advertised
414 * capabilities. If autonegotiation is disabled, we use the
415 * appropriate bits in the control register.
417 * Stolen from Linux's mii.c and phy_device.c
419 static uint mii_parse_link(uint mii_reg, struct tsec_private *priv)
421 /* We're using autonegotiation */
422 if (mii_reg & PHY_BMSR_AUTN_ABLE) {
426 /* Check for gigabit capability */
427 if (mii_reg & PHY_BMSR_EXT) {
428 /* We want a list of states supported by
429 * both PHYs in the link
431 gblpa = read_phy_reg(priv, PHY_1000BTSR);
432 gblpa &= read_phy_reg(priv, PHY_1000BTCR) << 2;
435 /* Set the baseline so we only have to set them
436 * if they're different
441 /* Check the gigabit fields */
442 if (gblpa & (PHY_1000BTSR_1000FD | PHY_1000BTSR_1000HD)) {
445 if (gblpa & PHY_1000BTSR_1000FD)
452 lpa = read_phy_reg(priv, PHY_ANAR);
453 lpa &= read_phy_reg(priv, PHY_ANLPAR);
455 if (lpa & (PHY_ANLPAR_TXFD | PHY_ANLPAR_TX)) {
458 if (lpa & PHY_ANLPAR_TXFD)
461 } else if (lpa & PHY_ANLPAR_10FD)
464 uint bmcr = read_phy_reg(priv, PHY_BMCR);
469 if (bmcr & PHY_BMCR_DPLX)
472 if (bmcr & PHY_BMCR_1000_MBPS)
474 else if (bmcr & PHY_BMCR_100_MBPS)
482 * "Ethernet@Wirespeed" needs to be enabled to achieve link in certain
483 * circumstances. eg a gigabit TSEC connected to a gigabit switch with
484 * a 4-wire ethernet cable. Both ends advertise gigabit, but can't
485 * link. "Ethernet@Wirespeed" reduces advertised speed until link
488 static uint mii_BCM54xx_wirespeed(uint mii_reg, struct tsec_private *priv)
490 return (read_phy_reg(priv, mii_reg) & 0x8FFF) | 0x8010;
494 * Parse the BCM54xx status register for speed and duplex information.
495 * The linux sungem_phy has this information, but in a table format.
497 static uint mii_parse_BCM54xx_sr(uint mii_reg, struct tsec_private *priv)
499 /* If there is no link, speed and duplex don't matter */
503 switch ((mii_reg & MIIM_BCM54xx_AUXSTATUS_LINKMODE_MASK) >>
504 MIIM_BCM54xx_AUXSTATUS_LINKMODE_SHIFT) {
530 printf("Auto-neg error, defaulting to 10BT/HD\n");
540 * Find out if PHY is in copper or serdes mode by looking at Expansion Reg
541 * 0x42 - "Operating Mode Status Register"
543 static int BCM8482_is_serdes(struct tsec_private *priv)
548 write_phy_reg(priv, MIIM_BCM54XX_EXP_SEL, MIIM_BCM54XX_EXP_SEL_ER | 0x42);
549 val = read_phy_reg(priv, MIIM_BCM54XX_EXP_DATA);
551 switch (val & 0x1f) {
552 case 0x0d: /* RGMII-to-100Base-FX */
553 case 0x0e: /* RGMII-to-SGMII */
554 case 0x0f: /* RGMII-to-SerDes */
555 case 0x12: /* SGMII-to-SerDes */
556 case 0x13: /* SGMII-to-100Base-FX */
557 case 0x16: /* SerDes-to-Serdes */
560 case 0x6: /* RGMII-to-Copper */
561 case 0x14: /* SGMII-to-Copper */
562 case 0x17: /* SerDes-to-Copper */
565 printf("ERROR, invalid PHY mode (0x%x\n)", val);
573 * Determine SerDes link speed and duplex from Expansion reg 0x42 "Operating
574 * Mode Status Register"
576 uint mii_parse_BCM5482_serdes_sr(struct tsec_private *priv)
581 /* Wait 1s for link - Clause 37 autonegotiation happens very fast */
583 write_phy_reg(priv, MIIM_BCM54XX_EXP_SEL,
584 MIIM_BCM54XX_EXP_SEL_ER | 0x42);
585 val = read_phy_reg(priv, MIIM_BCM54XX_EXP_DATA);
595 udelay(1000); /* 1 ms */
599 switch ((val >> 13) & 0x3) {
611 priv->duplexity = (val & 0x1000) == 0x1000;
617 * Figure out if BCM5482 is in serdes or copper mode and determine link
618 * configuration accordingly
620 static uint mii_parse_BCM5482_sr(uint mii_reg, struct tsec_private *priv)
622 if (BCM8482_is_serdes(priv)) {
623 mii_parse_BCM5482_serdes_sr(priv);
624 priv->flags |= TSEC_FIBER;
626 /* Wait for auto-negotiation to complete or fail */
627 mii_parse_sr(mii_reg, priv);
629 /* Parse BCM54xx copper aux status register */
630 mii_reg = read_phy_reg(priv, MIIM_BCM54xx_AUXSTATUS);
631 mii_parse_BCM54xx_sr(mii_reg, priv);
637 /* Parse the 88E1011's status register for speed and duplex
640 static uint mii_parse_88E1011_psr(uint mii_reg, struct tsec_private * priv)
644 mii_reg = read_phy_reg(priv, MIIM_88E1011_PHY_STATUS);
646 if ((mii_reg & MIIM_88E1011_PHYSTAT_LINK) &&
647 !(mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE)) {
650 puts("Waiting for PHY realtime link");
651 while (!(mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE)) {
652 /* Timeout reached ? */
653 if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
654 puts(" TIMEOUT !\n");
659 if ((i++ % 1000) == 0) {
662 udelay(1000); /* 1 ms */
663 mii_reg = read_phy_reg(priv, MIIM_88E1011_PHY_STATUS);
666 udelay(500000); /* another 500 ms (results in faster booting) */
668 if (mii_reg & MIIM_88E1011_PHYSTAT_LINK)
674 if (mii_reg & MIIM_88E1011_PHYSTAT_DUPLEX)
679 speed = (mii_reg & MIIM_88E1011_PHYSTAT_SPEED);
682 case MIIM_88E1011_PHYSTAT_GBIT:
685 case MIIM_88E1011_PHYSTAT_100:
695 /* Parse the RTL8211B's status register for speed and duplex
698 static uint mii_parse_RTL8211B_sr(uint mii_reg, struct tsec_private * priv)
702 mii_reg = read_phy_reg(priv, MIIM_RTL8211B_PHY_STATUS);
703 if (!(mii_reg & MIIM_RTL8211B_PHYSTAT_SPDDONE)) {
706 /* in case of timeout ->link is cleared */
708 puts("Waiting for PHY realtime link");
709 while (!(mii_reg & MIIM_RTL8211B_PHYSTAT_SPDDONE)) {
710 /* Timeout reached ? */
711 if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
712 puts(" TIMEOUT !\n");
717 if ((i++ % 1000) == 0) {
720 udelay(1000); /* 1 ms */
721 mii_reg = read_phy_reg(priv, MIIM_RTL8211B_PHY_STATUS);
724 udelay(500000); /* another 500 ms (results in faster booting) */
726 if (mii_reg & MIIM_RTL8211B_PHYSTAT_LINK)
732 if (mii_reg & MIIM_RTL8211B_PHYSTAT_DUPLEX)
737 speed = (mii_reg & MIIM_RTL8211B_PHYSTAT_SPEED);
740 case MIIM_RTL8211B_PHYSTAT_GBIT:
743 case MIIM_RTL8211B_PHYSTAT_100:
753 /* Parse the cis8201's status register for speed and duplex
756 static uint mii_parse_cis8201(uint mii_reg, struct tsec_private * priv)
760 if (mii_reg & MIIM_CIS8201_AUXCONSTAT_DUPLEX)
765 speed = mii_reg & MIIM_CIS8201_AUXCONSTAT_SPEED;
767 case MIIM_CIS8201_AUXCONSTAT_GBIT:
770 case MIIM_CIS8201_AUXCONSTAT_100:
781 /* Parse the vsc8244's status register for speed and duplex
784 static uint mii_parse_vsc8244(uint mii_reg, struct tsec_private * priv)
788 if (mii_reg & MIIM_VSC8244_AUXCONSTAT_DUPLEX)
793 speed = mii_reg & MIIM_VSC8244_AUXCONSTAT_SPEED;
795 case MIIM_VSC8244_AUXCONSTAT_GBIT:
798 case MIIM_VSC8244_AUXCONSTAT_100:
809 /* Parse the DM9161's status register for speed and duplex
812 static uint mii_parse_dm9161_scsr(uint mii_reg, struct tsec_private * priv)
814 if (mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_100H))
819 if (mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_10F))
828 * Hack to write all 4 PHYs with the LED values
830 static uint mii_cis8204_fixled(uint mii_reg, struct tsec_private * priv)
833 volatile tsec_mdio_t *regbase = priv->phyregs;
834 int timeout = 1000000;
836 for (phyid = 0; phyid < 4; phyid++) {
837 regbase->miimadd = (phyid << 8) | mii_reg;
838 regbase->miimcon = MIIM_CIS8204_SLEDCON_INIT;
842 while ((regbase->miimind & MIIMIND_BUSY) && timeout--) ;
845 return MIIM_CIS8204_SLEDCON_INIT;
848 static uint mii_cis8204_setmode(uint mii_reg, struct tsec_private * priv)
850 if (priv->flags & TSEC_REDUCED)
851 return MIIM_CIS8204_EPHYCON_INIT | MIIM_CIS8204_EPHYCON_RGMII;
853 return MIIM_CIS8204_EPHYCON_INIT;
856 static uint mii_m88e1111s_setmode(uint mii_reg, struct tsec_private *priv)
858 uint mii_data = read_phy_reg(priv, mii_reg);
860 if (priv->flags & TSEC_REDUCED)
861 mii_data = (mii_data & 0xfff0) | 0x000b;
865 /* Initialized required registers to appropriate values, zeroing
866 * those we don't care about (unless zero is bad, in which case,
867 * choose a more appropriate value)
869 static void init_registers(volatile tsec_t * regs)
872 regs->ievent = IEVENT_INIT_CLEAR;
874 regs->imask = IMASK_INIT_CLEAR;
876 regs->hash.iaddr0 = 0;
877 regs->hash.iaddr1 = 0;
878 regs->hash.iaddr2 = 0;
879 regs->hash.iaddr3 = 0;
880 regs->hash.iaddr4 = 0;
881 regs->hash.iaddr5 = 0;
882 regs->hash.iaddr6 = 0;
883 regs->hash.iaddr7 = 0;
885 regs->hash.gaddr0 = 0;
886 regs->hash.gaddr1 = 0;
887 regs->hash.gaddr2 = 0;
888 regs->hash.gaddr3 = 0;
889 regs->hash.gaddr4 = 0;
890 regs->hash.gaddr5 = 0;
891 regs->hash.gaddr6 = 0;
892 regs->hash.gaddr7 = 0;
894 regs->rctrl = 0x00000000;
896 /* Init RMON mib registers */
897 memset((void *)&(regs->rmon), 0, sizeof(rmon_mib_t));
899 regs->rmon.cam1 = 0xffffffff;
900 regs->rmon.cam2 = 0xffffffff;
902 regs->mrblr = MRBLR_INIT_SETTINGS;
904 regs->minflr = MINFLR_INIT_SETTINGS;
906 regs->attr = ATTR_INIT_SETTINGS;
907 regs->attreli = ATTRELI_INIT_SETTINGS;
911 /* Configure maccfg2 based on negotiated speed and duplex
912 * reported by PHY handling code
914 static void adjust_link(struct eth_device *dev)
916 struct tsec_private *priv = (struct tsec_private *)dev->priv;
917 volatile tsec_t *regs = priv->regs;
920 if (priv->duplexity != 0)
921 regs->maccfg2 |= MACCFG2_FULL_DUPLEX;
923 regs->maccfg2 &= ~(MACCFG2_FULL_DUPLEX);
925 switch (priv->speed) {
927 regs->maccfg2 = ((regs->maccfg2 & ~(MACCFG2_IF))
932 regs->maccfg2 = ((regs->maccfg2 & ~(MACCFG2_IF))
935 /* Set R100 bit in all modes although
936 * it is only used in RGMII mode
938 if (priv->speed == 100)
939 regs->ecntrl |= ECNTRL_R100;
941 regs->ecntrl &= ~(ECNTRL_R100);
944 printf("%s: Speed was bad\n", dev->name);
948 printf("Speed: %d, %s duplex%s\n", priv->speed,
949 (priv->duplexity) ? "full" : "half",
950 (priv->flags & TSEC_FIBER) ? ", fiber mode" : "");
953 printf("%s: No link.\n", dev->name);
957 /* Set up the buffers and their descriptors, and bring up the
960 static void startup_tsec(struct eth_device *dev)
963 struct tsec_private *priv = (struct tsec_private *)dev->priv;
964 volatile tsec_t *regs = priv->regs;
966 /* Point to the buffer descriptors */
967 regs->tbase = (unsigned int)(&rtx.txbd[txIdx]);
968 regs->rbase = (unsigned int)(&rtx.rxbd[rxIdx]);
970 /* Initialize the Rx Buffer descriptors */
971 for (i = 0; i < PKTBUFSRX; i++) {
972 rtx.rxbd[i].status = RXBD_EMPTY;
973 rtx.rxbd[i].length = 0;
974 rtx.rxbd[i].bufPtr = (uint) NetRxPackets[i];
976 rtx.rxbd[PKTBUFSRX - 1].status |= RXBD_WRAP;
978 /* Initialize the TX Buffer Descriptors */
979 for (i = 0; i < TX_BUF_CNT; i++) {
980 rtx.txbd[i].status = 0;
981 rtx.txbd[i].length = 0;
982 rtx.txbd[i].bufPtr = 0;
984 rtx.txbd[TX_BUF_CNT - 1].status |= TXBD_WRAP;
986 /* Start up the PHY */
988 phy_run_commands(priv, priv->phyinfo->startup);
992 /* Enable Transmit and Receive */
993 regs->maccfg1 |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
995 /* Tell the DMA it is clear to go */
996 regs->dmactrl |= DMACTRL_INIT_SETTINGS;
997 regs->tstat = TSTAT_CLEAR_THALT;
998 regs->rstat = RSTAT_CLEAR_RHALT;
999 regs->dmactrl &= ~(DMACTRL_GRS | DMACTRL_GTS);
1002 /* This returns the status bits of the device. The return value
1003 * is never checked, and this is what the 8260 driver did, so we
1004 * do the same. Presumably, this would be zero if there were no
1007 static int tsec_send(struct eth_device *dev, volatile void *packet, int length)
1011 struct tsec_private *priv = (struct tsec_private *)dev->priv;
1012 volatile tsec_t *regs = priv->regs;
1014 /* Find an empty buffer descriptor */
1015 for (i = 0; rtx.txbd[txIdx].status & TXBD_READY; i++) {
1016 if (i >= TOUT_LOOP) {
1017 debug("%s: tsec: tx buffers full\n", dev->name);
1022 rtx.txbd[txIdx].bufPtr = (uint) packet;
1023 rtx.txbd[txIdx].length = length;
1024 rtx.txbd[txIdx].status |=
1025 (TXBD_READY | TXBD_LAST | TXBD_CRC | TXBD_INTERRUPT);
1027 /* Tell the DMA to go */
1028 regs->tstat = TSTAT_CLEAR_THALT;
1030 /* Wait for buffer to be transmitted */
1031 for (i = 0; rtx.txbd[txIdx].status & TXBD_READY; i++) {
1032 if (i >= TOUT_LOOP) {
1033 debug("%s: tsec: tx error\n", dev->name);
1038 txIdx = (txIdx + 1) % TX_BUF_CNT;
1039 result = rtx.txbd[txIdx].status & TXBD_STATS;
1044 static int tsec_recv(struct eth_device *dev)
1047 struct tsec_private *priv = (struct tsec_private *)dev->priv;
1048 volatile tsec_t *regs = priv->regs;
1050 while (!(rtx.rxbd[rxIdx].status & RXBD_EMPTY)) {
1052 length = rtx.rxbd[rxIdx].length;
1054 /* Send the packet up if there were no errors */
1055 if (!(rtx.rxbd[rxIdx].status & RXBD_STATS)) {
1056 NetReceive(NetRxPackets[rxIdx], length - 4);
1058 printf("Got error %x\n",
1059 (rtx.rxbd[rxIdx].status & RXBD_STATS));
1062 rtx.rxbd[rxIdx].length = 0;
1064 /* Set the wrap bit if this is the last element in the list */
1065 rtx.rxbd[rxIdx].status =
1066 RXBD_EMPTY | (((rxIdx + 1) == PKTBUFSRX) ? RXBD_WRAP : 0);
1068 rxIdx = (rxIdx + 1) % PKTBUFSRX;
1071 if (regs->ievent & IEVENT_BSY) {
1072 regs->ievent = IEVENT_BSY;
1073 regs->rstat = RSTAT_CLEAR_RHALT;
1080 /* Stop the interface */
1081 static void tsec_halt(struct eth_device *dev)
1083 struct tsec_private *priv = (struct tsec_private *)dev->priv;
1084 volatile tsec_t *regs = priv->regs;
1086 regs->dmactrl &= ~(DMACTRL_GRS | DMACTRL_GTS);
1087 regs->dmactrl |= (DMACTRL_GRS | DMACTRL_GTS);
1089 while ((regs->ievent & (IEVENT_GRSC | IEVENT_GTSC))
1090 != (IEVENT_GRSC | IEVENT_GTSC)) ;
1092 regs->maccfg1 &= ~(MACCFG1_TX_EN | MACCFG1_RX_EN);
1094 /* Shut down the PHY, as needed */
1096 phy_run_commands(priv, priv->phyinfo->shutdown);
1099 static struct phy_info phy_info_M88E1149S = {
1103 (struct phy_cmd[]) { /* config */
1104 /* Reset and configure the PHY */
1105 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1107 {0x1e, 0x200c, NULL},
1110 {0x1e, 0x100, NULL},
1111 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
1112 {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
1113 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1114 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1117 (struct phy_cmd[]) { /* startup */
1118 /* Status is read once to clear old link state */
1119 {MIIM_STATUS, miim_read, NULL},
1120 /* Auto-negotiate */
1121 {MIIM_STATUS, miim_read, &mii_parse_sr},
1122 /* Read the status */
1123 {MIIM_88E1011_PHY_STATUS, miim_read, &mii_parse_88E1011_psr},
1126 (struct phy_cmd[]) { /* shutdown */
1131 /* The 5411 id is 0x206070, the 5421 is 0x2060e0 */
1132 static struct phy_info phy_info_BCM5461S = {
1133 0x02060c1, /* 5461 ID */
1134 "Broadcom BCM5461S",
1135 0, /* not clear to me what minor revisions we can shift away */
1136 (struct phy_cmd[]) { /* config */
1137 /* Reset and configure the PHY */
1138 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1139 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
1140 {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
1141 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1142 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1145 (struct phy_cmd[]) { /* startup */
1146 /* Status is read once to clear old link state */
1147 {MIIM_STATUS, miim_read, NULL},
1148 /* Auto-negotiate */
1149 {MIIM_STATUS, miim_read, &mii_parse_sr},
1150 /* Read the status */
1151 {MIIM_BCM54xx_AUXSTATUS, miim_read, &mii_parse_BCM54xx_sr},
1154 (struct phy_cmd[]) { /* shutdown */
1159 static struct phy_info phy_info_BCM5464S = {
1160 0x02060b1, /* 5464 ID */
1161 "Broadcom BCM5464S",
1162 0, /* not clear to me what minor revisions we can shift away */
1163 (struct phy_cmd[]) { /* config */
1164 /* Reset and configure the PHY */
1165 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1166 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
1167 {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
1168 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1169 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1172 (struct phy_cmd[]) { /* startup */
1173 /* Status is read once to clear old link state */
1174 {MIIM_STATUS, miim_read, NULL},
1175 /* Auto-negotiate */
1176 {MIIM_STATUS, miim_read, &mii_parse_sr},
1177 /* Read the status */
1178 {MIIM_BCM54xx_AUXSTATUS, miim_read, &mii_parse_BCM54xx_sr},
1181 (struct phy_cmd[]) { /* shutdown */
1186 static struct phy_info phy_info_BCM5482S = {
1188 "Broadcom BCM5482S",
1190 (struct phy_cmd[]) { /* config */
1191 /* Reset and configure the PHY */
1192 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1193 /* Setup read from auxilary control shadow register 7 */
1194 {MIIM_BCM54xx_AUXCNTL, MIIM_BCM54xx_AUXCNTL_ENCODE(7), NULL},
1195 /* Read Misc Control register and or in Ethernet@Wirespeed */
1196 {MIIM_BCM54xx_AUXCNTL, 0, &mii_BCM54xx_wirespeed},
1197 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1198 /* Initial config/enable of secondary SerDes interface */
1199 {MIIM_BCM54XX_SHD, MIIM_BCM54XX_SHD_WR_ENCODE(0x14, 0xf), NULL},
1200 /* Write intial value to secondary SerDes Contol */
1201 {MIIM_BCM54XX_EXP_SEL, MIIM_BCM54XX_EXP_SEL_SSD | 0, NULL},
1202 {MIIM_BCM54XX_EXP_DATA, MIIM_CONTROL_RESTART, NULL},
1203 /* Enable copper/fiber auto-detect */
1204 {MIIM_BCM54XX_SHD, MIIM_BCM54XX_SHD_WR_ENCODE(0x1e, 0x201)},
1207 (struct phy_cmd[]) { /* startup */
1208 /* Status is read once to clear old link state */
1209 {MIIM_STATUS, miim_read, NULL},
1210 /* Determine copper/fiber, auto-negotiate, and read the result */
1211 {MIIM_STATUS, miim_read, &mii_parse_BCM5482_sr},
1214 (struct phy_cmd[]) { /* shutdown */
1219 static struct phy_info phy_info_M88E1011S = {
1223 (struct phy_cmd[]) { /* config */
1224 /* Reset and configure the PHY */
1225 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1227 {0x1e, 0x200c, NULL},
1230 {0x1e, 0x100, NULL},
1231 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
1232 {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
1233 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1234 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1237 (struct phy_cmd[]) { /* startup */
1238 /* Status is read once to clear old link state */
1239 {MIIM_STATUS, miim_read, NULL},
1240 /* Auto-negotiate */
1241 {MIIM_STATUS, miim_read, &mii_parse_sr},
1242 /* Read the status */
1243 {MIIM_88E1011_PHY_STATUS, miim_read, &mii_parse_88E1011_psr},
1246 (struct phy_cmd[]) { /* shutdown */
1251 static struct phy_info phy_info_M88E1111S = {
1255 (struct phy_cmd[]) { /* config */
1256 /* Reset and configure the PHY */
1257 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1258 {0x1b, 0x848f, &mii_m88e1111s_setmode},
1259 {0x14, 0x0cd2, NULL}, /* Delay RGMII TX and RX */
1260 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
1261 {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
1262 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1263 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1266 (struct phy_cmd[]) { /* startup */
1267 /* Status is read once to clear old link state */
1268 {MIIM_STATUS, miim_read, NULL},
1269 /* Auto-negotiate */
1270 {MIIM_STATUS, miim_read, &mii_parse_sr},
1271 /* Read the status */
1272 {MIIM_88E1011_PHY_STATUS, miim_read, &mii_parse_88E1011_psr},
1275 (struct phy_cmd[]) { /* shutdown */
1280 static struct phy_info phy_info_M88E1118 = {
1284 (struct phy_cmd[]) { /* config */
1285 /* Reset and configure the PHY */
1286 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1287 {0x16, 0x0002, NULL}, /* Change Page Number */
1288 {0x15, 0x1070, NULL}, /* Delay RGMII TX and RX */
1289 {0x16, 0x0003, NULL}, /* Change Page Number */
1290 {0x10, 0x021e, NULL}, /* Adjust LED control */
1291 {0x16, 0x0000, NULL}, /* Change Page Number */
1292 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
1293 {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
1294 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1295 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1298 (struct phy_cmd[]) { /* startup */
1299 {0x16, 0x0000, NULL}, /* Change Page Number */
1300 /* Status is read once to clear old link state */
1301 {MIIM_STATUS, miim_read, NULL},
1302 /* Auto-negotiate */
1303 {MIIM_STATUS, miim_read, &mii_parse_sr},
1304 /* Read the status */
1305 {MIIM_88E1011_PHY_STATUS, miim_read,
1306 &mii_parse_88E1011_psr},
1309 (struct phy_cmd[]) { /* shutdown */
1315 * Since to access LED register we need do switch the page, we
1316 * do LED configuring in the miim_read-like function as follows
1318 static uint mii_88E1121_set_led (uint mii_reg, struct tsec_private *priv)
1322 /* Switch the page to access the led register */
1323 pg = read_phy_reg(priv, MIIM_88E1121_PHY_PAGE);
1324 write_phy_reg(priv, MIIM_88E1121_PHY_PAGE, MIIM_88E1121_PHY_LED_PAGE);
1326 /* Configure leds */
1327 write_phy_reg(priv, MIIM_88E1121_PHY_LED_CTRL,
1328 MIIM_88E1121_PHY_LED_DEF);
1330 /* Restore the page pointer */
1331 write_phy_reg(priv, MIIM_88E1121_PHY_PAGE, pg);
1335 static struct phy_info phy_info_M88E1121R = {
1339 (struct phy_cmd[]) { /* config */
1340 /* Reset and configure the PHY */
1341 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1342 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
1343 {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
1344 /* Configure leds */
1345 {MIIM_88E1121_PHY_LED_CTRL, miim_read, &mii_88E1121_set_led},
1346 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1347 /* Disable IRQs and de-assert interrupt */
1348 {MIIM_88E1121_PHY_IRQ_EN, 0, NULL},
1349 {MIIM_88E1121_PHY_IRQ_STATUS, miim_read, NULL},
1352 (struct phy_cmd[]) { /* startup */
1353 /* Status is read once to clear old link state */
1354 {MIIM_STATUS, miim_read, NULL},
1355 {MIIM_STATUS, miim_read, &mii_parse_sr},
1356 {MIIM_STATUS, miim_read, &mii_parse_link},
1359 (struct phy_cmd[]) { /* shutdown */
1364 static unsigned int m88e1145_setmode(uint mii_reg, struct tsec_private *priv)
1366 uint mii_data = read_phy_reg(priv, mii_reg);
1368 /* Setting MIIM_88E1145_PHY_EXT_CR */
1369 if (priv->flags & TSEC_REDUCED)
1371 MIIM_M88E1145_RGMII_RX_DELAY | MIIM_M88E1145_RGMII_TX_DELAY;
1376 static struct phy_info phy_info_M88E1145 = {
1380 (struct phy_cmd[]) { /* config */
1382 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1390 /* Configure the PHY */
1391 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
1392 {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
1393 {MIIM_88E1011_PHY_SCR, MIIM_88E1011_PHY_MDI_X_AUTO, NULL},
1394 {MIIM_88E1145_PHY_EXT_CR, 0, &m88e1145_setmode},
1395 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1396 {MIIM_CONTROL, MIIM_CONTROL_INIT, NULL},
1399 (struct phy_cmd[]) { /* startup */
1400 /* Status is read once to clear old link state */
1401 {MIIM_STATUS, miim_read, NULL},
1402 /* Auto-negotiate */
1403 {MIIM_STATUS, miim_read, &mii_parse_sr},
1404 {MIIM_88E1111_PHY_LED_CONTROL, MIIM_88E1111_PHY_LED_DIRECT, NULL},
1405 /* Read the Status */
1406 {MIIM_88E1011_PHY_STATUS, miim_read, &mii_parse_88E1011_psr},
1409 (struct phy_cmd[]) { /* shutdown */
1414 static struct phy_info phy_info_cis8204 = {
1418 (struct phy_cmd[]) { /* config */
1419 /* Override PHY config settings */
1420 {MIIM_CIS8201_AUX_CONSTAT, MIIM_CIS8201_AUXCONSTAT_INIT, NULL},
1421 /* Configure some basic stuff */
1422 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1423 {MIIM_CIS8204_SLED_CON, MIIM_CIS8204_SLEDCON_INIT,
1424 &mii_cis8204_fixled},
1425 {MIIM_CIS8204_EPHY_CON, MIIM_CIS8204_EPHYCON_INIT,
1426 &mii_cis8204_setmode},
1429 (struct phy_cmd[]) { /* startup */
1430 /* Read the Status (2x to make sure link is right) */
1431 {MIIM_STATUS, miim_read, NULL},
1432 /* Auto-negotiate */
1433 {MIIM_STATUS, miim_read, &mii_parse_sr},
1434 /* Read the status */
1435 {MIIM_CIS8201_AUX_CONSTAT, miim_read, &mii_parse_cis8201},
1438 (struct phy_cmd[]) { /* shutdown */
1444 static struct phy_info phy_info_cis8201 = {
1448 (struct phy_cmd[]) { /* config */
1449 /* Override PHY config settings */
1450 {MIIM_CIS8201_AUX_CONSTAT, MIIM_CIS8201_AUXCONSTAT_INIT, NULL},
1451 /* Set up the interface mode */
1452 {MIIM_CIS8201_EXT_CON1, MIIM_CIS8201_EXTCON1_INIT, NULL},
1453 /* Configure some basic stuff */
1454 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1457 (struct phy_cmd[]) { /* startup */
1458 /* Read the Status (2x to make sure link is right) */
1459 {MIIM_STATUS, miim_read, NULL},
1460 /* Auto-negotiate */
1461 {MIIM_STATUS, miim_read, &mii_parse_sr},
1462 /* Read the status */
1463 {MIIM_CIS8201_AUX_CONSTAT, miim_read, &mii_parse_cis8201},
1466 (struct phy_cmd[]) { /* shutdown */
1471 static struct phy_info phy_info_VSC8211 = {
1475 (struct phy_cmd[]) { /* config */
1476 /* Override PHY config settings */
1477 {MIIM_CIS8201_AUX_CONSTAT, MIIM_CIS8201_AUXCONSTAT_INIT, NULL},
1478 /* Set up the interface mode */
1479 {MIIM_CIS8201_EXT_CON1, MIIM_CIS8201_EXTCON1_INIT, NULL},
1480 /* Configure some basic stuff */
1481 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1484 (struct phy_cmd[]) { /* startup */
1485 /* Read the Status (2x to make sure link is right) */
1486 {MIIM_STATUS, miim_read, NULL},
1487 /* Auto-negotiate */
1488 {MIIM_STATUS, miim_read, &mii_parse_sr},
1489 /* Read the status */
1490 {MIIM_CIS8201_AUX_CONSTAT, miim_read, &mii_parse_cis8201},
1493 (struct phy_cmd[]) { /* shutdown */
1498 static struct phy_info phy_info_VSC8244 = {
1502 (struct phy_cmd[]) { /* config */
1503 /* Override PHY config settings */
1504 /* Configure some basic stuff */
1505 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1508 (struct phy_cmd[]) { /* startup */
1509 /* Read the Status (2x to make sure link is right) */
1510 {MIIM_STATUS, miim_read, NULL},
1511 /* Auto-negotiate */
1512 {MIIM_STATUS, miim_read, &mii_parse_sr},
1513 /* Read the status */
1514 {MIIM_VSC8244_AUX_CONSTAT, miim_read, &mii_parse_vsc8244},
1517 (struct phy_cmd[]) { /* shutdown */
1522 static struct phy_info phy_info_VSC8641 = {
1526 (struct phy_cmd[]) { /* config */
1527 /* Configure some basic stuff */
1528 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1531 (struct phy_cmd[]) { /* startup */
1532 /* Read the Status (2x to make sure link is right) */
1533 {MIIM_STATUS, miim_read, NULL},
1534 /* Auto-negotiate */
1535 {MIIM_STATUS, miim_read, &mii_parse_sr},
1536 /* Read the status */
1537 {MIIM_VSC8244_AUX_CONSTAT, miim_read, &mii_parse_vsc8244},
1540 (struct phy_cmd[]) { /* shutdown */
1545 static struct phy_info phy_info_VSC8221 = {
1549 (struct phy_cmd[]) { /* config */
1550 /* Configure some basic stuff */
1551 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1554 (struct phy_cmd[]) { /* startup */
1555 /* Read the Status (2x to make sure link is right) */
1556 {MIIM_STATUS, miim_read, NULL},
1557 /* Auto-negotiate */
1558 {MIIM_STATUS, miim_read, &mii_parse_sr},
1559 /* Read the status */
1560 {MIIM_VSC8244_AUX_CONSTAT, miim_read, &mii_parse_vsc8244},
1563 (struct phy_cmd[]) { /* shutdown */
1568 static struct phy_info phy_info_VSC8601 = {
1572 (struct phy_cmd[]) { /* config */
1573 /* Override PHY config settings */
1574 /* Configure some basic stuff */
1575 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1576 #ifdef CONFIG_SYS_VSC8601_SKEWFIX
1577 {MIIM_VSC8601_EPHY_CON,MIIM_VSC8601_EPHY_CON_INIT_SKEW,NULL},
1578 #if defined(CONFIG_SYS_VSC8601_SKEW_TX) && defined(CONFIG_SYS_VSC8601_SKEW_RX)
1579 {MIIM_EXT_PAGE_ACCESS,1,NULL},
1580 #define VSC8101_SKEW \
1581 (CONFIG_SYS_VSC8601_SKEW_TX << 14) | (CONFIG_SYS_VSC8601_SKEW_RX << 12)
1582 {MIIM_VSC8601_SKEW_CTRL,VSC8101_SKEW,NULL},
1583 {MIIM_EXT_PAGE_ACCESS,0,NULL},
1586 {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
1587 {MIIM_CONTROL, MIIM_CONTROL_RESTART, &mii_cr_init},
1590 (struct phy_cmd[]) { /* startup */
1591 /* Read the Status (2x to make sure link is right) */
1592 {MIIM_STATUS, miim_read, NULL},
1593 /* Auto-negotiate */
1594 {MIIM_STATUS, miim_read, &mii_parse_sr},
1595 /* Read the status */
1596 {MIIM_VSC8244_AUX_CONSTAT, miim_read, &mii_parse_vsc8244},
1599 (struct phy_cmd[]) { /* shutdown */
1604 static struct phy_info phy_info_dm9161 = {
1608 (struct phy_cmd[]) { /* config */
1609 {MIIM_CONTROL, MIIM_DM9161_CR_STOP, NULL},
1610 /* Do not bypass the scrambler/descrambler */
1611 {MIIM_DM9161_SCR, MIIM_DM9161_SCR_INIT, NULL},
1612 /* Clear 10BTCSR to default */
1613 {MIIM_DM9161_10BTCSR, MIIM_DM9161_10BTCSR_INIT, NULL},
1614 /* Configure some basic stuff */
1615 {MIIM_CONTROL, MIIM_CR_INIT, NULL},
1616 /* Restart Auto Negotiation */
1617 {MIIM_CONTROL, MIIM_DM9161_CR_RSTAN, NULL},
1620 (struct phy_cmd[]) { /* startup */
1621 /* Status is read once to clear old link state */
1622 {MIIM_STATUS, miim_read, NULL},
1623 /* Auto-negotiate */
1624 {MIIM_STATUS, miim_read, &mii_parse_sr},
1625 /* Read the status */
1626 {MIIM_DM9161_SCSR, miim_read, &mii_parse_dm9161_scsr},
1629 (struct phy_cmd[]) { /* shutdown */
1635 static struct phy_info phy_info_ksz804 = {
1637 "Micrel KSZ804 PHY",
1639 (struct phy_cmd[]) { /* config */
1640 {PHY_BMCR, PHY_BMCR_RESET, NULL},
1641 {PHY_BMCR, PHY_BMCR_AUTON|PHY_BMCR_RST_NEG, NULL},
1644 (struct phy_cmd[]) { /* startup */
1645 {PHY_BMSR, miim_read, NULL},
1646 {PHY_BMSR, miim_read, &mii_parse_sr},
1647 {PHY_BMSR, miim_read, &mii_parse_link},
1650 (struct phy_cmd[]) { /* shutdown */
1655 /* a generic flavor. */
1656 static struct phy_info phy_info_generic = {
1658 "Unknown/Generic PHY",
1660 (struct phy_cmd[]) { /* config */
1661 {PHY_BMCR, PHY_BMCR_RESET, NULL},
1662 {PHY_BMCR, PHY_BMCR_AUTON|PHY_BMCR_RST_NEG, NULL},
1665 (struct phy_cmd[]) { /* startup */
1666 {PHY_BMSR, miim_read, NULL},
1667 {PHY_BMSR, miim_read, &mii_parse_sr},
1668 {PHY_BMSR, miim_read, &mii_parse_link},
1671 (struct phy_cmd[]) { /* shutdown */
1676 static uint mii_parse_lxt971_sr2(uint mii_reg, struct tsec_private *priv)
1680 speed = mii_reg & MIIM_LXT971_SR2_SPEED_MASK;
1683 case MIIM_LXT971_SR2_10HDX:
1685 priv->duplexity = 0;
1687 case MIIM_LXT971_SR2_10FDX:
1689 priv->duplexity = 1;
1691 case MIIM_LXT971_SR2_100HDX:
1693 priv->duplexity = 0;
1697 priv->duplexity = 1;
1701 priv->duplexity = 0;
1707 static struct phy_info phy_info_lxt971 = {
1711 (struct phy_cmd[]) { /* config */
1712 {MIIM_CR, MIIM_CR_INIT, mii_cr_init}, /* autonegotiate */
1715 (struct phy_cmd[]) { /* startup - enable interrupts */
1716 /* { 0x12, 0x00f2, NULL }, */
1717 {MIIM_STATUS, miim_read, NULL},
1718 {MIIM_STATUS, miim_read, &mii_parse_sr},
1719 {MIIM_LXT971_SR2, miim_read, &mii_parse_lxt971_sr2},
1722 (struct phy_cmd[]) { /* shutdown - disable interrupts */
1727 /* Parse the DP83865's link and auto-neg status register for speed and duplex
1730 static uint mii_parse_dp83865_lanr(uint mii_reg, struct tsec_private *priv)
1732 switch (mii_reg & MIIM_DP83865_SPD_MASK) {
1734 case MIIM_DP83865_SPD_1000:
1738 case MIIM_DP83865_SPD_100:
1748 if (mii_reg & MIIM_DP83865_DPX_FULL)
1749 priv->duplexity = 1;
1751 priv->duplexity = 0;
1756 static struct phy_info phy_info_dp83865 = {
1760 (struct phy_cmd[]) { /* config */
1761 {MIIM_CONTROL, MIIM_DP83865_CR_INIT, NULL},
1764 (struct phy_cmd[]) { /* startup */
1765 /* Status is read once to clear old link state */
1766 {MIIM_STATUS, miim_read, NULL},
1767 /* Auto-negotiate */
1768 {MIIM_STATUS, miim_read, &mii_parse_sr},
1769 /* Read the link and auto-neg status */
1770 {MIIM_DP83865_LANR, miim_read, &mii_parse_dp83865_lanr},
1773 (struct phy_cmd[]) { /* shutdown */
1778 static struct phy_info phy_info_rtl8211b = {
1782 (struct phy_cmd[]) { /* config */
1783 /* Reset and configure the PHY */
1784 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1785 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
1786 {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
1787 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1788 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1791 (struct phy_cmd[]) { /* startup */
1792 /* Status is read once to clear old link state */
1793 {MIIM_STATUS, miim_read, NULL},
1794 /* Auto-negotiate */
1795 {MIIM_STATUS, miim_read, &mii_parse_sr},
1796 /* Read the status */
1797 {MIIM_RTL8211B_PHY_STATUS, miim_read, &mii_parse_RTL8211B_sr},
1800 (struct phy_cmd[]) { /* shutdown */
1805 static struct phy_info *phy_info[] = {
1811 &phy_info_M88E1011S,
1812 &phy_info_M88E1111S,
1814 &phy_info_M88E1121R,
1816 &phy_info_M88E1149S,
1827 &phy_info_generic, /* must be last; has ID 0 and 32 bit mask */
1831 /* Grab the identifier of the device's PHY, and search through
1832 * all of the known PHYs to see if one matches. If so, return
1833 * it, if not, return NULL
1835 static struct phy_info *get_phy_info(struct eth_device *dev)
1837 struct tsec_private *priv = (struct tsec_private *)dev->priv;
1838 uint phy_reg, phy_ID;
1840 struct phy_info *theInfo = NULL;
1842 /* Grab the bits from PHYIR1, and put them in the upper half */
1843 phy_reg = read_phy_reg(priv, MIIM_PHYIR1);
1844 phy_ID = (phy_reg & 0xffff) << 16;
1846 /* Grab the bits from PHYIR2, and put them in the lower half */
1847 phy_reg = read_phy_reg(priv, MIIM_PHYIR2);
1848 phy_ID |= (phy_reg & 0xffff);
1850 /* loop through all the known PHY types, and find one that */
1851 /* matches the ID we read from the PHY. */
1852 for (i = 0; phy_info[i]; i++) {
1853 if (phy_info[i]->id == (phy_ID >> phy_info[i]->shift)) {
1854 theInfo = phy_info[i];
1859 if (theInfo == &phy_info_generic) {
1860 printf("%s: No support for PHY id %x; assuming generic\n",
1863 debug("%s: PHY is %s (%x)\n", dev->name, theInfo->name, phy_ID);
1869 /* Execute the given series of commands on the given device's
1870 * PHY, running functions as necessary
1872 static void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd)
1876 volatile tsec_mdio_t *phyregs = priv->phyregs;
1878 phyregs->miimcfg = MIIMCFG_RESET;
1880 phyregs->miimcfg = MIIMCFG_INIT_VALUE;
1882 while (phyregs->miimind & MIIMIND_BUSY) ;
1884 for (i = 0; cmd->mii_reg != miim_end; i++) {
1885 if (cmd->mii_data == miim_read) {
1886 result = read_phy_reg(priv, cmd->mii_reg);
1888 if (cmd->funct != NULL)
1889 (*(cmd->funct)) (result, priv);
1892 if (cmd->funct != NULL)
1893 result = (*(cmd->funct)) (cmd->mii_reg, priv);
1895 result = cmd->mii_data;
1897 write_phy_reg(priv, cmd->mii_reg, result);
1904 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \
1905 && !defined(BITBANGMII)
1908 * Read a MII PHY register.
1913 static int tsec_miiphy_read(char *devname, unsigned char addr,
1914 unsigned char reg, unsigned short *value)
1917 struct tsec_private *priv = privlist[0];
1920 printf("Can't read PHY at address %d\n", addr);
1924 ret = (unsigned short)tsec_local_mdio_read(priv->phyregs, addr, reg);
1931 * Write a MII PHY register.
1936 static int tsec_miiphy_write(char *devname, unsigned char addr,
1937 unsigned char reg, unsigned short value)
1939 struct tsec_private *priv = privlist[0];
1942 printf("Can't write PHY at address %d\n", addr);
1946 tsec_local_mdio_write(priv->phyregs, addr, reg, value);
1953 #ifdef CONFIG_MCAST_TFTP
1955 /* CREDITS: linux gianfar driver, slightly adjusted... thanx. */
1957 /* Set the appropriate hash bit for the given addr */
1959 /* The algorithm works like so:
1960 * 1) Take the Destination Address (ie the multicast address), and
1961 * do a CRC on it (little endian), and reverse the bits of the
1963 * 2) Use the 8 most significant bits as a hash into a 256-entry
1964 * table. The table is controlled through 8 32-bit registers:
1965 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is
1966 * gaddr7. This means that the 3 most significant bits in the
1967 * hash index which gaddr register to use, and the 5 other bits
1968 * indicate which bit (assuming an IBM numbering scheme, which
1969 * for PowerPC (tm) is usually the case) in the tregister holds
1972 tsec_mcast_addr (struct eth_device *dev, u8 mcast_mac, u8 set)
1974 struct tsec_private *priv = privlist[1];
1975 volatile tsec_t *regs = priv->regs;
1976 volatile u32 *reg_array, value;
1977 u8 result, whichbit, whichreg;
1979 result = (u8)((ether_crc(MAC_ADDR_LEN,mcast_mac) >> 24) & 0xff);
1980 whichbit = result & 0x1f; /* the 5 LSB = which bit to set */
1981 whichreg = result >> 5; /* the 3 MSB = which reg to set it in */
1982 value = (1 << (31-whichbit));
1984 reg_array = &(regs->hash.gaddr0);
1987 reg_array[whichreg] |= value;
1989 reg_array[whichreg] &= ~value;
1993 #endif /* Multicast TFTP ? */