2 * Freescale Three Speed Ethernet Controller driver
4 * This software may be used and distributed according to the
5 * terms of the GNU Public License, Version 2, incorporated
8 * Copyright (C) 2004-2009 Freescale Semiconductor, Inc.
9 * (C) Copyright 2003, Motorola, Inc.
20 #include <asm/errno.h>
24 DECLARE_GLOBAL_DATA_PTR;
28 static uint rxIdx; /* index of the current RX buffer */
29 static uint txIdx; /* index of the current TX buffer */
31 typedef volatile struct rtxbd {
32 txbd8_t txbd[TX_BUF_CNT];
33 rxbd8_t rxbd[PKTBUFSRX];
36 #define MAXCONTROLLERS (8)
38 static int relocated = 0;
40 static struct tsec_private *privlist[MAXCONTROLLERS];
41 static int num_tsecs = 0;
44 static RTXBD rtx __attribute__ ((aligned(8)));
46 #error "rtx must be 64-bit aligned"
49 static int tsec_send(struct eth_device *dev,
50 volatile void *packet, int length);
51 static int tsec_recv(struct eth_device *dev);
52 static int tsec_init(struct eth_device *dev, bd_t * bd);
53 static void tsec_halt(struct eth_device *dev);
54 static void init_registers(volatile tsec_t * regs);
55 static void startup_tsec(struct eth_device *dev);
56 static int init_phy(struct eth_device *dev);
57 void write_phy_reg(struct tsec_private *priv, uint regnum, uint value);
58 uint read_phy_reg(struct tsec_private *priv, uint regnum);
59 struct phy_info *get_phy_info(struct eth_device *dev);
60 void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd);
61 static void adjust_link(struct eth_device *dev);
62 static void relocate_cmds(void);
63 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \
64 && !defined(BITBANGMII)
65 static int tsec_miiphy_write(char *devname, unsigned char addr,
66 unsigned char reg, unsigned short value);
67 static int tsec_miiphy_read(char *devname, unsigned char addr,
68 unsigned char reg, unsigned short *value);
70 #ifdef CONFIG_MCAST_TFTP
71 static int tsec_mcast_addr (struct eth_device *dev, u8 mcast_mac, u8 set);
74 /* Default initializations for TSEC controllers. */
76 static struct tsec_info_struct tsec_info[] = {
78 STD_TSEC_INFO(1), /* TSEC1 */
81 STD_TSEC_INFO(2), /* TSEC2 */
83 #ifdef CONFIG_MPC85XX_FEC
85 .regs = (tsec_t *)(TSEC_BASE_ADDR + 0x2000),
86 .miiregs = (tsec_t *)(TSEC_BASE_ADDR),
87 .devname = CONFIG_MPC85XX_FEC_NAME,
88 .phyaddr = FEC_PHY_ADDR,
93 STD_TSEC_INFO(3), /* TSEC3 */
96 STD_TSEC_INFO(4), /* TSEC4 */
100 int tsec_eth_init(bd_t *bis, struct tsec_info_struct *tsecs, int num)
104 for (i = 0; i < num; i++)
105 tsec_initialize(bis, &tsecs[i]);
110 int tsec_standard_init(bd_t *bis)
112 return tsec_eth_init(bis, tsec_info, ARRAY_SIZE(tsec_info));
115 /* Initialize device structure. Returns success if PHY
116 * initialization succeeded (i.e. if it recognizes the PHY)
118 int tsec_initialize(bd_t * bis, struct tsec_info_struct *tsec_info)
120 struct eth_device *dev;
122 struct tsec_private *priv;
124 dev = (struct eth_device *)malloc(sizeof *dev);
129 memset(dev, 0, sizeof *dev);
131 priv = (struct tsec_private *)malloc(sizeof(*priv));
136 privlist[num_tsecs++] = priv;
137 priv->regs = tsec_info->regs;
138 priv->phyregs = tsec_info->miiregs;
140 priv->phyaddr = tsec_info->phyaddr;
141 priv->flags = tsec_info->flags;
143 sprintf(dev->name, tsec_info->devname);
146 dev->init = tsec_init;
147 dev->halt = tsec_halt;
148 dev->send = tsec_send;
149 dev->recv = tsec_recv;
150 #ifdef CONFIG_MCAST_TFTP
151 dev->mcast = tsec_mcast_addr;
154 /* Tell u-boot to get the addr from the env */
155 for (i = 0; i < 6; i++)
156 dev->enetaddr[i] = 0;
161 priv->regs->maccfg1 |= MACCFG1_SOFT_RESET;
162 udelay(2); /* Soft Reset must be asserted for 3 TX clocks */
163 priv->regs->maccfg1 &= ~(MACCFG1_SOFT_RESET);
165 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \
166 && !defined(BITBANGMII)
167 miiphy_register(dev->name, tsec_miiphy_read, tsec_miiphy_write);
170 /* Try to initialize PHY here, and return */
171 return init_phy(dev);
174 /* Initializes data structures and registers for the controller,
175 * and brings the interface up. Returns the link status, meaning
176 * that it returns success if the link is up, failure otherwise.
177 * This allows u-boot to find the first active controller.
179 int tsec_init(struct eth_device *dev, bd_t * bd)
182 char tmpbuf[MAC_ADDR_LEN];
184 struct tsec_private *priv = (struct tsec_private *)dev->priv;
185 volatile tsec_t *regs = priv->regs;
187 /* Make sure the controller is stopped */
190 /* Init MACCFG2. Defaults to GMII */
191 regs->maccfg2 = MACCFG2_INIT_SETTINGS;
194 regs->ecntrl = ECNTRL_INIT_SETTINGS;
196 /* Copy the station address into the address registers.
197 * Backwards, because little endian MACS are dumb */
198 for (i = 0; i < MAC_ADDR_LEN; i++) {
199 tmpbuf[MAC_ADDR_LEN - 1 - i] = dev->enetaddr[i];
201 tempval = (tmpbuf[0] << 24) | (tmpbuf[1] << 16) | (tmpbuf[2] << 8) |
204 regs->macstnaddr1 = tempval;
206 tempval = *((uint *) (tmpbuf + 4));
208 regs->macstnaddr2 = tempval;
210 /* reset the indices to zero */
214 /* Clear out (for the most part) the other registers */
215 init_registers(regs);
217 /* Ready the device for tx/rx */
220 /* If there's no link, fail */
221 return (priv->link ? 0 : -1);
224 /* Writes the given phy's reg with value, using the specified MDIO regs */
225 static void tsec_local_mdio_write(volatile tsec_t *phyregs, uint addr,
226 uint reg, uint value)
228 int timeout = 1000000;
230 phyregs->miimadd = (addr << 8) | reg;
231 phyregs->miimcon = value;
235 while ((phyregs->miimind & MIIMIND_BUSY) && timeout--) ;
239 /* Provide the default behavior of writing the PHY of this ethernet device */
240 #define write_phy_reg(priv, regnum, value) tsec_local_mdio_write(priv->phyregs,priv->phyaddr,regnum,value)
242 /* Reads register regnum on the device's PHY through the
243 * specified registers. It lowers and raises the read
244 * command, and waits for the data to become valid (miimind
245 * notvalid bit cleared), and the bus to cease activity (miimind
246 * busy bit cleared), and then returns the value
248 uint tsec_local_mdio_read(volatile tsec_t *phyregs, uint phyid, uint regnum)
252 /* Put the address of the phy, and the register
253 * number into MIIMADD */
254 phyregs->miimadd = (phyid << 8) | regnum;
256 /* Clear the command register, and wait */
257 phyregs->miimcom = 0;
260 /* Initiate a read command, and wait */
261 phyregs->miimcom = MIIM_READ_COMMAND;
264 /* Wait for the the indication that the read is done */
265 while ((phyregs->miimind & (MIIMIND_NOTVALID | MIIMIND_BUSY))) ;
267 /* Grab the value read from the PHY */
268 value = phyregs->miimstat;
273 /* #define to provide old read_phy_reg functionality without duplicating code */
274 #define read_phy_reg(priv,regnum) tsec_local_mdio_read(priv->phyregs,priv->phyaddr,regnum)
276 #define TBIANA_SETTINGS ( \
277 TBIANA_ASYMMETRIC_PAUSE \
278 | TBIANA_SYMMETRIC_PAUSE \
279 | TBIANA_FULL_DUPLEX \
282 #define TBICR_SETTINGS ( \
284 | TBICR_ANEG_ENABLE \
285 | TBICR_FULL_DUPLEX \
288 /* Configure the TBI for SGMII operation */
289 static void tsec_configure_serdes(struct tsec_private *priv)
291 /* Access TBI PHY registers at given TSEC register offset as opposed to the
292 * register offset used for external PHY accesses */
293 tsec_local_mdio_write(priv->regs, priv->regs->tbipa, TBI_ANA,
295 tsec_local_mdio_write(priv->regs, priv->regs->tbipa, TBI_TBICON,
297 tsec_local_mdio_write(priv->regs, priv->regs->tbipa, TBI_CR,
301 /* Discover which PHY is attached to the device, and configure it
302 * properly. If the PHY is not recognized, then return 0
303 * (failure). Otherwise, return 1
305 static int init_phy(struct eth_device *dev)
307 struct tsec_private *priv = (struct tsec_private *)dev->priv;
308 struct phy_info *curphy;
309 volatile tsec_t *phyregs = priv->phyregs;
310 volatile tsec_t *regs = priv->regs;
312 /* Assign a Physical address to the TBI */
313 regs->tbipa = CONFIG_SYS_TBIPA_VALUE;
314 phyregs->tbipa = CONFIG_SYS_TBIPA_VALUE;
317 /* Reset MII (due to new addresses) */
318 priv->phyregs->miimcfg = MIIMCFG_RESET;
320 priv->phyregs->miimcfg = MIIMCFG_INIT_VALUE;
322 while (priv->phyregs->miimind & MIIMIND_BUSY) ;
327 /* Get the cmd structure corresponding to the attached
329 curphy = get_phy_info(dev);
331 if (curphy == NULL) {
332 priv->phyinfo = NULL;
333 printf("%s: No PHY found\n", dev->name);
338 if (regs->ecntrl & ECNTRL_SGMII_MODE)
339 tsec_configure_serdes(priv);
341 priv->phyinfo = curphy;
343 phy_run_commands(priv, priv->phyinfo->config);
349 * Returns which value to write to the control register.
350 * For 10/100, the value is slightly different
352 uint mii_cr_init(uint mii_reg, struct tsec_private * priv)
354 if (priv->flags & TSEC_GIGABIT)
355 return MIIM_CONTROL_INIT;
361 * Wait for auto-negotiation to complete, then determine link
363 uint mii_parse_sr(uint mii_reg, struct tsec_private * priv)
366 * Wait if the link is up, and autonegotiation is in progress
367 * (ie - we're capable and it's not done)
369 mii_reg = read_phy_reg(priv, MIIM_STATUS);
370 if ((mii_reg & PHY_BMSR_AUTN_ABLE) && !(mii_reg & PHY_BMSR_AUTN_COMP)) {
373 puts("Waiting for PHY auto negotiation to complete");
374 while (!(mii_reg & PHY_BMSR_AUTN_COMP)) {
378 if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
379 puts(" TIMEOUT !\n");
385 puts("user interrupt!\n");
390 if ((i++ % 1000) == 0) {
393 udelay(1000); /* 1 ms */
394 mii_reg = read_phy_reg(priv, MIIM_STATUS);
398 /* Link status bit is latched low, read it again */
399 mii_reg = read_phy_reg(priv, MIIM_STATUS);
401 udelay(500000); /* another 500 ms (results in faster booting) */
404 priv->link = mii_reg & MIIM_STATUS_LINK ? 1 : 0;
409 /* Generic function which updates the speed and duplex. If
410 * autonegotiation is enabled, it uses the AND of the link
411 * partner's advertised capabilities and our advertised
412 * capabilities. If autonegotiation is disabled, we use the
413 * appropriate bits in the control register.
415 * Stolen from Linux's mii.c and phy_device.c
417 uint mii_parse_link(uint mii_reg, struct tsec_private *priv)
419 /* We're using autonegotiation */
420 if (mii_reg & PHY_BMSR_AUTN_ABLE) {
424 /* Check for gigabit capability */
425 if (mii_reg & PHY_BMSR_EXT) {
426 /* We want a list of states supported by
427 * both PHYs in the link
429 gblpa = read_phy_reg(priv, PHY_1000BTSR);
430 gblpa &= read_phy_reg(priv, PHY_1000BTCR) << 2;
433 /* Set the baseline so we only have to set them
434 * if they're different
439 /* Check the gigabit fields */
440 if (gblpa & (PHY_1000BTSR_1000FD | PHY_1000BTSR_1000HD)) {
443 if (gblpa & PHY_1000BTSR_1000FD)
450 lpa = read_phy_reg(priv, PHY_ANAR);
451 lpa &= read_phy_reg(priv, PHY_ANLPAR);
453 if (lpa & (PHY_ANLPAR_TXFD | PHY_ANLPAR_TX)) {
456 if (lpa & PHY_ANLPAR_TXFD)
459 } else if (lpa & PHY_ANLPAR_10FD)
462 uint bmcr = read_phy_reg(priv, PHY_BMCR);
467 if (bmcr & PHY_BMCR_DPLX)
470 if (bmcr & PHY_BMCR_1000_MBPS)
472 else if (bmcr & PHY_BMCR_100_MBPS)
480 * "Ethernet@Wirespeed" needs to be enabled to achieve link in certain
481 * circumstances. eg a gigabit TSEC connected to a gigabit switch with
482 * a 4-wire ethernet cable. Both ends advertise gigabit, but can't
483 * link. "Ethernet@Wirespeed" reduces advertised speed until link
486 uint mii_BCM54xx_wirespeed(uint mii_reg, struct tsec_private *priv)
488 return (read_phy_reg(priv, mii_reg) & 0x8FFF) | 0x8010;
492 * Parse the BCM54xx status register for speed and duplex information.
493 * The linux sungem_phy has this information, but in a table format.
495 uint mii_parse_BCM54xx_sr(uint mii_reg, struct tsec_private *priv)
498 switch((mii_reg & MIIM_BCM54xx_AUXSTATUS_LINKMODE_MASK) >> MIIM_BCM54xx_AUXSTATUS_LINKMODE_SHIFT){
501 printf("Enet starting in 10BT/HD\n");
507 printf("Enet starting in 10BT/FD\n");
513 printf("Enet starting in 100BT/HD\n");
519 printf("Enet starting in 100BT/FD\n");
525 printf("Enet starting in 1000BT/HD\n");
531 printf("Enet starting in 1000BT/FD\n");
537 printf("Auto-neg error, defaulting to 10BT/HD\n");
546 /* Parse the 88E1011's status register for speed and duplex
549 uint mii_parse_88E1011_psr(uint mii_reg, struct tsec_private * priv)
553 mii_reg = read_phy_reg(priv, MIIM_88E1011_PHY_STATUS);
555 if ((mii_reg & MIIM_88E1011_PHYSTAT_LINK) &&
556 !(mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE)) {
559 puts("Waiting for PHY realtime link");
560 while (!(mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE)) {
561 /* Timeout reached ? */
562 if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
563 puts(" TIMEOUT !\n");
568 if ((i++ % 1000) == 0) {
571 udelay(1000); /* 1 ms */
572 mii_reg = read_phy_reg(priv, MIIM_88E1011_PHY_STATUS);
575 udelay(500000); /* another 500 ms (results in faster booting) */
577 if (mii_reg & MIIM_88E1011_PHYSTAT_LINK)
583 if (mii_reg & MIIM_88E1011_PHYSTAT_DUPLEX)
588 speed = (mii_reg & MIIM_88E1011_PHYSTAT_SPEED);
591 case MIIM_88E1011_PHYSTAT_GBIT:
594 case MIIM_88E1011_PHYSTAT_100:
604 /* Parse the RTL8211B's status register for speed and duplex
607 uint mii_parse_RTL8211B_sr(uint mii_reg, struct tsec_private * priv)
611 mii_reg = read_phy_reg(priv, MIIM_RTL8211B_PHY_STATUS);
612 if (!(mii_reg & MIIM_RTL8211B_PHYSTAT_SPDDONE)) {
615 /* in case of timeout ->link is cleared */
617 puts("Waiting for PHY realtime link");
618 while (!(mii_reg & MIIM_RTL8211B_PHYSTAT_SPDDONE)) {
619 /* Timeout reached ? */
620 if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
621 puts(" TIMEOUT !\n");
626 if ((i++ % 1000) == 0) {
629 udelay(1000); /* 1 ms */
630 mii_reg = read_phy_reg(priv, MIIM_RTL8211B_PHY_STATUS);
633 udelay(500000); /* another 500 ms (results in faster booting) */
635 if (mii_reg & MIIM_RTL8211B_PHYSTAT_LINK)
641 if (mii_reg & MIIM_RTL8211B_PHYSTAT_DUPLEX)
646 speed = (mii_reg & MIIM_RTL8211B_PHYSTAT_SPEED);
649 case MIIM_RTL8211B_PHYSTAT_GBIT:
652 case MIIM_RTL8211B_PHYSTAT_100:
662 /* Parse the cis8201's status register for speed and duplex
665 uint mii_parse_cis8201(uint mii_reg, struct tsec_private * priv)
669 if (mii_reg & MIIM_CIS8201_AUXCONSTAT_DUPLEX)
674 speed = mii_reg & MIIM_CIS8201_AUXCONSTAT_SPEED;
676 case MIIM_CIS8201_AUXCONSTAT_GBIT:
679 case MIIM_CIS8201_AUXCONSTAT_100:
690 /* Parse the vsc8244's status register for speed and duplex
693 uint mii_parse_vsc8244(uint mii_reg, struct tsec_private * priv)
697 if (mii_reg & MIIM_VSC8244_AUXCONSTAT_DUPLEX)
702 speed = mii_reg & MIIM_VSC8244_AUXCONSTAT_SPEED;
704 case MIIM_VSC8244_AUXCONSTAT_GBIT:
707 case MIIM_VSC8244_AUXCONSTAT_100:
718 /* Parse the DM9161's status register for speed and duplex
721 uint mii_parse_dm9161_scsr(uint mii_reg, struct tsec_private * priv)
723 if (mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_100H))
728 if (mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_10F))
737 * Hack to write all 4 PHYs with the LED values
739 uint mii_cis8204_fixled(uint mii_reg, struct tsec_private * priv)
742 volatile tsec_t *regbase = priv->phyregs;
743 int timeout = 1000000;
745 for (phyid = 0; phyid < 4; phyid++) {
746 regbase->miimadd = (phyid << 8) | mii_reg;
747 regbase->miimcon = MIIM_CIS8204_SLEDCON_INIT;
751 while ((regbase->miimind & MIIMIND_BUSY) && timeout--) ;
754 return MIIM_CIS8204_SLEDCON_INIT;
757 uint mii_cis8204_setmode(uint mii_reg, struct tsec_private * priv)
759 if (priv->flags & TSEC_REDUCED)
760 return MIIM_CIS8204_EPHYCON_INIT | MIIM_CIS8204_EPHYCON_RGMII;
762 return MIIM_CIS8204_EPHYCON_INIT;
765 uint mii_m88e1111s_setmode(uint mii_reg, struct tsec_private *priv)
767 uint mii_data = read_phy_reg(priv, mii_reg);
769 if (priv->flags & TSEC_REDUCED)
770 mii_data = (mii_data & 0xfff0) | 0x000b;
774 /* Initialized required registers to appropriate values, zeroing
775 * those we don't care about (unless zero is bad, in which case,
776 * choose a more appropriate value)
778 static void init_registers(volatile tsec_t * regs)
781 regs->ievent = IEVENT_INIT_CLEAR;
783 regs->imask = IMASK_INIT_CLEAR;
785 regs->hash.iaddr0 = 0;
786 regs->hash.iaddr1 = 0;
787 regs->hash.iaddr2 = 0;
788 regs->hash.iaddr3 = 0;
789 regs->hash.iaddr4 = 0;
790 regs->hash.iaddr5 = 0;
791 regs->hash.iaddr6 = 0;
792 regs->hash.iaddr7 = 0;
794 regs->hash.gaddr0 = 0;
795 regs->hash.gaddr1 = 0;
796 regs->hash.gaddr2 = 0;
797 regs->hash.gaddr3 = 0;
798 regs->hash.gaddr4 = 0;
799 regs->hash.gaddr5 = 0;
800 regs->hash.gaddr6 = 0;
801 regs->hash.gaddr7 = 0;
803 regs->rctrl = 0x00000000;
805 /* Init RMON mib registers */
806 memset((void *)&(regs->rmon), 0, sizeof(rmon_mib_t));
808 regs->rmon.cam1 = 0xffffffff;
809 regs->rmon.cam2 = 0xffffffff;
811 regs->mrblr = MRBLR_INIT_SETTINGS;
813 regs->minflr = MINFLR_INIT_SETTINGS;
815 regs->attr = ATTR_INIT_SETTINGS;
816 regs->attreli = ATTRELI_INIT_SETTINGS;
820 /* Configure maccfg2 based on negotiated speed and duplex
821 * reported by PHY handling code
823 static void adjust_link(struct eth_device *dev)
825 struct tsec_private *priv = (struct tsec_private *)dev->priv;
826 volatile tsec_t *regs = priv->regs;
829 if (priv->duplexity != 0)
830 regs->maccfg2 |= MACCFG2_FULL_DUPLEX;
832 regs->maccfg2 &= ~(MACCFG2_FULL_DUPLEX);
834 switch (priv->speed) {
836 regs->maccfg2 = ((regs->maccfg2 & ~(MACCFG2_IF))
841 regs->maccfg2 = ((regs->maccfg2 & ~(MACCFG2_IF))
844 /* Set R100 bit in all modes although
845 * it is only used in RGMII mode
847 if (priv->speed == 100)
848 regs->ecntrl |= ECNTRL_R100;
850 regs->ecntrl &= ~(ECNTRL_R100);
853 printf("%s: Speed was bad\n", dev->name);
857 printf("Speed: %d, %s duplex\n", priv->speed,
858 (priv->duplexity) ? "full" : "half");
861 printf("%s: No link.\n", dev->name);
865 /* Set up the buffers and their descriptors, and bring up the
868 static void startup_tsec(struct eth_device *dev)
871 struct tsec_private *priv = (struct tsec_private *)dev->priv;
872 volatile tsec_t *regs = priv->regs;
874 /* Point to the buffer descriptors */
875 regs->tbase = (unsigned int)(&rtx.txbd[txIdx]);
876 regs->rbase = (unsigned int)(&rtx.rxbd[rxIdx]);
878 /* Initialize the Rx Buffer descriptors */
879 for (i = 0; i < PKTBUFSRX; i++) {
880 rtx.rxbd[i].status = RXBD_EMPTY;
881 rtx.rxbd[i].length = 0;
882 rtx.rxbd[i].bufPtr = (uint) NetRxPackets[i];
884 rtx.rxbd[PKTBUFSRX - 1].status |= RXBD_WRAP;
886 /* Initialize the TX Buffer Descriptors */
887 for (i = 0; i < TX_BUF_CNT; i++) {
888 rtx.txbd[i].status = 0;
889 rtx.txbd[i].length = 0;
890 rtx.txbd[i].bufPtr = 0;
892 rtx.txbd[TX_BUF_CNT - 1].status |= TXBD_WRAP;
894 /* Start up the PHY */
896 phy_run_commands(priv, priv->phyinfo->startup);
900 /* Enable Transmit and Receive */
901 regs->maccfg1 |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
903 /* Tell the DMA it is clear to go */
904 regs->dmactrl |= DMACTRL_INIT_SETTINGS;
905 regs->tstat = TSTAT_CLEAR_THALT;
906 regs->rstat = RSTAT_CLEAR_RHALT;
907 regs->dmactrl &= ~(DMACTRL_GRS | DMACTRL_GTS);
910 /* This returns the status bits of the device. The return value
911 * is never checked, and this is what the 8260 driver did, so we
912 * do the same. Presumably, this would be zero if there were no
915 static int tsec_send(struct eth_device *dev, volatile void *packet, int length)
919 struct tsec_private *priv = (struct tsec_private *)dev->priv;
920 volatile tsec_t *regs = priv->regs;
922 /* Find an empty buffer descriptor */
923 for (i = 0; rtx.txbd[txIdx].status & TXBD_READY; i++) {
924 if (i >= TOUT_LOOP) {
925 debug("%s: tsec: tx buffers full\n", dev->name);
930 rtx.txbd[txIdx].bufPtr = (uint) packet;
931 rtx.txbd[txIdx].length = length;
932 rtx.txbd[txIdx].status |=
933 (TXBD_READY | TXBD_LAST | TXBD_CRC | TXBD_INTERRUPT);
935 /* Tell the DMA to go */
936 regs->tstat = TSTAT_CLEAR_THALT;
938 /* Wait for buffer to be transmitted */
939 for (i = 0; rtx.txbd[txIdx].status & TXBD_READY; i++) {
940 if (i >= TOUT_LOOP) {
941 debug("%s: tsec: tx error\n", dev->name);
946 txIdx = (txIdx + 1) % TX_BUF_CNT;
947 result = rtx.txbd[txIdx].status & TXBD_STATS;
952 static int tsec_recv(struct eth_device *dev)
955 struct tsec_private *priv = (struct tsec_private *)dev->priv;
956 volatile tsec_t *regs = priv->regs;
958 while (!(rtx.rxbd[rxIdx].status & RXBD_EMPTY)) {
960 length = rtx.rxbd[rxIdx].length;
962 /* Send the packet up if there were no errors */
963 if (!(rtx.rxbd[rxIdx].status & RXBD_STATS)) {
964 NetReceive(NetRxPackets[rxIdx], length - 4);
966 printf("Got error %x\n",
967 (rtx.rxbd[rxIdx].status & RXBD_STATS));
970 rtx.rxbd[rxIdx].length = 0;
972 /* Set the wrap bit if this is the last element in the list */
973 rtx.rxbd[rxIdx].status =
974 RXBD_EMPTY | (((rxIdx + 1) == PKTBUFSRX) ? RXBD_WRAP : 0);
976 rxIdx = (rxIdx + 1) % PKTBUFSRX;
979 if (regs->ievent & IEVENT_BSY) {
980 regs->ievent = IEVENT_BSY;
981 regs->rstat = RSTAT_CLEAR_RHALT;
988 /* Stop the interface */
989 static void tsec_halt(struct eth_device *dev)
991 struct tsec_private *priv = (struct tsec_private *)dev->priv;
992 volatile tsec_t *regs = priv->regs;
994 regs->dmactrl &= ~(DMACTRL_GRS | DMACTRL_GTS);
995 regs->dmactrl |= (DMACTRL_GRS | DMACTRL_GTS);
997 while (!(regs->ievent & (IEVENT_GRSC | IEVENT_GTSC))) ;
999 regs->maccfg1 &= ~(MACCFG1_TX_EN | MACCFG1_RX_EN);
1001 /* Shut down the PHY, as needed */
1003 phy_run_commands(priv, priv->phyinfo->shutdown);
1006 struct phy_info phy_info_M88E1149S = {
1010 (struct phy_cmd[]){ /* config */
1011 /* Reset and configure the PHY */
1012 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1014 {0x1e, 0x200c, NULL},
1017 {0x1e, 0x100, NULL},
1018 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
1019 {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
1020 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1021 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1024 (struct phy_cmd[]){ /* startup */
1025 /* Status is read once to clear old link state */
1026 {MIIM_STATUS, miim_read, NULL},
1027 /* Auto-negotiate */
1028 {MIIM_STATUS, miim_read, &mii_parse_sr},
1029 /* Read the status */
1030 {MIIM_88E1011_PHY_STATUS, miim_read,
1031 &mii_parse_88E1011_psr},
1034 (struct phy_cmd[]){ /* shutdown */
1039 /* The 5411 id is 0x206070, the 5421 is 0x2060e0 */
1040 struct phy_info phy_info_BCM5461S = {
1041 0x02060c1, /* 5461 ID */
1042 "Broadcom BCM5461S",
1043 0, /* not clear to me what minor revisions we can shift away */
1044 (struct phy_cmd[]) { /* config */
1045 /* Reset and configure the PHY */
1046 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1047 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
1048 {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
1049 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1050 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1053 (struct phy_cmd[]) { /* startup */
1054 /* Status is read once to clear old link state */
1055 {MIIM_STATUS, miim_read, NULL},
1056 /* Auto-negotiate */
1057 {MIIM_STATUS, miim_read, &mii_parse_sr},
1058 /* Read the status */
1059 {MIIM_BCM54xx_AUXSTATUS, miim_read, &mii_parse_BCM54xx_sr},
1062 (struct phy_cmd[]) { /* shutdown */
1067 struct phy_info phy_info_BCM5464S = {
1068 0x02060b1, /* 5464 ID */
1069 "Broadcom BCM5464S",
1070 0, /* not clear to me what minor revisions we can shift away */
1071 (struct phy_cmd[]) { /* config */
1072 /* Reset and configure the PHY */
1073 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1074 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
1075 {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
1076 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1077 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1080 (struct phy_cmd[]) { /* startup */
1081 /* Status is read once to clear old link state */
1082 {MIIM_STATUS, miim_read, NULL},
1083 /* Auto-negotiate */
1084 {MIIM_STATUS, miim_read, &mii_parse_sr},
1085 /* Read the status */
1086 {MIIM_BCM54xx_AUXSTATUS, miim_read, &mii_parse_BCM54xx_sr},
1089 (struct phy_cmd[]) { /* shutdown */
1094 struct phy_info phy_info_BCM5482S = {
1096 "Broadcom BCM5482S",
1098 (struct phy_cmd[]) { /* config */
1099 /* Reset and configure the PHY */
1100 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1101 /* Setup read from auxilary control shadow register 7 */
1102 {MIIM_BCM54xx_AUXCNTL, MIIM_BCM54xx_AUXCNTL_ENCODE(7), NULL},
1103 /* Read Misc Control register and or in Ethernet@Wirespeed */
1104 {MIIM_BCM54xx_AUXCNTL, 0, &mii_BCM54xx_wirespeed},
1105 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1108 (struct phy_cmd[]) { /* startup */
1109 /* Status is read once to clear old link state */
1110 {MIIM_STATUS, miim_read, NULL},
1111 /* Auto-negotiate */
1112 {MIIM_STATUS, miim_read, &mii_parse_sr},
1113 /* Read the status */
1114 {MIIM_BCM54xx_AUXSTATUS, miim_read, &mii_parse_BCM54xx_sr},
1117 (struct phy_cmd[]) { /* shutdown */
1122 struct phy_info phy_info_M88E1011S = {
1126 (struct phy_cmd[]){ /* config */
1127 /* Reset and configure the PHY */
1128 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1130 {0x1e, 0x200c, NULL},
1133 {0x1e, 0x100, NULL},
1134 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
1135 {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
1136 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1137 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1140 (struct phy_cmd[]){ /* startup */
1141 /* Status is read once to clear old link state */
1142 {MIIM_STATUS, miim_read, NULL},
1143 /* Auto-negotiate */
1144 {MIIM_STATUS, miim_read, &mii_parse_sr},
1145 /* Read the status */
1146 {MIIM_88E1011_PHY_STATUS, miim_read,
1147 &mii_parse_88E1011_psr},
1150 (struct phy_cmd[]){ /* shutdown */
1155 struct phy_info phy_info_M88E1111S = {
1159 (struct phy_cmd[]){ /* config */
1160 /* Reset and configure the PHY */
1161 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1162 {0x1b, 0x848f, &mii_m88e1111s_setmode},
1163 {0x14, 0x0cd2, NULL}, /* Delay RGMII TX and RX */
1164 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
1165 {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
1166 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1167 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1170 (struct phy_cmd[]){ /* startup */
1171 /* Status is read once to clear old link state */
1172 {MIIM_STATUS, miim_read, NULL},
1173 /* Auto-negotiate */
1174 {MIIM_STATUS, miim_read, &mii_parse_sr},
1175 /* Read the status */
1176 {MIIM_88E1011_PHY_STATUS, miim_read,
1177 &mii_parse_88E1011_psr},
1180 (struct phy_cmd[]){ /* shutdown */
1185 struct phy_info phy_info_M88E1118 = {
1189 (struct phy_cmd[]){ /* config */
1190 /* Reset and configure the PHY */
1191 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1192 {0x16, 0x0002, NULL}, /* Change Page Number */
1193 {0x15, 0x1070, NULL}, /* Delay RGMII TX and RX */
1194 {0x16, 0x0003, NULL}, /* Change Page Number */
1195 {0x10, 0x021e, NULL}, /* Adjust LED control */
1196 {0x16, 0x0000, NULL}, /* Change Page Number */
1197 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
1198 {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
1199 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1200 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1203 (struct phy_cmd[]){ /* startup */
1204 {0x16, 0x0000, NULL}, /* Change Page Number */
1205 /* Status is read once to clear old link state */
1206 {MIIM_STATUS, miim_read, NULL},
1207 /* Auto-negotiate */
1208 {MIIM_STATUS, miim_read, &mii_parse_sr},
1209 /* Read the status */
1210 {MIIM_88E1011_PHY_STATUS, miim_read,
1211 &mii_parse_88E1011_psr},
1214 (struct phy_cmd[]){ /* shutdown */
1220 * Since to access LED register we need do switch the page, we
1221 * do LED configuring in the miim_read-like function as follows
1223 uint mii_88E1121_set_led (uint mii_reg, struct tsec_private *priv)
1227 /* Switch the page to access the led register */
1228 pg = read_phy_reg(priv, MIIM_88E1121_PHY_PAGE);
1229 write_phy_reg(priv, MIIM_88E1121_PHY_PAGE, MIIM_88E1121_PHY_LED_PAGE);
1231 /* Configure leds */
1232 write_phy_reg(priv, MIIM_88E1121_PHY_LED_CTRL,
1233 MIIM_88E1121_PHY_LED_DEF);
1235 /* Restore the page pointer */
1236 write_phy_reg(priv, MIIM_88E1121_PHY_PAGE, pg);
1240 struct phy_info phy_info_M88E1121R = {
1244 (struct phy_cmd[]){ /* config */
1245 /* Reset and configure the PHY */
1246 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1247 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
1248 {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
1249 /* Configure leds */
1250 {MIIM_88E1121_PHY_LED_CTRL, miim_read,
1251 &mii_88E1121_set_led},
1252 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1253 /* Disable IRQs and de-assert interrupt */
1254 {MIIM_88E1121_PHY_IRQ_EN, 0, NULL},
1255 {MIIM_88E1121_PHY_IRQ_STATUS, miim_read, NULL},
1258 (struct phy_cmd[]){ /* startup */
1259 /* Status is read once to clear old link state */
1260 {MIIM_STATUS, miim_read, NULL},
1261 {MIIM_STATUS, miim_read, &mii_parse_sr},
1262 {MIIM_STATUS, miim_read, &mii_parse_link},
1265 (struct phy_cmd[]){ /* shutdown */
1270 static unsigned int m88e1145_setmode(uint mii_reg, struct tsec_private *priv)
1272 uint mii_data = read_phy_reg(priv, mii_reg);
1274 /* Setting MIIM_88E1145_PHY_EXT_CR */
1275 if (priv->flags & TSEC_REDUCED)
1277 MIIM_M88E1145_RGMII_RX_DELAY | MIIM_M88E1145_RGMII_TX_DELAY;
1282 static struct phy_info phy_info_M88E1145 = {
1286 (struct phy_cmd[]){ /* config */
1288 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1296 /* Configure the PHY */
1297 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
1298 {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
1299 {MIIM_88E1011_PHY_SCR, MIIM_88E1011_PHY_MDI_X_AUTO,
1301 {MIIM_88E1145_PHY_EXT_CR, 0, &m88e1145_setmode},
1302 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1303 {MIIM_CONTROL, MIIM_CONTROL_INIT, NULL},
1306 (struct phy_cmd[]){ /* startup */
1307 /* Status is read once to clear old link state */
1308 {MIIM_STATUS, miim_read, NULL},
1309 /* Auto-negotiate */
1310 {MIIM_STATUS, miim_read, &mii_parse_sr},
1311 {MIIM_88E1111_PHY_LED_CONTROL,
1312 MIIM_88E1111_PHY_LED_DIRECT, NULL},
1313 /* Read the Status */
1314 {MIIM_88E1011_PHY_STATUS, miim_read,
1315 &mii_parse_88E1011_psr},
1318 (struct phy_cmd[]){ /* shutdown */
1323 struct phy_info phy_info_cis8204 = {
1327 (struct phy_cmd[]){ /* config */
1328 /* Override PHY config settings */
1329 {MIIM_CIS8201_AUX_CONSTAT,
1330 MIIM_CIS8201_AUXCONSTAT_INIT, NULL},
1331 /* Configure some basic stuff */
1332 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1333 {MIIM_CIS8204_SLED_CON, MIIM_CIS8204_SLEDCON_INIT,
1334 &mii_cis8204_fixled},
1335 {MIIM_CIS8204_EPHY_CON, MIIM_CIS8204_EPHYCON_INIT,
1336 &mii_cis8204_setmode},
1339 (struct phy_cmd[]){ /* startup */
1340 /* Read the Status (2x to make sure link is right) */
1341 {MIIM_STATUS, miim_read, NULL},
1342 /* Auto-negotiate */
1343 {MIIM_STATUS, miim_read, &mii_parse_sr},
1344 /* Read the status */
1345 {MIIM_CIS8201_AUX_CONSTAT, miim_read,
1346 &mii_parse_cis8201},
1349 (struct phy_cmd[]){ /* shutdown */
1355 struct phy_info phy_info_cis8201 = {
1359 (struct phy_cmd[]){ /* config */
1360 /* Override PHY config settings */
1361 {MIIM_CIS8201_AUX_CONSTAT,
1362 MIIM_CIS8201_AUXCONSTAT_INIT, NULL},
1363 /* Set up the interface mode */
1364 {MIIM_CIS8201_EXT_CON1, MIIM_CIS8201_EXTCON1_INIT,
1366 /* Configure some basic stuff */
1367 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1370 (struct phy_cmd[]){ /* startup */
1371 /* Read the Status (2x to make sure link is right) */
1372 {MIIM_STATUS, miim_read, NULL},
1373 /* Auto-negotiate */
1374 {MIIM_STATUS, miim_read, &mii_parse_sr},
1375 /* Read the status */
1376 {MIIM_CIS8201_AUX_CONSTAT, miim_read,
1377 &mii_parse_cis8201},
1380 (struct phy_cmd[]){ /* shutdown */
1384 struct phy_info phy_info_VSC8211 = {
1388 (struct phy_cmd[]) { /* config */
1389 /* Override PHY config settings */
1390 {MIIM_CIS8201_AUX_CONSTAT,
1391 MIIM_CIS8201_AUXCONSTAT_INIT, NULL},
1392 /* Set up the interface mode */
1393 {MIIM_CIS8201_EXT_CON1,
1394 MIIM_CIS8201_EXTCON1_INIT, NULL},
1395 /* Configure some basic stuff */
1396 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1399 (struct phy_cmd[]) { /* startup */
1400 /* Read the Status (2x to make sure link is right) */
1401 {MIIM_STATUS, miim_read, NULL},
1402 /* Auto-negotiate */
1403 {MIIM_STATUS, miim_read, &mii_parse_sr},
1404 /* Read the status */
1405 {MIIM_CIS8201_AUX_CONSTAT, miim_read,
1406 &mii_parse_cis8201},
1409 (struct phy_cmd[]) { /* shutdown */
1413 struct phy_info phy_info_VSC8244 = {
1417 (struct phy_cmd[]){ /* config */
1418 /* Override PHY config settings */
1419 /* Configure some basic stuff */
1420 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1423 (struct phy_cmd[]){ /* startup */
1424 /* Read the Status (2x to make sure link is right) */
1425 {MIIM_STATUS, miim_read, NULL},
1426 /* Auto-negotiate */
1427 {MIIM_STATUS, miim_read, &mii_parse_sr},
1428 /* Read the status */
1429 {MIIM_VSC8244_AUX_CONSTAT, miim_read,
1430 &mii_parse_vsc8244},
1433 (struct phy_cmd[]){ /* shutdown */
1438 struct phy_info phy_info_VSC8641 = {
1442 (struct phy_cmd[]){ /* config */
1443 /* Configure some basic stuff */
1444 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1447 (struct phy_cmd[]){ /* startup */
1448 /* Read the Status (2x to make sure link is right) */
1449 {MIIM_STATUS, miim_read, NULL},
1450 /* Auto-negotiate */
1451 {MIIM_STATUS, miim_read, &mii_parse_sr},
1452 /* Read the status */
1453 {MIIM_VSC8244_AUX_CONSTAT, miim_read,
1454 &mii_parse_vsc8244},
1457 (struct phy_cmd[]){ /* shutdown */
1462 struct phy_info phy_info_VSC8221 = {
1466 (struct phy_cmd[]){ /* config */
1467 /* Configure some basic stuff */
1468 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1471 (struct phy_cmd[]){ /* startup */
1472 /* Read the Status (2x to make sure link is right) */
1473 {MIIM_STATUS, miim_read, NULL},
1474 /* Auto-negotiate */
1475 {MIIM_STATUS, miim_read, &mii_parse_sr},
1476 /* Read the status */
1477 {MIIM_VSC8244_AUX_CONSTAT, miim_read,
1478 &mii_parse_vsc8244},
1481 (struct phy_cmd[]){ /* shutdown */
1486 struct phy_info phy_info_VSC8601 = {
1490 (struct phy_cmd[]){ /* config */
1491 /* Override PHY config settings */
1492 /* Configure some basic stuff */
1493 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1494 #ifdef CONFIG_SYS_VSC8601_SKEWFIX
1495 {MIIM_VSC8601_EPHY_CON,MIIM_VSC8601_EPHY_CON_INIT_SKEW,NULL},
1496 #if defined(CONFIG_SYS_VSC8601_SKEW_TX) && defined(CONFIG_SYS_VSC8601_SKEW_RX)
1497 {MIIM_EXT_PAGE_ACCESS,1,NULL},
1498 #define VSC8101_SKEW (CONFIG_SYS_VSC8601_SKEW_TX<<14)|(CONFIG_SYS_VSC8601_SKEW_RX<<12)
1499 {MIIM_VSC8601_SKEW_CTRL,VSC8101_SKEW,NULL},
1500 {MIIM_EXT_PAGE_ACCESS,0,NULL},
1503 {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
1504 {MIIM_CONTROL, MIIM_CONTROL_RESTART, &mii_cr_init},
1507 (struct phy_cmd[]){ /* startup */
1508 /* Read the Status (2x to make sure link is right) */
1509 {MIIM_STATUS, miim_read, NULL},
1510 /* Auto-negotiate */
1511 {MIIM_STATUS, miim_read, &mii_parse_sr},
1512 /* Read the status */
1513 {MIIM_VSC8244_AUX_CONSTAT, miim_read,
1514 &mii_parse_vsc8244},
1517 (struct phy_cmd[]){ /* shutdown */
1523 struct phy_info phy_info_dm9161 = {
1527 (struct phy_cmd[]){ /* config */
1528 {MIIM_CONTROL, MIIM_DM9161_CR_STOP, NULL},
1529 /* Do not bypass the scrambler/descrambler */
1530 {MIIM_DM9161_SCR, MIIM_DM9161_SCR_INIT, NULL},
1531 /* Clear 10BTCSR to default */
1532 {MIIM_DM9161_10BTCSR, MIIM_DM9161_10BTCSR_INIT,
1534 /* Configure some basic stuff */
1535 {MIIM_CONTROL, MIIM_CR_INIT, NULL},
1536 /* Restart Auto Negotiation */
1537 {MIIM_CONTROL, MIIM_DM9161_CR_RSTAN, NULL},
1540 (struct phy_cmd[]){ /* startup */
1541 /* Status is read once to clear old link state */
1542 {MIIM_STATUS, miim_read, NULL},
1543 /* Auto-negotiate */
1544 {MIIM_STATUS, miim_read, &mii_parse_sr},
1545 /* Read the status */
1546 {MIIM_DM9161_SCSR, miim_read,
1547 &mii_parse_dm9161_scsr},
1550 (struct phy_cmd[]){ /* shutdown */
1554 /* a generic flavor. */
1555 struct phy_info phy_info_generic = {
1557 "Unknown/Generic PHY",
1559 (struct phy_cmd[]) { /* config */
1560 {PHY_BMCR, PHY_BMCR_RESET, NULL},
1561 {PHY_BMCR, PHY_BMCR_AUTON|PHY_BMCR_RST_NEG, NULL},
1564 (struct phy_cmd[]) { /* startup */
1565 {PHY_BMSR, miim_read, NULL},
1566 {PHY_BMSR, miim_read, &mii_parse_sr},
1567 {PHY_BMSR, miim_read, &mii_parse_link},
1570 (struct phy_cmd[]) { /* shutdown */
1576 uint mii_parse_lxt971_sr2(uint mii_reg, struct tsec_private *priv)
1580 speed = mii_reg & MIIM_LXT971_SR2_SPEED_MASK;
1583 case MIIM_LXT971_SR2_10HDX:
1585 priv->duplexity = 0;
1587 case MIIM_LXT971_SR2_10FDX:
1589 priv->duplexity = 1;
1591 case MIIM_LXT971_SR2_100HDX:
1593 priv->duplexity = 0;
1597 priv->duplexity = 1;
1601 priv->duplexity = 0;
1607 static struct phy_info phy_info_lxt971 = {
1611 (struct phy_cmd[]){ /* config */
1612 {MIIM_CR, MIIM_CR_INIT, mii_cr_init}, /* autonegotiate */
1615 (struct phy_cmd[]){ /* startup - enable interrupts */
1616 /* { 0x12, 0x00f2, NULL }, */
1617 {MIIM_STATUS, miim_read, NULL},
1618 {MIIM_STATUS, miim_read, &mii_parse_sr},
1619 {MIIM_LXT971_SR2, miim_read, &mii_parse_lxt971_sr2},
1622 (struct phy_cmd[]){ /* shutdown - disable interrupts */
1627 /* Parse the DP83865's link and auto-neg status register for speed and duplex
1630 uint mii_parse_dp83865_lanr(uint mii_reg, struct tsec_private *priv)
1632 switch (mii_reg & MIIM_DP83865_SPD_MASK) {
1634 case MIIM_DP83865_SPD_1000:
1638 case MIIM_DP83865_SPD_100:
1648 if (mii_reg & MIIM_DP83865_DPX_FULL)
1649 priv->duplexity = 1;
1651 priv->duplexity = 0;
1656 struct phy_info phy_info_dp83865 = {
1660 (struct phy_cmd[]){ /* config */
1661 {MIIM_CONTROL, MIIM_DP83865_CR_INIT, NULL},
1664 (struct phy_cmd[]){ /* startup */
1665 /* Status is read once to clear old link state */
1666 {MIIM_STATUS, miim_read, NULL},
1667 /* Auto-negotiate */
1668 {MIIM_STATUS, miim_read, &mii_parse_sr},
1669 /* Read the link and auto-neg status */
1670 {MIIM_DP83865_LANR, miim_read,
1671 &mii_parse_dp83865_lanr},
1674 (struct phy_cmd[]){ /* shutdown */
1679 struct phy_info phy_info_rtl8211b = {
1683 (struct phy_cmd[]){ /* config */
1684 /* Reset and configure the PHY */
1685 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1686 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
1687 {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
1688 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1689 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1692 (struct phy_cmd[]){ /* startup */
1693 /* Status is read once to clear old link state */
1694 {MIIM_STATUS, miim_read, NULL},
1695 /* Auto-negotiate */
1696 {MIIM_STATUS, miim_read, &mii_parse_sr},
1697 /* Read the status */
1698 {MIIM_RTL8211B_PHY_STATUS, miim_read, &mii_parse_RTL8211B_sr},
1701 (struct phy_cmd[]){ /* shutdown */
1706 struct phy_info *phy_info[] = {
1712 &phy_info_M88E1011S,
1713 &phy_info_M88E1111S,
1715 &phy_info_M88E1121R,
1717 &phy_info_M88E1149S,
1727 &phy_info_generic, /* must be last; has ID 0 and 32 bit mask */
1731 /* Grab the identifier of the device's PHY, and search through
1732 * all of the known PHYs to see if one matches. If so, return
1733 * it, if not, return NULL
1735 struct phy_info *get_phy_info(struct eth_device *dev)
1737 struct tsec_private *priv = (struct tsec_private *)dev->priv;
1738 uint phy_reg, phy_ID;
1740 struct phy_info *theInfo = NULL;
1742 /* Grab the bits from PHYIR1, and put them in the upper half */
1743 phy_reg = read_phy_reg(priv, MIIM_PHYIR1);
1744 phy_ID = (phy_reg & 0xffff) << 16;
1746 /* Grab the bits from PHYIR2, and put them in the lower half */
1747 phy_reg = read_phy_reg(priv, MIIM_PHYIR2);
1748 phy_ID |= (phy_reg & 0xffff);
1750 /* loop through all the known PHY types, and find one that */
1751 /* matches the ID we read from the PHY. */
1752 for (i = 0; phy_info[i]; i++) {
1753 if (phy_info[i]->id == (phy_ID >> phy_info[i]->shift)) {
1754 theInfo = phy_info[i];
1759 if (theInfo == &phy_info_generic) {
1760 printf("%s: No support for PHY id %x; assuming generic\n", dev->name, phy_ID);
1762 debug("%s: PHY is %s (%x)\n", dev->name, theInfo->name, phy_ID);
1768 /* Execute the given series of commands on the given device's
1769 * PHY, running functions as necessary
1771 void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd)
1775 volatile tsec_t *phyregs = priv->phyregs;
1777 phyregs->miimcfg = MIIMCFG_RESET;
1779 phyregs->miimcfg = MIIMCFG_INIT_VALUE;
1781 while (phyregs->miimind & MIIMIND_BUSY) ;
1783 for (i = 0; cmd->mii_reg != miim_end; i++) {
1784 if (cmd->mii_data == miim_read) {
1785 result = read_phy_reg(priv, cmd->mii_reg);
1787 if (cmd->funct != NULL)
1788 (*(cmd->funct)) (result, priv);
1791 if (cmd->funct != NULL)
1792 result = (*(cmd->funct)) (cmd->mii_reg, priv);
1794 result = cmd->mii_data;
1796 write_phy_reg(priv, cmd->mii_reg, result);
1803 /* Relocate the function pointers in the phy cmd lists */
1804 static void relocate_cmds(void)
1806 struct phy_cmd **cmdlistptr;
1807 struct phy_cmd *cmd;
1810 for (i = 0; phy_info[i]; i++) {
1811 /* First thing's first: relocate the pointers to the
1812 * PHY command structures (the structs were done) */
1813 phy_info[i] = (struct phy_info *)((uint) phy_info[i]
1815 phy_info[i]->name += gd->reloc_off;
1816 phy_info[i]->config =
1817 (struct phy_cmd *)((uint) phy_info[i]->config
1819 phy_info[i]->startup =
1820 (struct phy_cmd *)((uint) phy_info[i]->startup
1822 phy_info[i]->shutdown =
1823 (struct phy_cmd *)((uint) phy_info[i]->shutdown
1826 cmdlistptr = &phy_info[i]->config;
1828 for (; cmdlistptr <= &phy_info[i]->shutdown; cmdlistptr++) {
1830 for (cmd = *cmdlistptr;
1831 cmd->mii_reg != miim_end;
1833 /* Only relocate non-NULL pointers */
1835 cmd->funct += gd->reloc_off;
1846 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \
1847 && !defined(BITBANGMII)
1850 * Read a MII PHY register.
1855 static int tsec_miiphy_read(char *devname, unsigned char addr,
1856 unsigned char reg, unsigned short *value)
1859 struct tsec_private *priv = privlist[0];
1862 printf("Can't read PHY at address %d\n", addr);
1866 ret = (unsigned short)tsec_local_mdio_read(priv->phyregs, addr, reg);
1873 * Write a MII PHY register.
1878 static int tsec_miiphy_write(char *devname, unsigned char addr,
1879 unsigned char reg, unsigned short value)
1881 struct tsec_private *priv = privlist[0];
1884 printf("Can't write PHY at address %d\n", addr);
1888 tsec_local_mdio_write(priv->phyregs, addr, reg, value);
1895 #ifdef CONFIG_MCAST_TFTP
1897 /* CREDITS: linux gianfar driver, slightly adjusted... thanx. */
1899 /* Set the appropriate hash bit for the given addr */
1901 /* The algorithm works like so:
1902 * 1) Take the Destination Address (ie the multicast address), and
1903 * do a CRC on it (little endian), and reverse the bits of the
1905 * 2) Use the 8 most significant bits as a hash into a 256-entry
1906 * table. The table is controlled through 8 32-bit registers:
1907 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is
1908 * gaddr7. This means that the 3 most significant bits in the
1909 * hash index which gaddr register to use, and the 5 other bits
1910 * indicate which bit (assuming an IBM numbering scheme, which
1911 * for PowerPC (tm) is usually the case) in the tregister holds
1914 tsec_mcast_addr (struct eth_device *dev, u8 mcast_mac, u8 set)
1916 struct tsec_private *priv = privlist[1];
1917 volatile tsec_t *regs = priv->regs;
1918 volatile u32 *reg_array, value;
1919 u8 result, whichbit, whichreg;
1921 result = (u8)((ether_crc(MAC_ADDR_LEN,mcast_mac) >> 24) & 0xff);
1922 whichbit = result & 0x1f; /* the 5 LSB = which bit to set */
1923 whichreg = result >> 5; /* the 3 MSB = which reg to set it in */
1924 value = (1 << (31-whichbit));
1926 reg_array = &(regs->hash.gaddr0);
1929 reg_array[whichreg] |= value;
1931 reg_array[whichreg] &= ~value;
1935 #endif /* Multicast TFTP ? */