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1 /*
2  *  Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved.
3  *
4  * This program is free software; you can redistribute it and/or
5  * modify it under the terms of the GNU General Public License
6  * version 2 as published by the Free Software Foundation.
7  *
8  */
9
10 #include <linux/signal.h>
11 #include <linux/slab.h>
12 #include <linux/module.h>
13 #include <linux/netdevice.h>
14 #include <linux/etherdevice.h>
15 #include <linux/mii.h>
16 #include <linux/ethtool.h>
17 #include <linux/usb.h>
18 #include <linux/crc32.h>
19 #include <linux/if_vlan.h>
20 #include <linux/uaccess.h>
21 #include <linux/list.h>
22 #include <linux/ip.h>
23 #include <linux/ipv6.h>
24 #include <net/ip6_checksum.h>
25 #include <uapi/linux/mdio.h>
26 #include <linux/mdio.h>
27
28 /* Version Information */
29 #define DRIVER_VERSION "v1.06.1 (2014/10/01)"
30 #define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>"
31 #define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters"
32 #define MODULENAME "r8152"
33
34 #define R8152_PHY_ID            32
35
36 #define PLA_IDR                 0xc000
37 #define PLA_RCR                 0xc010
38 #define PLA_RMS                 0xc016
39 #define PLA_RXFIFO_CTRL0        0xc0a0
40 #define PLA_RXFIFO_CTRL1        0xc0a4
41 #define PLA_RXFIFO_CTRL2        0xc0a8
42 #define PLA_FMC                 0xc0b4
43 #define PLA_CFG_WOL             0xc0b6
44 #define PLA_TEREDO_CFG          0xc0bc
45 #define PLA_MAR                 0xcd00
46 #define PLA_BACKUP              0xd000
47 #define PAL_BDC_CR              0xd1a0
48 #define PLA_TEREDO_TIMER        0xd2cc
49 #define PLA_REALWOW_TIMER       0xd2e8
50 #define PLA_LEDSEL              0xdd90
51 #define PLA_LED_FEATURE         0xdd92
52 #define PLA_PHYAR               0xde00
53 #define PLA_BOOT_CTRL           0xe004
54 #define PLA_GPHY_INTR_IMR       0xe022
55 #define PLA_EEE_CR              0xe040
56 #define PLA_EEEP_CR             0xe080
57 #define PLA_MAC_PWR_CTRL        0xe0c0
58 #define PLA_MAC_PWR_CTRL2       0xe0ca
59 #define PLA_MAC_PWR_CTRL3       0xe0cc
60 #define PLA_MAC_PWR_CTRL4       0xe0ce
61 #define PLA_WDT6_CTRL           0xe428
62 #define PLA_TCR0                0xe610
63 #define PLA_TCR1                0xe612
64 #define PLA_MTPS                0xe615
65 #define PLA_TXFIFO_CTRL         0xe618
66 #define PLA_RSTTALLY            0xe800
67 #define PLA_CR                  0xe813
68 #define PLA_CRWECR              0xe81c
69 #define PLA_CONFIG12            0xe81e  /* CONFIG1, CONFIG2 */
70 #define PLA_CONFIG34            0xe820  /* CONFIG3, CONFIG4 */
71 #define PLA_CONFIG5             0xe822
72 #define PLA_PHY_PWR             0xe84c
73 #define PLA_OOB_CTRL            0xe84f
74 #define PLA_CPCR                0xe854
75 #define PLA_MISC_0              0xe858
76 #define PLA_MISC_1              0xe85a
77 #define PLA_OCP_GPHY_BASE       0xe86c
78 #define PLA_TALLYCNT            0xe890
79 #define PLA_SFF_STS_7           0xe8de
80 #define PLA_PHYSTATUS           0xe908
81 #define PLA_BP_BA               0xfc26
82 #define PLA_BP_0                0xfc28
83 #define PLA_BP_1                0xfc2a
84 #define PLA_BP_2                0xfc2c
85 #define PLA_BP_3                0xfc2e
86 #define PLA_BP_4                0xfc30
87 #define PLA_BP_5                0xfc32
88 #define PLA_BP_6                0xfc34
89 #define PLA_BP_7                0xfc36
90 #define PLA_BP_EN               0xfc38
91
92 #define USB_U2P3_CTRL           0xb460
93 #define USB_DEV_STAT            0xb808
94 #define USB_USB_CTRL            0xd406
95 #define USB_PHY_CTRL            0xd408
96 #define USB_TX_AGG              0xd40a
97 #define USB_RX_BUF_TH           0xd40c
98 #define USB_USB_TIMER           0xd428
99 #define USB_RX_EARLY_AGG        0xd42c
100 #define USB_PM_CTRL_STATUS      0xd432
101 #define USB_TX_DMA              0xd434
102 #define USB_TOLERANCE           0xd490
103 #define USB_LPM_CTRL            0xd41a
104 #define USB_UPS_CTRL            0xd800
105 #define USB_MISC_0              0xd81a
106 #define USB_POWER_CUT           0xd80a
107 #define USB_AFE_CTRL2           0xd824
108 #define USB_WDT11_CTRL          0xe43c
109 #define USB_BP_BA               0xfc26
110 #define USB_BP_0                0xfc28
111 #define USB_BP_1                0xfc2a
112 #define USB_BP_2                0xfc2c
113 #define USB_BP_3                0xfc2e
114 #define USB_BP_4                0xfc30
115 #define USB_BP_5                0xfc32
116 #define USB_BP_6                0xfc34
117 #define USB_BP_7                0xfc36
118 #define USB_BP_EN               0xfc38
119
120 /* OCP Registers */
121 #define OCP_ALDPS_CONFIG        0x2010
122 #define OCP_EEE_CONFIG1         0x2080
123 #define OCP_EEE_CONFIG2         0x2092
124 #define OCP_EEE_CONFIG3         0x2094
125 #define OCP_BASE_MII            0xa400
126 #define OCP_EEE_AR              0xa41a
127 #define OCP_EEE_DATA            0xa41c
128 #define OCP_PHY_STATUS          0xa420
129 #define OCP_POWER_CFG           0xa430
130 #define OCP_EEE_CFG             0xa432
131 #define OCP_SRAM_ADDR           0xa436
132 #define OCP_SRAM_DATA           0xa438
133 #define OCP_DOWN_SPEED          0xa442
134 #define OCP_EEE_ABLE            0xa5c4
135 #define OCP_EEE_ADV             0xa5d0
136 #define OCP_EEE_LPABLE          0xa5d2
137 #define OCP_ADC_CFG             0xbc06
138
139 /* SRAM Register */
140 #define SRAM_LPF_CFG            0x8012
141 #define SRAM_10M_AMP1           0x8080
142 #define SRAM_10M_AMP2           0x8082
143 #define SRAM_IMPEDANCE          0x8084
144
145 /* PLA_RCR */
146 #define RCR_AAP                 0x00000001
147 #define RCR_APM                 0x00000002
148 #define RCR_AM                  0x00000004
149 #define RCR_AB                  0x00000008
150 #define RCR_ACPT_ALL            (RCR_AAP | RCR_APM | RCR_AM | RCR_AB)
151
152 /* PLA_RXFIFO_CTRL0 */
153 #define RXFIFO_THR1_NORMAL      0x00080002
154 #define RXFIFO_THR1_OOB         0x01800003
155
156 /* PLA_RXFIFO_CTRL1 */
157 #define RXFIFO_THR2_FULL        0x00000060
158 #define RXFIFO_THR2_HIGH        0x00000038
159 #define RXFIFO_THR2_OOB         0x0000004a
160 #define RXFIFO_THR2_NORMAL      0x00a0
161
162 /* PLA_RXFIFO_CTRL2 */
163 #define RXFIFO_THR3_FULL        0x00000078
164 #define RXFIFO_THR3_HIGH        0x00000048
165 #define RXFIFO_THR3_OOB         0x0000005a
166 #define RXFIFO_THR3_NORMAL      0x0110
167
168 /* PLA_TXFIFO_CTRL */
169 #define TXFIFO_THR_NORMAL       0x00400008
170 #define TXFIFO_THR_NORMAL2      0x01000008
171
172 /* PLA_FMC */
173 #define FMC_FCR_MCU_EN          0x0001
174
175 /* PLA_EEEP_CR */
176 #define EEEP_CR_EEEP_TX         0x0002
177
178 /* PLA_WDT6_CTRL */
179 #define WDT6_SET_MODE           0x0010
180
181 /* PLA_TCR0 */
182 #define TCR0_TX_EMPTY           0x0800
183 #define TCR0_AUTO_FIFO          0x0080
184
185 /* PLA_TCR1 */
186 #define VERSION_MASK            0x7cf0
187
188 /* PLA_MTPS */
189 #define MTPS_JUMBO              (12 * 1024 / 64)
190 #define MTPS_DEFAULT            (6 * 1024 / 64)
191
192 /* PLA_RSTTALLY */
193 #define TALLY_RESET             0x0001
194
195 /* PLA_CR */
196 #define CR_RST                  0x10
197 #define CR_RE                   0x08
198 #define CR_TE                   0x04
199
200 /* PLA_CRWECR */
201 #define CRWECR_NORAML           0x00
202 #define CRWECR_CONFIG           0xc0
203
204 /* PLA_OOB_CTRL */
205 #define NOW_IS_OOB              0x80
206 #define TXFIFO_EMPTY            0x20
207 #define RXFIFO_EMPTY            0x10
208 #define LINK_LIST_READY         0x02
209 #define DIS_MCU_CLROOB          0x01
210 #define FIFO_EMPTY              (TXFIFO_EMPTY | RXFIFO_EMPTY)
211
212 /* PLA_MISC_1 */
213 #define RXDY_GATED_EN           0x0008
214
215 /* PLA_SFF_STS_7 */
216 #define RE_INIT_LL              0x8000
217 #define MCU_BORW_EN             0x4000
218
219 /* PLA_CPCR */
220 #define CPCR_RX_VLAN            0x0040
221
222 /* PLA_CFG_WOL */
223 #define MAGIC_EN                0x0001
224
225 /* PLA_TEREDO_CFG */
226 #define TEREDO_SEL              0x8000
227 #define TEREDO_WAKE_MASK        0x7f00
228 #define TEREDO_RS_EVENT_MASK    0x00fe
229 #define OOB_TEREDO_EN           0x0001
230
231 /* PAL_BDC_CR */
232 #define ALDPS_PROXY_MODE        0x0001
233
234 /* PLA_CONFIG34 */
235 #define LINK_ON_WAKE_EN         0x0010
236 #define LINK_OFF_WAKE_EN        0x0008
237
238 /* PLA_CONFIG5 */
239 #define BWF_EN                  0x0040
240 #define MWF_EN                  0x0020
241 #define UWF_EN                  0x0010
242 #define LAN_WAKE_EN             0x0002
243
244 /* PLA_LED_FEATURE */
245 #define LED_MODE_MASK           0x0700
246
247 /* PLA_PHY_PWR */
248 #define TX_10M_IDLE_EN          0x0080
249 #define PFM_PWM_SWITCH          0x0040
250
251 /* PLA_MAC_PWR_CTRL */
252 #define D3_CLK_GATED_EN         0x00004000
253 #define MCU_CLK_RATIO           0x07010f07
254 #define MCU_CLK_RATIO_MASK      0x0f0f0f0f
255 #define ALDPS_SPDWN_RATIO       0x0f87
256
257 /* PLA_MAC_PWR_CTRL2 */
258 #define EEE_SPDWN_RATIO         0x8007
259
260 /* PLA_MAC_PWR_CTRL3 */
261 #define PKT_AVAIL_SPDWN_EN      0x0100
262 #define SUSPEND_SPDWN_EN        0x0004
263 #define U1U2_SPDWN_EN           0x0002
264 #define L1_SPDWN_EN             0x0001
265
266 /* PLA_MAC_PWR_CTRL4 */
267 #define PWRSAVE_SPDWN_EN        0x1000
268 #define RXDV_SPDWN_EN           0x0800
269 #define TX10MIDLE_EN            0x0100
270 #define TP100_SPDWN_EN          0x0020
271 #define TP500_SPDWN_EN          0x0010
272 #define TP1000_SPDWN_EN         0x0008
273 #define EEE_SPDWN_EN            0x0001
274
275 /* PLA_GPHY_INTR_IMR */
276 #define GPHY_STS_MSK            0x0001
277 #define SPEED_DOWN_MSK          0x0002
278 #define SPDWN_RXDV_MSK          0x0004
279 #define SPDWN_LINKCHG_MSK       0x0008
280
281 /* PLA_PHYAR */
282 #define PHYAR_FLAG              0x80000000
283
284 /* PLA_EEE_CR */
285 #define EEE_RX_EN               0x0001
286 #define EEE_TX_EN               0x0002
287
288 /* PLA_BOOT_CTRL */
289 #define AUTOLOAD_DONE           0x0002
290
291 /* USB_DEV_STAT */
292 #define STAT_SPEED_MASK         0x0006
293 #define STAT_SPEED_HIGH         0x0000
294 #define STAT_SPEED_FULL         0x0002
295
296 /* USB_TX_AGG */
297 #define TX_AGG_MAX_THRESHOLD    0x03
298
299 /* USB_RX_BUF_TH */
300 #define RX_THR_SUPPER           0x0c350180
301 #define RX_THR_HIGH             0x7a120180
302 #define RX_THR_SLOW             0xffff0180
303
304 /* USB_TX_DMA */
305 #define TEST_MODE_DISABLE       0x00000001
306 #define TX_SIZE_ADJUST1         0x00000100
307
308 /* USB_UPS_CTRL */
309 #define POWER_CUT               0x0100
310
311 /* USB_PM_CTRL_STATUS */
312 #define RESUME_INDICATE         0x0001
313
314 /* USB_USB_CTRL */
315 #define RX_AGG_DISABLE          0x0010
316
317 /* USB_U2P3_CTRL */
318 #define U2P3_ENABLE             0x0001
319
320 /* USB_POWER_CUT */
321 #define PWR_EN                  0x0001
322 #define PHASE2_EN               0x0008
323
324 /* USB_MISC_0 */
325 #define PCUT_STATUS             0x0001
326
327 /* USB_RX_EARLY_AGG */
328 #define EARLY_AGG_SUPPER        0x0e832981
329 #define EARLY_AGG_HIGH          0x0e837a12
330 #define EARLY_AGG_SLOW          0x0e83ffff
331
332 /* USB_WDT11_CTRL */
333 #define TIMER11_EN              0x0001
334
335 /* USB_LPM_CTRL */
336 #define LPM_TIMER_MASK          0x0c
337 #define LPM_TIMER_500MS         0x04    /* 500 ms */
338 #define LPM_TIMER_500US         0x0c    /* 500 us */
339
340 /* USB_AFE_CTRL2 */
341 #define SEN_VAL_MASK            0xf800
342 #define SEN_VAL_NORMAL          0xa000
343 #define SEL_RXIDLE              0x0100
344
345 /* OCP_ALDPS_CONFIG */
346 #define ENPWRSAVE               0x8000
347 #define ENPDNPS                 0x0200
348 #define LINKENA                 0x0100
349 #define DIS_SDSAVE              0x0010
350
351 /* OCP_PHY_STATUS */
352 #define PHY_STAT_MASK           0x0007
353 #define PHY_STAT_LAN_ON         3
354 #define PHY_STAT_PWRDN          5
355
356 /* OCP_POWER_CFG */
357 #define EEE_CLKDIV_EN           0x8000
358 #define EN_ALDPS                0x0004
359 #define EN_10M_PLLOFF           0x0001
360
361 /* OCP_EEE_CONFIG1 */
362 #define RG_TXLPI_MSK_HFDUP      0x8000
363 #define RG_MATCLR_EN            0x4000
364 #define EEE_10_CAP              0x2000
365 #define EEE_NWAY_EN             0x1000
366 #define TX_QUIET_EN             0x0200
367 #define RX_QUIET_EN             0x0100
368 #define sd_rise_time_mask       0x0070
369 #define sd_rise_time(x)         (min(x, 7) << 4)        /* bit 4 ~ 6 */
370 #define RG_RXLPI_MSK_HFDUP      0x0008
371 #define SDFALLTIME              0x0007  /* bit 0 ~ 2 */
372
373 /* OCP_EEE_CONFIG2 */
374 #define RG_LPIHYS_NUM           0x7000  /* bit 12 ~ 15 */
375 #define RG_DACQUIET_EN          0x0400
376 #define RG_LDVQUIET_EN          0x0200
377 #define RG_CKRSEL               0x0020
378 #define RG_EEEPRG_EN            0x0010
379
380 /* OCP_EEE_CONFIG3 */
381 #define fast_snr_mask           0xff80
382 #define fast_snr(x)             (min(x, 0x1ff) << 7)    /* bit 7 ~ 15 */
383 #define RG_LFS_SEL              0x0060  /* bit 6 ~ 5 */
384 #define MSK_PH                  0x0006  /* bit 0 ~ 3 */
385
386 /* OCP_EEE_AR */
387 /* bit[15:14] function */
388 #define FUN_ADDR                0x0000
389 #define FUN_DATA                0x4000
390 /* bit[4:0] device addr */
391
392 /* OCP_EEE_CFG */
393 #define CTAP_SHORT_EN           0x0040
394 #define EEE10_EN                0x0010
395
396 /* OCP_DOWN_SPEED */
397 #define EN_10M_BGOFF            0x0080
398
399 /* OCP_ADC_CFG */
400 #define CKADSEL_L               0x0100
401 #define ADC_EN                  0x0080
402 #define EN_EMI_L                0x0040
403
404 /* SRAM_LPF_CFG */
405 #define LPF_AUTO_TUNE           0x8000
406
407 /* SRAM_10M_AMP1 */
408 #define GDAC_IB_UPALL           0x0008
409
410 /* SRAM_10M_AMP2 */
411 #define AMP_DN                  0x0200
412
413 /* SRAM_IMPEDANCE */
414 #define RX_DRIVING_MASK         0x6000
415
416 enum rtl_register_content {
417         _1000bps        = 0x10,
418         _100bps         = 0x08,
419         _10bps          = 0x04,
420         LINK_STATUS     = 0x02,
421         FULL_DUP        = 0x01,
422 };
423
424 #define RTL8152_MAX_TX          4
425 #define RTL8152_MAX_RX          10
426 #define INTBUFSIZE              2
427 #define CRC_SIZE                4
428 #define TX_ALIGN                4
429 #define RX_ALIGN                8
430
431 #define INTR_LINK               0x0004
432
433 #define RTL8152_REQT_READ       0xc0
434 #define RTL8152_REQT_WRITE      0x40
435 #define RTL8152_REQ_GET_REGS    0x05
436 #define RTL8152_REQ_SET_REGS    0x05
437
438 #define BYTE_EN_DWORD           0xff
439 #define BYTE_EN_WORD            0x33
440 #define BYTE_EN_BYTE            0x11
441 #define BYTE_EN_SIX_BYTES       0x3f
442 #define BYTE_EN_START_MASK      0x0f
443 #define BYTE_EN_END_MASK        0xf0
444
445 #define RTL8153_MAX_PACKET      9216 /* 9K */
446 #define RTL8153_MAX_MTU         (RTL8153_MAX_PACKET - VLAN_ETH_HLEN - VLAN_HLEN)
447 #define RTL8152_RMS             (VLAN_ETH_FRAME_LEN + VLAN_HLEN)
448 #define RTL8153_RMS             RTL8153_MAX_PACKET
449 #define RTL8152_TX_TIMEOUT      (5 * HZ)
450
451 /* rtl8152 flags */
452 enum rtl8152_flags {
453         RTL8152_UNPLUG = 0,
454         RTL8152_SET_RX_MODE,
455         WORK_ENABLE,
456         RTL8152_LINK_CHG,
457         SELECTIVE_SUSPEND,
458         PHY_RESET,
459         SCHEDULE_TASKLET,
460 };
461
462 /* Define these values to match your device */
463 #define VENDOR_ID_REALTEK               0x0bda
464 #define PRODUCT_ID_RTL8152              0x8152
465 #define PRODUCT_ID_RTL8153              0x8153
466
467 #define VENDOR_ID_SAMSUNG               0x04e8
468 #define PRODUCT_ID_SAMSUNG              0xa101
469
470 #define MCU_TYPE_PLA                    0x0100
471 #define MCU_TYPE_USB                    0x0000
472
473 #define REALTEK_USB_DEVICE(vend, prod)  \
474         USB_DEVICE_INTERFACE_CLASS(vend, prod, USB_CLASS_VENDOR_SPEC)
475
476 struct tally_counter {
477         __le64  tx_packets;
478         __le64  rx_packets;
479         __le64  tx_errors;
480         __le32  rx_errors;
481         __le16  rx_missed;
482         __le16  align_errors;
483         __le32  tx_one_collision;
484         __le32  tx_multi_collision;
485         __le64  rx_unicast;
486         __le64  rx_broadcast;
487         __le32  rx_multicast;
488         __le16  tx_aborted;
489         __le16  tx_underun;
490 };
491
492 struct rx_desc {
493         __le32 opts1;
494 #define RX_LEN_MASK                     0x7fff
495
496         __le32 opts2;
497 #define RD_UDP_CS                       (1 << 23)
498 #define RD_TCP_CS                       (1 << 22)
499 #define RD_IPV6_CS                      (1 << 20)
500 #define RD_IPV4_CS                      (1 << 19)
501
502         __le32 opts3;
503 #define IPF                             (1 << 23) /* IP checksum fail */
504 #define UDPF                            (1 << 22) /* UDP checksum fail */
505 #define TCPF                            (1 << 21) /* TCP checksum fail */
506 #define RX_VLAN_TAG                     (1 << 16)
507
508         __le32 opts4;
509         __le32 opts5;
510         __le32 opts6;
511 };
512
513 struct tx_desc {
514         __le32 opts1;
515 #define TX_FS                   (1 << 31) /* First segment of a packet */
516 #define TX_LS                   (1 << 30) /* Final segment of a packet */
517 #define GTSENDV4                (1 << 28)
518 #define GTSENDV6                (1 << 27)
519 #define GTTCPHO_SHIFT           18
520 #define GTTCPHO_MAX             0x7fU
521 #define TX_LEN_MAX              0x3ffffU
522
523         __le32 opts2;
524 #define UDP_CS                  (1 << 31) /* Calculate UDP/IP checksum */
525 #define TCP_CS                  (1 << 30) /* Calculate TCP/IP checksum */
526 #define IPV4_CS                 (1 << 29) /* Calculate IPv4 checksum */
527 #define IPV6_CS                 (1 << 28) /* Calculate IPv6 checksum */
528 #define MSS_SHIFT               17
529 #define MSS_MAX                 0x7ffU
530 #define TCPHO_SHIFT             17
531 #define TCPHO_MAX               0x7ffU
532 #define TX_VLAN_TAG                     (1 << 16)
533 };
534
535 struct r8152;
536
537 struct rx_agg {
538         struct list_head list;
539         struct urb *urb;
540         struct r8152 *context;
541         void *buffer;
542         void *head;
543 };
544
545 struct tx_agg {
546         struct list_head list;
547         struct urb *urb;
548         struct r8152 *context;
549         void *buffer;
550         void *head;
551         u32 skb_num;
552         u32 skb_len;
553 };
554
555 struct r8152 {
556         unsigned long flags;
557         struct usb_device *udev;
558         struct tasklet_struct tl;
559         struct usb_interface *intf;
560         struct net_device *netdev;
561         struct urb *intr_urb;
562         struct tx_agg tx_info[RTL8152_MAX_TX];
563         struct rx_agg rx_info[RTL8152_MAX_RX];
564         struct list_head rx_done, tx_free;
565         struct sk_buff_head tx_queue;
566         spinlock_t rx_lock, tx_lock;
567         struct delayed_work schedule;
568         struct mii_if_info mii;
569
570         struct rtl_ops {
571                 void (*init)(struct r8152 *);
572                 int (*enable)(struct r8152 *);
573                 void (*disable)(struct r8152 *);
574                 void (*up)(struct r8152 *);
575                 void (*down)(struct r8152 *);
576                 void (*unload)(struct r8152 *);
577                 int (*eee_get)(struct r8152 *, struct ethtool_eee *);
578                 int (*eee_set)(struct r8152 *, struct ethtool_eee *);
579         } rtl_ops;
580
581         int intr_interval;
582         u32 saved_wolopts;
583         u32 msg_enable;
584         u32 tx_qlen;
585         u16 ocp_base;
586         u8 *intr_buff;
587         u8 version;
588         u8 speed;
589 };
590
591 enum rtl_version {
592         RTL_VER_UNKNOWN = 0,
593         RTL_VER_01,
594         RTL_VER_02,
595         RTL_VER_03,
596         RTL_VER_04,
597         RTL_VER_05,
598         RTL_VER_MAX
599 };
600
601 enum tx_csum_stat {
602         TX_CSUM_SUCCESS = 0,
603         TX_CSUM_TSO,
604         TX_CSUM_NONE
605 };
606
607 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
608  * The RTL chips use a 64 element hash table based on the Ethernet CRC.
609  */
610 static const int multicast_filter_limit = 32;
611 static unsigned int agg_buf_sz = 16384;
612
613 #define RTL_LIMITED_TSO_SIZE    (agg_buf_sz - sizeof(struct tx_desc) - \
614                                  VLAN_ETH_HLEN - VLAN_HLEN)
615
616 static
617 int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
618 {
619         int ret;
620         void *tmp;
621
622         tmp = kmalloc(size, GFP_KERNEL);
623         if (!tmp)
624                 return -ENOMEM;
625
626         ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0),
627                               RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
628                               value, index, tmp, size, 500);
629
630         memcpy(data, tmp, size);
631         kfree(tmp);
632
633         return ret;
634 }
635
636 static
637 int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
638 {
639         int ret;
640         void *tmp;
641
642         tmp = kmemdup(data, size, GFP_KERNEL);
643         if (!tmp)
644                 return -ENOMEM;
645
646         ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0),
647                               RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE,
648                               value, index, tmp, size, 500);
649
650         kfree(tmp);
651
652         return ret;
653 }
654
655 static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
656                             void *data, u16 type)
657 {
658         u16 limit = 64;
659         int ret = 0;
660
661         if (test_bit(RTL8152_UNPLUG, &tp->flags))
662                 return -ENODEV;
663
664         /* both size and indix must be 4 bytes align */
665         if ((size & 3) || !size || (index & 3) || !data)
666                 return -EPERM;
667
668         if ((u32)index + (u32)size > 0xffff)
669                 return -EPERM;
670
671         while (size) {
672                 if (size > limit) {
673                         ret = get_registers(tp, index, type, limit, data);
674                         if (ret < 0)
675                                 break;
676
677                         index += limit;
678                         data += limit;
679                         size -= limit;
680                 } else {
681                         ret = get_registers(tp, index, type, size, data);
682                         if (ret < 0)
683                                 break;
684
685                         index += size;
686                         data += size;
687                         size = 0;
688                         break;
689                 }
690         }
691
692         return ret;
693 }
694
695 static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
696                              u16 size, void *data, u16 type)
697 {
698         int ret;
699         u16 byteen_start, byteen_end, byen;
700         u16 limit = 512;
701
702         if (test_bit(RTL8152_UNPLUG, &tp->flags))
703                 return -ENODEV;
704
705         /* both size and indix must be 4 bytes align */
706         if ((size & 3) || !size || (index & 3) || !data)
707                 return -EPERM;
708
709         if ((u32)index + (u32)size > 0xffff)
710                 return -EPERM;
711
712         byteen_start = byteen & BYTE_EN_START_MASK;
713         byteen_end = byteen & BYTE_EN_END_MASK;
714
715         byen = byteen_start | (byteen_start << 4);
716         ret = set_registers(tp, index, type | byen, 4, data);
717         if (ret < 0)
718                 goto error1;
719
720         index += 4;
721         data += 4;
722         size -= 4;
723
724         if (size) {
725                 size -= 4;
726
727                 while (size) {
728                         if (size > limit) {
729                                 ret = set_registers(tp, index,
730                                                     type | BYTE_EN_DWORD,
731                                                     limit, data);
732                                 if (ret < 0)
733                                         goto error1;
734
735                                 index += limit;
736                                 data += limit;
737                                 size -= limit;
738                         } else {
739                                 ret = set_registers(tp, index,
740                                                     type | BYTE_EN_DWORD,
741                                                     size, data);
742                                 if (ret < 0)
743                                         goto error1;
744
745                                 index += size;
746                                 data += size;
747                                 size = 0;
748                                 break;
749                         }
750                 }
751
752                 byen = byteen_end | (byteen_end >> 4);
753                 ret = set_registers(tp, index, type | byen, 4, data);
754                 if (ret < 0)
755                         goto error1;
756         }
757
758 error1:
759         return ret;
760 }
761
762 static inline
763 int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
764 {
765         return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA);
766 }
767
768 static inline
769 int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
770 {
771         return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA);
772 }
773
774 static inline
775 int usb_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
776 {
777         return generic_ocp_read(tp, index, size, data, MCU_TYPE_USB);
778 }
779
780 static inline
781 int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
782 {
783         return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB);
784 }
785
786 static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index)
787 {
788         __le32 data;
789
790         generic_ocp_read(tp, index, sizeof(data), &data, type);
791
792         return __le32_to_cpu(data);
793 }
794
795 static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data)
796 {
797         __le32 tmp = __cpu_to_le32(data);
798
799         generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type);
800 }
801
802 static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index)
803 {
804         u32 data;
805         __le32 tmp;
806         u8 shift = index & 2;
807
808         index &= ~3;
809
810         generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
811
812         data = __le32_to_cpu(tmp);
813         data >>= (shift * 8);
814         data &= 0xffff;
815
816         return (u16)data;
817 }
818
819 static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data)
820 {
821         u32 mask = 0xffff;
822         __le32 tmp;
823         u16 byen = BYTE_EN_WORD;
824         u8 shift = index & 2;
825
826         data &= mask;
827
828         if (index & 2) {
829                 byen <<= shift;
830                 mask <<= (shift * 8);
831                 data <<= (shift * 8);
832                 index &= ~3;
833         }
834
835         generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
836
837         data |= __le32_to_cpu(tmp) & ~mask;
838         tmp = __cpu_to_le32(data);
839
840         generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
841 }
842
843 static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index)
844 {
845         u32 data;
846         __le32 tmp;
847         u8 shift = index & 3;
848
849         index &= ~3;
850
851         generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
852
853         data = __le32_to_cpu(tmp);
854         data >>= (shift * 8);
855         data &= 0xff;
856
857         return (u8)data;
858 }
859
860 static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data)
861 {
862         u32 mask = 0xff;
863         __le32 tmp;
864         u16 byen = BYTE_EN_BYTE;
865         u8 shift = index & 3;
866
867         data &= mask;
868
869         if (index & 3) {
870                 byen <<= shift;
871                 mask <<= (shift * 8);
872                 data <<= (shift * 8);
873                 index &= ~3;
874         }
875
876         generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
877
878         data |= __le32_to_cpu(tmp) & ~mask;
879         tmp = __cpu_to_le32(data);
880
881         generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
882 }
883
884 static u16 ocp_reg_read(struct r8152 *tp, u16 addr)
885 {
886         u16 ocp_base, ocp_index;
887
888         ocp_base = addr & 0xf000;
889         if (ocp_base != tp->ocp_base) {
890                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
891                 tp->ocp_base = ocp_base;
892         }
893
894         ocp_index = (addr & 0x0fff) | 0xb000;
895         return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index);
896 }
897
898 static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data)
899 {
900         u16 ocp_base, ocp_index;
901
902         ocp_base = addr & 0xf000;
903         if (ocp_base != tp->ocp_base) {
904                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
905                 tp->ocp_base = ocp_base;
906         }
907
908         ocp_index = (addr & 0x0fff) | 0xb000;
909         ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data);
910 }
911
912 static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value)
913 {
914         ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value);
915 }
916
917 static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr)
918 {
919         return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2);
920 }
921
922 static void sram_write(struct r8152 *tp, u16 addr, u16 data)
923 {
924         ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
925         ocp_reg_write(tp, OCP_SRAM_DATA, data);
926 }
927
928 static u16 sram_read(struct r8152 *tp, u16 addr)
929 {
930         ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
931         return ocp_reg_read(tp, OCP_SRAM_DATA);
932 }
933
934 static int read_mii_word(struct net_device *netdev, int phy_id, int reg)
935 {
936         struct r8152 *tp = netdev_priv(netdev);
937         int ret;
938
939         if (test_bit(RTL8152_UNPLUG, &tp->flags))
940                 return -ENODEV;
941
942         if (phy_id != R8152_PHY_ID)
943                 return -EINVAL;
944
945         ret = usb_autopm_get_interface(tp->intf);
946         if (ret < 0)
947                 goto out;
948
949         ret = r8152_mdio_read(tp, reg);
950
951         usb_autopm_put_interface(tp->intf);
952
953 out:
954         return ret;
955 }
956
957 static
958 void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val)
959 {
960         struct r8152 *tp = netdev_priv(netdev);
961
962         if (test_bit(RTL8152_UNPLUG, &tp->flags))
963                 return;
964
965         if (phy_id != R8152_PHY_ID)
966                 return;
967
968         if (usb_autopm_get_interface(tp->intf) < 0)
969                 return;
970
971         r8152_mdio_write(tp, reg, val);
972
973         usb_autopm_put_interface(tp->intf);
974 }
975
976 static int
977 r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags);
978
979 static int rtl8152_set_mac_address(struct net_device *netdev, void *p)
980 {
981         struct r8152 *tp = netdev_priv(netdev);
982         struct sockaddr *addr = p;
983
984         if (!is_valid_ether_addr(addr->sa_data))
985                 return -EADDRNOTAVAIL;
986
987         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
988
989         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
990         pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data);
991         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
992
993         return 0;
994 }
995
996 static int set_ethernet_addr(struct r8152 *tp)
997 {
998         struct net_device *dev = tp->netdev;
999         struct sockaddr sa;
1000         int ret;
1001
1002         if (tp->version == RTL_VER_01)
1003                 ret = pla_ocp_read(tp, PLA_IDR, 8, sa.sa_data);
1004         else
1005                 ret = pla_ocp_read(tp, PLA_BACKUP, 8, sa.sa_data);
1006
1007         if (ret < 0) {
1008                 netif_err(tp, probe, dev, "Get ether addr fail\n");
1009         } else if (!is_valid_ether_addr(sa.sa_data)) {
1010                 netif_err(tp, probe, dev, "Invalid ether addr %pM\n",
1011                           sa.sa_data);
1012                 eth_hw_addr_random(dev);
1013                 ether_addr_copy(sa.sa_data, dev->dev_addr);
1014                 ret = rtl8152_set_mac_address(dev, &sa);
1015                 netif_info(tp, probe, dev, "Random ether addr %pM\n",
1016                            sa.sa_data);
1017         } else {
1018                 if (tp->version == RTL_VER_01)
1019                         ether_addr_copy(dev->dev_addr, sa.sa_data);
1020                 else
1021                         ret = rtl8152_set_mac_address(dev, &sa);
1022         }
1023
1024         return ret;
1025 }
1026
1027 static void read_bulk_callback(struct urb *urb)
1028 {
1029         struct net_device *netdev;
1030         int status = urb->status;
1031         struct rx_agg *agg;
1032         struct r8152 *tp;
1033         int result;
1034
1035         agg = urb->context;
1036         if (!agg)
1037                 return;
1038
1039         tp = agg->context;
1040         if (!tp)
1041                 return;
1042
1043         if (test_bit(RTL8152_UNPLUG, &tp->flags))
1044                 return;
1045
1046         if (!test_bit(WORK_ENABLE, &tp->flags))
1047                 return;
1048
1049         netdev = tp->netdev;
1050
1051         /* When link down, the driver would cancel all bulks. */
1052         /* This avoid the re-submitting bulk */
1053         if (!netif_carrier_ok(netdev))
1054                 return;
1055
1056         usb_mark_last_busy(tp->udev);
1057
1058         switch (status) {
1059         case 0:
1060                 if (urb->actual_length < ETH_ZLEN)
1061                         break;
1062
1063                 spin_lock(&tp->rx_lock);
1064                 list_add_tail(&agg->list, &tp->rx_done);
1065                 spin_unlock(&tp->rx_lock);
1066                 tasklet_schedule(&tp->tl);
1067                 return;
1068         case -ESHUTDOWN:
1069                 set_bit(RTL8152_UNPLUG, &tp->flags);
1070                 netif_device_detach(tp->netdev);
1071                 return;
1072         case -ENOENT:
1073                 return; /* the urb is in unlink state */
1074         case -ETIME:
1075                 if (net_ratelimit())
1076                         netdev_warn(netdev, "maybe reset is needed?\n");
1077                 break;
1078         default:
1079                 if (net_ratelimit())
1080                         netdev_warn(netdev, "Rx status %d\n", status);
1081                 break;
1082         }
1083
1084         result = r8152_submit_rx(tp, agg, GFP_ATOMIC);
1085         if (result == -ENODEV) {
1086                 netif_device_detach(tp->netdev);
1087         } else if (result) {
1088                 spin_lock(&tp->rx_lock);
1089                 list_add_tail(&agg->list, &tp->rx_done);
1090                 spin_unlock(&tp->rx_lock);
1091                 tasklet_schedule(&tp->tl);
1092         }
1093 }
1094
1095 static void write_bulk_callback(struct urb *urb)
1096 {
1097         struct net_device_stats *stats;
1098         struct net_device *netdev;
1099         struct tx_agg *agg;
1100         struct r8152 *tp;
1101         int status = urb->status;
1102
1103         agg = urb->context;
1104         if (!agg)
1105                 return;
1106
1107         tp = agg->context;
1108         if (!tp)
1109                 return;
1110
1111         netdev = tp->netdev;
1112         stats = &netdev->stats;
1113         if (status) {
1114                 if (net_ratelimit())
1115                         netdev_warn(netdev, "Tx status %d\n", status);
1116                 stats->tx_errors += agg->skb_num;
1117         } else {
1118                 stats->tx_packets += agg->skb_num;
1119                 stats->tx_bytes += agg->skb_len;
1120         }
1121
1122         spin_lock(&tp->tx_lock);
1123         list_add_tail(&agg->list, &tp->tx_free);
1124         spin_unlock(&tp->tx_lock);
1125
1126         usb_autopm_put_interface_async(tp->intf);
1127
1128         if (!netif_carrier_ok(netdev))
1129                 return;
1130
1131         if (!test_bit(WORK_ENABLE, &tp->flags))
1132                 return;
1133
1134         if (test_bit(RTL8152_UNPLUG, &tp->flags))
1135                 return;
1136
1137         if (!skb_queue_empty(&tp->tx_queue))
1138                 tasklet_schedule(&tp->tl);
1139 }
1140
1141 static void intr_callback(struct urb *urb)
1142 {
1143         struct r8152 *tp;
1144         __le16 *d;
1145         int status = urb->status;
1146         int res;
1147
1148         tp = urb->context;
1149         if (!tp)
1150                 return;
1151
1152         if (!test_bit(WORK_ENABLE, &tp->flags))
1153                 return;
1154
1155         if (test_bit(RTL8152_UNPLUG, &tp->flags))
1156                 return;
1157
1158         switch (status) {
1159         case 0:                 /* success */
1160                 break;
1161         case -ECONNRESET:       /* unlink */
1162         case -ESHUTDOWN:
1163                 netif_device_detach(tp->netdev);
1164         case -ENOENT:
1165                 return;
1166         case -EOVERFLOW:
1167                 netif_info(tp, intr, tp->netdev, "intr status -EOVERFLOW\n");
1168                 goto resubmit;
1169         /* -EPIPE:  should clear the halt */
1170         default:
1171                 netif_info(tp, intr, tp->netdev, "intr status %d\n", status);
1172                 goto resubmit;
1173         }
1174
1175         d = urb->transfer_buffer;
1176         if (INTR_LINK & __le16_to_cpu(d[0])) {
1177                 if (!(tp->speed & LINK_STATUS)) {
1178                         set_bit(RTL8152_LINK_CHG, &tp->flags);
1179                         schedule_delayed_work(&tp->schedule, 0);
1180                 }
1181         } else {
1182                 if (tp->speed & LINK_STATUS) {
1183                         set_bit(RTL8152_LINK_CHG, &tp->flags);
1184                         schedule_delayed_work(&tp->schedule, 0);
1185                 }
1186         }
1187
1188 resubmit:
1189         res = usb_submit_urb(urb, GFP_ATOMIC);
1190         if (res == -ENODEV)
1191                 netif_device_detach(tp->netdev);
1192         else if (res)
1193                 netif_err(tp, intr, tp->netdev,
1194                           "can't resubmit intr, status %d\n", res);
1195 }
1196
1197 static inline void *rx_agg_align(void *data)
1198 {
1199         return (void *)ALIGN((uintptr_t)data, RX_ALIGN);
1200 }
1201
1202 static inline void *tx_agg_align(void *data)
1203 {
1204         return (void *)ALIGN((uintptr_t)data, TX_ALIGN);
1205 }
1206
1207 static void free_all_mem(struct r8152 *tp)
1208 {
1209         int i;
1210
1211         for (i = 0; i < RTL8152_MAX_RX; i++) {
1212                 usb_free_urb(tp->rx_info[i].urb);
1213                 tp->rx_info[i].urb = NULL;
1214
1215                 kfree(tp->rx_info[i].buffer);
1216                 tp->rx_info[i].buffer = NULL;
1217                 tp->rx_info[i].head = NULL;
1218         }
1219
1220         for (i = 0; i < RTL8152_MAX_TX; i++) {
1221                 usb_free_urb(tp->tx_info[i].urb);
1222                 tp->tx_info[i].urb = NULL;
1223
1224                 kfree(tp->tx_info[i].buffer);
1225                 tp->tx_info[i].buffer = NULL;
1226                 tp->tx_info[i].head = NULL;
1227         }
1228
1229         usb_free_urb(tp->intr_urb);
1230         tp->intr_urb = NULL;
1231
1232         kfree(tp->intr_buff);
1233         tp->intr_buff = NULL;
1234 }
1235
1236 static int alloc_all_mem(struct r8152 *tp)
1237 {
1238         struct net_device *netdev = tp->netdev;
1239         struct usb_interface *intf = tp->intf;
1240         struct usb_host_interface *alt = intf->cur_altsetting;
1241         struct usb_host_endpoint *ep_intr = alt->endpoint + 2;
1242         struct urb *urb;
1243         int node, i;
1244         u8 *buf;
1245
1246         node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1;
1247
1248         spin_lock_init(&tp->rx_lock);
1249         spin_lock_init(&tp->tx_lock);
1250         INIT_LIST_HEAD(&tp->rx_done);
1251         INIT_LIST_HEAD(&tp->tx_free);
1252         skb_queue_head_init(&tp->tx_queue);
1253
1254         for (i = 0; i < RTL8152_MAX_RX; i++) {
1255                 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
1256                 if (!buf)
1257                         goto err1;
1258
1259                 if (buf != rx_agg_align(buf)) {
1260                         kfree(buf);
1261                         buf = kmalloc_node(agg_buf_sz + RX_ALIGN, GFP_KERNEL,
1262                                            node);
1263                         if (!buf)
1264                                 goto err1;
1265                 }
1266
1267                 urb = usb_alloc_urb(0, GFP_KERNEL);
1268                 if (!urb) {
1269                         kfree(buf);
1270                         goto err1;
1271                 }
1272
1273                 INIT_LIST_HEAD(&tp->rx_info[i].list);
1274                 tp->rx_info[i].context = tp;
1275                 tp->rx_info[i].urb = urb;
1276                 tp->rx_info[i].buffer = buf;
1277                 tp->rx_info[i].head = rx_agg_align(buf);
1278         }
1279
1280         for (i = 0; i < RTL8152_MAX_TX; i++) {
1281                 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
1282                 if (!buf)
1283                         goto err1;
1284
1285                 if (buf != tx_agg_align(buf)) {
1286                         kfree(buf);
1287                         buf = kmalloc_node(agg_buf_sz + TX_ALIGN, GFP_KERNEL,
1288                                            node);
1289                         if (!buf)
1290                                 goto err1;
1291                 }
1292
1293                 urb = usb_alloc_urb(0, GFP_KERNEL);
1294                 if (!urb) {
1295                         kfree(buf);
1296                         goto err1;
1297                 }
1298
1299                 INIT_LIST_HEAD(&tp->tx_info[i].list);
1300                 tp->tx_info[i].context = tp;
1301                 tp->tx_info[i].urb = urb;
1302                 tp->tx_info[i].buffer = buf;
1303                 tp->tx_info[i].head = tx_agg_align(buf);
1304
1305                 list_add_tail(&tp->tx_info[i].list, &tp->tx_free);
1306         }
1307
1308         tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL);
1309         if (!tp->intr_urb)
1310                 goto err1;
1311
1312         tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL);
1313         if (!tp->intr_buff)
1314                 goto err1;
1315
1316         tp->intr_interval = (int)ep_intr->desc.bInterval;
1317         usb_fill_int_urb(tp->intr_urb, tp->udev, usb_rcvintpipe(tp->udev, 3),
1318                          tp->intr_buff, INTBUFSIZE, intr_callback,
1319                          tp, tp->intr_interval);
1320
1321         return 0;
1322
1323 err1:
1324         free_all_mem(tp);
1325         return -ENOMEM;
1326 }
1327
1328 static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp)
1329 {
1330         struct tx_agg *agg = NULL;
1331         unsigned long flags;
1332
1333         if (list_empty(&tp->tx_free))
1334                 return NULL;
1335
1336         spin_lock_irqsave(&tp->tx_lock, flags);
1337         if (!list_empty(&tp->tx_free)) {
1338                 struct list_head *cursor;
1339
1340                 cursor = tp->tx_free.next;
1341                 list_del_init(cursor);
1342                 agg = list_entry(cursor, struct tx_agg, list);
1343         }
1344         spin_unlock_irqrestore(&tp->tx_lock, flags);
1345
1346         return agg;
1347 }
1348
1349 static inline __be16 get_protocol(struct sk_buff *skb)
1350 {
1351         __be16 protocol;
1352
1353         if (skb->protocol == htons(ETH_P_8021Q))
1354                 protocol = vlan_eth_hdr(skb)->h_vlan_encapsulated_proto;
1355         else
1356                 protocol = skb->protocol;
1357
1358         return protocol;
1359 }
1360
1361 /* r8152_csum_workaround()
1362  * The hw limites the value the transport offset. When the offset is out of the
1363  * range, calculate the checksum by sw.
1364  */
1365 static void r8152_csum_workaround(struct r8152 *tp, struct sk_buff *skb,
1366                                   struct sk_buff_head *list)
1367 {
1368         if (skb_shinfo(skb)->gso_size) {
1369                 netdev_features_t features = tp->netdev->features;
1370                 struct sk_buff_head seg_list;
1371                 struct sk_buff *segs, *nskb;
1372
1373                 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
1374                 segs = skb_gso_segment(skb, features);
1375                 if (IS_ERR(segs) || !segs)
1376                         goto drop;
1377
1378                 __skb_queue_head_init(&seg_list);
1379
1380                 do {
1381                         nskb = segs;
1382                         segs = segs->next;
1383                         nskb->next = NULL;
1384                         __skb_queue_tail(&seg_list, nskb);
1385                 } while (segs);
1386
1387                 skb_queue_splice(&seg_list, list);
1388                 dev_kfree_skb(skb);
1389         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
1390                 if (skb_checksum_help(skb) < 0)
1391                         goto drop;
1392
1393                 __skb_queue_head(list, skb);
1394         } else {
1395                 struct net_device_stats *stats;
1396
1397 drop:
1398                 stats = &tp->netdev->stats;
1399                 stats->tx_dropped++;
1400                 dev_kfree_skb(skb);
1401         }
1402 }
1403
1404 /* msdn_giant_send_check()
1405  * According to the document of microsoft, the TCP Pseudo Header excludes the
1406  * packet length for IPv6 TCP large packets.
1407  */
1408 static int msdn_giant_send_check(struct sk_buff *skb)
1409 {
1410         const struct ipv6hdr *ipv6h;
1411         struct tcphdr *th;
1412         int ret;
1413
1414         ret = skb_cow_head(skb, 0);
1415         if (ret)
1416                 return ret;
1417
1418         ipv6h = ipv6_hdr(skb);
1419         th = tcp_hdr(skb);
1420
1421         th->check = 0;
1422         th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
1423
1424         return ret;
1425 }
1426
1427 static inline void rtl_tx_vlan_tag(struct tx_desc *desc, struct sk_buff *skb)
1428 {
1429         if (vlan_tx_tag_present(skb)) {
1430                 u32 opts2;
1431
1432                 opts2 = TX_VLAN_TAG | swab16(vlan_tx_tag_get(skb));
1433                 desc->opts2 |= cpu_to_le32(opts2);
1434         }
1435 }
1436
1437 static inline void rtl_rx_vlan_tag(struct rx_desc *desc, struct sk_buff *skb)
1438 {
1439         u32 opts2 = le32_to_cpu(desc->opts2);
1440
1441         if (opts2 & RX_VLAN_TAG)
1442                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
1443                                        swab16(opts2 & 0xffff));
1444 }
1445
1446 static int r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc,
1447                          struct sk_buff *skb, u32 len, u32 transport_offset)
1448 {
1449         u32 mss = skb_shinfo(skb)->gso_size;
1450         u32 opts1, opts2 = 0;
1451         int ret = TX_CSUM_SUCCESS;
1452
1453         WARN_ON_ONCE(len > TX_LEN_MAX);
1454
1455         opts1 = len | TX_FS | TX_LS;
1456
1457         if (mss) {
1458                 if (transport_offset > GTTCPHO_MAX) {
1459                         netif_warn(tp, tx_err, tp->netdev,
1460                                    "Invalid transport offset 0x%x for TSO\n",
1461                                    transport_offset);
1462                         ret = TX_CSUM_TSO;
1463                         goto unavailable;
1464                 }
1465
1466                 switch (get_protocol(skb)) {
1467                 case htons(ETH_P_IP):
1468                         opts1 |= GTSENDV4;
1469                         break;
1470
1471                 case htons(ETH_P_IPV6):
1472                         if (msdn_giant_send_check(skb)) {
1473                                 ret = TX_CSUM_TSO;
1474                                 goto unavailable;
1475                         }
1476                         opts1 |= GTSENDV6;
1477                         break;
1478
1479                 default:
1480                         WARN_ON_ONCE(1);
1481                         break;
1482                 }
1483
1484                 opts1 |= transport_offset << GTTCPHO_SHIFT;
1485                 opts2 |= min(mss, MSS_MAX) << MSS_SHIFT;
1486         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
1487                 u8 ip_protocol;
1488
1489                 if (transport_offset > TCPHO_MAX) {
1490                         netif_warn(tp, tx_err, tp->netdev,
1491                                    "Invalid transport offset 0x%x\n",
1492                                    transport_offset);
1493                         ret = TX_CSUM_NONE;
1494                         goto unavailable;
1495                 }
1496
1497                 switch (get_protocol(skb)) {
1498                 case htons(ETH_P_IP):
1499                         opts2 |= IPV4_CS;
1500                         ip_protocol = ip_hdr(skb)->protocol;
1501                         break;
1502
1503                 case htons(ETH_P_IPV6):
1504                         opts2 |= IPV6_CS;
1505                         ip_protocol = ipv6_hdr(skb)->nexthdr;
1506                         break;
1507
1508                 default:
1509                         ip_protocol = IPPROTO_RAW;
1510                         break;
1511                 }
1512
1513                 if (ip_protocol == IPPROTO_TCP)
1514                         opts2 |= TCP_CS;
1515                 else if (ip_protocol == IPPROTO_UDP)
1516                         opts2 |= UDP_CS;
1517                 else
1518                         WARN_ON_ONCE(1);
1519
1520                 opts2 |= transport_offset << TCPHO_SHIFT;
1521         }
1522
1523         desc->opts2 = cpu_to_le32(opts2);
1524         desc->opts1 = cpu_to_le32(opts1);
1525
1526 unavailable:
1527         return ret;
1528 }
1529
1530 static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg)
1531 {
1532         struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
1533         int remain, ret;
1534         u8 *tx_data;
1535
1536         __skb_queue_head_init(&skb_head);
1537         spin_lock(&tx_queue->lock);
1538         skb_queue_splice_init(tx_queue, &skb_head);
1539         spin_unlock(&tx_queue->lock);
1540
1541         tx_data = agg->head;
1542         agg->skb_num = 0;
1543         agg->skb_len = 0;
1544         remain = agg_buf_sz;
1545
1546         while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) {
1547                 struct tx_desc *tx_desc;
1548                 struct sk_buff *skb;
1549                 unsigned int len;
1550                 u32 offset;
1551
1552                 skb = __skb_dequeue(&skb_head);
1553                 if (!skb)
1554                         break;
1555
1556                 len = skb->len + sizeof(*tx_desc);
1557
1558                 if (len > remain) {
1559                         __skb_queue_head(&skb_head, skb);
1560                         break;
1561                 }
1562
1563                 tx_data = tx_agg_align(tx_data);
1564                 tx_desc = (struct tx_desc *)tx_data;
1565
1566                 offset = (u32)skb_transport_offset(skb);
1567
1568                 if (r8152_tx_csum(tp, tx_desc, skb, skb->len, offset)) {
1569                         r8152_csum_workaround(tp, skb, &skb_head);
1570                         continue;
1571                 }
1572
1573                 rtl_tx_vlan_tag(tx_desc, skb);
1574
1575                 tx_data += sizeof(*tx_desc);
1576
1577                 len = skb->len;
1578                 if (skb_copy_bits(skb, 0, tx_data, len) < 0) {
1579                         struct net_device_stats *stats = &tp->netdev->stats;
1580
1581                         stats->tx_dropped++;
1582                         dev_kfree_skb_any(skb);
1583                         tx_data -= sizeof(*tx_desc);
1584                         continue;
1585                 }
1586
1587                 tx_data += len;
1588                 agg->skb_len += len;
1589                 agg->skb_num++;
1590
1591                 dev_kfree_skb_any(skb);
1592
1593                 remain = agg_buf_sz - (int)(tx_agg_align(tx_data) - agg->head);
1594         }
1595
1596         if (!skb_queue_empty(&skb_head)) {
1597                 spin_lock(&tx_queue->lock);
1598                 skb_queue_splice(&skb_head, tx_queue);
1599                 spin_unlock(&tx_queue->lock);
1600         }
1601
1602         netif_tx_lock(tp->netdev);
1603
1604         if (netif_queue_stopped(tp->netdev) &&
1605             skb_queue_len(&tp->tx_queue) < tp->tx_qlen)
1606                 netif_wake_queue(tp->netdev);
1607
1608         netif_tx_unlock(tp->netdev);
1609
1610         ret = usb_autopm_get_interface_async(tp->intf);
1611         if (ret < 0)
1612                 goto out_tx_fill;
1613
1614         usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2),
1615                           agg->head, (int)(tx_data - (u8 *)agg->head),
1616                           (usb_complete_t)write_bulk_callback, agg);
1617
1618         ret = usb_submit_urb(agg->urb, GFP_ATOMIC);
1619         if (ret < 0)
1620                 usb_autopm_put_interface_async(tp->intf);
1621
1622 out_tx_fill:
1623         return ret;
1624 }
1625
1626 static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc)
1627 {
1628         u8 checksum = CHECKSUM_NONE;
1629         u32 opts2, opts3;
1630
1631         if (tp->version == RTL_VER_01)
1632                 goto return_result;
1633
1634         opts2 = le32_to_cpu(rx_desc->opts2);
1635         opts3 = le32_to_cpu(rx_desc->opts3);
1636
1637         if (opts2 & RD_IPV4_CS) {
1638                 if (opts3 & IPF)
1639                         checksum = CHECKSUM_NONE;
1640                 else if ((opts2 & RD_UDP_CS) && (opts3 & UDPF))
1641                         checksum = CHECKSUM_NONE;
1642                 else if ((opts2 & RD_TCP_CS) && (opts3 & TCPF))
1643                         checksum = CHECKSUM_NONE;
1644                 else
1645                         checksum = CHECKSUM_UNNECESSARY;
1646         } else if (RD_IPV6_CS) {
1647                 if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))
1648                         checksum = CHECKSUM_UNNECESSARY;
1649                 else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))
1650                         checksum = CHECKSUM_UNNECESSARY;
1651         }
1652
1653 return_result:
1654         return checksum;
1655 }
1656
1657 static void rx_bottom(struct r8152 *tp)
1658 {
1659         unsigned long flags;
1660         struct list_head *cursor, *next, rx_queue;
1661
1662         if (list_empty(&tp->rx_done))
1663                 return;
1664
1665         INIT_LIST_HEAD(&rx_queue);
1666         spin_lock_irqsave(&tp->rx_lock, flags);
1667         list_splice_init(&tp->rx_done, &rx_queue);
1668         spin_unlock_irqrestore(&tp->rx_lock, flags);
1669
1670         list_for_each_safe(cursor, next, &rx_queue) {
1671                 struct rx_desc *rx_desc;
1672                 struct rx_agg *agg;
1673                 int len_used = 0;
1674                 struct urb *urb;
1675                 u8 *rx_data;
1676                 int ret;
1677
1678                 list_del_init(cursor);
1679
1680                 agg = list_entry(cursor, struct rx_agg, list);
1681                 urb = agg->urb;
1682                 if (urb->actual_length < ETH_ZLEN)
1683                         goto submit;
1684
1685                 rx_desc = agg->head;
1686                 rx_data = agg->head;
1687                 len_used += sizeof(struct rx_desc);
1688
1689                 while (urb->actual_length > len_used) {
1690                         struct net_device *netdev = tp->netdev;
1691                         struct net_device_stats *stats = &netdev->stats;
1692                         unsigned int pkt_len;
1693                         struct sk_buff *skb;
1694
1695                         pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
1696                         if (pkt_len < ETH_ZLEN)
1697                                 break;
1698
1699                         len_used += pkt_len;
1700                         if (urb->actual_length < len_used)
1701                                 break;
1702
1703                         pkt_len -= CRC_SIZE;
1704                         rx_data += sizeof(struct rx_desc);
1705
1706                         skb = netdev_alloc_skb_ip_align(netdev, pkt_len);
1707                         if (!skb) {
1708                                 stats->rx_dropped++;
1709                                 goto find_next_rx;
1710                         }
1711
1712                         skb->ip_summed = r8152_rx_csum(tp, rx_desc);
1713                         memcpy(skb->data, rx_data, pkt_len);
1714                         skb_put(skb, pkt_len);
1715                         skb->protocol = eth_type_trans(skb, netdev);
1716                         rtl_rx_vlan_tag(rx_desc, skb);
1717                         netif_receive_skb(skb);
1718                         stats->rx_packets++;
1719                         stats->rx_bytes += pkt_len;
1720
1721 find_next_rx:
1722                         rx_data = rx_agg_align(rx_data + pkt_len + CRC_SIZE);
1723                         rx_desc = (struct rx_desc *)rx_data;
1724                         len_used = (int)(rx_data - (u8 *)agg->head);
1725                         len_used += sizeof(struct rx_desc);
1726                 }
1727
1728 submit:
1729                 ret = r8152_submit_rx(tp, agg, GFP_ATOMIC);
1730                 if (ret && ret != -ENODEV) {
1731                         spin_lock_irqsave(&tp->rx_lock, flags);
1732                         list_add_tail(&agg->list, &tp->rx_done);
1733                         spin_unlock_irqrestore(&tp->rx_lock, flags);
1734                         tasklet_schedule(&tp->tl);
1735                 }
1736         }
1737 }
1738
1739 static void tx_bottom(struct r8152 *tp)
1740 {
1741         int res;
1742
1743         do {
1744                 struct tx_agg *agg;
1745
1746                 if (skb_queue_empty(&tp->tx_queue))
1747                         break;
1748
1749                 agg = r8152_get_tx_agg(tp);
1750                 if (!agg)
1751                         break;
1752
1753                 res = r8152_tx_agg_fill(tp, agg);
1754                 if (res) {
1755                         struct net_device *netdev = tp->netdev;
1756
1757                         if (res == -ENODEV) {
1758                                 netif_device_detach(netdev);
1759                         } else {
1760                                 struct net_device_stats *stats = &netdev->stats;
1761                                 unsigned long flags;
1762
1763                                 netif_warn(tp, tx_err, netdev,
1764                                            "failed tx_urb %d\n", res);
1765                                 stats->tx_dropped += agg->skb_num;
1766
1767                                 spin_lock_irqsave(&tp->tx_lock, flags);
1768                                 list_add_tail(&agg->list, &tp->tx_free);
1769                                 spin_unlock_irqrestore(&tp->tx_lock, flags);
1770                         }
1771                 }
1772         } while (res == 0);
1773 }
1774
1775 static void bottom_half(unsigned long data)
1776 {
1777         struct r8152 *tp;
1778
1779         tp = (struct r8152 *)data;
1780
1781         if (test_bit(RTL8152_UNPLUG, &tp->flags))
1782                 return;
1783
1784         if (!test_bit(WORK_ENABLE, &tp->flags))
1785                 return;
1786
1787         /* When link down, the driver would cancel all bulks. */
1788         /* This avoid the re-submitting bulk */
1789         if (!netif_carrier_ok(tp->netdev))
1790                 return;
1791
1792         rx_bottom(tp);
1793         tx_bottom(tp);
1794 }
1795
1796 static
1797 int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags)
1798 {
1799         usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1),
1800                           agg->head, agg_buf_sz,
1801                           (usb_complete_t)read_bulk_callback, agg);
1802
1803         return usb_submit_urb(agg->urb, mem_flags);
1804 }
1805
1806 static void rtl_drop_queued_tx(struct r8152 *tp)
1807 {
1808         struct net_device_stats *stats = &tp->netdev->stats;
1809         struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
1810         struct sk_buff *skb;
1811
1812         if (skb_queue_empty(tx_queue))
1813                 return;
1814
1815         __skb_queue_head_init(&skb_head);
1816         spin_lock_bh(&tx_queue->lock);
1817         skb_queue_splice_init(tx_queue, &skb_head);
1818         spin_unlock_bh(&tx_queue->lock);
1819
1820         while ((skb = __skb_dequeue(&skb_head))) {
1821                 dev_kfree_skb(skb);
1822                 stats->tx_dropped++;
1823         }
1824 }
1825
1826 static void rtl8152_tx_timeout(struct net_device *netdev)
1827 {
1828         struct r8152 *tp = netdev_priv(netdev);
1829         int i;
1830
1831         netif_warn(tp, tx_err, netdev, "Tx timeout\n");
1832         for (i = 0; i < RTL8152_MAX_TX; i++)
1833                 usb_unlink_urb(tp->tx_info[i].urb);
1834 }
1835
1836 static void rtl8152_set_rx_mode(struct net_device *netdev)
1837 {
1838         struct r8152 *tp = netdev_priv(netdev);
1839
1840         if (tp->speed & LINK_STATUS) {
1841                 set_bit(RTL8152_SET_RX_MODE, &tp->flags);
1842                 schedule_delayed_work(&tp->schedule, 0);
1843         }
1844 }
1845
1846 static void _rtl8152_set_rx_mode(struct net_device *netdev)
1847 {
1848         struct r8152 *tp = netdev_priv(netdev);
1849         u32 mc_filter[2];       /* Multicast hash filter */
1850         __le32 tmp[2];
1851         u32 ocp_data;
1852
1853         clear_bit(RTL8152_SET_RX_MODE, &tp->flags);
1854         netif_stop_queue(netdev);
1855         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
1856         ocp_data &= ~RCR_ACPT_ALL;
1857         ocp_data |= RCR_AB | RCR_APM;
1858
1859         if (netdev->flags & IFF_PROMISC) {
1860                 /* Unconditionally log net taps. */
1861                 netif_notice(tp, link, netdev, "Promiscuous mode enabled\n");
1862                 ocp_data |= RCR_AM | RCR_AAP;
1863                 mc_filter[1] = 0xffffffff;
1864                 mc_filter[0] = 0xffffffff;
1865         } else if ((netdev_mc_count(netdev) > multicast_filter_limit) ||
1866                    (netdev->flags & IFF_ALLMULTI)) {
1867                 /* Too many to filter perfectly -- accept all multicasts. */
1868                 ocp_data |= RCR_AM;
1869                 mc_filter[1] = 0xffffffff;
1870                 mc_filter[0] = 0xffffffff;
1871         } else {
1872                 struct netdev_hw_addr *ha;
1873
1874                 mc_filter[1] = 0;
1875                 mc_filter[0] = 0;
1876                 netdev_for_each_mc_addr(ha, netdev) {
1877                         int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
1878
1879                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
1880                         ocp_data |= RCR_AM;
1881                 }
1882         }
1883
1884         tmp[0] = __cpu_to_le32(swab32(mc_filter[1]));
1885         tmp[1] = __cpu_to_le32(swab32(mc_filter[0]));
1886
1887         pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp);
1888         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
1889         netif_wake_queue(netdev);
1890 }
1891
1892 static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb,
1893                                       struct net_device *netdev)
1894 {
1895         struct r8152 *tp = netdev_priv(netdev);
1896
1897         skb_tx_timestamp(skb);
1898
1899         skb_queue_tail(&tp->tx_queue, skb);
1900
1901         if (!list_empty(&tp->tx_free)) {
1902                 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
1903                         set_bit(SCHEDULE_TASKLET, &tp->flags);
1904                         schedule_delayed_work(&tp->schedule, 0);
1905                 } else {
1906                         usb_mark_last_busy(tp->udev);
1907                         tasklet_schedule(&tp->tl);
1908                 }
1909         } else if (skb_queue_len(&tp->tx_queue) > tp->tx_qlen) {
1910                 netif_stop_queue(netdev);
1911         }
1912
1913         return NETDEV_TX_OK;
1914 }
1915
1916 static void r8152b_reset_packet_filter(struct r8152 *tp)
1917 {
1918         u32     ocp_data;
1919
1920         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC);
1921         ocp_data &= ~FMC_FCR_MCU_EN;
1922         ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
1923         ocp_data |= FMC_FCR_MCU_EN;
1924         ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
1925 }
1926
1927 static void rtl8152_nic_reset(struct r8152 *tp)
1928 {
1929         int     i;
1930
1931         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST);
1932
1933         for (i = 0; i < 1000; i++) {
1934                 if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST))
1935                         break;
1936                 usleep_range(100, 400);
1937         }
1938 }
1939
1940 static void set_tx_qlen(struct r8152 *tp)
1941 {
1942         struct net_device *netdev = tp->netdev;
1943
1944         tp->tx_qlen = agg_buf_sz / (netdev->mtu + VLAN_ETH_HLEN + VLAN_HLEN +
1945                                     sizeof(struct tx_desc));
1946 }
1947
1948 static inline u8 rtl8152_get_speed(struct r8152 *tp)
1949 {
1950         return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS);
1951 }
1952
1953 static void rtl_set_eee_plus(struct r8152 *tp)
1954 {
1955         u32 ocp_data;
1956         u8 speed;
1957
1958         speed = rtl8152_get_speed(tp);
1959         if (speed & _10bps) {
1960                 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
1961                 ocp_data |= EEEP_CR_EEEP_TX;
1962                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
1963         } else {
1964                 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
1965                 ocp_data &= ~EEEP_CR_EEEP_TX;
1966                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
1967         }
1968 }
1969
1970 static void rxdy_gated_en(struct r8152 *tp, bool enable)
1971 {
1972         u32 ocp_data;
1973
1974         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
1975         if (enable)
1976                 ocp_data |= RXDY_GATED_EN;
1977         else
1978                 ocp_data &= ~RXDY_GATED_EN;
1979         ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
1980 }
1981
1982 static int rtl_start_rx(struct r8152 *tp)
1983 {
1984         int i, ret = 0;
1985
1986         INIT_LIST_HEAD(&tp->rx_done);
1987         for (i = 0; i < RTL8152_MAX_RX; i++) {
1988                 INIT_LIST_HEAD(&tp->rx_info[i].list);
1989                 ret = r8152_submit_rx(tp, &tp->rx_info[i], GFP_KERNEL);
1990                 if (ret)
1991                         break;
1992         }
1993
1994         return ret;
1995 }
1996
1997 static int rtl_stop_rx(struct r8152 *tp)
1998 {
1999         int i;
2000
2001         for (i = 0; i < RTL8152_MAX_RX; i++)
2002                 usb_kill_urb(tp->rx_info[i].urb);
2003
2004         return 0;
2005 }
2006
2007 static int rtl_enable(struct r8152 *tp)
2008 {
2009         u32 ocp_data;
2010
2011         r8152b_reset_packet_filter(tp);
2012
2013         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
2014         ocp_data |= CR_RE | CR_TE;
2015         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
2016
2017         rxdy_gated_en(tp, false);
2018
2019         return rtl_start_rx(tp);
2020 }
2021
2022 static int rtl8152_enable(struct r8152 *tp)
2023 {
2024         if (test_bit(RTL8152_UNPLUG, &tp->flags))
2025                 return -ENODEV;
2026
2027         set_tx_qlen(tp);
2028         rtl_set_eee_plus(tp);
2029
2030         return rtl_enable(tp);
2031 }
2032
2033 static void r8153_set_rx_agg(struct r8152 *tp)
2034 {
2035         u8 speed;
2036
2037         speed = rtl8152_get_speed(tp);
2038         if (speed & _1000bps) {
2039                 if (tp->udev->speed == USB_SPEED_SUPER) {
2040                         ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH,
2041                                         RX_THR_SUPPER);
2042                         ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_EARLY_AGG,
2043                                         EARLY_AGG_SUPPER);
2044                 } else {
2045                         ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH,
2046                                         RX_THR_HIGH);
2047                         ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_EARLY_AGG,
2048                                         EARLY_AGG_HIGH);
2049                 }
2050         } else {
2051                 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_SLOW);
2052                 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_EARLY_AGG,
2053                                 EARLY_AGG_SLOW);
2054         }
2055 }
2056
2057 static int rtl8153_enable(struct r8152 *tp)
2058 {
2059         if (test_bit(RTL8152_UNPLUG, &tp->flags))
2060                 return -ENODEV;
2061
2062         set_tx_qlen(tp);
2063         rtl_set_eee_plus(tp);
2064         r8153_set_rx_agg(tp);
2065
2066         return rtl_enable(tp);
2067 }
2068
2069 static void rtl_disable(struct r8152 *tp)
2070 {
2071         u32 ocp_data;
2072         int i;
2073
2074         if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
2075                 rtl_drop_queued_tx(tp);
2076                 return;
2077         }
2078
2079         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2080         ocp_data &= ~RCR_ACPT_ALL;
2081         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2082
2083         rtl_drop_queued_tx(tp);
2084
2085         for (i = 0; i < RTL8152_MAX_TX; i++)
2086                 usb_kill_urb(tp->tx_info[i].urb);
2087
2088         rxdy_gated_en(tp, true);
2089
2090         for (i = 0; i < 1000; i++) {
2091                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2092                 if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY)
2093                         break;
2094                 usleep_range(1000, 2000);
2095         }
2096
2097         for (i = 0; i < 1000; i++) {
2098                 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY)
2099                         break;
2100                 usleep_range(1000, 2000);
2101         }
2102
2103         rtl_stop_rx(tp);
2104
2105         rtl8152_nic_reset(tp);
2106 }
2107
2108 static void r8152_power_cut_en(struct r8152 *tp, bool enable)
2109 {
2110         u32 ocp_data;
2111
2112         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
2113         if (enable)
2114                 ocp_data |= POWER_CUT;
2115         else
2116                 ocp_data &= ~POWER_CUT;
2117         ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
2118
2119         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
2120         ocp_data &= ~RESUME_INDICATE;
2121         ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
2122 }
2123
2124 static void rtl_rx_vlan_en(struct r8152 *tp, bool enable)
2125 {
2126         u32 ocp_data;
2127
2128         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
2129         if (enable)
2130                 ocp_data |= CPCR_RX_VLAN;
2131         else
2132                 ocp_data &= ~CPCR_RX_VLAN;
2133         ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
2134 }
2135
2136 static int rtl8152_set_features(struct net_device *dev,
2137                                 netdev_features_t features)
2138 {
2139         netdev_features_t changed = features ^ dev->features;
2140         struct r8152 *tp = netdev_priv(dev);
2141
2142         if (changed & NETIF_F_HW_VLAN_CTAG_RX) {
2143                 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2144                         rtl_rx_vlan_en(tp, true);
2145                 else
2146                         rtl_rx_vlan_en(tp, false);
2147         }
2148
2149         return 0;
2150 }
2151
2152 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
2153
2154 static u32 __rtl_get_wol(struct r8152 *tp)
2155 {
2156         u32 ocp_data;
2157         u32 wolopts = 0;
2158
2159         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2160         if (!(ocp_data & LAN_WAKE_EN))
2161                 return 0;
2162
2163         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2164         if (ocp_data & LINK_ON_WAKE_EN)
2165                 wolopts |= WAKE_PHY;
2166
2167         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2168         if (ocp_data & UWF_EN)
2169                 wolopts |= WAKE_UCAST;
2170         if (ocp_data & BWF_EN)
2171                 wolopts |= WAKE_BCAST;
2172         if (ocp_data & MWF_EN)
2173                 wolopts |= WAKE_MCAST;
2174
2175         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
2176         if (ocp_data & MAGIC_EN)
2177                 wolopts |= WAKE_MAGIC;
2178
2179         return wolopts;
2180 }
2181
2182 static void __rtl_set_wol(struct r8152 *tp, u32 wolopts)
2183 {
2184         u32 ocp_data;
2185
2186         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
2187
2188         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2189         ocp_data &= ~LINK_ON_WAKE_EN;
2190         if (wolopts & WAKE_PHY)
2191                 ocp_data |= LINK_ON_WAKE_EN;
2192         ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
2193
2194         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2195         ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN | LAN_WAKE_EN);
2196         if (wolopts & WAKE_UCAST)
2197                 ocp_data |= UWF_EN;
2198         if (wolopts & WAKE_BCAST)
2199                 ocp_data |= BWF_EN;
2200         if (wolopts & WAKE_MCAST)
2201                 ocp_data |= MWF_EN;
2202         if (wolopts & WAKE_ANY)
2203                 ocp_data |= LAN_WAKE_EN;
2204         ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data);
2205
2206         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2207
2208         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
2209         ocp_data &= ~MAGIC_EN;
2210         if (wolopts & WAKE_MAGIC)
2211                 ocp_data |= MAGIC_EN;
2212         ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data);
2213
2214         if (wolopts & WAKE_ANY)
2215                 device_set_wakeup_enable(&tp->udev->dev, true);
2216         else
2217                 device_set_wakeup_enable(&tp->udev->dev, false);
2218 }
2219
2220 static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable)
2221 {
2222         if (enable) {
2223                 u32 ocp_data;
2224
2225                 __rtl_set_wol(tp, WAKE_ANY);
2226
2227                 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
2228
2229                 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2230                 ocp_data |= LINK_OFF_WAKE_EN;
2231                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
2232
2233                 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2234         } else {
2235                 __rtl_set_wol(tp, tp->saved_wolopts);
2236         }
2237 }
2238
2239 static void rtl_phy_reset(struct r8152 *tp)
2240 {
2241         u16 data;
2242         int i;
2243
2244         clear_bit(PHY_RESET, &tp->flags);
2245
2246         data = r8152_mdio_read(tp, MII_BMCR);
2247
2248         /* don't reset again before the previous one complete */
2249         if (data & BMCR_RESET)
2250                 return;
2251
2252         data |= BMCR_RESET;
2253         r8152_mdio_write(tp, MII_BMCR, data);
2254
2255         for (i = 0; i < 50; i++) {
2256                 msleep(20);
2257                 if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0)
2258                         break;
2259         }
2260 }
2261
2262 static void r8153_teredo_off(struct r8152 *tp)
2263 {
2264         u32 ocp_data;
2265
2266         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
2267         ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK | OOB_TEREDO_EN);
2268         ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
2269
2270         ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE);
2271         ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0);
2272         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0);
2273 }
2274
2275 static void r8152b_disable_aldps(struct r8152 *tp)
2276 {
2277         ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA | DIS_SDSAVE);
2278         msleep(20);
2279 }
2280
2281 static inline void r8152b_enable_aldps(struct r8152 *tp)
2282 {
2283         ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS |
2284                                             LINKENA | DIS_SDSAVE);
2285 }
2286
2287 static void rtl8152_disable(struct r8152 *tp)
2288 {
2289         r8152b_disable_aldps(tp);
2290         rtl_disable(tp);
2291         r8152b_enable_aldps(tp);
2292 }
2293
2294 static void r8152b_hw_phy_cfg(struct r8152 *tp)
2295 {
2296         u16 data;
2297
2298         data = r8152_mdio_read(tp, MII_BMCR);
2299         if (data & BMCR_PDOWN) {
2300                 data &= ~BMCR_PDOWN;
2301                 r8152_mdio_write(tp, MII_BMCR, data);
2302         }
2303
2304         set_bit(PHY_RESET, &tp->flags);
2305 }
2306
2307 static void r8152b_exit_oob(struct r8152 *tp)
2308 {
2309         u32 ocp_data;
2310         int i;
2311
2312         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2313         ocp_data &= ~RCR_ACPT_ALL;
2314         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2315
2316         rxdy_gated_en(tp, true);
2317         r8153_teredo_off(tp);
2318         r8152b_hw_phy_cfg(tp);
2319
2320         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2321         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00);
2322
2323         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2324         ocp_data &= ~NOW_IS_OOB;
2325         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2326
2327         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2328         ocp_data &= ~MCU_BORW_EN;
2329         ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2330
2331         for (i = 0; i < 1000; i++) {
2332                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2333                 if (ocp_data & LINK_LIST_READY)
2334                         break;
2335                 usleep_range(1000, 2000);
2336         }
2337
2338         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2339         ocp_data |= RE_INIT_LL;
2340         ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2341
2342         for (i = 0; i < 1000; i++) {
2343                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2344                 if (ocp_data & LINK_LIST_READY)
2345                         break;
2346                 usleep_range(1000, 2000);
2347         }
2348
2349         rtl8152_nic_reset(tp);
2350
2351         /* rx share fifo credit full threshold */
2352         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
2353
2354         if (tp->udev->speed == USB_SPEED_FULL ||
2355             tp->udev->speed == USB_SPEED_LOW) {
2356                 /* rx share fifo credit near full threshold */
2357                 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
2358                                 RXFIFO_THR2_FULL);
2359                 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
2360                                 RXFIFO_THR3_FULL);
2361         } else {
2362                 /* rx share fifo credit near full threshold */
2363                 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
2364                                 RXFIFO_THR2_HIGH);
2365                 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
2366                                 RXFIFO_THR3_HIGH);
2367         }
2368
2369         /* TX share fifo free credit full threshold */
2370         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL);
2371
2372         ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD);
2373         ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH);
2374         ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA,
2375                         TEST_MODE_DISABLE | TX_SIZE_ADJUST1);
2376
2377         rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
2378
2379         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
2380
2381         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
2382         ocp_data |= TCR0_AUTO_FIFO;
2383         ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
2384 }
2385
2386 static void r8152b_enter_oob(struct r8152 *tp)
2387 {
2388         u32 ocp_data;
2389         int i;
2390
2391         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2392         ocp_data &= ~NOW_IS_OOB;
2393         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2394
2395         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
2396         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);
2397         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);
2398
2399         rtl_disable(tp);
2400
2401         for (i = 0; i < 1000; i++) {
2402                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2403                 if (ocp_data & LINK_LIST_READY)
2404                         break;
2405                 usleep_range(1000, 2000);
2406         }
2407
2408         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2409         ocp_data |= RE_INIT_LL;
2410         ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2411
2412         for (i = 0; i < 1000; i++) {
2413                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2414                 if (ocp_data & LINK_LIST_READY)
2415                         break;
2416                 usleep_range(1000, 2000);
2417         }
2418
2419         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
2420
2421         rtl_rx_vlan_en(tp, true);
2422
2423         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
2424         ocp_data |= ALDPS_PROXY_MODE;
2425         ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
2426
2427         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2428         ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
2429         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2430
2431         rxdy_gated_en(tp, false);
2432
2433         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2434         ocp_data |= RCR_APM | RCR_AM | RCR_AB;
2435         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2436 }
2437
2438 static void r8153_hw_phy_cfg(struct r8152 *tp)
2439 {
2440         u32 ocp_data;
2441         u16 data;
2442
2443         ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L);
2444         data = r8152_mdio_read(tp, MII_BMCR);
2445         if (data & BMCR_PDOWN) {
2446                 data &= ~BMCR_PDOWN;
2447                 r8152_mdio_write(tp, MII_BMCR, data);
2448         }
2449
2450         if (tp->version == RTL_VER_03) {
2451                 data = ocp_reg_read(tp, OCP_EEE_CFG);
2452                 data &= ~CTAP_SHORT_EN;
2453                 ocp_reg_write(tp, OCP_EEE_CFG, data);
2454         }
2455
2456         data = ocp_reg_read(tp, OCP_POWER_CFG);
2457         data |= EEE_CLKDIV_EN;
2458         ocp_reg_write(tp, OCP_POWER_CFG, data);
2459
2460         data = ocp_reg_read(tp, OCP_DOWN_SPEED);
2461         data |= EN_10M_BGOFF;
2462         ocp_reg_write(tp, OCP_DOWN_SPEED, data);
2463         data = ocp_reg_read(tp, OCP_POWER_CFG);
2464         data |= EN_10M_PLLOFF;
2465         ocp_reg_write(tp, OCP_POWER_CFG, data);
2466         data = sram_read(tp, SRAM_IMPEDANCE);
2467         data &= ~RX_DRIVING_MASK;
2468         sram_write(tp, SRAM_IMPEDANCE, data);
2469
2470         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
2471         ocp_data |= PFM_PWM_SWITCH;
2472         ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
2473
2474         data = sram_read(tp, SRAM_LPF_CFG);
2475         data |= LPF_AUTO_TUNE;
2476         sram_write(tp, SRAM_LPF_CFG, data);
2477
2478         data = sram_read(tp, SRAM_10M_AMP1);
2479         data |= GDAC_IB_UPALL;
2480         sram_write(tp, SRAM_10M_AMP1, data);
2481         data = sram_read(tp, SRAM_10M_AMP2);
2482         data |= AMP_DN;
2483         sram_write(tp, SRAM_10M_AMP2, data);
2484
2485         set_bit(PHY_RESET, &tp->flags);
2486 }
2487
2488 static void r8153_u1u2en(struct r8152 *tp, bool enable)
2489 {
2490         u8 u1u2[8];
2491
2492         if (enable)
2493                 memset(u1u2, 0xff, sizeof(u1u2));
2494         else
2495                 memset(u1u2, 0x00, sizeof(u1u2));
2496
2497         usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2);
2498 }
2499
2500 static void r8153_u2p3en(struct r8152 *tp, bool enable)
2501 {
2502         u32 ocp_data;
2503
2504         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);
2505         if (enable)
2506                 ocp_data |= U2P3_ENABLE;
2507         else
2508                 ocp_data &= ~U2P3_ENABLE;
2509         ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data);
2510 }
2511
2512 static void r8153_power_cut_en(struct r8152 *tp, bool enable)
2513 {
2514         u32 ocp_data;
2515
2516         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
2517         if (enable)
2518                 ocp_data |= PWR_EN | PHASE2_EN;
2519         else
2520                 ocp_data &= ~(PWR_EN | PHASE2_EN);
2521         ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
2522
2523         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
2524         ocp_data &= ~PCUT_STATUS;
2525         ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
2526 }
2527
2528 static void r8153_first_init(struct r8152 *tp)
2529 {
2530         u32 ocp_data;
2531         int i;
2532
2533         rxdy_gated_en(tp, true);
2534         r8153_teredo_off(tp);
2535
2536         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2537         ocp_data &= ~RCR_ACPT_ALL;
2538         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2539
2540         r8153_hw_phy_cfg(tp);
2541
2542         rtl8152_nic_reset(tp);
2543
2544         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2545         ocp_data &= ~NOW_IS_OOB;
2546         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2547
2548         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2549         ocp_data &= ~MCU_BORW_EN;
2550         ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2551
2552         for (i = 0; i < 1000; i++) {
2553                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2554                 if (ocp_data & LINK_LIST_READY)
2555                         break;
2556                 usleep_range(1000, 2000);
2557         }
2558
2559         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2560         ocp_data |= RE_INIT_LL;
2561         ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2562
2563         for (i = 0; i < 1000; i++) {
2564                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2565                 if (ocp_data & LINK_LIST_READY)
2566                         break;
2567                 usleep_range(1000, 2000);
2568         }
2569
2570         rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
2571
2572         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8153_RMS);
2573         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO);
2574
2575         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
2576         ocp_data |= TCR0_AUTO_FIFO;
2577         ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
2578
2579         rtl8152_nic_reset(tp);
2580
2581         /* rx share fifo credit full threshold */
2582         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
2583         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL);
2584         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL);
2585         /* TX share fifo free credit full threshold */
2586         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2);
2587
2588         /* rx aggregation */
2589         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
2590         ocp_data &= ~RX_AGG_DISABLE;
2591         ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
2592 }
2593
2594 static void r8153_enter_oob(struct r8152 *tp)
2595 {
2596         u32 ocp_data;
2597         int i;
2598
2599         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2600         ocp_data &= ~NOW_IS_OOB;
2601         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2602
2603         rtl_disable(tp);
2604
2605         for (i = 0; i < 1000; i++) {
2606                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2607                 if (ocp_data & LINK_LIST_READY)
2608                         break;
2609                 usleep_range(1000, 2000);
2610         }
2611
2612         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2613         ocp_data |= RE_INIT_LL;
2614         ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2615
2616         for (i = 0; i < 1000; i++) {
2617                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2618                 if (ocp_data & LINK_LIST_READY)
2619                         break;
2620                 usleep_range(1000, 2000);
2621         }
2622
2623         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8153_RMS);
2624
2625         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
2626         ocp_data &= ~TEREDO_WAKE_MASK;
2627         ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
2628
2629         rtl_rx_vlan_en(tp, true);
2630
2631         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
2632         ocp_data |= ALDPS_PROXY_MODE;
2633         ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
2634
2635         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2636         ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
2637         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2638
2639         rxdy_gated_en(tp, false);
2640
2641         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2642         ocp_data |= RCR_APM | RCR_AM | RCR_AB;
2643         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2644 }
2645
2646 static void r8153_disable_aldps(struct r8152 *tp)
2647 {
2648         u16 data;
2649
2650         data = ocp_reg_read(tp, OCP_POWER_CFG);
2651         data &= ~EN_ALDPS;
2652         ocp_reg_write(tp, OCP_POWER_CFG, data);
2653         msleep(20);
2654 }
2655
2656 static void r8153_enable_aldps(struct r8152 *tp)
2657 {
2658         u16 data;
2659
2660         data = ocp_reg_read(tp, OCP_POWER_CFG);
2661         data |= EN_ALDPS;
2662         ocp_reg_write(tp, OCP_POWER_CFG, data);
2663 }
2664
2665 static void rtl8153_disable(struct r8152 *tp)
2666 {
2667         r8153_disable_aldps(tp);
2668         rtl_disable(tp);
2669         r8153_enable_aldps(tp);
2670 }
2671
2672 static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex)
2673 {
2674         u16 bmcr, anar, gbcr;
2675         int ret = 0;
2676
2677         cancel_delayed_work_sync(&tp->schedule);
2678         anar = r8152_mdio_read(tp, MII_ADVERTISE);
2679         anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
2680                   ADVERTISE_100HALF | ADVERTISE_100FULL);
2681         if (tp->mii.supports_gmii) {
2682                 gbcr = r8152_mdio_read(tp, MII_CTRL1000);
2683                 gbcr &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
2684         } else {
2685                 gbcr = 0;
2686         }
2687
2688         if (autoneg == AUTONEG_DISABLE) {
2689                 if (speed == SPEED_10) {
2690                         bmcr = 0;
2691                         anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
2692                 } else if (speed == SPEED_100) {
2693                         bmcr = BMCR_SPEED100;
2694                         anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
2695                 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) {
2696                         bmcr = BMCR_SPEED1000;
2697                         gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
2698                 } else {
2699                         ret = -EINVAL;
2700                         goto out;
2701                 }
2702
2703                 if (duplex == DUPLEX_FULL)
2704                         bmcr |= BMCR_FULLDPLX;
2705         } else {
2706                 if (speed == SPEED_10) {
2707                         if (duplex == DUPLEX_FULL)
2708                                 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
2709                         else
2710                                 anar |= ADVERTISE_10HALF;
2711                 } else if (speed == SPEED_100) {
2712                         if (duplex == DUPLEX_FULL) {
2713                                 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
2714                                 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
2715                         } else {
2716                                 anar |= ADVERTISE_10HALF;
2717                                 anar |= ADVERTISE_100HALF;
2718                         }
2719                 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) {
2720                         if (duplex == DUPLEX_FULL) {
2721                                 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
2722                                 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
2723                                 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
2724                         } else {
2725                                 anar |= ADVERTISE_10HALF;
2726                                 anar |= ADVERTISE_100HALF;
2727                                 gbcr |= ADVERTISE_1000HALF;
2728                         }
2729                 } else {
2730                         ret = -EINVAL;
2731                         goto out;
2732                 }
2733
2734                 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
2735         }
2736
2737         if (test_bit(PHY_RESET, &tp->flags))
2738                 bmcr |= BMCR_RESET;
2739
2740         if (tp->mii.supports_gmii)
2741                 r8152_mdio_write(tp, MII_CTRL1000, gbcr);
2742
2743         r8152_mdio_write(tp, MII_ADVERTISE, anar);
2744         r8152_mdio_write(tp, MII_BMCR, bmcr);
2745
2746         if (test_bit(PHY_RESET, &tp->flags)) {
2747                 int i;
2748
2749                 clear_bit(PHY_RESET, &tp->flags);
2750                 for (i = 0; i < 50; i++) {
2751                         msleep(20);
2752                         if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0)
2753                                 break;
2754                 }
2755         }
2756
2757 out:
2758
2759         return ret;
2760 }
2761
2762 static void rtl8152_up(struct r8152 *tp)
2763 {
2764         if (test_bit(RTL8152_UNPLUG, &tp->flags))
2765                 return;
2766
2767         r8152b_disable_aldps(tp);
2768         r8152b_exit_oob(tp);
2769         r8152b_enable_aldps(tp);
2770 }
2771
2772 static void rtl8152_down(struct r8152 *tp)
2773 {
2774         if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
2775                 rtl_drop_queued_tx(tp);
2776                 return;
2777         }
2778
2779         r8152_power_cut_en(tp, false);
2780         r8152b_disable_aldps(tp);
2781         r8152b_enter_oob(tp);
2782         r8152b_enable_aldps(tp);
2783 }
2784
2785 static void rtl8153_up(struct r8152 *tp)
2786 {
2787         if (test_bit(RTL8152_UNPLUG, &tp->flags))
2788                 return;
2789
2790         r8153_disable_aldps(tp);
2791         r8153_first_init(tp);
2792         r8153_enable_aldps(tp);
2793 }
2794
2795 static void rtl8153_down(struct r8152 *tp)
2796 {
2797         if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
2798                 rtl_drop_queued_tx(tp);
2799                 return;
2800         }
2801
2802         r8153_u1u2en(tp, false);
2803         r8153_power_cut_en(tp, false);
2804         r8153_disable_aldps(tp);
2805         r8153_enter_oob(tp);
2806         r8153_enable_aldps(tp);
2807 }
2808
2809 static void set_carrier(struct r8152 *tp)
2810 {
2811         struct net_device *netdev = tp->netdev;
2812         u8 speed;
2813
2814         clear_bit(RTL8152_LINK_CHG, &tp->flags);
2815         speed = rtl8152_get_speed(tp);
2816
2817         if (speed & LINK_STATUS) {
2818                 if (!(tp->speed & LINK_STATUS)) {
2819                         tp->rtl_ops.enable(tp);
2820                         set_bit(RTL8152_SET_RX_MODE, &tp->flags);
2821                         netif_carrier_on(netdev);
2822                 }
2823         } else {
2824                 if (tp->speed & LINK_STATUS) {
2825                         netif_carrier_off(netdev);
2826                         tasklet_disable(&tp->tl);
2827                         tp->rtl_ops.disable(tp);
2828                         tasklet_enable(&tp->tl);
2829                 }
2830         }
2831         tp->speed = speed;
2832 }
2833
2834 static void rtl_work_func_t(struct work_struct *work)
2835 {
2836         struct r8152 *tp = container_of(work, struct r8152, schedule.work);
2837
2838         if (usb_autopm_get_interface(tp->intf) < 0)
2839                 return;
2840
2841         if (!test_bit(WORK_ENABLE, &tp->flags))
2842                 goto out1;
2843
2844         if (test_bit(RTL8152_UNPLUG, &tp->flags))
2845                 goto out1;
2846
2847         if (test_bit(RTL8152_LINK_CHG, &tp->flags))
2848                 set_carrier(tp);
2849
2850         if (test_bit(RTL8152_SET_RX_MODE, &tp->flags))
2851                 _rtl8152_set_rx_mode(tp->netdev);
2852
2853         if (test_bit(SCHEDULE_TASKLET, &tp->flags) &&
2854             (tp->speed & LINK_STATUS)) {
2855                 clear_bit(SCHEDULE_TASKLET, &tp->flags);
2856                 tasklet_schedule(&tp->tl);
2857         }
2858
2859         if (test_bit(PHY_RESET, &tp->flags))
2860                 rtl_phy_reset(tp);
2861
2862 out1:
2863         usb_autopm_put_interface(tp->intf);
2864 }
2865
2866 static int rtl8152_open(struct net_device *netdev)
2867 {
2868         struct r8152 *tp = netdev_priv(netdev);
2869         int res = 0;
2870
2871         res = alloc_all_mem(tp);
2872         if (res)
2873                 goto out;
2874
2875         res = usb_autopm_get_interface(tp->intf);
2876         if (res < 0) {
2877                 free_all_mem(tp);
2878                 goto out;
2879         }
2880
2881         /* The WORK_ENABLE may be set when autoresume occurs */
2882         if (test_bit(WORK_ENABLE, &tp->flags)) {
2883                 clear_bit(WORK_ENABLE, &tp->flags);
2884                 usb_kill_urb(tp->intr_urb);
2885                 cancel_delayed_work_sync(&tp->schedule);
2886                 if (tp->speed & LINK_STATUS)
2887                         tp->rtl_ops.disable(tp);
2888         }
2889
2890         tp->rtl_ops.up(tp);
2891
2892         rtl8152_set_speed(tp, AUTONEG_ENABLE,
2893                           tp->mii.supports_gmii ? SPEED_1000 : SPEED_100,
2894                           DUPLEX_FULL);
2895         tp->speed = 0;
2896         netif_carrier_off(netdev);
2897         netif_start_queue(netdev);
2898         set_bit(WORK_ENABLE, &tp->flags);
2899
2900         res = usb_submit_urb(tp->intr_urb, GFP_KERNEL);
2901         if (res) {
2902                 if (res == -ENODEV)
2903                         netif_device_detach(tp->netdev);
2904                 netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n",
2905                            res);
2906                 free_all_mem(tp);
2907         }
2908
2909         usb_autopm_put_interface(tp->intf);
2910
2911 out:
2912         return res;
2913 }
2914
2915 static int rtl8152_close(struct net_device *netdev)
2916 {
2917         struct r8152 *tp = netdev_priv(netdev);
2918         int res = 0;
2919
2920         clear_bit(WORK_ENABLE, &tp->flags);
2921         usb_kill_urb(tp->intr_urb);
2922         cancel_delayed_work_sync(&tp->schedule);
2923         netif_stop_queue(netdev);
2924
2925         res = usb_autopm_get_interface(tp->intf);
2926         if (res < 0) {
2927                 rtl_drop_queued_tx(tp);
2928         } else {
2929                 /* The autosuspend may have been enabled and wouldn't
2930                  * be disable when autoresume occurs, because the
2931                  * netif_running() would be false.
2932                  */
2933                 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
2934                         rtl_runtime_suspend_enable(tp, false);
2935                         clear_bit(SELECTIVE_SUSPEND, &tp->flags);
2936                 }
2937
2938                 tasklet_disable(&tp->tl);
2939                 tp->rtl_ops.down(tp);
2940                 tasklet_enable(&tp->tl);
2941                 usb_autopm_put_interface(tp->intf);
2942         }
2943
2944         free_all_mem(tp);
2945
2946         return res;
2947 }
2948
2949 static inline void r8152_mmd_indirect(struct r8152 *tp, u16 dev, u16 reg)
2950 {
2951         ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | dev);
2952         ocp_reg_write(tp, OCP_EEE_DATA, reg);
2953         ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | dev);
2954 }
2955
2956 static u16 r8152_mmd_read(struct r8152 *tp, u16 dev, u16 reg)
2957 {
2958         u16 data;
2959
2960         r8152_mmd_indirect(tp, dev, reg);
2961         data = ocp_reg_read(tp, OCP_EEE_DATA);
2962         ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
2963
2964         return data;
2965 }
2966
2967 static void r8152_mmd_write(struct r8152 *tp, u16 dev, u16 reg, u16 data)
2968 {
2969         r8152_mmd_indirect(tp, dev, reg);
2970         ocp_reg_write(tp, OCP_EEE_DATA, data);
2971         ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
2972 }
2973
2974 static void r8152_eee_en(struct r8152 *tp, bool enable)
2975 {
2976         u16 config1, config2, config3;
2977         u32 ocp_data;
2978
2979         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
2980         config1 = ocp_reg_read(tp, OCP_EEE_CONFIG1) & ~sd_rise_time_mask;
2981         config2 = ocp_reg_read(tp, OCP_EEE_CONFIG2);
2982         config3 = ocp_reg_read(tp, OCP_EEE_CONFIG3) & ~fast_snr_mask;
2983
2984         if (enable) {
2985                 ocp_data |= EEE_RX_EN | EEE_TX_EN;
2986                 config1 |= EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | RX_QUIET_EN;
2987                 config1 |= sd_rise_time(1);
2988                 config2 |= RG_DACQUIET_EN | RG_LDVQUIET_EN;
2989                 config3 |= fast_snr(42);
2990         } else {
2991                 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
2992                 config1 &= ~(EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN |
2993                              RX_QUIET_EN);
2994                 config1 |= sd_rise_time(7);
2995                 config2 &= ~(RG_DACQUIET_EN | RG_LDVQUIET_EN);
2996                 config3 |= fast_snr(511);
2997         }
2998
2999         ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
3000         ocp_reg_write(tp, OCP_EEE_CONFIG1, config1);
3001         ocp_reg_write(tp, OCP_EEE_CONFIG2, config2);
3002         ocp_reg_write(tp, OCP_EEE_CONFIG3, config3);
3003 }
3004
3005 static void r8152b_enable_eee(struct r8152 *tp)
3006 {
3007         r8152_eee_en(tp, true);
3008         r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, MDIO_EEE_100TX);
3009 }
3010
3011 static void r8153_eee_en(struct r8152 *tp, bool enable)
3012 {
3013         u32 ocp_data;
3014         u16 config;
3015
3016         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
3017         config = ocp_reg_read(tp, OCP_EEE_CFG);
3018
3019         if (enable) {
3020                 ocp_data |= EEE_RX_EN | EEE_TX_EN;
3021                 config |= EEE10_EN;
3022         } else {
3023                 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
3024                 config &= ~EEE10_EN;
3025         }
3026
3027         ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
3028         ocp_reg_write(tp, OCP_EEE_CFG, config);
3029 }
3030
3031 static void r8153_enable_eee(struct r8152 *tp)
3032 {
3033         r8153_eee_en(tp, true);
3034         ocp_reg_write(tp, OCP_EEE_ADV, MDIO_EEE_1000T | MDIO_EEE_100TX);
3035 }
3036
3037 static void r8152b_enable_fc(struct r8152 *tp)
3038 {
3039         u16 anar;
3040
3041         anar = r8152_mdio_read(tp, MII_ADVERTISE);
3042         anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
3043         r8152_mdio_write(tp, MII_ADVERTISE, anar);
3044 }
3045
3046 static void rtl_tally_reset(struct r8152 *tp)
3047 {
3048         u32 ocp_data;
3049
3050         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY);
3051         ocp_data |= TALLY_RESET;
3052         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data);
3053 }
3054
3055 static void r8152b_init(struct r8152 *tp)
3056 {
3057         u32 ocp_data;
3058
3059         if (test_bit(RTL8152_UNPLUG, &tp->flags))
3060                 return;
3061
3062         r8152b_disable_aldps(tp);
3063
3064         if (tp->version == RTL_VER_01) {
3065                 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
3066                 ocp_data &= ~LED_MODE_MASK;
3067                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
3068         }
3069
3070         r8152_power_cut_en(tp, false);
3071
3072         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
3073         ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH;
3074         ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
3075         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL);
3076         ocp_data &= ~MCU_CLK_RATIO_MASK;
3077         ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN;
3078         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data);
3079         ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK |
3080                    SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK;
3081         ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data);
3082
3083         r8152b_enable_eee(tp);
3084         r8152b_enable_aldps(tp);
3085         r8152b_enable_fc(tp);
3086         rtl_tally_reset(tp);
3087
3088         /* enable rx aggregation */
3089         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
3090         ocp_data &= ~RX_AGG_DISABLE;
3091         ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
3092 }
3093
3094 static void r8153_init(struct r8152 *tp)
3095 {
3096         u32 ocp_data;
3097         int i;
3098
3099         if (test_bit(RTL8152_UNPLUG, &tp->flags))
3100                 return;
3101
3102         r8153_disable_aldps(tp);
3103         r8153_u1u2en(tp, false);
3104
3105         for (i = 0; i < 500; i++) {
3106                 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
3107                     AUTOLOAD_DONE)
3108                         break;
3109                 msleep(20);
3110         }
3111
3112         for (i = 0; i < 500; i++) {
3113                 ocp_data = ocp_reg_read(tp, OCP_PHY_STATUS) & PHY_STAT_MASK;
3114                 if (ocp_data == PHY_STAT_LAN_ON || ocp_data == PHY_STAT_PWRDN)
3115                         break;
3116                 msleep(20);
3117         }
3118
3119         r8153_u2p3en(tp, false);
3120
3121         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL);
3122         ocp_data &= ~TIMER11_EN;
3123         ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data);
3124
3125         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
3126         ocp_data &= ~LED_MODE_MASK;
3127         ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
3128
3129         ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL);
3130         ocp_data &= ~LPM_TIMER_MASK;
3131         if (tp->udev->speed == USB_SPEED_SUPER)
3132                 ocp_data |= LPM_TIMER_500US;
3133         else
3134                 ocp_data |= LPM_TIMER_500MS;
3135         ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data);
3136
3137         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2);
3138         ocp_data &= ~SEN_VAL_MASK;
3139         ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE;
3140         ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data);
3141
3142         r8153_power_cut_en(tp, false);
3143         r8153_u1u2en(tp, true);
3144
3145         ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ALDPS_SPDWN_RATIO);
3146         ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, EEE_SPDWN_RATIO);
3147         ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3,
3148                        PKT_AVAIL_SPDWN_EN | SUSPEND_SPDWN_EN |
3149                        U1U2_SPDWN_EN | L1_SPDWN_EN);
3150         ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4,
3151                        PWRSAVE_SPDWN_EN | RXDV_SPDWN_EN | TX10MIDLE_EN |
3152                        TP100_SPDWN_EN | TP500_SPDWN_EN | TP1000_SPDWN_EN |
3153                        EEE_SPDWN_EN);
3154
3155         r8153_enable_eee(tp);
3156         r8153_enable_aldps(tp);
3157         r8152b_enable_fc(tp);
3158         rtl_tally_reset(tp);
3159 }
3160
3161 static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message)
3162 {
3163         struct r8152 *tp = usb_get_intfdata(intf);
3164
3165         if (PMSG_IS_AUTO(message))
3166                 set_bit(SELECTIVE_SUSPEND, &tp->flags);
3167         else
3168                 netif_device_detach(tp->netdev);
3169
3170         if (netif_running(tp->netdev)) {
3171                 clear_bit(WORK_ENABLE, &tp->flags);
3172                 usb_kill_urb(tp->intr_urb);
3173                 cancel_delayed_work_sync(&tp->schedule);
3174                 tasklet_disable(&tp->tl);
3175                 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
3176                         rtl_stop_rx(tp);
3177                         rtl_runtime_suspend_enable(tp, true);
3178                 } else {
3179                         tp->rtl_ops.down(tp);
3180                 }
3181                 tasklet_enable(&tp->tl);
3182         }
3183
3184         return 0;
3185 }
3186
3187 static int rtl8152_resume(struct usb_interface *intf)
3188 {
3189         struct r8152 *tp = usb_get_intfdata(intf);
3190
3191         if (!test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
3192                 tp->rtl_ops.init(tp);
3193                 netif_device_attach(tp->netdev);
3194         }
3195
3196         if (netif_running(tp->netdev)) {
3197                 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
3198                         rtl_runtime_suspend_enable(tp, false);
3199                         clear_bit(SELECTIVE_SUSPEND, &tp->flags);
3200                         set_bit(WORK_ENABLE, &tp->flags);
3201                         if (tp->speed & LINK_STATUS)
3202                                 rtl_start_rx(tp);
3203                 } else {
3204                         tp->rtl_ops.up(tp);
3205                         rtl8152_set_speed(tp, AUTONEG_ENABLE,
3206                                           tp->mii.supports_gmii ?
3207                                           SPEED_1000 : SPEED_100,
3208                                           DUPLEX_FULL);
3209                         tp->speed = 0;
3210                         netif_carrier_off(tp->netdev);
3211                         set_bit(WORK_ENABLE, &tp->flags);
3212                 }
3213                 usb_submit_urb(tp->intr_urb, GFP_KERNEL);
3214         }
3215
3216         return 0;
3217 }
3218
3219 static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3220 {
3221         struct r8152 *tp = netdev_priv(dev);
3222
3223         if (usb_autopm_get_interface(tp->intf) < 0)
3224                 return;
3225
3226         wol->supported = WAKE_ANY;
3227         wol->wolopts = __rtl_get_wol(tp);
3228
3229         usb_autopm_put_interface(tp->intf);
3230 }
3231
3232 static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3233 {
3234         struct r8152 *tp = netdev_priv(dev);
3235         int ret;
3236
3237         ret = usb_autopm_get_interface(tp->intf);
3238         if (ret < 0)
3239                 goto out_set_wol;
3240
3241         __rtl_set_wol(tp, wol->wolopts);
3242         tp->saved_wolopts = wol->wolopts & WAKE_ANY;
3243
3244         usb_autopm_put_interface(tp->intf);
3245
3246 out_set_wol:
3247         return ret;
3248 }
3249
3250 static u32 rtl8152_get_msglevel(struct net_device *dev)
3251 {
3252         struct r8152 *tp = netdev_priv(dev);
3253
3254         return tp->msg_enable;
3255 }
3256
3257 static void rtl8152_set_msglevel(struct net_device *dev, u32 value)
3258 {
3259         struct r8152 *tp = netdev_priv(dev);
3260
3261         tp->msg_enable = value;
3262 }
3263
3264 static void rtl8152_get_drvinfo(struct net_device *netdev,
3265                                 struct ethtool_drvinfo *info)
3266 {
3267         struct r8152 *tp = netdev_priv(netdev);
3268
3269         strlcpy(info->driver, MODULENAME, sizeof(info->driver));
3270         strlcpy(info->version, DRIVER_VERSION, sizeof(info->version));
3271         usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info));
3272 }
3273
3274 static
3275 int rtl8152_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
3276 {
3277         struct r8152 *tp = netdev_priv(netdev);
3278
3279         if (!tp->mii.mdio_read)
3280                 return -EOPNOTSUPP;
3281
3282         return mii_ethtool_gset(&tp->mii, cmd);
3283 }
3284
3285 static int rtl8152_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
3286 {
3287         struct r8152 *tp = netdev_priv(dev);
3288         int ret;
3289
3290         ret = usb_autopm_get_interface(tp->intf);
3291         if (ret < 0)
3292                 goto out;
3293
3294         ret = rtl8152_set_speed(tp, cmd->autoneg, cmd->speed, cmd->duplex);
3295
3296         usb_autopm_put_interface(tp->intf);
3297
3298 out:
3299         return ret;
3300 }
3301
3302 static const char rtl8152_gstrings[][ETH_GSTRING_LEN] = {
3303         "tx_packets",
3304         "rx_packets",
3305         "tx_errors",
3306         "rx_errors",
3307         "rx_missed",
3308         "align_errors",
3309         "tx_single_collisions",
3310         "tx_multi_collisions",
3311         "rx_unicast",
3312         "rx_broadcast",
3313         "rx_multicast",
3314         "tx_aborted",
3315         "tx_underrun",
3316 };
3317
3318 static int rtl8152_get_sset_count(struct net_device *dev, int sset)
3319 {
3320         switch (sset) {
3321         case ETH_SS_STATS:
3322                 return ARRAY_SIZE(rtl8152_gstrings);
3323         default:
3324                 return -EOPNOTSUPP;
3325         }
3326 }
3327
3328 static void rtl8152_get_ethtool_stats(struct net_device *dev,
3329                                       struct ethtool_stats *stats, u64 *data)
3330 {
3331         struct r8152 *tp = netdev_priv(dev);
3332         struct tally_counter tally;
3333
3334         if (usb_autopm_get_interface(tp->intf) < 0)
3335                 return;
3336
3337         generic_ocp_read(tp, PLA_TALLYCNT, sizeof(tally), &tally, MCU_TYPE_PLA);
3338
3339         usb_autopm_put_interface(tp->intf);
3340
3341         data[0] = le64_to_cpu(tally.tx_packets);
3342         data[1] = le64_to_cpu(tally.rx_packets);
3343         data[2] = le64_to_cpu(tally.tx_errors);
3344         data[3] = le32_to_cpu(tally.rx_errors);
3345         data[4] = le16_to_cpu(tally.rx_missed);
3346         data[5] = le16_to_cpu(tally.align_errors);
3347         data[6] = le32_to_cpu(tally.tx_one_collision);
3348         data[7] = le32_to_cpu(tally.tx_multi_collision);
3349         data[8] = le64_to_cpu(tally.rx_unicast);
3350         data[9] = le64_to_cpu(tally.rx_broadcast);
3351         data[10] = le32_to_cpu(tally.rx_multicast);
3352         data[11] = le16_to_cpu(tally.tx_aborted);
3353         data[12] = le16_to_cpu(tally.tx_underun);
3354 }
3355
3356 static void rtl8152_get_strings(struct net_device *dev, u32 stringset, u8 *data)
3357 {
3358         switch (stringset) {
3359         case ETH_SS_STATS:
3360                 memcpy(data, *rtl8152_gstrings, sizeof(rtl8152_gstrings));
3361                 break;
3362         }
3363 }
3364
3365 static int r8152_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
3366 {
3367         u32 ocp_data, lp, adv, supported = 0;
3368         u16 val;
3369
3370         val = r8152_mmd_read(tp, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
3371         supported = mmd_eee_cap_to_ethtool_sup_t(val);
3372
3373         val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
3374         adv = mmd_eee_adv_to_ethtool_adv_t(val);
3375
3376         val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE);
3377         lp = mmd_eee_adv_to_ethtool_adv_t(val);
3378
3379         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
3380         ocp_data &= EEE_RX_EN | EEE_TX_EN;
3381
3382         eee->eee_enabled = !!ocp_data;
3383         eee->eee_active = !!(supported & adv & lp);
3384         eee->supported = supported;
3385         eee->advertised = adv;
3386         eee->lp_advertised = lp;
3387
3388         return 0;
3389 }
3390
3391 static int r8152_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
3392 {
3393         u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
3394
3395         r8152_eee_en(tp, eee->eee_enabled);
3396
3397         if (!eee->eee_enabled)
3398                 val = 0;
3399
3400         r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
3401
3402         return 0;
3403 }
3404
3405 static int r8153_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
3406 {
3407         u32 ocp_data, lp, adv, supported = 0;
3408         u16 val;
3409
3410         val = ocp_reg_read(tp, OCP_EEE_ABLE);
3411         supported = mmd_eee_cap_to_ethtool_sup_t(val);
3412
3413         val = ocp_reg_read(tp, OCP_EEE_ADV);
3414         adv = mmd_eee_adv_to_ethtool_adv_t(val);
3415
3416         val = ocp_reg_read(tp, OCP_EEE_LPABLE);
3417         lp = mmd_eee_adv_to_ethtool_adv_t(val);
3418
3419         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
3420         ocp_data &= EEE_RX_EN | EEE_TX_EN;
3421
3422         eee->eee_enabled = !!ocp_data;
3423         eee->eee_active = !!(supported & adv & lp);
3424         eee->supported = supported;
3425         eee->advertised = adv;
3426         eee->lp_advertised = lp;
3427
3428         return 0;
3429 }
3430
3431 static int r8153_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
3432 {
3433         u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
3434
3435         r8153_eee_en(tp, eee->eee_enabled);
3436
3437         if (!eee->eee_enabled)
3438                 val = 0;
3439
3440         ocp_reg_write(tp, OCP_EEE_ADV, val);
3441
3442         return 0;
3443 }
3444
3445 static int
3446 rtl_ethtool_get_eee(struct net_device *net, struct ethtool_eee *edata)
3447 {
3448         struct r8152 *tp = netdev_priv(net);
3449         int ret;
3450
3451         ret = usb_autopm_get_interface(tp->intf);
3452         if (ret < 0)
3453                 goto out;
3454
3455         ret = tp->rtl_ops.eee_get(tp, edata);
3456
3457         usb_autopm_put_interface(tp->intf);
3458
3459 out:
3460         return ret;
3461 }
3462
3463 static int
3464 rtl_ethtool_set_eee(struct net_device *net, struct ethtool_eee *edata)
3465 {
3466         struct r8152 *tp = netdev_priv(net);
3467         int ret;
3468
3469         ret = usb_autopm_get_interface(tp->intf);
3470         if (ret < 0)
3471                 goto out;
3472
3473         ret = tp->rtl_ops.eee_set(tp, edata);
3474         if (!ret)
3475                 ret = mii_nway_restart(&tp->mii);
3476
3477         usb_autopm_put_interface(tp->intf);
3478
3479 out:
3480         return ret;
3481 }
3482
3483 static struct ethtool_ops ops = {
3484         .get_drvinfo = rtl8152_get_drvinfo,
3485         .get_settings = rtl8152_get_settings,
3486         .set_settings = rtl8152_set_settings,
3487         .get_link = ethtool_op_get_link,
3488         .get_msglevel = rtl8152_get_msglevel,
3489         .set_msglevel = rtl8152_set_msglevel,
3490         .get_wol = rtl8152_get_wol,
3491         .set_wol = rtl8152_set_wol,
3492         .get_strings = rtl8152_get_strings,
3493         .get_sset_count = rtl8152_get_sset_count,
3494         .get_ethtool_stats = rtl8152_get_ethtool_stats,
3495         .get_eee = rtl_ethtool_get_eee,
3496         .set_eee = rtl_ethtool_set_eee,
3497 };
3498
3499 static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
3500 {
3501         struct r8152 *tp = netdev_priv(netdev);
3502         struct mii_ioctl_data *data = if_mii(rq);
3503         int res;
3504
3505         if (test_bit(RTL8152_UNPLUG, &tp->flags))
3506                 return -ENODEV;
3507
3508         res = usb_autopm_get_interface(tp->intf);
3509         if (res < 0)
3510                 goto out;
3511
3512         switch (cmd) {
3513         case SIOCGMIIPHY:
3514                 data->phy_id = R8152_PHY_ID; /* Internal PHY */
3515                 break;
3516
3517         case SIOCGMIIREG:
3518                 data->val_out = r8152_mdio_read(tp, data->reg_num);
3519                 break;
3520
3521         case SIOCSMIIREG:
3522                 if (!capable(CAP_NET_ADMIN)) {
3523                         res = -EPERM;
3524                         break;
3525                 }
3526                 r8152_mdio_write(tp, data->reg_num, data->val_in);
3527                 break;
3528
3529         default:
3530                 res = -EOPNOTSUPP;
3531         }
3532
3533         usb_autopm_put_interface(tp->intf);
3534
3535 out:
3536         return res;
3537 }
3538
3539 static int rtl8152_change_mtu(struct net_device *dev, int new_mtu)
3540 {
3541         struct r8152 *tp = netdev_priv(dev);
3542
3543         switch (tp->version) {
3544         case RTL_VER_01:
3545         case RTL_VER_02:
3546                 return eth_change_mtu(dev, new_mtu);
3547         default:
3548                 break;
3549         }
3550
3551         if (new_mtu < 68 || new_mtu > RTL8153_MAX_MTU)
3552                 return -EINVAL;
3553
3554         dev->mtu = new_mtu;
3555
3556         return 0;
3557 }
3558
3559 static const struct net_device_ops rtl8152_netdev_ops = {
3560         .ndo_open               = rtl8152_open,
3561         .ndo_stop               = rtl8152_close,
3562         .ndo_do_ioctl           = rtl8152_ioctl,
3563         .ndo_start_xmit         = rtl8152_start_xmit,
3564         .ndo_tx_timeout         = rtl8152_tx_timeout,
3565         .ndo_set_features       = rtl8152_set_features,
3566         .ndo_set_rx_mode        = rtl8152_set_rx_mode,
3567         .ndo_set_mac_address    = rtl8152_set_mac_address,
3568         .ndo_change_mtu         = rtl8152_change_mtu,
3569         .ndo_validate_addr      = eth_validate_addr,
3570 };
3571
3572 static void r8152b_get_version(struct r8152 *tp)
3573 {
3574         u32     ocp_data;
3575         u16     version;
3576
3577         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR1);
3578         version = (u16)(ocp_data & VERSION_MASK);
3579
3580         switch (version) {
3581         case 0x4c00:
3582                 tp->version = RTL_VER_01;
3583                 break;
3584         case 0x4c10:
3585                 tp->version = RTL_VER_02;
3586                 break;
3587         case 0x5c00:
3588                 tp->version = RTL_VER_03;
3589                 tp->mii.supports_gmii = 1;
3590                 break;
3591         case 0x5c10:
3592                 tp->version = RTL_VER_04;
3593                 tp->mii.supports_gmii = 1;
3594                 break;
3595         case 0x5c20:
3596                 tp->version = RTL_VER_05;
3597                 tp->mii.supports_gmii = 1;
3598                 break;
3599         default:
3600                 netif_info(tp, probe, tp->netdev,
3601                            "Unknown version 0x%04x\n", version);
3602                 break;
3603         }
3604 }
3605
3606 static void rtl8152_unload(struct r8152 *tp)
3607 {
3608         if (test_bit(RTL8152_UNPLUG, &tp->flags))
3609                 return;
3610
3611         if (tp->version != RTL_VER_01)
3612                 r8152_power_cut_en(tp, true);
3613 }
3614
3615 static void rtl8153_unload(struct r8152 *tp)
3616 {
3617         if (test_bit(RTL8152_UNPLUG, &tp->flags))
3618                 return;
3619
3620         r8153_power_cut_en(tp, false);
3621 }
3622
3623 static int rtl_ops_init(struct r8152 *tp, const struct usb_device_id *id)
3624 {
3625         struct rtl_ops *ops = &tp->rtl_ops;
3626         int ret = -ENODEV;
3627
3628         switch (id->idVendor) {
3629         case VENDOR_ID_REALTEK:
3630                 switch (id->idProduct) {
3631                 case PRODUCT_ID_RTL8152:
3632                         ops->init               = r8152b_init;
3633                         ops->enable             = rtl8152_enable;
3634                         ops->disable            = rtl8152_disable;
3635                         ops->up                 = rtl8152_up;
3636                         ops->down               = rtl8152_down;
3637                         ops->unload             = rtl8152_unload;
3638                         ops->eee_get            = r8152_get_eee;
3639                         ops->eee_set            = r8152_set_eee;
3640                         ret = 0;
3641                         break;
3642                 case PRODUCT_ID_RTL8153:
3643                         ops->init               = r8153_init;
3644                         ops->enable             = rtl8153_enable;
3645                         ops->disable            = rtl8153_disable;
3646                         ops->up                 = rtl8153_up;
3647                         ops->down               = rtl8153_down;
3648                         ops->unload             = rtl8153_unload;
3649                         ops->eee_get            = r8153_get_eee;
3650                         ops->eee_set            = r8153_set_eee;
3651                         ret = 0;
3652                         break;
3653                 default:
3654                         break;
3655                 }
3656                 break;
3657
3658         case VENDOR_ID_SAMSUNG:
3659                 switch (id->idProduct) {
3660                 case PRODUCT_ID_SAMSUNG:
3661                         ops->init               = r8153_init;
3662                         ops->enable             = rtl8153_enable;
3663                         ops->disable            = rtl8153_disable;
3664                         ops->up                 = rtl8153_up;
3665                         ops->down               = rtl8153_down;
3666                         ops->unload             = rtl8153_unload;
3667                         ops->eee_get            = r8153_get_eee;
3668                         ops->eee_set            = r8153_set_eee;
3669                         ret = 0;
3670                         break;
3671                 default:
3672                         break;
3673                 }
3674                 break;
3675
3676         default:
3677                 break;
3678         }
3679
3680         if (ret)
3681                 netif_err(tp, probe, tp->netdev, "Unknown Device\n");
3682
3683         return ret;
3684 }
3685
3686 static int rtl8152_probe(struct usb_interface *intf,
3687                          const struct usb_device_id *id)
3688 {
3689         struct usb_device *udev = interface_to_usbdev(intf);
3690         struct r8152 *tp;
3691         struct net_device *netdev;
3692         int ret;
3693
3694         if (udev->actconfig->desc.bConfigurationValue != 1) {
3695                 usb_driver_set_configuration(udev, 1);
3696                 return -ENODEV;
3697         }
3698
3699         usb_reset_device(udev);
3700         netdev = alloc_etherdev(sizeof(struct r8152));
3701         if (!netdev) {
3702                 dev_err(&intf->dev, "Out of memory\n");
3703                 return -ENOMEM;
3704         }
3705
3706         SET_NETDEV_DEV(netdev, &intf->dev);
3707         tp = netdev_priv(netdev);
3708         tp->msg_enable = 0x7FFF;
3709
3710         tp->udev = udev;
3711         tp->netdev = netdev;
3712         tp->intf = intf;
3713
3714         ret = rtl_ops_init(tp, id);
3715         if (ret)
3716                 goto out;
3717
3718         tasklet_init(&tp->tl, bottom_half, (unsigned long)tp);
3719         INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t);
3720
3721         netdev->netdev_ops = &rtl8152_netdev_ops;
3722         netdev->watchdog_timeo = RTL8152_TX_TIMEOUT;
3723
3724         netdev->features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
3725                             NETIF_F_TSO | NETIF_F_FRAGLIST | NETIF_F_IPV6_CSUM |
3726                             NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_RX |
3727                             NETIF_F_HW_VLAN_CTAG_TX;
3728         netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
3729                               NETIF_F_TSO | NETIF_F_FRAGLIST |
3730                               NETIF_F_IPV6_CSUM | NETIF_F_TSO6 |
3731                               NETIF_F_HW_VLAN_CTAG_RX |
3732                               NETIF_F_HW_VLAN_CTAG_TX;
3733         netdev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
3734                                 NETIF_F_HIGHDMA | NETIF_F_FRAGLIST |
3735                                 NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
3736
3737         netdev->ethtool_ops = &ops;
3738         netif_set_gso_max_size(netdev, RTL_LIMITED_TSO_SIZE);
3739
3740         tp->mii.dev = netdev;
3741         tp->mii.mdio_read = read_mii_word;
3742         tp->mii.mdio_write = write_mii_word;
3743         tp->mii.phy_id_mask = 0x3f;
3744         tp->mii.reg_num_mask = 0x1f;
3745         tp->mii.phy_id = R8152_PHY_ID;
3746         tp->mii.supports_gmii = 0;
3747
3748         intf->needs_remote_wakeup = 1;
3749
3750         r8152b_get_version(tp);
3751         tp->rtl_ops.init(tp);
3752         set_ethernet_addr(tp);
3753
3754         usb_set_intfdata(intf, tp);
3755
3756         ret = register_netdev(netdev);
3757         if (ret != 0) {
3758                 netif_err(tp, probe, netdev, "couldn't register the device\n");
3759                 goto out1;
3760         }
3761
3762         tp->saved_wolopts = __rtl_get_wol(tp);
3763         if (tp->saved_wolopts)
3764                 device_set_wakeup_enable(&udev->dev, true);
3765         else
3766                 device_set_wakeup_enable(&udev->dev, false);
3767
3768         netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION);
3769
3770         return 0;
3771
3772 out1:
3773         usb_set_intfdata(intf, NULL);
3774 out:
3775         free_netdev(netdev);
3776         return ret;
3777 }
3778
3779 static void rtl8152_disconnect(struct usb_interface *intf)
3780 {
3781         struct r8152 *tp = usb_get_intfdata(intf);
3782
3783         usb_set_intfdata(intf, NULL);
3784         if (tp) {
3785                 struct usb_device *udev = tp->udev;
3786
3787                 if (udev->state == USB_STATE_NOTATTACHED)
3788                         set_bit(RTL8152_UNPLUG, &tp->flags);
3789
3790                 tasklet_kill(&tp->tl);
3791                 unregister_netdev(tp->netdev);
3792                 tp->rtl_ops.unload(tp);
3793                 free_netdev(tp->netdev);
3794         }
3795 }
3796
3797 /* table of devices that work with this driver */
3798 static struct usb_device_id rtl8152_table[] = {
3799         {USB_DEVICE(VENDOR_ID_REALTEK, PRODUCT_ID_RTL8152)},
3800         {USB_DEVICE(VENDOR_ID_REALTEK, PRODUCT_ID_RTL8153)},
3801         {USB_DEVICE(VENDOR_ID_SAMSUNG, PRODUCT_ID_SAMSUNG)},
3802         {}
3803 };
3804
3805 MODULE_DEVICE_TABLE(usb, rtl8152_table);
3806
3807 static struct usb_driver rtl8152_driver = {
3808         .name =         MODULENAME,
3809         .id_table =     rtl8152_table,
3810         .probe =        rtl8152_probe,
3811         .disconnect =   rtl8152_disconnect,
3812         .suspend =      rtl8152_suspend,
3813         .resume =       rtl8152_resume,
3814         .reset_resume = rtl8152_resume,
3815         .supports_autosuspend = 1,
3816         .disable_hub_initiated_lpm = 1,
3817 };
3818
3819 module_usb_driver(rtl8152_driver);
3820
3821 MODULE_AUTHOR(DRIVER_AUTHOR);
3822 MODULE_DESCRIPTION(DRIVER_DESC);
3823 MODULE_LICENSE("GPL");