2 * Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * version 2 as published by the Free Software Foundation.
10 #include <linux/signal.h>
11 #include <linux/slab.h>
12 #include <linux/module.h>
13 #include <linux/netdevice.h>
14 #include <linux/etherdevice.h>
15 #include <linux/mii.h>
16 #include <linux/ethtool.h>
17 #include <linux/usb.h>
18 #include <linux/crc32.h>
19 #include <linux/if_vlan.h>
20 #include <linux/uaccess.h>
21 #include <linux/list.h>
23 #include <linux/ipv6.h>
24 #include <net/ip6_checksum.h>
25 #include <uapi/linux/mdio.h>
26 #include <linux/mdio.h>
28 /* Version Information */
29 #define DRIVER_VERSION "v1.06.1 (2014/10/01)"
30 #define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>"
31 #define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters"
32 #define MODULENAME "r8152"
34 #define R8152_PHY_ID 32
36 #define PLA_IDR 0xc000
37 #define PLA_RCR 0xc010
38 #define PLA_RMS 0xc016
39 #define PLA_RXFIFO_CTRL0 0xc0a0
40 #define PLA_RXFIFO_CTRL1 0xc0a4
41 #define PLA_RXFIFO_CTRL2 0xc0a8
42 #define PLA_FMC 0xc0b4
43 #define PLA_CFG_WOL 0xc0b6
44 #define PLA_TEREDO_CFG 0xc0bc
45 #define PLA_MAR 0xcd00
46 #define PLA_BACKUP 0xd000
47 #define PAL_BDC_CR 0xd1a0
48 #define PLA_TEREDO_TIMER 0xd2cc
49 #define PLA_REALWOW_TIMER 0xd2e8
50 #define PLA_LEDSEL 0xdd90
51 #define PLA_LED_FEATURE 0xdd92
52 #define PLA_PHYAR 0xde00
53 #define PLA_BOOT_CTRL 0xe004
54 #define PLA_GPHY_INTR_IMR 0xe022
55 #define PLA_EEE_CR 0xe040
56 #define PLA_EEEP_CR 0xe080
57 #define PLA_MAC_PWR_CTRL 0xe0c0
58 #define PLA_MAC_PWR_CTRL2 0xe0ca
59 #define PLA_MAC_PWR_CTRL3 0xe0cc
60 #define PLA_MAC_PWR_CTRL4 0xe0ce
61 #define PLA_WDT6_CTRL 0xe428
62 #define PLA_TCR0 0xe610
63 #define PLA_TCR1 0xe612
64 #define PLA_MTPS 0xe615
65 #define PLA_TXFIFO_CTRL 0xe618
66 #define PLA_RSTTALLY 0xe800
68 #define PLA_CRWECR 0xe81c
69 #define PLA_CONFIG12 0xe81e /* CONFIG1, CONFIG2 */
70 #define PLA_CONFIG34 0xe820 /* CONFIG3, CONFIG4 */
71 #define PLA_CONFIG5 0xe822
72 #define PLA_PHY_PWR 0xe84c
73 #define PLA_OOB_CTRL 0xe84f
74 #define PLA_CPCR 0xe854
75 #define PLA_MISC_0 0xe858
76 #define PLA_MISC_1 0xe85a
77 #define PLA_OCP_GPHY_BASE 0xe86c
78 #define PLA_TALLYCNT 0xe890
79 #define PLA_SFF_STS_7 0xe8de
80 #define PLA_PHYSTATUS 0xe908
81 #define PLA_BP_BA 0xfc26
82 #define PLA_BP_0 0xfc28
83 #define PLA_BP_1 0xfc2a
84 #define PLA_BP_2 0xfc2c
85 #define PLA_BP_3 0xfc2e
86 #define PLA_BP_4 0xfc30
87 #define PLA_BP_5 0xfc32
88 #define PLA_BP_6 0xfc34
89 #define PLA_BP_7 0xfc36
90 #define PLA_BP_EN 0xfc38
92 #define USB_U2P3_CTRL 0xb460
93 #define USB_DEV_STAT 0xb808
94 #define USB_USB_CTRL 0xd406
95 #define USB_PHY_CTRL 0xd408
96 #define USB_TX_AGG 0xd40a
97 #define USB_RX_BUF_TH 0xd40c
98 #define USB_USB_TIMER 0xd428
99 #define USB_RX_EARLY_AGG 0xd42c
100 #define USB_PM_CTRL_STATUS 0xd432
101 #define USB_TX_DMA 0xd434
102 #define USB_TOLERANCE 0xd490
103 #define USB_LPM_CTRL 0xd41a
104 #define USB_UPS_CTRL 0xd800
105 #define USB_MISC_0 0xd81a
106 #define USB_POWER_CUT 0xd80a
107 #define USB_AFE_CTRL2 0xd824
108 #define USB_WDT11_CTRL 0xe43c
109 #define USB_BP_BA 0xfc26
110 #define USB_BP_0 0xfc28
111 #define USB_BP_1 0xfc2a
112 #define USB_BP_2 0xfc2c
113 #define USB_BP_3 0xfc2e
114 #define USB_BP_4 0xfc30
115 #define USB_BP_5 0xfc32
116 #define USB_BP_6 0xfc34
117 #define USB_BP_7 0xfc36
118 #define USB_BP_EN 0xfc38
121 #define OCP_ALDPS_CONFIG 0x2010
122 #define OCP_EEE_CONFIG1 0x2080
123 #define OCP_EEE_CONFIG2 0x2092
124 #define OCP_EEE_CONFIG3 0x2094
125 #define OCP_BASE_MII 0xa400
126 #define OCP_EEE_AR 0xa41a
127 #define OCP_EEE_DATA 0xa41c
128 #define OCP_PHY_STATUS 0xa420
129 #define OCP_POWER_CFG 0xa430
130 #define OCP_EEE_CFG 0xa432
131 #define OCP_SRAM_ADDR 0xa436
132 #define OCP_SRAM_DATA 0xa438
133 #define OCP_DOWN_SPEED 0xa442
134 #define OCP_EEE_ABLE 0xa5c4
135 #define OCP_EEE_ADV 0xa5d0
136 #define OCP_EEE_LPABLE 0xa5d2
137 #define OCP_ADC_CFG 0xbc06
140 #define SRAM_LPF_CFG 0x8012
141 #define SRAM_10M_AMP1 0x8080
142 #define SRAM_10M_AMP2 0x8082
143 #define SRAM_IMPEDANCE 0x8084
146 #define RCR_AAP 0x00000001
147 #define RCR_APM 0x00000002
148 #define RCR_AM 0x00000004
149 #define RCR_AB 0x00000008
150 #define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB)
152 /* PLA_RXFIFO_CTRL0 */
153 #define RXFIFO_THR1_NORMAL 0x00080002
154 #define RXFIFO_THR1_OOB 0x01800003
156 /* PLA_RXFIFO_CTRL1 */
157 #define RXFIFO_THR2_FULL 0x00000060
158 #define RXFIFO_THR2_HIGH 0x00000038
159 #define RXFIFO_THR2_OOB 0x0000004a
160 #define RXFIFO_THR2_NORMAL 0x00a0
162 /* PLA_RXFIFO_CTRL2 */
163 #define RXFIFO_THR3_FULL 0x00000078
164 #define RXFIFO_THR3_HIGH 0x00000048
165 #define RXFIFO_THR3_OOB 0x0000005a
166 #define RXFIFO_THR3_NORMAL 0x0110
168 /* PLA_TXFIFO_CTRL */
169 #define TXFIFO_THR_NORMAL 0x00400008
170 #define TXFIFO_THR_NORMAL2 0x01000008
173 #define FMC_FCR_MCU_EN 0x0001
176 #define EEEP_CR_EEEP_TX 0x0002
179 #define WDT6_SET_MODE 0x0010
182 #define TCR0_TX_EMPTY 0x0800
183 #define TCR0_AUTO_FIFO 0x0080
186 #define VERSION_MASK 0x7cf0
189 #define MTPS_JUMBO (12 * 1024 / 64)
190 #define MTPS_DEFAULT (6 * 1024 / 64)
193 #define TALLY_RESET 0x0001
201 #define CRWECR_NORAML 0x00
202 #define CRWECR_CONFIG 0xc0
205 #define NOW_IS_OOB 0x80
206 #define TXFIFO_EMPTY 0x20
207 #define RXFIFO_EMPTY 0x10
208 #define LINK_LIST_READY 0x02
209 #define DIS_MCU_CLROOB 0x01
210 #define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY)
213 #define RXDY_GATED_EN 0x0008
216 #define RE_INIT_LL 0x8000
217 #define MCU_BORW_EN 0x4000
220 #define CPCR_RX_VLAN 0x0040
223 #define MAGIC_EN 0x0001
226 #define TEREDO_SEL 0x8000
227 #define TEREDO_WAKE_MASK 0x7f00
228 #define TEREDO_RS_EVENT_MASK 0x00fe
229 #define OOB_TEREDO_EN 0x0001
232 #define ALDPS_PROXY_MODE 0x0001
235 #define LINK_ON_WAKE_EN 0x0010
236 #define LINK_OFF_WAKE_EN 0x0008
239 #define BWF_EN 0x0040
240 #define MWF_EN 0x0020
241 #define UWF_EN 0x0010
242 #define LAN_WAKE_EN 0x0002
244 /* PLA_LED_FEATURE */
245 #define LED_MODE_MASK 0x0700
248 #define TX_10M_IDLE_EN 0x0080
249 #define PFM_PWM_SWITCH 0x0040
251 /* PLA_MAC_PWR_CTRL */
252 #define D3_CLK_GATED_EN 0x00004000
253 #define MCU_CLK_RATIO 0x07010f07
254 #define MCU_CLK_RATIO_MASK 0x0f0f0f0f
255 #define ALDPS_SPDWN_RATIO 0x0f87
257 /* PLA_MAC_PWR_CTRL2 */
258 #define EEE_SPDWN_RATIO 0x8007
260 /* PLA_MAC_PWR_CTRL3 */
261 #define PKT_AVAIL_SPDWN_EN 0x0100
262 #define SUSPEND_SPDWN_EN 0x0004
263 #define U1U2_SPDWN_EN 0x0002
264 #define L1_SPDWN_EN 0x0001
266 /* PLA_MAC_PWR_CTRL4 */
267 #define PWRSAVE_SPDWN_EN 0x1000
268 #define RXDV_SPDWN_EN 0x0800
269 #define TX10MIDLE_EN 0x0100
270 #define TP100_SPDWN_EN 0x0020
271 #define TP500_SPDWN_EN 0x0010
272 #define TP1000_SPDWN_EN 0x0008
273 #define EEE_SPDWN_EN 0x0001
275 /* PLA_GPHY_INTR_IMR */
276 #define GPHY_STS_MSK 0x0001
277 #define SPEED_DOWN_MSK 0x0002
278 #define SPDWN_RXDV_MSK 0x0004
279 #define SPDWN_LINKCHG_MSK 0x0008
282 #define PHYAR_FLAG 0x80000000
285 #define EEE_RX_EN 0x0001
286 #define EEE_TX_EN 0x0002
289 #define AUTOLOAD_DONE 0x0002
292 #define STAT_SPEED_MASK 0x0006
293 #define STAT_SPEED_HIGH 0x0000
294 #define STAT_SPEED_FULL 0x0002
297 #define TX_AGG_MAX_THRESHOLD 0x03
300 #define RX_THR_SUPPER 0x0c350180
301 #define RX_THR_HIGH 0x7a120180
302 #define RX_THR_SLOW 0xffff0180
305 #define TEST_MODE_DISABLE 0x00000001
306 #define TX_SIZE_ADJUST1 0x00000100
309 #define POWER_CUT 0x0100
311 /* USB_PM_CTRL_STATUS */
312 #define RESUME_INDICATE 0x0001
315 #define RX_AGG_DISABLE 0x0010
318 #define U2P3_ENABLE 0x0001
321 #define PWR_EN 0x0001
322 #define PHASE2_EN 0x0008
325 #define PCUT_STATUS 0x0001
327 /* USB_RX_EARLY_AGG */
328 #define EARLY_AGG_SUPPER 0x0e832981
329 #define EARLY_AGG_HIGH 0x0e837a12
330 #define EARLY_AGG_SLOW 0x0e83ffff
333 #define TIMER11_EN 0x0001
336 #define LPM_TIMER_MASK 0x0c
337 #define LPM_TIMER_500MS 0x04 /* 500 ms */
338 #define LPM_TIMER_500US 0x0c /* 500 us */
341 #define SEN_VAL_MASK 0xf800
342 #define SEN_VAL_NORMAL 0xa000
343 #define SEL_RXIDLE 0x0100
345 /* OCP_ALDPS_CONFIG */
346 #define ENPWRSAVE 0x8000
347 #define ENPDNPS 0x0200
348 #define LINKENA 0x0100
349 #define DIS_SDSAVE 0x0010
352 #define PHY_STAT_MASK 0x0007
353 #define PHY_STAT_LAN_ON 3
354 #define PHY_STAT_PWRDN 5
357 #define EEE_CLKDIV_EN 0x8000
358 #define EN_ALDPS 0x0004
359 #define EN_10M_PLLOFF 0x0001
361 /* OCP_EEE_CONFIG1 */
362 #define RG_TXLPI_MSK_HFDUP 0x8000
363 #define RG_MATCLR_EN 0x4000
364 #define EEE_10_CAP 0x2000
365 #define EEE_NWAY_EN 0x1000
366 #define TX_QUIET_EN 0x0200
367 #define RX_QUIET_EN 0x0100
368 #define sd_rise_time_mask 0x0070
369 #define sd_rise_time(x) (min(x, 7) << 4) /* bit 4 ~ 6 */
370 #define RG_RXLPI_MSK_HFDUP 0x0008
371 #define SDFALLTIME 0x0007 /* bit 0 ~ 2 */
373 /* OCP_EEE_CONFIG2 */
374 #define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */
375 #define RG_DACQUIET_EN 0x0400
376 #define RG_LDVQUIET_EN 0x0200
377 #define RG_CKRSEL 0x0020
378 #define RG_EEEPRG_EN 0x0010
380 /* OCP_EEE_CONFIG3 */
381 #define fast_snr_mask 0xff80
382 #define fast_snr(x) (min(x, 0x1ff) << 7) /* bit 7 ~ 15 */
383 #define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */
384 #define MSK_PH 0x0006 /* bit 0 ~ 3 */
387 /* bit[15:14] function */
388 #define FUN_ADDR 0x0000
389 #define FUN_DATA 0x4000
390 /* bit[4:0] device addr */
393 #define CTAP_SHORT_EN 0x0040
394 #define EEE10_EN 0x0010
397 #define EN_10M_BGOFF 0x0080
400 #define CKADSEL_L 0x0100
401 #define ADC_EN 0x0080
402 #define EN_EMI_L 0x0040
405 #define LPF_AUTO_TUNE 0x8000
408 #define GDAC_IB_UPALL 0x0008
411 #define AMP_DN 0x0200
414 #define RX_DRIVING_MASK 0x6000
416 enum rtl_register_content {
424 #define RTL8152_MAX_TX 4
425 #define RTL8152_MAX_RX 10
431 #define INTR_LINK 0x0004
433 #define RTL8152_REQT_READ 0xc0
434 #define RTL8152_REQT_WRITE 0x40
435 #define RTL8152_REQ_GET_REGS 0x05
436 #define RTL8152_REQ_SET_REGS 0x05
438 #define BYTE_EN_DWORD 0xff
439 #define BYTE_EN_WORD 0x33
440 #define BYTE_EN_BYTE 0x11
441 #define BYTE_EN_SIX_BYTES 0x3f
442 #define BYTE_EN_START_MASK 0x0f
443 #define BYTE_EN_END_MASK 0xf0
445 #define RTL8153_MAX_PACKET 9216 /* 9K */
446 #define RTL8153_MAX_MTU (RTL8153_MAX_PACKET - VLAN_ETH_HLEN - VLAN_HLEN)
447 #define RTL8152_RMS (VLAN_ETH_FRAME_LEN + VLAN_HLEN)
448 #define RTL8153_RMS RTL8153_MAX_PACKET
449 #define RTL8152_TX_TIMEOUT (5 * HZ)
462 /* Define these values to match your device */
463 #define VENDOR_ID_REALTEK 0x0bda
464 #define PRODUCT_ID_RTL8152 0x8152
465 #define PRODUCT_ID_RTL8153 0x8153
467 #define VENDOR_ID_SAMSUNG 0x04e8
468 #define PRODUCT_ID_SAMSUNG 0xa101
470 #define MCU_TYPE_PLA 0x0100
471 #define MCU_TYPE_USB 0x0000
473 #define REALTEK_USB_DEVICE(vend, prod) \
474 USB_DEVICE_INTERFACE_CLASS(vend, prod, USB_CLASS_VENDOR_SPEC)
476 struct tally_counter {
483 __le32 tx_one_collision;
484 __le32 tx_multi_collision;
494 #define RX_LEN_MASK 0x7fff
497 #define RD_UDP_CS (1 << 23)
498 #define RD_TCP_CS (1 << 22)
499 #define RD_IPV6_CS (1 << 20)
500 #define RD_IPV4_CS (1 << 19)
503 #define IPF (1 << 23) /* IP checksum fail */
504 #define UDPF (1 << 22) /* UDP checksum fail */
505 #define TCPF (1 << 21) /* TCP checksum fail */
506 #define RX_VLAN_TAG (1 << 16)
515 #define TX_FS (1 << 31) /* First segment of a packet */
516 #define TX_LS (1 << 30) /* Final segment of a packet */
517 #define GTSENDV4 (1 << 28)
518 #define GTSENDV6 (1 << 27)
519 #define GTTCPHO_SHIFT 18
520 #define GTTCPHO_MAX 0x7fU
521 #define TX_LEN_MAX 0x3ffffU
524 #define UDP_CS (1 << 31) /* Calculate UDP/IP checksum */
525 #define TCP_CS (1 << 30) /* Calculate TCP/IP checksum */
526 #define IPV4_CS (1 << 29) /* Calculate IPv4 checksum */
527 #define IPV6_CS (1 << 28) /* Calculate IPv6 checksum */
529 #define MSS_MAX 0x7ffU
530 #define TCPHO_SHIFT 17
531 #define TCPHO_MAX 0x7ffU
532 #define TX_VLAN_TAG (1 << 16)
538 struct list_head list;
540 struct r8152 *context;
546 struct list_head list;
548 struct r8152 *context;
557 struct usb_device *udev;
558 struct tasklet_struct tl;
559 struct usb_interface *intf;
560 struct net_device *netdev;
561 struct urb *intr_urb;
562 struct tx_agg tx_info[RTL8152_MAX_TX];
563 struct rx_agg rx_info[RTL8152_MAX_RX];
564 struct list_head rx_done, tx_free;
565 struct sk_buff_head tx_queue;
566 spinlock_t rx_lock, tx_lock;
567 struct delayed_work schedule;
568 struct mii_if_info mii;
571 void (*init)(struct r8152 *);
572 int (*enable)(struct r8152 *);
573 void (*disable)(struct r8152 *);
574 void (*up)(struct r8152 *);
575 void (*down)(struct r8152 *);
576 void (*unload)(struct r8152 *);
577 int (*eee_get)(struct r8152 *, struct ethtool_eee *);
578 int (*eee_set)(struct r8152 *, struct ethtool_eee *);
607 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
608 * The RTL chips use a 64 element hash table based on the Ethernet CRC.
610 static const int multicast_filter_limit = 32;
611 static unsigned int agg_buf_sz = 16384;
613 #define RTL_LIMITED_TSO_SIZE (agg_buf_sz - sizeof(struct tx_desc) - \
614 VLAN_ETH_HLEN - VLAN_HLEN)
617 int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
622 tmp = kmalloc(size, GFP_KERNEL);
626 ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0),
627 RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
628 value, index, tmp, size, 500);
630 memcpy(data, tmp, size);
637 int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
642 tmp = kmemdup(data, size, GFP_KERNEL);
646 ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0),
647 RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE,
648 value, index, tmp, size, 500);
655 static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
656 void *data, u16 type)
661 if (test_bit(RTL8152_UNPLUG, &tp->flags))
664 /* both size and indix must be 4 bytes align */
665 if ((size & 3) || !size || (index & 3) || !data)
668 if ((u32)index + (u32)size > 0xffff)
673 ret = get_registers(tp, index, type, limit, data);
681 ret = get_registers(tp, index, type, size, data);
695 static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
696 u16 size, void *data, u16 type)
699 u16 byteen_start, byteen_end, byen;
702 if (test_bit(RTL8152_UNPLUG, &tp->flags))
705 /* both size and indix must be 4 bytes align */
706 if ((size & 3) || !size || (index & 3) || !data)
709 if ((u32)index + (u32)size > 0xffff)
712 byteen_start = byteen & BYTE_EN_START_MASK;
713 byteen_end = byteen & BYTE_EN_END_MASK;
715 byen = byteen_start | (byteen_start << 4);
716 ret = set_registers(tp, index, type | byen, 4, data);
729 ret = set_registers(tp, index,
730 type | BYTE_EN_DWORD,
739 ret = set_registers(tp, index,
740 type | BYTE_EN_DWORD,
752 byen = byteen_end | (byteen_end >> 4);
753 ret = set_registers(tp, index, type | byen, 4, data);
763 int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
765 return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA);
769 int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
771 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA);
775 int usb_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
777 return generic_ocp_read(tp, index, size, data, MCU_TYPE_USB);
781 int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
783 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB);
786 static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index)
790 generic_ocp_read(tp, index, sizeof(data), &data, type);
792 return __le32_to_cpu(data);
795 static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data)
797 __le32 tmp = __cpu_to_le32(data);
799 generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type);
802 static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index)
806 u8 shift = index & 2;
810 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
812 data = __le32_to_cpu(tmp);
813 data >>= (shift * 8);
819 static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data)
823 u16 byen = BYTE_EN_WORD;
824 u8 shift = index & 2;
830 mask <<= (shift * 8);
831 data <<= (shift * 8);
835 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
837 data |= __le32_to_cpu(tmp) & ~mask;
838 tmp = __cpu_to_le32(data);
840 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
843 static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index)
847 u8 shift = index & 3;
851 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
853 data = __le32_to_cpu(tmp);
854 data >>= (shift * 8);
860 static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data)
864 u16 byen = BYTE_EN_BYTE;
865 u8 shift = index & 3;
871 mask <<= (shift * 8);
872 data <<= (shift * 8);
876 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
878 data |= __le32_to_cpu(tmp) & ~mask;
879 tmp = __cpu_to_le32(data);
881 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
884 static u16 ocp_reg_read(struct r8152 *tp, u16 addr)
886 u16 ocp_base, ocp_index;
888 ocp_base = addr & 0xf000;
889 if (ocp_base != tp->ocp_base) {
890 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
891 tp->ocp_base = ocp_base;
894 ocp_index = (addr & 0x0fff) | 0xb000;
895 return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index);
898 static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data)
900 u16 ocp_base, ocp_index;
902 ocp_base = addr & 0xf000;
903 if (ocp_base != tp->ocp_base) {
904 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
905 tp->ocp_base = ocp_base;
908 ocp_index = (addr & 0x0fff) | 0xb000;
909 ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data);
912 static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value)
914 ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value);
917 static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr)
919 return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2);
922 static void sram_write(struct r8152 *tp, u16 addr, u16 data)
924 ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
925 ocp_reg_write(tp, OCP_SRAM_DATA, data);
928 static u16 sram_read(struct r8152 *tp, u16 addr)
930 ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
931 return ocp_reg_read(tp, OCP_SRAM_DATA);
934 static int read_mii_word(struct net_device *netdev, int phy_id, int reg)
936 struct r8152 *tp = netdev_priv(netdev);
939 if (test_bit(RTL8152_UNPLUG, &tp->flags))
942 if (phy_id != R8152_PHY_ID)
945 ret = usb_autopm_get_interface(tp->intf);
949 ret = r8152_mdio_read(tp, reg);
951 usb_autopm_put_interface(tp->intf);
958 void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val)
960 struct r8152 *tp = netdev_priv(netdev);
962 if (test_bit(RTL8152_UNPLUG, &tp->flags))
965 if (phy_id != R8152_PHY_ID)
968 if (usb_autopm_get_interface(tp->intf) < 0)
971 r8152_mdio_write(tp, reg, val);
973 usb_autopm_put_interface(tp->intf);
977 r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags);
979 static int rtl8152_set_mac_address(struct net_device *netdev, void *p)
981 struct r8152 *tp = netdev_priv(netdev);
982 struct sockaddr *addr = p;
984 if (!is_valid_ether_addr(addr->sa_data))
985 return -EADDRNOTAVAIL;
987 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
989 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
990 pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data);
991 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
996 static int set_ethernet_addr(struct r8152 *tp)
998 struct net_device *dev = tp->netdev;
1002 if (tp->version == RTL_VER_01)
1003 ret = pla_ocp_read(tp, PLA_IDR, 8, sa.sa_data);
1005 ret = pla_ocp_read(tp, PLA_BACKUP, 8, sa.sa_data);
1008 netif_err(tp, probe, dev, "Get ether addr fail\n");
1009 } else if (!is_valid_ether_addr(sa.sa_data)) {
1010 netif_err(tp, probe, dev, "Invalid ether addr %pM\n",
1012 eth_hw_addr_random(dev);
1013 ether_addr_copy(sa.sa_data, dev->dev_addr);
1014 ret = rtl8152_set_mac_address(dev, &sa);
1015 netif_info(tp, probe, dev, "Random ether addr %pM\n",
1018 if (tp->version == RTL_VER_01)
1019 ether_addr_copy(dev->dev_addr, sa.sa_data);
1021 ret = rtl8152_set_mac_address(dev, &sa);
1027 static void read_bulk_callback(struct urb *urb)
1029 struct net_device *netdev;
1030 int status = urb->status;
1043 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1046 if (!test_bit(WORK_ENABLE, &tp->flags))
1049 netdev = tp->netdev;
1051 /* When link down, the driver would cancel all bulks. */
1052 /* This avoid the re-submitting bulk */
1053 if (!netif_carrier_ok(netdev))
1056 usb_mark_last_busy(tp->udev);
1060 if (urb->actual_length < ETH_ZLEN)
1063 spin_lock(&tp->rx_lock);
1064 list_add_tail(&agg->list, &tp->rx_done);
1065 spin_unlock(&tp->rx_lock);
1066 tasklet_schedule(&tp->tl);
1069 set_bit(RTL8152_UNPLUG, &tp->flags);
1070 netif_device_detach(tp->netdev);
1073 return; /* the urb is in unlink state */
1075 if (net_ratelimit())
1076 netdev_warn(netdev, "maybe reset is needed?\n");
1079 if (net_ratelimit())
1080 netdev_warn(netdev, "Rx status %d\n", status);
1084 result = r8152_submit_rx(tp, agg, GFP_ATOMIC);
1085 if (result == -ENODEV) {
1086 netif_device_detach(tp->netdev);
1087 } else if (result) {
1088 spin_lock(&tp->rx_lock);
1089 list_add_tail(&agg->list, &tp->rx_done);
1090 spin_unlock(&tp->rx_lock);
1091 tasklet_schedule(&tp->tl);
1095 static void write_bulk_callback(struct urb *urb)
1097 struct net_device_stats *stats;
1098 struct net_device *netdev;
1101 int status = urb->status;
1111 netdev = tp->netdev;
1112 stats = &netdev->stats;
1114 if (net_ratelimit())
1115 netdev_warn(netdev, "Tx status %d\n", status);
1116 stats->tx_errors += agg->skb_num;
1118 stats->tx_packets += agg->skb_num;
1119 stats->tx_bytes += agg->skb_len;
1122 spin_lock(&tp->tx_lock);
1123 list_add_tail(&agg->list, &tp->tx_free);
1124 spin_unlock(&tp->tx_lock);
1126 usb_autopm_put_interface_async(tp->intf);
1128 if (!netif_carrier_ok(netdev))
1131 if (!test_bit(WORK_ENABLE, &tp->flags))
1134 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1137 if (!skb_queue_empty(&tp->tx_queue))
1138 tasklet_schedule(&tp->tl);
1141 static void intr_callback(struct urb *urb)
1145 int status = urb->status;
1152 if (!test_bit(WORK_ENABLE, &tp->flags))
1155 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1159 case 0: /* success */
1161 case -ECONNRESET: /* unlink */
1163 netif_device_detach(tp->netdev);
1167 netif_info(tp, intr, tp->netdev, "intr status -EOVERFLOW\n");
1169 /* -EPIPE: should clear the halt */
1171 netif_info(tp, intr, tp->netdev, "intr status %d\n", status);
1175 d = urb->transfer_buffer;
1176 if (INTR_LINK & __le16_to_cpu(d[0])) {
1177 if (!(tp->speed & LINK_STATUS)) {
1178 set_bit(RTL8152_LINK_CHG, &tp->flags);
1179 schedule_delayed_work(&tp->schedule, 0);
1182 if (tp->speed & LINK_STATUS) {
1183 set_bit(RTL8152_LINK_CHG, &tp->flags);
1184 schedule_delayed_work(&tp->schedule, 0);
1189 res = usb_submit_urb(urb, GFP_ATOMIC);
1191 netif_device_detach(tp->netdev);
1193 netif_err(tp, intr, tp->netdev,
1194 "can't resubmit intr, status %d\n", res);
1197 static inline void *rx_agg_align(void *data)
1199 return (void *)ALIGN((uintptr_t)data, RX_ALIGN);
1202 static inline void *tx_agg_align(void *data)
1204 return (void *)ALIGN((uintptr_t)data, TX_ALIGN);
1207 static void free_all_mem(struct r8152 *tp)
1211 for (i = 0; i < RTL8152_MAX_RX; i++) {
1212 usb_free_urb(tp->rx_info[i].urb);
1213 tp->rx_info[i].urb = NULL;
1215 kfree(tp->rx_info[i].buffer);
1216 tp->rx_info[i].buffer = NULL;
1217 tp->rx_info[i].head = NULL;
1220 for (i = 0; i < RTL8152_MAX_TX; i++) {
1221 usb_free_urb(tp->tx_info[i].urb);
1222 tp->tx_info[i].urb = NULL;
1224 kfree(tp->tx_info[i].buffer);
1225 tp->tx_info[i].buffer = NULL;
1226 tp->tx_info[i].head = NULL;
1229 usb_free_urb(tp->intr_urb);
1230 tp->intr_urb = NULL;
1232 kfree(tp->intr_buff);
1233 tp->intr_buff = NULL;
1236 static int alloc_all_mem(struct r8152 *tp)
1238 struct net_device *netdev = tp->netdev;
1239 struct usb_interface *intf = tp->intf;
1240 struct usb_host_interface *alt = intf->cur_altsetting;
1241 struct usb_host_endpoint *ep_intr = alt->endpoint + 2;
1246 node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1;
1248 spin_lock_init(&tp->rx_lock);
1249 spin_lock_init(&tp->tx_lock);
1250 INIT_LIST_HEAD(&tp->rx_done);
1251 INIT_LIST_HEAD(&tp->tx_free);
1252 skb_queue_head_init(&tp->tx_queue);
1254 for (i = 0; i < RTL8152_MAX_RX; i++) {
1255 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
1259 if (buf != rx_agg_align(buf)) {
1261 buf = kmalloc_node(agg_buf_sz + RX_ALIGN, GFP_KERNEL,
1267 urb = usb_alloc_urb(0, GFP_KERNEL);
1273 INIT_LIST_HEAD(&tp->rx_info[i].list);
1274 tp->rx_info[i].context = tp;
1275 tp->rx_info[i].urb = urb;
1276 tp->rx_info[i].buffer = buf;
1277 tp->rx_info[i].head = rx_agg_align(buf);
1280 for (i = 0; i < RTL8152_MAX_TX; i++) {
1281 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
1285 if (buf != tx_agg_align(buf)) {
1287 buf = kmalloc_node(agg_buf_sz + TX_ALIGN, GFP_KERNEL,
1293 urb = usb_alloc_urb(0, GFP_KERNEL);
1299 INIT_LIST_HEAD(&tp->tx_info[i].list);
1300 tp->tx_info[i].context = tp;
1301 tp->tx_info[i].urb = urb;
1302 tp->tx_info[i].buffer = buf;
1303 tp->tx_info[i].head = tx_agg_align(buf);
1305 list_add_tail(&tp->tx_info[i].list, &tp->tx_free);
1308 tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL);
1312 tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL);
1316 tp->intr_interval = (int)ep_intr->desc.bInterval;
1317 usb_fill_int_urb(tp->intr_urb, tp->udev, usb_rcvintpipe(tp->udev, 3),
1318 tp->intr_buff, INTBUFSIZE, intr_callback,
1319 tp, tp->intr_interval);
1328 static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp)
1330 struct tx_agg *agg = NULL;
1331 unsigned long flags;
1333 if (list_empty(&tp->tx_free))
1336 spin_lock_irqsave(&tp->tx_lock, flags);
1337 if (!list_empty(&tp->tx_free)) {
1338 struct list_head *cursor;
1340 cursor = tp->tx_free.next;
1341 list_del_init(cursor);
1342 agg = list_entry(cursor, struct tx_agg, list);
1344 spin_unlock_irqrestore(&tp->tx_lock, flags);
1349 static inline __be16 get_protocol(struct sk_buff *skb)
1353 if (skb->protocol == htons(ETH_P_8021Q))
1354 protocol = vlan_eth_hdr(skb)->h_vlan_encapsulated_proto;
1356 protocol = skb->protocol;
1361 /* r8152_csum_workaround()
1362 * The hw limites the value the transport offset. When the offset is out of the
1363 * range, calculate the checksum by sw.
1365 static void r8152_csum_workaround(struct r8152 *tp, struct sk_buff *skb,
1366 struct sk_buff_head *list)
1368 if (skb_shinfo(skb)->gso_size) {
1369 netdev_features_t features = tp->netdev->features;
1370 struct sk_buff_head seg_list;
1371 struct sk_buff *segs, *nskb;
1373 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
1374 segs = skb_gso_segment(skb, features);
1375 if (IS_ERR(segs) || !segs)
1378 __skb_queue_head_init(&seg_list);
1384 __skb_queue_tail(&seg_list, nskb);
1387 skb_queue_splice(&seg_list, list);
1389 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
1390 if (skb_checksum_help(skb) < 0)
1393 __skb_queue_head(list, skb);
1395 struct net_device_stats *stats;
1398 stats = &tp->netdev->stats;
1399 stats->tx_dropped++;
1404 /* msdn_giant_send_check()
1405 * According to the document of microsoft, the TCP Pseudo Header excludes the
1406 * packet length for IPv6 TCP large packets.
1408 static int msdn_giant_send_check(struct sk_buff *skb)
1410 const struct ipv6hdr *ipv6h;
1414 ret = skb_cow_head(skb, 0);
1418 ipv6h = ipv6_hdr(skb);
1422 th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
1427 static inline void rtl_tx_vlan_tag(struct tx_desc *desc, struct sk_buff *skb)
1429 if (vlan_tx_tag_present(skb)) {
1432 opts2 = TX_VLAN_TAG | swab16(vlan_tx_tag_get(skb));
1433 desc->opts2 |= cpu_to_le32(opts2);
1437 static inline void rtl_rx_vlan_tag(struct rx_desc *desc, struct sk_buff *skb)
1439 u32 opts2 = le32_to_cpu(desc->opts2);
1441 if (opts2 & RX_VLAN_TAG)
1442 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
1443 swab16(opts2 & 0xffff));
1446 static int r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc,
1447 struct sk_buff *skb, u32 len, u32 transport_offset)
1449 u32 mss = skb_shinfo(skb)->gso_size;
1450 u32 opts1, opts2 = 0;
1451 int ret = TX_CSUM_SUCCESS;
1453 WARN_ON_ONCE(len > TX_LEN_MAX);
1455 opts1 = len | TX_FS | TX_LS;
1458 if (transport_offset > GTTCPHO_MAX) {
1459 netif_warn(tp, tx_err, tp->netdev,
1460 "Invalid transport offset 0x%x for TSO\n",
1466 switch (get_protocol(skb)) {
1467 case htons(ETH_P_IP):
1471 case htons(ETH_P_IPV6):
1472 if (msdn_giant_send_check(skb)) {
1484 opts1 |= transport_offset << GTTCPHO_SHIFT;
1485 opts2 |= min(mss, MSS_MAX) << MSS_SHIFT;
1486 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
1489 if (transport_offset > TCPHO_MAX) {
1490 netif_warn(tp, tx_err, tp->netdev,
1491 "Invalid transport offset 0x%x\n",
1497 switch (get_protocol(skb)) {
1498 case htons(ETH_P_IP):
1500 ip_protocol = ip_hdr(skb)->protocol;
1503 case htons(ETH_P_IPV6):
1505 ip_protocol = ipv6_hdr(skb)->nexthdr;
1509 ip_protocol = IPPROTO_RAW;
1513 if (ip_protocol == IPPROTO_TCP)
1515 else if (ip_protocol == IPPROTO_UDP)
1520 opts2 |= transport_offset << TCPHO_SHIFT;
1523 desc->opts2 = cpu_to_le32(opts2);
1524 desc->opts1 = cpu_to_le32(opts1);
1530 static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg)
1532 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
1536 __skb_queue_head_init(&skb_head);
1537 spin_lock(&tx_queue->lock);
1538 skb_queue_splice_init(tx_queue, &skb_head);
1539 spin_unlock(&tx_queue->lock);
1541 tx_data = agg->head;
1544 remain = agg_buf_sz;
1546 while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) {
1547 struct tx_desc *tx_desc;
1548 struct sk_buff *skb;
1552 skb = __skb_dequeue(&skb_head);
1556 len = skb->len + sizeof(*tx_desc);
1559 __skb_queue_head(&skb_head, skb);
1563 tx_data = tx_agg_align(tx_data);
1564 tx_desc = (struct tx_desc *)tx_data;
1566 offset = (u32)skb_transport_offset(skb);
1568 if (r8152_tx_csum(tp, tx_desc, skb, skb->len, offset)) {
1569 r8152_csum_workaround(tp, skb, &skb_head);
1573 rtl_tx_vlan_tag(tx_desc, skb);
1575 tx_data += sizeof(*tx_desc);
1578 if (skb_copy_bits(skb, 0, tx_data, len) < 0) {
1579 struct net_device_stats *stats = &tp->netdev->stats;
1581 stats->tx_dropped++;
1582 dev_kfree_skb_any(skb);
1583 tx_data -= sizeof(*tx_desc);
1588 agg->skb_len += len;
1591 dev_kfree_skb_any(skb);
1593 remain = agg_buf_sz - (int)(tx_agg_align(tx_data) - agg->head);
1596 if (!skb_queue_empty(&skb_head)) {
1597 spin_lock(&tx_queue->lock);
1598 skb_queue_splice(&skb_head, tx_queue);
1599 spin_unlock(&tx_queue->lock);
1602 netif_tx_lock(tp->netdev);
1604 if (netif_queue_stopped(tp->netdev) &&
1605 skb_queue_len(&tp->tx_queue) < tp->tx_qlen)
1606 netif_wake_queue(tp->netdev);
1608 netif_tx_unlock(tp->netdev);
1610 ret = usb_autopm_get_interface_async(tp->intf);
1614 usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2),
1615 agg->head, (int)(tx_data - (u8 *)agg->head),
1616 (usb_complete_t)write_bulk_callback, agg);
1618 ret = usb_submit_urb(agg->urb, GFP_ATOMIC);
1620 usb_autopm_put_interface_async(tp->intf);
1626 static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc)
1628 u8 checksum = CHECKSUM_NONE;
1631 if (tp->version == RTL_VER_01)
1634 opts2 = le32_to_cpu(rx_desc->opts2);
1635 opts3 = le32_to_cpu(rx_desc->opts3);
1637 if (opts2 & RD_IPV4_CS) {
1639 checksum = CHECKSUM_NONE;
1640 else if ((opts2 & RD_UDP_CS) && (opts3 & UDPF))
1641 checksum = CHECKSUM_NONE;
1642 else if ((opts2 & RD_TCP_CS) && (opts3 & TCPF))
1643 checksum = CHECKSUM_NONE;
1645 checksum = CHECKSUM_UNNECESSARY;
1646 } else if (RD_IPV6_CS) {
1647 if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))
1648 checksum = CHECKSUM_UNNECESSARY;
1649 else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))
1650 checksum = CHECKSUM_UNNECESSARY;
1657 static void rx_bottom(struct r8152 *tp)
1659 unsigned long flags;
1660 struct list_head *cursor, *next, rx_queue;
1662 if (list_empty(&tp->rx_done))
1665 INIT_LIST_HEAD(&rx_queue);
1666 spin_lock_irqsave(&tp->rx_lock, flags);
1667 list_splice_init(&tp->rx_done, &rx_queue);
1668 spin_unlock_irqrestore(&tp->rx_lock, flags);
1670 list_for_each_safe(cursor, next, &rx_queue) {
1671 struct rx_desc *rx_desc;
1678 list_del_init(cursor);
1680 agg = list_entry(cursor, struct rx_agg, list);
1682 if (urb->actual_length < ETH_ZLEN)
1685 rx_desc = agg->head;
1686 rx_data = agg->head;
1687 len_used += sizeof(struct rx_desc);
1689 while (urb->actual_length > len_used) {
1690 struct net_device *netdev = tp->netdev;
1691 struct net_device_stats *stats = &netdev->stats;
1692 unsigned int pkt_len;
1693 struct sk_buff *skb;
1695 pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
1696 if (pkt_len < ETH_ZLEN)
1699 len_used += pkt_len;
1700 if (urb->actual_length < len_used)
1703 pkt_len -= CRC_SIZE;
1704 rx_data += sizeof(struct rx_desc);
1706 skb = netdev_alloc_skb_ip_align(netdev, pkt_len);
1708 stats->rx_dropped++;
1712 skb->ip_summed = r8152_rx_csum(tp, rx_desc);
1713 memcpy(skb->data, rx_data, pkt_len);
1714 skb_put(skb, pkt_len);
1715 skb->protocol = eth_type_trans(skb, netdev);
1716 rtl_rx_vlan_tag(rx_desc, skb);
1717 netif_receive_skb(skb);
1718 stats->rx_packets++;
1719 stats->rx_bytes += pkt_len;
1722 rx_data = rx_agg_align(rx_data + pkt_len + CRC_SIZE);
1723 rx_desc = (struct rx_desc *)rx_data;
1724 len_used = (int)(rx_data - (u8 *)agg->head);
1725 len_used += sizeof(struct rx_desc);
1729 ret = r8152_submit_rx(tp, agg, GFP_ATOMIC);
1730 if (ret && ret != -ENODEV) {
1731 spin_lock_irqsave(&tp->rx_lock, flags);
1732 list_add_tail(&agg->list, &tp->rx_done);
1733 spin_unlock_irqrestore(&tp->rx_lock, flags);
1734 tasklet_schedule(&tp->tl);
1739 static void tx_bottom(struct r8152 *tp)
1746 if (skb_queue_empty(&tp->tx_queue))
1749 agg = r8152_get_tx_agg(tp);
1753 res = r8152_tx_agg_fill(tp, agg);
1755 struct net_device *netdev = tp->netdev;
1757 if (res == -ENODEV) {
1758 netif_device_detach(netdev);
1760 struct net_device_stats *stats = &netdev->stats;
1761 unsigned long flags;
1763 netif_warn(tp, tx_err, netdev,
1764 "failed tx_urb %d\n", res);
1765 stats->tx_dropped += agg->skb_num;
1767 spin_lock_irqsave(&tp->tx_lock, flags);
1768 list_add_tail(&agg->list, &tp->tx_free);
1769 spin_unlock_irqrestore(&tp->tx_lock, flags);
1775 static void bottom_half(unsigned long data)
1779 tp = (struct r8152 *)data;
1781 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1784 if (!test_bit(WORK_ENABLE, &tp->flags))
1787 /* When link down, the driver would cancel all bulks. */
1788 /* This avoid the re-submitting bulk */
1789 if (!netif_carrier_ok(tp->netdev))
1797 int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags)
1799 usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1),
1800 agg->head, agg_buf_sz,
1801 (usb_complete_t)read_bulk_callback, agg);
1803 return usb_submit_urb(agg->urb, mem_flags);
1806 static void rtl_drop_queued_tx(struct r8152 *tp)
1808 struct net_device_stats *stats = &tp->netdev->stats;
1809 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
1810 struct sk_buff *skb;
1812 if (skb_queue_empty(tx_queue))
1815 __skb_queue_head_init(&skb_head);
1816 spin_lock_bh(&tx_queue->lock);
1817 skb_queue_splice_init(tx_queue, &skb_head);
1818 spin_unlock_bh(&tx_queue->lock);
1820 while ((skb = __skb_dequeue(&skb_head))) {
1822 stats->tx_dropped++;
1826 static void rtl8152_tx_timeout(struct net_device *netdev)
1828 struct r8152 *tp = netdev_priv(netdev);
1831 netif_warn(tp, tx_err, netdev, "Tx timeout\n");
1832 for (i = 0; i < RTL8152_MAX_TX; i++)
1833 usb_unlink_urb(tp->tx_info[i].urb);
1836 static void rtl8152_set_rx_mode(struct net_device *netdev)
1838 struct r8152 *tp = netdev_priv(netdev);
1840 if (tp->speed & LINK_STATUS) {
1841 set_bit(RTL8152_SET_RX_MODE, &tp->flags);
1842 schedule_delayed_work(&tp->schedule, 0);
1846 static void _rtl8152_set_rx_mode(struct net_device *netdev)
1848 struct r8152 *tp = netdev_priv(netdev);
1849 u32 mc_filter[2]; /* Multicast hash filter */
1853 clear_bit(RTL8152_SET_RX_MODE, &tp->flags);
1854 netif_stop_queue(netdev);
1855 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
1856 ocp_data &= ~RCR_ACPT_ALL;
1857 ocp_data |= RCR_AB | RCR_APM;
1859 if (netdev->flags & IFF_PROMISC) {
1860 /* Unconditionally log net taps. */
1861 netif_notice(tp, link, netdev, "Promiscuous mode enabled\n");
1862 ocp_data |= RCR_AM | RCR_AAP;
1863 mc_filter[1] = 0xffffffff;
1864 mc_filter[0] = 0xffffffff;
1865 } else if ((netdev_mc_count(netdev) > multicast_filter_limit) ||
1866 (netdev->flags & IFF_ALLMULTI)) {
1867 /* Too many to filter perfectly -- accept all multicasts. */
1869 mc_filter[1] = 0xffffffff;
1870 mc_filter[0] = 0xffffffff;
1872 struct netdev_hw_addr *ha;
1876 netdev_for_each_mc_addr(ha, netdev) {
1877 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
1879 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
1884 tmp[0] = __cpu_to_le32(swab32(mc_filter[1]));
1885 tmp[1] = __cpu_to_le32(swab32(mc_filter[0]));
1887 pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp);
1888 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
1889 netif_wake_queue(netdev);
1892 static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb,
1893 struct net_device *netdev)
1895 struct r8152 *tp = netdev_priv(netdev);
1897 skb_tx_timestamp(skb);
1899 skb_queue_tail(&tp->tx_queue, skb);
1901 if (!list_empty(&tp->tx_free)) {
1902 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
1903 set_bit(SCHEDULE_TASKLET, &tp->flags);
1904 schedule_delayed_work(&tp->schedule, 0);
1906 usb_mark_last_busy(tp->udev);
1907 tasklet_schedule(&tp->tl);
1909 } else if (skb_queue_len(&tp->tx_queue) > tp->tx_qlen) {
1910 netif_stop_queue(netdev);
1913 return NETDEV_TX_OK;
1916 static void r8152b_reset_packet_filter(struct r8152 *tp)
1920 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC);
1921 ocp_data &= ~FMC_FCR_MCU_EN;
1922 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
1923 ocp_data |= FMC_FCR_MCU_EN;
1924 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
1927 static void rtl8152_nic_reset(struct r8152 *tp)
1931 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST);
1933 for (i = 0; i < 1000; i++) {
1934 if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST))
1936 usleep_range(100, 400);
1940 static void set_tx_qlen(struct r8152 *tp)
1942 struct net_device *netdev = tp->netdev;
1944 tp->tx_qlen = agg_buf_sz / (netdev->mtu + VLAN_ETH_HLEN + VLAN_HLEN +
1945 sizeof(struct tx_desc));
1948 static inline u8 rtl8152_get_speed(struct r8152 *tp)
1950 return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS);
1953 static void rtl_set_eee_plus(struct r8152 *tp)
1958 speed = rtl8152_get_speed(tp);
1959 if (speed & _10bps) {
1960 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
1961 ocp_data |= EEEP_CR_EEEP_TX;
1962 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
1964 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
1965 ocp_data &= ~EEEP_CR_EEEP_TX;
1966 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
1970 static void rxdy_gated_en(struct r8152 *tp, bool enable)
1974 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
1976 ocp_data |= RXDY_GATED_EN;
1978 ocp_data &= ~RXDY_GATED_EN;
1979 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
1982 static int rtl_start_rx(struct r8152 *tp)
1986 INIT_LIST_HEAD(&tp->rx_done);
1987 for (i = 0; i < RTL8152_MAX_RX; i++) {
1988 INIT_LIST_HEAD(&tp->rx_info[i].list);
1989 ret = r8152_submit_rx(tp, &tp->rx_info[i], GFP_KERNEL);
1997 static int rtl_stop_rx(struct r8152 *tp)
2001 for (i = 0; i < RTL8152_MAX_RX; i++)
2002 usb_kill_urb(tp->rx_info[i].urb);
2007 static int rtl_enable(struct r8152 *tp)
2011 r8152b_reset_packet_filter(tp);
2013 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
2014 ocp_data |= CR_RE | CR_TE;
2015 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
2017 rxdy_gated_en(tp, false);
2019 return rtl_start_rx(tp);
2022 static int rtl8152_enable(struct r8152 *tp)
2024 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2028 rtl_set_eee_plus(tp);
2030 return rtl_enable(tp);
2033 static void r8153_set_rx_agg(struct r8152 *tp)
2037 speed = rtl8152_get_speed(tp);
2038 if (speed & _1000bps) {
2039 if (tp->udev->speed == USB_SPEED_SUPER) {
2040 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH,
2042 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_EARLY_AGG,
2045 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH,
2047 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_EARLY_AGG,
2051 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_SLOW);
2052 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_EARLY_AGG,
2057 static int rtl8153_enable(struct r8152 *tp)
2059 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2063 rtl_set_eee_plus(tp);
2064 r8153_set_rx_agg(tp);
2066 return rtl_enable(tp);
2069 static void rtl_disable(struct r8152 *tp)
2074 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
2075 rtl_drop_queued_tx(tp);
2079 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2080 ocp_data &= ~RCR_ACPT_ALL;
2081 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2083 rtl_drop_queued_tx(tp);
2085 for (i = 0; i < RTL8152_MAX_TX; i++)
2086 usb_kill_urb(tp->tx_info[i].urb);
2088 rxdy_gated_en(tp, true);
2090 for (i = 0; i < 1000; i++) {
2091 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2092 if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY)
2094 usleep_range(1000, 2000);
2097 for (i = 0; i < 1000; i++) {
2098 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY)
2100 usleep_range(1000, 2000);
2105 rtl8152_nic_reset(tp);
2108 static void r8152_power_cut_en(struct r8152 *tp, bool enable)
2112 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
2114 ocp_data |= POWER_CUT;
2116 ocp_data &= ~POWER_CUT;
2117 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
2119 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
2120 ocp_data &= ~RESUME_INDICATE;
2121 ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
2124 static void rtl_rx_vlan_en(struct r8152 *tp, bool enable)
2128 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
2130 ocp_data |= CPCR_RX_VLAN;
2132 ocp_data &= ~CPCR_RX_VLAN;
2133 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
2136 static int rtl8152_set_features(struct net_device *dev,
2137 netdev_features_t features)
2139 netdev_features_t changed = features ^ dev->features;
2140 struct r8152 *tp = netdev_priv(dev);
2142 if (changed & NETIF_F_HW_VLAN_CTAG_RX) {
2143 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2144 rtl_rx_vlan_en(tp, true);
2146 rtl_rx_vlan_en(tp, false);
2152 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
2154 static u32 __rtl_get_wol(struct r8152 *tp)
2159 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2160 if (!(ocp_data & LAN_WAKE_EN))
2163 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2164 if (ocp_data & LINK_ON_WAKE_EN)
2165 wolopts |= WAKE_PHY;
2167 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2168 if (ocp_data & UWF_EN)
2169 wolopts |= WAKE_UCAST;
2170 if (ocp_data & BWF_EN)
2171 wolopts |= WAKE_BCAST;
2172 if (ocp_data & MWF_EN)
2173 wolopts |= WAKE_MCAST;
2175 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
2176 if (ocp_data & MAGIC_EN)
2177 wolopts |= WAKE_MAGIC;
2182 static void __rtl_set_wol(struct r8152 *tp, u32 wolopts)
2186 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
2188 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2189 ocp_data &= ~LINK_ON_WAKE_EN;
2190 if (wolopts & WAKE_PHY)
2191 ocp_data |= LINK_ON_WAKE_EN;
2192 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
2194 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2195 ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN | LAN_WAKE_EN);
2196 if (wolopts & WAKE_UCAST)
2198 if (wolopts & WAKE_BCAST)
2200 if (wolopts & WAKE_MCAST)
2202 if (wolopts & WAKE_ANY)
2203 ocp_data |= LAN_WAKE_EN;
2204 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data);
2206 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2208 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
2209 ocp_data &= ~MAGIC_EN;
2210 if (wolopts & WAKE_MAGIC)
2211 ocp_data |= MAGIC_EN;
2212 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data);
2214 if (wolopts & WAKE_ANY)
2215 device_set_wakeup_enable(&tp->udev->dev, true);
2217 device_set_wakeup_enable(&tp->udev->dev, false);
2220 static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable)
2225 __rtl_set_wol(tp, WAKE_ANY);
2227 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
2229 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2230 ocp_data |= LINK_OFF_WAKE_EN;
2231 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
2233 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2235 __rtl_set_wol(tp, tp->saved_wolopts);
2239 static void rtl_phy_reset(struct r8152 *tp)
2244 clear_bit(PHY_RESET, &tp->flags);
2246 data = r8152_mdio_read(tp, MII_BMCR);
2248 /* don't reset again before the previous one complete */
2249 if (data & BMCR_RESET)
2253 r8152_mdio_write(tp, MII_BMCR, data);
2255 for (i = 0; i < 50; i++) {
2257 if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0)
2262 static void r8153_teredo_off(struct r8152 *tp)
2266 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
2267 ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK | OOB_TEREDO_EN);
2268 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
2270 ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE);
2271 ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0);
2272 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0);
2275 static void r8152b_disable_aldps(struct r8152 *tp)
2277 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA | DIS_SDSAVE);
2281 static inline void r8152b_enable_aldps(struct r8152 *tp)
2283 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS |
2284 LINKENA | DIS_SDSAVE);
2287 static void rtl8152_disable(struct r8152 *tp)
2289 r8152b_disable_aldps(tp);
2291 r8152b_enable_aldps(tp);
2294 static void r8152b_hw_phy_cfg(struct r8152 *tp)
2298 data = r8152_mdio_read(tp, MII_BMCR);
2299 if (data & BMCR_PDOWN) {
2300 data &= ~BMCR_PDOWN;
2301 r8152_mdio_write(tp, MII_BMCR, data);
2304 set_bit(PHY_RESET, &tp->flags);
2307 static void r8152b_exit_oob(struct r8152 *tp)
2312 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2313 ocp_data &= ~RCR_ACPT_ALL;
2314 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2316 rxdy_gated_en(tp, true);
2317 r8153_teredo_off(tp);
2318 r8152b_hw_phy_cfg(tp);
2320 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2321 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00);
2323 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2324 ocp_data &= ~NOW_IS_OOB;
2325 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2327 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2328 ocp_data &= ~MCU_BORW_EN;
2329 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2331 for (i = 0; i < 1000; i++) {
2332 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2333 if (ocp_data & LINK_LIST_READY)
2335 usleep_range(1000, 2000);
2338 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2339 ocp_data |= RE_INIT_LL;
2340 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2342 for (i = 0; i < 1000; i++) {
2343 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2344 if (ocp_data & LINK_LIST_READY)
2346 usleep_range(1000, 2000);
2349 rtl8152_nic_reset(tp);
2351 /* rx share fifo credit full threshold */
2352 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
2354 if (tp->udev->speed == USB_SPEED_FULL ||
2355 tp->udev->speed == USB_SPEED_LOW) {
2356 /* rx share fifo credit near full threshold */
2357 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
2359 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
2362 /* rx share fifo credit near full threshold */
2363 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
2365 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
2369 /* TX share fifo free credit full threshold */
2370 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL);
2372 ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD);
2373 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH);
2374 ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA,
2375 TEST_MODE_DISABLE | TX_SIZE_ADJUST1);
2377 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
2379 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
2381 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
2382 ocp_data |= TCR0_AUTO_FIFO;
2383 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
2386 static void r8152b_enter_oob(struct r8152 *tp)
2391 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2392 ocp_data &= ~NOW_IS_OOB;
2393 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2395 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
2396 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);
2397 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);
2401 for (i = 0; i < 1000; i++) {
2402 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2403 if (ocp_data & LINK_LIST_READY)
2405 usleep_range(1000, 2000);
2408 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2409 ocp_data |= RE_INIT_LL;
2410 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2412 for (i = 0; i < 1000; i++) {
2413 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2414 if (ocp_data & LINK_LIST_READY)
2416 usleep_range(1000, 2000);
2419 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
2421 rtl_rx_vlan_en(tp, true);
2423 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
2424 ocp_data |= ALDPS_PROXY_MODE;
2425 ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
2427 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2428 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
2429 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2431 rxdy_gated_en(tp, false);
2433 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2434 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
2435 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2438 static void r8153_hw_phy_cfg(struct r8152 *tp)
2443 ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L);
2444 data = r8152_mdio_read(tp, MII_BMCR);
2445 if (data & BMCR_PDOWN) {
2446 data &= ~BMCR_PDOWN;
2447 r8152_mdio_write(tp, MII_BMCR, data);
2450 if (tp->version == RTL_VER_03) {
2451 data = ocp_reg_read(tp, OCP_EEE_CFG);
2452 data &= ~CTAP_SHORT_EN;
2453 ocp_reg_write(tp, OCP_EEE_CFG, data);
2456 data = ocp_reg_read(tp, OCP_POWER_CFG);
2457 data |= EEE_CLKDIV_EN;
2458 ocp_reg_write(tp, OCP_POWER_CFG, data);
2460 data = ocp_reg_read(tp, OCP_DOWN_SPEED);
2461 data |= EN_10M_BGOFF;
2462 ocp_reg_write(tp, OCP_DOWN_SPEED, data);
2463 data = ocp_reg_read(tp, OCP_POWER_CFG);
2464 data |= EN_10M_PLLOFF;
2465 ocp_reg_write(tp, OCP_POWER_CFG, data);
2466 data = sram_read(tp, SRAM_IMPEDANCE);
2467 data &= ~RX_DRIVING_MASK;
2468 sram_write(tp, SRAM_IMPEDANCE, data);
2470 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
2471 ocp_data |= PFM_PWM_SWITCH;
2472 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
2474 data = sram_read(tp, SRAM_LPF_CFG);
2475 data |= LPF_AUTO_TUNE;
2476 sram_write(tp, SRAM_LPF_CFG, data);
2478 data = sram_read(tp, SRAM_10M_AMP1);
2479 data |= GDAC_IB_UPALL;
2480 sram_write(tp, SRAM_10M_AMP1, data);
2481 data = sram_read(tp, SRAM_10M_AMP2);
2483 sram_write(tp, SRAM_10M_AMP2, data);
2485 set_bit(PHY_RESET, &tp->flags);
2488 static void r8153_u1u2en(struct r8152 *tp, bool enable)
2493 memset(u1u2, 0xff, sizeof(u1u2));
2495 memset(u1u2, 0x00, sizeof(u1u2));
2497 usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2);
2500 static void r8153_u2p3en(struct r8152 *tp, bool enable)
2504 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);
2506 ocp_data |= U2P3_ENABLE;
2508 ocp_data &= ~U2P3_ENABLE;
2509 ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data);
2512 static void r8153_power_cut_en(struct r8152 *tp, bool enable)
2516 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
2518 ocp_data |= PWR_EN | PHASE2_EN;
2520 ocp_data &= ~(PWR_EN | PHASE2_EN);
2521 ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
2523 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
2524 ocp_data &= ~PCUT_STATUS;
2525 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
2528 static void r8153_first_init(struct r8152 *tp)
2533 rxdy_gated_en(tp, true);
2534 r8153_teredo_off(tp);
2536 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2537 ocp_data &= ~RCR_ACPT_ALL;
2538 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2540 r8153_hw_phy_cfg(tp);
2542 rtl8152_nic_reset(tp);
2544 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2545 ocp_data &= ~NOW_IS_OOB;
2546 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2548 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2549 ocp_data &= ~MCU_BORW_EN;
2550 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2552 for (i = 0; i < 1000; i++) {
2553 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2554 if (ocp_data & LINK_LIST_READY)
2556 usleep_range(1000, 2000);
2559 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2560 ocp_data |= RE_INIT_LL;
2561 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2563 for (i = 0; i < 1000; i++) {
2564 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2565 if (ocp_data & LINK_LIST_READY)
2567 usleep_range(1000, 2000);
2570 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
2572 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8153_RMS);
2573 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO);
2575 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
2576 ocp_data |= TCR0_AUTO_FIFO;
2577 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
2579 rtl8152_nic_reset(tp);
2581 /* rx share fifo credit full threshold */
2582 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
2583 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL);
2584 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL);
2585 /* TX share fifo free credit full threshold */
2586 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2);
2588 /* rx aggregation */
2589 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
2590 ocp_data &= ~RX_AGG_DISABLE;
2591 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
2594 static void r8153_enter_oob(struct r8152 *tp)
2599 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2600 ocp_data &= ~NOW_IS_OOB;
2601 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2605 for (i = 0; i < 1000; i++) {
2606 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2607 if (ocp_data & LINK_LIST_READY)
2609 usleep_range(1000, 2000);
2612 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2613 ocp_data |= RE_INIT_LL;
2614 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2616 for (i = 0; i < 1000; i++) {
2617 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2618 if (ocp_data & LINK_LIST_READY)
2620 usleep_range(1000, 2000);
2623 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8153_RMS);
2625 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
2626 ocp_data &= ~TEREDO_WAKE_MASK;
2627 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
2629 rtl_rx_vlan_en(tp, true);
2631 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
2632 ocp_data |= ALDPS_PROXY_MODE;
2633 ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
2635 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2636 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
2637 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2639 rxdy_gated_en(tp, false);
2641 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2642 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
2643 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2646 static void r8153_disable_aldps(struct r8152 *tp)
2650 data = ocp_reg_read(tp, OCP_POWER_CFG);
2652 ocp_reg_write(tp, OCP_POWER_CFG, data);
2656 static void r8153_enable_aldps(struct r8152 *tp)
2660 data = ocp_reg_read(tp, OCP_POWER_CFG);
2662 ocp_reg_write(tp, OCP_POWER_CFG, data);
2665 static void rtl8153_disable(struct r8152 *tp)
2667 r8153_disable_aldps(tp);
2669 r8153_enable_aldps(tp);
2672 static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex)
2674 u16 bmcr, anar, gbcr;
2677 cancel_delayed_work_sync(&tp->schedule);
2678 anar = r8152_mdio_read(tp, MII_ADVERTISE);
2679 anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
2680 ADVERTISE_100HALF | ADVERTISE_100FULL);
2681 if (tp->mii.supports_gmii) {
2682 gbcr = r8152_mdio_read(tp, MII_CTRL1000);
2683 gbcr &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
2688 if (autoneg == AUTONEG_DISABLE) {
2689 if (speed == SPEED_10) {
2691 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
2692 } else if (speed == SPEED_100) {
2693 bmcr = BMCR_SPEED100;
2694 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
2695 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) {
2696 bmcr = BMCR_SPEED1000;
2697 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
2703 if (duplex == DUPLEX_FULL)
2704 bmcr |= BMCR_FULLDPLX;
2706 if (speed == SPEED_10) {
2707 if (duplex == DUPLEX_FULL)
2708 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
2710 anar |= ADVERTISE_10HALF;
2711 } else if (speed == SPEED_100) {
2712 if (duplex == DUPLEX_FULL) {
2713 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
2714 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
2716 anar |= ADVERTISE_10HALF;
2717 anar |= ADVERTISE_100HALF;
2719 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) {
2720 if (duplex == DUPLEX_FULL) {
2721 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
2722 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
2723 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
2725 anar |= ADVERTISE_10HALF;
2726 anar |= ADVERTISE_100HALF;
2727 gbcr |= ADVERTISE_1000HALF;
2734 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
2737 if (test_bit(PHY_RESET, &tp->flags))
2740 if (tp->mii.supports_gmii)
2741 r8152_mdio_write(tp, MII_CTRL1000, gbcr);
2743 r8152_mdio_write(tp, MII_ADVERTISE, anar);
2744 r8152_mdio_write(tp, MII_BMCR, bmcr);
2746 if (test_bit(PHY_RESET, &tp->flags)) {
2749 clear_bit(PHY_RESET, &tp->flags);
2750 for (i = 0; i < 50; i++) {
2752 if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0)
2762 static void rtl8152_up(struct r8152 *tp)
2764 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2767 r8152b_disable_aldps(tp);
2768 r8152b_exit_oob(tp);
2769 r8152b_enable_aldps(tp);
2772 static void rtl8152_down(struct r8152 *tp)
2774 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
2775 rtl_drop_queued_tx(tp);
2779 r8152_power_cut_en(tp, false);
2780 r8152b_disable_aldps(tp);
2781 r8152b_enter_oob(tp);
2782 r8152b_enable_aldps(tp);
2785 static void rtl8153_up(struct r8152 *tp)
2787 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2790 r8153_disable_aldps(tp);
2791 r8153_first_init(tp);
2792 r8153_enable_aldps(tp);
2795 static void rtl8153_down(struct r8152 *tp)
2797 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
2798 rtl_drop_queued_tx(tp);
2802 r8153_u1u2en(tp, false);
2803 r8153_power_cut_en(tp, false);
2804 r8153_disable_aldps(tp);
2805 r8153_enter_oob(tp);
2806 r8153_enable_aldps(tp);
2809 static void set_carrier(struct r8152 *tp)
2811 struct net_device *netdev = tp->netdev;
2814 clear_bit(RTL8152_LINK_CHG, &tp->flags);
2815 speed = rtl8152_get_speed(tp);
2817 if (speed & LINK_STATUS) {
2818 if (!(tp->speed & LINK_STATUS)) {
2819 tp->rtl_ops.enable(tp);
2820 set_bit(RTL8152_SET_RX_MODE, &tp->flags);
2821 netif_carrier_on(netdev);
2824 if (tp->speed & LINK_STATUS) {
2825 netif_carrier_off(netdev);
2826 tasklet_disable(&tp->tl);
2827 tp->rtl_ops.disable(tp);
2828 tasklet_enable(&tp->tl);
2834 static void rtl_work_func_t(struct work_struct *work)
2836 struct r8152 *tp = container_of(work, struct r8152, schedule.work);
2838 if (usb_autopm_get_interface(tp->intf) < 0)
2841 if (!test_bit(WORK_ENABLE, &tp->flags))
2844 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2847 if (test_bit(RTL8152_LINK_CHG, &tp->flags))
2850 if (test_bit(RTL8152_SET_RX_MODE, &tp->flags))
2851 _rtl8152_set_rx_mode(tp->netdev);
2853 if (test_bit(SCHEDULE_TASKLET, &tp->flags) &&
2854 (tp->speed & LINK_STATUS)) {
2855 clear_bit(SCHEDULE_TASKLET, &tp->flags);
2856 tasklet_schedule(&tp->tl);
2859 if (test_bit(PHY_RESET, &tp->flags))
2863 usb_autopm_put_interface(tp->intf);
2866 static int rtl8152_open(struct net_device *netdev)
2868 struct r8152 *tp = netdev_priv(netdev);
2871 res = alloc_all_mem(tp);
2875 res = usb_autopm_get_interface(tp->intf);
2881 /* The WORK_ENABLE may be set when autoresume occurs */
2882 if (test_bit(WORK_ENABLE, &tp->flags)) {
2883 clear_bit(WORK_ENABLE, &tp->flags);
2884 usb_kill_urb(tp->intr_urb);
2885 cancel_delayed_work_sync(&tp->schedule);
2886 if (tp->speed & LINK_STATUS)
2887 tp->rtl_ops.disable(tp);
2892 rtl8152_set_speed(tp, AUTONEG_ENABLE,
2893 tp->mii.supports_gmii ? SPEED_1000 : SPEED_100,
2896 netif_carrier_off(netdev);
2897 netif_start_queue(netdev);
2898 set_bit(WORK_ENABLE, &tp->flags);
2900 res = usb_submit_urb(tp->intr_urb, GFP_KERNEL);
2903 netif_device_detach(tp->netdev);
2904 netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n",
2909 usb_autopm_put_interface(tp->intf);
2915 static int rtl8152_close(struct net_device *netdev)
2917 struct r8152 *tp = netdev_priv(netdev);
2920 clear_bit(WORK_ENABLE, &tp->flags);
2921 usb_kill_urb(tp->intr_urb);
2922 cancel_delayed_work_sync(&tp->schedule);
2923 netif_stop_queue(netdev);
2925 res = usb_autopm_get_interface(tp->intf);
2927 rtl_drop_queued_tx(tp);
2929 /* The autosuspend may have been enabled and wouldn't
2930 * be disable when autoresume occurs, because the
2931 * netif_running() would be false.
2933 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
2934 rtl_runtime_suspend_enable(tp, false);
2935 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
2938 tasklet_disable(&tp->tl);
2939 tp->rtl_ops.down(tp);
2940 tasklet_enable(&tp->tl);
2941 usb_autopm_put_interface(tp->intf);
2949 static inline void r8152_mmd_indirect(struct r8152 *tp, u16 dev, u16 reg)
2951 ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | dev);
2952 ocp_reg_write(tp, OCP_EEE_DATA, reg);
2953 ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | dev);
2956 static u16 r8152_mmd_read(struct r8152 *tp, u16 dev, u16 reg)
2960 r8152_mmd_indirect(tp, dev, reg);
2961 data = ocp_reg_read(tp, OCP_EEE_DATA);
2962 ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
2967 static void r8152_mmd_write(struct r8152 *tp, u16 dev, u16 reg, u16 data)
2969 r8152_mmd_indirect(tp, dev, reg);
2970 ocp_reg_write(tp, OCP_EEE_DATA, data);
2971 ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
2974 static void r8152_eee_en(struct r8152 *tp, bool enable)
2976 u16 config1, config2, config3;
2979 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
2980 config1 = ocp_reg_read(tp, OCP_EEE_CONFIG1) & ~sd_rise_time_mask;
2981 config2 = ocp_reg_read(tp, OCP_EEE_CONFIG2);
2982 config3 = ocp_reg_read(tp, OCP_EEE_CONFIG3) & ~fast_snr_mask;
2985 ocp_data |= EEE_RX_EN | EEE_TX_EN;
2986 config1 |= EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | RX_QUIET_EN;
2987 config1 |= sd_rise_time(1);
2988 config2 |= RG_DACQUIET_EN | RG_LDVQUIET_EN;
2989 config3 |= fast_snr(42);
2991 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
2992 config1 &= ~(EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN |
2994 config1 |= sd_rise_time(7);
2995 config2 &= ~(RG_DACQUIET_EN | RG_LDVQUIET_EN);
2996 config3 |= fast_snr(511);
2999 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
3000 ocp_reg_write(tp, OCP_EEE_CONFIG1, config1);
3001 ocp_reg_write(tp, OCP_EEE_CONFIG2, config2);
3002 ocp_reg_write(tp, OCP_EEE_CONFIG3, config3);
3005 static void r8152b_enable_eee(struct r8152 *tp)
3007 r8152_eee_en(tp, true);
3008 r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, MDIO_EEE_100TX);
3011 static void r8153_eee_en(struct r8152 *tp, bool enable)
3016 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
3017 config = ocp_reg_read(tp, OCP_EEE_CFG);
3020 ocp_data |= EEE_RX_EN | EEE_TX_EN;
3023 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
3024 config &= ~EEE10_EN;
3027 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
3028 ocp_reg_write(tp, OCP_EEE_CFG, config);
3031 static void r8153_enable_eee(struct r8152 *tp)
3033 r8153_eee_en(tp, true);
3034 ocp_reg_write(tp, OCP_EEE_ADV, MDIO_EEE_1000T | MDIO_EEE_100TX);
3037 static void r8152b_enable_fc(struct r8152 *tp)
3041 anar = r8152_mdio_read(tp, MII_ADVERTISE);
3042 anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
3043 r8152_mdio_write(tp, MII_ADVERTISE, anar);
3046 static void rtl_tally_reset(struct r8152 *tp)
3050 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY);
3051 ocp_data |= TALLY_RESET;
3052 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data);
3055 static void r8152b_init(struct r8152 *tp)
3059 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3062 r8152b_disable_aldps(tp);
3064 if (tp->version == RTL_VER_01) {
3065 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
3066 ocp_data &= ~LED_MODE_MASK;
3067 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
3070 r8152_power_cut_en(tp, false);
3072 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
3073 ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH;
3074 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
3075 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL);
3076 ocp_data &= ~MCU_CLK_RATIO_MASK;
3077 ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN;
3078 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data);
3079 ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK |
3080 SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK;
3081 ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data);
3083 r8152b_enable_eee(tp);
3084 r8152b_enable_aldps(tp);
3085 r8152b_enable_fc(tp);
3086 rtl_tally_reset(tp);
3088 /* enable rx aggregation */
3089 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
3090 ocp_data &= ~RX_AGG_DISABLE;
3091 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
3094 static void r8153_init(struct r8152 *tp)
3099 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3102 r8153_disable_aldps(tp);
3103 r8153_u1u2en(tp, false);
3105 for (i = 0; i < 500; i++) {
3106 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
3112 for (i = 0; i < 500; i++) {
3113 ocp_data = ocp_reg_read(tp, OCP_PHY_STATUS) & PHY_STAT_MASK;
3114 if (ocp_data == PHY_STAT_LAN_ON || ocp_data == PHY_STAT_PWRDN)
3119 r8153_u2p3en(tp, false);
3121 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL);
3122 ocp_data &= ~TIMER11_EN;
3123 ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data);
3125 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
3126 ocp_data &= ~LED_MODE_MASK;
3127 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
3129 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL);
3130 ocp_data &= ~LPM_TIMER_MASK;
3131 if (tp->udev->speed == USB_SPEED_SUPER)
3132 ocp_data |= LPM_TIMER_500US;
3134 ocp_data |= LPM_TIMER_500MS;
3135 ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data);
3137 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2);
3138 ocp_data &= ~SEN_VAL_MASK;
3139 ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE;
3140 ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data);
3142 r8153_power_cut_en(tp, false);
3143 r8153_u1u2en(tp, true);
3145 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ALDPS_SPDWN_RATIO);
3146 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, EEE_SPDWN_RATIO);
3147 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3,
3148 PKT_AVAIL_SPDWN_EN | SUSPEND_SPDWN_EN |
3149 U1U2_SPDWN_EN | L1_SPDWN_EN);
3150 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4,
3151 PWRSAVE_SPDWN_EN | RXDV_SPDWN_EN | TX10MIDLE_EN |
3152 TP100_SPDWN_EN | TP500_SPDWN_EN | TP1000_SPDWN_EN |
3155 r8153_enable_eee(tp);
3156 r8153_enable_aldps(tp);
3157 r8152b_enable_fc(tp);
3158 rtl_tally_reset(tp);
3161 static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message)
3163 struct r8152 *tp = usb_get_intfdata(intf);
3165 if (PMSG_IS_AUTO(message))
3166 set_bit(SELECTIVE_SUSPEND, &tp->flags);
3168 netif_device_detach(tp->netdev);
3170 if (netif_running(tp->netdev)) {
3171 clear_bit(WORK_ENABLE, &tp->flags);
3172 usb_kill_urb(tp->intr_urb);
3173 cancel_delayed_work_sync(&tp->schedule);
3174 tasklet_disable(&tp->tl);
3175 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
3177 rtl_runtime_suspend_enable(tp, true);
3179 tp->rtl_ops.down(tp);
3181 tasklet_enable(&tp->tl);
3187 static int rtl8152_resume(struct usb_interface *intf)
3189 struct r8152 *tp = usb_get_intfdata(intf);
3191 if (!test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
3192 tp->rtl_ops.init(tp);
3193 netif_device_attach(tp->netdev);
3196 if (netif_running(tp->netdev)) {
3197 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
3198 rtl_runtime_suspend_enable(tp, false);
3199 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
3200 set_bit(WORK_ENABLE, &tp->flags);
3201 if (tp->speed & LINK_STATUS)
3205 rtl8152_set_speed(tp, AUTONEG_ENABLE,
3206 tp->mii.supports_gmii ?
3207 SPEED_1000 : SPEED_100,
3210 netif_carrier_off(tp->netdev);
3211 set_bit(WORK_ENABLE, &tp->flags);
3213 usb_submit_urb(tp->intr_urb, GFP_KERNEL);
3219 static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3221 struct r8152 *tp = netdev_priv(dev);
3223 if (usb_autopm_get_interface(tp->intf) < 0)
3226 wol->supported = WAKE_ANY;
3227 wol->wolopts = __rtl_get_wol(tp);
3229 usb_autopm_put_interface(tp->intf);
3232 static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3234 struct r8152 *tp = netdev_priv(dev);
3237 ret = usb_autopm_get_interface(tp->intf);
3241 __rtl_set_wol(tp, wol->wolopts);
3242 tp->saved_wolopts = wol->wolopts & WAKE_ANY;
3244 usb_autopm_put_interface(tp->intf);
3250 static u32 rtl8152_get_msglevel(struct net_device *dev)
3252 struct r8152 *tp = netdev_priv(dev);
3254 return tp->msg_enable;
3257 static void rtl8152_set_msglevel(struct net_device *dev, u32 value)
3259 struct r8152 *tp = netdev_priv(dev);
3261 tp->msg_enable = value;
3264 static void rtl8152_get_drvinfo(struct net_device *netdev,
3265 struct ethtool_drvinfo *info)
3267 struct r8152 *tp = netdev_priv(netdev);
3269 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
3270 strlcpy(info->version, DRIVER_VERSION, sizeof(info->version));
3271 usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info));
3275 int rtl8152_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
3277 struct r8152 *tp = netdev_priv(netdev);
3279 if (!tp->mii.mdio_read)
3282 return mii_ethtool_gset(&tp->mii, cmd);
3285 static int rtl8152_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
3287 struct r8152 *tp = netdev_priv(dev);
3290 ret = usb_autopm_get_interface(tp->intf);
3294 ret = rtl8152_set_speed(tp, cmd->autoneg, cmd->speed, cmd->duplex);
3296 usb_autopm_put_interface(tp->intf);
3302 static const char rtl8152_gstrings[][ETH_GSTRING_LEN] = {
3309 "tx_single_collisions",
3310 "tx_multi_collisions",
3318 static int rtl8152_get_sset_count(struct net_device *dev, int sset)
3322 return ARRAY_SIZE(rtl8152_gstrings);
3328 static void rtl8152_get_ethtool_stats(struct net_device *dev,
3329 struct ethtool_stats *stats, u64 *data)
3331 struct r8152 *tp = netdev_priv(dev);
3332 struct tally_counter tally;
3334 if (usb_autopm_get_interface(tp->intf) < 0)
3337 generic_ocp_read(tp, PLA_TALLYCNT, sizeof(tally), &tally, MCU_TYPE_PLA);
3339 usb_autopm_put_interface(tp->intf);
3341 data[0] = le64_to_cpu(tally.tx_packets);
3342 data[1] = le64_to_cpu(tally.rx_packets);
3343 data[2] = le64_to_cpu(tally.tx_errors);
3344 data[3] = le32_to_cpu(tally.rx_errors);
3345 data[4] = le16_to_cpu(tally.rx_missed);
3346 data[5] = le16_to_cpu(tally.align_errors);
3347 data[6] = le32_to_cpu(tally.tx_one_collision);
3348 data[7] = le32_to_cpu(tally.tx_multi_collision);
3349 data[8] = le64_to_cpu(tally.rx_unicast);
3350 data[9] = le64_to_cpu(tally.rx_broadcast);
3351 data[10] = le32_to_cpu(tally.rx_multicast);
3352 data[11] = le16_to_cpu(tally.tx_aborted);
3353 data[12] = le16_to_cpu(tally.tx_underun);
3356 static void rtl8152_get_strings(struct net_device *dev, u32 stringset, u8 *data)
3358 switch (stringset) {
3360 memcpy(data, *rtl8152_gstrings, sizeof(rtl8152_gstrings));
3365 static int r8152_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
3367 u32 ocp_data, lp, adv, supported = 0;
3370 val = r8152_mmd_read(tp, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
3371 supported = mmd_eee_cap_to_ethtool_sup_t(val);
3373 val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
3374 adv = mmd_eee_adv_to_ethtool_adv_t(val);
3376 val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE);
3377 lp = mmd_eee_adv_to_ethtool_adv_t(val);
3379 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
3380 ocp_data &= EEE_RX_EN | EEE_TX_EN;
3382 eee->eee_enabled = !!ocp_data;
3383 eee->eee_active = !!(supported & adv & lp);
3384 eee->supported = supported;
3385 eee->advertised = adv;
3386 eee->lp_advertised = lp;
3391 static int r8152_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
3393 u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
3395 r8152_eee_en(tp, eee->eee_enabled);
3397 if (!eee->eee_enabled)
3400 r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
3405 static int r8153_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
3407 u32 ocp_data, lp, adv, supported = 0;
3410 val = ocp_reg_read(tp, OCP_EEE_ABLE);
3411 supported = mmd_eee_cap_to_ethtool_sup_t(val);
3413 val = ocp_reg_read(tp, OCP_EEE_ADV);
3414 adv = mmd_eee_adv_to_ethtool_adv_t(val);
3416 val = ocp_reg_read(tp, OCP_EEE_LPABLE);
3417 lp = mmd_eee_adv_to_ethtool_adv_t(val);
3419 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
3420 ocp_data &= EEE_RX_EN | EEE_TX_EN;
3422 eee->eee_enabled = !!ocp_data;
3423 eee->eee_active = !!(supported & adv & lp);
3424 eee->supported = supported;
3425 eee->advertised = adv;
3426 eee->lp_advertised = lp;
3431 static int r8153_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
3433 u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
3435 r8153_eee_en(tp, eee->eee_enabled);
3437 if (!eee->eee_enabled)
3440 ocp_reg_write(tp, OCP_EEE_ADV, val);
3446 rtl_ethtool_get_eee(struct net_device *net, struct ethtool_eee *edata)
3448 struct r8152 *tp = netdev_priv(net);
3451 ret = usb_autopm_get_interface(tp->intf);
3455 ret = tp->rtl_ops.eee_get(tp, edata);
3457 usb_autopm_put_interface(tp->intf);
3464 rtl_ethtool_set_eee(struct net_device *net, struct ethtool_eee *edata)
3466 struct r8152 *tp = netdev_priv(net);
3469 ret = usb_autopm_get_interface(tp->intf);
3473 ret = tp->rtl_ops.eee_set(tp, edata);
3475 ret = mii_nway_restart(&tp->mii);
3477 usb_autopm_put_interface(tp->intf);
3483 static struct ethtool_ops ops = {
3484 .get_drvinfo = rtl8152_get_drvinfo,
3485 .get_settings = rtl8152_get_settings,
3486 .set_settings = rtl8152_set_settings,
3487 .get_link = ethtool_op_get_link,
3488 .get_msglevel = rtl8152_get_msglevel,
3489 .set_msglevel = rtl8152_set_msglevel,
3490 .get_wol = rtl8152_get_wol,
3491 .set_wol = rtl8152_set_wol,
3492 .get_strings = rtl8152_get_strings,
3493 .get_sset_count = rtl8152_get_sset_count,
3494 .get_ethtool_stats = rtl8152_get_ethtool_stats,
3495 .get_eee = rtl_ethtool_get_eee,
3496 .set_eee = rtl_ethtool_set_eee,
3499 static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
3501 struct r8152 *tp = netdev_priv(netdev);
3502 struct mii_ioctl_data *data = if_mii(rq);
3505 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3508 res = usb_autopm_get_interface(tp->intf);
3514 data->phy_id = R8152_PHY_ID; /* Internal PHY */
3518 data->val_out = r8152_mdio_read(tp, data->reg_num);
3522 if (!capable(CAP_NET_ADMIN)) {
3526 r8152_mdio_write(tp, data->reg_num, data->val_in);
3533 usb_autopm_put_interface(tp->intf);
3539 static int rtl8152_change_mtu(struct net_device *dev, int new_mtu)
3541 struct r8152 *tp = netdev_priv(dev);
3543 switch (tp->version) {
3546 return eth_change_mtu(dev, new_mtu);
3551 if (new_mtu < 68 || new_mtu > RTL8153_MAX_MTU)
3559 static const struct net_device_ops rtl8152_netdev_ops = {
3560 .ndo_open = rtl8152_open,
3561 .ndo_stop = rtl8152_close,
3562 .ndo_do_ioctl = rtl8152_ioctl,
3563 .ndo_start_xmit = rtl8152_start_xmit,
3564 .ndo_tx_timeout = rtl8152_tx_timeout,
3565 .ndo_set_features = rtl8152_set_features,
3566 .ndo_set_rx_mode = rtl8152_set_rx_mode,
3567 .ndo_set_mac_address = rtl8152_set_mac_address,
3568 .ndo_change_mtu = rtl8152_change_mtu,
3569 .ndo_validate_addr = eth_validate_addr,
3572 static void r8152b_get_version(struct r8152 *tp)
3577 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR1);
3578 version = (u16)(ocp_data & VERSION_MASK);
3582 tp->version = RTL_VER_01;
3585 tp->version = RTL_VER_02;
3588 tp->version = RTL_VER_03;
3589 tp->mii.supports_gmii = 1;
3592 tp->version = RTL_VER_04;
3593 tp->mii.supports_gmii = 1;
3596 tp->version = RTL_VER_05;
3597 tp->mii.supports_gmii = 1;
3600 netif_info(tp, probe, tp->netdev,
3601 "Unknown version 0x%04x\n", version);
3606 static void rtl8152_unload(struct r8152 *tp)
3608 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3611 if (tp->version != RTL_VER_01)
3612 r8152_power_cut_en(tp, true);
3615 static void rtl8153_unload(struct r8152 *tp)
3617 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3620 r8153_power_cut_en(tp, false);
3623 static int rtl_ops_init(struct r8152 *tp, const struct usb_device_id *id)
3625 struct rtl_ops *ops = &tp->rtl_ops;
3628 switch (id->idVendor) {
3629 case VENDOR_ID_REALTEK:
3630 switch (id->idProduct) {
3631 case PRODUCT_ID_RTL8152:
3632 ops->init = r8152b_init;
3633 ops->enable = rtl8152_enable;
3634 ops->disable = rtl8152_disable;
3635 ops->up = rtl8152_up;
3636 ops->down = rtl8152_down;
3637 ops->unload = rtl8152_unload;
3638 ops->eee_get = r8152_get_eee;
3639 ops->eee_set = r8152_set_eee;
3642 case PRODUCT_ID_RTL8153:
3643 ops->init = r8153_init;
3644 ops->enable = rtl8153_enable;
3645 ops->disable = rtl8153_disable;
3646 ops->up = rtl8153_up;
3647 ops->down = rtl8153_down;
3648 ops->unload = rtl8153_unload;
3649 ops->eee_get = r8153_get_eee;
3650 ops->eee_set = r8153_set_eee;
3658 case VENDOR_ID_SAMSUNG:
3659 switch (id->idProduct) {
3660 case PRODUCT_ID_SAMSUNG:
3661 ops->init = r8153_init;
3662 ops->enable = rtl8153_enable;
3663 ops->disable = rtl8153_disable;
3664 ops->up = rtl8153_up;
3665 ops->down = rtl8153_down;
3666 ops->unload = rtl8153_unload;
3667 ops->eee_get = r8153_get_eee;
3668 ops->eee_set = r8153_set_eee;
3681 netif_err(tp, probe, tp->netdev, "Unknown Device\n");
3686 static int rtl8152_probe(struct usb_interface *intf,
3687 const struct usb_device_id *id)
3689 struct usb_device *udev = interface_to_usbdev(intf);
3691 struct net_device *netdev;
3694 if (udev->actconfig->desc.bConfigurationValue != 1) {
3695 usb_driver_set_configuration(udev, 1);
3699 usb_reset_device(udev);
3700 netdev = alloc_etherdev(sizeof(struct r8152));
3702 dev_err(&intf->dev, "Out of memory\n");
3706 SET_NETDEV_DEV(netdev, &intf->dev);
3707 tp = netdev_priv(netdev);
3708 tp->msg_enable = 0x7FFF;
3711 tp->netdev = netdev;
3714 ret = rtl_ops_init(tp, id);
3718 tasklet_init(&tp->tl, bottom_half, (unsigned long)tp);
3719 INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t);
3721 netdev->netdev_ops = &rtl8152_netdev_ops;
3722 netdev->watchdog_timeo = RTL8152_TX_TIMEOUT;
3724 netdev->features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
3725 NETIF_F_TSO | NETIF_F_FRAGLIST | NETIF_F_IPV6_CSUM |
3726 NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_RX |
3727 NETIF_F_HW_VLAN_CTAG_TX;
3728 netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
3729 NETIF_F_TSO | NETIF_F_FRAGLIST |
3730 NETIF_F_IPV6_CSUM | NETIF_F_TSO6 |
3731 NETIF_F_HW_VLAN_CTAG_RX |
3732 NETIF_F_HW_VLAN_CTAG_TX;
3733 netdev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
3734 NETIF_F_HIGHDMA | NETIF_F_FRAGLIST |
3735 NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
3737 netdev->ethtool_ops = &ops;
3738 netif_set_gso_max_size(netdev, RTL_LIMITED_TSO_SIZE);
3740 tp->mii.dev = netdev;
3741 tp->mii.mdio_read = read_mii_word;
3742 tp->mii.mdio_write = write_mii_word;
3743 tp->mii.phy_id_mask = 0x3f;
3744 tp->mii.reg_num_mask = 0x1f;
3745 tp->mii.phy_id = R8152_PHY_ID;
3746 tp->mii.supports_gmii = 0;
3748 intf->needs_remote_wakeup = 1;
3750 r8152b_get_version(tp);
3751 tp->rtl_ops.init(tp);
3752 set_ethernet_addr(tp);
3754 usb_set_intfdata(intf, tp);
3756 ret = register_netdev(netdev);
3758 netif_err(tp, probe, netdev, "couldn't register the device\n");
3762 tp->saved_wolopts = __rtl_get_wol(tp);
3763 if (tp->saved_wolopts)
3764 device_set_wakeup_enable(&udev->dev, true);
3766 device_set_wakeup_enable(&udev->dev, false);
3768 netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION);
3773 usb_set_intfdata(intf, NULL);
3775 free_netdev(netdev);
3779 static void rtl8152_disconnect(struct usb_interface *intf)
3781 struct r8152 *tp = usb_get_intfdata(intf);
3783 usb_set_intfdata(intf, NULL);
3785 struct usb_device *udev = tp->udev;
3787 if (udev->state == USB_STATE_NOTATTACHED)
3788 set_bit(RTL8152_UNPLUG, &tp->flags);
3790 tasklet_kill(&tp->tl);
3791 unregister_netdev(tp->netdev);
3792 tp->rtl_ops.unload(tp);
3793 free_netdev(tp->netdev);
3797 /* table of devices that work with this driver */
3798 static struct usb_device_id rtl8152_table[] = {
3799 {USB_DEVICE(VENDOR_ID_REALTEK, PRODUCT_ID_RTL8152)},
3800 {USB_DEVICE(VENDOR_ID_REALTEK, PRODUCT_ID_RTL8153)},
3801 {USB_DEVICE(VENDOR_ID_SAMSUNG, PRODUCT_ID_SAMSUNG)},
3805 MODULE_DEVICE_TABLE(usb, rtl8152_table);
3807 static struct usb_driver rtl8152_driver = {
3809 .id_table = rtl8152_table,
3810 .probe = rtl8152_probe,
3811 .disconnect = rtl8152_disconnect,
3812 .suspend = rtl8152_suspend,
3813 .resume = rtl8152_resume,
3814 .reset_resume = rtl8152_resume,
3815 .supports_autosuspend = 1,
3816 .disable_hub_initiated_lpm = 1,
3819 module_usb_driver(rtl8152_driver);
3821 MODULE_AUTHOR(DRIVER_AUTHOR);
3822 MODULE_DESCRIPTION(DRIVER_DESC);
3823 MODULE_LICENSE("GPL");