2 * drivers/net/wan/dscc4/dscc4.c: a DSCC4 HDLC driver for Linux
4 * This software may be used and distributed according to the terms of the
5 * GNU General Public License.
7 * The author may be reached as romieu@cogenit.fr.
8 * Specific bug reports/asian food will be welcome.
10 * Special thanks to the nice people at CS-Telecom for the hardware and the
11 * access to the test/measure tools.
16 * I. Board Compatibility
18 * This device driver is designed for the Siemens PEB20534 4 ports serial
19 * controller as found on Etinc PCISYNC cards. The documentation for the
20 * chipset is available at http://www.infineon.com:
21 * - Data Sheet "DSCC4, DMA Supported Serial Communication Controller with
22 * 4 Channels, PEB 20534 Version 2.1, PEF 20534 Version 2.1";
23 * - Application Hint "Management of DSCC4 on-chip FIFO resources".
24 * - Errata sheet DS5 (courtesy of Michael Skerritt).
25 * Jens David has built an adapter based on the same chipset. Take a look
26 * at http://www.afthd.tu-darmstadt.de/~dg1kjd/pciscc4 for a specific
28 * Sample code (2 revisions) is available at Infineon.
30 * II. Board-specific settings
32 * Pcisync can transmit some clock signal to the outside world on the
33 * *first two* ports provided you put a quartz and a line driver on it and
34 * remove the jumpers. The operation is described on Etinc web site. If you
35 * go DCE on these ports, don't forget to use an adequate cable.
37 * Sharing of the PCI interrupt line for this board is possible.
39 * III. Driver operation
41 * The rx/tx operations are based on a linked list of descriptors. The driver
42 * doesn't use HOLD mode any more. HOLD mode is definitely buggy and the more
43 * I tried to fix it, the more it started to look like (convoluted) software
44 * mutation of LxDA method. Errata sheet DS5 suggests to use LxDA: consider
45 * this a rfc2119 MUST.
48 * When the tx ring is full, the xmit routine issues a call to netdev_stop.
49 * The device is supposed to be enabled again during an ALLS irq (we could
50 * use HI but as it's easy to lose events, it's fscked).
53 * The received frames aren't supposed to span over multiple receiving areas.
54 * I may implement it some day but it isn't the highest ranked item.
57 * The current error (XDU, RFO) recovery code is untested.
58 * So far, RDO takes his RX channel down and the right sequence to enable it
59 * again is still a mystery. If RDO happens, plan a reboot. More details
60 * in the code (NB: as this happens, TX still works).
61 * Don't mess the cables during operation, especially on DTE ports. I don't
62 * suggest it for DCE either but at least one can get some messages instead
63 * of a complete instant freeze.
64 * Tests are done on Rev. 20 of the silicium. The RDO handling changes with
65 * the documentation/chipset releases.
69 * - use polling at high irq/s,
70 * - performance analysis,
73 * 2001/12/10 Daniela Squassoni <daniela@cyclades.com>
74 * - Contribution to support the new generic HDLC layer.
77 * - old style interface removal
78 * - dscc4_release_ring fix (related to DMA mapping)
79 * - hard_start_xmit fix (hint: TxSizeMax)
83 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
85 #include <linux/module.h>
86 #include <linux/sched.h>
87 #include <linux/types.h>
88 #include <linux/errno.h>
89 #include <linux/list.h>
90 #include <linux/ioport.h>
91 #include <linux/pci.h>
92 #include <linux/kernel.h>
94 #include <linux/slab.h>
96 #include <asm/cache.h>
97 #include <asm/byteorder.h>
98 #include <asm/uaccess.h>
102 #include <linux/init.h>
103 #include <linux/interrupt.h>
104 #include <linux/string.h>
106 #include <linux/if_arp.h>
107 #include <linux/netdevice.h>
108 #include <linux/skbuff.h>
109 #include <linux/delay.h>
110 #include <linux/hdlc.h>
111 #include <linux/mutex.h>
114 static const char version[] = "$Id: dscc4.c,v 1.173 2003/09/20 23:55:34 romieu Exp $ for Linux\n";
118 #ifdef CONFIG_DSCC4_PCI_RST
119 static DEFINE_MUTEX(dscc4_mutex);
120 static u32 dscc4_pci_config_store[16];
123 #define DRV_NAME "dscc4"
127 /* Module parameters */
129 MODULE_AUTHOR("Maintainer: Francois Romieu <romieu@cogenit.fr>");
130 MODULE_DESCRIPTION("Siemens PEB20534 PCI Controller");
131 MODULE_LICENSE("GPL");
132 module_param(debug, int, 0);
133 MODULE_PARM_DESC(debug,"Enable/disable extra messages");
134 module_param(quartz, int, 0);
135 MODULE_PARM_DESC(quartz,"If present, on-board quartz frequency (Hz)");
149 u32 jiffies; /* Allows sizeof(TxFD) == sizeof(RxFD) + extra hack */
150 /* FWIW, datasheet calls that "dummy" and says that card
151 * never looks at it; neither does the driver */
162 #define DUMMY_SKB_SIZE 64
164 #define TX_RING_SIZE 32
165 #define RX_RING_SIZE 32
166 #define TX_TOTAL_SIZE TX_RING_SIZE*sizeof(struct TxFD)
167 #define RX_TOTAL_SIZE RX_RING_SIZE*sizeof(struct RxFD)
168 #define IRQ_RING_SIZE 64 /* Keep it a multiple of 32 */
169 #define TX_TIMEOUT (HZ/10)
170 #define DSCC4_HZ_MAX 33000000
171 #define BRR_DIVIDER_MAX 64*0x00004000 /* Cf errata DS5 p.10 */
172 #define dev_per_card 4
173 #define SCC_REGISTERS_MAX 23 /* Cf errata DS5 p.4 */
175 #define SOURCE_ID(flags) (((flags) >> 28) & 0x03)
176 #define TO_SIZE(state) (((state) >> 16) & 0x1fff)
179 * Given the operating range of Linux HDLC, the 2 defines below could be
180 * made simpler. However they are a fine reminder for the limitations of
181 * the driver: it's better to stay < TxSizeMax and < RxSizeMax.
183 #define TO_STATE_TX(len) cpu_to_le32(((len) & TxSizeMax) << 16)
184 #define TO_STATE_RX(len) cpu_to_le32((RX_MAX(len) % RxSizeMax) << 16)
185 #define RX_MAX(len) ((((len) >> 5) + 1) << 5) /* Cf RLCR */
186 #define SCC_REG_START(dpriv) (SCC_START+(dpriv->dev_id)*SCC_OFFSET)
188 struct dscc4_pci_priv {
192 struct pci_dev *pdev;
194 struct dscc4_dev_priv *root;
195 dma_addr_t iqcfg_dma;
199 struct dscc4_dev_priv {
200 struct sk_buff *rx_skbuff[RX_RING_SIZE];
201 struct sk_buff *tx_skbuff[TX_RING_SIZE];
208 /* FIXME: check all the volatile are required */
209 volatile u32 tx_current;
214 volatile u32 tx_dirty;
219 dma_addr_t tx_fd_dma;
220 dma_addr_t rx_fd_dma;
224 u32 scc_regs[SCC_REGISTERS_MAX]; /* Cf errata DS5 p.4 */
226 struct timer_list timer;
228 struct dscc4_pci_priv *pci_priv;
235 unsigned short encoding;
236 unsigned short parity;
237 struct net_device *dev;
238 sync_serial_settings settings;
239 void __iomem *base_addr;
240 u32 __pad __attribute__ ((aligned (4)));
243 /* GLOBAL registers definitions */
264 /* SCC registers definitions */
265 #define SCC_START 0x0100
266 #define SCC_OFFSET 0x80
278 #define GPDATA 0x0404
282 #define EncodingMask 0x00700000
283 #define CrcMask 0x00000003
285 #define IntRxScc0 0x10000000
286 #define IntTxScc0 0x01000000
288 #define TxPollCmd 0x00000400
289 #define RxActivate 0x08000000
290 #define MTFi 0x04000000
291 #define Rdr 0x00400000
292 #define Rdt 0x00200000
293 #define Idr 0x00100000
294 #define Idt 0x00080000
295 #define TxSccRes 0x01000000
296 #define RxSccRes 0x00010000
297 #define TxSizeMax 0x1fff /* Datasheet DS1 - 11.1.1.1 */
298 #define RxSizeMax 0x1ffc /* Datasheet DS1 - 11.1.2.1 */
300 #define Ccr0ClockMask 0x0000003f
301 #define Ccr1LoopMask 0x00000200
302 #define IsrMask 0x000fffff
303 #define BrrExpMask 0x00000f00
304 #define BrrMultMask 0x0000003f
305 #define EncodingMask 0x00700000
306 #define Hold cpu_to_le32(0x40000000)
307 #define SccBusy 0x10000000
308 #define PowerUp 0x80000000
309 #define Vis 0x00001000
310 #define FrameOk (FrameVfr | FrameCrc)
311 #define FrameVfr 0x80
312 #define FrameRdo 0x40
313 #define FrameCrc 0x20
314 #define FrameRab 0x10
315 #define FrameAborted cpu_to_le32(0x00000200)
316 #define FrameEnd cpu_to_le32(0x80000000)
317 #define DataComplete cpu_to_le32(0x40000000)
318 #define LengthCheck 0x00008000
319 #define SccEvt 0x02000000
320 #define NoAck 0x00000200
321 #define Action 0x00000001
322 #define HiDesc cpu_to_le32(0x20000000)
325 #define RxEvt 0xf0000000
326 #define TxEvt 0x0f000000
327 #define Alls 0x00040000
328 #define Xdu 0x00010000
329 #define Cts 0x00004000
330 #define Xmr 0x00002000
331 #define Xpr 0x00001000
332 #define Rdo 0x00000080
333 #define Rfs 0x00000040
334 #define Cd 0x00000004
335 #define Rfo 0x00000002
336 #define Flex 0x00000001
338 /* DMA core events */
339 #define Cfg 0x00200000
340 #define Hi 0x00040000
341 #define Fi 0x00020000
342 #define Err 0x00010000
343 #define Arf 0x00000002
344 #define ArAck 0x00000001
347 #define Ready 0x00000000
348 #define NeedIDR 0x00000001
349 #define NeedIDT 0x00000002
350 #define RdoSet 0x00000004
351 #define FakeReset 0x00000008
353 /* Don't mask RDO. Ever. */
355 #define EventsMask 0xfffeef7f
357 #define EventsMask 0xfffa8f7a
360 /* Functions prototypes */
361 static void dscc4_rx_irq(struct dscc4_pci_priv *, struct dscc4_dev_priv *);
362 static void dscc4_tx_irq(struct dscc4_pci_priv *, struct dscc4_dev_priv *);
363 static int dscc4_found1(struct pci_dev *, void __iomem *ioaddr);
364 static int dscc4_init_one(struct pci_dev *, const struct pci_device_id *ent);
365 static int dscc4_open(struct net_device *);
366 static netdev_tx_t dscc4_start_xmit(struct sk_buff *,
367 struct net_device *);
368 static int dscc4_close(struct net_device *);
369 static int dscc4_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
370 static int dscc4_init_ring(struct net_device *);
371 static void dscc4_release_ring(struct dscc4_dev_priv *);
372 static void dscc4_timer(unsigned long);
373 static void dscc4_tx_timeout(struct net_device *);
374 static irqreturn_t dscc4_irq(int irq, void *dev_id);
375 static int dscc4_hdlc_attach(struct net_device *, unsigned short, unsigned short);
376 static int dscc4_set_iface(struct dscc4_dev_priv *, struct net_device *);
378 static int dscc4_tx_poll(struct dscc4_dev_priv *, struct net_device *);
381 static inline struct dscc4_dev_priv *dscc4_priv(struct net_device *dev)
383 return dev_to_hdlc(dev)->priv;
386 static inline struct net_device *dscc4_to_dev(struct dscc4_dev_priv *p)
391 static void scc_patchl(u32 mask, u32 value, struct dscc4_dev_priv *dpriv,
392 struct net_device *dev, int offset)
396 /* Cf scc_writel for concern regarding thread-safety */
397 state = dpriv->scc_regs[offset >> 2];
400 dpriv->scc_regs[offset >> 2] = state;
401 writel(state, dpriv->base_addr + SCC_REG_START(dpriv) + offset);
404 static void scc_writel(u32 bits, struct dscc4_dev_priv *dpriv,
405 struct net_device *dev, int offset)
409 * As of 2002/02/16, there are no thread racing for access.
411 dpriv->scc_regs[offset >> 2] = bits;
412 writel(bits, dpriv->base_addr + SCC_REG_START(dpriv) + offset);
415 static inline u32 scc_readl(struct dscc4_dev_priv *dpriv, int offset)
417 return dpriv->scc_regs[offset >> 2];
420 static u32 scc_readl_star(struct dscc4_dev_priv *dpriv, struct net_device *dev)
422 /* Cf errata DS5 p.4 */
423 readl(dpriv->base_addr + SCC_REG_START(dpriv) + STAR);
424 return readl(dpriv->base_addr + SCC_REG_START(dpriv) + STAR);
427 static inline void dscc4_do_tx(struct dscc4_dev_priv *dpriv,
428 struct net_device *dev)
430 dpriv->ltda = dpriv->tx_fd_dma +
431 ((dpriv->tx_current-1)%TX_RING_SIZE)*sizeof(struct TxFD);
432 writel(dpriv->ltda, dpriv->base_addr + CH0LTDA + dpriv->dev_id*4);
433 /* Flush posted writes *NOW* */
434 readl(dpriv->base_addr + CH0LTDA + dpriv->dev_id*4);
437 static inline void dscc4_rx_update(struct dscc4_dev_priv *dpriv,
438 struct net_device *dev)
440 dpriv->lrda = dpriv->rx_fd_dma +
441 ((dpriv->rx_dirty - 1)%RX_RING_SIZE)*sizeof(struct RxFD);
442 writel(dpriv->lrda, dpriv->base_addr + CH0LRDA + dpriv->dev_id*4);
445 static inline unsigned int dscc4_tx_done(struct dscc4_dev_priv *dpriv)
447 return dpriv->tx_current == dpriv->tx_dirty;
450 static inline unsigned int dscc4_tx_quiescent(struct dscc4_dev_priv *dpriv,
451 struct net_device *dev)
453 return readl(dpriv->base_addr + CH0FTDA + dpriv->dev_id*4) == dpriv->ltda;
456 static int state_check(u32 state, struct dscc4_dev_priv *dpriv,
457 struct net_device *dev, const char *msg)
462 if (SOURCE_ID(state) != dpriv->dev_id) {
463 printk(KERN_DEBUG "%s (%s): Source Id=%d, state=%08x\n",
464 dev->name, msg, SOURCE_ID(state), state );
467 if (state & 0x0df80c00) {
468 printk(KERN_DEBUG "%s (%s): state=%08x (UFO alert)\n",
469 dev->name, msg, state);
476 static void dscc4_tx_print(struct net_device *dev,
477 struct dscc4_dev_priv *dpriv,
480 printk(KERN_DEBUG "%s: tx_current=%02d tx_dirty=%02d (%s)\n",
481 dev->name, dpriv->tx_current, dpriv->tx_dirty, msg);
484 static void dscc4_release_ring(struct dscc4_dev_priv *dpriv)
486 struct pci_dev *pdev = dpriv->pci_priv->pdev;
487 struct TxFD *tx_fd = dpriv->tx_fd;
488 struct RxFD *rx_fd = dpriv->rx_fd;
489 struct sk_buff **skbuff;
492 pci_free_consistent(pdev, TX_TOTAL_SIZE, tx_fd, dpriv->tx_fd_dma);
493 pci_free_consistent(pdev, RX_TOTAL_SIZE, rx_fd, dpriv->rx_fd_dma);
495 skbuff = dpriv->tx_skbuff;
496 for (i = 0; i < TX_RING_SIZE; i++) {
498 pci_unmap_single(pdev, le32_to_cpu(tx_fd->data),
499 (*skbuff)->len, PCI_DMA_TODEVICE);
500 dev_kfree_skb(*skbuff);
506 skbuff = dpriv->rx_skbuff;
507 for (i = 0; i < RX_RING_SIZE; i++) {
509 pci_unmap_single(pdev, le32_to_cpu(rx_fd->data),
510 RX_MAX(HDLC_MAX_MRU), PCI_DMA_FROMDEVICE);
511 dev_kfree_skb(*skbuff);
518 static inline int try_get_rx_skb(struct dscc4_dev_priv *dpriv,
519 struct net_device *dev)
521 unsigned int dirty = dpriv->rx_dirty%RX_RING_SIZE;
522 struct RxFD *rx_fd = dpriv->rx_fd + dirty;
523 const int len = RX_MAX(HDLC_MAX_MRU);
527 skb = dev_alloc_skb(len);
528 dpriv->rx_skbuff[dirty] = skb;
530 skb->protocol = hdlc_type_trans(skb, dev);
531 rx_fd->data = cpu_to_le32(pci_map_single(dpriv->pci_priv->pdev,
532 skb->data, len, PCI_DMA_FROMDEVICE));
541 * IRQ/thread/whatever safe
543 static int dscc4_wait_ack_cec(struct dscc4_dev_priv *dpriv,
544 struct net_device *dev, char *msg)
549 if (!(scc_readl_star(dpriv, dev) & SccBusy)) {
550 printk(KERN_DEBUG "%s: %s ack (%d try)\n", dev->name,
554 schedule_timeout_uninterruptible(msecs_to_jiffies(100));
557 netdev_err(dev, "%s timeout\n", msg);
559 return (i >= 0) ? i : -EAGAIN;
562 static int dscc4_do_action(struct net_device *dev, char *msg)
564 void __iomem *ioaddr = dscc4_priv(dev)->base_addr;
567 writel(Action, ioaddr + GCMDR);
570 u32 state = readl(ioaddr);
573 netdev_dbg(dev, "%s ack\n", msg);
574 writel(ArAck, ioaddr);
576 } else if (state & Arf) {
577 netdev_err(dev, "%s failed\n", msg);
584 netdev_err(dev, "%s timeout\n", msg);
589 static inline int dscc4_xpr_ack(struct dscc4_dev_priv *dpriv)
591 int cur = dpriv->iqtx_current%IRQ_RING_SIZE;
595 if (!(dpriv->flags & (NeedIDR | NeedIDT)) ||
596 (dpriv->iqtx[cur] & cpu_to_le32(Xpr)))
599 schedule_timeout_uninterruptible(msecs_to_jiffies(100));
602 return (i >= 0 ) ? i : -EAGAIN;
605 #if 0 /* dscc4_{rx/tx}_reset are both unreliable - more tweak needed */
606 static void dscc4_rx_reset(struct dscc4_dev_priv *dpriv, struct net_device *dev)
610 spin_lock_irqsave(&dpriv->pci_priv->lock, flags);
611 /* Cf errata DS5 p.6 */
612 writel(0x00000000, dpriv->base_addr + CH0LRDA + dpriv->dev_id*4);
613 scc_patchl(PowerUp, 0, dpriv, dev, CCR0);
614 readl(dpriv->base_addr + CH0LRDA + dpriv->dev_id*4);
615 writel(MTFi|Rdr, dpriv->base_addr + dpriv->dev_id*0x0c + CH0CFG);
616 writel(Action, dpriv->base_addr + GCMDR);
617 spin_unlock_irqrestore(&dpriv->pci_priv->lock, flags);
623 static void dscc4_tx_reset(struct dscc4_dev_priv *dpriv, struct net_device *dev)
627 /* Cf errata DS5 p.7 */
628 scc_patchl(PowerUp, 0, dpriv, dev, CCR0);
629 scc_writel(0x00050000, dpriv, dev, CCR2);
631 * Must be longer than the time required to fill the fifo.
633 while (!dscc4_tx_quiescent(dpriv, dev) && ++i) {
638 writel(MTFi|Rdt, dpriv->base_addr + dpriv->dev_id*0x0c + CH0CFG);
639 if (dscc4_do_action(dev, "Rdt") < 0)
640 netdev_err(dev, "Tx reset failed\n");
644 /* TODO: (ab)use this function to refill a completely depleted RX ring. */
645 static inline void dscc4_rx_skb(struct dscc4_dev_priv *dpriv,
646 struct net_device *dev)
648 struct RxFD *rx_fd = dpriv->rx_fd + dpriv->rx_current%RX_RING_SIZE;
649 struct pci_dev *pdev = dpriv->pci_priv->pdev;
653 skb = dpriv->rx_skbuff[dpriv->rx_current++%RX_RING_SIZE];
655 printk(KERN_DEBUG "%s: skb=0 (%s)\n", dev->name, __func__);
658 pkt_len = TO_SIZE(le32_to_cpu(rx_fd->state2));
659 pci_unmap_single(pdev, le32_to_cpu(rx_fd->data),
660 RX_MAX(HDLC_MAX_MRU), PCI_DMA_FROMDEVICE);
661 if ((skb->data[--pkt_len] & FrameOk) == FrameOk) {
662 dev->stats.rx_packets++;
663 dev->stats.rx_bytes += pkt_len;
664 skb_put(skb, pkt_len);
665 if (netif_running(dev))
666 skb->protocol = hdlc_type_trans(skb, dev);
669 if (skb->data[pkt_len] & FrameRdo)
670 dev->stats.rx_fifo_errors++;
671 else if (!(skb->data[pkt_len] & FrameCrc))
672 dev->stats.rx_crc_errors++;
673 else if ((skb->data[pkt_len] & (FrameVfr | FrameRab)) !=
674 (FrameVfr | FrameRab))
675 dev->stats.rx_length_errors++;
676 dev->stats.rx_errors++;
677 dev_kfree_skb_irq(skb);
680 while ((dpriv->rx_dirty - dpriv->rx_current) % RX_RING_SIZE) {
681 if (try_get_rx_skb(dpriv, dev) < 0)
685 dscc4_rx_update(dpriv, dev);
686 rx_fd->state2 = 0x00000000;
687 rx_fd->end = cpu_to_le32(0xbabeface);
690 static void dscc4_free1(struct pci_dev *pdev)
692 struct dscc4_pci_priv *ppriv;
693 struct dscc4_dev_priv *root;
696 ppriv = pci_get_drvdata(pdev);
699 for (i = 0; i < dev_per_card; i++)
700 unregister_hdlc_device(dscc4_to_dev(root + i));
702 for (i = 0; i < dev_per_card; i++)
703 free_netdev(root[i].dev);
708 static int dscc4_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
710 struct dscc4_pci_priv *priv;
711 struct dscc4_dev_priv *dpriv;
712 void __iomem *ioaddr;
715 printk(KERN_DEBUG "%s", version);
717 rc = pci_enable_device(pdev);
721 rc = pci_request_region(pdev, 0, "registers");
723 pr_err("can't reserve MMIO region (regs)\n");
726 rc = pci_request_region(pdev, 1, "LBI interface");
728 pr_err("can't reserve MMIO region (lbi)\n");
729 goto err_free_mmio_region_1;
732 ioaddr = pci_ioremap_bar(pdev, 0);
734 pr_err("cannot remap MMIO region %llx @ %llx\n",
735 (unsigned long long)pci_resource_len(pdev, 0),
736 (unsigned long long)pci_resource_start(pdev, 0));
738 goto err_free_mmio_regions_2;
740 printk(KERN_DEBUG "Siemens DSCC4, MMIO at %#llx (regs), %#llx (lbi), IRQ %d\n",
741 (unsigned long long)pci_resource_start(pdev, 0),
742 (unsigned long long)pci_resource_start(pdev, 1), pdev->irq);
744 /* Cf errata DS5 p.2 */
745 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xf8);
746 pci_set_master(pdev);
748 rc = dscc4_found1(pdev, ioaddr);
752 priv = pci_get_drvdata(pdev);
754 rc = request_irq(pdev->irq, dscc4_irq, IRQF_SHARED, DRV_NAME, priv->root);
756 pr_warn("IRQ %d busy\n", pdev->irq);
760 /* power up/little endian/dma core controlled via lrda/ltda */
761 writel(0x00000001, ioaddr + GMODE);
762 /* Shared interrupt queue */
766 bits = (IRQ_RING_SIZE >> 5) - 1;
770 writel(bits, ioaddr + IQLENR0);
772 /* Global interrupt queue */
773 writel((u32)(((IRQ_RING_SIZE >> 5) - 1) << 20), ioaddr + IQLENR1);
777 priv->iqcfg = (__le32 *) pci_alloc_consistent(pdev,
778 IRQ_RING_SIZE*sizeof(__le32), &priv->iqcfg_dma);
781 writel(priv->iqcfg_dma, ioaddr + IQCFG);
784 * SCC 0-3 private rx/tx irq structures
785 * IQRX/TXi needs to be set soon. Learned it the hard way...
787 for (i = 0; i < dev_per_card; i++) {
788 dpriv = priv->root + i;
789 dpriv->iqtx = (__le32 *) pci_alloc_consistent(pdev,
790 IRQ_RING_SIZE*sizeof(u32), &dpriv->iqtx_dma);
792 goto err_free_iqtx_6;
793 writel(dpriv->iqtx_dma, ioaddr + IQTX0 + i*4);
795 for (i = 0; i < dev_per_card; i++) {
796 dpriv = priv->root + i;
797 dpriv->iqrx = (__le32 *) pci_alloc_consistent(pdev,
798 IRQ_RING_SIZE*sizeof(u32), &dpriv->iqrx_dma);
800 goto err_free_iqrx_7;
801 writel(dpriv->iqrx_dma, ioaddr + IQRX0 + i*4);
804 /* Cf application hint. Beware of hard-lock condition on threshold. */
805 writel(0x42104000, ioaddr + FIFOCR1);
806 //writel(0x9ce69800, ioaddr + FIFOCR2);
807 writel(0xdef6d800, ioaddr + FIFOCR2);
808 //writel(0x11111111, ioaddr + FIFOCR4);
809 writel(0x18181818, ioaddr + FIFOCR4);
810 // FIXME: should depend on the chipset revision
811 writel(0x0000000e, ioaddr + FIFOCR3);
813 writel(0xff200001, ioaddr + GCMDR);
821 dpriv = priv->root + i;
822 pci_free_consistent(pdev, IRQ_RING_SIZE*sizeof(u32),
823 dpriv->iqrx, dpriv->iqrx_dma);
828 dpriv = priv->root + i;
829 pci_free_consistent(pdev, IRQ_RING_SIZE*sizeof(u32),
830 dpriv->iqtx, dpriv->iqtx_dma);
832 pci_free_consistent(pdev, IRQ_RING_SIZE*sizeof(u32), priv->iqcfg,
835 free_irq(pdev->irq, priv->root);
840 err_free_mmio_regions_2:
841 pci_release_region(pdev, 1);
842 err_free_mmio_region_1:
843 pci_release_region(pdev, 0);
845 pci_disable_device(pdev);
850 * Let's hope the default values are decent enough to protect my
851 * feet from the user's gun - Ueimor
853 static void dscc4_init_registers(struct dscc4_dev_priv *dpriv,
854 struct net_device *dev)
856 /* No interrupts, SCC core disabled. Let's relax */
857 scc_writel(0x00000000, dpriv, dev, CCR0);
859 scc_writel(LengthCheck | (HDLC_MAX_MRU >> 5), dpriv, dev, RLCR);
862 * No address recognition/crc-CCITT/cts enabled
863 * Shared flags transmission disabled - cf errata DS5 p.11
864 * Carrier detect disabled - cf errata p.14
865 * FIXME: carrier detection/polarity may be handled more gracefully.
867 scc_writel(0x02408000, dpriv, dev, CCR1);
869 /* crc not forwarded - Cf errata DS5 p.11 */
870 scc_writel(0x00050008 & ~RxActivate, dpriv, dev, CCR2);
872 //scc_writel(0x00250008 & ~RxActivate, dpriv, dev, CCR2);
875 static inline int dscc4_set_quartz(struct dscc4_dev_priv *dpriv, int hz)
879 if ((hz < 0) || (hz > DSCC4_HZ_MAX))
882 dpriv->pci_priv->xtal_hz = hz;
887 static const struct net_device_ops dscc4_ops = {
888 .ndo_open = dscc4_open,
889 .ndo_stop = dscc4_close,
890 .ndo_change_mtu = hdlc_change_mtu,
891 .ndo_start_xmit = hdlc_start_xmit,
892 .ndo_do_ioctl = dscc4_ioctl,
893 .ndo_tx_timeout = dscc4_tx_timeout,
896 static int dscc4_found1(struct pci_dev *pdev, void __iomem *ioaddr)
898 struct dscc4_pci_priv *ppriv;
899 struct dscc4_dev_priv *root;
900 int i, ret = -ENOMEM;
902 root = kcalloc(dev_per_card, sizeof(*root), GFP_KERNEL);
906 for (i = 0; i < dev_per_card; i++) {
907 root[i].dev = alloc_hdlcdev(root + i);
912 ppriv = kzalloc(sizeof(*ppriv), GFP_KERNEL);
917 spin_lock_init(&ppriv->lock);
919 for (i = 0; i < dev_per_card; i++) {
920 struct dscc4_dev_priv *dpriv = root + i;
921 struct net_device *d = dscc4_to_dev(dpriv);
922 hdlc_device *hdlc = dev_to_hdlc(d);
924 d->base_addr = (unsigned long)ioaddr;
926 d->netdev_ops = &dscc4_ops;
927 d->watchdog_timeo = TX_TIMEOUT;
928 SET_NETDEV_DEV(d, &pdev->dev);
931 dpriv->pci_priv = ppriv;
932 dpriv->base_addr = ioaddr;
933 spin_lock_init(&dpriv->lock);
935 hdlc->xmit = dscc4_start_xmit;
936 hdlc->attach = dscc4_hdlc_attach;
938 dscc4_init_registers(dpriv, d);
939 dpriv->parity = PARITY_CRC16_PR0_CCITT;
940 dpriv->encoding = ENCODING_NRZ;
942 ret = dscc4_init_ring(d);
946 ret = register_hdlc_device(d);
948 pr_err("unable to register\n");
949 dscc4_release_ring(dpriv);
954 ret = dscc4_set_quartz(root, quartz);
958 pci_set_drvdata(pdev, ppriv);
963 dscc4_release_ring(root + i);
964 unregister_hdlc_device(dscc4_to_dev(root + i));
970 free_netdev(root[i].dev);
976 /* FIXME: get rid of the unneeded code */
977 static void dscc4_timer(unsigned long data)
979 struct net_device *dev = (struct net_device *)data;
980 struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
981 // struct dscc4_pci_priv *ppriv;
985 dpriv->timer.expires = jiffies + TX_TIMEOUT;
986 add_timer(&dpriv->timer);
989 static void dscc4_tx_timeout(struct net_device *dev)
991 /* FIXME: something is missing there */
994 static int dscc4_loopback_check(struct dscc4_dev_priv *dpriv)
996 sync_serial_settings *settings = &dpriv->settings;
998 if (settings->loopback && (settings->clock_type != CLOCK_INT)) {
999 struct net_device *dev = dscc4_to_dev(dpriv);
1001 netdev_info(dev, "loopback requires clock\n");
1007 #ifdef CONFIG_DSCC4_PCI_RST
1009 * Some DSCC4-based cards wires the GPIO port and the PCI #RST pin together
1010 * so as to provide a safe way to reset the asic while not the whole machine
1013 * This code doesn't need to be efficient. Keep It Simple
1015 static void dscc4_pci_reset(struct pci_dev *pdev, void __iomem *ioaddr)
1019 mutex_lock(&dscc4_mutex);
1020 for (i = 0; i < 16; i++)
1021 pci_read_config_dword(pdev, i << 2, dscc4_pci_config_store + i);
1023 /* Maximal LBI clock divider (who cares ?) and whole GPIO range. */
1024 writel(0x001c0000, ioaddr + GMODE);
1025 /* Configure GPIO port as output */
1026 writel(0x0000ffff, ioaddr + GPDIR);
1027 /* Disable interruption */
1028 writel(0x0000ffff, ioaddr + GPIM);
1030 writel(0x0000ffff, ioaddr + GPDATA);
1031 writel(0x00000000, ioaddr + GPDATA);
1033 /* Flush posted writes */
1034 readl(ioaddr + GSTAR);
1036 schedule_timeout_uninterruptible(msecs_to_jiffies(100));
1038 for (i = 0; i < 16; i++)
1039 pci_write_config_dword(pdev, i << 2, dscc4_pci_config_store[i]);
1040 mutex_unlock(&dscc4_mutex);
1043 #define dscc4_pci_reset(pdev,ioaddr) do {} while (0)
1044 #endif /* CONFIG_DSCC4_PCI_RST */
1046 static int dscc4_open(struct net_device *dev)
1048 struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
1051 if ((dscc4_loopback_check(dpriv) < 0))
1054 if ((ret = hdlc_open(dev)))
1058 * Due to various bugs, there is no way to reliably reset a
1059 * specific port (manufacturer's dependent special PCI #RST wiring
1060 * apart: it affects all ports). Thus the device goes in the best
1061 * silent mode possible at dscc4_close() time and simply claims to
1062 * be up if it's opened again. It still isn't possible to change
1063 * the HDLC configuration without rebooting but at least the ports
1064 * can be up/down ifconfig'ed without killing the host.
1066 if (dpriv->flags & FakeReset) {
1067 dpriv->flags &= ~FakeReset;
1068 scc_patchl(0, PowerUp, dpriv, dev, CCR0);
1069 scc_patchl(0, 0x00050000, dpriv, dev, CCR2);
1070 scc_writel(EventsMask, dpriv, dev, IMR);
1071 netdev_info(dev, "up again\n");
1075 /* IDT+IDR during XPR */
1076 dpriv->flags = NeedIDR | NeedIDT;
1078 scc_patchl(0, PowerUp | Vis, dpriv, dev, CCR0);
1081 * The following is a bit paranoid...
1083 * NB: the datasheet "...CEC will stay active if the SCC is in
1084 * power-down mode or..." and CCR2.RAC = 1 are two different
1087 if (scc_readl_star(dpriv, dev) & SccBusy) {
1088 netdev_err(dev, "busy - try later\n");
1092 netdev_info(dev, "available - good\n");
1094 scc_writel(EventsMask, dpriv, dev, IMR);
1096 /* Posted write is flushed in the wait_ack loop */
1097 scc_writel(TxSccRes | RxSccRes, dpriv, dev, CMDR);
1099 if ((ret = dscc4_wait_ack_cec(dpriv, dev, "Cec")) < 0)
1100 goto err_disable_scc_events;
1103 * I would expect XPR near CE completion (before ? after ?).
1104 * At worst, this code won't see a late XPR and people
1105 * will have to re-issue an ifconfig (this is harmless).
1106 * WARNING, a really missing XPR usually means a hardware
1107 * reset is needed. Suggestions anyone ?
1109 if ((ret = dscc4_xpr_ack(dpriv)) < 0) {
1110 pr_err("XPR timeout\n");
1111 goto err_disable_scc_events;
1115 dscc4_tx_print(dev, dpriv, "Open");
1118 netif_start_queue(dev);
1120 init_timer(&dpriv->timer);
1121 dpriv->timer.expires = jiffies + 10*HZ;
1122 dpriv->timer.data = (unsigned long)dev;
1123 dpriv->timer.function = dscc4_timer;
1124 add_timer(&dpriv->timer);
1125 netif_carrier_on(dev);
1129 err_disable_scc_events:
1130 scc_writel(0xffffffff, dpriv, dev, IMR);
1131 scc_patchl(PowerUp | Vis, 0, dpriv, dev, CCR0);
1138 #ifdef DSCC4_POLLING
1139 static int dscc4_tx_poll(struct dscc4_dev_priv *dpriv, struct net_device *dev)
1141 /* FIXME: it's gonna be easy (TM), for sure */
1143 #endif /* DSCC4_POLLING */
1145 static netdev_tx_t dscc4_start_xmit(struct sk_buff *skb,
1146 struct net_device *dev)
1148 struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
1149 struct dscc4_pci_priv *ppriv = dpriv->pci_priv;
1153 next = dpriv->tx_current%TX_RING_SIZE;
1154 dpriv->tx_skbuff[next] = skb;
1155 tx_fd = dpriv->tx_fd + next;
1156 tx_fd->state = FrameEnd | TO_STATE_TX(skb->len);
1157 tx_fd->data = cpu_to_le32(pci_map_single(ppriv->pdev, skb->data, skb->len,
1159 tx_fd->complete = 0x00000000;
1160 tx_fd->jiffies = jiffies;
1163 #ifdef DSCC4_POLLING
1164 spin_lock(&dpriv->lock);
1165 while (dscc4_tx_poll(dpriv, dev));
1166 spin_unlock(&dpriv->lock);
1170 dscc4_tx_print(dev, dpriv, "Xmit");
1171 /* To be cleaned(unsigned int)/optimized. Later, ok ? */
1172 if (!((++dpriv->tx_current - dpriv->tx_dirty)%TX_RING_SIZE))
1173 netif_stop_queue(dev);
1175 if (dscc4_tx_quiescent(dpriv, dev))
1176 dscc4_do_tx(dpriv, dev);
1178 return NETDEV_TX_OK;
1181 static int dscc4_close(struct net_device *dev)
1183 struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
1185 del_timer_sync(&dpriv->timer);
1186 netif_stop_queue(dev);
1188 scc_patchl(PowerUp | Vis, 0, dpriv, dev, CCR0);
1189 scc_patchl(0x00050000, 0, dpriv, dev, CCR2);
1190 scc_writel(0xffffffff, dpriv, dev, IMR);
1192 dpriv->flags |= FakeReset;
1199 static inline int dscc4_check_clock_ability(int port)
1203 #ifdef CONFIG_DSCC4_PCISYNC
1211 * DS1 p.137: "There are a total of 13 different clocking modes..."
1214 * - by default, assume a clock is provided on pin RxClk/TxClk (clock mode 0a).
1215 * Clock mode 3b _should_ work but the testing seems to make this point
1216 * dubious (DIY testing requires setting CCR0 at 0x00000033).
1217 * This is supposed to provide least surprise "DTE like" behavior.
1218 * - if line rate is specified, clocks are assumed to be locally generated.
1219 * A quartz must be available (on pin XTAL1). Modes 6b/7b are used. Choosing
1220 * between these it automagically done according on the required frequency
1221 * scaling. Of course some rounding may take place.
1222 * - no high speed mode (40Mb/s). May be trivial to do but I don't have an
1223 * appropriate external clocking device for testing.
1224 * - no time-slot/clock mode 5: shameless laziness.
1226 * The clock signals wiring can be (is ?) manufacturer dependent. Good luck.
1228 * BIG FAT WARNING: if the device isn't provided enough clocking signal, it
1229 * won't pass the init sequence. For example, straight back-to-back DTE without
1230 * external clock will fail when dscc4_open() (<- 'ifconfig hdlcx xxx') is
1233 * Typos lurk in datasheet (missing divier in clock mode 7a figure 51 p.153
1236 * Clock mode related bits of CCR0:
1237 * +------------ TOE: output TxClk (0b/2b/3a/3b/6b/7a/7b only)
1238 * | +---------- SSEL: sub-mode select 0 -> a, 1 -> b
1239 * | | +-------- High Speed: say 0
1240 * | | | +-+-+-- Clock Mode: 0..7
1243 * x|x|5|4|3|2|1|0| lower bits
1245 * Division factor of BRR: k = (N+1)x2^M (total divider = 16xk in mode 6b)
1246 * +-+-+-+------------------ M (0..15)
1247 * | | | | +-+-+-+-+-+-- N (0..63)
1248 * 0 0 0 0 | | | | 0 0 | | | | | |
1249 * ...-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
1250 * f|e|d|c|b|a|9|8|7|6|5|4|3|2|1|0| lower bits
1253 static int dscc4_set_clock(struct net_device *dev, u32 *bps, u32 *state)
1255 struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
1259 *state &= ~Ccr0ClockMask;
1260 if (*bps) { /* Clock generated - required for DCE */
1261 u32 n = 0, m = 0, divider;
1264 xtal = dpriv->pci_priv->xtal_hz;
1267 if (dscc4_check_clock_ability(dpriv->dev_id) < 0)
1269 divider = xtal / *bps;
1270 if (divider > BRR_DIVIDER_MAX) {
1272 *state |= 0x00000036; /* Clock mode 6b (BRG/16) */
1274 *state |= 0x00000037; /* Clock mode 7b (BRG) */
1275 if (divider >> 22) {
1278 } else if (divider) {
1279 /* Extraction of the 6 highest weighted bits */
1281 while (0xffffffc0 & divider) {
1289 if (!(*state & 0x00000001)) /* ?b mode mask => clock mode 6b */
1291 *bps = xtal / divider;
1294 * External clock - DTE
1295 * "state" already reflects Clock mode 0a (CCR0 = 0xzzzzzz00).
1296 * Nothing more to be done
1300 scc_writel(brr, dpriv, dev, BRR);
1306 static int dscc4_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1308 sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1309 struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
1310 const size_t size = sizeof(dpriv->settings);
1313 if (dev->flags & IFF_UP)
1316 if (cmd != SIOCWANDEV)
1319 switch(ifr->ifr_settings.type) {
1321 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
1322 if (ifr->ifr_settings.size < size) {
1323 ifr->ifr_settings.size = size; /* data size wanted */
1326 if (copy_to_user(line, &dpriv->settings, size))
1330 case IF_IFACE_SYNC_SERIAL:
1331 if (!capable(CAP_NET_ADMIN))
1334 if (dpriv->flags & FakeReset) {
1335 netdev_info(dev, "please reset the device before this command\n");
1338 if (copy_from_user(&dpriv->settings, line, size))
1340 ret = dscc4_set_iface(dpriv, dev);
1344 ret = hdlc_ioctl(dev, ifr, cmd);
1351 static int dscc4_match(const struct thingie *p, int value)
1355 for (i = 0; p[i].define != -1; i++) {
1356 if (value == p[i].define)
1359 if (p[i].define == -1)
1365 static int dscc4_clock_setting(struct dscc4_dev_priv *dpriv,
1366 struct net_device *dev)
1368 sync_serial_settings *settings = &dpriv->settings;
1369 int ret = -EOPNOTSUPP;
1372 bps = settings->clock_rate;
1373 state = scc_readl(dpriv, CCR0);
1374 if (dscc4_set_clock(dev, &bps, &state) < 0)
1376 if (bps) { /* DCE */
1377 printk(KERN_DEBUG "%s: generated RxClk (DCE)\n", dev->name);
1378 if (settings->clock_rate != bps) {
1379 printk(KERN_DEBUG "%s: clock adjusted (%08d -> %08d)\n",
1380 dev->name, settings->clock_rate, bps);
1381 settings->clock_rate = bps;
1384 state |= PowerUp | Vis;
1385 printk(KERN_DEBUG "%s: external RxClk (DTE)\n", dev->name);
1387 scc_writel(state, dpriv, dev, CCR0);
1393 static int dscc4_encoding_setting(struct dscc4_dev_priv *dpriv,
1394 struct net_device *dev)
1396 static const struct thingie encoding[] = {
1397 { ENCODING_NRZ, 0x00000000 },
1398 { ENCODING_NRZI, 0x00200000 },
1399 { ENCODING_FM_MARK, 0x00400000 },
1400 { ENCODING_FM_SPACE, 0x00500000 },
1401 { ENCODING_MANCHESTER, 0x00600000 },
1406 i = dscc4_match(encoding, dpriv->encoding);
1408 scc_patchl(EncodingMask, encoding[i].bits, dpriv, dev, CCR0);
1414 static int dscc4_loopback_setting(struct dscc4_dev_priv *dpriv,
1415 struct net_device *dev)
1417 sync_serial_settings *settings = &dpriv->settings;
1420 state = scc_readl(dpriv, CCR1);
1421 if (settings->loopback) {
1422 printk(KERN_DEBUG "%s: loopback\n", dev->name);
1423 state |= 0x00000100;
1425 printk(KERN_DEBUG "%s: normal\n", dev->name);
1426 state &= ~0x00000100;
1428 scc_writel(state, dpriv, dev, CCR1);
1432 static int dscc4_crc_setting(struct dscc4_dev_priv *dpriv,
1433 struct net_device *dev)
1435 static const struct thingie crc[] = {
1436 { PARITY_CRC16_PR0_CCITT, 0x00000010 },
1437 { PARITY_CRC16_PR1_CCITT, 0x00000000 },
1438 { PARITY_CRC32_PR0_CCITT, 0x00000011 },
1439 { PARITY_CRC32_PR1_CCITT, 0x00000001 }
1443 i = dscc4_match(crc, dpriv->parity);
1445 scc_patchl(CrcMask, crc[i].bits, dpriv, dev, CCR1);
1451 static int dscc4_set_iface(struct dscc4_dev_priv *dpriv, struct net_device *dev)
1454 int (*action)(struct dscc4_dev_priv *, struct net_device *);
1455 } *p, do_setting[] = {
1456 { dscc4_encoding_setting },
1457 { dscc4_clock_setting },
1458 { dscc4_loopback_setting },
1459 { dscc4_crc_setting },
1464 for (p = do_setting; p->action; p++) {
1465 if ((ret = p->action(dpriv, dev)) < 0)
1471 static irqreturn_t dscc4_irq(int irq, void *token)
1473 struct dscc4_dev_priv *root = token;
1474 struct dscc4_pci_priv *priv;
1475 struct net_device *dev;
1476 void __iomem *ioaddr;
1478 unsigned long flags;
1481 priv = root->pci_priv;
1482 dev = dscc4_to_dev(root);
1484 spin_lock_irqsave(&priv->lock, flags);
1486 ioaddr = root->base_addr;
1488 state = readl(ioaddr + GSTAR);
1494 printk(KERN_DEBUG "%s: GSTAR = 0x%08x\n", DRV_NAME, state);
1495 writel(state, ioaddr + GSTAR);
1498 netdev_err(dev, "failure (Arf). Harass the maintainer\n");
1504 printk(KERN_DEBUG "%s: CfgIV\n", DRV_NAME);
1505 if (priv->iqcfg[priv->cfg_cur++%IRQ_RING_SIZE] & cpu_to_le32(Arf))
1506 netdev_err(dev, "CFG failed\n");
1507 if (!(state &= ~Cfg))
1510 if (state & RxEvt) {
1511 i = dev_per_card - 1;
1513 dscc4_rx_irq(priv, root + i);
1517 if (state & TxEvt) {
1518 i = dev_per_card - 1;
1520 dscc4_tx_irq(priv, root + i);
1525 spin_unlock_irqrestore(&priv->lock, flags);
1526 return IRQ_RETVAL(handled);
1529 static void dscc4_tx_irq(struct dscc4_pci_priv *ppriv,
1530 struct dscc4_dev_priv *dpriv)
1532 struct net_device *dev = dscc4_to_dev(dpriv);
1537 cur = dpriv->iqtx_current%IRQ_RING_SIZE;
1538 state = le32_to_cpu(dpriv->iqtx[cur]);
1541 printk(KERN_DEBUG "%s: Tx ISR = 0x%08x\n", dev->name,
1543 if ((debug > 1) && (loop > 1))
1544 printk(KERN_DEBUG "%s: Tx irq loop=%d\n", dev->name, loop);
1545 if (loop && netif_queue_stopped(dev))
1546 if ((dpriv->tx_current - dpriv->tx_dirty)%TX_RING_SIZE)
1547 netif_wake_queue(dev);
1549 if (netif_running(dev) && dscc4_tx_quiescent(dpriv, dev) &&
1550 !dscc4_tx_done(dpriv))
1551 dscc4_do_tx(dpriv, dev);
1555 dpriv->iqtx[cur] = 0;
1556 dpriv->iqtx_current++;
1558 if (state_check(state, dpriv, dev, "Tx") < 0)
1561 if (state & SccEvt) {
1563 struct sk_buff *skb;
1567 dscc4_tx_print(dev, dpriv, "Alls");
1569 * DataComplete can't be trusted for Tx completion.
1572 cur = dpriv->tx_dirty%TX_RING_SIZE;
1573 tx_fd = dpriv->tx_fd + cur;
1574 skb = dpriv->tx_skbuff[cur];
1576 pci_unmap_single(ppriv->pdev, le32_to_cpu(tx_fd->data),
1577 skb->len, PCI_DMA_TODEVICE);
1578 if (tx_fd->state & FrameEnd) {
1579 dev->stats.tx_packets++;
1580 dev->stats.tx_bytes += skb->len;
1582 dev_kfree_skb_irq(skb);
1583 dpriv->tx_skbuff[cur] = NULL;
1587 netdev_err(dev, "Tx: NULL skb %d\n",
1591 * If the driver ends sending crap on the wire, it
1592 * will be way easier to diagnose than the (not so)
1593 * random freeze induced by null sized tx frames.
1595 tx_fd->data = tx_fd->next;
1596 tx_fd->state = FrameEnd | TO_STATE_TX(2*DUMMY_SKB_SIZE);
1597 tx_fd->complete = 0x00000000;
1600 if (!(state &= ~Alls))
1604 * Transmit Data Underrun
1607 netdev_err(dev, "Tx Data Underrun. Ask maintainer\n");
1608 dpriv->flags = NeedIDT;
1611 dpriv->base_addr + 0x0c*dpriv->dev_id + CH0CFG);
1612 writel(Action, dpriv->base_addr + GCMDR);
1616 netdev_info(dev, "CTS transition\n");
1617 if (!(state &= ~Cts)) /* DEBUG */
1621 /* Frame needs to be sent again - FIXME */
1622 netdev_err(dev, "Tx ReTx. Ask maintainer\n");
1623 if (!(state &= ~Xmr)) /* DEBUG */
1627 void __iomem *scc_addr;
1632 * - the busy condition happens (sometimes);
1633 * - it doesn't seem to make the handler unreliable.
1635 for (i = 1; i; i <<= 1) {
1636 if (!(scc_readl_star(dpriv, dev) & SccBusy))
1640 netdev_info(dev, "busy in irq\n");
1642 scc_addr = dpriv->base_addr + 0x0c*dpriv->dev_id;
1643 /* Keep this order: IDT before IDR */
1644 if (dpriv->flags & NeedIDT) {
1646 dscc4_tx_print(dev, dpriv, "Xpr");
1647 ring = dpriv->tx_fd_dma +
1648 (dpriv->tx_dirty%TX_RING_SIZE)*
1649 sizeof(struct TxFD);
1650 writel(ring, scc_addr + CH0BTDA);
1651 dscc4_do_tx(dpriv, dev);
1652 writel(MTFi | Idt, scc_addr + CH0CFG);
1653 if (dscc4_do_action(dev, "IDT") < 0)
1655 dpriv->flags &= ~NeedIDT;
1657 if (dpriv->flags & NeedIDR) {
1658 ring = dpriv->rx_fd_dma +
1659 (dpriv->rx_current%RX_RING_SIZE)*
1660 sizeof(struct RxFD);
1661 writel(ring, scc_addr + CH0BRDA);
1662 dscc4_rx_update(dpriv, dev);
1663 writel(MTFi | Idr, scc_addr + CH0CFG);
1664 if (dscc4_do_action(dev, "IDR") < 0)
1666 dpriv->flags &= ~NeedIDR;
1668 /* Activate receiver and misc */
1669 scc_writel(0x08050008, dpriv, dev, CCR2);
1672 if (!(state &= ~Xpr))
1677 netdev_info(dev, "CD transition\n");
1678 if (!(state &= ~Cd)) /* DEBUG */
1681 } else { /* ! SccEvt */
1683 #ifdef DSCC4_POLLING
1684 while (!dscc4_tx_poll(dpriv, dev));
1686 netdev_info(dev, "Tx Hi\n");
1690 netdev_info(dev, "Tx ERR\n");
1691 dev->stats.tx_errors++;
1698 static void dscc4_rx_irq(struct dscc4_pci_priv *priv,
1699 struct dscc4_dev_priv *dpriv)
1701 struct net_device *dev = dscc4_to_dev(dpriv);
1706 cur = dpriv->iqrx_current%IRQ_RING_SIZE;
1707 state = le32_to_cpu(dpriv->iqrx[cur]);
1710 dpriv->iqrx[cur] = 0;
1711 dpriv->iqrx_current++;
1713 if (state_check(state, dpriv, dev, "Rx") < 0)
1716 if (!(state & SccEvt)){
1720 printk(KERN_DEBUG "%s: Rx ISR = 0x%08x\n", dev->name,
1722 state &= 0x00ffffff;
1723 if (state & Err) { /* Hold or reset */
1724 printk(KERN_DEBUG "%s: Rx ERR\n", dev->name);
1725 cur = dpriv->rx_current%RX_RING_SIZE;
1726 rx_fd = dpriv->rx_fd + cur;
1728 * Presume we're not facing a DMAC receiver reset.
1729 * As We use the rx size-filtering feature of the
1730 * DSCC4, the beginning of a new frame is waiting in
1731 * the rx fifo. I bet a Receive Data Overflow will
1732 * happen most of time but let's try and avoid it.
1733 * Btw (as for RDO) if one experiences ERR whereas
1734 * the system looks rather idle, there may be a
1735 * problem with latency. In this case, increasing
1736 * RX_RING_SIZE may help.
1738 //while (dpriv->rx_needs_refill) {
1739 while (!(rx_fd->state1 & Hold)) {
1742 if (!(cur = cur%RX_RING_SIZE))
1743 rx_fd = dpriv->rx_fd;
1745 //dpriv->rx_needs_refill--;
1746 try_get_rx_skb(dpriv, dev);
1749 rx_fd->state1 &= ~Hold;
1750 rx_fd->state2 = 0x00000000;
1751 rx_fd->end = cpu_to_le32(0xbabeface);
1756 dscc4_rx_skb(dpriv, dev);
1759 if (state & Hi ) { /* HI bit */
1760 netdev_info(dev, "Rx Hi\n");
1764 } else { /* SccEvt */
1766 //FIXME: verifier la presence de tous les evenements
1769 const char *irq_name;
1771 { 0x00008000, "TIN"},
1772 { 0x00000020, "RSC"},
1773 { 0x00000010, "PCE"},
1774 { 0x00000008, "PLLA"},
1778 for (evt = evts; evt->irq_name; evt++) {
1779 if (state & evt->mask) {
1780 printk(KERN_DEBUG "%s: %s\n",
1781 dev->name, evt->irq_name);
1782 if (!(state &= ~evt->mask))
1787 if (!(state &= ~0x0000c03c))
1791 netdev_info(dev, "CTS transition\n");
1792 if (!(state &= ~Cts)) /* DEBUG */
1796 * Receive Data Overflow (FIXME: fscked)
1800 void __iomem *scc_addr;
1804 // dscc4_rx_dump(dpriv);
1805 scc_addr = dpriv->base_addr + 0x0c*dpriv->dev_id;
1807 scc_patchl(RxActivate, 0, dpriv, dev, CCR2);
1809 * This has no effect. Why ?
1810 * ORed with TxSccRes, one sees the CFG ack (for
1811 * the TX part only).
1813 scc_writel(RxSccRes, dpriv, dev, CMDR);
1814 dpriv->flags |= RdoSet;
1817 * Let's try and save something in the received data.
1818 * rx_current must be incremented at least once to
1819 * avoid HOLD in the BRDA-to-be-pointed desc.
1822 cur = dpriv->rx_current++%RX_RING_SIZE;
1823 rx_fd = dpriv->rx_fd + cur;
1824 if (!(rx_fd->state2 & DataComplete))
1826 if (rx_fd->state2 & FrameAborted) {
1827 dev->stats.rx_over_errors++;
1828 rx_fd->state1 |= Hold;
1829 rx_fd->state2 = 0x00000000;
1830 rx_fd->end = cpu_to_le32(0xbabeface);
1832 dscc4_rx_skb(dpriv, dev);
1836 if (dpriv->flags & RdoSet)
1838 "%s: no RDO in Rx data\n", DRV_NAME);
1840 #ifdef DSCC4_RDO_EXPERIMENTAL_RECOVERY
1842 * FIXME: must the reset be this violent ?
1844 #warning "FIXME: CH0BRDA"
1845 writel(dpriv->rx_fd_dma +
1846 (dpriv->rx_current%RX_RING_SIZE)*
1847 sizeof(struct RxFD), scc_addr + CH0BRDA);
1848 writel(MTFi|Rdr|Idr, scc_addr + CH0CFG);
1849 if (dscc4_do_action(dev, "RDR") < 0) {
1850 netdev_err(dev, "RDO recovery failed(RDR)\n");
1853 writel(MTFi|Idr, scc_addr + CH0CFG);
1854 if (dscc4_do_action(dev, "IDR") < 0) {
1855 netdev_err(dev, "RDO recovery failed(IDR)\n");
1860 scc_patchl(0, RxActivate, dpriv, dev, CCR2);
1864 netdev_info(dev, "CD transition\n");
1865 if (!(state &= ~Cd)) /* DEBUG */
1869 printk(KERN_DEBUG "%s: Flex. Ttttt...\n", DRV_NAME);
1870 if (!(state &= ~Flex))
1877 * I had expected the following to work for the first descriptor
1878 * (tx_fd->state = 0xc0000000)
1879 * - Hold=1 (don't try and branch to the next descripto);
1880 * - No=0 (I want an empty data section, i.e. size=0);
1881 * - Fe=1 (required by No=0 or we got an Err irq and must reset).
1882 * It failed and locked solid. Thus the introduction of a dummy skb.
1883 * Problem is acknowledged in errata sheet DS5. Joy :o/
1885 static struct sk_buff *dscc4_init_dummy_skb(struct dscc4_dev_priv *dpriv)
1887 struct sk_buff *skb;
1889 skb = dev_alloc_skb(DUMMY_SKB_SIZE);
1891 int last = dpriv->tx_dirty%TX_RING_SIZE;
1892 struct TxFD *tx_fd = dpriv->tx_fd + last;
1894 skb->len = DUMMY_SKB_SIZE;
1895 skb_copy_to_linear_data(skb, version,
1896 strlen(version) % DUMMY_SKB_SIZE);
1897 tx_fd->state = FrameEnd | TO_STATE_TX(DUMMY_SKB_SIZE);
1898 tx_fd->data = cpu_to_le32(pci_map_single(dpriv->pci_priv->pdev,
1899 skb->data, DUMMY_SKB_SIZE,
1901 dpriv->tx_skbuff[last] = skb;
1906 static int dscc4_init_ring(struct net_device *dev)
1908 struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
1909 struct pci_dev *pdev = dpriv->pci_priv->pdev;
1915 ring = pci_alloc_consistent(pdev, RX_TOTAL_SIZE, &dpriv->rx_fd_dma);
1918 dpriv->rx_fd = rx_fd = (struct RxFD *) ring;
1920 ring = pci_alloc_consistent(pdev, TX_TOTAL_SIZE, &dpriv->tx_fd_dma);
1922 goto err_free_dma_rx;
1923 dpriv->tx_fd = tx_fd = (struct TxFD *) ring;
1925 memset(dpriv->tx_skbuff, 0, sizeof(struct sk_buff *)*TX_RING_SIZE);
1926 dpriv->tx_dirty = 0xffffffff;
1927 i = dpriv->tx_current = 0;
1929 tx_fd->state = FrameEnd | TO_STATE_TX(2*DUMMY_SKB_SIZE);
1930 tx_fd->complete = 0x00000000;
1931 /* FIXME: NULL should be ok - to be tried */
1932 tx_fd->data = cpu_to_le32(dpriv->tx_fd_dma);
1933 (tx_fd++)->next = cpu_to_le32(dpriv->tx_fd_dma +
1934 (++i%TX_RING_SIZE)*sizeof(*tx_fd));
1935 } while (i < TX_RING_SIZE);
1937 if (!dscc4_init_dummy_skb(dpriv))
1938 goto err_free_dma_tx;
1940 memset(dpriv->rx_skbuff, 0, sizeof(struct sk_buff *)*RX_RING_SIZE);
1941 i = dpriv->rx_dirty = dpriv->rx_current = 0;
1943 /* size set by the host. Multiple of 4 bytes please */
1944 rx_fd->state1 = HiDesc;
1945 rx_fd->state2 = 0x00000000;
1946 rx_fd->end = cpu_to_le32(0xbabeface);
1947 rx_fd->state1 |= TO_STATE_RX(HDLC_MAX_MRU);
1948 // FIXME: return value verifiee mais traitement suspect
1949 if (try_get_rx_skb(dpriv, dev) >= 0)
1951 (rx_fd++)->next = cpu_to_le32(dpriv->rx_fd_dma +
1952 (++i%RX_RING_SIZE)*sizeof(*rx_fd));
1953 } while (i < RX_RING_SIZE);
1958 pci_free_consistent(pdev, TX_TOTAL_SIZE, ring, dpriv->tx_fd_dma);
1960 pci_free_consistent(pdev, RX_TOTAL_SIZE, rx_fd, dpriv->rx_fd_dma);
1965 static void dscc4_remove_one(struct pci_dev *pdev)
1967 struct dscc4_pci_priv *ppriv;
1968 struct dscc4_dev_priv *root;
1969 void __iomem *ioaddr;
1972 ppriv = pci_get_drvdata(pdev);
1975 ioaddr = root->base_addr;
1977 dscc4_pci_reset(pdev, ioaddr);
1979 free_irq(pdev->irq, root);
1980 pci_free_consistent(pdev, IRQ_RING_SIZE*sizeof(u32), ppriv->iqcfg,
1982 for (i = 0; i < dev_per_card; i++) {
1983 struct dscc4_dev_priv *dpriv = root + i;
1985 dscc4_release_ring(dpriv);
1986 pci_free_consistent(pdev, IRQ_RING_SIZE*sizeof(u32),
1987 dpriv->iqrx, dpriv->iqrx_dma);
1988 pci_free_consistent(pdev, IRQ_RING_SIZE*sizeof(u32),
1989 dpriv->iqtx, dpriv->iqtx_dma);
1996 pci_release_region(pdev, 1);
1997 pci_release_region(pdev, 0);
1999 pci_disable_device(pdev);
2002 static int dscc4_hdlc_attach(struct net_device *dev, unsigned short encoding,
2003 unsigned short parity)
2005 struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
2007 if (encoding != ENCODING_NRZ &&
2008 encoding != ENCODING_NRZI &&
2009 encoding != ENCODING_FM_MARK &&
2010 encoding != ENCODING_FM_SPACE &&
2011 encoding != ENCODING_MANCHESTER)
2014 if (parity != PARITY_NONE &&
2015 parity != PARITY_CRC16_PR0_CCITT &&
2016 parity != PARITY_CRC16_PR1_CCITT &&
2017 parity != PARITY_CRC32_PR0_CCITT &&
2018 parity != PARITY_CRC32_PR1_CCITT)
2021 dpriv->encoding = encoding;
2022 dpriv->parity = parity;
2027 static int __init dscc4_setup(char *str)
2029 int *args[] = { &debug, &quartz, NULL }, **p = args;
2031 while (*p && (get_option(&str, *p) == 2))
2036 __setup("dscc4.setup=", dscc4_setup);
2039 static const struct pci_device_id dscc4_pci_tbl[] = {
2040 { PCI_VENDOR_ID_SIEMENS, PCI_DEVICE_ID_SIEMENS_DSCC4,
2041 PCI_ANY_ID, PCI_ANY_ID, },
2044 MODULE_DEVICE_TABLE(pci, dscc4_pci_tbl);
2046 static struct pci_driver dscc4_driver = {
2048 .id_table = dscc4_pci_tbl,
2049 .probe = dscc4_init_one,
2050 .remove = dscc4_remove_one,
2053 module_pci_driver(dscc4_driver);