2 * Cyclades PC300 synchronous serial card driver for Linux
4 * Copyright (C) 2000-2007 Krzysztof Halasa <khc@pm.waw.pl>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of version 2 of the GNU General Public License
8 * as published by the Free Software Foundation.
10 * For information see <http://www.kernel.org/pub/linux/utils/net/hdlc/>.
12 * Sources of information:
13 * Hitachi HD64572 SCA-II User's Manual
14 * Cyclades PC300 Linux driver
16 * This driver currently supports only PC300/RSV (V.24/V.35) and
20 #include <linux/module.h>
21 #include <linux/kernel.h>
22 #include <linux/slab.h>
23 #include <linux/sched.h>
24 #include <linux/types.h>
25 #include <linux/fcntl.h>
27 #include <linux/string.h>
28 #include <linux/errno.h>
29 #include <linux/init.h>
30 #include <linux/ioport.h>
31 #include <linux/moduleparam.h>
32 #include <linux/netdevice.h>
33 #include <linux/hdlc.h>
34 #include <linux/pci.h>
35 #include <linux/delay.h>
40 static const char* version = "Cyclades PC300 driver version: 1.17";
41 static const char* devname = "PC300";
46 #define PC300_PLX_SIZE 0x80 /* PLX control window size (128 B) */
47 #define PC300_SCA_SIZE 0x400 /* SCA window size (1 KB) */
48 #define MAX_TX_BUFFERS 10
50 static int pci_clock_freq = 33000000;
51 static int use_crystal_clock = 0;
52 static unsigned int CLOCK_BASE;
54 /* Masks to access the init_ctrl PLX register */
55 #define PC300_CLKSEL_MASK (0x00000004UL)
56 #define PC300_CHMEDIA_MASK(port) (0x00000020UL << ((port) * 3))
57 #define PC300_CTYPE_MASK (0x00000800UL)
60 enum { PC300_RSV = 1, PC300_X21, PC300_TE }; /* card types */
63 * PLX PCI9050-1 local configuration and shared runtime registers.
64 * This structure can be used to access 9050 registers (memory mapped).
67 u32 loc_addr_range[4]; /* 00-0Ch : Local Address Ranges */
68 u32 loc_rom_range; /* 10h : Local ROM Range */
69 u32 loc_addr_base[4]; /* 14-20h : Local Address Base Addrs */
70 u32 loc_rom_base; /* 24h : Local ROM Base */
71 u32 loc_bus_descr[4]; /* 28-34h : Local Bus Descriptors */
72 u32 rom_bus_descr; /* 38h : ROM Bus Descriptor */
73 u32 cs_base[4]; /* 3C-48h : Chip Select Base Addrs */
74 u32 intr_ctrl_stat; /* 4Ch : Interrupt Control/Status */
75 u32 init_ctrl; /* 50h : EEPROM ctrl, Init Ctrl, etc */
80 typedef struct port_s {
81 struct net_device *dev;
83 spinlock_t lock; /* TX lock */
84 sync_serial_settings settings;
85 int rxpart; /* partial frame received, next frame invalid*/
86 unsigned short encoding;
87 unsigned short parity;
89 u16 rxin; /* rx ring buffer 'in' pointer */
90 u16 txin; /* tx ring buffer 'in' and 'last' pointers */
92 u8 rxs, txs, tmc; /* SCA registers */
93 u8 phy_node; /* physical port # - 0 or 1 */
98 typedef struct card_s {
99 int type; /* RSV, X21, etc. */
100 int n_ports; /* 1 or 2 ports */
101 u8 __iomem *rambase; /* buffer memory base (virtual) */
102 u8 __iomem *scabase; /* SCA memory base (virtual) */
103 plx9050 __iomem *plxbase; /* PLX registers memory base (virtual) */
104 u32 init_ctrl_value; /* Saved value - 9050 bug workaround */
105 u16 rx_ring_buffers; /* number of buffers in a ring */
107 u16 buff_offset; /* offset of first buffer of first channel */
108 u8 irq; /* interrupt request level */
114 #define sca_in(reg, card) readb(card->scabase + (reg))
115 #define sca_out(value, reg, card) writeb(value, card->scabase + (reg))
116 #define sca_inw(reg, card) readw(card->scabase + (reg))
117 #define sca_outw(value, reg, card) writew(value, card->scabase + (reg))
118 #define sca_inl(reg, card) readl(card->scabase + (reg))
119 #define sca_outl(value, reg, card) writel(value, card->scabase + (reg))
121 #define port_to_card(port) (port->card)
122 #define log_node(port) (port->phy_node)
123 #define phy_node(port) (port->phy_node)
124 #define winbase(card) (card->rambase)
125 #define get_port(card, port) ((port) < (card)->n_ports ? \
126 (&(card)->ports[port]) : (NULL))
131 static void pc300_set_iface(port_t *port)
133 card_t *card = port->card;
134 u32 __iomem * init_ctrl = &card->plxbase->init_ctrl;
135 u16 msci = get_msci(port);
136 u8 rxs = port->rxs & CLK_BRG_MASK;
137 u8 txs = port->txs & CLK_BRG_MASK;
139 sca_out(EXS_TES1, (phy_node(port) ? MSCI1_OFFSET : MSCI0_OFFSET) + EXS,
141 switch(port->settings.clock_type) {
143 rxs |= CLK_BRG; /* BRG output */
144 txs |= CLK_PIN_OUT | CLK_TX_RXCLK; /* RX clock */
148 rxs |= CLK_LINE; /* RXC input */
149 txs |= CLK_PIN_OUT | CLK_BRG; /* BRG output */
153 rxs |= CLK_LINE; /* RXC input */
154 txs |= CLK_PIN_OUT | CLK_TX_RXCLK; /* RX clock */
157 default: /* EXTernal clock */
158 rxs |= CLK_LINE; /* RXC input */
159 txs |= CLK_PIN_OUT | CLK_LINE; /* TXC input */
165 sca_out(rxs, msci + RXS, card);
166 sca_out(txs, msci + TXS, card);
169 if (port->card->type == PC300_RSV) {
170 if (port->iface == IF_IFACE_V35)
171 writel(card->init_ctrl_value |
172 PC300_CHMEDIA_MASK(port->phy_node), init_ctrl);
174 writel(card->init_ctrl_value &
175 ~PC300_CHMEDIA_MASK(port->phy_node), init_ctrl);
181 static int pc300_open(struct net_device *dev)
183 port_t *port = dev_to_port(dev);
185 int result = hdlc_open(dev);
190 pc300_set_iface(port);
196 static int pc300_close(struct net_device *dev)
205 static int pc300_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
207 const size_t size = sizeof(sync_serial_settings);
208 sync_serial_settings new_line;
209 sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
211 port_t *port = dev_to_port(dev);
214 if (cmd == SIOCDEVPRIVATE) {
219 if (cmd != SIOCWANDEV)
220 return hdlc_ioctl(dev, ifr, cmd);
222 if (ifr->ifr_settings.type == IF_GET_IFACE) {
223 ifr->ifr_settings.type = port->iface;
224 if (ifr->ifr_settings.size < size) {
225 ifr->ifr_settings.size = size; /* data size wanted */
228 if (copy_to_user(line, &port->settings, size))
234 if (port->card->type == PC300_X21 &&
235 (ifr->ifr_settings.type == IF_IFACE_SYNC_SERIAL ||
236 ifr->ifr_settings.type == IF_IFACE_X21))
237 new_type = IF_IFACE_X21;
239 else if (port->card->type == PC300_RSV &&
240 (ifr->ifr_settings.type == IF_IFACE_SYNC_SERIAL ||
241 ifr->ifr_settings.type == IF_IFACE_V35))
242 new_type = IF_IFACE_V35;
244 else if (port->card->type == PC300_RSV &&
245 ifr->ifr_settings.type == IF_IFACE_V24)
246 new_type = IF_IFACE_V24;
249 return hdlc_ioctl(dev, ifr, cmd);
251 if (!capable(CAP_NET_ADMIN))
254 if (copy_from_user(&new_line, line, size))
257 if (new_line.clock_type != CLOCK_EXT &&
258 new_line.clock_type != CLOCK_TXFROMRX &&
259 new_line.clock_type != CLOCK_INT &&
260 new_line.clock_type != CLOCK_TXINT)
261 return -EINVAL; /* No such clock setting */
263 if (new_line.loopback != 0 && new_line.loopback != 1)
266 memcpy(&port->settings, &new_line, size); /* Update settings */
267 port->iface = new_type;
268 pc300_set_iface(port);
274 static void pc300_pci_remove_one(struct pci_dev *pdev)
277 card_t *card = pci_get_drvdata(pdev);
279 for (i = 0; i < 2; i++)
280 if (card->ports[i].card) {
281 struct net_device *dev = port_to_dev(&card->ports[i]);
282 unregister_hdlc_device(dev);
286 free_irq(card->irq, card);
289 iounmap(card->rambase);
291 iounmap(card->scabase);
293 iounmap(card->plxbase);
295 pci_release_regions(pdev);
296 pci_disable_device(pdev);
297 pci_set_drvdata(pdev, NULL);
298 if (card->ports[0].dev)
299 free_netdev(card->ports[0].dev);
300 if (card->ports[1].dev)
301 free_netdev(card->ports[1].dev);
307 static int __devinit pc300_pci_init_one(struct pci_dev *pdev,
308 const struct pci_device_id *ent)
314 u32 ramphys; /* buffer memory base */
315 u32 scaphys; /* SCA memory base */
316 u32 plxphys; /* PLX registers memory base */
319 static int printed_version;
320 if (!printed_version++)
321 printk(KERN_INFO "%s\n", version);
324 i = pci_enable_device(pdev);
328 i = pci_request_regions(pdev, "PC300");
330 pci_disable_device(pdev);
334 card = kzalloc(sizeof(card_t), GFP_KERNEL);
336 printk(KERN_ERR "pc300: unable to allocate memory\n");
337 pci_release_regions(pdev);
338 pci_disable_device(pdev);
341 pci_set_drvdata(pdev, card);
343 if (pdev->device == PCI_DEVICE_ID_PC300_TE_1 ||
344 pdev->device == PCI_DEVICE_ID_PC300_TE_2)
345 card->type = PC300_TE; /* not fully supported */
346 else if (card->init_ctrl_value & PC300_CTYPE_MASK)
347 card->type = PC300_X21;
349 card->type = PC300_RSV;
351 if (pdev->device == PCI_DEVICE_ID_PC300_RX_1 ||
352 pdev->device == PCI_DEVICE_ID_PC300_TE_1)
357 for (i = 0; i < card->n_ports; i++)
358 if (!(card->ports[i].dev = alloc_hdlcdev(&card->ports[i]))) {
359 printk(KERN_ERR "pc300: unable to allocate memory\n");
360 pc300_pci_remove_one(pdev);
364 if (pci_resource_len(pdev, 0) != PC300_PLX_SIZE ||
365 pci_resource_len(pdev, 2) != PC300_SCA_SIZE ||
366 pci_resource_len(pdev, 3) < 16384) {
367 printk(KERN_ERR "pc300: invalid card EEPROM parameters\n");
368 pc300_pci_remove_one(pdev);
372 plxphys = pci_resource_start(pdev,0) & PCI_BASE_ADDRESS_MEM_MASK;
373 card->plxbase = ioremap(plxphys, PC300_PLX_SIZE);
375 scaphys = pci_resource_start(pdev,2) & PCI_BASE_ADDRESS_MEM_MASK;
376 card->scabase = ioremap(scaphys, PC300_SCA_SIZE);
378 ramphys = pci_resource_start(pdev,3) & PCI_BASE_ADDRESS_MEM_MASK;
379 card->rambase = pci_ioremap_bar(pdev, 3);
381 if (card->plxbase == NULL ||
382 card->scabase == NULL ||
383 card->rambase == NULL) {
384 printk(KERN_ERR "pc300: ioremap() failed\n");
385 pc300_pci_remove_one(pdev);
388 /* PLX PCI 9050 workaround for local configuration register read bug */
389 pci_write_config_dword(pdev, PCI_BASE_ADDRESS_0, scaphys);
390 card->init_ctrl_value = readl(&((plx9050 __iomem *)card->scabase)->init_ctrl);
391 pci_write_config_dword(pdev, PCI_BASE_ADDRESS_0, plxphys);
394 p = &card->plxbase->init_ctrl;
395 writel(card->init_ctrl_value | 0x40000000, p);
396 readl(p); /* Flush the write - do not use sca_flush */
399 writel(card->init_ctrl_value, p);
400 readl(p); /* Flush the write - do not use sca_flush */
403 /* Reload Config. Registers from EEPROM */
404 writel(card->init_ctrl_value | 0x20000000, p);
405 readl(p); /* Flush the write - do not use sca_flush */
408 writel(card->init_ctrl_value, p);
409 readl(p); /* Flush the write - do not use sca_flush */
412 ramsize = sca_detect_ram(card, card->rambase,
413 pci_resource_len(pdev, 3));
415 if (use_crystal_clock)
416 card->init_ctrl_value &= ~PC300_CLKSEL_MASK;
418 card->init_ctrl_value |= PC300_CLKSEL_MASK;
420 writel(card->init_ctrl_value, &card->plxbase->init_ctrl);
421 /* number of TX + RX buffers for one port */
422 i = ramsize / (card->n_ports * (sizeof(pkt_desc) + HDLC_MAX_MRU));
423 card->tx_ring_buffers = min(i / 2, MAX_TX_BUFFERS);
424 card->rx_ring_buffers = i - card->tx_ring_buffers;
426 card->buff_offset = card->n_ports * sizeof(pkt_desc) *
427 (card->tx_ring_buffers + card->rx_ring_buffers);
429 printk(KERN_INFO "pc300: PC300/%s, %u KB RAM at 0x%x, IRQ%u, "
430 "using %u TX + %u RX packets rings\n",
431 card->type == PC300_X21 ? "X21" :
432 card->type == PC300_TE ? "TE" : "RSV",
433 ramsize / 1024, ramphys, pdev->irq,
434 card->tx_ring_buffers, card->rx_ring_buffers);
436 if (card->tx_ring_buffers < 1) {
437 printk(KERN_ERR "pc300: RAM test failed\n");
438 pc300_pci_remove_one(pdev);
442 /* Enable interrupts on the PCI bridge, LINTi1 active low */
443 writew(0x0041, &card->plxbase->intr_ctrl_stat);
446 if (request_irq(pdev->irq, sca_intr, IRQF_SHARED, devname, card)) {
447 printk(KERN_WARNING "pc300: could not allocate IRQ%d.\n",
449 pc300_pci_remove_one(pdev);
452 card->irq = pdev->irq;
456 // COTE not set - allows better TX DMA settings
457 // sca_out(sca_in(PCR, card) | PCR_COTE, PCR, card);
459 sca_out(0x10, BTCR, card);
461 for (i = 0; i < card->n_ports; i++) {
462 port_t *port = &card->ports[i];
463 struct net_device *dev = port_to_dev(port);
464 hdlc_device *hdlc = dev_to_hdlc(dev);
467 spin_lock_init(&port->lock);
468 dev->irq = card->irq;
469 dev->mem_start = ramphys;
470 dev->mem_end = ramphys + ramsize - 1;
471 dev->tx_queue_len = 50;
472 dev->do_ioctl = pc300_ioctl;
473 dev->open = pc300_open;
474 dev->stop = pc300_close;
475 hdlc->attach = sca_attach;
476 hdlc->xmit = sca_xmit;
477 port->settings.clock_type = CLOCK_EXT;
479 if (card->type == PC300_X21)
480 port->iface = IF_IFACE_X21;
482 port->iface = IF_IFACE_V35;
484 if (register_hdlc_device(dev)) {
485 printk(KERN_ERR "pc300: unable to register hdlc "
488 pc300_pci_remove_one(pdev);
491 sca_init_port(port); /* Set up SCA memory */
493 printk(KERN_INFO "%s: PC300 node %d\n",
494 dev->name, port->phy_node);
501 static struct pci_device_id pc300_pci_tbl[] __devinitdata = {
502 { PCI_VENDOR_ID_CYCLADES, PCI_DEVICE_ID_PC300_RX_1, PCI_ANY_ID,
503 PCI_ANY_ID, 0, 0, 0 },
504 { PCI_VENDOR_ID_CYCLADES, PCI_DEVICE_ID_PC300_RX_2, PCI_ANY_ID,
505 PCI_ANY_ID, 0, 0, 0 },
506 { PCI_VENDOR_ID_CYCLADES, PCI_DEVICE_ID_PC300_TE_1, PCI_ANY_ID,
507 PCI_ANY_ID, 0, 0, 0 },
508 { PCI_VENDOR_ID_CYCLADES, PCI_DEVICE_ID_PC300_TE_2, PCI_ANY_ID,
509 PCI_ANY_ID, 0, 0, 0 },
514 static struct pci_driver pc300_pci_driver = {
516 .id_table = pc300_pci_tbl,
517 .probe = pc300_pci_init_one,
518 .remove = pc300_pci_remove_one,
522 static int __init pc300_init_module(void)
525 printk(KERN_INFO "%s\n", version);
527 if (pci_clock_freq < 1000000 || pci_clock_freq > 80000000) {
528 printk(KERN_ERR "pc300: Invalid PCI clock frequency\n");
531 if (use_crystal_clock != 0 && use_crystal_clock != 1) {
532 printk(KERN_ERR "pc300: Invalid 'use_crystal_clock' value\n");
536 CLOCK_BASE = use_crystal_clock ? 24576000 : pci_clock_freq;
538 return pci_register_driver(&pc300_pci_driver);
543 static void __exit pc300_cleanup_module(void)
545 pci_unregister_driver(&pc300_pci_driver);
548 MODULE_AUTHOR("Krzysztof Halasa <khc@pm.waw.pl>");
549 MODULE_DESCRIPTION("Cyclades PC300 serial port driver");
550 MODULE_LICENSE("GPL v2");
551 MODULE_DEVICE_TABLE(pci, pc300_pci_tbl);
552 module_param(pci_clock_freq, int, 0444);
553 MODULE_PARM_DESC(pci_clock_freq, "System PCI clock frequency in Hz");
554 module_param(use_crystal_clock, int, 0444);
555 MODULE_PARM_DESC(use_crystal_clock,
556 "Use 24.576 MHz clock instead of PCI clock");
557 module_init(pc300_init_module);
558 module_exit(pc300_cleanup_module);