2 * Copyright (c) 2005-2011 Atheros Communications Inc.
3 * Copyright (c) 2011-2013 Qualcomm Atheros, Inc.
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
24 * Support for Copy Engine hardware, which is mainly used for
25 * communication between Host and Target over a PCIe interconnect.
29 * A single CopyEngine (CE) comprises two "rings":
33 * Each ring consists of a number of descriptors which specify
34 * an address, length, and meta-data.
36 * Typically, one side of the PCIe interconnect (Host or Target)
37 * controls one ring and the other side controls the other ring.
38 * The source side chooses when to initiate a transfer and it
39 * chooses what to send (buffer address, length). The destination
40 * side keeps a supply of "anonymous receive buffers" available and
41 * it handles incoming data as it arrives (when the destination
42 * recieves an interrupt).
44 * The sender may send a simple buffer (address/length) or it may
45 * send a small list of buffers. When a small list is sent, hardware
46 * "gathers" these and they end up in a single destination buffer
47 * with a single interrupt.
49 * There are several "contexts" managed by this layer -- more, it
50 * may seem -- than should be needed. These are provided mainly for
51 * maximum flexibility and especially to facilitate a simpler HIF
52 * implementation. There are per-CopyEngine recv, send, and watermark
53 * contexts. These are supplied by the caller when a recv, send,
54 * or watermark handler is established and they are echoed back to
55 * the caller when the respective callbacks are invoked. There is
56 * also a per-transfer context supplied by the caller when a buffer
57 * (or sendlist) is sent and when a buffer is enqueued for recv.
58 * These per-transfer contexts are echoed back to the caller when
59 * the buffer is sent/received.
62 static inline void ath10k_ce_dest_ring_write_index_set(struct ath10k *ar,
66 ath10k_pci_write32(ar, ce_ctrl_addr + DST_WR_INDEX_ADDRESS, n);
69 static inline u32 ath10k_ce_dest_ring_write_index_get(struct ath10k *ar,
72 return ath10k_pci_read32(ar, ce_ctrl_addr + DST_WR_INDEX_ADDRESS);
75 static inline void ath10k_ce_src_ring_write_index_set(struct ath10k *ar,
79 ath10k_pci_write32(ar, ce_ctrl_addr + SR_WR_INDEX_ADDRESS, n);
82 static inline u32 ath10k_ce_src_ring_write_index_get(struct ath10k *ar,
85 return ath10k_pci_read32(ar, ce_ctrl_addr + SR_WR_INDEX_ADDRESS);
88 static inline u32 ath10k_ce_src_ring_read_index_get(struct ath10k *ar,
91 return ath10k_pci_read32(ar, ce_ctrl_addr + CURRENT_SRRI_ADDRESS);
94 static inline void ath10k_ce_src_ring_base_addr_set(struct ath10k *ar,
98 ath10k_pci_write32(ar, ce_ctrl_addr + SR_BA_ADDRESS, addr);
101 static inline void ath10k_ce_src_ring_size_set(struct ath10k *ar,
105 ath10k_pci_write32(ar, ce_ctrl_addr + SR_SIZE_ADDRESS, n);
108 static inline void ath10k_ce_src_ring_dmax_set(struct ath10k *ar,
112 u32 ctrl1_addr = ath10k_pci_read32((ar),
113 (ce_ctrl_addr) + CE_CTRL1_ADDRESS);
115 ath10k_pci_write32(ar, ce_ctrl_addr + CE_CTRL1_ADDRESS,
116 (ctrl1_addr & ~CE_CTRL1_DMAX_LENGTH_MASK) |
117 CE_CTRL1_DMAX_LENGTH_SET(n));
120 static inline void ath10k_ce_src_ring_byte_swap_set(struct ath10k *ar,
124 u32 ctrl1_addr = ath10k_pci_read32(ar, ce_ctrl_addr + CE_CTRL1_ADDRESS);
126 ath10k_pci_write32(ar, ce_ctrl_addr + CE_CTRL1_ADDRESS,
127 (ctrl1_addr & ~CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK) |
128 CE_CTRL1_SRC_RING_BYTE_SWAP_EN_SET(n));
131 static inline void ath10k_ce_dest_ring_byte_swap_set(struct ath10k *ar,
135 u32 ctrl1_addr = ath10k_pci_read32(ar, ce_ctrl_addr + CE_CTRL1_ADDRESS);
137 ath10k_pci_write32(ar, ce_ctrl_addr + CE_CTRL1_ADDRESS,
138 (ctrl1_addr & ~CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK) |
139 CE_CTRL1_DST_RING_BYTE_SWAP_EN_SET(n));
142 static inline u32 ath10k_ce_dest_ring_read_index_get(struct ath10k *ar,
145 return ath10k_pci_read32(ar, ce_ctrl_addr + CURRENT_DRRI_ADDRESS);
148 static inline void ath10k_ce_dest_ring_base_addr_set(struct ath10k *ar,
152 ath10k_pci_write32(ar, ce_ctrl_addr + DR_BA_ADDRESS, addr);
155 static inline void ath10k_ce_dest_ring_size_set(struct ath10k *ar,
159 ath10k_pci_write32(ar, ce_ctrl_addr + DR_SIZE_ADDRESS, n);
162 static inline void ath10k_ce_src_ring_highmark_set(struct ath10k *ar,
166 u32 addr = ath10k_pci_read32(ar, ce_ctrl_addr + SRC_WATERMARK_ADDRESS);
168 ath10k_pci_write32(ar, ce_ctrl_addr + SRC_WATERMARK_ADDRESS,
169 (addr & ~SRC_WATERMARK_HIGH_MASK) |
170 SRC_WATERMARK_HIGH_SET(n));
173 static inline void ath10k_ce_src_ring_lowmark_set(struct ath10k *ar,
177 u32 addr = ath10k_pci_read32(ar, ce_ctrl_addr + SRC_WATERMARK_ADDRESS);
179 ath10k_pci_write32(ar, ce_ctrl_addr + SRC_WATERMARK_ADDRESS,
180 (addr & ~SRC_WATERMARK_LOW_MASK) |
181 SRC_WATERMARK_LOW_SET(n));
184 static inline void ath10k_ce_dest_ring_highmark_set(struct ath10k *ar,
188 u32 addr = ath10k_pci_read32(ar, ce_ctrl_addr + DST_WATERMARK_ADDRESS);
190 ath10k_pci_write32(ar, ce_ctrl_addr + DST_WATERMARK_ADDRESS,
191 (addr & ~DST_WATERMARK_HIGH_MASK) |
192 DST_WATERMARK_HIGH_SET(n));
195 static inline void ath10k_ce_dest_ring_lowmark_set(struct ath10k *ar,
199 u32 addr = ath10k_pci_read32(ar, ce_ctrl_addr + DST_WATERMARK_ADDRESS);
201 ath10k_pci_write32(ar, ce_ctrl_addr + DST_WATERMARK_ADDRESS,
202 (addr & ~DST_WATERMARK_LOW_MASK) |
203 DST_WATERMARK_LOW_SET(n));
206 static inline void ath10k_ce_copy_complete_inter_enable(struct ath10k *ar,
209 u32 host_ie_addr = ath10k_pci_read32(ar,
210 ce_ctrl_addr + HOST_IE_ADDRESS);
212 ath10k_pci_write32(ar, ce_ctrl_addr + HOST_IE_ADDRESS,
213 host_ie_addr | HOST_IE_COPY_COMPLETE_MASK);
216 static inline void ath10k_ce_copy_complete_intr_disable(struct ath10k *ar,
219 u32 host_ie_addr = ath10k_pci_read32(ar,
220 ce_ctrl_addr + HOST_IE_ADDRESS);
222 ath10k_pci_write32(ar, ce_ctrl_addr + HOST_IE_ADDRESS,
223 host_ie_addr & ~HOST_IE_COPY_COMPLETE_MASK);
226 static inline void ath10k_ce_watermark_intr_disable(struct ath10k *ar,
229 u32 host_ie_addr = ath10k_pci_read32(ar,
230 ce_ctrl_addr + HOST_IE_ADDRESS);
232 ath10k_pci_write32(ar, ce_ctrl_addr + HOST_IE_ADDRESS,
233 host_ie_addr & ~CE_WATERMARK_MASK);
236 static inline void ath10k_ce_error_intr_enable(struct ath10k *ar,
239 u32 misc_ie_addr = ath10k_pci_read32(ar,
240 ce_ctrl_addr + MISC_IE_ADDRESS);
242 ath10k_pci_write32(ar, ce_ctrl_addr + MISC_IE_ADDRESS,
243 misc_ie_addr | CE_ERROR_MASK);
246 static inline void ath10k_ce_engine_int_status_clear(struct ath10k *ar,
250 ath10k_pci_write32(ar, ce_ctrl_addr + HOST_IS_ADDRESS, mask);
255 * Guts of ath10k_ce_send, used by both ath10k_ce_send and
256 * ath10k_ce_sendlist_send.
257 * The caller takes responsibility for any needed locking.
259 static int ath10k_ce_send_nolock(struct ath10k_ce_pipe *ce_state,
260 void *per_transfer_context,
263 unsigned int transfer_id,
266 struct ath10k *ar = ce_state->ar;
267 struct ath10k_ce_ring *src_ring = ce_state->src_ring;
268 struct ce_desc *desc, *sdesc;
269 unsigned int nentries_mask = src_ring->nentries_mask;
270 unsigned int sw_index = src_ring->sw_index;
271 unsigned int write_index = src_ring->write_index;
272 u32 ctrl_addr = ce_state->ctrl_addr;
276 if (nbytes > ce_state->src_sz_max)
277 ath10k_warn("%s: send more we can (nbytes: %d, max: %d)\n",
278 __func__, nbytes, ce_state->src_sz_max);
280 ret = ath10k_pci_wake(ar);
284 if (unlikely(CE_RING_DELTA(nentries_mask,
285 write_index, sw_index - 1) <= 0)) {
290 desc = CE_SRC_RING_TO_DESC(src_ring->base_addr_owner_space,
292 sdesc = CE_SRC_RING_TO_DESC(src_ring->shadow_base, write_index);
294 desc_flags |= SM(transfer_id, CE_DESC_FLAGS_META_DATA);
296 if (flags & CE_SEND_FLAG_GATHER)
297 desc_flags |= CE_DESC_FLAGS_GATHER;
298 if (flags & CE_SEND_FLAG_BYTE_SWAP)
299 desc_flags |= CE_DESC_FLAGS_BYTE_SWAP;
301 sdesc->addr = __cpu_to_le32(buffer);
302 sdesc->nbytes = __cpu_to_le16(nbytes);
303 sdesc->flags = __cpu_to_le16(desc_flags);
307 src_ring->per_transfer_context[write_index] = per_transfer_context;
309 /* Update Source Ring Write Index */
310 write_index = CE_RING_IDX_INCR(nentries_mask, write_index);
313 if (!(flags & CE_SEND_FLAG_GATHER))
314 ath10k_ce_src_ring_write_index_set(ar, ctrl_addr, write_index);
316 src_ring->write_index = write_index;
318 ath10k_pci_sleep(ar);
322 int ath10k_ce_send(struct ath10k_ce_pipe *ce_state,
323 void *per_transfer_context,
326 unsigned int transfer_id,
329 struct ath10k *ar = ce_state->ar;
330 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
333 spin_lock_bh(&ar_pci->ce_lock);
334 ret = ath10k_ce_send_nolock(ce_state, per_transfer_context,
335 buffer, nbytes, transfer_id, flags);
336 spin_unlock_bh(&ar_pci->ce_lock);
341 void ath10k_ce_sendlist_buf_add(struct ce_sendlist *sendlist, u32 buffer,
342 unsigned int nbytes, u32 flags)
344 unsigned int num_items = sendlist->num_items;
345 struct ce_sendlist_item *item;
347 item = &sendlist->item[num_items];
349 item->u.nbytes = nbytes;
351 sendlist->num_items++;
354 int ath10k_ce_sendlist_send(struct ath10k_ce_pipe *ce_state,
355 void *per_transfer_context,
356 struct ce_sendlist *sendlist,
357 unsigned int transfer_id)
359 struct ath10k_ce_ring *src_ring = ce_state->src_ring;
360 struct ce_sendlist_item *item;
361 struct ath10k *ar = ce_state->ar;
362 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
363 unsigned int nentries_mask = src_ring->nentries_mask;
364 unsigned int num_items = sendlist->num_items;
365 unsigned int sw_index;
366 unsigned int write_index;
367 int i, delta, ret = -ENOMEM;
369 spin_lock_bh(&ar_pci->ce_lock);
371 sw_index = src_ring->sw_index;
372 write_index = src_ring->write_index;
374 delta = CE_RING_DELTA(nentries_mask, write_index, sw_index - 1);
376 if (delta >= num_items) {
378 * Handle all but the last item uniformly.
380 for (i = 0; i < num_items - 1; i++) {
381 item = &sendlist->item[i];
382 ret = ath10k_ce_send_nolock(ce_state,
383 CE_SENDLIST_ITEM_CTXT,
385 item->u.nbytes, transfer_id,
387 CE_SEND_FLAG_GATHER);
389 ath10k_warn("CE send failed for item: %d\n", i);
392 * Provide valid context pointer for final item.
394 item = &sendlist->item[i];
395 ret = ath10k_ce_send_nolock(ce_state, per_transfer_context,
396 (u32) item->data, item->u.nbytes,
397 transfer_id, item->flags);
399 ath10k_warn("CE send failed for last item: %d\n", i);
402 spin_unlock_bh(&ar_pci->ce_lock);
407 int ath10k_ce_recv_buf_enqueue(struct ath10k_ce_pipe *ce_state,
408 void *per_recv_context,
411 struct ath10k_ce_ring *dest_ring = ce_state->dest_ring;
412 u32 ctrl_addr = ce_state->ctrl_addr;
413 struct ath10k *ar = ce_state->ar;
414 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
415 unsigned int nentries_mask = dest_ring->nentries_mask;
416 unsigned int write_index;
417 unsigned int sw_index;
420 spin_lock_bh(&ar_pci->ce_lock);
421 write_index = dest_ring->write_index;
422 sw_index = dest_ring->sw_index;
424 ret = ath10k_pci_wake(ar);
428 if (CE_RING_DELTA(nentries_mask, write_index, sw_index - 1) > 0) {
429 struct ce_desc *base = dest_ring->base_addr_owner_space;
430 struct ce_desc *desc = CE_DEST_RING_TO_DESC(base, write_index);
432 /* Update destination descriptor */
433 desc->addr = __cpu_to_le32(buffer);
436 dest_ring->per_transfer_context[write_index] =
439 /* Update Destination Ring Write Index */
440 write_index = CE_RING_IDX_INCR(nentries_mask, write_index);
441 ath10k_ce_dest_ring_write_index_set(ar, ctrl_addr, write_index);
442 dest_ring->write_index = write_index;
447 ath10k_pci_sleep(ar);
450 spin_unlock_bh(&ar_pci->ce_lock);
456 * Guts of ath10k_ce_completed_recv_next.
457 * The caller takes responsibility for any necessary locking.
459 static int ath10k_ce_completed_recv_next_nolock(struct ath10k_ce_pipe *ce_state,
460 void **per_transfer_contextp,
462 unsigned int *nbytesp,
463 unsigned int *transfer_idp,
464 unsigned int *flagsp)
466 struct ath10k_ce_ring *dest_ring = ce_state->dest_ring;
467 unsigned int nentries_mask = dest_ring->nentries_mask;
468 unsigned int sw_index = dest_ring->sw_index;
470 struct ce_desc *base = dest_ring->base_addr_owner_space;
471 struct ce_desc *desc = CE_DEST_RING_TO_DESC(base, sw_index);
472 struct ce_desc sdesc;
475 /* Copy in one go for performance reasons */
478 nbytes = __le16_to_cpu(sdesc.nbytes);
481 * This closes a relatively unusual race where the Host
482 * sees the updated DRRI before the update to the
483 * corresponding descriptor has completed. We treat this
484 * as a descriptor that is not yet done.
491 /* Return data from completed destination descriptor */
492 *bufferp = __le32_to_cpu(sdesc.addr);
494 *transfer_idp = MS(__le16_to_cpu(sdesc.flags), CE_DESC_FLAGS_META_DATA);
496 if (__le16_to_cpu(sdesc.flags) & CE_DESC_FLAGS_BYTE_SWAP)
497 *flagsp = CE_RECV_FLAG_SWAPPED;
501 if (per_transfer_contextp)
502 *per_transfer_contextp =
503 dest_ring->per_transfer_context[sw_index];
506 dest_ring->per_transfer_context[sw_index] = NULL;
508 /* Update sw_index */
509 sw_index = CE_RING_IDX_INCR(nentries_mask, sw_index);
510 dest_ring->sw_index = sw_index;
515 int ath10k_ce_completed_recv_next(struct ath10k_ce_pipe *ce_state,
516 void **per_transfer_contextp,
518 unsigned int *nbytesp,
519 unsigned int *transfer_idp,
520 unsigned int *flagsp)
522 struct ath10k *ar = ce_state->ar;
523 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
526 spin_lock_bh(&ar_pci->ce_lock);
527 ret = ath10k_ce_completed_recv_next_nolock(ce_state,
528 per_transfer_contextp,
530 transfer_idp, flagsp);
531 spin_unlock_bh(&ar_pci->ce_lock);
536 int ath10k_ce_revoke_recv_next(struct ath10k_ce_pipe *ce_state,
537 void **per_transfer_contextp,
540 struct ath10k_ce_ring *dest_ring;
541 unsigned int nentries_mask;
542 unsigned int sw_index;
543 unsigned int write_index;
546 struct ath10k_pci *ar_pci;
548 dest_ring = ce_state->dest_ring;
554 ar_pci = ath10k_pci_priv(ar);
556 spin_lock_bh(&ar_pci->ce_lock);
558 nentries_mask = dest_ring->nentries_mask;
559 sw_index = dest_ring->sw_index;
560 write_index = dest_ring->write_index;
561 if (write_index != sw_index) {
562 struct ce_desc *base = dest_ring->base_addr_owner_space;
563 struct ce_desc *desc = CE_DEST_RING_TO_DESC(base, sw_index);
565 /* Return data from completed destination descriptor */
566 *bufferp = __le32_to_cpu(desc->addr);
568 if (per_transfer_contextp)
569 *per_transfer_contextp =
570 dest_ring->per_transfer_context[sw_index];
573 dest_ring->per_transfer_context[sw_index] = NULL;
575 /* Update sw_index */
576 sw_index = CE_RING_IDX_INCR(nentries_mask, sw_index);
577 dest_ring->sw_index = sw_index;
583 spin_unlock_bh(&ar_pci->ce_lock);
589 * Guts of ath10k_ce_completed_send_next.
590 * The caller takes responsibility for any necessary locking.
592 static int ath10k_ce_completed_send_next_nolock(struct ath10k_ce_pipe *ce_state,
593 void **per_transfer_contextp,
595 unsigned int *nbytesp,
596 unsigned int *transfer_idp)
598 struct ath10k_ce_ring *src_ring = ce_state->src_ring;
599 u32 ctrl_addr = ce_state->ctrl_addr;
600 struct ath10k *ar = ce_state->ar;
601 unsigned int nentries_mask = src_ring->nentries_mask;
602 unsigned int sw_index = src_ring->sw_index;
603 struct ce_desc *sdesc, *sbase;
604 unsigned int read_index;
607 if (src_ring->hw_index == sw_index) {
609 * The SW completion index has caught up with the cached
610 * version of the HW completion index.
611 * Update the cached HW completion index to see whether
612 * the SW has really caught up to the HW, or if the cached
613 * value of the HW index has become stale.
616 ret = ath10k_pci_wake(ar);
621 ath10k_ce_src_ring_read_index_get(ar, ctrl_addr);
622 src_ring->hw_index &= nentries_mask;
624 ath10k_pci_sleep(ar);
627 read_index = src_ring->hw_index;
629 if ((read_index == sw_index) || (read_index == 0xffffffff))
632 sbase = src_ring->shadow_base;
633 sdesc = CE_SRC_RING_TO_DESC(sbase, sw_index);
635 /* Return data from completed source descriptor */
636 *bufferp = __le32_to_cpu(sdesc->addr);
637 *nbytesp = __le16_to_cpu(sdesc->nbytes);
638 *transfer_idp = MS(__le16_to_cpu(sdesc->flags),
639 CE_DESC_FLAGS_META_DATA);
641 if (per_transfer_contextp)
642 *per_transfer_contextp =
643 src_ring->per_transfer_context[sw_index];
646 src_ring->per_transfer_context[sw_index] = NULL;
648 /* Update sw_index */
649 sw_index = CE_RING_IDX_INCR(nentries_mask, sw_index);
650 src_ring->sw_index = sw_index;
655 /* NB: Modeled after ath10k_ce_completed_send_next */
656 int ath10k_ce_cancel_send_next(struct ath10k_ce_pipe *ce_state,
657 void **per_transfer_contextp,
659 unsigned int *nbytesp,
660 unsigned int *transfer_idp)
662 struct ath10k_ce_ring *src_ring;
663 unsigned int nentries_mask;
664 unsigned int sw_index;
665 unsigned int write_index;
668 struct ath10k_pci *ar_pci;
670 src_ring = ce_state->src_ring;
676 ar_pci = ath10k_pci_priv(ar);
678 spin_lock_bh(&ar_pci->ce_lock);
680 nentries_mask = src_ring->nentries_mask;
681 sw_index = src_ring->sw_index;
682 write_index = src_ring->write_index;
684 if (write_index != sw_index) {
685 struct ce_desc *base = src_ring->base_addr_owner_space;
686 struct ce_desc *desc = CE_SRC_RING_TO_DESC(base, sw_index);
688 /* Return data from completed source descriptor */
689 *bufferp = __le32_to_cpu(desc->addr);
690 *nbytesp = __le16_to_cpu(desc->nbytes);
691 *transfer_idp = MS(__le16_to_cpu(desc->flags),
692 CE_DESC_FLAGS_META_DATA);
694 if (per_transfer_contextp)
695 *per_transfer_contextp =
696 src_ring->per_transfer_context[sw_index];
699 src_ring->per_transfer_context[sw_index] = NULL;
701 /* Update sw_index */
702 sw_index = CE_RING_IDX_INCR(nentries_mask, sw_index);
703 src_ring->sw_index = sw_index;
709 spin_unlock_bh(&ar_pci->ce_lock);
714 int ath10k_ce_completed_send_next(struct ath10k_ce_pipe *ce_state,
715 void **per_transfer_contextp,
717 unsigned int *nbytesp,
718 unsigned int *transfer_idp)
720 struct ath10k *ar = ce_state->ar;
721 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
724 spin_lock_bh(&ar_pci->ce_lock);
725 ret = ath10k_ce_completed_send_next_nolock(ce_state,
726 per_transfer_contextp,
729 spin_unlock_bh(&ar_pci->ce_lock);
735 * Guts of interrupt handler for per-engine interrupts on a particular CE.
737 * Invokes registered callbacks for recv_complete,
738 * send_complete, and watermarks.
740 void ath10k_ce_per_engine_service(struct ath10k *ar, unsigned int ce_id)
742 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
743 struct ath10k_ce_pipe *ce_state = &ar_pci->ce_states[ce_id];
744 u32 ctrl_addr = ce_state->ctrl_addr;
747 ret = ath10k_pci_wake(ar);
751 spin_lock_bh(&ar_pci->ce_lock);
753 /* Clear the copy-complete interrupts that will be handled here. */
754 ath10k_ce_engine_int_status_clear(ar, ctrl_addr,
755 HOST_IS_COPY_COMPLETE_MASK);
757 spin_unlock_bh(&ar_pci->ce_lock);
759 if (ce_state->recv_cb)
760 ce_state->recv_cb(ce_state);
762 if (ce_state->send_cb)
763 ce_state->send_cb(ce_state);
765 spin_lock_bh(&ar_pci->ce_lock);
768 * Misc CE interrupts are not being handled, but still need
771 ath10k_ce_engine_int_status_clear(ar, ctrl_addr, CE_WATERMARK_MASK);
773 spin_unlock_bh(&ar_pci->ce_lock);
774 ath10k_pci_sleep(ar);
778 * Handler for per-engine interrupts on ALL active CEs.
779 * This is used in cases where the system is sharing a
780 * single interrput for all CEs
783 void ath10k_ce_per_engine_service_any(struct ath10k *ar)
785 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
789 ret = ath10k_pci_wake(ar);
793 intr_summary = CE_INTERRUPT_SUMMARY(ar);
795 for (ce_id = 0; intr_summary && (ce_id < ar_pci->ce_count); ce_id++) {
796 if (intr_summary & (1 << ce_id))
797 intr_summary &= ~(1 << ce_id);
799 /* no intr pending on this CE */
802 ath10k_ce_per_engine_service(ar, ce_id);
805 ath10k_pci_sleep(ar);
809 * Adjust interrupts for the copy complete handler.
810 * If it's needed for either send or recv, then unmask
811 * this interrupt; otherwise, mask it.
813 * Called with ce_lock held.
815 static void ath10k_ce_per_engine_handler_adjust(struct ath10k_ce_pipe *ce_state,
816 int disable_copy_compl_intr)
818 u32 ctrl_addr = ce_state->ctrl_addr;
819 struct ath10k *ar = ce_state->ar;
822 ret = ath10k_pci_wake(ar);
826 if ((!disable_copy_compl_intr) &&
827 (ce_state->send_cb || ce_state->recv_cb))
828 ath10k_ce_copy_complete_inter_enable(ar, ctrl_addr);
830 ath10k_ce_copy_complete_intr_disable(ar, ctrl_addr);
832 ath10k_ce_watermark_intr_disable(ar, ctrl_addr);
834 ath10k_pci_sleep(ar);
837 void ath10k_ce_disable_interrupts(struct ath10k *ar)
839 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
842 ret = ath10k_pci_wake(ar);
846 for (ce_id = 0; ce_id < ar_pci->ce_count; ce_id++) {
847 struct ath10k_ce_pipe *ce_state = &ar_pci->ce_states[ce_id];
848 u32 ctrl_addr = ce_state->ctrl_addr;
850 ath10k_ce_copy_complete_intr_disable(ar, ctrl_addr);
852 ath10k_pci_sleep(ar);
855 void ath10k_ce_send_cb_register(struct ath10k_ce_pipe *ce_state,
856 void (*send_cb)(struct ath10k_ce_pipe *),
857 int disable_interrupts)
859 struct ath10k *ar = ce_state->ar;
860 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
862 spin_lock_bh(&ar_pci->ce_lock);
863 ce_state->send_cb = send_cb;
864 ath10k_ce_per_engine_handler_adjust(ce_state, disable_interrupts);
865 spin_unlock_bh(&ar_pci->ce_lock);
868 void ath10k_ce_recv_cb_register(struct ath10k_ce_pipe *ce_state,
869 void (*recv_cb)(struct ath10k_ce_pipe *))
871 struct ath10k *ar = ce_state->ar;
872 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
874 spin_lock_bh(&ar_pci->ce_lock);
875 ce_state->recv_cb = recv_cb;
876 ath10k_ce_per_engine_handler_adjust(ce_state, 0);
877 spin_unlock_bh(&ar_pci->ce_lock);
880 static int ath10k_ce_init_src_ring(struct ath10k *ar,
882 struct ath10k_ce_pipe *ce_state,
883 const struct ce_attr *attr)
885 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
886 struct ath10k_ce_ring *src_ring;
887 unsigned int nentries = attr->src_nentries;
888 unsigned int ce_nbytes;
889 u32 ctrl_addr = ath10k_ce_base_address(ce_id);
890 dma_addr_t base_addr;
893 nentries = roundup_pow_of_two(nentries);
895 if (ce_state->src_ring) {
896 WARN_ON(ce_state->src_ring->nentries != nentries);
900 ce_nbytes = sizeof(struct ath10k_ce_ring) + (nentries * sizeof(void *));
901 ptr = kzalloc(ce_nbytes, GFP_KERNEL);
905 ce_state->src_ring = (struct ath10k_ce_ring *)ptr;
906 src_ring = ce_state->src_ring;
908 ptr += sizeof(struct ath10k_ce_ring);
909 src_ring->nentries = nentries;
910 src_ring->nentries_mask = nentries - 1;
912 src_ring->sw_index = ath10k_ce_src_ring_read_index_get(ar, ctrl_addr);
913 src_ring->sw_index &= src_ring->nentries_mask;
914 src_ring->hw_index = src_ring->sw_index;
916 src_ring->write_index =
917 ath10k_ce_src_ring_write_index_get(ar, ctrl_addr);
918 src_ring->write_index &= src_ring->nentries_mask;
920 src_ring->per_transfer_context = (void **)ptr;
923 * Legacy platforms that do not support cache
924 * coherent DMA are unsupported
926 src_ring->base_addr_owner_space_unaligned =
927 pci_alloc_consistent(ar_pci->pdev,
928 (nentries * sizeof(struct ce_desc) +
931 if (!src_ring->base_addr_owner_space_unaligned) {
932 kfree(ce_state->src_ring);
933 ce_state->src_ring = NULL;
937 src_ring->base_addr_ce_space_unaligned = base_addr;
939 src_ring->base_addr_owner_space = PTR_ALIGN(
940 src_ring->base_addr_owner_space_unaligned,
942 src_ring->base_addr_ce_space = ALIGN(
943 src_ring->base_addr_ce_space_unaligned,
947 * Also allocate a shadow src ring in regular
948 * mem to use for faster access.
950 src_ring->shadow_base_unaligned =
951 kmalloc((nentries * sizeof(struct ce_desc) +
952 CE_DESC_RING_ALIGN), GFP_KERNEL);
953 if (!src_ring->shadow_base_unaligned) {
954 pci_free_consistent(ar_pci->pdev,
955 (nentries * sizeof(struct ce_desc) +
957 src_ring->base_addr_owner_space,
958 src_ring->base_addr_ce_space);
959 kfree(ce_state->src_ring);
960 ce_state->src_ring = NULL;
964 src_ring->shadow_base = PTR_ALIGN(
965 src_ring->shadow_base_unaligned,
968 ath10k_ce_src_ring_base_addr_set(ar, ctrl_addr,
969 src_ring->base_addr_ce_space);
970 ath10k_ce_src_ring_size_set(ar, ctrl_addr, nentries);
971 ath10k_ce_src_ring_dmax_set(ar, ctrl_addr, attr->src_sz_max);
972 ath10k_ce_src_ring_byte_swap_set(ar, ctrl_addr, 0);
973 ath10k_ce_src_ring_lowmark_set(ar, ctrl_addr, 0);
974 ath10k_ce_src_ring_highmark_set(ar, ctrl_addr, nentries);
976 ath10k_dbg(ATH10K_DBG_BOOT,
977 "boot ce src ring id %d entries %d base_addr %p\n",
978 ce_id, nentries, src_ring->base_addr_owner_space);
983 static int ath10k_ce_init_dest_ring(struct ath10k *ar,
985 struct ath10k_ce_pipe *ce_state,
986 const struct ce_attr *attr)
988 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
989 struct ath10k_ce_ring *dest_ring;
990 unsigned int nentries = attr->dest_nentries;
991 unsigned int ce_nbytes;
992 u32 ctrl_addr = ath10k_ce_base_address(ce_id);
993 dma_addr_t base_addr;
996 nentries = roundup_pow_of_two(nentries);
998 if (ce_state->dest_ring) {
999 WARN_ON(ce_state->dest_ring->nentries != nentries);
1003 ce_nbytes = sizeof(struct ath10k_ce_ring) + (nentries * sizeof(void *));
1004 ptr = kzalloc(ce_nbytes, GFP_KERNEL);
1008 ce_state->dest_ring = (struct ath10k_ce_ring *)ptr;
1009 dest_ring = ce_state->dest_ring;
1011 ptr += sizeof(struct ath10k_ce_ring);
1012 dest_ring->nentries = nentries;
1013 dest_ring->nentries_mask = nentries - 1;
1015 dest_ring->sw_index = ath10k_ce_dest_ring_read_index_get(ar, ctrl_addr);
1016 dest_ring->sw_index &= dest_ring->nentries_mask;
1017 dest_ring->write_index =
1018 ath10k_ce_dest_ring_write_index_get(ar, ctrl_addr);
1019 dest_ring->write_index &= dest_ring->nentries_mask;
1021 dest_ring->per_transfer_context = (void **)ptr;
1024 * Legacy platforms that do not support cache
1025 * coherent DMA are unsupported
1027 dest_ring->base_addr_owner_space_unaligned =
1028 pci_alloc_consistent(ar_pci->pdev,
1029 (nentries * sizeof(struct ce_desc) +
1030 CE_DESC_RING_ALIGN),
1032 if (!dest_ring->base_addr_owner_space_unaligned) {
1033 kfree(ce_state->dest_ring);
1034 ce_state->dest_ring = NULL;
1038 dest_ring->base_addr_ce_space_unaligned = base_addr;
1041 * Correctly initialize memory to 0 to prevent garbage
1042 * data crashing system when download firmware
1044 memset(dest_ring->base_addr_owner_space_unaligned, 0,
1045 nentries * sizeof(struct ce_desc) + CE_DESC_RING_ALIGN);
1047 dest_ring->base_addr_owner_space = PTR_ALIGN(
1048 dest_ring->base_addr_owner_space_unaligned,
1049 CE_DESC_RING_ALIGN);
1050 dest_ring->base_addr_ce_space = ALIGN(
1051 dest_ring->base_addr_ce_space_unaligned,
1052 CE_DESC_RING_ALIGN);
1054 ath10k_ce_dest_ring_base_addr_set(ar, ctrl_addr,
1055 dest_ring->base_addr_ce_space);
1056 ath10k_ce_dest_ring_size_set(ar, ctrl_addr, nentries);
1057 ath10k_ce_dest_ring_byte_swap_set(ar, ctrl_addr, 0);
1058 ath10k_ce_dest_ring_lowmark_set(ar, ctrl_addr, 0);
1059 ath10k_ce_dest_ring_highmark_set(ar, ctrl_addr, nentries);
1061 ath10k_dbg(ATH10K_DBG_BOOT,
1062 "boot ce dest ring id %d entries %d base_addr %p\n",
1063 ce_id, nentries, dest_ring->base_addr_owner_space);
1068 static struct ath10k_ce_pipe *ath10k_ce_init_state(struct ath10k *ar,
1070 const struct ce_attr *attr)
1072 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1073 struct ath10k_ce_pipe *ce_state = &ar_pci->ce_states[ce_id];
1074 u32 ctrl_addr = ath10k_ce_base_address(ce_id);
1076 spin_lock_bh(&ar_pci->ce_lock);
1079 ce_state->id = ce_id;
1080 ce_state->ctrl_addr = ctrl_addr;
1081 ce_state->attr_flags = attr->flags;
1082 ce_state->src_sz_max = attr->src_sz_max;
1084 spin_unlock_bh(&ar_pci->ce_lock);
1090 * Initialize a Copy Engine based on caller-supplied attributes.
1091 * This may be called once to initialize both source and destination
1092 * rings or it may be called twice for separate source and destination
1093 * initialization. It may be that only one side or the other is
1094 * initialized by software/firmware.
1096 struct ath10k_ce_pipe *ath10k_ce_init(struct ath10k *ar,
1098 const struct ce_attr *attr)
1100 struct ath10k_ce_pipe *ce_state;
1101 u32 ctrl_addr = ath10k_ce_base_address(ce_id);
1104 ret = ath10k_pci_wake(ar);
1108 ce_state = ath10k_ce_init_state(ar, ce_id, attr);
1110 ath10k_err("Failed to initialize CE state for ID: %d\n", ce_id);
1114 if (attr->src_nentries) {
1115 ret = ath10k_ce_init_src_ring(ar, ce_id, ce_state, attr);
1117 ath10k_err("Failed to initialize CE src ring for ID: %d (%d)\n",
1119 ath10k_ce_deinit(ce_state);
1124 if (attr->dest_nentries) {
1125 ret = ath10k_ce_init_dest_ring(ar, ce_id, ce_state, attr);
1127 ath10k_err("Failed to initialize CE dest ring for ID: %d (%d)\n",
1129 ath10k_ce_deinit(ce_state);
1134 /* Enable CE error interrupts */
1135 ath10k_ce_error_intr_enable(ar, ctrl_addr);
1137 ath10k_pci_sleep(ar);
1142 void ath10k_ce_deinit(struct ath10k_ce_pipe *ce_state)
1144 struct ath10k *ar = ce_state->ar;
1145 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1147 if (ce_state->src_ring) {
1148 kfree(ce_state->src_ring->shadow_base_unaligned);
1149 pci_free_consistent(ar_pci->pdev,
1150 (ce_state->src_ring->nentries *
1151 sizeof(struct ce_desc) +
1152 CE_DESC_RING_ALIGN),
1153 ce_state->src_ring->base_addr_owner_space,
1154 ce_state->src_ring->base_addr_ce_space);
1155 kfree(ce_state->src_ring);
1158 if (ce_state->dest_ring) {
1159 pci_free_consistent(ar_pci->pdev,
1160 (ce_state->dest_ring->nentries *
1161 sizeof(struct ce_desc) +
1162 CE_DESC_RING_ALIGN),
1163 ce_state->dest_ring->base_addr_owner_space,
1164 ce_state->dest_ring->base_addr_ce_space);
1165 kfree(ce_state->dest_ring);
1168 ce_state->src_ring = NULL;
1169 ce_state->dest_ring = NULL;