2 * Copyright (c) 2005-2011 Atheros Communications Inc.
3 * Copyright (c) 2011-2013 Qualcomm Atheros, Inc.
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
21 #include <linux/bug.h>
22 #include <linux/interrupt.h>
23 #include <linux/dmapool.h>
24 #include <linux/hashtable.h>
25 #include <net/mac80211.h>
32 enum htt_dbg_stats_type {
33 HTT_DBG_STATS_WAL_PDEV_TXRX = 1 << 0,
34 HTT_DBG_STATS_RX_REORDER = 1 << 1,
35 HTT_DBG_STATS_RX_RATE_INFO = 1 << 2,
36 HTT_DBG_STATS_TX_PPDU_LOG = 1 << 3,
37 HTT_DBG_STATS_TX_RATE_INFO = 1 << 4,
38 /* bits 5-23 currently reserved */
40 HTT_DBG_NUM_STATS /* keep this last */
43 enum htt_h2t_msg_type { /* host-to-target */
44 HTT_H2T_MSG_TYPE_VERSION_REQ = 0,
45 HTT_H2T_MSG_TYPE_TX_FRM = 1,
46 HTT_H2T_MSG_TYPE_RX_RING_CFG = 2,
47 HTT_H2T_MSG_TYPE_STATS_REQ = 3,
48 HTT_H2T_MSG_TYPE_SYNC = 4,
49 HTT_H2T_MSG_TYPE_AGGR_CFG = 5,
50 HTT_H2T_MSG_TYPE_FRAG_DESC_BANK_CFG = 6,
52 /* This command is used for sending management frames in HTT < 3.0.
53 * HTT >= 3.0 uses TX_FRM for everything. */
54 HTT_H2T_MSG_TYPE_MGMT_TX = 7,
56 HTT_H2T_NUM_MSGS /* keep this last */
64 u8 pad[sizeof(u32) - sizeof(struct htt_cmd_hdr)];
68 * HTT tx MSDU descriptor
70 * The HTT tx MSDU descriptor is created by the host HTT SW for each
71 * tx MSDU. The HTT tx MSDU descriptor contains the information that
72 * the target firmware needs for the FW's tx processing, particularly
73 * for creating the HW msdu descriptor.
74 * The same HTT tx descriptor is used for HL and LL systems, though
75 * a few fields within the tx descriptor are used only by LL or
77 * The HTT tx descriptor is defined in two manners: by a struct with
78 * bitfields, and by a series of [dword offset, bit mask, bit shift]
80 * The target should use the struct def, for simplicitly and clarity,
81 * but the host shall use the bit-mast + bit-shift defs, to be endian-
82 * neutral. Specifically, the host shall use the get/set macros built
83 * around the mask + shift defs.
85 struct htt_data_tx_desc_frag {
87 struct double_word_addr {
90 } __packed dword_addr;
91 struct triple_word_addr {
95 } __packed tword_addr;
99 struct htt_msdu_ext_desc {
101 __le16 ip_identification;
104 struct htt_data_tx_desc_frag frags[6];
107 #define HTT_MSDU_EXT_DESC_FLAG_IPV4_CSUM_ENABLE BIT(0)
108 #define HTT_MSDU_EXT_DESC_FLAG_UDP_IPV4_CSUM_ENABLE BIT(1)
109 #define HTT_MSDU_EXT_DESC_FLAG_UDP_IPV6_CSUM_ENABLE BIT(2)
110 #define HTT_MSDU_EXT_DESC_FLAG_TCP_IPV4_CSUM_ENABLE BIT(3)
111 #define HTT_MSDU_EXT_DESC_FLAG_TCP_IPV6_CSUM_ENABLE BIT(4)
113 #define HTT_MSDU_CHECKSUM_ENABLE (HTT_MSDU_EXT_DESC_FLAG_IPV4_CSUM_ENABLE \
114 | HTT_MSDU_EXT_DESC_FLAG_UDP_IPV4_CSUM_ENABLE \
115 | HTT_MSDU_EXT_DESC_FLAG_UDP_IPV6_CSUM_ENABLE \
116 | HTT_MSDU_EXT_DESC_FLAG_TCP_IPV4_CSUM_ENABLE \
117 | HTT_MSDU_EXT_DESC_FLAG_TCP_IPV6_CSUM_ENABLE)
119 enum htt_data_tx_desc_flags0 {
120 HTT_DATA_TX_DESC_FLAGS0_MAC_HDR_PRESENT = 1 << 0,
121 HTT_DATA_TX_DESC_FLAGS0_NO_AGGR = 1 << 1,
122 HTT_DATA_TX_DESC_FLAGS0_NO_ENCRYPT = 1 << 2,
123 HTT_DATA_TX_DESC_FLAGS0_NO_CLASSIFY = 1 << 3,
124 HTT_DATA_TX_DESC_FLAGS0_RSVD0 = 1 << 4
125 #define HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE_MASK 0xE0
126 #define HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE_LSB 5
129 enum htt_data_tx_desc_flags1 {
130 #define HTT_DATA_TX_DESC_FLAGS1_VDEV_ID_BITS 6
131 #define HTT_DATA_TX_DESC_FLAGS1_VDEV_ID_MASK 0x003F
132 #define HTT_DATA_TX_DESC_FLAGS1_VDEV_ID_LSB 0
133 #define HTT_DATA_TX_DESC_FLAGS1_EXT_TID_BITS 5
134 #define HTT_DATA_TX_DESC_FLAGS1_EXT_TID_MASK 0x07C0
135 #define HTT_DATA_TX_DESC_FLAGS1_EXT_TID_LSB 6
136 HTT_DATA_TX_DESC_FLAGS1_POSTPONED = 1 << 11,
137 HTT_DATA_TX_DESC_FLAGS1_MORE_IN_BATCH = 1 << 12,
138 HTT_DATA_TX_DESC_FLAGS1_CKSUM_L3_OFFLOAD = 1 << 13,
139 HTT_DATA_TX_DESC_FLAGS1_CKSUM_L4_OFFLOAD = 1 << 14,
140 HTT_DATA_TX_DESC_FLAGS1_RSVD1 = 1 << 15
143 enum htt_data_tx_ext_tid {
144 HTT_DATA_TX_EXT_TID_NON_QOS_MCAST_BCAST = 16,
145 HTT_DATA_TX_EXT_TID_MGMT = 17,
146 HTT_DATA_TX_EXT_TID_INVALID = 31
149 #define HTT_INVALID_PEERID 0xFFFF
152 * htt_data_tx_desc - used for data tx path
154 * Note: vdev_id irrelevant for pkt_type == raw and no_classify == 1.
155 * ext_tid: for qos-data frames (0-15), see %HTT_DATA_TX_EXT_TID_
156 * for special kinds of tids
157 * postponed: only for HL hosts. indicates if this is a resend
158 * (HL hosts manage queues on the host )
159 * more_in_batch: only for HL hosts. indicates if more packets are
160 * pending. this allows target to wait and aggregate
161 * freq: 0 means home channel of given vdev. intended for offchannel
163 struct htt_data_tx_desc {
164 u8 flags0; /* %HTT_DATA_TX_DESC_FLAGS0_ */
165 __le16 flags1; /* %HTT_DATA_TX_DESC_FLAGS1_ */
174 } __packed offchan_tx;
176 u8 prefetch[0]; /* start of frame, for FW classification engine */
179 enum htt_rx_ring_flags {
180 HTT_RX_RING_FLAGS_MAC80211_HDR = 1 << 0,
181 HTT_RX_RING_FLAGS_MSDU_PAYLOAD = 1 << 1,
182 HTT_RX_RING_FLAGS_PPDU_START = 1 << 2,
183 HTT_RX_RING_FLAGS_PPDU_END = 1 << 3,
184 HTT_RX_RING_FLAGS_MPDU_START = 1 << 4,
185 HTT_RX_RING_FLAGS_MPDU_END = 1 << 5,
186 HTT_RX_RING_FLAGS_MSDU_START = 1 << 6,
187 HTT_RX_RING_FLAGS_MSDU_END = 1 << 7,
188 HTT_RX_RING_FLAGS_RX_ATTENTION = 1 << 8,
189 HTT_RX_RING_FLAGS_FRAG_INFO = 1 << 9,
190 HTT_RX_RING_FLAGS_UNICAST_RX = 1 << 10,
191 HTT_RX_RING_FLAGS_MULTICAST_RX = 1 << 11,
192 HTT_RX_RING_FLAGS_CTRL_RX = 1 << 12,
193 HTT_RX_RING_FLAGS_MGMT_RX = 1 << 13,
194 HTT_RX_RING_FLAGS_NULL_RX = 1 << 14,
195 HTT_RX_RING_FLAGS_PHY_DATA_RX = 1 << 15
198 #define HTT_RX_RING_SIZE_MIN 128
199 #define HTT_RX_RING_SIZE_MAX 2048
201 struct htt_rx_ring_setup_ring {
202 __le32 fw_idx_shadow_reg_paddr;
203 __le32 rx_ring_base_paddr;
204 __le16 rx_ring_len; /* in 4-byte words */
205 __le16 rx_ring_bufsize; /* rx skb size - in bytes */
206 __le16 flags; /* %HTT_RX_RING_FLAGS_ */
207 __le16 fw_idx_init_val;
209 /* the following offsets are in 4-byte units */
210 __le16 mac80211_hdr_offset;
211 __le16 msdu_payload_offset;
212 __le16 ppdu_start_offset;
213 __le16 ppdu_end_offset;
214 __le16 mpdu_start_offset;
215 __le16 mpdu_end_offset;
216 __le16 msdu_start_offset;
217 __le16 msdu_end_offset;
218 __le16 rx_attention_offset;
219 __le16 frag_info_offset;
222 struct htt_rx_ring_setup_hdr {
223 u8 num_rings; /* supported values: 1, 2 */
227 struct htt_rx_ring_setup {
228 struct htt_rx_ring_setup_hdr hdr;
229 struct htt_rx_ring_setup_ring rings[0];
233 * htt_stats_req - request target to send specified statistics
235 * @msg_type: hardcoded %HTT_H2T_MSG_TYPE_STATS_REQ
236 * @upload_types: see %htt_dbg_stats_type. this is 24bit field actually
237 * so make sure its little-endian.
238 * @reset_types: see %htt_dbg_stats_type. this is 24bit field actually
239 * so make sure its little-endian.
240 * @cfg_val: stat_type specific configuration
241 * @stat_type: see %htt_dbg_stats_type
242 * @cookie_lsb: used for confirmation message from target->host
243 * @cookie_msb: ditto as %cookie
245 struct htt_stats_req {
259 #define HTT_STATS_REQ_CFG_STAT_TYPE_INVALID 0xff
262 * htt_oob_sync_req - request out-of-band sync
264 * The HTT SYNC tells the target to suspend processing of subsequent
265 * HTT host-to-target messages until some other target agent locally
266 * informs the target HTT FW that the current sync counter is equal to
267 * or greater than (in a modulo sense) the sync counter specified in
270 * This allows other host-target components to synchronize their operation
271 * with HTT, e.g. to ensure that tx frames don't get transmitted until a
272 * security key has been downloaded to and activated by the target.
273 * In the absence of any explicit synchronization counter value
274 * specification, the target HTT FW will use zero as the default current
277 * The HTT target FW will suspend its host->target message processing as long
278 * as 0 < (in-band sync counter - out-of-band sync counter) & 0xff < 128.
280 struct htt_oob_sync_req {
285 struct htt_aggr_conf {
286 u8 max_num_ampdu_subframes;
287 /* amsdu_subframes is limited by 0x1F mask */
288 u8 max_num_amsdu_subframes;
291 #define HTT_MGMT_FRM_HDR_DOWNLOAD_LEN 32
292 struct htt_mgmt_tx_desc_qca99x0 {
296 struct htt_mgmt_tx_desc {
297 u8 pad[sizeof(u32) - sizeof(struct htt_cmd_hdr)];
302 u8 hdr[HTT_MGMT_FRM_HDR_DOWNLOAD_LEN];
304 struct htt_mgmt_tx_desc_qca99x0 qca99x0;
308 enum htt_mgmt_tx_status {
309 HTT_MGMT_TX_STATUS_OK = 0,
310 HTT_MGMT_TX_STATUS_RETRY = 1,
311 HTT_MGMT_TX_STATUS_DROP = 2
314 /*=== target -> host messages ===============================================*/
316 enum htt_main_t2h_msg_type {
317 HTT_MAIN_T2H_MSG_TYPE_VERSION_CONF = 0x0,
318 HTT_MAIN_T2H_MSG_TYPE_RX_IND = 0x1,
319 HTT_MAIN_T2H_MSG_TYPE_RX_FLUSH = 0x2,
320 HTT_MAIN_T2H_MSG_TYPE_PEER_MAP = 0x3,
321 HTT_MAIN_T2H_MSG_TYPE_PEER_UNMAP = 0x4,
322 HTT_MAIN_T2H_MSG_TYPE_RX_ADDBA = 0x5,
323 HTT_MAIN_T2H_MSG_TYPE_RX_DELBA = 0x6,
324 HTT_MAIN_T2H_MSG_TYPE_TX_COMPL_IND = 0x7,
325 HTT_MAIN_T2H_MSG_TYPE_PKTLOG = 0x8,
326 HTT_MAIN_T2H_MSG_TYPE_STATS_CONF = 0x9,
327 HTT_MAIN_T2H_MSG_TYPE_RX_FRAG_IND = 0xa,
328 HTT_MAIN_T2H_MSG_TYPE_SEC_IND = 0xb,
329 HTT_MAIN_T2H_MSG_TYPE_TX_INSPECT_IND = 0xd,
330 HTT_MAIN_T2H_MSG_TYPE_MGMT_TX_COMPL_IND = 0xe,
331 HTT_MAIN_T2H_MSG_TYPE_TX_CREDIT_UPDATE_IND = 0xf,
332 HTT_MAIN_T2H_MSG_TYPE_RX_PN_IND = 0x10,
333 HTT_MAIN_T2H_MSG_TYPE_RX_OFFLOAD_DELIVER_IND = 0x11,
334 HTT_MAIN_T2H_MSG_TYPE_TEST,
336 HTT_MAIN_T2H_NUM_MSGS
339 enum htt_10x_t2h_msg_type {
340 HTT_10X_T2H_MSG_TYPE_VERSION_CONF = 0x0,
341 HTT_10X_T2H_MSG_TYPE_RX_IND = 0x1,
342 HTT_10X_T2H_MSG_TYPE_RX_FLUSH = 0x2,
343 HTT_10X_T2H_MSG_TYPE_PEER_MAP = 0x3,
344 HTT_10X_T2H_MSG_TYPE_PEER_UNMAP = 0x4,
345 HTT_10X_T2H_MSG_TYPE_RX_ADDBA = 0x5,
346 HTT_10X_T2H_MSG_TYPE_RX_DELBA = 0x6,
347 HTT_10X_T2H_MSG_TYPE_TX_COMPL_IND = 0x7,
348 HTT_10X_T2H_MSG_TYPE_PKTLOG = 0x8,
349 HTT_10X_T2H_MSG_TYPE_STATS_CONF = 0x9,
350 HTT_10X_T2H_MSG_TYPE_RX_FRAG_IND = 0xa,
351 HTT_10X_T2H_MSG_TYPE_SEC_IND = 0xb,
352 HTT_10X_T2H_MSG_TYPE_RC_UPDATE_IND = 0xc,
353 HTT_10X_T2H_MSG_TYPE_TX_INSPECT_IND = 0xd,
354 HTT_10X_T2H_MSG_TYPE_TEST = 0xe,
355 HTT_10X_T2H_MSG_TYPE_CHAN_CHANGE = 0xf,
356 HTT_10X_T2H_MSG_TYPE_AGGR_CONF = 0x11,
357 HTT_10X_T2H_MSG_TYPE_STATS_NOUPLOAD = 0x12,
358 HTT_10X_T2H_MSG_TYPE_MGMT_TX_COMPL_IND = 0x13,
363 enum htt_tlv_t2h_msg_type {
364 HTT_TLV_T2H_MSG_TYPE_VERSION_CONF = 0x0,
365 HTT_TLV_T2H_MSG_TYPE_RX_IND = 0x1,
366 HTT_TLV_T2H_MSG_TYPE_RX_FLUSH = 0x2,
367 HTT_TLV_T2H_MSG_TYPE_PEER_MAP = 0x3,
368 HTT_TLV_T2H_MSG_TYPE_PEER_UNMAP = 0x4,
369 HTT_TLV_T2H_MSG_TYPE_RX_ADDBA = 0x5,
370 HTT_TLV_T2H_MSG_TYPE_RX_DELBA = 0x6,
371 HTT_TLV_T2H_MSG_TYPE_TX_COMPL_IND = 0x7,
372 HTT_TLV_T2H_MSG_TYPE_PKTLOG = 0x8,
373 HTT_TLV_T2H_MSG_TYPE_STATS_CONF = 0x9,
374 HTT_TLV_T2H_MSG_TYPE_RX_FRAG_IND = 0xa,
375 HTT_TLV_T2H_MSG_TYPE_SEC_IND = 0xb,
376 HTT_TLV_T2H_MSG_TYPE_RC_UPDATE_IND = 0xc, /* deprecated */
377 HTT_TLV_T2H_MSG_TYPE_TX_INSPECT_IND = 0xd,
378 HTT_TLV_T2H_MSG_TYPE_MGMT_TX_COMPL_IND = 0xe,
379 HTT_TLV_T2H_MSG_TYPE_TX_CREDIT_UPDATE_IND = 0xf,
380 HTT_TLV_T2H_MSG_TYPE_RX_PN_IND = 0x10,
381 HTT_TLV_T2H_MSG_TYPE_RX_OFFLOAD_DELIVER_IND = 0x11,
382 HTT_TLV_T2H_MSG_TYPE_RX_IN_ORD_PADDR_IND = 0x12,
384 HTT_TLV_T2H_MSG_TYPE_WDI_IPA_OP_RESPONSE = 0x14,
385 HTT_TLV_T2H_MSG_TYPE_CHAN_CHANGE = 0x15,
386 HTT_TLV_T2H_MSG_TYPE_RX_OFLD_PKT_ERR = 0x16,
387 HTT_TLV_T2H_MSG_TYPE_TEST,
392 enum htt_10_4_t2h_msg_type {
393 HTT_10_4_T2H_MSG_TYPE_VERSION_CONF = 0x0,
394 HTT_10_4_T2H_MSG_TYPE_RX_IND = 0x1,
395 HTT_10_4_T2H_MSG_TYPE_RX_FLUSH = 0x2,
396 HTT_10_4_T2H_MSG_TYPE_PEER_MAP = 0x3,
397 HTT_10_4_T2H_MSG_TYPE_PEER_UNMAP = 0x4,
398 HTT_10_4_T2H_MSG_TYPE_RX_ADDBA = 0x5,
399 HTT_10_4_T2H_MSG_TYPE_RX_DELBA = 0x6,
400 HTT_10_4_T2H_MSG_TYPE_TX_COMPL_IND = 0x7,
401 HTT_10_4_T2H_MSG_TYPE_PKTLOG = 0x8,
402 HTT_10_4_T2H_MSG_TYPE_STATS_CONF = 0x9,
403 HTT_10_4_T2H_MSG_TYPE_RX_FRAG_IND = 0xa,
404 HTT_10_4_T2H_MSG_TYPE_SEC_IND = 0xb,
405 HTT_10_4_T2H_MSG_TYPE_RC_UPDATE_IND = 0xc,
406 HTT_10_4_T2H_MSG_TYPE_TX_INSPECT_IND = 0xd,
407 HTT_10_4_T2H_MSG_TYPE_MGMT_TX_COMPL_IND = 0xe,
408 HTT_10_4_T2H_MSG_TYPE_CHAN_CHANGE = 0xf,
409 HTT_10_4_T2H_MSG_TYPE_TX_CREDIT_UPDATE_IND = 0x10,
410 HTT_10_4_T2H_MSG_TYPE_RX_PN_IND = 0x11,
411 HTT_10_4_T2H_MSG_TYPE_RX_OFFLOAD_DELIVER_IND = 0x12,
412 HTT_10_4_T2H_MSG_TYPE_TEST = 0x13,
413 HTT_10_4_T2H_MSG_TYPE_EN_STATS = 0x14,
414 HTT_10_4_T2H_MSG_TYPE_AGGR_CONF = 0x15,
415 HTT_10_4_T2H_MSG_TYPE_TX_FETCH_IND = 0x16,
416 HTT_10_4_T2H_MSG_TYPE_TX_FETCH_CONFIRM = 0x17,
417 HTT_10_4_T2H_MSG_TYPE_STATS_NOUPLOAD = 0x18,
418 /* 0x19 to 0x2f are reserved */
419 HTT_10_4_T2H_MSG_TYPE_TX_MODE_SWITCH_IND = 0x30,
421 HTT_10_4_T2H_NUM_MSGS
424 enum htt_t2h_msg_type {
425 HTT_T2H_MSG_TYPE_VERSION_CONF,
426 HTT_T2H_MSG_TYPE_RX_IND,
427 HTT_T2H_MSG_TYPE_RX_FLUSH,
428 HTT_T2H_MSG_TYPE_PEER_MAP,
429 HTT_T2H_MSG_TYPE_PEER_UNMAP,
430 HTT_T2H_MSG_TYPE_RX_ADDBA,
431 HTT_T2H_MSG_TYPE_RX_DELBA,
432 HTT_T2H_MSG_TYPE_TX_COMPL_IND,
433 HTT_T2H_MSG_TYPE_PKTLOG,
434 HTT_T2H_MSG_TYPE_STATS_CONF,
435 HTT_T2H_MSG_TYPE_RX_FRAG_IND,
436 HTT_T2H_MSG_TYPE_SEC_IND,
437 HTT_T2H_MSG_TYPE_RC_UPDATE_IND,
438 HTT_T2H_MSG_TYPE_TX_INSPECT_IND,
439 HTT_T2H_MSG_TYPE_MGMT_TX_COMPLETION,
440 HTT_T2H_MSG_TYPE_TX_CREDIT_UPDATE_IND,
441 HTT_T2H_MSG_TYPE_RX_PN_IND,
442 HTT_T2H_MSG_TYPE_RX_OFFLOAD_DELIVER_IND,
443 HTT_T2H_MSG_TYPE_RX_IN_ORD_PADDR_IND,
444 HTT_T2H_MSG_TYPE_WDI_IPA_OP_RESPONSE,
445 HTT_T2H_MSG_TYPE_CHAN_CHANGE,
446 HTT_T2H_MSG_TYPE_RX_OFLD_PKT_ERR,
447 HTT_T2H_MSG_TYPE_AGGR_CONF,
448 HTT_T2H_MSG_TYPE_STATS_NOUPLOAD,
449 HTT_T2H_MSG_TYPE_TEST,
450 HTT_T2H_MSG_TYPE_EN_STATS,
451 HTT_T2H_MSG_TYPE_TX_FETCH_IND,
452 HTT_T2H_MSG_TYPE_TX_FETCH_CONFIRM,
453 HTT_T2H_MSG_TYPE_TX_MODE_SWITCH_IND,
459 * htt_resp_hdr - header for target-to-host messages
461 * msg_type: see htt_t2h_msg_type
463 struct htt_resp_hdr {
467 #define HTT_RESP_HDR_MSG_TYPE_OFFSET 0
468 #define HTT_RESP_HDR_MSG_TYPE_MASK 0xff
469 #define HTT_RESP_HDR_MSG_TYPE_LSB 0
471 /* htt_ver_resp - response sent for htt_ver_req */
472 struct htt_ver_resp {
478 struct htt_mgmt_tx_completion {
486 #define HTT_RX_INDICATION_INFO0_EXT_TID_MASK (0x3F)
487 #define HTT_RX_INDICATION_INFO0_EXT_TID_LSB (0)
488 #define HTT_RX_INDICATION_INFO0_FLUSH_VALID (1 << 6)
489 #define HTT_RX_INDICATION_INFO0_RELEASE_VALID (1 << 7)
491 #define HTT_RX_INDICATION_INFO1_FLUSH_START_SEQNO_MASK 0x0000003F
492 #define HTT_RX_INDICATION_INFO1_FLUSH_START_SEQNO_LSB 0
493 #define HTT_RX_INDICATION_INFO1_FLUSH_END_SEQNO_MASK 0x00000FC0
494 #define HTT_RX_INDICATION_INFO1_FLUSH_END_SEQNO_LSB 6
495 #define HTT_RX_INDICATION_INFO1_RELEASE_START_SEQNO_MASK 0x0003F000
496 #define HTT_RX_INDICATION_INFO1_RELEASE_START_SEQNO_LSB 12
497 #define HTT_RX_INDICATION_INFO1_RELEASE_END_SEQNO_MASK 0x00FC0000
498 #define HTT_RX_INDICATION_INFO1_RELEASE_END_SEQNO_LSB 18
499 #define HTT_RX_INDICATION_INFO1_NUM_MPDU_RANGES_MASK 0xFF000000
500 #define HTT_RX_INDICATION_INFO1_NUM_MPDU_RANGES_LSB 24
502 struct htt_rx_indication_hdr {
503 u8 info0; /* %HTT_RX_INDICATION_INFO0_ */
505 __le32 info1; /* %HTT_RX_INDICATION_INFO1_ */
508 #define HTT_RX_INDICATION_INFO0_PHY_ERR_VALID (1 << 0)
509 #define HTT_RX_INDICATION_INFO0_LEGACY_RATE_MASK (0x1E)
510 #define HTT_RX_INDICATION_INFO0_LEGACY_RATE_LSB (1)
511 #define HTT_RX_INDICATION_INFO0_LEGACY_RATE_CCK (1 << 5)
512 #define HTT_RX_INDICATION_INFO0_END_VALID (1 << 6)
513 #define HTT_RX_INDICATION_INFO0_START_VALID (1 << 7)
515 #define HTT_RX_INDICATION_INFO1_VHT_SIG_A1_MASK 0x00FFFFFF
516 #define HTT_RX_INDICATION_INFO1_VHT_SIG_A1_LSB 0
517 #define HTT_RX_INDICATION_INFO1_PREAMBLE_TYPE_MASK 0xFF000000
518 #define HTT_RX_INDICATION_INFO1_PREAMBLE_TYPE_LSB 24
520 #define HTT_RX_INDICATION_INFO2_VHT_SIG_A1_MASK 0x00FFFFFF
521 #define HTT_RX_INDICATION_INFO2_VHT_SIG_A1_LSB 0
522 #define HTT_RX_INDICATION_INFO2_SERVICE_MASK 0xFF000000
523 #define HTT_RX_INDICATION_INFO2_SERVICE_LSB 24
525 enum htt_rx_legacy_rate {
536 HTT_RX_CCK_11_LP = 0,
537 HTT_RX_CCK_5_5_LP = 1,
546 enum htt_rx_legacy_rate_type {
547 HTT_RX_LEGACY_RATE_OFDM = 0,
548 HTT_RX_LEGACY_RATE_CCK
551 enum htt_rx_preamble_type {
554 HTT_RX_HT_WITH_TXBF = 0x9,
556 HTT_RX_VHT_WITH_TXBF = 0xD,
560 * Fields: phy_err_valid, phy_err_code, tsf,
561 * usec_timestamp, sub_usec_timestamp
562 * ..are valid only if end_valid == 1.
564 * Fields: rssi_chains, legacy_rate_type,
565 * legacy_rate_cck, preamble_type, service,
567 * ..are valid only if start_valid == 1;
569 struct htt_rx_indication_ppdu {
571 u8 sub_usec_timestamp;
573 u8 info0; /* HTT_RX_INDICATION_INFO0_ */
579 } __packed rssi_chains[4];
581 __le32 usec_timestamp;
582 __le32 info1; /* HTT_RX_INDICATION_INFO1_ */
583 __le32 info2; /* HTT_RX_INDICATION_INFO2_ */
586 enum htt_rx_mpdu_status {
587 HTT_RX_IND_MPDU_STATUS_UNKNOWN = 0x0,
588 HTT_RX_IND_MPDU_STATUS_OK,
589 HTT_RX_IND_MPDU_STATUS_ERR_FCS,
590 HTT_RX_IND_MPDU_STATUS_ERR_DUP,
591 HTT_RX_IND_MPDU_STATUS_ERR_REPLAY,
592 HTT_RX_IND_MPDU_STATUS_ERR_INV_PEER,
593 /* only accept EAPOL frames */
594 HTT_RX_IND_MPDU_STATUS_UNAUTH_PEER,
595 HTT_RX_IND_MPDU_STATUS_OUT_OF_SYNC,
596 /* Non-data in promiscous mode */
597 HTT_RX_IND_MPDU_STATUS_MGMT_CTRL,
598 HTT_RX_IND_MPDU_STATUS_TKIP_MIC_ERR,
599 HTT_RX_IND_MPDU_STATUS_DECRYPT_ERR,
600 HTT_RX_IND_MPDU_STATUS_MPDU_LENGTH_ERR,
601 HTT_RX_IND_MPDU_STATUS_ENCRYPT_REQUIRED_ERR,
602 HTT_RX_IND_MPDU_STATUS_PRIVACY_ERR,
605 * MISC: discard for unspecified reasons.
606 * Leave this enum value last.
608 HTT_RX_IND_MPDU_STATUS_ERR_MISC = 0xFF
611 struct htt_rx_indication_mpdu_range {
613 u8 mpdu_range_status; /* %htt_rx_mpdu_status */
618 struct htt_rx_indication_prefix {
619 __le16 fw_rx_desc_bytes;
624 struct htt_rx_indication {
625 struct htt_rx_indication_hdr hdr;
626 struct htt_rx_indication_ppdu ppdu;
627 struct htt_rx_indication_prefix prefix;
630 * the following fields are both dynamically sized, so
631 * take care addressing them
634 /* the size of this is %fw_rx_desc_bytes */
635 struct fw_rx_desc_base fw_desc;
638 * %mpdu_ranges starts after &%prefix + roundup(%fw_rx_desc_bytes, 4)
639 * and has %num_mpdu_ranges elements.
641 struct htt_rx_indication_mpdu_range mpdu_ranges[0];
644 static inline struct htt_rx_indication_mpdu_range *
645 htt_rx_ind_get_mpdu_ranges(struct htt_rx_indication *rx_ind)
649 ptr += sizeof(rx_ind->hdr)
650 + sizeof(rx_ind->ppdu)
651 + sizeof(rx_ind->prefix)
652 + roundup(__le16_to_cpu(rx_ind->prefix.fw_rx_desc_bytes), 4);
656 enum htt_rx_flush_mpdu_status {
657 HTT_RX_FLUSH_MPDU_DISCARD = 0,
658 HTT_RX_FLUSH_MPDU_REORDER = 1,
662 * htt_rx_flush - discard or reorder given range of mpdus
664 * Note: host must check if all sequence numbers between
665 * [seq_num_start, seq_num_end-1] are valid.
667 struct htt_rx_flush {
671 u8 mpdu_status; /* %htt_rx_flush_mpdu_status */
672 u8 seq_num_start; /* it is 6 LSBs of 802.11 seq no */
673 u8 seq_num_end; /* it is 6 LSBs of 802.11 seq no */
676 struct htt_rx_peer_map {
684 struct htt_rx_peer_unmap {
689 enum htt_security_types {
695 HTT_SECURITY_TKIP_NOMIC,
696 HTT_SECURITY_AES_CCMP,
699 HTT_NUM_SECURITY_TYPES /* keep this last! */
702 enum htt_security_flags {
703 #define HTT_SECURITY_TYPE_MASK 0x7F
704 #define HTT_SECURITY_TYPE_LSB 0
705 HTT_SECURITY_IS_UNICAST = 1 << 7
708 struct htt_security_indication {
710 /* dont use bitfields; undefined behaviour */
711 u8 flags; /* %htt_security_flags */
713 u8 security_type:7, /* %htt_security_types */
722 #define HTT_RX_BA_INFO0_TID_MASK 0x000F
723 #define HTT_RX_BA_INFO0_TID_LSB 0
724 #define HTT_RX_BA_INFO0_PEER_ID_MASK 0xFFF0
725 #define HTT_RX_BA_INFO0_PEER_ID_LSB 4
727 struct htt_rx_addba {
729 __le16 info0; /* %HTT_RX_BA_INFO0_ */
732 struct htt_rx_delba {
734 __le16 info0; /* %HTT_RX_BA_INFO0_ */
737 enum htt_data_tx_status {
738 HTT_DATA_TX_STATUS_OK = 0,
739 HTT_DATA_TX_STATUS_DISCARD = 1,
740 HTT_DATA_TX_STATUS_NO_ACK = 2,
741 HTT_DATA_TX_STATUS_POSTPONE = 3, /* HL only */
742 HTT_DATA_TX_STATUS_DOWNLOAD_FAIL = 128
745 enum htt_data_tx_flags {
746 #define HTT_DATA_TX_STATUS_MASK 0x07
747 #define HTT_DATA_TX_STATUS_LSB 0
748 #define HTT_DATA_TX_TID_MASK 0x78
749 #define HTT_DATA_TX_TID_LSB 3
750 HTT_DATA_TX_TID_INVALID = 1 << 7
753 #define HTT_TX_COMPL_INV_MSDU_ID 0xFFFF
755 struct htt_data_tx_completion {
766 __le16 msdus[0]; /* variable length based on %num_msdus */
769 struct htt_tx_compl_ind_base {
771 u16 payload[1/*or more*/];
774 struct htt_rc_tx_done_params {
778 u32 num_enqued; /* 1 for non-AMPDU */
780 u32 num_failed; /* for AMPDU */
786 struct htt_rc_update {
792 struct htt_rc_tx_done_params params[0]; /* variable length %num_elems */
795 /* see htt_rx_indication for similar fields and descriptions */
796 struct htt_rx_fragment_indication {
798 u8 info0; /* %HTT_RX_FRAG_IND_INFO0_ */
805 __le32 info1; /* %HTT_RX_FRAG_IND_INFO1_ */
806 __le16 fw_rx_desc_bytes;
809 u8 fw_msdu_rx_desc[0];
812 #define HTT_RX_FRAG_IND_INFO0_EXT_TID_MASK 0x1F
813 #define HTT_RX_FRAG_IND_INFO0_EXT_TID_LSB 0
814 #define HTT_RX_FRAG_IND_INFO0_FLUSH_VALID_MASK 0x20
815 #define HTT_RX_FRAG_IND_INFO0_FLUSH_VALID_LSB 5
817 #define HTT_RX_FRAG_IND_INFO1_FLUSH_SEQ_NUM_START_MASK 0x0000003F
818 #define HTT_RX_FRAG_IND_INFO1_FLUSH_SEQ_NUM_START_LSB 0
819 #define HTT_RX_FRAG_IND_INFO1_FLUSH_SEQ_NUM_END_MASK 0x00000FC0
820 #define HTT_RX_FRAG_IND_INFO1_FLUSH_SEQ_NUM_END_LSB 6
822 struct htt_rx_pn_ind {
832 struct htt_rx_offload_msdu {
841 struct htt_rx_offload_ind {
846 struct htt_rx_in_ord_msdu_desc {
853 struct htt_rx_in_ord_ind {
859 struct htt_rx_in_ord_msdu_desc msdu_descs[0];
862 #define HTT_RX_IN_ORD_IND_INFO_TID_MASK 0x0000001f
863 #define HTT_RX_IN_ORD_IND_INFO_TID_LSB 0
864 #define HTT_RX_IN_ORD_IND_INFO_OFFLOAD_MASK 0x00000020
865 #define HTT_RX_IN_ORD_IND_INFO_OFFLOAD_LSB 5
866 #define HTT_RX_IN_ORD_IND_INFO_FRAG_MASK 0x00000040
867 #define HTT_RX_IN_ORD_IND_INFO_FRAG_LSB 6
870 * target -> host test message definition
872 * The following field definitions describe the format of the test
873 * message sent from the target to the host.
874 * The message consists of a 4-octet header, followed by a variable
875 * number of 32-bit integer values, followed by a variable number
876 * of 8-bit character values.
879 * |-----------------------------------------------------------|
880 * | num chars | num ints | msg type |
881 * |-----------------------------------------------------------|
883 * |-----------------------------------------------------------|
885 * |-----------------------------------------------------------|
887 * |-----------------------------------------------------------|
888 * | char 3 | char 2 | char 1 | char 0 |
889 * |-----------------------------------------------------------|
890 * | | | ... | char 4 |
891 * |-----------------------------------------------------------|
894 * Purpose: identifies this as a test message
895 * Value: HTT_MSG_TYPE_TEST
898 * Purpose: indicate how many 32-bit integers follow the message header
901 * Purpose: indicate how many 8-bit charaters follow the series of integers
907 /* payload consists of 2 lists:
908 * a) num_ints * sizeof(__le32)
909 * b) num_chars * sizeof(u8) aligned to 4bytes */
913 static inline __le32 *htt_rx_test_get_ints(struct htt_rx_test *rx_test)
915 return (__le32 *)rx_test->payload;
918 static inline u8 *htt_rx_test_get_chars(struct htt_rx_test *rx_test)
920 return rx_test->payload + (rx_test->num_ints * sizeof(__le32));
924 * target -> host packet log message
926 * The following field definitions describe the format of the packet log
927 * message sent from the target to the host.
928 * The message consists of a 4-octet header,followed by a variable number
929 * of 32-bit character values.
931 * |31 24|23 16|15 8|7 0|
932 * |-----------------------------------------------------------|
934 * |-----------------------------------------------------------|
936 * |-----------------------------------------------------------|
939 * Purpose: identifies this as a test message
940 * Value: HTT_MSG_TYPE_PACKETLOG
942 struct htt_pktlog_msg {
947 struct htt_dbg_stats_rx_reorder_stats {
948 /* Non QoS MPDUs received */
949 __le32 deliver_non_qos;
951 /* MPDUs received in-order */
952 __le32 deliver_in_order;
954 /* Flush due to reorder timer expired */
955 __le32 deliver_flush_timeout;
957 /* Flush due to move out of window */
958 __le32 deliver_flush_oow;
960 /* Flush due to DELBA */
961 __le32 deliver_flush_delba;
963 /* MPDUs dropped due to FCS error */
966 /* MPDUs dropped due to monitor mode non-data packet */
969 /* MPDUs dropped due to invalid peer */
972 /* MPDUs dropped due to duplication (non aggregation) */
975 /* MPDUs dropped due to processed before */
978 /* MPDUs dropped due to duplicate in reorder queue */
979 __le32 dup_in_reorder;
981 /* Reorder timeout happened */
982 __le32 reorder_timeout;
984 /* invalid bar ssn */
985 __le32 invalid_bar_ssn;
987 /* reorder reset due to bar ssn */
991 struct htt_dbg_stats_wal_tx_stats {
992 /* Num HTT cookies queued to dispatch list */
995 /* Num HTT cookies dispatched */
996 __le32 comp_delivered;
998 /* Num MSDU queued to WAL */
1001 /* Num MPDU queue to WAL */
1004 /* Num MSDUs dropped by WMM limit */
1007 /* Num Local frames queued */
1008 __le32 local_enqued;
1010 /* Num Local frames done */
1013 /* Num queued to HW */
1016 /* Num PPDU reaped from HW */
1022 /* Num PPDUs cleaned up in TX abort */
1025 /* Num MPDUs requed by SW */
1026 __le32 mpdus_requed;
1028 /* excessive retries */
1031 /* data hw rate code */
1034 /* Scheduler self triggers */
1035 __le32 self_triggers;
1037 /* frames dropped due to excessive sw retries */
1038 __le32 sw_retry_failure;
1040 /* illegal rate phy errors */
1041 __le32 illgl_rate_phy_err;
1043 /* wal pdev continous xretry */
1044 __le32 pdev_cont_xretry;
1046 /* wal pdev continous xretry */
1047 __le32 pdev_tx_timeout;
1049 /* wal pdev resets */
1052 __le32 phy_underrun;
1054 /* MPDU is more than txop limit */
1058 struct htt_dbg_stats_wal_rx_stats {
1059 /* Cnts any change in ring routing mid-ppdu */
1060 __le32 mid_ppdu_route_change;
1062 /* Total number of statuses processed */
1065 /* Extra frags on rings 0-3 */
1071 /* MSDUs / MPDUs delivered to HTT */
1075 /* MSDUs / MPDUs delivered to local stack */
1079 /* AMSDUs that have more MSDUs than the status ring size */
1080 __le32 oversize_amsdu;
1082 /* Number of PHY errors */
1085 /* Number of PHY errors drops */
1086 __le32 phy_err_drop;
1088 /* Number of mpdu errors - FCS, MIC, ENC etc. */
1092 struct htt_dbg_stats_wal_peer_stats {
1093 __le32 dummy; /* REMOVE THIS ONCE REAL PEER STAT COUNTERS ARE ADDED */
1096 struct htt_dbg_stats_wal_pdev_txrx {
1097 struct htt_dbg_stats_wal_tx_stats tx_stats;
1098 struct htt_dbg_stats_wal_rx_stats rx_stats;
1099 struct htt_dbg_stats_wal_peer_stats peer_stats;
1102 struct htt_dbg_stats_rx_rate_info {
1114 * htt_dbg_stats_status -
1115 * present - The requested stats have been delivered in full.
1116 * This indicates that either the stats information was contained
1117 * in its entirety within this message, or else this message
1118 * completes the delivery of the requested stats info that was
1119 * partially delivered through earlier STATS_CONF messages.
1120 * partial - The requested stats have been delivered in part.
1121 * One or more subsequent STATS_CONF messages with the same
1122 * cookie value will be sent to deliver the remainder of the
1124 * error - The requested stats could not be delivered, for example due
1125 * to a shortage of memory to construct a message holding the
1127 * invalid - The requested stat type is either not recognized, or the
1128 * target is configured to not gather the stats type in question.
1129 * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
1130 * series_done - This special value indicates that no further stats info
1131 * elements are present within a series of stats info elems
1132 * (within a stats upload confirmation message).
1134 enum htt_dbg_stats_status {
1135 HTT_DBG_STATS_STATUS_PRESENT = 0,
1136 HTT_DBG_STATS_STATUS_PARTIAL = 1,
1137 HTT_DBG_STATS_STATUS_ERROR = 2,
1138 HTT_DBG_STATS_STATUS_INVALID = 3,
1139 HTT_DBG_STATS_STATUS_SERIES_DONE = 7
1143 * target -> host statistics upload
1145 * The following field definitions describe the format of the HTT target
1146 * to host stats upload confirmation message.
1147 * The message contains a cookie echoed from the HTT host->target stats
1148 * upload request, which identifies which request the confirmation is
1149 * for, and a series of tag-length-value stats information elements.
1150 * The tag-length header for each stats info element also includes a
1151 * status field, to indicate whether the request for the stat type in
1152 * question was fully met, partially met, unable to be met, or invalid
1153 * (if the stat type in question is disabled in the target).
1154 * A special value of all 1's in this status field is used to indicate
1155 * the end of the series of stats info elements.
1158 * |31 16|15 8|7 5|4 0|
1159 * |------------------------------------------------------------|
1160 * | reserved | msg type |
1161 * |------------------------------------------------------------|
1163 * |------------------------------------------------------------|
1165 * |------------------------------------------------------------|
1166 * | stats entry length | reserved | S |stat type|
1167 * |------------------------------------------------------------|
1169 * | type-specific stats info |
1171 * |------------------------------------------------------------|
1172 * | stats entry length | reserved | S |stat type|
1173 * |------------------------------------------------------------|
1175 * | type-specific stats info |
1177 * |------------------------------------------------------------|
1178 * | n/a | reserved | 111 | n/a |
1179 * |------------------------------------------------------------|
1183 * Purpose: identifies this is a statistics upload confirmation message
1187 * Purpose: Provide a mechanism to match a target->host stats confirmation
1188 * message with its preceding host->target stats request message.
1189 * Value: LSBs of the opaque cookie specified by the host-side requestor
1192 * Purpose: Provide a mechanism to match a target->host stats confirmation
1193 * message with its preceding host->target stats request message.
1194 * Value: MSBs of the opaque cookie specified by the host-side requestor
1196 * Stats Information Element tag-length header fields:
1199 * Purpose: identifies the type of statistics info held in the
1200 * following information element
1201 * Value: htt_dbg_stats_type
1204 * Purpose: indicate whether the requested stats are present
1205 * Value: htt_dbg_stats_status, including a special value (0x7) to mark
1206 * the completion of the stats entry series
1209 * Purpose: indicate the stats information size
1210 * Value: This field specifies the number of bytes of stats information
1211 * that follows the element tag-length header.
1212 * It is expected but not required that this length is a multiple of
1213 * 4 bytes. Even if the length is not an integer multiple of 4, the
1214 * subsequent stats entry header will begin on a 4-byte aligned
1218 #define HTT_STATS_CONF_ITEM_INFO_STAT_TYPE_MASK 0x1F
1219 #define HTT_STATS_CONF_ITEM_INFO_STAT_TYPE_LSB 0
1220 #define HTT_STATS_CONF_ITEM_INFO_STATUS_MASK 0xE0
1221 #define HTT_STATS_CONF_ITEM_INFO_STATUS_LSB 5
1223 struct htt_stats_conf_item {
1227 u8 stat_type:5; /* %HTT_DBG_STATS_ */
1228 u8 status:3; /* %HTT_DBG_STATS_STATUS_ */
1233 u8 payload[0]; /* roundup(length, 4) long */
1236 struct htt_stats_conf {
1241 /* each item has variable length! */
1242 struct htt_stats_conf_item items[0];
1245 static inline struct htt_stats_conf_item *htt_stats_conf_next_item(
1246 const struct htt_stats_conf_item *item)
1248 return (void *)item + sizeof(*item) + roundup(item->length, 4);
1252 * host -> target FRAG DESCRIPTOR/MSDU_EXT DESC bank
1254 * The following field definitions describe the format of the HTT host
1255 * to target frag_desc/msdu_ext bank configuration message.
1256 * The message contains the based address and the min and max id of the
1257 * MSDU_EXT/FRAG_DESC that will be used by the HTT to map MSDU DESC and
1258 * MSDU_EXT/FRAG_DESC.
1259 * HTT will use id in HTT descriptor instead sending the frag_desc_ptr.
1260 * For QCA988X HW the firmware will use fragment_desc_ptr but in WIFI2.0
1261 * the hardware does the mapping/translation.
1263 * Total banks that can be configured is configured to 16.
1265 * This should be called before any TX has be initiated by the HTT
1267 * |31 16|15 8|7 5|4 0|
1268 * |------------------------------------------------------------|
1269 * | DESC_SIZE | NUM_BANKS | RES |SWP|pdev| msg type |
1270 * |------------------------------------------------------------|
1271 * | BANK0_BASE_ADDRESS |
1272 * |------------------------------------------------------------|
1274 * |------------------------------------------------------------|
1275 * | BANK15_BASE_ADDRESS |
1276 * |------------------------------------------------------------|
1277 * | BANK0_MAX_ID | BANK0_MIN_ID |
1278 * |------------------------------------------------------------|
1280 * |------------------------------------------------------------|
1281 * | BANK15_MAX_ID | BANK15_MIN_ID |
1282 * |------------------------------------------------------------|
1287 * - BANKx_BASE_ADDRESS
1289 * Purpose: Provide a mechanism to specify the base address of the MSDU_EXT
1290 * bank physical/bus address.
1293 * Purpose: Provide a mechanism to specify the min index that needs to
1297 * Purpose: Provide a mechanism to specify the max index that needs to
1300 struct htt_frag_desc_bank_id {
1305 /* real is 16 but it wouldn't fit in the max htt message size
1306 * so we use a conservatively safe value for now */
1307 #define HTT_FRAG_DESC_BANK_MAX 4
1309 #define HTT_FRAG_DESC_BANK_CFG_INFO_PDEV_ID_MASK 0x03
1310 #define HTT_FRAG_DESC_BANK_CFG_INFO_PDEV_ID_LSB 0
1311 #define HTT_FRAG_DESC_BANK_CFG_INFO_SWAP (1 << 2)
1313 struct htt_frag_desc_bank_cfg {
1314 u8 info; /* HTT_FRAG_DESC_BANK_CFG_INFO_ */
1317 __le32 bank_base_addrs[HTT_FRAG_DESC_BANK_MAX];
1318 struct htt_frag_desc_bank_id bank_id[HTT_FRAG_DESC_BANK_MAX];
1322 /* WEP: 24-bit PN */
1325 /* TKIP or CCMP: 48-bit PN */
1328 /* WAPI: 128-bit PN */
1333 struct htt_cmd_hdr hdr;
1335 struct htt_ver_req ver_req;
1336 struct htt_mgmt_tx_desc mgmt_tx;
1337 struct htt_data_tx_desc data_tx;
1338 struct htt_rx_ring_setup rx_setup;
1339 struct htt_stats_req stats_req;
1340 struct htt_oob_sync_req oob_sync_req;
1341 struct htt_aggr_conf aggr_conf;
1342 struct htt_frag_desc_bank_cfg frag_desc_bank_cfg;
1347 struct htt_resp_hdr hdr;
1349 struct htt_ver_resp ver_resp;
1350 struct htt_mgmt_tx_completion mgmt_tx_completion;
1351 struct htt_data_tx_completion data_tx_completion;
1352 struct htt_rx_indication rx_ind;
1353 struct htt_rx_fragment_indication rx_frag_ind;
1354 struct htt_rx_peer_map peer_map;
1355 struct htt_rx_peer_unmap peer_unmap;
1356 struct htt_rx_flush rx_flush;
1357 struct htt_rx_addba rx_addba;
1358 struct htt_rx_delba rx_delba;
1359 struct htt_security_indication security_indication;
1360 struct htt_rc_update rc_update;
1361 struct htt_rx_test rx_test;
1362 struct htt_pktlog_msg pktlog_msg;
1363 struct htt_stats_conf stats_conf;
1364 struct htt_rx_pn_ind rx_pn_ind;
1365 struct htt_rx_offload_ind rx_offload_ind;
1366 struct htt_rx_in_ord_ind rx_in_ord_ind;
1370 /*** host side structures follow ***/
1372 struct htt_tx_done {
1379 struct htt_peer_map_event {
1385 struct htt_peer_unmap_event {
1389 struct ath10k_htt_txbuf {
1390 struct htt_data_tx_desc_frag frags[2];
1391 struct ath10k_htc_hdr htc_hdr;
1392 struct htt_cmd_hdr cmd_hdr;
1393 struct htt_data_tx_desc cmd_tx;
1398 enum ath10k_htc_ep_id eid;
1400 u8 target_version_major;
1401 u8 target_version_minor;
1402 struct completion target_version_received;
1403 enum ath10k_fw_htt_op_version op_version;
1407 const enum htt_t2h_msg_type *t2h_msg_types;
1408 u32 t2h_msg_types_max;
1412 * Ring of network buffer objects - This ring is
1413 * used exclusively by the host SW. This ring
1414 * mirrors the dev_addrs_ring that is shared
1415 * between the host SW and the MAC HW. The host SW
1416 * uses this netbufs ring to locate the network
1417 * buffer objects whose data buffers the HW has
1420 struct sk_buff **netbufs_ring;
1422 /* This is used only with firmware supporting IN_ORD_IND.
1424 * With Full Rx Reorder the HTT Rx Ring is more of a temporary
1425 * buffer ring from which buffer addresses are copied by the
1426 * firmware to MAC Rx ring. Firmware then delivers IN_ORD_IND
1427 * pointing to specific (re-ordered) buffers.
1429 * FIXME: With kernel generic hashing functions there's a lot
1430 * of hash collisions for sk_buffs.
1433 DECLARE_HASHTABLE(skb_table, 4);
1436 * Ring of buffer addresses -
1437 * This ring holds the "physical" device address of the
1438 * rx buffers the host SW provides for the MAC HW to
1441 __le32 *paddrs_ring;
1444 * Base address of ring, as a "physical" device address
1445 * rather than a CPU address.
1447 dma_addr_t base_paddr;
1449 /* how many elems in the ring (power of 2) */
1455 /* how many rx buffers to keep in the ring */
1458 /* how many rx buffers (full+empty) are in the ring */
1462 * alloc_idx - where HTT SW has deposited empty buffers
1463 * This is allocated in consistent mem, so that the FW can
1464 * read this variable, and program the HW's FW_IDX reg with
1465 * the value of this shadow register.
1472 /* where HTT SW has processed bufs filled by rx MAC DMA */
1474 unsigned msdu_payld;
1478 * refill_retry_timer - timer triggered when the ring is
1479 * not refilled to the level expected
1481 struct timer_list refill_retry_timer;
1483 /* Protects access to all rx ring buffer state variables */
1487 unsigned int prefetch_len;
1489 /* Protects access to pending_tx, num_pending_tx */
1491 int max_num_pending_tx;
1493 int num_pending_mgmt_tx;
1494 struct idr pending_tx;
1495 wait_queue_head_t empty_tx_wq;
1497 /* set if host-fw communication goes haywire
1498 * used to avoid further failures */
1500 struct tasklet_struct rx_replenish_task;
1502 /* This is used to group tx/rx completions separately and process them
1503 * in batches to reduce cache stalls */
1504 struct tasklet_struct txrx_compl_task;
1505 struct sk_buff_head tx_compl_q;
1506 struct sk_buff_head rx_compl_q;
1507 struct sk_buff_head rx_in_ord_compl_q;
1509 /* rx_status template */
1510 struct ieee80211_rx_status rx_status;
1514 struct htt_msdu_ext_desc *vaddr;
1519 struct ath10k_htt_txbuf *vaddr;
1523 #define RX_HTT_HDR_STATUS_LEN 64
1525 /* This structure layout is programmed via rx ring setup
1526 * so that FW knows how to transfer the rx descriptor to the host.
1527 * Buffers like this are placed on the rx ring. */
1528 struct htt_rx_desc {
1530 /* This field is filled on the host using the msdu buffer
1531 * from htt_rx_indication */
1532 struct fw_rx_desc_base fw_desc;
1536 struct rx_attention attention;
1537 struct rx_frag_info frag_info;
1538 struct rx_mpdu_start mpdu_start;
1539 struct rx_msdu_start msdu_start;
1540 struct rx_msdu_end msdu_end;
1541 struct rx_mpdu_end mpdu_end;
1542 struct rx_ppdu_start ppdu_start;
1543 struct rx_ppdu_end ppdu_end;
1545 u8 rx_hdr_status[RX_HTT_HDR_STATUS_LEN];
1549 #define HTT_RX_DESC_ALIGN 8
1551 #define HTT_MAC_ADDR_LEN 6
1555 * Should be: sizeof(struct htt_host_rx_desc) + max rx MSDU size,
1556 * rounded up to a cache line size.
1558 #define HTT_RX_BUF_SIZE 1920
1559 #define HTT_RX_MSDU_SIZE (HTT_RX_BUF_SIZE - (int)sizeof(struct htt_rx_desc))
1561 /* Refill a bunch of RX buffers for each refill round so that FW/HW can handle
1562 * aggregated traffic more nicely. */
1563 #define ATH10K_HTT_MAX_NUM_REFILL 16
1566 * DMA_MAP expects the buffer to be an integral number of cache lines.
1567 * Rather than checking the actual cache line size, this code makes a
1568 * conservative estimate of what the cache line size could be.
1570 #define HTT_LOG2_MAX_CACHE_LINE_SIZE 7 /* 2^7 = 128 */
1571 #define HTT_MAX_CACHE_LINE_SIZE_MASK ((1 << HTT_LOG2_MAX_CACHE_LINE_SIZE) - 1)
1573 /* These values are default in most firmware revisions and apparently are a
1574 * sweet spot performance wise.
1576 #define ATH10K_HTT_MAX_NUM_AMSDU_DEFAULT 3
1577 #define ATH10K_HTT_MAX_NUM_AMPDU_DEFAULT 64
1579 int ath10k_htt_connect(struct ath10k_htt *htt);
1580 int ath10k_htt_init(struct ath10k *ar);
1581 int ath10k_htt_setup(struct ath10k_htt *htt);
1583 int ath10k_htt_tx_alloc(struct ath10k_htt *htt);
1584 void ath10k_htt_tx_free(struct ath10k_htt *htt);
1586 int ath10k_htt_rx_alloc(struct ath10k_htt *htt);
1587 int ath10k_htt_rx_ring_refill(struct ath10k *ar);
1588 void ath10k_htt_rx_free(struct ath10k_htt *htt);
1590 void ath10k_htt_htc_tx_complete(struct ath10k *ar, struct sk_buff *skb);
1591 void ath10k_htt_t2h_msg_handler(struct ath10k *ar, struct sk_buff *skb);
1592 int ath10k_htt_h2t_ver_req_msg(struct ath10k_htt *htt);
1593 int ath10k_htt_h2t_stats_req(struct ath10k_htt *htt, u8 mask, u64 cookie);
1594 int ath10k_htt_send_frag_desc_bank_cfg(struct ath10k_htt *htt);
1595 int ath10k_htt_send_rx_ring_cfg_ll(struct ath10k_htt *htt);
1596 int ath10k_htt_h2t_aggr_cfg_msg(struct ath10k_htt *htt,
1597 u8 max_subfrms_ampdu,
1598 u8 max_subfrms_amsdu);
1599 void ath10k_htt_hif_tx_complete(struct ath10k *ar, struct sk_buff *skb);
1601 void __ath10k_htt_tx_dec_pending(struct ath10k_htt *htt, bool limit_mgmt_desc);
1602 int ath10k_htt_tx_alloc_msdu_id(struct ath10k_htt *htt, struct sk_buff *skb);
1603 void ath10k_htt_tx_free_msdu_id(struct ath10k_htt *htt, u16 msdu_id);
1604 int ath10k_htt_mgmt_tx(struct ath10k_htt *htt, struct sk_buff *);
1605 int ath10k_htt_tx(struct ath10k_htt *htt,
1606 enum ath10k_hw_txrx_mode txmode,
1607 struct sk_buff *msdu);
1608 void ath10k_htt_rx_pktlog_completion_handler(struct ath10k *ar,
1609 struct sk_buff *skb);