drivers/net/wireless/ath/ath10k/hw.c

   1 /*
   2  * Copyright (c) 2014-2015 Qualcomm Atheros, Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <linux/types.h>
  18 #include "core.h"
  19 #include "hw.h"
  20 #include "hif.h"
  21 #include "wmi-ops.h"
  22
  23 const struct ath10k_hw_regs qca988x_regs = {
  24         .rtc_soc_base_address           = 0x00004000,
  25         .rtc_wmac_base_address          = 0x00005000,
  26         .soc_core_base_address          = 0x00009000,
  27         .wlan_mac_base_address          = 0x00020000,
  28         .ce_wrapper_base_address        = 0x00057000,
  29         .ce0_base_address               = 0x00057400,
  30         .ce1_base_address               = 0x00057800,
  31         .ce2_base_address               = 0x00057c00,
  32         .ce3_base_address               = 0x00058000,
  33         .ce4_base_address               = 0x00058400,
  34         .ce5_base_address               = 0x00058800,
  35         .ce6_base_address               = 0x00058c00,
  36         .ce7_base_address               = 0x00059000,
  37         .soc_reset_control_si0_rst_mask = 0x00000001,
  38         .soc_reset_control_ce_rst_mask  = 0x00040000,
  39         .soc_chip_id_address            = 0x000000ec,
  40         .scratch_3_address              = 0x00000030,
  41         .fw_indicator_address           = 0x00009030,
  42         .pcie_local_base_address        = 0x00080000,
  43         .ce_wrap_intr_sum_host_msi_lsb  = 0x00000008,
  44         .ce_wrap_intr_sum_host_msi_mask = 0x0000ff00,
  45         .pcie_intr_fw_mask              = 0x00000400,
  46         .pcie_intr_ce_mask_all          = 0x0007f800,
  47         .pcie_intr_clr_address          = 0x00000014,
  48 };
  49
  50 const struct ath10k_hw_regs qca6174_regs = {
  51         .rtc_soc_base_address                   = 0x00000800,
  52         .rtc_wmac_base_address                  = 0x00001000,
  53         .soc_core_base_address                  = 0x0003a000,
  54         .wlan_mac_base_address                  = 0x00010000,
  55         .ce_wrapper_base_address                = 0x00034000,
  56         .ce0_base_address                       = 0x00034400,
  57         .ce1_base_address                       = 0x00034800,
  58         .ce2_base_address                       = 0x00034c00,
  59         .ce3_base_address                       = 0x00035000,
  60         .ce4_base_address                       = 0x00035400,
  61         .ce5_base_address                       = 0x00035800,
  62         .ce6_base_address                       = 0x00035c00,
  63         .ce7_base_address                       = 0x00036000,
  64         .soc_reset_control_si0_rst_mask         = 0x00000000,
  65         .soc_reset_control_ce_rst_mask          = 0x00000001,
  66         .soc_chip_id_address                    = 0x000000f0,
  67         .scratch_3_address                      = 0x00000028,
  68         .fw_indicator_address                   = 0x0003a028,
  69         .pcie_local_base_address                = 0x00080000,
  70         .ce_wrap_intr_sum_host_msi_lsb          = 0x00000008,
  71         .ce_wrap_intr_sum_host_msi_mask         = 0x0000ff00,
  72         .pcie_intr_fw_mask                      = 0x00000400,
  73         .pcie_intr_ce_mask_all                  = 0x0007f800,
  74         .pcie_intr_clr_address                  = 0x00000014,
  75 };
  76
  77 const struct ath10k_hw_regs qca99x0_regs = {
  78         .rtc_soc_base_address                   = 0x00080000,
  79         .rtc_wmac_base_address                  = 0x00000000,
  80         .soc_core_base_address                  = 0x00082000,
  81         .wlan_mac_base_address                  = 0x00030000,
  82         .ce_wrapper_base_address                = 0x0004d000,
  83         .ce0_base_address                       = 0x0004a000,
  84         .ce1_base_address                       = 0x0004a400,
  85         .ce2_base_address                       = 0x0004a800,
  86         .ce3_base_address                       = 0x0004ac00,
  87         .ce4_base_address                       = 0x0004b000,
  88         .ce5_base_address                       = 0x0004b400,
  89         .ce6_base_address                       = 0x0004b800,
  90         .ce7_base_address                       = 0x0004bc00,
  91         /* Note: qca99x0 supports upto 12 Copy Engines. Other than address of
  92          * CE0 and CE1 no other copy engine is directly referred in the code.
  93          * It is not really necessary to assign address for newly supported
  94          * CEs in this address table.
  95          *      Copy Engine             Address
  96          *      CE8                     0x0004c000
  97          *      CE9                     0x0004c400
  98          *      CE10                    0x0004c800
  99          *      CE11                    0x0004cc00
 100          */
 101         .soc_reset_control_si0_rst_mask         = 0x00000001,
 102         .soc_reset_control_ce_rst_mask          = 0x00000100,
 103         .soc_chip_id_address                    = 0x000000ec,
 104         .scratch_3_address                      = 0x00040050,
 105         .fw_indicator_address                   = 0x00040050,
 106         .pcie_local_base_address                = 0x00000000,
 107         .ce_wrap_intr_sum_host_msi_lsb          = 0x0000000c,
 108         .ce_wrap_intr_sum_host_msi_mask         = 0x00fff000,
 109         .pcie_intr_fw_mask                      = 0x00100000,
 110         .pcie_intr_ce_mask_all                  = 0x000fff00,
 111         .pcie_intr_clr_address                  = 0x00000010,
 112 };
 113
 114 const struct ath10k_hw_regs qca4019_regs = {
 115         .rtc_soc_base_address                   = 0x00080000,
 116         .soc_core_base_address                  = 0x00082000,
 117         .wlan_mac_base_address                  = 0x00030000,
 118         .ce_wrapper_base_address                = 0x0004d000,
 119         .ce0_base_address                       = 0x0004a000,
 120         .ce1_base_address                       = 0x0004a400,
 121         .ce2_base_address                       = 0x0004a800,
 122         .ce3_base_address                       = 0x0004ac00,
 123         .ce4_base_address                       = 0x0004b000,
 124         .ce5_base_address                       = 0x0004b400,
 125         .ce6_base_address                       = 0x0004b800,
 126         .ce7_base_address                       = 0x0004bc00,
 127         /* qca4019 supports upto 12 copy engines. Since base address
 128          * of ce8 to ce11 are not directly referred in the code,
 129          * no need have them in separate members in this table.
 130          *      Copy Engine             Address
 131          *      CE8                     0x0004c000
 132          *      CE9                     0x0004c400
 133          *      CE10                    0x0004c800
 134          *      CE11                    0x0004cc00
 135          */
 136         .soc_reset_control_si0_rst_mask         = 0x00000001,
 137         .soc_reset_control_ce_rst_mask          = 0x00000100,
 138         .soc_chip_id_address                    = 0x000000ec,
 139         .fw_indicator_address                   = 0x0004f00c,
 140         .ce_wrap_intr_sum_host_msi_lsb          = 0x0000000c,
 141         .ce_wrap_intr_sum_host_msi_mask         = 0x00fff000,
 142         .pcie_intr_fw_mask                      = 0x00100000,
 143         .pcie_intr_ce_mask_all                  = 0x000fff00,
 144         .pcie_intr_clr_address                  = 0x00000010,
 145 };
 146
 147 const struct ath10k_hw_values qca988x_values = {
 148         .rtc_state_val_on               = 3,
 149         .ce_count                       = 8,
 150         .msi_assign_ce_max              = 7,
 151         .num_target_ce_config_wlan      = 7,
 152         .ce_desc_meta_data_mask         = 0xFFFC,
 153         .ce_desc_meta_data_lsb          = 2,
 154 };
 155
 156 const struct ath10k_hw_values qca6174_values = {
 157         .rtc_state_val_on               = 3,
 158         .ce_count                       = 8,
 159         .msi_assign_ce_max              = 7,
 160         .num_target_ce_config_wlan      = 7,
 161         .ce_desc_meta_data_mask         = 0xFFFC,
 162         .ce_desc_meta_data_lsb          = 2,
 163 };
 164
 165 const struct ath10k_hw_values qca99x0_values = {
 166         .rtc_state_val_on               = 5,
 167         .ce_count                       = 12,
 168         .msi_assign_ce_max              = 12,
 169         .num_target_ce_config_wlan      = 10,
 170         .ce_desc_meta_data_mask         = 0xFFF0,
 171         .ce_desc_meta_data_lsb          = 4,
 172 };
 173
 174 const struct ath10k_hw_values qca9888_values = {
 175         .rtc_state_val_on               = 3,
 176         .ce_count                       = 12,
 177         .msi_assign_ce_max              = 12,
 178         .num_target_ce_config_wlan      = 10,
 179         .ce_desc_meta_data_mask         = 0xFFF0,
 180         .ce_desc_meta_data_lsb          = 4,
 181 };
 182
 183 const struct ath10k_hw_values qca4019_values = {
 184         .ce_count                       = 12,
 185         .num_target_ce_config_wlan      = 10,
 186         .ce_desc_meta_data_mask         = 0xFFF0,
 187         .ce_desc_meta_data_lsb          = 4,
 188 };
 189
 190 void ath10k_hw_fill_survey_time(struct ath10k *ar, struct survey_info *survey,
 191                                 u32 cc, u32 rcc, u32 cc_prev, u32 rcc_prev)
 192 {
 193         u32 cc_fix = 0;
 194         u32 rcc_fix = 0;
 195         enum ath10k_hw_cc_wraparound_type wraparound_type;
 196
 197         survey->filled |= SURVEY_INFO_TIME |
 198                           SURVEY_INFO_TIME_BUSY;
 199
 200         wraparound_type = ar->hw_params.cc_wraparound_type;
 201
 202         if (cc < cc_prev || rcc < rcc_prev) {
 203                 switch (wraparound_type) {
 204                 case ATH10K_HW_CC_WRAP_SHIFTED_ALL:
 205                         if (cc < cc_prev) {
 206                                 cc_fix = 0x7fffffff;
 207                                 survey->filled &= ~SURVEY_INFO_TIME_BUSY;
 208                         }
 209                         break;
 210                 case ATH10K_HW_CC_WRAP_SHIFTED_EACH:
 211                         if (cc < cc_prev)
 212                                 cc_fix = 0x7fffffff;
 213
 214                         if (rcc < rcc_prev)
 215                                 rcc_fix = 0x7fffffff;
 216                         break;
 217                 case ATH10K_HW_CC_WRAP_DISABLED:
 218                         break;
 219                 }
 220         }
 221
 222         cc -= cc_prev - cc_fix;
 223         rcc -= rcc_prev - rcc_fix;
 224
 225         survey->time = CCNT_TO_MSEC(ar, cc);
 226         survey->time_busy = CCNT_TO_MSEC(ar, rcc);
 227 }
 228
 229 /* The firmware does not support setting the coverage class. Instead this
 230  * function monitors and modifies the corresponding MAC registers.
 231  */
 232 static void ath10k_hw_qca988x_set_coverage_class(struct ath10k *ar,
 233                                                  s16 value)
 234 {
 235         u32 slottime_reg;
 236         u32 slottime;
 237         u32 timeout_reg;
 238         u32 ack_timeout;
 239         u32 cts_timeout;
 240         u32 phyclk_reg;
 241         u32 phyclk;
 242         u64 fw_dbglog_mask;
 243         u32 fw_dbglog_level;
 244
 245         mutex_lock(&ar->conf_mutex);
 246
 247         /* Only modify registers if the core is started. */
 248         if ((ar->state != ATH10K_STATE_ON) &&
 249             (ar->state != ATH10K_STATE_RESTARTED))
 250                 goto unlock;
 251
 252         /* Retrieve the current values of the two registers that need to be
 253          * adjusted.
 254          */
 255         slottime_reg = ath10k_hif_read32(ar, WLAN_MAC_BASE_ADDRESS +
 256                                              WAVE1_PCU_GBL_IFS_SLOT);
 257         timeout_reg = ath10k_hif_read32(ar, WLAN_MAC_BASE_ADDRESS +
 258                                             WAVE1_PCU_ACK_CTS_TIMEOUT);
 259         phyclk_reg = ath10k_hif_read32(ar, WLAN_MAC_BASE_ADDRESS +
 260                                            WAVE1_PHYCLK);
 261         phyclk = MS(phyclk_reg, WAVE1_PHYCLK_USEC) + 1;
 262
 263         if (value < 0)
 264                 value = ar->fw_coverage.coverage_class;
 265
 266         /* Break out if the coverage class and registers have the expected
 267          * value.
 268          */
 269         if (value == ar->fw_coverage.coverage_class &&
 270             slottime_reg == ar->fw_coverage.reg_slottime_conf &&
 271             timeout_reg == ar->fw_coverage.reg_ack_cts_timeout_conf &&
 272             phyclk_reg == ar->fw_coverage.reg_phyclk)
 273                 goto unlock;
 274
 275         /* Store new initial register values from the firmware. */
 276         if (slottime_reg != ar->fw_coverage.reg_slottime_conf)
 277                 ar->fw_coverage.reg_slottime_orig = slottime_reg;
 278         if (timeout_reg != ar->fw_coverage.reg_ack_cts_timeout_conf)
 279                 ar->fw_coverage.reg_ack_cts_timeout_orig = timeout_reg;
 280         ar->fw_coverage.reg_phyclk = phyclk_reg;
 281
 282         /* Calculat new value based on the (original) firmware calculation. */
 283         slottime_reg = ar->fw_coverage.reg_slottime_orig;
 284         timeout_reg = ar->fw_coverage.reg_ack_cts_timeout_orig;
 285
 286         /* Do some sanity checks on the slottime register. */
 287         if (slottime_reg % phyclk) {
 288                 ath10k_warn(ar,
 289                             "failed to set coverage class: expected integer microsecond value in register\n");
 290
 291                 goto store_regs;
 292         }
 293
 294         slottime = MS(slottime_reg, WAVE1_PCU_GBL_IFS_SLOT);
 295         slottime = slottime / phyclk;
 296         if (slottime != 9 && slottime != 20) {
 297                 ath10k_warn(ar,
 298                             "failed to set coverage class: expected slot time of 9 or 20us in HW register. It is %uus.\n",
 299                             slottime);
 300
 301                 goto store_regs;
 302         }
 303
 304         /* Recalculate the register values by adding the additional propagation
 305          * delay (3us per coverage class).
 306          */
 307
 308         slottime = MS(slottime_reg, WAVE1_PCU_GBL_IFS_SLOT);
 309         slottime += value * 3 * phyclk;
 310         slottime = min_t(u32, slottime, WAVE1_PCU_GBL_IFS_SLOT_MAX);
 311         slottime = SM(slottime, WAVE1_PCU_GBL_IFS_SLOT);
 312         slottime_reg = (slottime_reg & ~WAVE1_PCU_GBL_IFS_SLOT_MASK) | slottime;
 313
 314         /* Update ack timeout (lower halfword). */
 315         ack_timeout = MS(timeout_reg, WAVE1_PCU_ACK_CTS_TIMEOUT_ACK);
 316         ack_timeout += 3 * value * phyclk;
 317         ack_timeout = min_t(u32, ack_timeout, WAVE1_PCU_ACK_CTS_TIMEOUT_MAX);
 318         ack_timeout = SM(ack_timeout, WAVE1_PCU_ACK_CTS_TIMEOUT_ACK);
 319
 320         /* Update cts timeout (upper halfword). */
 321         cts_timeout = MS(timeout_reg, WAVE1_PCU_ACK_CTS_TIMEOUT_CTS);
 322         cts_timeout += 3 * value * phyclk;
 323         cts_timeout = min_t(u32, cts_timeout, WAVE1_PCU_ACK_CTS_TIMEOUT_MAX);
 324         cts_timeout = SM(cts_timeout, WAVE1_PCU_ACK_CTS_TIMEOUT_CTS);
 325
 326         timeout_reg = ack_timeout | cts_timeout;
 327
 328         ath10k_hif_write32(ar,
 329                            WLAN_MAC_BASE_ADDRESS + WAVE1_PCU_GBL_IFS_SLOT,
 330                            slottime_reg);
 331         ath10k_hif_write32(ar,
 332                            WLAN_MAC_BASE_ADDRESS + WAVE1_PCU_ACK_CTS_TIMEOUT,
 333                            timeout_reg);
 334
 335         /* Ensure we have a debug level of WARN set for the case that the
 336          * coverage class is larger than 0. This is important as we need to
 337          * set the registers again if the firmware does an internal reset and
 338          * this way we will be notified of the event.
 339          */
 340         fw_dbglog_mask = ath10k_debug_get_fw_dbglog_mask(ar);
 341         fw_dbglog_level = ath10k_debug_get_fw_dbglog_level(ar);
 342
 343         if (value > 0) {
 344                 if (fw_dbglog_level > ATH10K_DBGLOG_LEVEL_WARN)
 345                         fw_dbglog_level = ATH10K_DBGLOG_LEVEL_WARN;
 346                 fw_dbglog_mask = ~0;
 347         }
 348
 349         ath10k_wmi_dbglog_cfg(ar, fw_dbglog_mask, fw_dbglog_level);
 350
 351 store_regs:
 352         /* After an error we will not retry setting the coverage class. */
 353         spin_lock_bh(&ar->data_lock);
 354         ar->fw_coverage.coverage_class = value;
 355         spin_unlock_bh(&ar->data_lock);
 356
 357         ar->fw_coverage.reg_slottime_conf = slottime_reg;
 358         ar->fw_coverage.reg_ack_cts_timeout_conf = timeout_reg;
 359
 360 unlock:
 361         mutex_unlock(&ar->conf_mutex);
 362 }
 363
 364 const struct ath10k_hw_ops qca988x_ops = {
 365         .set_coverage_class = ath10k_hw_qca988x_set_coverage_class,
 366 };
 367
 368 static int ath10k_qca99x0_rx_desc_get_l3_pad_bytes(struct htt_rx_desc *rxd)
 369 {
 370         return MS(__le32_to_cpu(rxd->msdu_end.qca99x0.info1),
 371                   RX_MSDU_END_INFO1_L3_HDR_PAD);
 372 }
 373
 374 const struct ath10k_hw_ops qca99x0_ops = {
 375         .rx_desc_get_l3_pad_bytes = ath10k_qca99x0_rx_desc_get_l3_pad_bytes,
 376 };