2 * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org>
3 * Copyright (c) 2006-2007 Nick Kossifidis <mickflemm@gmail.com>
5 * Permission to use, copy, modify, and distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
21 /* TODO: Clean up channel debugging (doesn't work anyway) and start
22 * working on reg. control code using all available eeprom information
23 * (rev. engineering needed) */
27 #include <linux/interrupt.h>
28 #include <linux/types.h>
29 #include <linux/average.h>
30 #include <linux/leds.h>
31 #include <net/mac80211.h>
33 /* RX/TX descriptor hw structs
34 * TODO: Driver part should only see sw structs */
37 /* EEPROM structs/offsets
38 * TODO: Make a more generic struct (eg. add more stuff to ath5k_capabilities)
39 * and clean up common bits, then introduce set/get functions in eeprom.c */
46 #define PCI_DEVICE_ID_ATHEROS_AR5210 0x0007 /* AR5210 */
47 #define PCI_DEVICE_ID_ATHEROS_AR5311 0x0011 /* AR5311 */
48 #define PCI_DEVICE_ID_ATHEROS_AR5211 0x0012 /* AR5211 */
49 #define PCI_DEVICE_ID_ATHEROS_AR5212 0x0013 /* AR5212 */
50 #define PCI_DEVICE_ID_3COM_3CRDAG675 0x0013 /* 3CRDAG675 (Atheros AR5212) */
51 #define PCI_DEVICE_ID_3COM_2_3CRPAG175 0x0013 /* 3CRPAG175 (Atheros AR5212) */
52 #define PCI_DEVICE_ID_ATHEROS_AR5210_AP 0x0207 /* AR5210 (Early) */
53 #define PCI_DEVICE_ID_ATHEROS_AR5212_IBM 0x1014 /* AR5212 (IBM MiniPCI) */
54 #define PCI_DEVICE_ID_ATHEROS_AR5210_DEFAULT 0x1107 /* AR5210 (no eeprom) */
55 #define PCI_DEVICE_ID_ATHEROS_AR5212_DEFAULT 0x1113 /* AR5212 (no eeprom) */
56 #define PCI_DEVICE_ID_ATHEROS_AR5211_DEFAULT 0x1112 /* AR5211 (no eeprom) */
57 #define PCI_DEVICE_ID_ATHEROS_AR5212_FPGA 0xf013 /* AR5212 (emulation board) */
58 #define PCI_DEVICE_ID_ATHEROS_AR5211_LEGACY 0xff12 /* AR5211 (emulation board) */
59 #define PCI_DEVICE_ID_ATHEROS_AR5211_FPGA11B 0xf11b /* AR5211 (emulation board) */
60 #define PCI_DEVICE_ID_ATHEROS_AR5312_REV2 0x0052 /* AR5312 WMAC (AP31) */
61 #define PCI_DEVICE_ID_ATHEROS_AR5312_REV7 0x0057 /* AR5312 WMAC (AP30-040) */
62 #define PCI_DEVICE_ID_ATHEROS_AR5312_REV8 0x0058 /* AR5312 WMAC (AP43-030) */
63 #define PCI_DEVICE_ID_ATHEROS_AR5212_0014 0x0014 /* AR5212 compatible */
64 #define PCI_DEVICE_ID_ATHEROS_AR5212_0015 0x0015 /* AR5212 compatible */
65 #define PCI_DEVICE_ID_ATHEROS_AR5212_0016 0x0016 /* AR5212 compatible */
66 #define PCI_DEVICE_ID_ATHEROS_AR5212_0017 0x0017 /* AR5212 compatible */
67 #define PCI_DEVICE_ID_ATHEROS_AR5212_0018 0x0018 /* AR5212 compatible */
68 #define PCI_DEVICE_ID_ATHEROS_AR5212_0019 0x0019 /* AR5212 compatible */
69 #define PCI_DEVICE_ID_ATHEROS_AR2413 0x001a /* AR2413 (Griffin-lite) */
70 #define PCI_DEVICE_ID_ATHEROS_AR5413 0x001b /* AR5413 (Eagle) */
71 #define PCI_DEVICE_ID_ATHEROS_AR5424 0x001c /* AR5424 (Condor PCI-E) */
72 #define PCI_DEVICE_ID_ATHEROS_AR5416 0x0023 /* AR5416 */
73 #define PCI_DEVICE_ID_ATHEROS_AR5418 0x0024 /* AR5418 */
75 /****************************\
76 GENERIC DRIVER DEFINITIONS
77 \****************************/
79 #define ATH5K_PRINTF(fmt, ...) \
80 printk(KERN_WARNING "%s: " fmt, __func__, ##__VA_ARGS__)
82 #define ATH5K_PRINTK(_sc, _level, _fmt, ...) \
83 printk(_level "ath5k %s: " _fmt, \
84 ((_sc) && (_sc)->hw) ? wiphy_name((_sc)->hw->wiphy) : "", \
87 #define ATH5K_PRINTK_LIMIT(_sc, _level, _fmt, ...) do { \
88 if (net_ratelimit()) \
89 ATH5K_PRINTK(_sc, _level, _fmt, ##__VA_ARGS__); \
92 #define ATH5K_INFO(_sc, _fmt, ...) \
93 ATH5K_PRINTK(_sc, KERN_INFO, _fmt, ##__VA_ARGS__)
95 #define ATH5K_WARN(_sc, _fmt, ...) \
96 ATH5K_PRINTK_LIMIT(_sc, KERN_WARNING, _fmt, ##__VA_ARGS__)
98 #define ATH5K_ERR(_sc, _fmt, ...) \
99 ATH5K_PRINTK_LIMIT(_sc, KERN_ERR, _fmt, ##__VA_ARGS__)
102 * AR5K REGISTER ACCESS
105 /* Some macros to read/write fields */
107 /* First shift, then mask */
108 #define AR5K_REG_SM(_val, _flags) \
109 (((_val) << _flags##_S) & (_flags))
111 /* First mask, then shift */
112 #define AR5K_REG_MS(_val, _flags) \
113 (((_val) & (_flags)) >> _flags##_S)
115 /* Some registers can hold multiple values of interest. For this
116 * reason when we want to write to these registers we must first
117 * retrieve the values which we do not want to clear (lets call this
118 * old_data) and then set the register with this and our new_value:
119 * ( old_data | new_value) */
120 #define AR5K_REG_WRITE_BITS(ah, _reg, _flags, _val) \
121 ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, _reg) & ~(_flags)) | \
122 (((_val) << _flags##_S) & (_flags)), _reg)
124 #define AR5K_REG_MASKED_BITS(ah, _reg, _flags, _mask) \
125 ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, _reg) & \
126 (_mask)) | (_flags), _reg)
128 #define AR5K_REG_ENABLE_BITS(ah, _reg, _flags) \
129 ath5k_hw_reg_write(ah, ath5k_hw_reg_read(ah, _reg) | (_flags), _reg)
131 #define AR5K_REG_DISABLE_BITS(ah, _reg, _flags) \
132 ath5k_hw_reg_write(ah, ath5k_hw_reg_read(ah, _reg) & ~(_flags), _reg)
134 /* Access to PHY registers */
135 #define AR5K_PHY_READ(ah, _reg) \
136 ath5k_hw_reg_read(ah, (ah)->ah_phy + ((_reg) << 2))
138 #define AR5K_PHY_WRITE(ah, _reg, _val) \
139 ath5k_hw_reg_write(ah, _val, (ah)->ah_phy + ((_reg) << 2))
141 /* Access QCU registers per queue */
142 #define AR5K_REG_READ_Q(ah, _reg, _queue) \
143 (ath5k_hw_reg_read(ah, _reg) & (1 << _queue)) \
145 #define AR5K_REG_WRITE_Q(ah, _reg, _queue) \
146 ath5k_hw_reg_write(ah, (1 << _queue), _reg)
148 #define AR5K_Q_ENABLE_BITS(_reg, _queue) do { \
149 _reg |= 1 << _queue; \
152 #define AR5K_Q_DISABLE_BITS(_reg, _queue) do { \
153 _reg &= ~(1 << _queue); \
156 /* Used while writing initvals */
157 #define AR5K_REG_WAIT(_i) do { \
163 * Some tunable values (these should be changeable by the user)
164 * TODO: Make use of them and add more options OR use debug/configfs
166 #define AR5K_TUNE_DMA_BEACON_RESP 2
167 #define AR5K_TUNE_SW_BEACON_RESP 10
168 #define AR5K_TUNE_ADDITIONAL_SWBA_BACKOFF 0
169 #define AR5K_TUNE_RADAR_ALERT false
170 #define AR5K_TUNE_MIN_TX_FIFO_THRES 1
171 #define AR5K_TUNE_MAX_TX_FIFO_THRES ((IEEE80211_MAX_FRAME_LEN / 64) + 1)
172 #define AR5K_TUNE_REGISTER_TIMEOUT 20000
173 /* Register for RSSI threshold has a mask of 0xff, so 255 seems to
174 * be the max value. */
175 #define AR5K_TUNE_RSSI_THRES 129
176 /* This must be set when setting the RSSI threshold otherwise it can
177 * prevent a reset. If AR5K_RSSI_THR is read after writing to it
178 * the BMISS_THRES will be seen as 0, seems hardware doesn't keep
179 * track of it. Max value depends on hardware. For AR5210 this is just 7.
180 * For AR5211+ this seems to be up to 255. */
181 #define AR5K_TUNE_BMISS_THRES 7
182 #define AR5K_TUNE_REGISTER_DWELL_TIME 20000
183 #define AR5K_TUNE_BEACON_INTERVAL 100
184 #define AR5K_TUNE_AIFS 2
185 #define AR5K_TUNE_AIFS_11B 2
186 #define AR5K_TUNE_AIFS_XR 0
187 #define AR5K_TUNE_CWMIN 15
188 #define AR5K_TUNE_CWMIN_11B 31
189 #define AR5K_TUNE_CWMIN_XR 3
190 #define AR5K_TUNE_CWMAX 1023
191 #define AR5K_TUNE_CWMAX_11B 1023
192 #define AR5K_TUNE_CWMAX_XR 7
193 #define AR5K_TUNE_NOISE_FLOOR -72
194 #define AR5K_TUNE_CCA_MAX_GOOD_VALUE -95
195 #define AR5K_TUNE_MAX_TXPOWER 63
196 #define AR5K_TUNE_DEFAULT_TXPOWER 25
197 #define AR5K_TUNE_TPC_TXPOWER false
198 #define ATH5K_TUNE_CALIBRATION_INTERVAL_FULL 10000 /* 10 sec */
199 #define ATH5K_TUNE_CALIBRATION_INTERVAL_ANI 1000 /* 1 sec */
200 #define ATH5K_TUNE_CALIBRATION_INTERVAL_NF 60000 /* 60 sec */
202 #define ATH5K_TX_COMPLETE_POLL_INT 3000 /* 3 sec */
204 #define AR5K_INIT_CARR_SENSE_EN 1
206 /*Swap RX/TX Descriptor for big endian archs*/
207 #if defined(__BIG_ENDIAN)
208 #define AR5K_INIT_CFG ( \
209 AR5K_CFG_SWTD | AR5K_CFG_SWRD \
212 #define AR5K_INIT_CFG 0x00000000
216 #define AR5K_INIT_CYCRSSI_THR1 2
218 /* Tx retry limit defaults from standard */
219 #define AR5K_INIT_RETRY_SHORT 7
220 #define AR5K_INIT_RETRY_LONG 4
223 #define AR5K_INIT_SLOT_TIME_TURBO 6
224 #define AR5K_INIT_SLOT_TIME_DEFAULT 9
225 #define AR5K_INIT_SLOT_TIME_HALF_RATE 13
226 #define AR5K_INIT_SLOT_TIME_QUARTER_RATE 21
227 #define AR5K_INIT_SLOT_TIME_B 20
228 #define AR5K_SLOT_TIME_MAX 0xffff
231 #define AR5K_INIT_SIFS_TURBO 6
232 #define AR5K_INIT_SIFS_DEFAULT_BG 10
233 #define AR5K_INIT_SIFS_DEFAULT_A 16
234 #define AR5K_INIT_SIFS_HALF_RATE 32
235 #define AR5K_INIT_SIFS_QUARTER_RATE 64
237 /* Used to calculate tx time for non 5/10/40MHz
239 /* It's preamble time + signal time (16 + 4) */
240 #define AR5K_INIT_OFDM_PREAMPLE_TIME 20
241 /* Preamble time for 40MHz (turbo) operation (min ?) */
242 #define AR5K_INIT_OFDM_PREAMBLE_TIME_MIN 14
243 #define AR5K_INIT_OFDM_SYMBOL_TIME 4
244 #define AR5K_INIT_OFDM_PLCP_BITS 22
246 /* Rx latency for 5 and 10MHz operation (max ?) */
247 #define AR5K_INIT_RX_LAT_MAX 63
248 /* Tx latencies from initvals (5212 only but no problem
249 * because we only tweak them on 5212) */
250 #define AR5K_INIT_TX_LAT_A 54
251 #define AR5K_INIT_TX_LAT_BG 384
252 /* Tx latency for 40MHz (turbo) operation (min ?) */
253 #define AR5K_INIT_TX_LAT_MIN 32
254 /* Default Tx/Rx latencies (same for 5211)*/
255 #define AR5K_INIT_TX_LATENCY_5210 54
256 #define AR5K_INIT_RX_LATENCY_5210 29
258 /* Tx frame to Tx data start delay */
259 #define AR5K_INIT_TXF2TXD_START_DEFAULT 14
260 #define AR5K_INIT_TXF2TXD_START_DELAY_10MHZ 12
261 #define AR5K_INIT_TXF2TXD_START_DELAY_5MHZ 13
263 /* We need to increase PHY switch and agc settling time
265 #define AR5K_SWITCH_SETTLING 5760
266 #define AR5K_SWITCH_SETTLING_TURBO 7168
268 #define AR5K_AGC_SETTLING 28
269 /* 38 on 5210 but shouldn't matter */
270 #define AR5K_AGC_SETTLING_TURBO 37
273 /* GENERIC CHIPSET DEFINITIONS */
295 * Common silicon revision/version values
298 enum ath5k_srev_type {
303 struct ath5k_srev_name {
305 enum ath5k_srev_type sr_type;
309 #define AR5K_SREV_UNKNOWN 0xffff
311 #define AR5K_SREV_AR5210 0x00 /* Crete */
312 #define AR5K_SREV_AR5311 0x10 /* Maui 1 */
313 #define AR5K_SREV_AR5311A 0x20 /* Maui 2 */
314 #define AR5K_SREV_AR5311B 0x30 /* Spirit */
315 #define AR5K_SREV_AR5211 0x40 /* Oahu */
316 #define AR5K_SREV_AR5212 0x50 /* Venice */
317 #define AR5K_SREV_AR5312_R2 0x52 /* AP31 */
318 #define AR5K_SREV_AR5212_V4 0x54 /* ??? */
319 #define AR5K_SREV_AR5213 0x55 /* ??? */
320 #define AR5K_SREV_AR5312_R7 0x57 /* AP30 */
321 #define AR5K_SREV_AR2313_R8 0x58 /* AP43 */
322 #define AR5K_SREV_AR5213A 0x59 /* Hainan */
323 #define AR5K_SREV_AR2413 0x78 /* Griffin lite */
324 #define AR5K_SREV_AR2414 0x70 /* Griffin */
325 #define AR5K_SREV_AR2315_R6 0x86 /* AP51-Light */
326 #define AR5K_SREV_AR2315_R7 0x87 /* AP51-Full */
327 #define AR5K_SREV_AR5424 0x90 /* Condor */
328 #define AR5K_SREV_AR2317_R1 0x90 /* AP61-Light */
329 #define AR5K_SREV_AR2317_R2 0x91 /* AP61-Full */
330 #define AR5K_SREV_AR5413 0xa4 /* Eagle lite */
331 #define AR5K_SREV_AR5414 0xa0 /* Eagle */
332 #define AR5K_SREV_AR2415 0xb0 /* Talon */
333 #define AR5K_SREV_AR5416 0xc0 /* PCI-E */
334 #define AR5K_SREV_AR5418 0xca /* PCI-E */
335 #define AR5K_SREV_AR2425 0xe0 /* Swan */
336 #define AR5K_SREV_AR2417 0xf0 /* Nala */
338 #define AR5K_SREV_RAD_5110 0x00
339 #define AR5K_SREV_RAD_5111 0x10
340 #define AR5K_SREV_RAD_5111A 0x15
341 #define AR5K_SREV_RAD_2111 0x20
342 #define AR5K_SREV_RAD_5112 0x30
343 #define AR5K_SREV_RAD_5112A 0x35
344 #define AR5K_SREV_RAD_5112B 0x36
345 #define AR5K_SREV_RAD_2112 0x40
346 #define AR5K_SREV_RAD_2112A 0x45
347 #define AR5K_SREV_RAD_2112B 0x46
348 #define AR5K_SREV_RAD_2413 0x50
349 #define AR5K_SREV_RAD_5413 0x60
350 #define AR5K_SREV_RAD_2316 0x70 /* Cobra SoC */
351 #define AR5K_SREV_RAD_2317 0x80
352 #define AR5K_SREV_RAD_5424 0xa0 /* Mostly same as 5413 */
353 #define AR5K_SREV_RAD_2425 0xa2
354 #define AR5K_SREV_RAD_5133 0xc0
356 #define AR5K_SREV_PHY_5211 0x30
357 #define AR5K_SREV_PHY_5212 0x41
358 #define AR5K_SREV_PHY_5212A 0x42
359 #define AR5K_SREV_PHY_5212B 0x43
360 #define AR5K_SREV_PHY_2413 0x45
361 #define AR5K_SREV_PHY_5413 0x61
362 #define AR5K_SREV_PHY_2425 0x70
364 /* TODO add support to mac80211 for vendor-specific rates and modes */
367 * Some of this information is based on Documentation from:
369 * http://madwifi-project.org/wiki/ChipsetFeatures/SuperAG
371 * Modulation for Atheros' eXtended Range - range enhancing extension that is
372 * supposed to double the distance an Atheros client device can keep a
373 * connection with an Atheros access point. This is achieved by increasing
374 * the receiver sensitivity up to, -105dBm, which is about 20dB above what
375 * the 802.11 specifications demand. In addition, new (proprietary) data rates
376 * are introduced: 3, 2, 1, 0.5 and 0.25 MBit/s.
378 * Please note that can you either use XR or TURBO but you cannot use both,
379 * they are exclusive.
382 #define MODULATION_XR 0x00000200
384 * Modulation for Atheros' Turbo G and Turbo A, its supposed to provide a
385 * throughput transmission speed up to 40Mbit/s-60Mbit/s at a 108Mbit/s
386 * signaling rate achieved through the bonding of two 54Mbit/s 802.11g
387 * channels. To use this feature your Access Point must also support it.
388 * There is also a distinction between "static" and "dynamic" turbo modes:
390 * - Static: is the dumb version: devices set to this mode stick to it until
391 * the mode is turned off.
392 * - Dynamic: is the intelligent version, the network decides itself if it
393 * is ok to use turbo. As soon as traffic is detected on adjacent channels
394 * (which would get used in turbo mode), or when a non-turbo station joins
395 * the network, turbo mode won't be used until the situation changes again.
396 * Dynamic mode is achieved by Atheros' Adaptive Radio (AR) feature which
397 * monitors the used radio band in order to decide whether turbo mode may
400 * This article claims Super G sticks to bonding of channels 5 and 6 for
403 * http://www.pcworld.com/article/id,113428-page,1/article.html
405 * The channel bonding seems to be driver specific though. In addition to
406 * deciding what channels will be used, these "Turbo" modes are accomplished
407 * by also enabling the following features:
409 * - Bursting: allows multiple frames to be sent at once, rather than pausing
410 * after each frame. Bursting is a standards-compliant feature that can be
411 * used with any Access Point.
412 * - Fast frames: increases the amount of information that can be sent per
413 * frame, also resulting in a reduction of transmission overhead. It is a
414 * proprietary feature that needs to be supported by the Access Point.
415 * - Compression: data frames are compressed in real time using a Lempel Ziv
416 * algorithm. This is done transparently. Once this feature is enabled,
417 * compression and decompression takes place inside the chipset, without
418 * putting additional load on the host CPU.
421 #define MODULATION_TURBO 0x00000080
423 enum ath5k_driver_mode {
431 enum ath5k_ant_mode {
432 AR5K_ANTMODE_DEFAULT = 0, /* default antenna setup */
433 AR5K_ANTMODE_FIXED_A = 1, /* only antenna A is present */
434 AR5K_ANTMODE_FIXED_B = 2, /* only antenna B is present */
435 AR5K_ANTMODE_SINGLE_AP = 3, /* sta locked on a single ap */
436 AR5K_ANTMODE_SECTOR_AP = 4, /* AP with tx antenna set on tx desc */
437 AR5K_ANTMODE_SECTOR_STA = 5, /* STA with tx antenna set on tx desc */
438 AR5K_ANTMODE_DEBUG = 6, /* Debug mode -A -> Rx, B-> Tx- */
443 AR5K_BWMODE_DEFAULT = 0, /* 20MHz, default operation */
444 AR5K_BWMODE_5MHZ = 1, /* Quarter rate */
445 AR5K_BWMODE_10MHZ = 2, /* Half rate */
446 AR5K_BWMODE_40MHZ = 3 /* Turbo */
454 * TX Status descriptor
456 struct ath5k_tx_status {
468 #define AR5K_TXSTAT_ALTRATE 0x80
469 #define AR5K_TXERR_XRETRY 0x01
470 #define AR5K_TXERR_FILT 0x02
471 #define AR5K_TXERR_FIFO 0x04
474 * enum ath5k_tx_queue - Queue types used to classify tx queues.
475 * @AR5K_TX_QUEUE_INACTIVE: q is unused -- see ath5k_hw_release_tx_queue
476 * @AR5K_TX_QUEUE_DATA: A normal data queue
477 * @AR5K_TX_QUEUE_XR_DATA: An XR-data queue
478 * @AR5K_TX_QUEUE_BEACON: The beacon queue
479 * @AR5K_TX_QUEUE_CAB: The after-beacon queue
480 * @AR5K_TX_QUEUE_UAPSD: Unscheduled Automatic Power Save Delivery queue
482 enum ath5k_tx_queue {
483 AR5K_TX_QUEUE_INACTIVE = 0,
485 AR5K_TX_QUEUE_XR_DATA,
486 AR5K_TX_QUEUE_BEACON,
491 #define AR5K_NUM_TX_QUEUES 10
492 #define AR5K_NUM_TX_QUEUES_NOQCU 2
495 * Queue syb-types to classify normal data queues.
496 * These are the 4 Access Categories as defined in
497 * WME spec. 0 is the lowest priority and 4 is the
498 * highest. Normal data that hasn't been classified
499 * goes to the Best Effort AC.
501 enum ath5k_tx_queue_subtype {
502 AR5K_WME_AC_BK = 0, /*Background traffic*/
503 AR5K_WME_AC_BE, /*Best-effort (normal) traffic*/
504 AR5K_WME_AC_VI, /*Video traffic*/
505 AR5K_WME_AC_VO, /*Voice traffic*/
509 * Queue ID numbers as returned by the hw functions, each number
510 * represents a hw queue. If hw does not support hw queues
511 * (eg 5210) all data goes in one queue. These match
512 * d80211 definitions (net80211/MadWiFi don't use them).
514 enum ath5k_tx_queue_id {
515 AR5K_TX_QUEUE_ID_NOQCU_DATA = 0,
516 AR5K_TX_QUEUE_ID_NOQCU_BEACON = 1,
517 AR5K_TX_QUEUE_ID_DATA_MIN = 0, /*IEEE80211_TX_QUEUE_DATA0*/
518 AR5K_TX_QUEUE_ID_DATA_MAX = 3, /*IEEE80211_TX_QUEUE_DATA3*/
519 AR5K_TX_QUEUE_ID_DATA_SVP = 5, /*IEEE80211_TX_QUEUE_SVP - Spectralink Voice Protocol*/
520 AR5K_TX_QUEUE_ID_CAB = 6, /*IEEE80211_TX_QUEUE_AFTER_BEACON*/
521 AR5K_TX_QUEUE_ID_BEACON = 7, /*IEEE80211_TX_QUEUE_BEACON*/
522 AR5K_TX_QUEUE_ID_UAPSD = 8,
523 AR5K_TX_QUEUE_ID_XR_DATA = 9,
527 * Flags to set hw queue's parameters...
529 #define AR5K_TXQ_FLAG_TXOKINT_ENABLE 0x0001 /* Enable TXOK interrupt */
530 #define AR5K_TXQ_FLAG_TXERRINT_ENABLE 0x0002 /* Enable TXERR interrupt */
531 #define AR5K_TXQ_FLAG_TXEOLINT_ENABLE 0x0004 /* Enable TXEOL interrupt -not used- */
532 #define AR5K_TXQ_FLAG_TXDESCINT_ENABLE 0x0008 /* Enable TXDESC interrupt -not used- */
533 #define AR5K_TXQ_FLAG_TXURNINT_ENABLE 0x0010 /* Enable TXURN interrupt */
534 #define AR5K_TXQ_FLAG_CBRORNINT_ENABLE 0x0020 /* Enable CBRORN interrupt */
535 #define AR5K_TXQ_FLAG_CBRURNINT_ENABLE 0x0040 /* Enable CBRURN interrupt */
536 #define AR5K_TXQ_FLAG_QTRIGINT_ENABLE 0x0080 /* Enable QTRIG interrupt */
537 #define AR5K_TXQ_FLAG_TXNOFRMINT_ENABLE 0x0100 /* Enable TXNOFRM interrupt */
538 #define AR5K_TXQ_FLAG_BACKOFF_DISABLE 0x0200 /* Disable random post-backoff */
539 #define AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE 0x0300 /* Enable ready time expiry policy (?)*/
540 #define AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE 0x0800 /* Enable backoff while bursting */
541 #define AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS 0x1000 /* Disable backoff while bursting */
542 #define AR5K_TXQ_FLAG_COMPRESSION_ENABLE 0x2000 /* Enable hw compression -not implemented-*/
545 * Data transmit queue state. One of these exists for each
546 * hardware transmit queue. Packets sent to us from above
547 * are assigned to queues based on their priority. Not all
548 * devices support a complete set of hardware transmit queues.
549 * For those devices the array sc_ac2q will map multiple
550 * priorities to fewer hardware queues (typically all to one
554 unsigned int qnum; /* hardware q number */
555 u32 *link; /* link ptr in last TX desc */
556 struct list_head q; /* transmit queue */
557 spinlock_t lock; /* lock on q and link */
559 int txq_len; /* number of queued buffers */
560 int txq_max; /* max allowed num of queued buffers */
562 unsigned int txq_stuck; /* informational counter */
566 * A struct to hold tx queue's parameters
568 struct ath5k_txq_info {
569 enum ath5k_tx_queue tqi_type;
570 enum ath5k_tx_queue_subtype tqi_subtype;
571 u16 tqi_flags; /* Tx queue flags (see above) */
572 u8 tqi_aifs; /* Arbitrated Interframe Space */
573 u16 tqi_cw_min; /* Minimum Contention Window */
574 u16 tqi_cw_max; /* Maximum Contention Window */
575 u32 tqi_cbr_period; /* Constant bit rate period */
576 u32 tqi_cbr_overflow_limit;
578 u32 tqi_ready_time; /* Time queue waits after an event */
582 * Transmit packet types.
583 * used on tx control descriptor
585 enum ath5k_pkt_type {
586 AR5K_PKT_TYPE_NORMAL = 0,
587 AR5K_PKT_TYPE_ATIM = 1,
588 AR5K_PKT_TYPE_PSPOLL = 2,
589 AR5K_PKT_TYPE_BEACON = 3,
590 AR5K_PKT_TYPE_PROBE_RESP = 4,
591 AR5K_PKT_TYPE_PIFS = 5,
595 * TX power and TPC settings
597 #define AR5K_TXPOWER_OFDM(_r, _v) ( \
598 ((0 & 1) << ((_v) + 6)) | \
599 (((ah->ah_txpower.txp_rates_power_table[(_r)]) & 0x3f) << (_v)) \
602 #define AR5K_TXPOWER_CCK(_r, _v) ( \
603 (ah->ah_txpower.txp_rates_power_table[(_r)] & 0x3f) << (_v) \
607 * DMA size definitions (2^(n+2))
626 * RX Status descriptor
628 struct ath5k_rx_status {
640 #define AR5K_RXERR_CRC 0x01
641 #define AR5K_RXERR_PHY 0x02
642 #define AR5K_RXERR_FIFO 0x04
643 #define AR5K_RXERR_DECRYPT 0x08
644 #define AR5K_RXERR_MIC 0x10
645 #define AR5K_RXKEYIX_INVALID ((u8) -1)
646 #define AR5K_TXKEYIX_INVALID ((u32) -1)
649 /**************************\
650 BEACON TIMERS DEFINITIONS
651 \**************************/
653 #define AR5K_BEACON_PERIOD 0x0000ffff
654 #define AR5K_BEACON_ENA 0x00800000 /*enable beacon xmit*/
655 #define AR5K_BEACON_RESET_TSF 0x01000000 /*force a TSF reset*/
659 * TSF to TU conversion:
661 * TSF is a 64bit value in usec (microseconds).
662 * TU is a 32bit value and defined by IEEE802.11 (page 6) as "A measurement of
663 * time equal to 1024 usec", so it's roughly milliseconds (usec / 1024).
665 #define TSF_TO_TU(_tsf) (u32)((_tsf) >> 10)
668 /*******************************\
669 GAIN OPTIMIZATION DEFINITIONS
670 \*******************************/
673 AR5K_RFGAIN_INACTIVE = 0,
675 AR5K_RFGAIN_READ_REQUESTED,
676 AR5K_RFGAIN_NEED_CHANGE,
689 /********************\
691 \********************/
693 #define AR5K_SLOT_TIME_9 396
694 #define AR5K_SLOT_TIME_20 880
695 #define AR5K_SLOT_TIME_MAX 0xffff
698 #define CHANNEL_CW_INT 0x0008 /* Contention Window interference detected */
699 #define CHANNEL_CCK 0x0020 /* CCK channel */
700 #define CHANNEL_OFDM 0x0040 /* OFDM channel */
701 #define CHANNEL_2GHZ 0x0080 /* 2GHz channel. */
702 #define CHANNEL_5GHZ 0x0100 /* 5GHz channel */
703 #define CHANNEL_PASSIVE 0x0200 /* Only passive scan allowed */
704 #define CHANNEL_DYN 0x0400 /* Dynamic CCK-OFDM channel (for g operation) */
705 #define CHANNEL_XR 0x0800 /* XR channel */
707 #define CHANNEL_A (CHANNEL_5GHZ | CHANNEL_OFDM)
708 #define CHANNEL_B (CHANNEL_2GHZ | CHANNEL_CCK)
709 #define CHANNEL_G (CHANNEL_2GHZ | CHANNEL_OFDM)
710 #define CHANNEL_X (CHANNEL_5GHZ | CHANNEL_OFDM | CHANNEL_XR)
712 #define CHANNEL_ALL (CHANNEL_OFDM | CHANNEL_CCK | \
713 CHANNEL_2GHZ | CHANNEL_5GHZ)
715 #define CHANNEL_MODES CHANNEL_ALL
718 * Used internally for ath5k_hw_reset_tx_queue().
719 * Also see struct struct ieee80211_channel.
721 #define IS_CHAN_XR(_c) ((_c->hw_value & CHANNEL_XR) != 0)
722 #define IS_CHAN_B(_c) ((_c->hw_value & CHANNEL_B) != 0)
725 * The following structure is used to map 2GHz channels to
726 * 5GHz Atheros channels.
729 struct ath5k_athchan_2ghz {
740 * Seems the ar5xxx hardware supports up to 32 rates, indexed by 1-32.
742 * The rate code is used to get the RX rate or set the TX rate on the
743 * hardware descriptors. It is also used for internal modulation control
746 * This is the hardware rate map we are aware of:
748 * rate_code 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08
749 * rate_kbps 3000 1000 ? ? ? 2000 500 48000
751 * rate_code 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10
752 * rate_kbps 24000 12000 6000 54000 36000 18000 9000 ?
754 * rate_code 17 18 19 20 21 22 23 24
755 * rate_kbps ? ? ? ? ? ? ? 11000
757 * rate_code 25 26 27 28 29 30 31 32
758 * rate_kbps 5500 2000 1000 11000S 5500S 2000S ? ?
760 * "S" indicates CCK rates with short preamble.
762 * AR5211 has different rate codes for CCK (802.11B) rates. It only uses the
763 * lowest 4 bits, so they are the same as below with a 0xF mask.
764 * (0xB, 0xA, 0x9 and 0x8 for 1M, 2M, 5.5M and 11M).
765 * We handle this in ath5k_setup_bands().
767 #define AR5K_MAX_RATES 32
770 #define ATH5K_RATE_CODE_1M 0x1B
771 #define ATH5K_RATE_CODE_2M 0x1A
772 #define ATH5K_RATE_CODE_5_5M 0x19
773 #define ATH5K_RATE_CODE_11M 0x18
775 #define ATH5K_RATE_CODE_6M 0x0B
776 #define ATH5K_RATE_CODE_9M 0x0F
777 #define ATH5K_RATE_CODE_12M 0x0A
778 #define ATH5K_RATE_CODE_18M 0x0E
779 #define ATH5K_RATE_CODE_24M 0x09
780 #define ATH5K_RATE_CODE_36M 0x0D
781 #define ATH5K_RATE_CODE_48M 0x08
782 #define ATH5K_RATE_CODE_54M 0x0C
784 #define ATH5K_RATE_CODE_XR_500K 0x07
785 #define ATH5K_RATE_CODE_XR_1M 0x02
786 #define ATH5K_RATE_CODE_XR_2M 0x06
787 #define ATH5K_RATE_CODE_XR_3M 0x01
789 /* adding this flag to rate_code enables short preamble */
790 #define AR5K_SET_SHORT_PREAMBLE 0x04
796 #define AR5K_KEYCACHE_SIZE 8
797 extern int ath5k_modparam_nohwcrypt;
799 /***********************\
800 HW RELATED DEFINITIONS
801 \***********************/
806 #define AR5K_RSSI_EP_MULTIPLIER (1 << 7)
808 #define AR5K_ASSERT_ENTRY(_e, _s) do { \
814 * Hardware interrupt abstraction
818 * enum ath5k_int - Hardware interrupt masks helpers
820 * @AR5K_INT_RX: mask to identify received frame interrupts, of type
821 * AR5K_ISR_RXOK or AR5K_ISR_RXERR
822 * @AR5K_INT_RXDESC: Request RX descriptor/Read RX descriptor (?)
823 * @AR5K_INT_RXNOFRM: No frame received (?)
824 * @AR5K_INT_RXEOL: received End Of List for VEOL (Virtual End Of List). The
825 * Queue Control Unit (QCU) signals an EOL interrupt only if a descriptor's
826 * LinkPtr is NULL. For more details, refer to:
827 * http://www.freepatentsonline.com/20030225739.html
828 * @AR5K_INT_RXORN: Indicates we got RX overrun (eg. no more descriptors).
829 * Note that Rx overrun is not always fatal, on some chips we can continue
830 * operation without resetting the card, that's why int_fatal is not
831 * common for all chips.
832 * @AR5K_INT_TX: mask to identify received frame interrupts, of type
833 * AR5K_ISR_TXOK or AR5K_ISR_TXERR
834 * @AR5K_INT_TXDESC: Request TX descriptor/Read TX status descriptor (?)
835 * @AR5K_INT_TXURN: received when we should increase the TX trigger threshold
836 * We currently do increments on interrupt by
837 * (AR5K_TUNE_MAX_TX_FIFO_THRES - current_trigger_level) / 2
838 * @AR5K_INT_MIB: Indicates the either Management Information Base counters or
839 * one of the PHY error counters reached the maximum value and should be
841 * @AR5K_INT_RXPHY: RX PHY Error
842 * @AR5K_INT_RXKCM: RX Key cache miss
843 * @AR5K_INT_SWBA: SoftWare Beacon Alert - indicates its time to send a
844 * beacon that must be handled in software. The alternative is if you
845 * have VEOL support, in that case you let the hardware deal with things.
846 * @AR5K_INT_BMISS: If in STA mode this indicates we have stopped seeing
847 * beacons from the AP have associated with, we should probably try to
848 * reassociate. When in IBSS mode this might mean we have not received
849 * any beacons from any local stations. Note that every station in an
850 * IBSS schedules to send beacons at the Target Beacon Transmission Time
851 * (TBTT) with a random backoff.
852 * @AR5K_INT_BNR: Beacon Not Ready interrupt - ??
853 * @AR5K_INT_GPIO: GPIO interrupt is used for RF Kill, disabled for now
854 * until properly handled
855 * @AR5K_INT_FATAL: Fatal errors were encountered, typically caused by DMA
856 * errors. These types of errors we can enable seem to be of type
857 * AR5K_SIMR2_MCABT, AR5K_SIMR2_SSERR and AR5K_SIMR2_DPERR.
858 * @AR5K_INT_GLOBAL: Used to clear and set the IER
859 * @AR5K_INT_NOCARD: signals the card has been removed
860 * @AR5K_INT_COMMON: common interrupts shared among MACs with the same
863 * These are mapped to take advantage of some common bits
864 * between the MACs, to be able to set intr properties
865 * easier. Some of them are not used yet inside hw.c. Most map
866 * to the respective hw interrupt value as they are common among different
870 AR5K_INT_RXOK = 0x00000001,
871 AR5K_INT_RXDESC = 0x00000002,
872 AR5K_INT_RXERR = 0x00000004,
873 AR5K_INT_RXNOFRM = 0x00000008,
874 AR5K_INT_RXEOL = 0x00000010,
875 AR5K_INT_RXORN = 0x00000020,
876 AR5K_INT_TXOK = 0x00000040,
877 AR5K_INT_TXDESC = 0x00000080,
878 AR5K_INT_TXERR = 0x00000100,
879 AR5K_INT_TXNOFRM = 0x00000200,
880 AR5K_INT_TXEOL = 0x00000400,
881 AR5K_INT_TXURN = 0x00000800,
882 AR5K_INT_MIB = 0x00001000,
883 AR5K_INT_SWI = 0x00002000,
884 AR5K_INT_RXPHY = 0x00004000,
885 AR5K_INT_RXKCM = 0x00008000,
886 AR5K_INT_SWBA = 0x00010000,
887 AR5K_INT_BRSSI = 0x00020000,
888 AR5K_INT_BMISS = 0x00040000,
889 AR5K_INT_FATAL = 0x00080000, /* Non common */
890 AR5K_INT_BNR = 0x00100000, /* Non common */
891 AR5K_INT_TIM = 0x00200000, /* Non common */
892 AR5K_INT_DTIM = 0x00400000, /* Non common */
893 AR5K_INT_DTIM_SYNC = 0x00800000, /* Non common */
894 AR5K_INT_GPIO = 0x01000000,
895 AR5K_INT_BCN_TIMEOUT = 0x02000000, /* Non common */
896 AR5K_INT_CAB_TIMEOUT = 0x04000000, /* Non common */
897 AR5K_INT_RX_DOPPLER = 0x08000000, /* Non common */
898 AR5K_INT_QCBRORN = 0x10000000, /* Non common */
899 AR5K_INT_QCBRURN = 0x20000000, /* Non common */
900 AR5K_INT_QTRIG = 0x40000000, /* Non common */
901 AR5K_INT_GLOBAL = 0x80000000,
903 AR5K_INT_TX_ALL = AR5K_INT_TXOK
909 AR5K_INT_RX_ALL = AR5K_INT_RXOK
916 AR5K_INT_COMMON = AR5K_INT_RXOK
938 AR5K_INT_NOCARD = 0xffffffff
941 /* mask which calibration is active at the moment */
942 enum ath5k_calibration_mask {
943 AR5K_CALIBRATION_FULL = 0x01,
944 AR5K_CALIBRATION_SHORT = 0x02,
945 AR5K_CALIBRATION_ANI = 0x04,
951 enum ath5k_power_mode {
952 AR5K_PM_UNDEFINED = 0,
956 AR5K_PM_NETWORK_SLEEP,
960 * These match net80211 definitions (not used in
962 * TODO: Clean this up
964 #define AR5K_LED_INIT 0 /*IEEE80211_S_INIT*/
965 #define AR5K_LED_SCAN 1 /*IEEE80211_S_SCAN*/
966 #define AR5K_LED_AUTH 2 /*IEEE80211_S_AUTH*/
967 #define AR5K_LED_ASSOC 3 /*IEEE80211_S_ASSOC*/
968 #define AR5K_LED_RUN 4 /*IEEE80211_S_RUN*/
970 /* GPIO-controlled software LED */
971 #define AR5K_SOFTLED_PIN 0
972 #define AR5K_SOFTLED_ON 0
973 #define AR5K_SOFTLED_OFF 1
976 /* XXX: we *may* move cap_range stuff to struct wiphy */
977 struct ath5k_capabilities {
979 * Supported PHY modes
980 * (ie. CHANNEL_A, CHANNEL_B, ...)
982 DECLARE_BITMAP(cap_mode, AR5K_MODE_MAX);
985 * Frequency range (without regulation restrictions)
995 * Values stored in the EEPROM (some of them...)
997 struct ath5k_eeprom_info cap_eeprom;
1006 bool cap_has_phyerr_counters;
1009 /* size of noise floor history (keep it a power of two) */
1010 #define ATH5K_NF_CAL_HIST_MAX 8
1011 struct ath5k_nfcal_hist {
1012 s16 index; /* current index into nfval */
1013 s16 nfval[ATH5K_NF_CAL_HIST_MAX]; /* last few noise floors */
1017 * struct avg_val - Helper structure for average calculation
1018 * @avg: contains the actual average value
1019 * @avg_weight: is used internally during calculation to prevent rounding errors
1021 struct ath5k_avg_val {
1026 #define ATH5K_LED_MAX_NAME_LEN 31
1029 * State for LED triggers
1032 char name[ATH5K_LED_MAX_NAME_LEN + 1]; /* name of the LED in sysfs */
1033 struct ath5k_hw *ah; /* driver state */
1034 struct led_classdev led_dev; /* led classdev */
1038 struct ath5k_rfkill {
1039 /* GPIO PIN for rfkill */
1041 /* polarity of rfkill GPIO PIN */
1043 /* RFKILL toggle tasklet */
1044 struct tasklet_struct toggleq;
1048 struct ath5k_statistics {
1050 unsigned int antenna_rx[5]; /* frames count per antenna RX */
1051 unsigned int antenna_tx[5]; /* frames count per antenna TX */
1054 unsigned int rx_all_count; /* all RX frames, including errors */
1055 unsigned int tx_all_count; /* all TX frames, including errors */
1056 unsigned int rx_bytes_count; /* all RX bytes, including errored pkts
1057 * and the MAC headers for each packet
1059 unsigned int tx_bytes_count; /* all TX bytes, including errored pkts
1060 * and the MAC headers and padding for
1063 unsigned int rxerr_crc;
1064 unsigned int rxerr_phy;
1065 unsigned int rxerr_phy_code[32];
1066 unsigned int rxerr_fifo;
1067 unsigned int rxerr_decrypt;
1068 unsigned int rxerr_mic;
1069 unsigned int rxerr_proc;
1070 unsigned int rxerr_jumbo;
1071 unsigned int txerr_retry;
1072 unsigned int txerr_fifo;
1073 unsigned int txerr_filt;
1076 unsigned int ack_fail;
1077 unsigned int rts_fail;
1078 unsigned int rts_ok;
1079 unsigned int fcs_error;
1080 unsigned int beacons;
1082 unsigned int mib_intr;
1083 unsigned int rxorn_intr;
1084 unsigned int rxeol_intr;
1091 #define AR5K_MAX_GPIO 10
1092 #define AR5K_MAX_RF_BANKS 8
1095 #define ATH_CHAN_MAX (26 + 26 + 26 + 200 + 200)
1097 #define ATH_CHAN_MAX (14 + 14 + 14 + 252 + 20)
1100 #define ATH_RXBUF 40 /* number of RX buffers */
1101 #define ATH_TXBUF 200 /* number of TX buffers */
1102 #define ATH_BCBUF 4 /* number of beacon buffers */
1103 #define ATH5K_TXQ_LEN_MAX (ATH_TXBUF / 4) /* bufs per queue */
1104 #define ATH5K_TXQ_LEN_LOW (ATH5K_TXQ_LEN_MAX / 2) /* low mark */
1106 /* Driver state associated with an instance of a device */
1108 struct ath_common common;
1110 struct pci_dev *pdev;
1111 struct device *dev; /* for dma mapping */
1114 void __iomem *iobase; /* address of the device */
1115 struct mutex lock; /* dev-level lock */
1116 struct ieee80211_hw *hw; /* IEEE 802.11 common */
1117 struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS];
1118 struct ieee80211_channel channels[ATH_CHAN_MAX];
1119 struct ieee80211_rate rates[IEEE80211_NUM_BANDS][AR5K_MAX_RATES];
1120 s8 rate_idx[IEEE80211_NUM_BANDS][AR5K_MAX_RATES];
1121 enum nl80211_iftype opmode;
1123 #ifdef CONFIG_ATH5K_DEBUG
1124 struct ath5k_dbg_info debug; /* debug info */
1125 #endif /* CONFIG_ATH5K_DEBUG */
1127 struct ath5k_buf *bufptr; /* allocated buffer ptr */
1128 struct ath5k_desc *desc; /* TX/RX descriptors */
1129 dma_addr_t desc_daddr; /* DMA (physical) address */
1130 size_t desc_len; /* size of TX/RX descriptors */
1132 DECLARE_BITMAP(status, 6);
1133 #define ATH_STAT_INVALID 0 /* disable hardware accesses */
1134 #define ATH_STAT_MRRETRY 1 /* multi-rate retry support */
1135 #define ATH_STAT_PROMISC 2
1136 #define ATH_STAT_LEDSOFT 3 /* enable LED gpio status */
1137 #define ATH_STAT_STARTED 4 /* opened & irqs enabled */
1138 #define ATH_STAT_2G_DISABLED 5 /* multiband radio without 2G */
1140 unsigned int filter_flags; /* HW flags, AR5K_RX_FILTER_* */
1141 struct ieee80211_channel *curchan; /* current h/w channel */
1145 enum ath5k_int imask; /* interrupt mask copy */
1148 bool rx_pending; /* rx tasklet pending */
1149 bool tx_pending; /* tx tasklet pending */
1151 u8 lladdr[ETH_ALEN];
1152 u8 bssidmask[ETH_ALEN];
1154 unsigned int led_pin, /* GPIO pin for driving LED */
1155 led_on; /* pin setting for LED on */
1157 struct work_struct reset_work; /* deferred chip reset */
1159 unsigned int rxbufsize; /* rx size based on mtu */
1160 struct list_head rxbuf; /* receive buffer */
1161 spinlock_t rxbuflock;
1162 u32 *rxlink; /* link ptr in last RX desc */
1163 struct tasklet_struct rxtq; /* rx intr tasklet */
1164 struct ath5k_led rx_led; /* rx led */
1166 struct list_head txbuf; /* transmit buffer */
1167 spinlock_t txbuflock;
1168 unsigned int txbuf_len; /* buf count in txbuf list */
1169 struct ath5k_txq txqs[AR5K_NUM_TX_QUEUES]; /* tx queues */
1170 struct tasklet_struct txtq; /* tx intr tasklet */
1171 struct ath5k_led tx_led; /* tx led */
1173 struct ath5k_rfkill rf_kill;
1175 struct tasklet_struct calib; /* calibration tasklet */
1177 spinlock_t block; /* protects beacon */
1178 struct tasklet_struct beacontq; /* beacon intr tasklet */
1179 struct list_head bcbuf; /* beacon buffer */
1180 struct ieee80211_vif *bslot[ATH_BCBUF];
1183 unsigned int bhalq, /* SW q for outgoing beacons */
1184 bmisscount, /* missed beacon transmits */
1185 bintval, /* beacon interval in TU */
1187 unsigned int nexttbtt; /* next beacon time in TU */
1188 struct ath5k_txq *cabq; /* content after beacon */
1190 int power_level; /* Requested tx power in dBm */
1191 bool assoc; /* associate state */
1192 bool enable_beacon; /* true if beacons are on */
1194 struct ath5k_statistics stats;
1196 struct ath5k_ani_state ani_state;
1197 struct tasklet_struct ani_tasklet; /* ANI calibration */
1199 struct delayed_work tx_complete_work;
1201 struct survey_info survey; /* collected survey info */
1203 enum ath5k_int ah_imr;
1205 struct ieee80211_channel *ah_current_channel;
1206 bool ah_calibration;
1207 bool ah_single_chip;
1209 enum ath5k_version ah_version;
1210 enum ath5k_radio ah_radio;
1214 u16 ah_mac_revision;
1215 u16 ah_phy_revision;
1216 u16 ah_radio_5ghz_revision;
1217 u16 ah_radio_2ghz_revision;
1219 #define ah_modes ah_capabilities.cap_mode
1220 #define ah_ee_version ah_capabilities.cap_eeprom.ee_version
1225 u32 ah_use_32khz_clock;
1227 u8 ah_coverage_class;
1228 bool ah_ack_bitrate_high;
1232 /* Antenna Control */
1233 u32 ah_ant_ctl[AR5K_EEPROM_N_MODES][AR5K_ANT_MAX];
1238 struct ath5k_capabilities ah_capabilities;
1240 struct ath5k_txq_info ah_txq[AR5K_NUM_TX_QUEUES];
1242 u32 ah_txq_imr_txok;
1243 u32 ah_txq_imr_txerr;
1244 u32 ah_txq_imr_txurn;
1245 u32 ah_txq_imr_txdesc;
1246 u32 ah_txq_imr_txeol;
1247 u32 ah_txq_imr_cbrorn;
1248 u32 ah_txq_imr_cbrurn;
1249 u32 ah_txq_imr_qtrig;
1250 u32 ah_txq_imr_nofrm;
1253 size_t ah_rf_banks_size;
1254 size_t ah_rf_regs_count;
1255 struct ath5k_gain ah_gain;
1256 u8 ah_offset[AR5K_MAX_RF_BANKS];
1260 /* Temporary tables used for interpolation */
1261 u8 tmpL[AR5K_EEPROM_N_PD_GAINS]
1262 [AR5K_EEPROM_POWER_TABLE_SIZE];
1263 u8 tmpR[AR5K_EEPROM_N_PD_GAINS]
1264 [AR5K_EEPROM_POWER_TABLE_SIZE];
1265 u8 txp_pd_table[AR5K_EEPROM_POWER_TABLE_SIZE * 2];
1266 u16 txp_rates_power_table[AR5K_MAX_RATES];
1269 /* Values in 0.25dB units */
1273 /* Values in 0.5dB units */
1276 s16 txp_cck_ofdm_gainf_delta;
1277 /* Value in dB units */
1278 s16 txp_cck_ofdm_pwr_delta;
1285 struct ieee80211_channel r_last_channel;
1288 struct ath5k_nfcal_hist ah_nfcal_hist;
1290 /* average beacon RSSI in our BSS (used by ANI) */
1291 struct ewma ah_beacon_rssi_avg;
1293 /* noise floor from last periodic calibration */
1296 /* Calibration timestamp */
1297 unsigned long ah_cal_next_full;
1298 unsigned long ah_cal_next_ani;
1299 unsigned long ah_cal_next_nf;
1301 /* Calibration mask */
1307 int (*ah_setup_tx_desc)(struct ath5k_hw *, struct ath5k_desc *,
1308 unsigned int, unsigned int, int, enum ath5k_pkt_type,
1309 unsigned int, unsigned int, unsigned int, unsigned int,
1310 unsigned int, unsigned int, unsigned int, unsigned int);
1311 int (*ah_proc_tx_desc)(struct ath5k_hw *, struct ath5k_desc *,
1312 struct ath5k_tx_status *);
1313 int (*ah_proc_rx_desc)(struct ath5k_hw *, struct ath5k_desc *,
1314 struct ath5k_rx_status *);
1317 struct ath_bus_ops {
1318 enum ath_bus_type ath_bus_type;
1319 void (*read_cachesize)(struct ath_common *common, int *csz);
1320 bool (*eeprom_read)(struct ath_common *common, u32 off, u16 *data);
1321 int (*eeprom_read_mac)(struct ath5k_hw *ah, u8 *mac);
1327 extern const struct ieee80211_ops ath5k_hw_ops;
1329 /* Initialization and detach functions */
1330 int ath5k_init_softc(struct ath5k_hw *ah, const struct ath_bus_ops *bus_ops);
1331 void ath5k_deinit_softc(struct ath5k_hw *ah);
1332 int ath5k_hw_init(struct ath5k_hw *ah);
1333 void ath5k_hw_deinit(struct ath5k_hw *ah);
1335 int ath5k_sysfs_register(struct ath5k_hw *ah);
1336 void ath5k_sysfs_unregister(struct ath5k_hw *ah);
1342 void ath5k_set_beacon_filter(struct ieee80211_hw *hw, bool enable);
1343 bool ath5k_any_vif_assoc(struct ath5k_hw *ah);
1344 void ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb,
1345 struct ath5k_txq *txq);
1346 int ath5k_start(struct ieee80211_hw *hw);
1347 void ath5k_stop(struct ieee80211_hw *hw);
1348 void ath5k_mode_setup(struct ath5k_hw *ah, struct ieee80211_vif *vif);
1349 void ath5k_update_bssid_mask_and_opmode(struct ath5k_hw *ah,
1350 struct ieee80211_vif *vif);
1351 int ath5k_chan_set(struct ath5k_hw *ah, struct ieee80211_channel *chan);
1352 void ath5k_beacon_update_timers(struct ath5k_hw *ah, u64 bc_tsf);
1353 int ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif);
1354 void ath5k_beacon_config(struct ath5k_hw *ah);
1355 void ath5k_txbuf_free_skb(struct ath5k_hw *ah, struct ath5k_buf *bf);
1356 void ath5k_rxbuf_free_skb(struct ath5k_hw *ah, struct ath5k_buf *bf);
1358 /*Chip id helper functions */
1359 const char *ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val);
1360 int ath5k_hw_read_srev(struct ath5k_hw *ah);
1363 int ath5k_init_leds(struct ath5k_hw *ah);
1364 void ath5k_led_enable(struct ath5k_hw *ah);
1365 void ath5k_led_off(struct ath5k_hw *ah);
1366 void ath5k_unregister_leds(struct ath5k_hw *ah);
1369 /* Reset Functions */
1370 int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, bool initial);
1371 int ath5k_hw_on_hold(struct ath5k_hw *ah);
1372 int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode,
1373 struct ieee80211_channel *channel, bool fast, bool skip_pcu);
1374 int ath5k_hw_register_timeout(struct ath5k_hw *ah, u32 reg, u32 flag, u32 val,
1376 /* Power management functions */
1379 /* Clock rate related functions */
1380 unsigned int ath5k_hw_htoclock(struct ath5k_hw *ah, unsigned int usec);
1381 unsigned int ath5k_hw_clocktoh(struct ath5k_hw *ah, unsigned int clock);
1382 void ath5k_hw_set_clockrate(struct ath5k_hw *ah);
1385 /* DMA Related Functions */
1386 void ath5k_hw_start_rx_dma(struct ath5k_hw *ah);
1387 u32 ath5k_hw_get_rxdp(struct ath5k_hw *ah);
1388 int ath5k_hw_set_rxdp(struct ath5k_hw *ah, u32 phys_addr);
1389 int ath5k_hw_start_tx_dma(struct ath5k_hw *ah, unsigned int queue);
1390 int ath5k_hw_stop_beacon_queue(struct ath5k_hw *ah, unsigned int queue);
1391 u32 ath5k_hw_get_txdp(struct ath5k_hw *ah, unsigned int queue);
1392 int ath5k_hw_set_txdp(struct ath5k_hw *ah, unsigned int queue,
1394 int ath5k_hw_update_tx_triglevel(struct ath5k_hw *ah, bool increase);
1395 /* Interrupt handling */
1396 bool ath5k_hw_is_intr_pending(struct ath5k_hw *ah);
1397 int ath5k_hw_get_isr(struct ath5k_hw *ah, enum ath5k_int *interrupt_mask);
1398 enum ath5k_int ath5k_hw_set_imr(struct ath5k_hw *ah, enum ath5k_int new_mask);
1399 void ath5k_hw_update_mib_counters(struct ath5k_hw *ah);
1400 /* Init/Stop functions */
1401 void ath5k_hw_dma_init(struct ath5k_hw *ah);
1402 int ath5k_hw_dma_stop(struct ath5k_hw *ah);
1404 /* EEPROM access functions */
1405 int ath5k_eeprom_init(struct ath5k_hw *ah);
1406 void ath5k_eeprom_detach(struct ath5k_hw *ah);
1409 /* Protocol Control Unit Functions */
1411 int ath5k_hw_get_frame_duration(struct ath5k_hw *ah,
1412 int len, struct ieee80211_rate *rate, bool shortpre);
1413 unsigned int ath5k_hw_get_default_slottime(struct ath5k_hw *ah);
1414 unsigned int ath5k_hw_get_default_sifs(struct ath5k_hw *ah);
1415 int ath5k_hw_set_opmode(struct ath5k_hw *ah, enum nl80211_iftype opmode);
1416 void ath5k_hw_set_coverage_class(struct ath5k_hw *ah, u8 coverage_class);
1417 /* RX filter control*/
1418 int ath5k_hw_set_lladdr(struct ath5k_hw *ah, const u8 *mac);
1419 void ath5k_hw_set_bssid(struct ath5k_hw *ah);
1420 void ath5k_hw_set_bssid_mask(struct ath5k_hw *ah, const u8 *mask);
1421 void ath5k_hw_set_mcast_filter(struct ath5k_hw *ah, u32 filter0, u32 filter1);
1422 u32 ath5k_hw_get_rx_filter(struct ath5k_hw *ah);
1423 void ath5k_hw_set_rx_filter(struct ath5k_hw *ah, u32 filter);
1424 /* Receive (DRU) start/stop functions */
1425 void ath5k_hw_start_rx_pcu(struct ath5k_hw *ah);
1426 void ath5k_hw_stop_rx_pcu(struct ath5k_hw *ah);
1427 /* Beacon control functions */
1428 u64 ath5k_hw_get_tsf64(struct ath5k_hw *ah);
1429 void ath5k_hw_set_tsf64(struct ath5k_hw *ah, u64 tsf64);
1430 void ath5k_hw_reset_tsf(struct ath5k_hw *ah);
1431 void ath5k_hw_init_beacon(struct ath5k_hw *ah, u32 next_beacon, u32 interval);
1432 bool ath5k_hw_check_beacon_timers(struct ath5k_hw *ah, int intval);
1434 void ath5k_hw_pcu_init(struct ath5k_hw *ah, enum nl80211_iftype op_mode,
1437 /* Queue Control Unit, DFS Control Unit Functions */
1438 int ath5k_hw_get_tx_queueprops(struct ath5k_hw *ah, int queue,
1439 struct ath5k_txq_info *queue_info);
1440 int ath5k_hw_set_tx_queueprops(struct ath5k_hw *ah, int queue,
1441 const struct ath5k_txq_info *queue_info);
1442 int ath5k_hw_setup_tx_queue(struct ath5k_hw *ah,
1443 enum ath5k_tx_queue queue_type,
1444 struct ath5k_txq_info *queue_info);
1445 void ath5k_hw_set_tx_retry_limits(struct ath5k_hw *ah,
1446 unsigned int queue);
1447 u32 ath5k_hw_num_tx_pending(struct ath5k_hw *ah, unsigned int queue);
1448 void ath5k_hw_release_tx_queue(struct ath5k_hw *ah, unsigned int queue);
1449 int ath5k_hw_reset_tx_queue(struct ath5k_hw *ah, unsigned int queue);
1450 int ath5k_hw_set_ifs_intervals(struct ath5k_hw *ah, unsigned int slot_time);
1452 int ath5k_hw_init_queues(struct ath5k_hw *ah);
1454 /* Hardware Descriptor Functions */
1455 int ath5k_hw_init_desc_functions(struct ath5k_hw *ah);
1456 int ath5k_hw_setup_rx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc,
1457 u32 size, unsigned int flags);
1458 int ath5k_hw_setup_mrr_tx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc,
1459 unsigned int tx_rate1, u_int tx_tries1, u_int tx_rate2,
1460 u_int tx_tries2, unsigned int tx_rate3, u_int tx_tries3);
1463 /* GPIO Functions */
1464 void ath5k_hw_set_ledstate(struct ath5k_hw *ah, unsigned int state);
1465 int ath5k_hw_set_gpio_input(struct ath5k_hw *ah, u32 gpio);
1466 int ath5k_hw_set_gpio_output(struct ath5k_hw *ah, u32 gpio);
1467 u32 ath5k_hw_get_gpio(struct ath5k_hw *ah, u32 gpio);
1468 int ath5k_hw_set_gpio(struct ath5k_hw *ah, u32 gpio, u32 val);
1469 void ath5k_hw_set_gpio_intr(struct ath5k_hw *ah, unsigned int gpio,
1470 u32 interrupt_level);
1473 /* RFkill Functions */
1474 void ath5k_rfkill_hw_start(struct ath5k_hw *ah);
1475 void ath5k_rfkill_hw_stop(struct ath5k_hw *ah);
1478 /* Misc functions TODO: Cleanup */
1479 int ath5k_hw_set_capabilities(struct ath5k_hw *ah);
1480 int ath5k_hw_enable_pspoll(struct ath5k_hw *ah, u8 *bssid, u16 assoc_id);
1481 int ath5k_hw_disable_pspoll(struct ath5k_hw *ah);
1484 /* Initial register settings functions */
1485 int ath5k_hw_write_initvals(struct ath5k_hw *ah, u8 mode, bool change_channel);
1489 /* Misc PHY functions */
1490 u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, unsigned int chan);
1491 int ath5k_hw_phy_disable(struct ath5k_hw *ah);
1492 /* Gain_F optimization */
1493 enum ath5k_rfgain ath5k_hw_gainf_calibrate(struct ath5k_hw *ah);
1494 int ath5k_hw_rfgain_opt_init(struct ath5k_hw *ah);
1495 /* PHY/RF channel functions */
1496 bool ath5k_channel_ok(struct ath5k_hw *ah, u16 freq, unsigned int flags);
1497 /* PHY calibration */
1498 void ath5k_hw_init_nfcal_hist(struct ath5k_hw *ah);
1499 int ath5k_hw_phy_calibrate(struct ath5k_hw *ah,
1500 struct ieee80211_channel *channel);
1501 void ath5k_hw_update_noise_floor(struct ath5k_hw *ah);
1502 /* Spur mitigation */
1503 bool ath5k_hw_chan_has_spur_noise(struct ath5k_hw *ah,
1504 struct ieee80211_channel *channel);
1505 /* Antenna control */
1506 void ath5k_hw_set_antenna_mode(struct ath5k_hw *ah, u8 ant_mode);
1507 void ath5k_hw_set_antenna_switch(struct ath5k_hw *ah, u8 ee_mode);
1508 /* TX power setup */
1509 int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, u8 txpower);
1511 int ath5k_hw_phy_init(struct ath5k_hw *ah, struct ieee80211_channel *channel,
1512 u8 mode, bool fast);
1515 * Functions used internally
1518 static inline struct ath_common *ath5k_hw_common(struct ath5k_hw *ah)
1523 static inline struct ath_regulatory *ath5k_hw_regulatory(struct ath5k_hw *ah)
1525 return &(ath5k_hw_common(ah)->regulatory);
1528 #ifdef CONFIG_ATHEROS_AR231X
1529 #define AR5K_AR2315_PCI_BASE ((void __iomem *)0xb0100000)
1531 static inline void __iomem *ath5k_ahb_reg(struct ath5k_hw *ah, u16 reg)
1533 /* On AR2315 and AR2317 the PCI clock domain registers
1534 * are outside of the WMAC register space */
1535 if (unlikely((reg >= 0x4000) && (reg < 0x5000) &&
1536 (ah->ah_mac_srev >= AR5K_SREV_AR2315_R6)))
1537 return AR5K_AR2315_PCI_BASE + reg;
1539 return ah->iobase + reg;
1542 static inline u32 ath5k_hw_reg_read(struct ath5k_hw *ah, u16 reg)
1544 return __raw_readl(ath5k_ahb_reg(ah, reg));
1547 static inline void ath5k_hw_reg_write(struct ath5k_hw *ah, u32 val, u16 reg)
1549 __raw_writel(val, ath5k_ahb_reg(ah, reg));
1554 static inline u32 ath5k_hw_reg_read(struct ath5k_hw *ah, u16 reg)
1556 return ioread32(ah->iobase + reg);
1559 static inline void ath5k_hw_reg_write(struct ath5k_hw *ah, u32 val, u16 reg)
1561 iowrite32(val, ah->iobase + reg);
1566 static inline enum ath_bus_type ath5k_get_bus_type(struct ath5k_hw *ah)
1568 return ath5k_hw_common(ah)->bus_ops->ath_bus_type;
1571 static inline void ath5k_read_cachesize(struct ath_common *common, int *csz)
1573 common->bus_ops->read_cachesize(common, csz);
1576 static inline bool ath5k_hw_nvram_read(struct ath5k_hw *ah, u32 off, u16 *data)
1578 struct ath_common *common = ath5k_hw_common(ah);
1579 return common->bus_ops->eeprom_read(common, off, data);
1582 static inline u32 ath5k_hw_bitswap(u32 val, unsigned int bits)
1584 u32 retval = 0, bit, i;
1586 for (i = 0; i < bits; i++) {
1587 bit = (val >> i) & 1;
1588 retval = (retval << 1) | bit;