2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
4 * Copyright (c) 2006 Devicescape Software, Inc.
5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39 * THE POSSIBILITY OF SUCH DAMAGES.
43 #include <linux/module.h>
44 #include <linux/delay.h>
45 #include <linux/hardirq.h>
48 #include <linux/netdevice.h>
49 #include <linux/cache.h>
50 #include <linux/pci.h>
51 #include <linux/ethtool.h>
52 #include <linux/uaccess.h>
54 #include <net/ieee80211_radiotap.h>
56 #include <asm/unaligned.h>
62 static int ath5k_calinterval = 10; /* Calibrate PHY every 10 secs (TODO: Fixme) */
63 static int modparam_nohwcrypt;
64 module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
65 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
67 static int modparam_all_channels;
68 module_param_named(all_channels, modparam_all_channels, bool, S_IRUGO);
69 MODULE_PARM_DESC(all_channels, "Expose all channels the device can use.");
77 MODULE_AUTHOR("Jiri Slaby");
78 MODULE_AUTHOR("Nick Kossifidis");
79 MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
80 MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
81 MODULE_LICENSE("Dual BSD/GPL");
82 MODULE_VERSION("0.6.0 (EXPERIMENTAL)");
86 static const struct pci_device_id ath5k_pci_id_table[] = {
87 { PCI_VDEVICE(ATHEROS, 0x0207), .driver_data = AR5K_AR5210 }, /* 5210 early */
88 { PCI_VDEVICE(ATHEROS, 0x0007), .driver_data = AR5K_AR5210 }, /* 5210 */
89 { PCI_VDEVICE(ATHEROS, 0x0011), .driver_data = AR5K_AR5211 }, /* 5311 - this is on AHB bus !*/
90 { PCI_VDEVICE(ATHEROS, 0x0012), .driver_data = AR5K_AR5211 }, /* 5211 */
91 { PCI_VDEVICE(ATHEROS, 0x0013), .driver_data = AR5K_AR5212 }, /* 5212 */
92 { PCI_VDEVICE(3COM_2, 0x0013), .driver_data = AR5K_AR5212 }, /* 3com 5212 */
93 { PCI_VDEVICE(3COM, 0x0013), .driver_data = AR5K_AR5212 }, /* 3com 3CRDAG675 5212 */
94 { PCI_VDEVICE(ATHEROS, 0x1014), .driver_data = AR5K_AR5212 }, /* IBM minipci 5212 */
95 { PCI_VDEVICE(ATHEROS, 0x0014), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
96 { PCI_VDEVICE(ATHEROS, 0x0015), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
97 { PCI_VDEVICE(ATHEROS, 0x0016), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
98 { PCI_VDEVICE(ATHEROS, 0x0017), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
99 { PCI_VDEVICE(ATHEROS, 0x0018), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
100 { PCI_VDEVICE(ATHEROS, 0x0019), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
101 { PCI_VDEVICE(ATHEROS, 0x001a), .driver_data = AR5K_AR5212 }, /* 2413 Griffin-lite */
102 { PCI_VDEVICE(ATHEROS, 0x001b), .driver_data = AR5K_AR5212 }, /* 5413 Eagle */
103 { PCI_VDEVICE(ATHEROS, 0x001c), .driver_data = AR5K_AR5212 }, /* PCI-E cards */
104 { PCI_VDEVICE(ATHEROS, 0x001d), .driver_data = AR5K_AR5212 }, /* 2417 Nala */
107 MODULE_DEVICE_TABLE(pci, ath5k_pci_id_table);
110 static const struct ath5k_srev_name srev_names[] = {
111 { "5210", AR5K_VERSION_MAC, AR5K_SREV_AR5210 },
112 { "5311", AR5K_VERSION_MAC, AR5K_SREV_AR5311 },
113 { "5311A", AR5K_VERSION_MAC, AR5K_SREV_AR5311A },
114 { "5311B", AR5K_VERSION_MAC, AR5K_SREV_AR5311B },
115 { "5211", AR5K_VERSION_MAC, AR5K_SREV_AR5211 },
116 { "5212", AR5K_VERSION_MAC, AR5K_SREV_AR5212 },
117 { "5213", AR5K_VERSION_MAC, AR5K_SREV_AR5213 },
118 { "5213A", AR5K_VERSION_MAC, AR5K_SREV_AR5213A },
119 { "2413", AR5K_VERSION_MAC, AR5K_SREV_AR2413 },
120 { "2414", AR5K_VERSION_MAC, AR5K_SREV_AR2414 },
121 { "5424", AR5K_VERSION_MAC, AR5K_SREV_AR5424 },
122 { "5413", AR5K_VERSION_MAC, AR5K_SREV_AR5413 },
123 { "5414", AR5K_VERSION_MAC, AR5K_SREV_AR5414 },
124 { "2415", AR5K_VERSION_MAC, AR5K_SREV_AR2415 },
125 { "5416", AR5K_VERSION_MAC, AR5K_SREV_AR5416 },
126 { "5418", AR5K_VERSION_MAC, AR5K_SREV_AR5418 },
127 { "2425", AR5K_VERSION_MAC, AR5K_SREV_AR2425 },
128 { "2417", AR5K_VERSION_MAC, AR5K_SREV_AR2417 },
129 { "xxxxx", AR5K_VERSION_MAC, AR5K_SREV_UNKNOWN },
130 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 },
131 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 },
132 { "5111A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111A },
133 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 },
134 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 },
135 { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A },
136 { "5112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112B },
137 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 },
138 { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A },
139 { "2112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112B },
140 { "2413", AR5K_VERSION_RAD, AR5K_SREV_RAD_2413 },
141 { "5413", AR5K_VERSION_RAD, AR5K_SREV_RAD_5413 },
142 { "2316", AR5K_VERSION_RAD, AR5K_SREV_RAD_2316 },
143 { "2317", AR5K_VERSION_RAD, AR5K_SREV_RAD_2317 },
144 { "5424", AR5K_VERSION_RAD, AR5K_SREV_RAD_5424 },
145 { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 },
146 { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN },
149 static const struct ieee80211_rate ath5k_rates[] = {
151 .hw_value = ATH5K_RATE_CODE_1M, },
153 .hw_value = ATH5K_RATE_CODE_2M,
154 .hw_value_short = ATH5K_RATE_CODE_2M | AR5K_SET_SHORT_PREAMBLE,
155 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
157 .hw_value = ATH5K_RATE_CODE_5_5M,
158 .hw_value_short = ATH5K_RATE_CODE_5_5M | AR5K_SET_SHORT_PREAMBLE,
159 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
161 .hw_value = ATH5K_RATE_CODE_11M,
162 .hw_value_short = ATH5K_RATE_CODE_11M | AR5K_SET_SHORT_PREAMBLE,
163 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
165 .hw_value = ATH5K_RATE_CODE_6M,
168 .hw_value = ATH5K_RATE_CODE_9M,
171 .hw_value = ATH5K_RATE_CODE_12M,
174 .hw_value = ATH5K_RATE_CODE_18M,
177 .hw_value = ATH5K_RATE_CODE_24M,
180 .hw_value = ATH5K_RATE_CODE_36M,
183 .hw_value = ATH5K_RATE_CODE_48M,
186 .hw_value = ATH5K_RATE_CODE_54M,
192 * Prototypes - PCI stack related functions
194 static int __devinit ath5k_pci_probe(struct pci_dev *pdev,
195 const struct pci_device_id *id);
196 static void __devexit ath5k_pci_remove(struct pci_dev *pdev);
198 static int ath5k_pci_suspend(struct pci_dev *pdev,
200 static int ath5k_pci_resume(struct pci_dev *pdev);
202 #define ath5k_pci_suspend NULL
203 #define ath5k_pci_resume NULL
204 #endif /* CONFIG_PM */
206 static struct pci_driver ath5k_pci_driver = {
207 .name = KBUILD_MODNAME,
208 .id_table = ath5k_pci_id_table,
209 .probe = ath5k_pci_probe,
210 .remove = __devexit_p(ath5k_pci_remove),
211 .suspend = ath5k_pci_suspend,
212 .resume = ath5k_pci_resume,
218 * Prototypes - MAC 802.11 stack related functions
220 static int ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb);
221 static int ath5k_reset(struct ath5k_softc *sc, bool stop, bool change_channel);
222 static int ath5k_reset_wake(struct ath5k_softc *sc);
223 static int ath5k_start(struct ieee80211_hw *hw);
224 static void ath5k_stop(struct ieee80211_hw *hw);
225 static int ath5k_add_interface(struct ieee80211_hw *hw,
226 struct ieee80211_if_init_conf *conf);
227 static void ath5k_remove_interface(struct ieee80211_hw *hw,
228 struct ieee80211_if_init_conf *conf);
229 static int ath5k_config(struct ieee80211_hw *hw, u32 changed);
230 static void ath5k_configure_filter(struct ieee80211_hw *hw,
231 unsigned int changed_flags,
232 unsigned int *new_flags,
233 int mc_count, struct dev_mc_list *mclist);
234 static int ath5k_set_key(struct ieee80211_hw *hw,
235 enum set_key_cmd cmd,
236 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
237 struct ieee80211_key_conf *key);
238 static int ath5k_get_stats(struct ieee80211_hw *hw,
239 struct ieee80211_low_level_stats *stats);
240 static int ath5k_get_tx_stats(struct ieee80211_hw *hw,
241 struct ieee80211_tx_queue_stats *stats);
242 static u64 ath5k_get_tsf(struct ieee80211_hw *hw);
243 static void ath5k_set_tsf(struct ieee80211_hw *hw, u64 tsf);
244 static void ath5k_reset_tsf(struct ieee80211_hw *hw);
245 static int ath5k_beacon_update(struct ath5k_softc *sc,
246 struct sk_buff *skb);
247 static void ath5k_bss_info_changed(struct ieee80211_hw *hw,
248 struct ieee80211_vif *vif,
249 struct ieee80211_bss_conf *bss_conf,
252 static const struct ieee80211_ops ath5k_hw_ops = {
254 .start = ath5k_start,
256 .add_interface = ath5k_add_interface,
257 .remove_interface = ath5k_remove_interface,
258 .config = ath5k_config,
259 .configure_filter = ath5k_configure_filter,
260 .set_key = ath5k_set_key,
261 .get_stats = ath5k_get_stats,
263 .get_tx_stats = ath5k_get_tx_stats,
264 .get_tsf = ath5k_get_tsf,
265 .set_tsf = ath5k_set_tsf,
266 .reset_tsf = ath5k_reset_tsf,
267 .bss_info_changed = ath5k_bss_info_changed,
271 * Prototypes - Internal functions
274 static int ath5k_attach(struct pci_dev *pdev,
275 struct ieee80211_hw *hw);
276 static void ath5k_detach(struct pci_dev *pdev,
277 struct ieee80211_hw *hw);
278 /* Channel/mode setup */
279 static inline short ath5k_ieee2mhz(short chan);
280 static unsigned int ath5k_copy_channels(struct ath5k_hw *ah,
281 struct ieee80211_channel *channels,
284 static int ath5k_setup_bands(struct ieee80211_hw *hw);
285 static int ath5k_chan_set(struct ath5k_softc *sc,
286 struct ieee80211_channel *chan);
287 static void ath5k_setcurmode(struct ath5k_softc *sc,
289 static void ath5k_mode_setup(struct ath5k_softc *sc);
291 /* Descriptor setup */
292 static int ath5k_desc_alloc(struct ath5k_softc *sc,
293 struct pci_dev *pdev);
294 static void ath5k_desc_free(struct ath5k_softc *sc,
295 struct pci_dev *pdev);
297 static int ath5k_rxbuf_setup(struct ath5k_softc *sc,
298 struct ath5k_buf *bf);
299 static int ath5k_txbuf_setup(struct ath5k_softc *sc,
300 struct ath5k_buf *bf);
301 static inline void ath5k_txbuf_free(struct ath5k_softc *sc,
302 struct ath5k_buf *bf)
307 pci_unmap_single(sc->pdev, bf->skbaddr, bf->skb->len,
309 dev_kfree_skb_any(bf->skb);
313 static inline void ath5k_rxbuf_free(struct ath5k_softc *sc,
314 struct ath5k_buf *bf)
319 pci_unmap_single(sc->pdev, bf->skbaddr, sc->rxbufsize,
321 dev_kfree_skb_any(bf->skb);
327 static struct ath5k_txq *ath5k_txq_setup(struct ath5k_softc *sc,
328 int qtype, int subtype);
329 static int ath5k_beaconq_setup(struct ath5k_hw *ah);
330 static int ath5k_beaconq_config(struct ath5k_softc *sc);
331 static void ath5k_txq_drainq(struct ath5k_softc *sc,
332 struct ath5k_txq *txq);
333 static void ath5k_txq_cleanup(struct ath5k_softc *sc);
334 static void ath5k_txq_release(struct ath5k_softc *sc);
336 static int ath5k_rx_start(struct ath5k_softc *sc);
337 static void ath5k_rx_stop(struct ath5k_softc *sc);
338 static unsigned int ath5k_rx_decrypted(struct ath5k_softc *sc,
339 struct ath5k_desc *ds,
341 struct ath5k_rx_status *rs);
342 static void ath5k_tasklet_rx(unsigned long data);
344 static void ath5k_tx_processq(struct ath5k_softc *sc,
345 struct ath5k_txq *txq);
346 static void ath5k_tasklet_tx(unsigned long data);
347 /* Beacon handling */
348 static int ath5k_beacon_setup(struct ath5k_softc *sc,
349 struct ath5k_buf *bf);
350 static void ath5k_beacon_send(struct ath5k_softc *sc);
351 static void ath5k_beacon_config(struct ath5k_softc *sc);
352 static void ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf);
353 static void ath5k_tasklet_beacon(unsigned long data);
355 static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
357 u64 tsf = ath5k_hw_get_tsf64(ah);
359 if ((tsf & 0x7fff) < rstamp)
362 return (tsf & ~0x7fff) | rstamp;
365 /* Interrupt handling */
366 static int ath5k_init(struct ath5k_softc *sc);
367 static int ath5k_stop_locked(struct ath5k_softc *sc);
368 static int ath5k_stop_hw(struct ath5k_softc *sc);
369 static irqreturn_t ath5k_intr(int irq, void *dev_id);
370 static void ath5k_tasklet_reset(unsigned long data);
372 static void ath5k_calibrate(unsigned long data);
375 * Module init/exit functions
384 ret = pci_register_driver(&ath5k_pci_driver);
386 printk(KERN_ERR "ath5k_pci: can't register pci driver\n");
396 pci_unregister_driver(&ath5k_pci_driver);
398 ath5k_debug_finish();
401 module_init(init_ath5k_pci);
402 module_exit(exit_ath5k_pci);
405 /********************\
406 * PCI Initialization *
407 \********************/
410 ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val)
412 const char *name = "xxxxx";
415 for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
416 if (srev_names[i].sr_type != type)
419 if ((val & 0xf0) == srev_names[i].sr_val)
420 name = srev_names[i].sr_name;
422 if ((val & 0xff) == srev_names[i].sr_val) {
423 name = srev_names[i].sr_name;
432 ath5k_pci_probe(struct pci_dev *pdev,
433 const struct pci_device_id *id)
436 struct ath5k_softc *sc;
437 struct ieee80211_hw *hw;
441 ret = pci_enable_device(pdev);
443 dev_err(&pdev->dev, "can't enable device\n");
447 /* XXX 32-bit addressing only */
448 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
450 dev_err(&pdev->dev, "32-bit DMA not available\n");
455 * Cache line size is used to size and align various
456 * structures used to communicate with the hardware.
458 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
461 * Linux 2.4.18 (at least) writes the cache line size
462 * register as a 16-bit wide register which is wrong.
463 * We must have this setup properly for rx buffer
464 * DMA to work so force a reasonable value here if it
467 csz = L1_CACHE_BYTES / sizeof(u32);
468 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
471 * The default setting of latency timer yields poor results,
472 * set it to the value used by other systems. It may be worth
473 * tweaking this setting more.
475 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
477 /* Enable bus mastering */
478 pci_set_master(pdev);
481 * Disable the RETRY_TIMEOUT register (0x41) to keep
482 * PCI Tx retries from interfering with C3 CPU state.
484 pci_write_config_byte(pdev, 0x41, 0);
486 ret = pci_request_region(pdev, 0, "ath5k");
488 dev_err(&pdev->dev, "cannot reserve PCI memory region\n");
492 mem = pci_iomap(pdev, 0, 0);
494 dev_err(&pdev->dev, "cannot remap PCI memory region\n") ;
500 * Allocate hw (mac80211 main struct)
501 * and hw->priv (driver private data)
503 hw = ieee80211_alloc_hw(sizeof(*sc), &ath5k_hw_ops);
505 dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n");
510 dev_info(&pdev->dev, "registered as '%s'\n", wiphy_name(hw->wiphy));
512 /* Initialize driver private data */
513 SET_IEEE80211_DEV(hw, &pdev->dev);
514 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
515 IEEE80211_HW_SIGNAL_DBM |
516 IEEE80211_HW_NOISE_DBM;
518 hw->wiphy->interface_modes =
519 BIT(NL80211_IFTYPE_STATION) |
520 BIT(NL80211_IFTYPE_ADHOC) |
521 BIT(NL80211_IFTYPE_MESH_POINT);
523 hw->extra_tx_headroom = 2;
524 hw->channel_change_time = 5000;
529 ath5k_debug_init_device(sc);
532 * Mark the device as detached to avoid processing
533 * interrupts until setup is complete.
535 __set_bit(ATH_STAT_INVALID, sc->status);
537 sc->iobase = mem; /* So we can unmap it on detach */
538 sc->cachelsz = csz * sizeof(u32); /* convert to bytes */
539 sc->opmode = NL80211_IFTYPE_STATION;
540 mutex_init(&sc->lock);
541 spin_lock_init(&sc->rxbuflock);
542 spin_lock_init(&sc->txbuflock);
543 spin_lock_init(&sc->block);
545 /* Set private data */
546 pci_set_drvdata(pdev, hw);
548 /* Setup interrupt handler */
549 ret = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
551 ATH5K_ERR(sc, "request_irq failed\n");
555 /* Initialize device */
556 sc->ah = ath5k_hw_attach(sc, id->driver_data);
557 if (IS_ERR(sc->ah)) {
558 ret = PTR_ERR(sc->ah);
562 /* set up multi-rate retry capabilities */
563 if (sc->ah->ah_version == AR5K_AR5212) {
565 hw->max_rate_tries = 11;
568 /* Finish private driver data initialization */
569 ret = ath5k_attach(pdev, hw);
573 ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
574 ath5k_chip_name(AR5K_VERSION_MAC, sc->ah->ah_mac_srev),
576 sc->ah->ah_phy_revision);
578 if (!sc->ah->ah_single_chip) {
579 /* Single chip radio (!RF5111) */
580 if (sc->ah->ah_radio_5ghz_revision &&
581 !sc->ah->ah_radio_2ghz_revision) {
582 /* No 5GHz support -> report 2GHz radio */
583 if (!test_bit(AR5K_MODE_11A,
584 sc->ah->ah_capabilities.cap_mode)) {
585 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
586 ath5k_chip_name(AR5K_VERSION_RAD,
587 sc->ah->ah_radio_5ghz_revision),
588 sc->ah->ah_radio_5ghz_revision);
589 /* No 2GHz support (5110 and some
590 * 5Ghz only cards) -> report 5Ghz radio */
591 } else if (!test_bit(AR5K_MODE_11B,
592 sc->ah->ah_capabilities.cap_mode)) {
593 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
594 ath5k_chip_name(AR5K_VERSION_RAD,
595 sc->ah->ah_radio_5ghz_revision),
596 sc->ah->ah_radio_5ghz_revision);
597 /* Multiband radio */
599 ATH5K_INFO(sc, "RF%s multiband radio found"
601 ath5k_chip_name(AR5K_VERSION_RAD,
602 sc->ah->ah_radio_5ghz_revision),
603 sc->ah->ah_radio_5ghz_revision);
606 /* Multi chip radio (RF5111 - RF2111) ->
607 * report both 2GHz/5GHz radios */
608 else if (sc->ah->ah_radio_5ghz_revision &&
609 sc->ah->ah_radio_2ghz_revision){
610 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
611 ath5k_chip_name(AR5K_VERSION_RAD,
612 sc->ah->ah_radio_5ghz_revision),
613 sc->ah->ah_radio_5ghz_revision);
614 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
615 ath5k_chip_name(AR5K_VERSION_RAD,
616 sc->ah->ah_radio_2ghz_revision),
617 sc->ah->ah_radio_2ghz_revision);
622 /* ready to process interrupts */
623 __clear_bit(ATH_STAT_INVALID, sc->status);
627 ath5k_hw_detach(sc->ah);
629 free_irq(pdev->irq, sc);
631 ieee80211_free_hw(hw);
633 pci_iounmap(pdev, mem);
635 pci_release_region(pdev, 0);
637 pci_disable_device(pdev);
642 static void __devexit
643 ath5k_pci_remove(struct pci_dev *pdev)
645 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
646 struct ath5k_softc *sc = hw->priv;
648 ath5k_debug_finish_device(sc);
649 ath5k_detach(pdev, hw);
650 ath5k_hw_detach(sc->ah);
651 free_irq(pdev->irq, sc);
652 pci_iounmap(pdev, sc->iobase);
653 pci_release_region(pdev, 0);
654 pci_disable_device(pdev);
655 ieee80211_free_hw(hw);
660 ath5k_pci_suspend(struct pci_dev *pdev, pm_message_t state)
662 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
663 struct ath5k_softc *sc = hw->priv;
667 free_irq(pdev->irq, sc);
668 pci_save_state(pdev);
669 pci_disable_device(pdev);
670 pci_set_power_state(pdev, PCI_D3hot);
676 ath5k_pci_resume(struct pci_dev *pdev)
678 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
679 struct ath5k_softc *sc = hw->priv;
682 pci_restore_state(pdev);
684 err = pci_enable_device(pdev);
688 err = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
690 ATH5K_ERR(sc, "request_irq failed\n");
694 ath5k_led_enable(sc);
698 pci_disable_device(pdev);
701 #endif /* CONFIG_PM */
704 /***********************\
705 * Driver Initialization *
706 \***********************/
708 static int ath5k_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request)
710 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
711 struct ath5k_softc *sc = hw->priv;
712 struct ath_regulatory *reg = &sc->ah->ah_regulatory;
714 return ath_reg_notifier_apply(wiphy, request, reg);
718 ath5k_attach(struct pci_dev *pdev, struct ieee80211_hw *hw)
720 struct ath5k_softc *sc = hw->priv;
721 struct ath5k_hw *ah = sc->ah;
722 u8 mac[ETH_ALEN] = {};
725 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "devid 0x%x\n", pdev->device);
728 * Check if the MAC has multi-rate retry support.
729 * We do this by trying to setup a fake extended
730 * descriptor. MAC's that don't have support will
731 * return false w/o doing anything. MAC's that do
732 * support it will return true w/o doing anything.
734 ret = ah->ah_setup_mrr_tx_desc(ah, NULL, 0, 0, 0, 0, 0, 0);
738 __set_bit(ATH_STAT_MRRETRY, sc->status);
741 * Collect the channel list. The 802.11 layer
742 * is resposible for filtering this list based
743 * on settings like the phy mode and regulatory
744 * domain restrictions.
746 ret = ath5k_setup_bands(hw);
748 ATH5K_ERR(sc, "can't get channels\n");
752 /* NB: setup here so ath5k_rate_update is happy */
753 if (test_bit(AR5K_MODE_11A, ah->ah_modes))
754 ath5k_setcurmode(sc, AR5K_MODE_11A);
756 ath5k_setcurmode(sc, AR5K_MODE_11B);
759 * Allocate tx+rx descriptors and populate the lists.
761 ret = ath5k_desc_alloc(sc, pdev);
763 ATH5K_ERR(sc, "can't allocate descriptors\n");
768 * Allocate hardware transmit queues: one queue for
769 * beacon frames and one data queue for each QoS
770 * priority. Note that hw functions handle reseting
771 * these queues at the needed time.
773 ret = ath5k_beaconq_setup(ah);
775 ATH5K_ERR(sc, "can't setup a beacon xmit queue\n");
780 sc->txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
781 if (IS_ERR(sc->txq)) {
782 ATH5K_ERR(sc, "can't setup xmit queue\n");
783 ret = PTR_ERR(sc->txq);
787 tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc);
788 tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc);
789 tasklet_init(&sc->restq, ath5k_tasklet_reset, (unsigned long)sc);
790 tasklet_init(&sc->beacontq, ath5k_tasklet_beacon, (unsigned long)sc);
791 setup_timer(&sc->calib_tim, ath5k_calibrate, (unsigned long)sc);
793 ret = ath5k_eeprom_read_mac(ah, mac);
795 ATH5K_ERR(sc, "unable to read address from EEPROM: 0x%04x\n",
800 SET_IEEE80211_PERM_ADDR(hw, mac);
801 /* All MAC address bits matter for ACKs */
802 memset(sc->bssidmask, 0xff, ETH_ALEN);
803 ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask);
805 ah->ah_regulatory.current_rd =
806 ah->ah_capabilities.cap_eeprom.ee_regdomain;
807 ret = ath_regd_init(&ah->ah_regulatory, hw->wiphy, ath5k_reg_notifier);
809 ATH5K_ERR(sc, "can't initialize regulatory system\n");
813 ret = ieee80211_register_hw(hw);
815 ATH5K_ERR(sc, "can't register ieee80211 hw\n");
819 if (!ath_is_world_regd(&sc->ah->ah_regulatory))
820 regulatory_hint(hw->wiphy, sc->ah->ah_regulatory.alpha2);
826 ath5k_txq_release(sc);
828 ath5k_hw_release_tx_queue(ah, sc->bhalq);
830 ath5k_desc_free(sc, pdev);
836 ath5k_detach(struct pci_dev *pdev, struct ieee80211_hw *hw)
838 struct ath5k_softc *sc = hw->priv;
841 * NB: the order of these is important:
842 * o call the 802.11 layer before detaching ath5k_hw to
843 * insure callbacks into the driver to delete global
844 * key cache entries can be handled
845 * o reclaim the tx queue data structures after calling
846 * the 802.11 layer as we'll get called back to reclaim
847 * node state and potentially want to use them
848 * o to cleanup the tx queues the hal is called, so detach
850 * XXX: ??? detach ath5k_hw ???
851 * Other than that, it's straightforward...
853 ieee80211_unregister_hw(hw);
854 ath5k_desc_free(sc, pdev);
855 ath5k_txq_release(sc);
856 ath5k_hw_release_tx_queue(sc->ah, sc->bhalq);
857 ath5k_unregister_leds(sc);
860 * NB: can't reclaim these until after ieee80211_ifdetach
861 * returns because we'll get called back to reclaim node
862 * state and potentially want to use them.
869 /********************\
870 * Channel/mode setup *
871 \********************/
874 * Convert IEEE channel number to MHz frequency.
877 ath5k_ieee2mhz(short chan)
879 if (chan <= 14 || chan >= 27)
880 return ieee80211chan2mhz(chan);
882 return 2212 + chan * 20;
886 * Returns true for the channel numbers used without all_channels modparam.
888 static bool ath5k_is_standard_channel(short chan)
890 return ((chan <= 14) ||
892 ((chan & 3) == 0 && chan >= 36 && chan <= 64) ||
894 ((chan & 3) == 0 && chan >= 100 && chan <= 140) ||
896 ((chan & 3) == 1 && chan >= 149 && chan <= 165));
900 ath5k_copy_channels(struct ath5k_hw *ah,
901 struct ieee80211_channel *channels,
905 unsigned int i, count, size, chfreq, freq, ch;
907 if (!test_bit(mode, ah->ah_modes))
912 case AR5K_MODE_11A_TURBO:
913 /* 1..220, but 2GHz frequencies are filtered by check_channel */
915 chfreq = CHANNEL_5GHZ;
919 case AR5K_MODE_11G_TURBO:
921 chfreq = CHANNEL_2GHZ;
924 ATH5K_WARN(ah->ah_sc, "bad mode, not copying channels\n");
928 for (i = 0, count = 0; i < size && max > 0; i++) {
930 freq = ath5k_ieee2mhz(ch);
932 /* Check if channel is supported by the chipset */
933 if (!ath5k_channel_ok(ah, freq, chfreq))
936 if (!modparam_all_channels && !ath5k_is_standard_channel(ch))
939 /* Write channel info and increment counter */
940 channels[count].center_freq = freq;
941 channels[count].band = (chfreq == CHANNEL_2GHZ) ?
942 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
946 channels[count].hw_value = chfreq | CHANNEL_OFDM;
948 case AR5K_MODE_11A_TURBO:
949 case AR5K_MODE_11G_TURBO:
950 channels[count].hw_value = chfreq |
951 CHANNEL_OFDM | CHANNEL_TURBO;
954 channels[count].hw_value = CHANNEL_B;
965 ath5k_setup_rate_idx(struct ath5k_softc *sc, struct ieee80211_supported_band *b)
969 for (i = 0; i < AR5K_MAX_RATES; i++)
970 sc->rate_idx[b->band][i] = -1;
972 for (i = 0; i < b->n_bitrates; i++) {
973 sc->rate_idx[b->band][b->bitrates[i].hw_value] = i;
974 if (b->bitrates[i].hw_value_short)
975 sc->rate_idx[b->band][b->bitrates[i].hw_value_short] = i;
980 ath5k_setup_bands(struct ieee80211_hw *hw)
982 struct ath5k_softc *sc = hw->priv;
983 struct ath5k_hw *ah = sc->ah;
984 struct ieee80211_supported_band *sband;
985 int max_c, count_c = 0;
988 BUILD_BUG_ON(ARRAY_SIZE(sc->sbands) < IEEE80211_NUM_BANDS);
989 max_c = ARRAY_SIZE(sc->channels);
992 sband = &sc->sbands[IEEE80211_BAND_2GHZ];
993 sband->band = IEEE80211_BAND_2GHZ;
994 sband->bitrates = &sc->rates[IEEE80211_BAND_2GHZ][0];
996 if (test_bit(AR5K_MODE_11G, sc->ah->ah_capabilities.cap_mode)) {
998 memcpy(sband->bitrates, &ath5k_rates[0],
999 sizeof(struct ieee80211_rate) * 12);
1000 sband->n_bitrates = 12;
1002 sband->channels = sc->channels;
1003 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
1004 AR5K_MODE_11G, max_c);
1006 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
1007 count_c = sband->n_channels;
1009 } else if (test_bit(AR5K_MODE_11B, sc->ah->ah_capabilities.cap_mode)) {
1011 memcpy(sband->bitrates, &ath5k_rates[0],
1012 sizeof(struct ieee80211_rate) * 4);
1013 sband->n_bitrates = 4;
1015 /* 5211 only supports B rates and uses 4bit rate codes
1016 * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B)
1019 if (ah->ah_version == AR5K_AR5211) {
1020 for (i = 0; i < 4; i++) {
1021 sband->bitrates[i].hw_value =
1022 sband->bitrates[i].hw_value & 0xF;
1023 sband->bitrates[i].hw_value_short =
1024 sband->bitrates[i].hw_value_short & 0xF;
1028 sband->channels = sc->channels;
1029 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
1030 AR5K_MODE_11B, max_c);
1032 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
1033 count_c = sband->n_channels;
1036 ath5k_setup_rate_idx(sc, sband);
1038 /* 5GHz band, A mode */
1039 if (test_bit(AR5K_MODE_11A, sc->ah->ah_capabilities.cap_mode)) {
1040 sband = &sc->sbands[IEEE80211_BAND_5GHZ];
1041 sband->band = IEEE80211_BAND_5GHZ;
1042 sband->bitrates = &sc->rates[IEEE80211_BAND_5GHZ][0];
1044 memcpy(sband->bitrates, &ath5k_rates[4],
1045 sizeof(struct ieee80211_rate) * 8);
1046 sband->n_bitrates = 8;
1048 sband->channels = &sc->channels[count_c];
1049 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
1050 AR5K_MODE_11A, max_c);
1052 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband;
1054 ath5k_setup_rate_idx(sc, sband);
1056 ath5k_debug_dump_bands(sc);
1062 * Set/change channels. If the channel is really being changed,
1063 * it's done by reseting the chip. To accomplish this we must
1064 * first cleanup any pending DMA, then restart stuff after a la
1067 * Called with sc->lock.
1070 ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan)
1072 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "(%u MHz) -> (%u MHz)\n",
1073 sc->curchan->center_freq, chan->center_freq);
1075 if (chan->center_freq != sc->curchan->center_freq ||
1076 chan->hw_value != sc->curchan->hw_value) {
1079 sc->curband = &sc->sbands[chan->band];
1082 * To switch channels clear any pending DMA operations;
1083 * wait long enough for the RX fifo to drain, reset the
1084 * hardware at the new frequency, and then re-enable
1085 * the relevant bits of the h/w.
1087 return ath5k_reset(sc, true, true);
1094 ath5k_setcurmode(struct ath5k_softc *sc, unsigned int mode)
1098 if (mode == AR5K_MODE_11A) {
1099 sc->curband = &sc->sbands[IEEE80211_BAND_5GHZ];
1101 sc->curband = &sc->sbands[IEEE80211_BAND_2GHZ];
1106 ath5k_mode_setup(struct ath5k_softc *sc)
1108 struct ath5k_hw *ah = sc->ah;
1111 /* configure rx filter */
1112 rfilt = sc->filter_flags;
1113 ath5k_hw_set_rx_filter(ah, rfilt);
1115 if (ath5k_hw_hasbssidmask(ah))
1116 ath5k_hw_set_bssid_mask(ah, sc->bssidmask);
1118 /* configure operational mode */
1119 ath5k_hw_set_opmode(ah);
1121 ath5k_hw_set_mcast_filter(ah, 0, 0);
1122 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
1126 ath5k_hw_to_driver_rix(struct ath5k_softc *sc, int hw_rix)
1130 /* return base rate on errors */
1131 if (WARN(hw_rix < 0 || hw_rix >= AR5K_MAX_RATES,
1132 "hw_rix out of bounds: %x\n", hw_rix))
1135 rix = sc->rate_idx[sc->curband->band][hw_rix];
1136 if (WARN(rix < 0, "invalid hw_rix: %x\n", hw_rix))
1147 struct sk_buff *ath5k_rx_skb_alloc(struct ath5k_softc *sc, dma_addr_t *skb_addr)
1149 struct sk_buff *skb;
1153 * Allocate buffer with headroom_needed space for the
1154 * fake physical layer header at the start.
1156 skb = dev_alloc_skb(sc->rxbufsize + sc->cachelsz - 1);
1159 ATH5K_ERR(sc, "can't alloc skbuff of size %u\n",
1160 sc->rxbufsize + sc->cachelsz - 1);
1164 * Cache-line-align. This is important (for the
1165 * 5210 at least) as not doing so causes bogus data
1168 off = ((unsigned long)skb->data) % sc->cachelsz;
1170 skb_reserve(skb, sc->cachelsz - off);
1172 *skb_addr = pci_map_single(sc->pdev,
1173 skb->data, sc->rxbufsize, PCI_DMA_FROMDEVICE);
1174 if (unlikely(pci_dma_mapping_error(sc->pdev, *skb_addr))) {
1175 ATH5K_ERR(sc, "%s: DMA mapping failed\n", __func__);
1183 ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1185 struct ath5k_hw *ah = sc->ah;
1186 struct sk_buff *skb = bf->skb;
1187 struct ath5k_desc *ds;
1190 skb = ath5k_rx_skb_alloc(sc, &bf->skbaddr);
1197 * Setup descriptors. For receive we always terminate
1198 * the descriptor list with a self-linked entry so we'll
1199 * not get overrun under high load (as can happen with a
1200 * 5212 when ANI processing enables PHY error frames).
1202 * To insure the last descriptor is self-linked we create
1203 * each descriptor as self-linked and add it to the end. As
1204 * each additional descriptor is added the previous self-linked
1205 * entry is ``fixed'' naturally. This should be safe even
1206 * if DMA is happening. When processing RX interrupts we
1207 * never remove/process the last, self-linked, entry on the
1208 * descriptor list. This insures the hardware always has
1209 * someplace to write a new frame.
1212 ds->ds_link = bf->daddr; /* link to self */
1213 ds->ds_data = bf->skbaddr;
1214 ah->ah_setup_rx_desc(ah, ds,
1215 skb_tailroom(skb), /* buffer size */
1218 if (sc->rxlink != NULL)
1219 *sc->rxlink = bf->daddr;
1220 sc->rxlink = &ds->ds_link;
1225 ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1227 struct ath5k_hw *ah = sc->ah;
1228 struct ath5k_txq *txq = sc->txq;
1229 struct ath5k_desc *ds = bf->desc;
1230 struct sk_buff *skb = bf->skb;
1231 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1232 unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID;
1233 struct ieee80211_rate *rate;
1234 unsigned int mrr_rate[3], mrr_tries[3];
1241 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
1243 /* XXX endianness */
1244 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1247 rate = ieee80211_get_tx_rate(sc->hw, info);
1249 if (info->flags & IEEE80211_TX_CTL_NO_ACK)
1250 flags |= AR5K_TXDESC_NOACK;
1252 rc_flags = info->control.rates[0].flags;
1253 hw_rate = (rc_flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) ?
1254 rate->hw_value_short : rate->hw_value;
1258 /* FIXME: If we are in g mode and rate is a CCK rate
1259 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
1260 * from tx power (value is in dB units already) */
1261 if (info->control.hw_key) {
1262 keyidx = info->control.hw_key->hw_key_idx;
1263 pktlen += info->control.hw_key->icv_len;
1265 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
1266 flags |= AR5K_TXDESC_RTSENA;
1267 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
1268 duration = le16_to_cpu(ieee80211_rts_duration(sc->hw,
1269 sc->vif, pktlen, info));
1271 if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
1272 flags |= AR5K_TXDESC_CTSENA;
1273 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
1274 duration = le16_to_cpu(ieee80211_ctstoself_duration(sc->hw,
1275 sc->vif, pktlen, info));
1277 ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
1278 ieee80211_get_hdrlen_from_skb(skb), AR5K_PKT_TYPE_NORMAL,
1279 (sc->power_level * 2),
1281 info->control.rates[0].count, keyidx, 0, flags,
1282 cts_rate, duration);
1286 memset(mrr_rate, 0, sizeof(mrr_rate));
1287 memset(mrr_tries, 0, sizeof(mrr_tries));
1288 for (i = 0; i < 3; i++) {
1289 rate = ieee80211_get_alt_retry_rate(sc->hw, info, i);
1293 mrr_rate[i] = rate->hw_value;
1294 mrr_tries[i] = info->control.rates[i + 1].count;
1297 ah->ah_setup_mrr_tx_desc(ah, ds,
1298 mrr_rate[0], mrr_tries[0],
1299 mrr_rate[1], mrr_tries[1],
1300 mrr_rate[2], mrr_tries[2]);
1303 ds->ds_data = bf->skbaddr;
1305 spin_lock_bh(&txq->lock);
1306 list_add_tail(&bf->list, &txq->q);
1307 sc->tx_stats[txq->qnum].len++;
1308 if (txq->link == NULL) /* is this first packet? */
1309 ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr);
1310 else /* no, so only link it */
1311 *txq->link = bf->daddr;
1313 txq->link = &ds->ds_link;
1314 ath5k_hw_start_tx_dma(ah, txq->qnum);
1316 spin_unlock_bh(&txq->lock);
1320 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
1324 /*******************\
1325 * Descriptors setup *
1326 \*******************/
1329 ath5k_desc_alloc(struct ath5k_softc *sc, struct pci_dev *pdev)
1331 struct ath5k_desc *ds;
1332 struct ath5k_buf *bf;
1337 /* allocate descriptors */
1338 sc->desc_len = sizeof(struct ath5k_desc) *
1339 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
1340 sc->desc = pci_alloc_consistent(pdev, sc->desc_len, &sc->desc_daddr);
1341 if (sc->desc == NULL) {
1342 ATH5K_ERR(sc, "can't allocate descriptors\n");
1347 da = sc->desc_daddr;
1348 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
1349 ds, sc->desc_len, (unsigned long long)sc->desc_daddr);
1351 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
1352 sizeof(struct ath5k_buf), GFP_KERNEL);
1354 ATH5K_ERR(sc, "can't allocate bufptr\n");
1360 INIT_LIST_HEAD(&sc->rxbuf);
1361 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
1364 list_add_tail(&bf->list, &sc->rxbuf);
1367 INIT_LIST_HEAD(&sc->txbuf);
1368 sc->txbuf_len = ATH_TXBUF;
1369 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++,
1370 da += sizeof(*ds)) {
1373 list_add_tail(&bf->list, &sc->txbuf);
1383 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1390 ath5k_desc_free(struct ath5k_softc *sc, struct pci_dev *pdev)
1392 struct ath5k_buf *bf;
1394 ath5k_txbuf_free(sc, sc->bbuf);
1395 list_for_each_entry(bf, &sc->txbuf, list)
1396 ath5k_txbuf_free(sc, bf);
1397 list_for_each_entry(bf, &sc->rxbuf, list)
1398 ath5k_rxbuf_free(sc, bf);
1400 /* Free memory associated with all descriptors */
1401 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1415 static struct ath5k_txq *
1416 ath5k_txq_setup(struct ath5k_softc *sc,
1417 int qtype, int subtype)
1419 struct ath5k_hw *ah = sc->ah;
1420 struct ath5k_txq *txq;
1421 struct ath5k_txq_info qi = {
1422 .tqi_subtype = subtype,
1423 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1424 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1425 .tqi_cw_max = AR5K_TXQ_USEDEFAULT
1430 * Enable interrupts only for EOL and DESC conditions.
1431 * We mark tx descriptors to receive a DESC interrupt
1432 * when a tx queue gets deep; otherwise waiting for the
1433 * EOL to reap descriptors. Note that this is done to
1434 * reduce interrupt load and this only defers reaping
1435 * descriptors, never transmitting frames. Aside from
1436 * reducing interrupts this also permits more concurrency.
1437 * The only potential downside is if the tx queue backs
1438 * up in which case the top half of the kernel may backup
1439 * due to a lack of tx descriptors.
1441 qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
1442 AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
1443 qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi);
1446 * NB: don't print a message, this happens
1447 * normally on parts with too few tx queues
1449 return ERR_PTR(qnum);
1451 if (qnum >= ARRAY_SIZE(sc->txqs)) {
1452 ATH5K_ERR(sc, "hw qnum %u out of range, max %tu!\n",
1453 qnum, ARRAY_SIZE(sc->txqs));
1454 ath5k_hw_release_tx_queue(ah, qnum);
1455 return ERR_PTR(-EINVAL);
1457 txq = &sc->txqs[qnum];
1461 INIT_LIST_HEAD(&txq->q);
1462 spin_lock_init(&txq->lock);
1465 return &sc->txqs[qnum];
1469 ath5k_beaconq_setup(struct ath5k_hw *ah)
1471 struct ath5k_txq_info qi = {
1472 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1473 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1474 .tqi_cw_max = AR5K_TXQ_USEDEFAULT,
1475 /* NB: for dynamic turbo, don't enable any other interrupts */
1476 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE
1479 return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi);
1483 ath5k_beaconq_config(struct ath5k_softc *sc)
1485 struct ath5k_hw *ah = sc->ah;
1486 struct ath5k_txq_info qi;
1489 ret = ath5k_hw_get_tx_queueprops(ah, sc->bhalq, &qi);
1492 if (sc->opmode == NL80211_IFTYPE_AP ||
1493 sc->opmode == NL80211_IFTYPE_MESH_POINT) {
1495 * Always burst out beacon and CAB traffic
1496 * (aifs = cwmin = cwmax = 0)
1501 } else if (sc->opmode == NL80211_IFTYPE_ADHOC) {
1503 * Adhoc mode; backoff between 0 and (2 * cw_min).
1507 qi.tqi_cw_max = 2 * ah->ah_cw_min;
1510 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1511 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
1512 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max);
1514 ret = ath5k_hw_set_tx_queueprops(ah, sc->bhalq, &qi);
1516 ATH5K_ERR(sc, "%s: unable to update parameters for beacon "
1517 "hardware queue!\n", __func__);
1521 return ath5k_hw_reset_tx_queue(ah, sc->bhalq); /* push to h/w */;
1525 ath5k_txq_drainq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1527 struct ath5k_buf *bf, *bf0;
1530 * NB: this assumes output has been stopped and
1531 * we do not need to block ath5k_tx_tasklet
1533 spin_lock_bh(&txq->lock);
1534 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1535 ath5k_debug_printtxbuf(sc, bf);
1537 ath5k_txbuf_free(sc, bf);
1539 spin_lock_bh(&sc->txbuflock);
1540 sc->tx_stats[txq->qnum].len--;
1541 list_move_tail(&bf->list, &sc->txbuf);
1543 spin_unlock_bh(&sc->txbuflock);
1546 spin_unlock_bh(&txq->lock);
1550 * Drain the transmit queues and reclaim resources.
1553 ath5k_txq_cleanup(struct ath5k_softc *sc)
1555 struct ath5k_hw *ah = sc->ah;
1558 /* XXX return value */
1559 if (likely(!test_bit(ATH_STAT_INVALID, sc->status))) {
1560 /* don't touch the hardware if marked invalid */
1561 ath5k_hw_stop_tx_dma(ah, sc->bhalq);
1562 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "beacon queue %x\n",
1563 ath5k_hw_get_txdp(ah, sc->bhalq));
1564 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1565 if (sc->txqs[i].setup) {
1566 ath5k_hw_stop_tx_dma(ah, sc->txqs[i].qnum);
1567 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "txq [%u] %x, "
1570 ath5k_hw_get_txdp(ah,
1575 ieee80211_wake_queues(sc->hw); /* XXX move to callers */
1577 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1578 if (sc->txqs[i].setup)
1579 ath5k_txq_drainq(sc, &sc->txqs[i]);
1583 ath5k_txq_release(struct ath5k_softc *sc)
1585 struct ath5k_txq *txq = sc->txqs;
1588 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++)
1590 ath5k_hw_release_tx_queue(sc->ah, txq->qnum);
1603 * Enable the receive h/w following a reset.
1606 ath5k_rx_start(struct ath5k_softc *sc)
1608 struct ath5k_hw *ah = sc->ah;
1609 struct ath5k_buf *bf;
1612 sc->rxbufsize = roundup(IEEE80211_MAX_LEN, sc->cachelsz);
1614 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "cachelsz %u rxbufsize %u\n",
1615 sc->cachelsz, sc->rxbufsize);
1617 spin_lock_bh(&sc->rxbuflock);
1619 list_for_each_entry(bf, &sc->rxbuf, list) {
1620 ret = ath5k_rxbuf_setup(sc, bf);
1622 spin_unlock_bh(&sc->rxbuflock);
1626 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1627 ath5k_hw_set_rxdp(ah, bf->daddr);
1628 spin_unlock_bh(&sc->rxbuflock);
1630 ath5k_hw_start_rx_dma(ah); /* enable recv descriptors */
1631 ath5k_mode_setup(sc); /* set filters, etc. */
1632 ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */
1640 * Disable the receive h/w in preparation for a reset.
1643 ath5k_rx_stop(struct ath5k_softc *sc)
1645 struct ath5k_hw *ah = sc->ah;
1647 ath5k_hw_stop_rx_pcu(ah); /* disable PCU */
1648 ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */
1649 ath5k_hw_stop_rx_dma(ah); /* disable DMA engine */
1651 ath5k_debug_printrxbuffs(sc, ah);
1653 sc->rxlink = NULL; /* just in case */
1657 ath5k_rx_decrypted(struct ath5k_softc *sc, struct ath5k_desc *ds,
1658 struct sk_buff *skb, struct ath5k_rx_status *rs)
1660 struct ieee80211_hdr *hdr = (void *)skb->data;
1661 unsigned int keyix, hlen;
1663 if (!(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1664 rs->rs_keyix != AR5K_RXKEYIX_INVALID)
1665 return RX_FLAG_DECRYPTED;
1667 /* Apparently when a default key is used to decrypt the packet
1668 the hw does not set the index used to decrypt. In such cases
1669 get the index from the packet. */
1670 hlen = ieee80211_hdrlen(hdr->frame_control);
1671 if (ieee80211_has_protected(hdr->frame_control) &&
1672 !(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1673 skb->len >= hlen + 4) {
1674 keyix = skb->data[hlen + 3] >> 6;
1676 if (test_bit(keyix, sc->keymap))
1677 return RX_FLAG_DECRYPTED;
1685 ath5k_check_ibss_tsf(struct ath5k_softc *sc, struct sk_buff *skb,
1686 struct ieee80211_rx_status *rxs)
1690 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1692 if (ieee80211_is_beacon(mgmt->frame_control) &&
1693 le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS &&
1694 memcmp(mgmt->bssid, sc->ah->ah_bssid, ETH_ALEN) == 0) {
1696 * Received an IBSS beacon with the same BSSID. Hardware *must*
1697 * have updated the local TSF. We have to work around various
1698 * hardware bugs, though...
1700 tsf = ath5k_hw_get_tsf64(sc->ah);
1701 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp);
1702 hw_tu = TSF_TO_TU(tsf);
1704 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1705 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
1706 (unsigned long long)bc_tstamp,
1707 (unsigned long long)rxs->mactime,
1708 (unsigned long long)(rxs->mactime - bc_tstamp),
1709 (unsigned long long)tsf);
1712 * Sometimes the HW will give us a wrong tstamp in the rx
1713 * status, causing the timestamp extension to go wrong.
1714 * (This seems to happen especially with beacon frames bigger
1715 * than 78 byte (incl. FCS))
1716 * But we know that the receive timestamp must be later than the
1717 * timestamp of the beacon since HW must have synced to that.
1719 * NOTE: here we assume mactime to be after the frame was
1720 * received, not like mac80211 which defines it at the start.
1722 if (bc_tstamp > rxs->mactime) {
1723 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1724 "fixing mactime from %llx to %llx\n",
1725 (unsigned long long)rxs->mactime,
1726 (unsigned long long)tsf);
1731 * Local TSF might have moved higher than our beacon timers,
1732 * in that case we have to update them to continue sending
1733 * beacons. This also takes care of synchronizing beacon sending
1734 * times with other stations.
1736 if (hw_tu >= sc->nexttbtt)
1737 ath5k_beacon_update_timers(sc, bc_tstamp);
1742 ath5k_tasklet_rx(unsigned long data)
1744 struct ieee80211_rx_status rxs = {};
1745 struct ath5k_rx_status rs = {};
1746 struct sk_buff *skb, *next_skb;
1747 dma_addr_t next_skb_addr;
1748 struct ath5k_softc *sc = (void *)data;
1749 struct ath5k_buf *bf;
1750 struct ath5k_desc *ds;
1755 spin_lock(&sc->rxbuflock);
1756 if (list_empty(&sc->rxbuf)) {
1757 ATH5K_WARN(sc, "empty rx buf pool\n");
1763 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1764 BUG_ON(bf->skb == NULL);
1768 /* bail if HW is still using self-linked descriptor */
1769 if (ath5k_hw_get_rxdp(sc->ah) == bf->daddr)
1772 ret = sc->ah->ah_proc_rx_desc(sc->ah, ds, &rs);
1773 if (unlikely(ret == -EINPROGRESS))
1775 else if (unlikely(ret)) {
1776 ATH5K_ERR(sc, "error in processing rx descriptor\n");
1777 spin_unlock(&sc->rxbuflock);
1781 if (unlikely(rs.rs_more)) {
1782 ATH5K_WARN(sc, "unsupported jumbo\n");
1786 if (unlikely(rs.rs_status)) {
1787 if (rs.rs_status & AR5K_RXERR_PHY)
1789 if (rs.rs_status & AR5K_RXERR_DECRYPT) {
1791 * Decrypt error. If the error occurred
1792 * because there was no hardware key, then
1793 * let the frame through so the upper layers
1794 * can process it. This is necessary for 5210
1795 * parts which have no way to setup a ``clear''
1798 * XXX do key cache faulting
1800 if (rs.rs_keyix == AR5K_RXKEYIX_INVALID &&
1801 !(rs.rs_status & AR5K_RXERR_CRC))
1804 if (rs.rs_status & AR5K_RXERR_MIC) {
1805 rxs.flag |= RX_FLAG_MMIC_ERROR;
1809 /* let crypto-error packets fall through in MNTR */
1811 ~(AR5K_RXERR_DECRYPT|AR5K_RXERR_MIC)) ||
1812 sc->opmode != NL80211_IFTYPE_MONITOR)
1816 next_skb = ath5k_rx_skb_alloc(sc, &next_skb_addr);
1819 * If we can't replace bf->skb with a new skb under memory
1820 * pressure, just skip this packet
1825 pci_unmap_single(sc->pdev, bf->skbaddr, sc->rxbufsize,
1826 PCI_DMA_FROMDEVICE);
1827 skb_put(skb, rs.rs_datalen);
1829 /* The MAC header is padded to have 32-bit boundary if the
1830 * packet payload is non-zero. The general calculation for
1831 * padsize would take into account odd header lengths:
1832 * padsize = (4 - hdrlen % 4) % 4; However, since only
1833 * even-length headers are used, padding can only be 0 or 2
1834 * bytes and we can optimize this a bit. In addition, we must
1835 * not try to remove padding from short control frames that do
1836 * not have payload. */
1837 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1838 padsize = ath5k_pad_size(hdrlen);
1840 memmove(skb->data + padsize, skb->data, hdrlen);
1841 skb_pull(skb, padsize);
1845 * always extend the mac timestamp, since this information is
1846 * also needed for proper IBSS merging.
1848 * XXX: it might be too late to do it here, since rs_tstamp is
1849 * 15bit only. that means TSF extension has to be done within
1850 * 32768usec (about 32ms). it might be necessary to move this to
1851 * the interrupt handler, like it is done in madwifi.
1853 * Unfortunately we don't know when the hardware takes the rx
1854 * timestamp (beginning of phy frame, data frame, end of rx?).
1855 * The only thing we know is that it is hardware specific...
1856 * On AR5213 it seems the rx timestamp is at the end of the
1857 * frame, but i'm not sure.
1859 * NOTE: mac80211 defines mactime at the beginning of the first
1860 * data symbol. Since we don't have any time references it's
1861 * impossible to comply to that. This affects IBSS merge only
1862 * right now, so it's not too bad...
1864 rxs.mactime = ath5k_extend_tsf(sc->ah, rs.rs_tstamp);
1865 rxs.flag |= RX_FLAG_TSFT;
1867 rxs.freq = sc->curchan->center_freq;
1868 rxs.band = sc->curband->band;
1870 rxs.noise = sc->ah->ah_noise_floor;
1871 rxs.signal = rxs.noise + rs.rs_rssi;
1873 /* An rssi of 35 indicates you should be able use
1874 * 54 Mbps reliably. A more elaborate scheme can be used
1875 * here but it requires a map of SNR/throughput for each
1876 * possible mode used */
1877 rxs.qual = rs.rs_rssi * 100 / 35;
1879 /* rssi can be more than 35 though, anything above that
1880 * should be considered at 100% */
1884 rxs.antenna = rs.rs_antenna;
1885 rxs.rate_idx = ath5k_hw_to_driver_rix(sc, rs.rs_rate);
1886 rxs.flag |= ath5k_rx_decrypted(sc, ds, skb, &rs);
1888 if (rxs.rate_idx >= 0 && rs.rs_rate ==
1889 sc->curband->bitrates[rxs.rate_idx].hw_value_short)
1890 rxs.flag |= RX_FLAG_SHORTPRE;
1892 ath5k_debug_dump_skb(sc, skb, "RX ", 0);
1894 /* check beacons in IBSS mode */
1895 if (sc->opmode == NL80211_IFTYPE_ADHOC)
1896 ath5k_check_ibss_tsf(sc, skb, &rxs);
1898 __ieee80211_rx(sc->hw, skb, &rxs);
1901 bf->skbaddr = next_skb_addr;
1903 list_move_tail(&bf->list, &sc->rxbuf);
1904 } while (ath5k_rxbuf_setup(sc, bf) == 0);
1906 spin_unlock(&sc->rxbuflock);
1917 ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1919 struct ath5k_tx_status ts = {};
1920 struct ath5k_buf *bf, *bf0;
1921 struct ath5k_desc *ds;
1922 struct sk_buff *skb;
1923 struct ieee80211_tx_info *info;
1926 spin_lock(&txq->lock);
1927 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1930 ret = sc->ah->ah_proc_tx_desc(sc->ah, ds, &ts);
1931 if (unlikely(ret == -EINPROGRESS))
1933 else if (unlikely(ret)) {
1934 ATH5K_ERR(sc, "error %d while processing queue %u\n",
1940 info = IEEE80211_SKB_CB(skb);
1943 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len,
1946 ieee80211_tx_info_clear_status(info);
1947 for (i = 0; i < 4; i++) {
1948 struct ieee80211_tx_rate *r =
1949 &info->status.rates[i];
1951 if (ts.ts_rate[i]) {
1952 r->idx = ath5k_hw_to_driver_rix(sc, ts.ts_rate[i]);
1953 r->count = ts.ts_retry[i];
1960 /* count the successful attempt as well */
1961 info->status.rates[ts.ts_final_idx].count++;
1963 if (unlikely(ts.ts_status)) {
1964 sc->ll_stats.dot11ACKFailureCount++;
1965 if (ts.ts_status & AR5K_TXERR_FILT)
1966 info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
1968 info->flags |= IEEE80211_TX_STAT_ACK;
1969 info->status.ack_signal = ts.ts_rssi;
1972 ieee80211_tx_status(sc->hw, skb);
1973 sc->tx_stats[txq->qnum].count++;
1975 spin_lock(&sc->txbuflock);
1976 sc->tx_stats[txq->qnum].len--;
1977 list_move_tail(&bf->list, &sc->txbuf);
1979 spin_unlock(&sc->txbuflock);
1981 if (likely(list_empty(&txq->q)))
1983 spin_unlock(&txq->lock);
1984 if (sc->txbuf_len > ATH_TXBUF / 5)
1985 ieee80211_wake_queues(sc->hw);
1989 ath5k_tasklet_tx(unsigned long data)
1991 struct ath5k_softc *sc = (void *)data;
1993 ath5k_tx_processq(sc, sc->txq);
2002 * Setup the beacon frame for transmit.
2005 ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
2007 struct sk_buff *skb = bf->skb;
2008 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2009 struct ath5k_hw *ah = sc->ah;
2010 struct ath5k_desc *ds;
2011 int ret, antenna = 0;
2014 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
2016 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
2017 "skbaddr %llx\n", skb, skb->data, skb->len,
2018 (unsigned long long)bf->skbaddr);
2019 if (pci_dma_mapping_error(sc->pdev, bf->skbaddr)) {
2020 ATH5K_ERR(sc, "beacon DMA mapping failed\n");
2026 flags = AR5K_TXDESC_NOACK;
2027 if (sc->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) {
2028 ds->ds_link = bf->daddr; /* self-linked */
2029 flags |= AR5K_TXDESC_VEOL;
2031 * Let hardware handle antenna switching if txantenna is not set
2036 * Switch antenna every 4 beacons if txantenna is not set
2037 * XXX assumes two antennas
2040 antenna = sc->bsent & 4 ? 2 : 1;
2043 /* FIXME: If we are in g mode and rate is a CCK rate
2044 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
2045 * from tx power (value is in dB units already) */
2046 ds->ds_data = bf->skbaddr;
2047 ret = ah->ah_setup_tx_desc(ah, ds, skb->len,
2048 ieee80211_get_hdrlen_from_skb(skb),
2049 AR5K_PKT_TYPE_BEACON, (sc->power_level * 2),
2050 ieee80211_get_tx_rate(sc->hw, info)->hw_value,
2051 1, AR5K_TXKEYIX_INVALID,
2052 antenna, flags, 0, 0);
2058 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
2063 * Transmit a beacon frame at SWBA. Dynamic updates to the
2064 * frame contents are done as needed and the slot time is
2065 * also adjusted based on current state.
2067 * This is called from software irq context (beacontq or restq
2068 * tasklets) or user context from ath5k_beacon_config.
2071 ath5k_beacon_send(struct ath5k_softc *sc)
2073 struct ath5k_buf *bf = sc->bbuf;
2074 struct ath5k_hw *ah = sc->ah;
2076 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "in beacon_send\n");
2078 if (unlikely(bf->skb == NULL || sc->opmode == NL80211_IFTYPE_STATION ||
2079 sc->opmode == NL80211_IFTYPE_MONITOR)) {
2080 ATH5K_WARN(sc, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL);
2084 * Check if the previous beacon has gone out. If
2085 * not don't don't try to post another, skip this
2086 * period and wait for the next. Missed beacons
2087 * indicate a problem and should not occur. If we
2088 * miss too many consecutive beacons reset the device.
2090 if (unlikely(ath5k_hw_num_tx_pending(ah, sc->bhalq) != 0)) {
2092 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2093 "missed %u consecutive beacons\n", sc->bmisscount);
2094 if (sc->bmisscount > 10) { /* NB: 10 is a guess */
2095 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2096 "stuck beacon time (%u missed)\n",
2098 tasklet_schedule(&sc->restq);
2102 if (unlikely(sc->bmisscount != 0)) {
2103 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2104 "resume beacon xmit after %u misses\n",
2110 * Stop any current dma and put the new frame on the queue.
2111 * This should never fail since we check above that no frames
2112 * are still pending on the queue.
2114 if (unlikely(ath5k_hw_stop_tx_dma(ah, sc->bhalq))) {
2115 ATH5K_WARN(sc, "beacon queue %u didn't start/stop ?\n", sc->bhalq);
2116 /* NB: hw still stops DMA, so proceed */
2119 /* Note: Beacon buffer is updated on beacon_update when mac80211
2120 * calls config_interface */
2121 ath5k_hw_set_txdp(ah, sc->bhalq, bf->daddr);
2122 ath5k_hw_start_tx_dma(ah, sc->bhalq);
2123 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
2124 sc->bhalq, (unsigned long long)bf->daddr, bf->desc);
2131 * ath5k_beacon_update_timers - update beacon timers
2133 * @sc: struct ath5k_softc pointer we are operating on
2134 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
2135 * beacon timer update based on the current HW TSF.
2137 * Calculate the next target beacon transmit time (TBTT) based on the timestamp
2138 * of a received beacon or the current local hardware TSF and write it to the
2139 * beacon timer registers.
2141 * This is called in a variety of situations, e.g. when a beacon is received,
2142 * when a TSF update has been detected, but also when an new IBSS is created or
2143 * when we otherwise know we have to update the timers, but we keep it in this
2144 * function to have it all together in one place.
2147 ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
2149 struct ath5k_hw *ah = sc->ah;
2150 u32 nexttbtt, intval, hw_tu, bc_tu;
2153 intval = sc->bintval & AR5K_BEACON_PERIOD;
2154 if (WARN_ON(!intval))
2157 /* beacon TSF converted to TU */
2158 bc_tu = TSF_TO_TU(bc_tsf);
2160 /* current TSF converted to TU */
2161 hw_tsf = ath5k_hw_get_tsf64(ah);
2162 hw_tu = TSF_TO_TU(hw_tsf);
2165 /* we use FUDGE to make sure the next TBTT is ahead of the current TU */
2168 * no beacons received, called internally.
2169 * just need to refresh timers based on HW TSF.
2171 nexttbtt = roundup(hw_tu + FUDGE, intval);
2172 } else if (bc_tsf == 0) {
2174 * no beacon received, probably called by ath5k_reset_tsf().
2175 * reset TSF to start with 0.
2178 intval |= AR5K_BEACON_RESET_TSF;
2179 } else if (bc_tsf > hw_tsf) {
2181 * beacon received, SW merge happend but HW TSF not yet updated.
2182 * not possible to reconfigure timers yet, but next time we
2183 * receive a beacon with the same BSSID, the hardware will
2184 * automatically update the TSF and then we need to reconfigure
2187 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2188 "need to wait for HW TSF sync\n");
2192 * most important case for beacon synchronization between STA.
2194 * beacon received and HW TSF has been already updated by HW.
2195 * update next TBTT based on the TSF of the beacon, but make
2196 * sure it is ahead of our local TSF timer.
2198 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval);
2202 sc->nexttbtt = nexttbtt;
2204 intval |= AR5K_BEACON_ENA;
2205 ath5k_hw_init_beacon(ah, nexttbtt, intval);
2208 * debugging output last in order to preserve the time critical aspect
2212 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2213 "reconfigured timers based on HW TSF\n");
2214 else if (bc_tsf == 0)
2215 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2216 "reset HW TSF and timers\n");
2218 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2219 "updated timers based on beacon TSF\n");
2221 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2222 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2223 (unsigned long long) bc_tsf,
2224 (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt);
2225 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "intval %u %s %s\n",
2226 intval & AR5K_BEACON_PERIOD,
2227 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "",
2228 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : "");
2233 * ath5k_beacon_config - Configure the beacon queues and interrupts
2235 * @sc: struct ath5k_softc pointer we are operating on
2237 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
2238 * interrupts to detect TSF updates only.
2241 ath5k_beacon_config(struct ath5k_softc *sc)
2243 struct ath5k_hw *ah = sc->ah;
2244 unsigned long flags;
2246 ath5k_hw_set_imr(ah, 0);
2248 sc->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA);
2250 if (sc->opmode == NL80211_IFTYPE_ADHOC ||
2251 sc->opmode == NL80211_IFTYPE_MESH_POINT ||
2252 sc->opmode == NL80211_IFTYPE_AP) {
2254 * In IBSS mode we use a self-linked tx descriptor and let the
2255 * hardware send the beacons automatically. We have to load it
2257 * We use the SWBA interrupt only to keep track of the beacon
2258 * timers in order to detect automatic TSF updates.
2260 ath5k_beaconq_config(sc);
2262 sc->imask |= AR5K_INT_SWBA;
2264 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
2265 if (ath5k_hw_hasveol(ah)) {
2266 spin_lock_irqsave(&sc->block, flags);
2267 ath5k_beacon_send(sc);
2268 spin_unlock_irqrestore(&sc->block, flags);
2271 ath5k_beacon_update_timers(sc, -1);
2274 ath5k_hw_set_imr(ah, sc->imask);
2277 static void ath5k_tasklet_beacon(unsigned long data)
2279 struct ath5k_softc *sc = (struct ath5k_softc *) data;
2282 * Software beacon alert--time to send a beacon.
2284 * In IBSS mode we use this interrupt just to
2285 * keep track of the next TBTT (target beacon
2286 * transmission time) in order to detect wether
2287 * automatic TSF updates happened.
2289 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
2290 /* XXX: only if VEOL suppported */
2291 u64 tsf = ath5k_hw_get_tsf64(sc->ah);
2292 sc->nexttbtt += sc->bintval;
2293 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2294 "SWBA nexttbtt: %x hw_tu: %x "
2298 (unsigned long long) tsf);
2300 spin_lock(&sc->block);
2301 ath5k_beacon_send(sc);
2302 spin_unlock(&sc->block);
2307 /********************\
2308 * Interrupt handling *
2309 \********************/
2312 ath5k_init(struct ath5k_softc *sc)
2314 struct ath5k_hw *ah = sc->ah;
2317 mutex_lock(&sc->lock);
2319 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mode %d\n", sc->opmode);
2322 * Stop anything previously setup. This is safe
2323 * no matter this is the first time through or not.
2325 ath5k_stop_locked(sc);
2328 * The basic interface to setting the hardware in a good
2329 * state is ``reset''. On return the hardware is known to
2330 * be powered up and with interrupts disabled. This must
2331 * be followed by initialization of the appropriate bits
2332 * and then setup of the interrupt mask.
2334 sc->curchan = sc->hw->conf.channel;
2335 sc->curband = &sc->sbands[sc->curchan->band];
2336 sc->imask = AR5K_INT_RXOK | AR5K_INT_RXERR | AR5K_INT_RXEOL |
2337 AR5K_INT_RXORN | AR5K_INT_TXDESC | AR5K_INT_TXEOL |
2338 AR5K_INT_FATAL | AR5K_INT_GLOBAL;
2339 ret = ath5k_reset(sc, false, false);
2344 * Reset the key cache since some parts do not reset the
2345 * contents on initial power up or resume from suspend.
2347 for (i = 0; i < AR5K_KEYTABLE_SIZE; i++)
2348 ath5k_hw_reset_key(ah, i);
2350 /* Set ack to be sent at low bit-rates */
2351 ath5k_hw_set_ack_bitrate_high(ah, false);
2353 mod_timer(&sc->calib_tim, round_jiffies(jiffies +
2354 msecs_to_jiffies(ath5k_calinterval * 1000)));
2359 mutex_unlock(&sc->lock);
2364 ath5k_stop_locked(struct ath5k_softc *sc)
2366 struct ath5k_hw *ah = sc->ah;
2368 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "invalid %u\n",
2369 test_bit(ATH_STAT_INVALID, sc->status));
2372 * Shutdown the hardware and driver:
2373 * stop output from above
2374 * disable interrupts
2376 * turn off the radio
2377 * clear transmit machinery
2378 * clear receive machinery
2379 * drain and release tx queues
2380 * reclaim beacon resources
2381 * power down hardware
2383 * Note that some of this work is not possible if the
2384 * hardware is gone (invalid).
2386 ieee80211_stop_queues(sc->hw);
2388 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2390 ath5k_hw_set_imr(ah, 0);
2391 synchronize_irq(sc->pdev->irq);
2393 ath5k_txq_cleanup(sc);
2394 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2396 ath5k_hw_phy_disable(ah);
2404 * Stop the device, grabbing the top-level lock to protect
2405 * against concurrent entry through ath5k_init (which can happen
2406 * if another thread does a system call and the thread doing the
2407 * stop is preempted).
2410 ath5k_stop_hw(struct ath5k_softc *sc)
2414 mutex_lock(&sc->lock);
2415 ret = ath5k_stop_locked(sc);
2416 if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) {
2418 * Set the chip in full sleep mode. Note that we are
2419 * careful to do this only when bringing the interface
2420 * completely to a stop. When the chip is in this state
2421 * it must be carefully woken up or references to
2422 * registers in the PCI clock domain may freeze the bus
2423 * (and system). This varies by chip and is mostly an
2424 * issue with newer parts that go to sleep more quickly.
2426 if (sc->ah->ah_mac_srev >= 0x78) {
2429 * don't put newer MAC revisions > 7.8 to sleep because
2430 * of the above mentioned problems
2432 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mac version > 7.8, "
2433 "not putting device to sleep\n");
2435 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2436 "putting device to full sleep\n");
2437 ath5k_hw_set_power(sc->ah, AR5K_PM_FULL_SLEEP, true, 0);
2440 ath5k_txbuf_free(sc, sc->bbuf);
2443 mutex_unlock(&sc->lock);
2445 del_timer_sync(&sc->calib_tim);
2446 tasklet_kill(&sc->rxtq);
2447 tasklet_kill(&sc->txtq);
2448 tasklet_kill(&sc->restq);
2449 tasklet_kill(&sc->beacontq);
2455 ath5k_intr(int irq, void *dev_id)
2457 struct ath5k_softc *sc = dev_id;
2458 struct ath5k_hw *ah = sc->ah;
2459 enum ath5k_int status;
2460 unsigned int counter = 1000;
2462 if (unlikely(test_bit(ATH_STAT_INVALID, sc->status) ||
2463 !ath5k_hw_is_intr_pending(ah)))
2467 ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */
2468 ATH5K_DBG(sc, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
2470 if (unlikely(status & AR5K_INT_FATAL)) {
2472 * Fatal errors are unrecoverable.
2473 * Typically these are caused by DMA errors.
2475 tasklet_schedule(&sc->restq);
2476 } else if (unlikely(status & AR5K_INT_RXORN)) {
2477 tasklet_schedule(&sc->restq);
2479 if (status & AR5K_INT_SWBA) {
2480 tasklet_hi_schedule(&sc->beacontq);
2482 if (status & AR5K_INT_RXEOL) {
2484 * NB: the hardware should re-read the link when
2485 * RXE bit is written, but it doesn't work at
2486 * least on older hardware revs.
2490 if (status & AR5K_INT_TXURN) {
2491 /* bump tx trigger level */
2492 ath5k_hw_update_tx_triglevel(ah, true);
2494 if (status & (AR5K_INT_RXOK | AR5K_INT_RXERR))
2495 tasklet_schedule(&sc->rxtq);
2496 if (status & (AR5K_INT_TXOK | AR5K_INT_TXDESC
2497 | AR5K_INT_TXERR | AR5K_INT_TXEOL))
2498 tasklet_schedule(&sc->txtq);
2499 if (status & AR5K_INT_BMISS) {
2502 if (status & AR5K_INT_MIB) {
2504 * These stats are also used for ANI i think
2505 * so how about updating them more often ?
2507 ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
2510 } while (ath5k_hw_is_intr_pending(ah) && --counter > 0);
2512 if (unlikely(!counter))
2513 ATH5K_WARN(sc, "too many interrupts, giving up for now\n");
2519 ath5k_tasklet_reset(unsigned long data)
2521 struct ath5k_softc *sc = (void *)data;
2523 ath5k_reset_wake(sc);
2527 * Periodically recalibrate the PHY to account
2528 * for temperature/environment changes.
2531 ath5k_calibrate(unsigned long data)
2533 struct ath5k_softc *sc = (void *)data;
2534 struct ath5k_hw *ah = sc->ah;
2536 ATH5K_DBG(sc, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
2537 ieee80211_frequency_to_channel(sc->curchan->center_freq),
2538 sc->curchan->hw_value);
2540 if (ath5k_hw_gainf_calibrate(ah) == AR5K_RFGAIN_NEED_CHANGE) {
2542 * Rfgain is out of bounds, reset the chip
2543 * to load new gain values.
2545 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "calibration, resetting\n");
2546 ath5k_reset_wake(sc);
2548 if (ath5k_hw_phy_calibrate(ah, sc->curchan))
2549 ATH5K_ERR(sc, "calibration of channel %u failed\n",
2550 ieee80211_frequency_to_channel(
2551 sc->curchan->center_freq));
2553 mod_timer(&sc->calib_tim, round_jiffies(jiffies +
2554 msecs_to_jiffies(ath5k_calinterval * 1000)));
2558 /********************\
2559 * Mac80211 functions *
2560 \********************/
2563 ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
2565 struct ath5k_softc *sc = hw->priv;
2566 struct ath5k_buf *bf;
2567 unsigned long flags;
2571 ath5k_debug_dump_skb(sc, skb, "TX ", 1);
2573 if (sc->opmode == NL80211_IFTYPE_MONITOR)
2574 ATH5K_DBG(sc, ATH5K_DEBUG_XMIT, "tx in monitor (scan?)\n");
2577 * the hardware expects the header padded to 4 byte boundaries
2578 * if this is not the case we add the padding after the header
2580 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2581 padsize = ath5k_pad_size(hdrlen);
2584 if (skb_headroom(skb) < padsize) {
2585 ATH5K_ERR(sc, "tx hdrlen not %%4: %d not enough"
2586 " headroom to pad %d\n", hdrlen, padsize);
2589 skb_push(skb, padsize);
2590 memmove(skb->data, skb->data+padsize, hdrlen);
2593 spin_lock_irqsave(&sc->txbuflock, flags);
2594 if (list_empty(&sc->txbuf)) {
2595 ATH5K_ERR(sc, "no further txbuf available, dropping packet\n");
2596 spin_unlock_irqrestore(&sc->txbuflock, flags);
2597 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
2600 bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list);
2601 list_del(&bf->list);
2603 if (list_empty(&sc->txbuf))
2604 ieee80211_stop_queues(hw);
2605 spin_unlock_irqrestore(&sc->txbuflock, flags);
2609 if (ath5k_txbuf_setup(sc, bf)) {
2611 spin_lock_irqsave(&sc->txbuflock, flags);
2612 list_add_tail(&bf->list, &sc->txbuf);
2614 spin_unlock_irqrestore(&sc->txbuflock, flags);
2617 return NETDEV_TX_OK;
2620 dev_kfree_skb_any(skb);
2621 return NETDEV_TX_OK;
2625 ath5k_reset(struct ath5k_softc *sc, bool stop, bool change_channel)
2627 struct ath5k_hw *ah = sc->ah;
2630 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n");
2633 ath5k_hw_set_imr(ah, 0);
2634 ath5k_txq_cleanup(sc);
2637 ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, true);
2639 ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret);
2643 ret = ath5k_rx_start(sc);
2645 ATH5K_ERR(sc, "can't start recv logic\n");
2650 * Change channels and update the h/w rate map if we're switching;
2651 * e.g. 11a to 11b/g.
2653 * We may be doing a reset in response to an ioctl that changes the
2654 * channel so update any state that might change as a result.
2658 /* ath5k_chan_change(sc, c); */
2660 ath5k_beacon_config(sc);
2661 /* intrs are enabled by ath5k_beacon_config */
2669 ath5k_reset_wake(struct ath5k_softc *sc)
2673 ret = ath5k_reset(sc, true, true);
2675 ieee80211_wake_queues(sc->hw);
2680 static int ath5k_start(struct ieee80211_hw *hw)
2682 return ath5k_init(hw->priv);
2685 static void ath5k_stop(struct ieee80211_hw *hw)
2687 ath5k_stop_hw(hw->priv);
2690 static int ath5k_add_interface(struct ieee80211_hw *hw,
2691 struct ieee80211_if_init_conf *conf)
2693 struct ath5k_softc *sc = hw->priv;
2696 mutex_lock(&sc->lock);
2702 sc->vif = conf->vif;
2704 switch (conf->type) {
2705 case NL80211_IFTYPE_AP:
2706 case NL80211_IFTYPE_STATION:
2707 case NL80211_IFTYPE_ADHOC:
2708 case NL80211_IFTYPE_MESH_POINT:
2709 case NL80211_IFTYPE_MONITOR:
2710 sc->opmode = conf->type;
2717 /* Set to a reasonable value. Note that this will
2718 * be set to mac80211's value at ath5k_config(). */
2720 ath5k_hw_set_lladdr(sc->ah, conf->mac_addr);
2724 mutex_unlock(&sc->lock);
2729 ath5k_remove_interface(struct ieee80211_hw *hw,
2730 struct ieee80211_if_init_conf *conf)
2732 struct ath5k_softc *sc = hw->priv;
2733 u8 mac[ETH_ALEN] = {};
2735 mutex_lock(&sc->lock);
2736 if (sc->vif != conf->vif)
2739 ath5k_hw_set_lladdr(sc->ah, mac);
2742 mutex_unlock(&sc->lock);
2746 * TODO: Phy disable/diversity etc
2749 ath5k_config(struct ieee80211_hw *hw, u32 changed)
2751 struct ath5k_softc *sc = hw->priv;
2752 struct ath5k_hw *ah = sc->ah;
2753 struct ieee80211_conf *conf = &hw->conf;
2756 mutex_lock(&sc->lock);
2758 sc->bintval = conf->beacon_int;
2760 if ((changed & IEEE80211_CONF_CHANGE_POWER) &&
2761 (sc->power_level != conf->power_level)) {
2762 sc->power_level = conf->power_level;
2765 ath5k_hw_set_txpower_limit(ah, (conf->power_level * 2));
2768 ret = ath5k_chan_set(sc, conf->channel);
2770 mutex_unlock(&sc->lock);
2774 #define SUPPORTED_FIF_FLAGS \
2775 FIF_PROMISC_IN_BSS | FIF_ALLMULTI | FIF_FCSFAIL | \
2776 FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \
2777 FIF_BCN_PRBRESP_PROMISC
2779 * o always accept unicast, broadcast, and multicast traffic
2780 * o multicast traffic for all BSSIDs will be enabled if mac80211
2782 * o maintain current state of phy ofdm or phy cck error reception.
2783 * If the hardware detects any of these type of errors then
2784 * ath5k_hw_get_rx_filter() will pass to us the respective
2785 * hardware filters to be able to receive these type of frames.
2786 * o probe request frames are accepted only when operating in
2787 * hostap, adhoc, or monitor modes
2788 * o enable promiscuous mode according to the interface state
2790 * - when operating in adhoc mode so the 802.11 layer creates
2791 * node table entries for peers,
2792 * - when operating in station mode for collecting rssi data when
2793 * the station is otherwise quiet, or
2796 static void ath5k_configure_filter(struct ieee80211_hw *hw,
2797 unsigned int changed_flags,
2798 unsigned int *new_flags,
2799 int mc_count, struct dev_mc_list *mclist)
2801 struct ath5k_softc *sc = hw->priv;
2802 struct ath5k_hw *ah = sc->ah;
2803 u32 mfilt[2], val, rfilt;
2810 /* Only deal with supported flags */
2811 changed_flags &= SUPPORTED_FIF_FLAGS;
2812 *new_flags &= SUPPORTED_FIF_FLAGS;
2814 /* If HW detects any phy or radar errors, leave those filters on.
2815 * Also, always enable Unicast, Broadcasts and Multicast
2816 * XXX: move unicast, bssid broadcasts and multicast to mac80211 */
2817 rfilt = (ath5k_hw_get_rx_filter(ah) & (AR5K_RX_FILTER_PHYERR)) |
2818 (AR5K_RX_FILTER_UCAST | AR5K_RX_FILTER_BCAST |
2819 AR5K_RX_FILTER_MCAST);
2821 if (changed_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS)) {
2822 if (*new_flags & FIF_PROMISC_IN_BSS) {
2823 rfilt |= AR5K_RX_FILTER_PROM;
2824 __set_bit(ATH_STAT_PROMISC, sc->status);
2826 __clear_bit(ATH_STAT_PROMISC, sc->status);
2830 /* Note, AR5K_RX_FILTER_MCAST is already enabled */
2831 if (*new_flags & FIF_ALLMULTI) {
2835 for (i = 0; i < mc_count; i++) {
2838 /* calculate XOR of eight 6-bit values */
2839 val = get_unaligned_le32(mclist->dmi_addr + 0);
2840 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2841 val = get_unaligned_le32(mclist->dmi_addr + 3);
2842 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2844 mfilt[pos / 32] |= (1 << (pos % 32));
2845 /* XXX: we might be able to just do this instead,
2846 * but not sure, needs testing, if we do use this we'd
2847 * neet to inform below to not reset the mcast */
2848 /* ath5k_hw_set_mcast_filterindex(ah,
2849 * mclist->dmi_addr[5]); */
2850 mclist = mclist->next;
2854 /* This is the best we can do */
2855 if (*new_flags & (FIF_FCSFAIL | FIF_PLCPFAIL))
2856 rfilt |= AR5K_RX_FILTER_PHYERR;
2858 /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons
2859 * and probes for any BSSID, this needs testing */
2860 if (*new_flags & FIF_BCN_PRBRESP_PROMISC)
2861 rfilt |= AR5K_RX_FILTER_BEACON | AR5K_RX_FILTER_PROBEREQ;
2863 /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not
2864 * set we should only pass on control frames for this
2865 * station. This needs testing. I believe right now this
2866 * enables *all* control frames, which is OK.. but
2867 * but we should see if we can improve on granularity */
2868 if (*new_flags & FIF_CONTROL)
2869 rfilt |= AR5K_RX_FILTER_CONTROL;
2871 /* Additional settings per mode -- this is per ath5k */
2873 /* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */
2875 if (sc->opmode == NL80211_IFTYPE_MONITOR)
2876 rfilt |= AR5K_RX_FILTER_CONTROL | AR5K_RX_FILTER_BEACON |
2877 AR5K_RX_FILTER_PROBEREQ | AR5K_RX_FILTER_PROM;
2878 if (sc->opmode != NL80211_IFTYPE_STATION)
2879 rfilt |= AR5K_RX_FILTER_PROBEREQ;
2880 if (sc->opmode != NL80211_IFTYPE_AP &&
2881 sc->opmode != NL80211_IFTYPE_MESH_POINT &&
2882 test_bit(ATH_STAT_PROMISC, sc->status))
2883 rfilt |= AR5K_RX_FILTER_PROM;
2884 if ((sc->opmode == NL80211_IFTYPE_STATION && sc->assoc) ||
2885 sc->opmode == NL80211_IFTYPE_ADHOC ||
2886 sc->opmode == NL80211_IFTYPE_AP)
2887 rfilt |= AR5K_RX_FILTER_BEACON;
2888 if (sc->opmode == NL80211_IFTYPE_MESH_POINT)
2889 rfilt |= AR5K_RX_FILTER_CONTROL | AR5K_RX_FILTER_BEACON |
2890 AR5K_RX_FILTER_PROBEREQ | AR5K_RX_FILTER_PROM;
2893 ath5k_hw_set_rx_filter(ah, rfilt);
2895 /* Set multicast bits */
2896 ath5k_hw_set_mcast_filter(ah, mfilt[0], mfilt[1]);
2897 /* Set the cached hw filter flags, this will alter actually
2899 sc->filter_flags = rfilt;
2903 ath5k_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
2904 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
2905 struct ieee80211_key_conf *key)
2907 struct ath5k_softc *sc = hw->priv;
2910 if (modparam_nohwcrypt)
2924 mutex_lock(&sc->lock);
2928 ret = ath5k_hw_set_key(sc->ah, key->keyidx, key,
2929 sta ? sta->addr : NULL);
2931 ATH5K_ERR(sc, "can't set the key\n");
2934 __set_bit(key->keyidx, sc->keymap);
2935 key->hw_key_idx = key->keyidx;
2936 key->flags |= (IEEE80211_KEY_FLAG_GENERATE_IV |
2937 IEEE80211_KEY_FLAG_GENERATE_MMIC);
2940 ath5k_hw_reset_key(sc->ah, key->keyidx);
2941 __clear_bit(key->keyidx, sc->keymap);
2950 mutex_unlock(&sc->lock);
2955 ath5k_get_stats(struct ieee80211_hw *hw,
2956 struct ieee80211_low_level_stats *stats)
2958 struct ath5k_softc *sc = hw->priv;
2959 struct ath5k_hw *ah = sc->ah;
2962 ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
2964 memcpy(stats, &sc->ll_stats, sizeof(sc->ll_stats));
2970 ath5k_get_tx_stats(struct ieee80211_hw *hw,
2971 struct ieee80211_tx_queue_stats *stats)
2973 struct ath5k_softc *sc = hw->priv;
2975 memcpy(stats, &sc->tx_stats, sizeof(sc->tx_stats));
2981 ath5k_get_tsf(struct ieee80211_hw *hw)
2983 struct ath5k_softc *sc = hw->priv;
2985 return ath5k_hw_get_tsf64(sc->ah);
2989 ath5k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
2991 struct ath5k_softc *sc = hw->priv;
2993 ath5k_hw_set_tsf64(sc->ah, tsf);
2997 ath5k_reset_tsf(struct ieee80211_hw *hw)
2999 struct ath5k_softc *sc = hw->priv;
3002 * in IBSS mode we need to update the beacon timers too.
3003 * this will also reset the TSF if we call it with 0
3005 if (sc->opmode == NL80211_IFTYPE_ADHOC)
3006 ath5k_beacon_update_timers(sc, 0);
3008 ath5k_hw_reset_tsf(sc->ah);
3012 ath5k_beacon_update(struct ath5k_softc *sc, struct sk_buff *skb)
3014 unsigned long flags;
3017 ath5k_debug_dump_skb(sc, skb, "BC ", 1);
3019 spin_lock_irqsave(&sc->block, flags);
3020 ath5k_txbuf_free(sc, sc->bbuf);
3021 sc->bbuf->skb = skb;
3022 ret = ath5k_beacon_setup(sc, sc->bbuf);
3024 sc->bbuf->skb = NULL;
3025 spin_unlock_irqrestore(&sc->block, flags);
3027 ath5k_beacon_config(sc);
3034 set_beacon_filter(struct ieee80211_hw *hw, bool enable)
3036 struct ath5k_softc *sc = hw->priv;
3037 struct ath5k_hw *ah = sc->ah;
3039 rfilt = ath5k_hw_get_rx_filter(ah);
3041 rfilt |= AR5K_RX_FILTER_BEACON;
3043 rfilt &= ~AR5K_RX_FILTER_BEACON;
3044 ath5k_hw_set_rx_filter(ah, rfilt);
3045 sc->filter_flags = rfilt;
3048 static void ath5k_bss_info_changed(struct ieee80211_hw *hw,
3049 struct ieee80211_vif *vif,
3050 struct ieee80211_bss_conf *bss_conf,
3053 struct ath5k_softc *sc = hw->priv;
3054 struct ath5k_hw *ah = sc->ah;
3056 mutex_lock(&sc->lock);
3057 if (WARN_ON(sc->vif != vif))
3060 if (changes & BSS_CHANGED_BSSID) {
3061 /* Cache for later use during resets */
3062 memcpy(ah->ah_bssid, bss_conf->bssid, ETH_ALEN);
3063 /* XXX: assoc id is set to 0 for now, mac80211 doesn't have
3064 * a clean way of letting us retrieve this yet. */
3065 ath5k_hw_set_associd(ah, ah->ah_bssid, 0);
3069 if (changes & BSS_CHANGED_BEACON_INT)
3070 sc->bintval = bss_conf->beacon_int;
3072 if (changes & BSS_CHANGED_ASSOC) {
3073 sc->assoc = bss_conf->assoc;
3074 if (sc->opmode == NL80211_IFTYPE_STATION)
3075 set_beacon_filter(hw, sc->assoc);
3078 if (changes & BSS_CHANGED_BEACON &&
3079 (vif->type == NL80211_IFTYPE_ADHOC ||
3080 vif->type == NL80211_IFTYPE_MESH_POINT ||
3081 vif->type == NL80211_IFTYPE_AP)) {
3082 struct sk_buff *beacon = ieee80211_beacon_get(hw, vif);
3085 ath5k_beacon_update(sc, beacon);
3089 mutex_unlock(&sc->lock);