2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
4 * Copyright (c) 2006 Devicescape Software, Inc.
5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39 * THE POSSIBILITY OF SUCH DAMAGES.
43 #include <linux/module.h>
44 #include <linux/delay.h>
45 #include <linux/hardirq.h>
48 #include <linux/netdevice.h>
49 #include <linux/cache.h>
50 #include <linux/pci.h>
51 #include <linux/pci-aspm.h>
52 #include <linux/ethtool.h>
53 #include <linux/uaccess.h>
54 #include <linux/slab.h>
55 #include <linux/etherdevice.h>
57 #include <net/ieee80211_radiotap.h>
59 #include <asm/unaligned.h>
66 static int modparam_nohwcrypt;
67 module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
68 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
70 static int modparam_all_channels;
71 module_param_named(all_channels, modparam_all_channels, bool, S_IRUGO);
72 MODULE_PARM_DESC(all_channels, "Expose all channels the device can use.");
75 MODULE_AUTHOR("Jiri Slaby");
76 MODULE_AUTHOR("Nick Kossifidis");
77 MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
78 MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
79 MODULE_LICENSE("Dual BSD/GPL");
80 MODULE_VERSION("0.6.0 (EXPERIMENTAL)");
82 static int ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan);
83 static int ath5k_beacon_update(struct ieee80211_hw *hw,
84 struct ieee80211_vif *vif);
85 static void ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf);
88 static DEFINE_PCI_DEVICE_TABLE(ath5k_pci_id_table) = {
89 { PCI_VDEVICE(ATHEROS, 0x0207) }, /* 5210 early */
90 { PCI_VDEVICE(ATHEROS, 0x0007) }, /* 5210 */
91 { PCI_VDEVICE(ATHEROS, 0x0011) }, /* 5311 - this is on AHB bus !*/
92 { PCI_VDEVICE(ATHEROS, 0x0012) }, /* 5211 */
93 { PCI_VDEVICE(ATHEROS, 0x0013) }, /* 5212 */
94 { PCI_VDEVICE(3COM_2, 0x0013) }, /* 3com 5212 */
95 { PCI_VDEVICE(3COM, 0x0013) }, /* 3com 3CRDAG675 5212 */
96 { PCI_VDEVICE(ATHEROS, 0x1014) }, /* IBM minipci 5212 */
97 { PCI_VDEVICE(ATHEROS, 0x0014) }, /* 5212 combatible */
98 { PCI_VDEVICE(ATHEROS, 0x0015) }, /* 5212 combatible */
99 { PCI_VDEVICE(ATHEROS, 0x0016) }, /* 5212 combatible */
100 { PCI_VDEVICE(ATHEROS, 0x0017) }, /* 5212 combatible */
101 { PCI_VDEVICE(ATHEROS, 0x0018) }, /* 5212 combatible */
102 { PCI_VDEVICE(ATHEROS, 0x0019) }, /* 5212 combatible */
103 { PCI_VDEVICE(ATHEROS, 0x001a) }, /* 2413 Griffin-lite */
104 { PCI_VDEVICE(ATHEROS, 0x001b) }, /* 5413 Eagle */
105 { PCI_VDEVICE(ATHEROS, 0x001c) }, /* PCI-E cards */
106 { PCI_VDEVICE(ATHEROS, 0x001d) }, /* 2417 Nala */
109 MODULE_DEVICE_TABLE(pci, ath5k_pci_id_table);
112 static const struct ath5k_srev_name srev_names[] = {
113 { "5210", AR5K_VERSION_MAC, AR5K_SREV_AR5210 },
114 { "5311", AR5K_VERSION_MAC, AR5K_SREV_AR5311 },
115 { "5311A", AR5K_VERSION_MAC, AR5K_SREV_AR5311A },
116 { "5311B", AR5K_VERSION_MAC, AR5K_SREV_AR5311B },
117 { "5211", AR5K_VERSION_MAC, AR5K_SREV_AR5211 },
118 { "5212", AR5K_VERSION_MAC, AR5K_SREV_AR5212 },
119 { "5213", AR5K_VERSION_MAC, AR5K_SREV_AR5213 },
120 { "5213A", AR5K_VERSION_MAC, AR5K_SREV_AR5213A },
121 { "2413", AR5K_VERSION_MAC, AR5K_SREV_AR2413 },
122 { "2414", AR5K_VERSION_MAC, AR5K_SREV_AR2414 },
123 { "5424", AR5K_VERSION_MAC, AR5K_SREV_AR5424 },
124 { "5413", AR5K_VERSION_MAC, AR5K_SREV_AR5413 },
125 { "5414", AR5K_VERSION_MAC, AR5K_SREV_AR5414 },
126 { "2415", AR5K_VERSION_MAC, AR5K_SREV_AR2415 },
127 { "5416", AR5K_VERSION_MAC, AR5K_SREV_AR5416 },
128 { "5418", AR5K_VERSION_MAC, AR5K_SREV_AR5418 },
129 { "2425", AR5K_VERSION_MAC, AR5K_SREV_AR2425 },
130 { "2417", AR5K_VERSION_MAC, AR5K_SREV_AR2417 },
131 { "xxxxx", AR5K_VERSION_MAC, AR5K_SREV_UNKNOWN },
132 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 },
133 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 },
134 { "5111A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111A },
135 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 },
136 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 },
137 { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A },
138 { "5112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112B },
139 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 },
140 { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A },
141 { "2112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112B },
142 { "2413", AR5K_VERSION_RAD, AR5K_SREV_RAD_2413 },
143 { "5413", AR5K_VERSION_RAD, AR5K_SREV_RAD_5413 },
144 { "2316", AR5K_VERSION_RAD, AR5K_SREV_RAD_2316 },
145 { "2317", AR5K_VERSION_RAD, AR5K_SREV_RAD_2317 },
146 { "5424", AR5K_VERSION_RAD, AR5K_SREV_RAD_5424 },
147 { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 },
148 { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN },
151 static const struct ieee80211_rate ath5k_rates[] = {
153 .hw_value = ATH5K_RATE_CODE_1M, },
155 .hw_value = ATH5K_RATE_CODE_2M,
156 .hw_value_short = ATH5K_RATE_CODE_2M | AR5K_SET_SHORT_PREAMBLE,
157 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
159 .hw_value = ATH5K_RATE_CODE_5_5M,
160 .hw_value_short = ATH5K_RATE_CODE_5_5M | AR5K_SET_SHORT_PREAMBLE,
161 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
163 .hw_value = ATH5K_RATE_CODE_11M,
164 .hw_value_short = ATH5K_RATE_CODE_11M | AR5K_SET_SHORT_PREAMBLE,
165 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
167 .hw_value = ATH5K_RATE_CODE_6M,
170 .hw_value = ATH5K_RATE_CODE_9M,
173 .hw_value = ATH5K_RATE_CODE_12M,
176 .hw_value = ATH5K_RATE_CODE_18M,
179 .hw_value = ATH5K_RATE_CODE_24M,
182 .hw_value = ATH5K_RATE_CODE_36M,
185 .hw_value = ATH5K_RATE_CODE_48M,
188 .hw_value = ATH5K_RATE_CODE_54M,
193 static inline void ath5k_txbuf_free_skb(struct ath5k_softc *sc,
194 struct ath5k_buf *bf)
199 pci_unmap_single(sc->pdev, bf->skbaddr, bf->skb->len,
201 dev_kfree_skb_any(bf->skb);
204 bf->desc->ds_data = 0;
207 static inline void ath5k_rxbuf_free_skb(struct ath5k_softc *sc,
208 struct ath5k_buf *bf)
210 struct ath5k_hw *ah = sc->ah;
211 struct ath_common *common = ath5k_hw_common(ah);
216 pci_unmap_single(sc->pdev, bf->skbaddr, common->rx_bufsize,
218 dev_kfree_skb_any(bf->skb);
221 bf->desc->ds_data = 0;
225 static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
227 u64 tsf = ath5k_hw_get_tsf64(ah);
229 if ((tsf & 0x7fff) < rstamp)
232 return (tsf & ~0x7fff) | rstamp;
236 ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val)
238 const char *name = "xxxxx";
241 for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
242 if (srev_names[i].sr_type != type)
245 if ((val & 0xf0) == srev_names[i].sr_val)
246 name = srev_names[i].sr_name;
248 if ((val & 0xff) == srev_names[i].sr_val) {
249 name = srev_names[i].sr_name;
256 static unsigned int ath5k_ioread32(void *hw_priv, u32 reg_offset)
258 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv;
259 return ath5k_hw_reg_read(ah, reg_offset);
262 static void ath5k_iowrite32(void *hw_priv, u32 val, u32 reg_offset)
264 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv;
265 ath5k_hw_reg_write(ah, val, reg_offset);
268 static const struct ath_ops ath5k_common_ops = {
269 .read = ath5k_ioread32,
270 .write = ath5k_iowrite32,
273 /***********************\
274 * Driver Initialization *
275 \***********************/
277 static int ath5k_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request)
279 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
280 struct ath5k_softc *sc = hw->priv;
281 struct ath_regulatory *regulatory = ath5k_hw_regulatory(sc->ah);
283 return ath_reg_notifier_apply(wiphy, request, regulatory);
286 /********************\
287 * Channel/mode setup *
288 \********************/
291 * Convert IEEE channel number to MHz frequency.
294 ath5k_ieee2mhz(short chan)
296 if (chan <= 14 || chan >= 27)
297 return ieee80211chan2mhz(chan);
299 return 2212 + chan * 20;
303 * Returns true for the channel numbers used without all_channels modparam.
305 static bool ath5k_is_standard_channel(short chan)
307 return ((chan <= 14) ||
309 ((chan & 3) == 0 && chan >= 36 && chan <= 64) ||
311 ((chan & 3) == 0 && chan >= 100 && chan <= 140) ||
313 ((chan & 3) == 1 && chan >= 149 && chan <= 165));
317 ath5k_copy_channels(struct ath5k_hw *ah,
318 struct ieee80211_channel *channels,
322 unsigned int i, count, size, chfreq, freq, ch;
324 if (!test_bit(mode, ah->ah_modes))
329 case AR5K_MODE_11A_TURBO:
330 /* 1..220, but 2GHz frequencies are filtered by check_channel */
332 chfreq = CHANNEL_5GHZ;
336 case AR5K_MODE_11G_TURBO:
338 chfreq = CHANNEL_2GHZ;
341 ATH5K_WARN(ah->ah_sc, "bad mode, not copying channels\n");
345 for (i = 0, count = 0; i < size && max > 0; i++) {
347 freq = ath5k_ieee2mhz(ch);
349 /* Check if channel is supported by the chipset */
350 if (!ath5k_channel_ok(ah, freq, chfreq))
353 if (!modparam_all_channels && !ath5k_is_standard_channel(ch))
356 /* Write channel info and increment counter */
357 channels[count].center_freq = freq;
358 channels[count].band = (chfreq == CHANNEL_2GHZ) ?
359 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
363 channels[count].hw_value = chfreq | CHANNEL_OFDM;
365 case AR5K_MODE_11A_TURBO:
366 case AR5K_MODE_11G_TURBO:
367 channels[count].hw_value = chfreq |
368 CHANNEL_OFDM | CHANNEL_TURBO;
371 channels[count].hw_value = CHANNEL_B;
382 ath5k_setup_rate_idx(struct ath5k_softc *sc, struct ieee80211_supported_band *b)
386 for (i = 0; i < AR5K_MAX_RATES; i++)
387 sc->rate_idx[b->band][i] = -1;
389 for (i = 0; i < b->n_bitrates; i++) {
390 sc->rate_idx[b->band][b->bitrates[i].hw_value] = i;
391 if (b->bitrates[i].hw_value_short)
392 sc->rate_idx[b->band][b->bitrates[i].hw_value_short] = i;
397 ath5k_setup_bands(struct ieee80211_hw *hw)
399 struct ath5k_softc *sc = hw->priv;
400 struct ath5k_hw *ah = sc->ah;
401 struct ieee80211_supported_band *sband;
402 int max_c, count_c = 0;
405 BUILD_BUG_ON(ARRAY_SIZE(sc->sbands) < IEEE80211_NUM_BANDS);
406 max_c = ARRAY_SIZE(sc->channels);
409 sband = &sc->sbands[IEEE80211_BAND_2GHZ];
410 sband->band = IEEE80211_BAND_2GHZ;
411 sband->bitrates = &sc->rates[IEEE80211_BAND_2GHZ][0];
413 if (test_bit(AR5K_MODE_11G, sc->ah->ah_capabilities.cap_mode)) {
415 memcpy(sband->bitrates, &ath5k_rates[0],
416 sizeof(struct ieee80211_rate) * 12);
417 sband->n_bitrates = 12;
419 sband->channels = sc->channels;
420 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
421 AR5K_MODE_11G, max_c);
423 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
424 count_c = sband->n_channels;
426 } else if (test_bit(AR5K_MODE_11B, sc->ah->ah_capabilities.cap_mode)) {
428 memcpy(sband->bitrates, &ath5k_rates[0],
429 sizeof(struct ieee80211_rate) * 4);
430 sband->n_bitrates = 4;
432 /* 5211 only supports B rates and uses 4bit rate codes
433 * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B)
436 if (ah->ah_version == AR5K_AR5211) {
437 for (i = 0; i < 4; i++) {
438 sband->bitrates[i].hw_value =
439 sband->bitrates[i].hw_value & 0xF;
440 sband->bitrates[i].hw_value_short =
441 sband->bitrates[i].hw_value_short & 0xF;
445 sband->channels = sc->channels;
446 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
447 AR5K_MODE_11B, max_c);
449 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
450 count_c = sband->n_channels;
453 ath5k_setup_rate_idx(sc, sband);
455 /* 5GHz band, A mode */
456 if (test_bit(AR5K_MODE_11A, sc->ah->ah_capabilities.cap_mode)) {
457 sband = &sc->sbands[IEEE80211_BAND_5GHZ];
458 sband->band = IEEE80211_BAND_5GHZ;
459 sband->bitrates = &sc->rates[IEEE80211_BAND_5GHZ][0];
461 memcpy(sband->bitrates, &ath5k_rates[4],
462 sizeof(struct ieee80211_rate) * 8);
463 sband->n_bitrates = 8;
465 sband->channels = &sc->channels[count_c];
466 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
467 AR5K_MODE_11A, max_c);
469 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband;
471 ath5k_setup_rate_idx(sc, sband);
473 ath5k_debug_dump_bands(sc);
479 * Set/change channels. We always reset the chip.
480 * To accomplish this we must first cleanup any pending DMA,
481 * then restart stuff after a la ath5k_init.
483 * Called with sc->lock.
486 ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan)
488 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
489 "channel set, resetting (%u -> %u MHz)\n",
490 sc->curchan->center_freq, chan->center_freq);
493 * To switch channels clear any pending DMA operations;
494 * wait long enough for the RX fifo to drain, reset the
495 * hardware at the new frequency, and then re-enable
496 * the relevant bits of the h/w.
498 return ath5k_reset(sc, chan);
502 ath5k_setcurmode(struct ath5k_softc *sc, unsigned int mode)
506 if (mode == AR5K_MODE_11A) {
507 sc->curband = &sc->sbands[IEEE80211_BAND_5GHZ];
509 sc->curband = &sc->sbands[IEEE80211_BAND_2GHZ];
513 struct ath_vif_iter_data {
514 const u8 *hw_macaddr;
516 u8 active_mac[ETH_ALEN]; /* first active MAC */
517 bool need_set_hw_addr;
522 static void ath_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
524 struct ath_vif_iter_data *iter_data = data;
527 if (iter_data->hw_macaddr)
528 for (i = 0; i < ETH_ALEN; i++)
529 iter_data->mask[i] &=
530 ~(iter_data->hw_macaddr[i] ^ mac[i]);
532 if (!iter_data->found_active) {
533 iter_data->found_active = true;
534 memcpy(iter_data->active_mac, mac, ETH_ALEN);
537 if (iter_data->need_set_hw_addr && iter_data->hw_macaddr)
538 if (compare_ether_addr(iter_data->hw_macaddr, mac) == 0)
539 iter_data->need_set_hw_addr = false;
541 if (!iter_data->any_assoc) {
542 struct ath5k_vif *avf = (void *)vif->drv_priv;
544 iter_data->any_assoc = true;
548 void ath5k_update_bssid_mask(struct ath5k_softc *sc, struct ieee80211_vif *vif)
550 struct ath_common *common = ath5k_hw_common(sc->ah);
551 struct ath_vif_iter_data iter_data;
554 * Use the hardware MAC address as reference, the hardware uses it
555 * together with the BSSID mask when matching addresses.
557 iter_data.hw_macaddr = common->macaddr;
558 memset(&iter_data.mask, 0xff, ETH_ALEN);
559 iter_data.found_active = false;
560 iter_data.need_set_hw_addr = true;
563 ath_vif_iter(&iter_data, vif->addr, vif);
565 /* Get list of all active MAC addresses */
566 ieee80211_iterate_active_interfaces_atomic(sc->hw, ath_vif_iter,
568 memcpy(sc->bssidmask, iter_data.mask, ETH_ALEN);
570 if (iter_data.need_set_hw_addr && iter_data.found_active)
571 ath5k_hw_set_lladdr(sc->ah, iter_data.active_mac);
573 ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask);
577 ath5k_mode_setup(struct ath5k_softc *sc, struct ieee80211_vif *vif)
579 struct ath5k_hw *ah = sc->ah;
582 /* configure rx filter */
583 rfilt = sc->filter_flags;
584 ath5k_hw_set_rx_filter(ah, rfilt);
586 if (ath5k_hw_hasbssidmask(ah))
587 ath5k_update_bssid_mask(sc, vif);
589 /* configure operational mode */
590 ath5k_hw_set_opmode(ah, sc->opmode);
592 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "mode setup opmode %d\n", sc->opmode);
593 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
597 ath5k_hw_to_driver_rix(struct ath5k_softc *sc, int hw_rix)
601 /* return base rate on errors */
602 if (WARN(hw_rix < 0 || hw_rix >= AR5K_MAX_RATES,
603 "hw_rix out of bounds: %x\n", hw_rix))
606 rix = sc->rate_idx[sc->curband->band][hw_rix];
607 if (WARN(rix < 0, "invalid hw_rix: %x\n", hw_rix))
618 struct sk_buff *ath5k_rx_skb_alloc(struct ath5k_softc *sc, dma_addr_t *skb_addr)
620 struct ath_common *common = ath5k_hw_common(sc->ah);
624 * Allocate buffer with headroom_needed space for the
625 * fake physical layer header at the start.
627 skb = ath_rxbuf_alloc(common,
632 ATH5K_ERR(sc, "can't alloc skbuff of size %u\n",
637 *skb_addr = pci_map_single(sc->pdev,
638 skb->data, common->rx_bufsize,
640 if (unlikely(pci_dma_mapping_error(sc->pdev, *skb_addr))) {
641 ATH5K_ERR(sc, "%s: DMA mapping failed\n", __func__);
649 ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
651 struct ath5k_hw *ah = sc->ah;
652 struct sk_buff *skb = bf->skb;
653 struct ath5k_desc *ds;
657 skb = ath5k_rx_skb_alloc(sc, &bf->skbaddr);
664 * Setup descriptors. For receive we always terminate
665 * the descriptor list with a self-linked entry so we'll
666 * not get overrun under high load (as can happen with a
667 * 5212 when ANI processing enables PHY error frames).
669 * To ensure the last descriptor is self-linked we create
670 * each descriptor as self-linked and add it to the end. As
671 * each additional descriptor is added the previous self-linked
672 * entry is "fixed" naturally. This should be safe even
673 * if DMA is happening. When processing RX interrupts we
674 * never remove/process the last, self-linked, entry on the
675 * descriptor list. This ensures the hardware always has
676 * someplace to write a new frame.
679 ds->ds_link = bf->daddr; /* link to self */
680 ds->ds_data = bf->skbaddr;
681 ret = ath5k_hw_setup_rx_desc(ah, ds, ah->common.rx_bufsize, 0);
683 ATH5K_ERR(sc, "%s: could not setup RX desc\n", __func__);
687 if (sc->rxlink != NULL)
688 *sc->rxlink = bf->daddr;
689 sc->rxlink = &ds->ds_link;
693 static enum ath5k_pkt_type get_hw_packet_type(struct sk_buff *skb)
695 struct ieee80211_hdr *hdr;
696 enum ath5k_pkt_type htype;
699 hdr = (struct ieee80211_hdr *)skb->data;
700 fc = hdr->frame_control;
702 if (ieee80211_is_beacon(fc))
703 htype = AR5K_PKT_TYPE_BEACON;
704 else if (ieee80211_is_probe_resp(fc))
705 htype = AR5K_PKT_TYPE_PROBE_RESP;
706 else if (ieee80211_is_atim(fc))
707 htype = AR5K_PKT_TYPE_ATIM;
708 else if (ieee80211_is_pspoll(fc))
709 htype = AR5K_PKT_TYPE_PSPOLL;
711 htype = AR5K_PKT_TYPE_NORMAL;
717 ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf,
718 struct ath5k_txq *txq, int padsize)
720 struct ath5k_hw *ah = sc->ah;
721 struct ath5k_desc *ds = bf->desc;
722 struct sk_buff *skb = bf->skb;
723 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
724 unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID;
725 struct ieee80211_rate *rate;
726 unsigned int mrr_rate[3], mrr_tries[3];
733 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
736 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
739 rate = ieee80211_get_tx_rate(sc->hw, info);
745 if (info->flags & IEEE80211_TX_CTL_NO_ACK)
746 flags |= AR5K_TXDESC_NOACK;
748 rc_flags = info->control.rates[0].flags;
749 hw_rate = (rc_flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) ?
750 rate->hw_value_short : rate->hw_value;
754 /* FIXME: If we are in g mode and rate is a CCK rate
755 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
756 * from tx power (value is in dB units already) */
757 if (info->control.hw_key) {
758 keyidx = info->control.hw_key->hw_key_idx;
759 pktlen += info->control.hw_key->icv_len;
761 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
762 flags |= AR5K_TXDESC_RTSENA;
763 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
764 duration = le16_to_cpu(ieee80211_rts_duration(sc->hw,
765 info->control.vif, pktlen, info));
767 if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
768 flags |= AR5K_TXDESC_CTSENA;
769 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
770 duration = le16_to_cpu(ieee80211_ctstoself_duration(sc->hw,
771 info->control.vif, pktlen, info));
773 ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
774 ieee80211_get_hdrlen_from_skb(skb), padsize,
775 get_hw_packet_type(skb),
776 (sc->power_level * 2),
778 info->control.rates[0].count, keyidx, ah->ah_tx_ant, flags,
783 memset(mrr_rate, 0, sizeof(mrr_rate));
784 memset(mrr_tries, 0, sizeof(mrr_tries));
785 for (i = 0; i < 3; i++) {
786 rate = ieee80211_get_alt_retry_rate(sc->hw, info, i);
790 mrr_rate[i] = rate->hw_value;
791 mrr_tries[i] = info->control.rates[i + 1].count;
794 ath5k_hw_setup_mrr_tx_desc(ah, ds,
795 mrr_rate[0], mrr_tries[0],
796 mrr_rate[1], mrr_tries[1],
797 mrr_rate[2], mrr_tries[2]);
800 ds->ds_data = bf->skbaddr;
802 spin_lock_bh(&txq->lock);
803 list_add_tail(&bf->list, &txq->q);
805 if (txq->link == NULL) /* is this first packet? */
806 ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr);
807 else /* no, so only link it */
808 *txq->link = bf->daddr;
810 txq->link = &ds->ds_link;
811 ath5k_hw_start_tx_dma(ah, txq->qnum);
813 spin_unlock_bh(&txq->lock);
817 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
821 /*******************\
822 * Descriptors setup *
823 \*******************/
826 ath5k_desc_alloc(struct ath5k_softc *sc, struct pci_dev *pdev)
828 struct ath5k_desc *ds;
829 struct ath5k_buf *bf;
834 /* allocate descriptors */
835 sc->desc_len = sizeof(struct ath5k_desc) *
836 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
837 sc->desc = pci_alloc_consistent(pdev, sc->desc_len, &sc->desc_daddr);
838 if (sc->desc == NULL) {
839 ATH5K_ERR(sc, "can't allocate descriptors\n");
845 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
846 ds, sc->desc_len, (unsigned long long)sc->desc_daddr);
848 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
849 sizeof(struct ath5k_buf), GFP_KERNEL);
851 ATH5K_ERR(sc, "can't allocate bufptr\n");
857 INIT_LIST_HEAD(&sc->rxbuf);
858 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
861 list_add_tail(&bf->list, &sc->rxbuf);
864 INIT_LIST_HEAD(&sc->txbuf);
865 sc->txbuf_len = ATH_TXBUF;
866 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++,
870 list_add_tail(&bf->list, &sc->txbuf);
874 INIT_LIST_HEAD(&sc->bcbuf);
875 for (i = 0; i < ATH_BCBUF; i++, bf++, ds++, da += sizeof(*ds)) {
878 list_add_tail(&bf->list, &sc->bcbuf);
883 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
890 ath5k_desc_free(struct ath5k_softc *sc, struct pci_dev *pdev)
892 struct ath5k_buf *bf;
894 list_for_each_entry(bf, &sc->txbuf, list)
895 ath5k_txbuf_free_skb(sc, bf);
896 list_for_each_entry(bf, &sc->rxbuf, list)
897 ath5k_rxbuf_free_skb(sc, bf);
898 list_for_each_entry(bf, &sc->bcbuf, list)
899 ath5k_txbuf_free_skb(sc, bf);
901 /* Free memory associated with all descriptors */
902 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
915 static struct ath5k_txq *
916 ath5k_txq_setup(struct ath5k_softc *sc,
917 int qtype, int subtype)
919 struct ath5k_hw *ah = sc->ah;
920 struct ath5k_txq *txq;
921 struct ath5k_txq_info qi = {
922 .tqi_subtype = subtype,
923 /* XXX: default values not correct for B and XR channels,
925 .tqi_aifs = AR5K_TUNE_AIFS,
926 .tqi_cw_min = AR5K_TUNE_CWMIN,
927 .tqi_cw_max = AR5K_TUNE_CWMAX
932 * Enable interrupts only for EOL and DESC conditions.
933 * We mark tx descriptors to receive a DESC interrupt
934 * when a tx queue gets deep; otherwise we wait for the
935 * EOL to reap descriptors. Note that this is done to
936 * reduce interrupt load and this only defers reaping
937 * descriptors, never transmitting frames. Aside from
938 * reducing interrupts this also permits more concurrency.
939 * The only potential downside is if the tx queue backs
940 * up in which case the top half of the kernel may backup
941 * due to a lack of tx descriptors.
943 qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
944 AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
945 qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi);
948 * NB: don't print a message, this happens
949 * normally on parts with too few tx queues
951 return ERR_PTR(qnum);
953 if (qnum >= ARRAY_SIZE(sc->txqs)) {
954 ATH5K_ERR(sc, "hw qnum %u out of range, max %tu!\n",
955 qnum, ARRAY_SIZE(sc->txqs));
956 ath5k_hw_release_tx_queue(ah, qnum);
957 return ERR_PTR(-EINVAL);
959 txq = &sc->txqs[qnum];
963 INIT_LIST_HEAD(&txq->q);
964 spin_lock_init(&txq->lock);
967 txq->txq_poll_mark = false;
970 return &sc->txqs[qnum];
974 ath5k_beaconq_setup(struct ath5k_hw *ah)
976 struct ath5k_txq_info qi = {
977 /* XXX: default values not correct for B and XR channels,
979 .tqi_aifs = AR5K_TUNE_AIFS,
980 .tqi_cw_min = AR5K_TUNE_CWMIN,
981 .tqi_cw_max = AR5K_TUNE_CWMAX,
982 /* NB: for dynamic turbo, don't enable any other interrupts */
983 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE
986 return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi);
990 ath5k_beaconq_config(struct ath5k_softc *sc)
992 struct ath5k_hw *ah = sc->ah;
993 struct ath5k_txq_info qi;
996 ret = ath5k_hw_get_tx_queueprops(ah, sc->bhalq, &qi);
1000 if (sc->opmode == NL80211_IFTYPE_AP ||
1001 sc->opmode == NL80211_IFTYPE_MESH_POINT) {
1003 * Always burst out beacon and CAB traffic
1004 * (aifs = cwmin = cwmax = 0)
1009 } else if (sc->opmode == NL80211_IFTYPE_ADHOC) {
1011 * Adhoc mode; backoff between 0 and (2 * cw_min).
1015 qi.tqi_cw_max = 2 * AR5K_TUNE_CWMIN;
1018 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1019 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
1020 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max);
1022 ret = ath5k_hw_set_tx_queueprops(ah, sc->bhalq, &qi);
1024 ATH5K_ERR(sc, "%s: unable to update parameters for beacon "
1025 "hardware queue!\n", __func__);
1028 ret = ath5k_hw_reset_tx_queue(ah, sc->bhalq); /* push to h/w */
1032 /* reconfigure cabq with ready time to 80% of beacon_interval */
1033 ret = ath5k_hw_get_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi);
1037 qi.tqi_ready_time = (sc->bintval * 80) / 100;
1038 ret = ath5k_hw_set_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi);
1042 ret = ath5k_hw_reset_tx_queue(ah, AR5K_TX_QUEUE_ID_CAB);
1048 ath5k_txq_drainq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1050 struct ath5k_buf *bf, *bf0;
1053 * NB: this assumes output has been stopped and
1054 * we do not need to block ath5k_tx_tasklet
1056 spin_lock_bh(&txq->lock);
1057 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1058 ath5k_debug_printtxbuf(sc, bf);
1060 ath5k_txbuf_free_skb(sc, bf);
1062 spin_lock_bh(&sc->txbuflock);
1063 list_move_tail(&bf->list, &sc->txbuf);
1066 spin_unlock_bh(&sc->txbuflock);
1069 txq->txq_poll_mark = false;
1070 spin_unlock_bh(&txq->lock);
1074 * Drain the transmit queues and reclaim resources.
1077 ath5k_txq_cleanup(struct ath5k_softc *sc)
1079 struct ath5k_hw *ah = sc->ah;
1082 /* XXX return value */
1083 if (likely(!test_bit(ATH_STAT_INVALID, sc->status))) {
1084 /* don't touch the hardware if marked invalid */
1085 ath5k_hw_stop_tx_dma(ah, sc->bhalq);
1086 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "beacon queue %x\n",
1087 ath5k_hw_get_txdp(ah, sc->bhalq));
1088 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1089 if (sc->txqs[i].setup) {
1090 ath5k_hw_stop_tx_dma(ah, sc->txqs[i].qnum);
1091 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "txq [%u] %x, "
1094 ath5k_hw_get_txdp(ah,
1100 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1101 if (sc->txqs[i].setup)
1102 ath5k_txq_drainq(sc, &sc->txqs[i]);
1106 ath5k_txq_release(struct ath5k_softc *sc)
1108 struct ath5k_txq *txq = sc->txqs;
1111 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++)
1113 ath5k_hw_release_tx_queue(sc->ah, txq->qnum);
1124 * Enable the receive h/w following a reset.
1127 ath5k_rx_start(struct ath5k_softc *sc)
1129 struct ath5k_hw *ah = sc->ah;
1130 struct ath_common *common = ath5k_hw_common(ah);
1131 struct ath5k_buf *bf;
1134 common->rx_bufsize = roundup(IEEE80211_MAX_FRAME_LEN, common->cachelsz);
1136 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "cachelsz %u rx_bufsize %u\n",
1137 common->cachelsz, common->rx_bufsize);
1139 spin_lock_bh(&sc->rxbuflock);
1141 list_for_each_entry(bf, &sc->rxbuf, list) {
1142 ret = ath5k_rxbuf_setup(sc, bf);
1144 spin_unlock_bh(&sc->rxbuflock);
1148 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1149 ath5k_hw_set_rxdp(ah, bf->daddr);
1150 spin_unlock_bh(&sc->rxbuflock);
1152 ath5k_hw_start_rx_dma(ah); /* enable recv descriptors */
1153 ath5k_mode_setup(sc, NULL); /* set filters, etc. */
1154 ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */
1162 * Disable the receive h/w in preparation for a reset.
1165 ath5k_rx_stop(struct ath5k_softc *sc)
1167 struct ath5k_hw *ah = sc->ah;
1169 ath5k_hw_stop_rx_pcu(ah); /* disable PCU */
1170 ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */
1171 ath5k_hw_stop_rx_dma(ah); /* disable DMA engine */
1173 ath5k_debug_printrxbuffs(sc, ah);
1177 ath5k_rx_decrypted(struct ath5k_softc *sc, struct sk_buff *skb,
1178 struct ath5k_rx_status *rs)
1180 struct ath5k_hw *ah = sc->ah;
1181 struct ath_common *common = ath5k_hw_common(ah);
1182 struct ieee80211_hdr *hdr = (void *)skb->data;
1183 unsigned int keyix, hlen;
1185 if (!(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1186 rs->rs_keyix != AR5K_RXKEYIX_INVALID)
1187 return RX_FLAG_DECRYPTED;
1189 /* Apparently when a default key is used to decrypt the packet
1190 the hw does not set the index used to decrypt. In such cases
1191 get the index from the packet. */
1192 hlen = ieee80211_hdrlen(hdr->frame_control);
1193 if (ieee80211_has_protected(hdr->frame_control) &&
1194 !(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1195 skb->len >= hlen + 4) {
1196 keyix = skb->data[hlen + 3] >> 6;
1198 if (test_bit(keyix, common->keymap))
1199 return RX_FLAG_DECRYPTED;
1207 ath5k_check_ibss_tsf(struct ath5k_softc *sc, struct sk_buff *skb,
1208 struct ieee80211_rx_status *rxs)
1210 struct ath_common *common = ath5k_hw_common(sc->ah);
1213 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1215 if (ieee80211_is_beacon(mgmt->frame_control) &&
1216 le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS &&
1217 memcmp(mgmt->bssid, common->curbssid, ETH_ALEN) == 0) {
1219 * Received an IBSS beacon with the same BSSID. Hardware *must*
1220 * have updated the local TSF. We have to work around various
1221 * hardware bugs, though...
1223 tsf = ath5k_hw_get_tsf64(sc->ah);
1224 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp);
1225 hw_tu = TSF_TO_TU(tsf);
1227 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1228 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
1229 (unsigned long long)bc_tstamp,
1230 (unsigned long long)rxs->mactime,
1231 (unsigned long long)(rxs->mactime - bc_tstamp),
1232 (unsigned long long)tsf);
1235 * Sometimes the HW will give us a wrong tstamp in the rx
1236 * status, causing the timestamp extension to go wrong.
1237 * (This seems to happen especially with beacon frames bigger
1238 * than 78 byte (incl. FCS))
1239 * But we know that the receive timestamp must be later than the
1240 * timestamp of the beacon since HW must have synced to that.
1242 * NOTE: here we assume mactime to be after the frame was
1243 * received, not like mac80211 which defines it at the start.
1245 if (bc_tstamp > rxs->mactime) {
1246 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1247 "fixing mactime from %llx to %llx\n",
1248 (unsigned long long)rxs->mactime,
1249 (unsigned long long)tsf);
1254 * Local TSF might have moved higher than our beacon timers,
1255 * in that case we have to update them to continue sending
1256 * beacons. This also takes care of synchronizing beacon sending
1257 * times with other stations.
1259 if (hw_tu >= sc->nexttbtt)
1260 ath5k_beacon_update_timers(sc, bc_tstamp);
1262 /* Check if the beacon timers are still correct, because a TSF
1263 * update might have created a window between them - for a
1264 * longer description see the comment of this function: */
1265 if (!ath5k_hw_check_beacon_timers(sc->ah, sc->bintval)) {
1266 ath5k_beacon_update_timers(sc, bc_tstamp);
1267 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1268 "fixed beacon timers after beacon receive\n");
1274 ath5k_update_beacon_rssi(struct ath5k_softc *sc, struct sk_buff *skb, int rssi)
1276 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1277 struct ath5k_hw *ah = sc->ah;
1278 struct ath_common *common = ath5k_hw_common(ah);
1280 /* only beacons from our BSSID */
1281 if (!ieee80211_is_beacon(mgmt->frame_control) ||
1282 memcmp(mgmt->bssid, common->curbssid, ETH_ALEN) != 0)
1285 ah->ah_beacon_rssi_avg = ath5k_moving_average(ah->ah_beacon_rssi_avg,
1288 /* in IBSS mode we should keep RSSI statistics per neighbour */
1289 /* le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS */
1293 * Compute padding position. skb must contain an IEEE 802.11 frame
1295 static int ath5k_common_padpos(struct sk_buff *skb)
1297 struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data;
1298 __le16 frame_control = hdr->frame_control;
1301 if (ieee80211_has_a4(frame_control)) {
1304 if (ieee80211_is_data_qos(frame_control)) {
1305 padpos += IEEE80211_QOS_CTL_LEN;
1312 * This function expects an 802.11 frame and returns the number of
1313 * bytes added, or -1 if we don't have enough header room.
1315 static int ath5k_add_padding(struct sk_buff *skb)
1317 int padpos = ath5k_common_padpos(skb);
1318 int padsize = padpos & 3;
1320 if (padsize && skb->len>padpos) {
1322 if (skb_headroom(skb) < padsize)
1325 skb_push(skb, padsize);
1326 memmove(skb->data, skb->data+padsize, padpos);
1334 * The MAC header is padded to have 32-bit boundary if the
1335 * packet payload is non-zero. The general calculation for
1336 * padsize would take into account odd header lengths:
1337 * padsize = 4 - (hdrlen & 3); however, since only
1338 * even-length headers are used, padding can only be 0 or 2
1339 * bytes and we can optimize this a bit. We must not try to
1340 * remove padding from short control frames that do not have a
1343 * This function expects an 802.11 frame and returns the number of
1346 static int ath5k_remove_padding(struct sk_buff *skb)
1348 int padpos = ath5k_common_padpos(skb);
1349 int padsize = padpos & 3;
1351 if (padsize && skb->len>=padpos+padsize) {
1352 memmove(skb->data + padsize, skb->data, padpos);
1353 skb_pull(skb, padsize);
1361 ath5k_receive_frame(struct ath5k_softc *sc, struct sk_buff *skb,
1362 struct ath5k_rx_status *rs)
1364 struct ieee80211_rx_status *rxs;
1366 ath5k_remove_padding(skb);
1368 rxs = IEEE80211_SKB_RXCB(skb);
1371 if (unlikely(rs->rs_status & AR5K_RXERR_MIC))
1372 rxs->flag |= RX_FLAG_MMIC_ERROR;
1375 * always extend the mac timestamp, since this information is
1376 * also needed for proper IBSS merging.
1378 * XXX: it might be too late to do it here, since rs_tstamp is
1379 * 15bit only. that means TSF extension has to be done within
1380 * 32768usec (about 32ms). it might be necessary to move this to
1381 * the interrupt handler, like it is done in madwifi.
1383 * Unfortunately we don't know when the hardware takes the rx
1384 * timestamp (beginning of phy frame, data frame, end of rx?).
1385 * The only thing we know is that it is hardware specific...
1386 * On AR5213 it seems the rx timestamp is at the end of the
1387 * frame, but i'm not sure.
1389 * NOTE: mac80211 defines mactime at the beginning of the first
1390 * data symbol. Since we don't have any time references it's
1391 * impossible to comply to that. This affects IBSS merge only
1392 * right now, so it's not too bad...
1394 rxs->mactime = ath5k_extend_tsf(sc->ah, rs->rs_tstamp);
1395 rxs->flag |= RX_FLAG_TSFT;
1397 rxs->freq = sc->curchan->center_freq;
1398 rxs->band = sc->curband->band;
1400 rxs->signal = sc->ah->ah_noise_floor + rs->rs_rssi;
1402 rxs->antenna = rs->rs_antenna;
1404 if (rs->rs_antenna > 0 && rs->rs_antenna < 5)
1405 sc->stats.antenna_rx[rs->rs_antenna]++;
1407 sc->stats.antenna_rx[0]++; /* invalid */
1409 rxs->rate_idx = ath5k_hw_to_driver_rix(sc, rs->rs_rate);
1410 rxs->flag |= ath5k_rx_decrypted(sc, skb, rs);
1412 if (rxs->rate_idx >= 0 && rs->rs_rate ==
1413 sc->curband->bitrates[rxs->rate_idx].hw_value_short)
1414 rxs->flag |= RX_FLAG_SHORTPRE;
1416 ath5k_debug_dump_skb(sc, skb, "RX ", 0);
1418 ath5k_update_beacon_rssi(sc, skb, rs->rs_rssi);
1420 /* check beacons in IBSS mode */
1421 if (sc->opmode == NL80211_IFTYPE_ADHOC)
1422 ath5k_check_ibss_tsf(sc, skb, rxs);
1424 ieee80211_rx(sc->hw, skb);
1427 /** ath5k_frame_receive_ok() - Do we want to receive this frame or not?
1429 * Check if we want to further process this frame or not. Also update
1430 * statistics. Return true if we want this frame, false if not.
1433 ath5k_receive_frame_ok(struct ath5k_softc *sc, struct ath5k_rx_status *rs)
1435 sc->stats.rx_all_count++;
1436 sc->stats.rx_bytes_count += rs->rs_datalen;
1438 if (unlikely(rs->rs_status)) {
1439 if (rs->rs_status & AR5K_RXERR_CRC)
1440 sc->stats.rxerr_crc++;
1441 if (rs->rs_status & AR5K_RXERR_FIFO)
1442 sc->stats.rxerr_fifo++;
1443 if (rs->rs_status & AR5K_RXERR_PHY) {
1444 sc->stats.rxerr_phy++;
1445 if (rs->rs_phyerr > 0 && rs->rs_phyerr < 32)
1446 sc->stats.rxerr_phy_code[rs->rs_phyerr]++;
1449 if (rs->rs_status & AR5K_RXERR_DECRYPT) {
1451 * Decrypt error. If the error occurred
1452 * because there was no hardware key, then
1453 * let the frame through so the upper layers
1454 * can process it. This is necessary for 5210
1455 * parts which have no way to setup a ``clear''
1458 * XXX do key cache faulting
1460 sc->stats.rxerr_decrypt++;
1461 if (rs->rs_keyix == AR5K_RXKEYIX_INVALID &&
1462 !(rs->rs_status & AR5K_RXERR_CRC))
1465 if (rs->rs_status & AR5K_RXERR_MIC) {
1466 sc->stats.rxerr_mic++;
1470 /* reject any frames with non-crypto errors */
1471 if (rs->rs_status & ~(AR5K_RXERR_DECRYPT))
1475 if (unlikely(rs->rs_more)) {
1476 sc->stats.rxerr_jumbo++;
1483 ath5k_tasklet_rx(unsigned long data)
1485 struct ath5k_rx_status rs = {};
1486 struct sk_buff *skb, *next_skb;
1487 dma_addr_t next_skb_addr;
1488 struct ath5k_softc *sc = (void *)data;
1489 struct ath5k_hw *ah = sc->ah;
1490 struct ath_common *common = ath5k_hw_common(ah);
1491 struct ath5k_buf *bf;
1492 struct ath5k_desc *ds;
1495 spin_lock(&sc->rxbuflock);
1496 if (list_empty(&sc->rxbuf)) {
1497 ATH5K_WARN(sc, "empty rx buf pool\n");
1501 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1502 BUG_ON(bf->skb == NULL);
1506 /* bail if HW is still using self-linked descriptor */
1507 if (ath5k_hw_get_rxdp(sc->ah) == bf->daddr)
1510 ret = sc->ah->ah_proc_rx_desc(sc->ah, ds, &rs);
1511 if (unlikely(ret == -EINPROGRESS))
1513 else if (unlikely(ret)) {
1514 ATH5K_ERR(sc, "error in processing rx descriptor\n");
1515 sc->stats.rxerr_proc++;
1519 if (ath5k_receive_frame_ok(sc, &rs)) {
1520 next_skb = ath5k_rx_skb_alloc(sc, &next_skb_addr);
1523 * If we can't replace bf->skb with a new skb under
1524 * memory pressure, just skip this packet
1529 pci_unmap_single(sc->pdev, bf->skbaddr,
1531 PCI_DMA_FROMDEVICE);
1533 skb_put(skb, rs.rs_datalen);
1535 ath5k_receive_frame(sc, skb, &rs);
1538 bf->skbaddr = next_skb_addr;
1541 list_move_tail(&bf->list, &sc->rxbuf);
1542 } while (ath5k_rxbuf_setup(sc, bf) == 0);
1544 spin_unlock(&sc->rxbuflock);
1552 static int ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb,
1553 struct ath5k_txq *txq)
1555 struct ath5k_softc *sc = hw->priv;
1556 struct ath5k_buf *bf;
1557 unsigned long flags;
1560 ath5k_debug_dump_skb(sc, skb, "TX ", 1);
1563 * The hardware expects the header padded to 4 byte boundaries.
1564 * If this is not the case, we add the padding after the header.
1566 padsize = ath5k_add_padding(skb);
1568 ATH5K_ERR(sc, "tx hdrlen not %%4: not enough"
1569 " headroom to pad");
1573 if (txq->txq_len >= ATH5K_TXQ_LEN_MAX)
1574 ieee80211_stop_queue(hw, txq->qnum);
1576 spin_lock_irqsave(&sc->txbuflock, flags);
1577 if (list_empty(&sc->txbuf)) {
1578 ATH5K_ERR(sc, "no further txbuf available, dropping packet\n");
1579 spin_unlock_irqrestore(&sc->txbuflock, flags);
1580 ieee80211_stop_queues(hw);
1583 bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list);
1584 list_del(&bf->list);
1586 if (list_empty(&sc->txbuf))
1587 ieee80211_stop_queues(hw);
1588 spin_unlock_irqrestore(&sc->txbuflock, flags);
1592 if (ath5k_txbuf_setup(sc, bf, txq, padsize)) {
1594 spin_lock_irqsave(&sc->txbuflock, flags);
1595 list_add_tail(&bf->list, &sc->txbuf);
1597 spin_unlock_irqrestore(&sc->txbuflock, flags);
1600 return NETDEV_TX_OK;
1603 dev_kfree_skb_any(skb);
1604 return NETDEV_TX_OK;
1608 ath5k_tx_frame_completed(struct ath5k_softc *sc, struct sk_buff *skb,
1609 struct ath5k_tx_status *ts)
1611 struct ieee80211_tx_info *info;
1614 sc->stats.tx_all_count++;
1615 sc->stats.tx_bytes_count += skb->len;
1616 info = IEEE80211_SKB_CB(skb);
1618 ieee80211_tx_info_clear_status(info);
1619 for (i = 0; i < 4; i++) {
1620 struct ieee80211_tx_rate *r =
1621 &info->status.rates[i];
1623 if (ts->ts_rate[i]) {
1624 r->idx = ath5k_hw_to_driver_rix(sc, ts->ts_rate[i]);
1625 r->count = ts->ts_retry[i];
1632 /* count the successful attempt as well */
1633 info->status.rates[ts->ts_final_idx].count++;
1635 if (unlikely(ts->ts_status)) {
1636 sc->stats.ack_fail++;
1637 if (ts->ts_status & AR5K_TXERR_FILT) {
1638 info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
1639 sc->stats.txerr_filt++;
1641 if (ts->ts_status & AR5K_TXERR_XRETRY)
1642 sc->stats.txerr_retry++;
1643 if (ts->ts_status & AR5K_TXERR_FIFO)
1644 sc->stats.txerr_fifo++;
1646 info->flags |= IEEE80211_TX_STAT_ACK;
1647 info->status.ack_signal = ts->ts_rssi;
1651 * Remove MAC header padding before giving the frame
1654 ath5k_remove_padding(skb);
1656 if (ts->ts_antenna > 0 && ts->ts_antenna < 5)
1657 sc->stats.antenna_tx[ts->ts_antenna]++;
1659 sc->stats.antenna_tx[0]++; /* invalid */
1661 ieee80211_tx_status(sc->hw, skb);
1665 ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1667 struct ath5k_tx_status ts = {};
1668 struct ath5k_buf *bf, *bf0;
1669 struct ath5k_desc *ds;
1670 struct sk_buff *skb;
1673 spin_lock(&txq->lock);
1674 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1676 txq->txq_poll_mark = false;
1678 /* skb might already have been processed last time. */
1679 if (bf->skb != NULL) {
1682 ret = sc->ah->ah_proc_tx_desc(sc->ah, ds, &ts);
1683 if (unlikely(ret == -EINPROGRESS))
1685 else if (unlikely(ret)) {
1687 "error %d while processing "
1688 "queue %u\n", ret, txq->qnum);
1694 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len,
1696 ath5k_tx_frame_completed(sc, skb, &ts);
1700 * It's possible that the hardware can say the buffer is
1701 * completed when it hasn't yet loaded the ds_link from
1702 * host memory and moved on.
1703 * Always keep the last descriptor to avoid HW races...
1705 if (ath5k_hw_get_txdp(sc->ah, txq->qnum) != bf->daddr) {
1706 spin_lock(&sc->txbuflock);
1707 list_move_tail(&bf->list, &sc->txbuf);
1710 spin_unlock(&sc->txbuflock);
1713 spin_unlock(&txq->lock);
1714 if (txq->txq_len < ATH5K_TXQ_LEN_LOW && txq->qnum < 4)
1715 ieee80211_wake_queue(sc->hw, txq->qnum);
1719 ath5k_tasklet_tx(unsigned long data)
1722 struct ath5k_softc *sc = (void *)data;
1724 for (i=0; i < AR5K_NUM_TX_QUEUES; i++)
1725 if (sc->txqs[i].setup && (sc->ah->ah_txq_isr & BIT(i)))
1726 ath5k_tx_processq(sc, &sc->txqs[i]);
1735 * Setup the beacon frame for transmit.
1738 ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1740 struct sk_buff *skb = bf->skb;
1741 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1742 struct ath5k_hw *ah = sc->ah;
1743 struct ath5k_desc *ds;
1747 const int padsize = 0;
1749 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1751 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
1752 "skbaddr %llx\n", skb, skb->data, skb->len,
1753 (unsigned long long)bf->skbaddr);
1754 if (pci_dma_mapping_error(sc->pdev, bf->skbaddr)) {
1755 ATH5K_ERR(sc, "beacon DMA mapping failed\n");
1760 antenna = ah->ah_tx_ant;
1762 flags = AR5K_TXDESC_NOACK;
1763 if (sc->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) {
1764 ds->ds_link = bf->daddr; /* self-linked */
1765 flags |= AR5K_TXDESC_VEOL;
1770 * If we use multiple antennas on AP and use
1771 * the Sectored AP scenario, switch antenna every
1772 * 4 beacons to make sure everybody hears our AP.
1773 * When a client tries to associate, hw will keep
1774 * track of the tx antenna to be used for this client
1775 * automaticaly, based on ACKed packets.
1777 * Note: AP still listens and transmits RTS on the
1778 * default antenna which is supposed to be an omni.
1780 * Note2: On sectored scenarios it's possible to have
1781 * multiple antennas (1 omni -- the default -- and 14
1782 * sectors), so if we choose to actually support this
1783 * mode, we need to allow the user to set how many antennas
1784 * we have and tweak the code below to send beacons
1787 if (ah->ah_ant_mode == AR5K_ANTMODE_SECTOR_AP)
1788 antenna = sc->bsent & 4 ? 2 : 1;
1791 /* FIXME: If we are in g mode and rate is a CCK rate
1792 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
1793 * from tx power (value is in dB units already) */
1794 ds->ds_data = bf->skbaddr;
1795 ret = ah->ah_setup_tx_desc(ah, ds, skb->len,
1796 ieee80211_get_hdrlen_from_skb(skb), padsize,
1797 AR5K_PKT_TYPE_BEACON, (sc->power_level * 2),
1798 ieee80211_get_tx_rate(sc->hw, info)->hw_value,
1799 1, AR5K_TXKEYIX_INVALID,
1800 antenna, flags, 0, 0);
1806 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
1811 * Updates the beacon that is sent by ath5k_beacon_send. For adhoc,
1812 * this is called only once at config_bss time, for AP we do it every
1813 * SWBA interrupt so that the TIM will reflect buffered frames.
1815 * Called with the beacon lock.
1818 ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
1821 struct ath5k_softc *sc = hw->priv;
1822 struct ath5k_vif *avf = (void *)vif->drv_priv;
1823 struct sk_buff *skb;
1825 if (WARN_ON(!vif)) {
1830 skb = ieee80211_beacon_get(hw, vif);
1837 ath5k_debug_dump_skb(sc, skb, "BC ", 1);
1839 ath5k_txbuf_free_skb(sc, avf->bbuf);
1840 avf->bbuf->skb = skb;
1841 ret = ath5k_beacon_setup(sc, avf->bbuf);
1843 avf->bbuf->skb = NULL;
1849 * Transmit a beacon frame at SWBA. Dynamic updates to the
1850 * frame contents are done as needed and the slot time is
1851 * also adjusted based on current state.
1853 * This is called from software irq context (beacontq tasklets)
1854 * or user context from ath5k_beacon_config.
1857 ath5k_beacon_send(struct ath5k_softc *sc)
1859 struct ath5k_hw *ah = sc->ah;
1860 struct ieee80211_vif *vif;
1861 struct ath5k_vif *avf;
1862 struct ath5k_buf *bf;
1863 struct sk_buff *skb;
1865 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "in beacon_send\n");
1868 * Check if the previous beacon has gone out. If
1869 * not, don't don't try to post another: skip this
1870 * period and wait for the next. Missed beacons
1871 * indicate a problem and should not occur. If we
1872 * miss too many consecutive beacons reset the device.
1874 if (unlikely(ath5k_hw_num_tx_pending(ah, sc->bhalq) != 0)) {
1876 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1877 "missed %u consecutive beacons\n", sc->bmisscount);
1878 if (sc->bmisscount > 10) { /* NB: 10 is a guess */
1879 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1880 "stuck beacon time (%u missed)\n",
1882 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
1883 "stuck beacon, resetting\n");
1884 ieee80211_queue_work(sc->hw, &sc->reset_work);
1888 if (unlikely(sc->bmisscount != 0)) {
1889 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1890 "resume beacon xmit after %u misses\n",
1895 if (sc->opmode == NL80211_IFTYPE_AP && sc->num_ap_vifs > 1) {
1896 u64 tsf = ath5k_hw_get_tsf64(ah);
1897 u32 tsftu = TSF_TO_TU(tsf);
1898 int slot = ((tsftu % sc->bintval) * ATH_BCBUF) / sc->bintval;
1899 vif = sc->bslot[(slot + 1) % ATH_BCBUF];
1900 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1901 "tsf %llx tsftu %x intval %u slot %u vif %p\n",
1902 (unsigned long long)tsf, tsftu, sc->bintval, slot, vif);
1903 } else /* only one interface */
1909 avf = (void *)vif->drv_priv;
1911 if (unlikely(bf->skb == NULL || sc->opmode == NL80211_IFTYPE_STATION ||
1912 sc->opmode == NL80211_IFTYPE_MONITOR)) {
1913 ATH5K_WARN(sc, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL);
1918 * Stop any current dma and put the new frame on the queue.
1919 * This should never fail since we check above that no frames
1920 * are still pending on the queue.
1922 if (unlikely(ath5k_hw_stop_tx_dma(ah, sc->bhalq))) {
1923 ATH5K_WARN(sc, "beacon queue %u didn't start/stop ?\n", sc->bhalq);
1924 /* NB: hw still stops DMA, so proceed */
1927 /* refresh the beacon for AP mode */
1928 if (sc->opmode == NL80211_IFTYPE_AP)
1929 ath5k_beacon_update(sc->hw, vif);
1931 ath5k_hw_set_txdp(ah, sc->bhalq, bf->daddr);
1932 ath5k_hw_start_tx_dma(ah, sc->bhalq);
1933 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
1934 sc->bhalq, (unsigned long long)bf->daddr, bf->desc);
1936 skb = ieee80211_get_buffered_bc(sc->hw, vif);
1938 ath5k_tx_queue(sc->hw, skb, sc->cabq);
1939 skb = ieee80211_get_buffered_bc(sc->hw, vif);
1946 * ath5k_beacon_update_timers - update beacon timers
1948 * @sc: struct ath5k_softc pointer we are operating on
1949 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
1950 * beacon timer update based on the current HW TSF.
1952 * Calculate the next target beacon transmit time (TBTT) based on the timestamp
1953 * of a received beacon or the current local hardware TSF and write it to the
1954 * beacon timer registers.
1956 * This is called in a variety of situations, e.g. when a beacon is received,
1957 * when a TSF update has been detected, but also when an new IBSS is created or
1958 * when we otherwise know we have to update the timers, but we keep it in this
1959 * function to have it all together in one place.
1962 ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
1964 struct ath5k_hw *ah = sc->ah;
1965 u32 nexttbtt, intval, hw_tu, bc_tu;
1968 intval = sc->bintval & AR5K_BEACON_PERIOD;
1969 if (sc->opmode == NL80211_IFTYPE_AP && sc->num_ap_vifs > 1) {
1970 intval /= ATH_BCBUF; /* staggered multi-bss beacons */
1972 ATH5K_WARN(sc, "intval %u is too low, min 15\n",
1975 if (WARN_ON(!intval))
1978 /* beacon TSF converted to TU */
1979 bc_tu = TSF_TO_TU(bc_tsf);
1981 /* current TSF converted to TU */
1982 hw_tsf = ath5k_hw_get_tsf64(ah);
1983 hw_tu = TSF_TO_TU(hw_tsf);
1985 #define FUDGE AR5K_TUNE_SW_BEACON_RESP + 3
1986 /* We use FUDGE to make sure the next TBTT is ahead of the current TU.
1987 * Since we later substract AR5K_TUNE_SW_BEACON_RESP (10) in the timer
1988 * configuration we need to make sure it is bigger than that. */
1992 * no beacons received, called internally.
1993 * just need to refresh timers based on HW TSF.
1995 nexttbtt = roundup(hw_tu + FUDGE, intval);
1996 } else if (bc_tsf == 0) {
1998 * no beacon received, probably called by ath5k_reset_tsf().
1999 * reset TSF to start with 0.
2002 intval |= AR5K_BEACON_RESET_TSF;
2003 } else if (bc_tsf > hw_tsf) {
2005 * beacon received, SW merge happend but HW TSF not yet updated.
2006 * not possible to reconfigure timers yet, but next time we
2007 * receive a beacon with the same BSSID, the hardware will
2008 * automatically update the TSF and then we need to reconfigure
2011 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2012 "need to wait for HW TSF sync\n");
2016 * most important case for beacon synchronization between STA.
2018 * beacon received and HW TSF has been already updated by HW.
2019 * update next TBTT based on the TSF of the beacon, but make
2020 * sure it is ahead of our local TSF timer.
2022 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval);
2026 sc->nexttbtt = nexttbtt;
2028 intval |= AR5K_BEACON_ENA;
2029 ath5k_hw_init_beacon(ah, nexttbtt, intval);
2032 * debugging output last in order to preserve the time critical aspect
2036 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2037 "reconfigured timers based on HW TSF\n");
2038 else if (bc_tsf == 0)
2039 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2040 "reset HW TSF and timers\n");
2042 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2043 "updated timers based on beacon TSF\n");
2045 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2046 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2047 (unsigned long long) bc_tsf,
2048 (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt);
2049 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "intval %u %s %s\n",
2050 intval & AR5K_BEACON_PERIOD,
2051 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "",
2052 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : "");
2056 * ath5k_beacon_config - Configure the beacon queues and interrupts
2058 * @sc: struct ath5k_softc pointer we are operating on
2060 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
2061 * interrupts to detect TSF updates only.
2064 ath5k_beacon_config(struct ath5k_softc *sc)
2066 struct ath5k_hw *ah = sc->ah;
2067 unsigned long flags;
2069 spin_lock_irqsave(&sc->block, flags);
2071 sc->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA);
2073 if (sc->enable_beacon) {
2075 * In IBSS mode we use a self-linked tx descriptor and let the
2076 * hardware send the beacons automatically. We have to load it
2078 * We use the SWBA interrupt only to keep track of the beacon
2079 * timers in order to detect automatic TSF updates.
2081 ath5k_beaconq_config(sc);
2083 sc->imask |= AR5K_INT_SWBA;
2085 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
2086 if (ath5k_hw_hasveol(ah))
2087 ath5k_beacon_send(sc);
2089 ath5k_beacon_update_timers(sc, -1);
2091 ath5k_hw_stop_tx_dma(sc->ah, sc->bhalq);
2094 ath5k_hw_set_imr(ah, sc->imask);
2096 spin_unlock_irqrestore(&sc->block, flags);
2099 static void ath5k_tasklet_beacon(unsigned long data)
2101 struct ath5k_softc *sc = (struct ath5k_softc *) data;
2104 * Software beacon alert--time to send a beacon.
2106 * In IBSS mode we use this interrupt just to
2107 * keep track of the next TBTT (target beacon
2108 * transmission time) in order to detect wether
2109 * automatic TSF updates happened.
2111 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
2112 /* XXX: only if VEOL suppported */
2113 u64 tsf = ath5k_hw_get_tsf64(sc->ah);
2114 sc->nexttbtt += sc->bintval;
2115 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2116 "SWBA nexttbtt: %x hw_tu: %x "
2120 (unsigned long long) tsf);
2122 spin_lock(&sc->block);
2123 ath5k_beacon_send(sc);
2124 spin_unlock(&sc->block);
2129 /********************\
2130 * Interrupt handling *
2131 \********************/
2134 ath5k_intr_calibration_poll(struct ath5k_hw *ah)
2136 if (time_is_before_eq_jiffies(ah->ah_cal_next_ani) &&
2137 !(ah->ah_cal_mask & AR5K_CALIBRATION_FULL)) {
2138 /* run ANI only when full calibration is not active */
2139 ah->ah_cal_next_ani = jiffies +
2140 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_ANI);
2141 tasklet_schedule(&ah->ah_sc->ani_tasklet);
2143 } else if (time_is_before_eq_jiffies(ah->ah_cal_next_full)) {
2144 ah->ah_cal_next_full = jiffies +
2145 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_FULL);
2146 tasklet_schedule(&ah->ah_sc->calib);
2148 /* we could use SWI to generate enough interrupts to meet our
2149 * calibration interval requirements, if necessary:
2150 * AR5K_REG_ENABLE_BITS(ah, AR5K_CR, AR5K_CR_SWI); */
2154 ath5k_intr(int irq, void *dev_id)
2156 struct ath5k_softc *sc = dev_id;
2157 struct ath5k_hw *ah = sc->ah;
2158 enum ath5k_int status;
2159 unsigned int counter = 1000;
2161 if (unlikely(test_bit(ATH_STAT_INVALID, sc->status) ||
2162 !ath5k_hw_is_intr_pending(ah)))
2166 ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */
2167 ATH5K_DBG(sc, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
2169 if (unlikely(status & AR5K_INT_FATAL)) {
2171 * Fatal errors are unrecoverable.
2172 * Typically these are caused by DMA errors.
2174 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2175 "fatal int, resetting\n");
2176 ieee80211_queue_work(sc->hw, &sc->reset_work);
2177 } else if (unlikely(status & AR5K_INT_RXORN)) {
2179 * Receive buffers are full. Either the bus is busy or
2180 * the CPU is not fast enough to process all received
2182 * Older chipsets need a reset to come out of this
2183 * condition, but we treat it as RX for newer chips.
2184 * We don't know exactly which versions need a reset -
2185 * this guess is copied from the HAL.
2187 sc->stats.rxorn_intr++;
2188 if (ah->ah_mac_srev < AR5K_SREV_AR5212) {
2189 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2190 "rx overrun, resetting\n");
2191 ieee80211_queue_work(sc->hw, &sc->reset_work);
2194 tasklet_schedule(&sc->rxtq);
2196 if (status & AR5K_INT_SWBA) {
2197 tasklet_hi_schedule(&sc->beacontq);
2199 if (status & AR5K_INT_RXEOL) {
2201 * NB: the hardware should re-read the link when
2202 * RXE bit is written, but it doesn't work at
2203 * least on older hardware revs.
2205 sc->stats.rxeol_intr++;
2207 if (status & AR5K_INT_TXURN) {
2208 /* bump tx trigger level */
2209 ath5k_hw_update_tx_triglevel(ah, true);
2211 if (status & (AR5K_INT_RXOK | AR5K_INT_RXERR))
2212 tasklet_schedule(&sc->rxtq);
2213 if (status & (AR5K_INT_TXOK | AR5K_INT_TXDESC
2214 | AR5K_INT_TXERR | AR5K_INT_TXEOL))
2215 tasklet_schedule(&sc->txtq);
2216 if (status & AR5K_INT_BMISS) {
2219 if (status & AR5K_INT_MIB) {
2220 sc->stats.mib_intr++;
2221 ath5k_hw_update_mib_counters(ah);
2222 ath5k_ani_mib_intr(ah);
2224 if (status & AR5K_INT_GPIO)
2225 tasklet_schedule(&sc->rf_kill.toggleq);
2228 } while (ath5k_hw_is_intr_pending(ah) && --counter > 0);
2230 if (unlikely(!counter))
2231 ATH5K_WARN(sc, "too many interrupts, giving up for now\n");
2233 ath5k_intr_calibration_poll(ah);
2239 * Periodically recalibrate the PHY to account
2240 * for temperature/environment changes.
2243 ath5k_tasklet_calibrate(unsigned long data)
2245 struct ath5k_softc *sc = (void *)data;
2246 struct ath5k_hw *ah = sc->ah;
2248 /* Only full calibration for now */
2249 ah->ah_cal_mask |= AR5K_CALIBRATION_FULL;
2251 ATH5K_DBG(sc, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
2252 ieee80211_frequency_to_channel(sc->curchan->center_freq),
2253 sc->curchan->hw_value);
2255 if (ath5k_hw_gainf_calibrate(ah) == AR5K_RFGAIN_NEED_CHANGE) {
2257 * Rfgain is out of bounds, reset the chip
2258 * to load new gain values.
2260 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "calibration, resetting\n");
2261 ieee80211_queue_work(sc->hw, &sc->reset_work);
2263 if (ath5k_hw_phy_calibrate(ah, sc->curchan))
2264 ATH5K_ERR(sc, "calibration of channel %u failed\n",
2265 ieee80211_frequency_to_channel(
2266 sc->curchan->center_freq));
2268 /* Noise floor calibration interrupts rx/tx path while I/Q calibration
2270 * TODO: We should stop TX here, so that it doesn't interfere.
2271 * Note that stopping the queues is not enough to stop TX! */
2272 if (time_is_before_eq_jiffies(ah->ah_cal_next_nf)) {
2273 ah->ah_cal_next_nf = jiffies +
2274 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_NF);
2275 ath5k_hw_update_noise_floor(ah);
2278 ah->ah_cal_mask &= ~AR5K_CALIBRATION_FULL;
2283 ath5k_tasklet_ani(unsigned long data)
2285 struct ath5k_softc *sc = (void *)data;
2286 struct ath5k_hw *ah = sc->ah;
2288 ah->ah_cal_mask |= AR5K_CALIBRATION_ANI;
2289 ath5k_ani_calibration(ah);
2290 ah->ah_cal_mask &= ~AR5K_CALIBRATION_ANI;
2295 ath5k_tx_complete_poll_work(struct work_struct *work)
2297 struct ath5k_softc *sc = container_of(work, struct ath5k_softc,
2298 tx_complete_work.work);
2299 struct ath5k_txq *txq;
2301 bool needreset = false;
2303 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++) {
2304 if (sc->txqs[i].setup) {
2306 spin_lock_bh(&txq->lock);
2307 if (txq->txq_len > 1) {
2308 if (txq->txq_poll_mark) {
2309 ATH5K_DBG(sc, ATH5K_DEBUG_XMIT,
2310 "TX queue stuck %d\n",
2314 spin_unlock_bh(&txq->lock);
2317 txq->txq_poll_mark = true;
2320 spin_unlock_bh(&txq->lock);
2325 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2326 "TX queues stuck, resetting\n");
2327 ath5k_reset(sc, sc->curchan);
2330 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work,
2331 msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT));
2335 /*************************\
2336 * Initialization routines *
2337 \*************************/
2340 ath5k_stop_locked(struct ath5k_softc *sc)
2342 struct ath5k_hw *ah = sc->ah;
2344 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "invalid %u\n",
2345 test_bit(ATH_STAT_INVALID, sc->status));
2348 * Shutdown the hardware and driver:
2349 * stop output from above
2350 * disable interrupts
2352 * turn off the radio
2353 * clear transmit machinery
2354 * clear receive machinery
2355 * drain and release tx queues
2356 * reclaim beacon resources
2357 * power down hardware
2359 * Note that some of this work is not possible if the
2360 * hardware is gone (invalid).
2362 ieee80211_stop_queues(sc->hw);
2364 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2366 ath5k_hw_set_imr(ah, 0);
2367 synchronize_irq(sc->pdev->irq);
2369 ath5k_txq_cleanup(sc);
2370 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2372 ath5k_hw_phy_disable(ah);
2379 ath5k_init(struct ath5k_softc *sc)
2381 struct ath5k_hw *ah = sc->ah;
2382 struct ath_common *common = ath5k_hw_common(ah);
2385 mutex_lock(&sc->lock);
2387 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mode %d\n", sc->opmode);
2390 * Stop anything previously setup. This is safe
2391 * no matter this is the first time through or not.
2393 ath5k_stop_locked(sc);
2396 * The basic interface to setting the hardware in a good
2397 * state is ``reset''. On return the hardware is known to
2398 * be powered up and with interrupts disabled. This must
2399 * be followed by initialization of the appropriate bits
2400 * and then setup of the interrupt mask.
2402 sc->curchan = sc->hw->conf.channel;
2403 sc->curband = &sc->sbands[sc->curchan->band];
2404 sc->imask = AR5K_INT_RXOK | AR5K_INT_RXERR | AR5K_INT_RXEOL |
2405 AR5K_INT_RXORN | AR5K_INT_TXDESC | AR5K_INT_TXEOL |
2406 AR5K_INT_FATAL | AR5K_INT_GLOBAL | AR5K_INT_MIB;
2408 ret = ath5k_reset(sc, NULL);
2412 ath5k_rfkill_hw_start(ah);
2415 * Reset the key cache since some parts do not reset the
2416 * contents on initial power up or resume from suspend.
2418 for (i = 0; i < common->keymax; i++)
2419 ath_hw_keyreset(common, (u16) i);
2421 ath5k_hw_set_ack_bitrate_high(ah, true);
2423 for (i = 0; i < ARRAY_SIZE(sc->bslot); i++)
2424 sc->bslot[i] = NULL;
2429 mutex_unlock(&sc->lock);
2431 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work,
2432 msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT));
2437 static void stop_tasklets(struct ath5k_softc *sc)
2439 tasklet_kill(&sc->rxtq);
2440 tasklet_kill(&sc->txtq);
2441 tasklet_kill(&sc->calib);
2442 tasklet_kill(&sc->beacontq);
2443 tasklet_kill(&sc->ani_tasklet);
2447 * Stop the device, grabbing the top-level lock to protect
2448 * against concurrent entry through ath5k_init (which can happen
2449 * if another thread does a system call and the thread doing the
2450 * stop is preempted).
2453 ath5k_stop_hw(struct ath5k_softc *sc)
2457 mutex_lock(&sc->lock);
2458 ret = ath5k_stop_locked(sc);
2459 if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) {
2461 * Don't set the card in full sleep mode!
2463 * a) When the device is in this state it must be carefully
2464 * woken up or references to registers in the PCI clock
2465 * domain may freeze the bus (and system). This varies
2466 * by chip and is mostly an issue with newer parts
2467 * (madwifi sources mentioned srev >= 0x78) that go to
2468 * sleep more quickly.
2470 * b) On older chips full sleep results a weird behaviour
2471 * during wakeup. I tested various cards with srev < 0x78
2472 * and they don't wake up after module reload, a second
2473 * module reload is needed to bring the card up again.
2475 * Until we figure out what's going on don't enable
2476 * full chip reset on any chip (this is what Legacy HAL
2477 * and Sam's HAL do anyway). Instead Perform a full reset
2478 * on the device (same as initial state after attach) and
2479 * leave it idle (keep MAC/BB on warm reset) */
2480 ret = ath5k_hw_on_hold(sc->ah);
2482 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2483 "putting device to sleep\n");
2487 mutex_unlock(&sc->lock);
2491 cancel_delayed_work_sync(&sc->tx_complete_work);
2493 ath5k_rfkill_hw_stop(sc->ah);
2499 * Reset the hardware. If chan is not NULL, then also pause rx/tx
2500 * and change to the given channel.
2502 * This should be called with sc->lock.
2505 ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan)
2507 struct ath5k_hw *ah = sc->ah;
2510 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n");
2512 ath5k_hw_set_imr(ah, 0);
2513 synchronize_irq(sc->pdev->irq);
2517 ath5k_txq_cleanup(sc);
2521 sc->curband = &sc->sbands[chan->band];
2523 ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, chan != NULL);
2525 ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret);
2529 ret = ath5k_rx_start(sc);
2531 ATH5K_ERR(sc, "can't start recv logic\n");
2535 ath5k_ani_init(ah, ah->ah_sc->ani_state.ani_mode);
2537 ah->ah_cal_next_full = jiffies;
2538 ah->ah_cal_next_ani = jiffies;
2539 ah->ah_cal_next_nf = jiffies;
2542 * Change channels and update the h/w rate map if we're switching;
2543 * e.g. 11a to 11b/g.
2545 * We may be doing a reset in response to an ioctl that changes the
2546 * channel so update any state that might change as a result.
2550 /* ath5k_chan_change(sc, c); */
2552 ath5k_beacon_config(sc);
2553 /* intrs are enabled by ath5k_beacon_config */
2555 ieee80211_wake_queues(sc->hw);
2562 static void ath5k_reset_work(struct work_struct *work)
2564 struct ath5k_softc *sc = container_of(work, struct ath5k_softc,
2567 mutex_lock(&sc->lock);
2568 ath5k_reset(sc, sc->curchan);
2569 mutex_unlock(&sc->lock);
2573 ath5k_attach(struct pci_dev *pdev, struct ieee80211_hw *hw)
2575 struct ath5k_softc *sc = hw->priv;
2576 struct ath5k_hw *ah = sc->ah;
2577 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah);
2578 struct ath5k_txq *txq;
2579 u8 mac[ETH_ALEN] = {};
2582 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "devid 0x%x\n", pdev->device);
2585 * Check if the MAC has multi-rate retry support.
2586 * We do this by trying to setup a fake extended
2587 * descriptor. MACs that don't have support will
2588 * return false w/o doing anything. MACs that do
2589 * support it will return true w/o doing anything.
2591 ret = ath5k_hw_setup_mrr_tx_desc(ah, NULL, 0, 0, 0, 0, 0, 0);
2596 __set_bit(ATH_STAT_MRRETRY, sc->status);
2599 * Collect the channel list. The 802.11 layer
2600 * is resposible for filtering this list based
2601 * on settings like the phy mode and regulatory
2602 * domain restrictions.
2604 ret = ath5k_setup_bands(hw);
2606 ATH5K_ERR(sc, "can't get channels\n");
2610 /* NB: setup here so ath5k_rate_update is happy */
2611 if (test_bit(AR5K_MODE_11A, ah->ah_modes))
2612 ath5k_setcurmode(sc, AR5K_MODE_11A);
2614 ath5k_setcurmode(sc, AR5K_MODE_11B);
2617 * Allocate tx+rx descriptors and populate the lists.
2619 ret = ath5k_desc_alloc(sc, pdev);
2621 ATH5K_ERR(sc, "can't allocate descriptors\n");
2626 * Allocate hardware transmit queues: one queue for
2627 * beacon frames and one data queue for each QoS
2628 * priority. Note that hw functions handle resetting
2629 * these queues at the needed time.
2631 ret = ath5k_beaconq_setup(ah);
2633 ATH5K_ERR(sc, "can't setup a beacon xmit queue\n");
2637 sc->cabq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_CAB, 0);
2638 if (IS_ERR(sc->cabq)) {
2639 ATH5K_ERR(sc, "can't setup cab queue\n");
2640 ret = PTR_ERR(sc->cabq);
2644 /* This order matches mac80211's queue priority, so we can
2645 * directly use the mac80211 queue number without any mapping */
2646 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VO);
2648 ATH5K_ERR(sc, "can't setup xmit queue\n");
2652 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VI);
2654 ATH5K_ERR(sc, "can't setup xmit queue\n");
2658 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BE);
2660 ATH5K_ERR(sc, "can't setup xmit queue\n");
2664 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
2666 ATH5K_ERR(sc, "can't setup xmit queue\n");
2672 tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc);
2673 tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc);
2674 tasklet_init(&sc->calib, ath5k_tasklet_calibrate, (unsigned long)sc);
2675 tasklet_init(&sc->beacontq, ath5k_tasklet_beacon, (unsigned long)sc);
2676 tasklet_init(&sc->ani_tasklet, ath5k_tasklet_ani, (unsigned long)sc);
2678 INIT_WORK(&sc->reset_work, ath5k_reset_work);
2679 INIT_DELAYED_WORK(&sc->tx_complete_work, ath5k_tx_complete_poll_work);
2681 ret = ath5k_eeprom_read_mac(ah, mac);
2683 ATH5K_ERR(sc, "unable to read address from EEPROM: 0x%04x\n",
2688 SET_IEEE80211_PERM_ADDR(hw, mac);
2689 memcpy(&sc->lladdr, mac, ETH_ALEN);
2690 /* All MAC address bits matter for ACKs */
2691 ath5k_update_bssid_mask(sc, NULL);
2693 regulatory->current_rd = ah->ah_capabilities.cap_eeprom.ee_regdomain;
2694 ret = ath_regd_init(regulatory, hw->wiphy, ath5k_reg_notifier);
2696 ATH5K_ERR(sc, "can't initialize regulatory system\n");
2700 ret = ieee80211_register_hw(hw);
2702 ATH5K_ERR(sc, "can't register ieee80211 hw\n");
2706 if (!ath_is_world_regd(regulatory))
2707 regulatory_hint(hw->wiphy, regulatory->alpha2);
2709 ath5k_init_leds(sc);
2711 ath5k_sysfs_register(sc);
2715 ath5k_txq_release(sc);
2717 ath5k_hw_release_tx_queue(ah, sc->bhalq);
2719 ath5k_desc_free(sc, pdev);
2725 ath5k_detach(struct pci_dev *pdev, struct ieee80211_hw *hw)
2727 struct ath5k_softc *sc = hw->priv;
2730 * NB: the order of these is important:
2731 * o call the 802.11 layer before detaching ath5k_hw to
2732 * ensure callbacks into the driver to delete global
2733 * key cache entries can be handled
2734 * o reclaim the tx queue data structures after calling
2735 * the 802.11 layer as we'll get called back to reclaim
2736 * node state and potentially want to use them
2737 * o to cleanup the tx queues the hal is called, so detach
2739 * XXX: ??? detach ath5k_hw ???
2740 * Other than that, it's straightforward...
2742 ieee80211_unregister_hw(hw);
2743 ath5k_desc_free(sc, pdev);
2744 ath5k_txq_release(sc);
2745 ath5k_hw_release_tx_queue(sc->ah, sc->bhalq);
2746 ath5k_unregister_leds(sc);
2748 ath5k_sysfs_unregister(sc);
2750 * NB: can't reclaim these until after ieee80211_ifdetach
2751 * returns because we'll get called back to reclaim node
2752 * state and potentially want to use them.
2756 /********************\
2757 * Mac80211 functions *
2758 \********************/
2761 ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
2763 struct ath5k_softc *sc = hw->priv;
2764 u16 qnum = skb_get_queue_mapping(skb);
2766 if (WARN_ON(qnum >= sc->ah->ah_capabilities.cap_queues.q_tx_num)) {
2767 dev_kfree_skb_any(skb);
2771 return ath5k_tx_queue(hw, skb, &sc->txqs[qnum]);
2774 static int ath5k_start(struct ieee80211_hw *hw)
2776 return ath5k_init(hw->priv);
2779 static void ath5k_stop(struct ieee80211_hw *hw)
2781 ath5k_stop_hw(hw->priv);
2784 static int ath5k_add_interface(struct ieee80211_hw *hw,
2785 struct ieee80211_vif *vif)
2787 struct ath5k_softc *sc = hw->priv;
2789 struct ath5k_hw *ah = sc->ah;
2790 struct ath5k_vif *avf = (void *)vif->drv_priv;
2792 mutex_lock(&sc->lock);
2794 if ((vif->type == NL80211_IFTYPE_AP ||
2795 vif->type == NL80211_IFTYPE_ADHOC)
2796 && (sc->num_ap_vifs + sc->num_adhoc_vifs) >= ATH_BCBUF) {
2801 /* Don't allow other interfaces if one ad-hoc is configured.
2802 * TODO: Fix the problems with ad-hoc and multiple other interfaces.
2803 * We would need to operate the HW in ad-hoc mode to allow TSF updates
2804 * for the IBSS, but this breaks with additional AP or STA interfaces
2806 if (sc->num_adhoc_vifs ||
2807 (sc->nvifs && vif->type == NL80211_IFTYPE_ADHOC)) {
2808 ATH5K_ERR(sc, "Only one single ad-hoc interface is allowed.\n");
2813 switch (vif->type) {
2814 case NL80211_IFTYPE_AP:
2815 case NL80211_IFTYPE_STATION:
2816 case NL80211_IFTYPE_ADHOC:
2817 case NL80211_IFTYPE_MESH_POINT:
2818 avf->opmode = vif->type;
2826 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "add interface mode %d\n", avf->opmode);
2828 /* Assign the vap/adhoc to a beacon xmit slot. */
2829 if ((avf->opmode == NL80211_IFTYPE_AP) ||
2830 (avf->opmode == NL80211_IFTYPE_ADHOC)) {
2833 WARN_ON(list_empty(&sc->bcbuf));
2834 avf->bbuf = list_first_entry(&sc->bcbuf, struct ath5k_buf,
2836 list_del(&avf->bbuf->list);
2839 for (slot = 0; slot < ATH_BCBUF; slot++) {
2840 if (!sc->bslot[slot]) {
2845 BUG_ON(sc->bslot[avf->bslot] != NULL);
2846 sc->bslot[avf->bslot] = vif;
2847 if (avf->opmode == NL80211_IFTYPE_AP)
2850 sc->num_adhoc_vifs++;
2853 /* Set combined mode - when APs are configured, operate in AP mode.
2854 * Otherwise use the mode of the new interface. This can currently
2855 * only deal with combinations of APs and STAs. Only one ad-hoc
2856 * interfaces is allowed above.
2858 if (sc->num_ap_vifs)
2859 sc->opmode = NL80211_IFTYPE_AP;
2861 sc->opmode = vif->type;
2863 ath5k_hw_set_opmode(ah, sc->opmode);
2865 /* Any MAC address is fine, all others are included through the
2868 memcpy(&sc->lladdr, vif->addr, ETH_ALEN);
2869 ath5k_hw_set_lladdr(sc->ah, vif->addr);
2871 memcpy(&avf->lladdr, vif->addr, ETH_ALEN);
2873 ath5k_mode_setup(sc, vif);
2877 mutex_unlock(&sc->lock);
2882 ath5k_remove_interface(struct ieee80211_hw *hw,
2883 struct ieee80211_vif *vif)
2885 struct ath5k_softc *sc = hw->priv;
2886 struct ath5k_vif *avf = (void *)vif->drv_priv;
2889 mutex_lock(&sc->lock);
2893 ath5k_txbuf_free_skb(sc, avf->bbuf);
2894 list_add_tail(&avf->bbuf->list, &sc->bcbuf);
2895 for (i = 0; i < ATH_BCBUF; i++) {
2896 if (sc->bslot[i] == vif) {
2897 sc->bslot[i] = NULL;
2903 if (avf->opmode == NL80211_IFTYPE_AP)
2905 else if (avf->opmode == NL80211_IFTYPE_ADHOC)
2906 sc->num_adhoc_vifs--;
2908 ath5k_update_bssid_mask(sc, NULL);
2909 mutex_unlock(&sc->lock);
2913 * TODO: Phy disable/diversity etc
2916 ath5k_config(struct ieee80211_hw *hw, u32 changed)
2918 struct ath5k_softc *sc = hw->priv;
2919 struct ath5k_hw *ah = sc->ah;
2920 struct ieee80211_conf *conf = &hw->conf;
2923 mutex_lock(&sc->lock);
2925 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
2926 ret = ath5k_chan_set(sc, conf->channel);
2931 if ((changed & IEEE80211_CONF_CHANGE_POWER) &&
2932 (sc->power_level != conf->power_level)) {
2933 sc->power_level = conf->power_level;
2936 ath5k_hw_set_txpower_limit(ah, (conf->power_level * 2));
2940 * 1) Move this on config_interface and handle each case
2941 * separately eg. when we have only one STA vif, use
2942 * AR5K_ANTMODE_SINGLE_AP
2944 * 2) Allow the user to change antenna mode eg. when only
2945 * one antenna is present
2947 * 3) Allow the user to set default/tx antenna when possible
2949 * 4) Default mode should handle 90% of the cases, together
2950 * with fixed a/b and single AP modes we should be able to
2951 * handle 99%. Sectored modes are extreme cases and i still
2952 * haven't found a usage for them. If we decide to support them,
2953 * then we must allow the user to set how many tx antennas we
2956 ath5k_hw_set_antenna_mode(ah, ah->ah_ant_mode);
2959 mutex_unlock(&sc->lock);
2963 static u64 ath5k_prepare_multicast(struct ieee80211_hw *hw,
2964 struct netdev_hw_addr_list *mc_list)
2968 struct netdev_hw_addr *ha;
2973 netdev_hw_addr_list_for_each(ha, mc_list) {
2974 /* calculate XOR of eight 6-bit values */
2975 val = get_unaligned_le32(ha->addr + 0);
2976 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2977 val = get_unaligned_le32(ha->addr + 3);
2978 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2980 mfilt[pos / 32] |= (1 << (pos % 32));
2981 /* XXX: we might be able to just do this instead,
2982 * but not sure, needs testing, if we do use this we'd
2983 * neet to inform below to not reset the mcast */
2984 /* ath5k_hw_set_mcast_filterindex(ah,
2988 return ((u64)(mfilt[1]) << 32) | mfilt[0];
2991 static bool ath_any_vif_assoc(struct ath5k_softc *sc)
2993 struct ath_vif_iter_data iter_data;
2994 iter_data.hw_macaddr = NULL;
2995 iter_data.any_assoc = false;
2996 iter_data.need_set_hw_addr = false;
2997 iter_data.found_active = true;
2999 ieee80211_iterate_active_interfaces_atomic(sc->hw, ath_vif_iter,
3001 return iter_data.any_assoc;
3004 #define SUPPORTED_FIF_FLAGS \
3005 FIF_PROMISC_IN_BSS | FIF_ALLMULTI | FIF_FCSFAIL | \
3006 FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \
3007 FIF_BCN_PRBRESP_PROMISC
3009 * o always accept unicast, broadcast, and multicast traffic
3010 * o multicast traffic for all BSSIDs will be enabled if mac80211
3012 * o maintain current state of phy ofdm or phy cck error reception.
3013 * If the hardware detects any of these type of errors then
3014 * ath5k_hw_get_rx_filter() will pass to us the respective
3015 * hardware filters to be able to receive these type of frames.
3016 * o probe request frames are accepted only when operating in
3017 * hostap, adhoc, or monitor modes
3018 * o enable promiscuous mode according to the interface state
3020 * - when operating in adhoc mode so the 802.11 layer creates
3021 * node table entries for peers,
3022 * - when operating in station mode for collecting rssi data when
3023 * the station is otherwise quiet, or
3026 static void ath5k_configure_filter(struct ieee80211_hw *hw,
3027 unsigned int changed_flags,
3028 unsigned int *new_flags,
3031 struct ath5k_softc *sc = hw->priv;
3032 struct ath5k_hw *ah = sc->ah;
3033 u32 mfilt[2], rfilt;
3035 mutex_lock(&sc->lock);
3037 mfilt[0] = multicast;
3038 mfilt[1] = multicast >> 32;
3040 /* Only deal with supported flags */
3041 changed_flags &= SUPPORTED_FIF_FLAGS;
3042 *new_flags &= SUPPORTED_FIF_FLAGS;
3044 /* If HW detects any phy or radar errors, leave those filters on.
3045 * Also, always enable Unicast, Broadcasts and Multicast
3046 * XXX: move unicast, bssid broadcasts and multicast to mac80211 */
3047 rfilt = (ath5k_hw_get_rx_filter(ah) & (AR5K_RX_FILTER_PHYERR)) |
3048 (AR5K_RX_FILTER_UCAST | AR5K_RX_FILTER_BCAST |
3049 AR5K_RX_FILTER_MCAST);
3051 if (changed_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS)) {
3052 if (*new_flags & FIF_PROMISC_IN_BSS) {
3053 __set_bit(ATH_STAT_PROMISC, sc->status);
3055 __clear_bit(ATH_STAT_PROMISC, sc->status);
3059 if (test_bit(ATH_STAT_PROMISC, sc->status))
3060 rfilt |= AR5K_RX_FILTER_PROM;
3062 /* Note, AR5K_RX_FILTER_MCAST is already enabled */
3063 if (*new_flags & FIF_ALLMULTI) {
3068 /* This is the best we can do */
3069 if (*new_flags & (FIF_FCSFAIL | FIF_PLCPFAIL))
3070 rfilt |= AR5K_RX_FILTER_PHYERR;
3072 /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons
3073 * and probes for any BSSID */
3074 if ((*new_flags & FIF_BCN_PRBRESP_PROMISC) || (sc->nvifs > 1))
3075 rfilt |= AR5K_RX_FILTER_BEACON;
3077 /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not
3078 * set we should only pass on control frames for this
3079 * station. This needs testing. I believe right now this
3080 * enables *all* control frames, which is OK.. but
3081 * but we should see if we can improve on granularity */
3082 if (*new_flags & FIF_CONTROL)
3083 rfilt |= AR5K_RX_FILTER_CONTROL;
3085 /* Additional settings per mode -- this is per ath5k */
3087 /* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */
3089 switch (sc->opmode) {
3090 case NL80211_IFTYPE_MESH_POINT:
3091 rfilt |= AR5K_RX_FILTER_CONTROL |
3092 AR5K_RX_FILTER_BEACON |
3093 AR5K_RX_FILTER_PROBEREQ |
3094 AR5K_RX_FILTER_PROM;
3096 case NL80211_IFTYPE_AP:
3097 case NL80211_IFTYPE_ADHOC:
3098 rfilt |= AR5K_RX_FILTER_PROBEREQ |
3099 AR5K_RX_FILTER_BEACON;
3101 case NL80211_IFTYPE_STATION:
3103 rfilt |= AR5K_RX_FILTER_BEACON;
3109 ath5k_hw_set_rx_filter(ah, rfilt);
3111 /* Set multicast bits */
3112 ath5k_hw_set_mcast_filter(ah, mfilt[0], mfilt[1]);
3113 /* Set the cached hw filter flags, this will later actually
3115 sc->filter_flags = rfilt;
3117 mutex_unlock(&sc->lock);
3121 ath5k_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
3122 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
3123 struct ieee80211_key_conf *key)
3125 struct ath5k_softc *sc = hw->priv;
3126 struct ath5k_hw *ah = sc->ah;
3127 struct ath_common *common = ath5k_hw_common(ah);
3130 if (modparam_nohwcrypt)
3133 switch (key->cipher) {
3134 case WLAN_CIPHER_SUITE_WEP40:
3135 case WLAN_CIPHER_SUITE_WEP104:
3136 case WLAN_CIPHER_SUITE_TKIP:
3138 case WLAN_CIPHER_SUITE_CCMP:
3139 if (common->crypt_caps & ATH_CRYPT_CAP_CIPHER_AESCCM)
3147 mutex_lock(&sc->lock);
3151 ret = ath_key_config(common, vif, sta, key);
3153 key->hw_key_idx = ret;
3154 /* push IV and Michael MIC generation to stack */
3155 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
3156 if (key->cipher == WLAN_CIPHER_SUITE_TKIP)
3157 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
3158 if (key->cipher == WLAN_CIPHER_SUITE_CCMP)
3159 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
3164 ath_key_delete(common, key);
3171 mutex_unlock(&sc->lock);
3176 ath5k_get_stats(struct ieee80211_hw *hw,
3177 struct ieee80211_low_level_stats *stats)
3179 struct ath5k_softc *sc = hw->priv;
3182 ath5k_hw_update_mib_counters(sc->ah);
3184 stats->dot11ACKFailureCount = sc->stats.ack_fail;
3185 stats->dot11RTSFailureCount = sc->stats.rts_fail;
3186 stats->dot11RTSSuccessCount = sc->stats.rts_ok;
3187 stats->dot11FCSErrorCount = sc->stats.fcs_error;
3192 static int ath5k_get_survey(struct ieee80211_hw *hw, int idx,
3193 struct survey_info *survey)
3195 struct ath5k_softc *sc = hw->priv;
3196 struct ieee80211_conf *conf = &hw->conf;
3201 survey->channel = conf->channel;
3202 survey->filled = SURVEY_INFO_NOISE_DBM;
3203 survey->noise = sc->ah->ah_noise_floor;
3209 ath5k_get_tsf(struct ieee80211_hw *hw)
3211 struct ath5k_softc *sc = hw->priv;
3213 return ath5k_hw_get_tsf64(sc->ah);
3217 ath5k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
3219 struct ath5k_softc *sc = hw->priv;
3221 ath5k_hw_set_tsf64(sc->ah, tsf);
3225 ath5k_reset_tsf(struct ieee80211_hw *hw)
3227 struct ath5k_softc *sc = hw->priv;
3230 * in IBSS mode we need to update the beacon timers too.
3231 * this will also reset the TSF if we call it with 0
3233 if (sc->opmode == NL80211_IFTYPE_ADHOC)
3234 ath5k_beacon_update_timers(sc, 0);
3236 ath5k_hw_reset_tsf(sc->ah);
3240 set_beacon_filter(struct ieee80211_hw *hw, bool enable)
3242 struct ath5k_softc *sc = hw->priv;
3243 struct ath5k_hw *ah = sc->ah;
3245 rfilt = ath5k_hw_get_rx_filter(ah);
3247 rfilt |= AR5K_RX_FILTER_BEACON;
3249 rfilt &= ~AR5K_RX_FILTER_BEACON;
3250 ath5k_hw_set_rx_filter(ah, rfilt);
3251 sc->filter_flags = rfilt;
3254 static void ath5k_bss_info_changed(struct ieee80211_hw *hw,
3255 struct ieee80211_vif *vif,
3256 struct ieee80211_bss_conf *bss_conf,
3259 struct ath5k_vif *avf = (void *)vif->drv_priv;
3260 struct ath5k_softc *sc = hw->priv;
3261 struct ath5k_hw *ah = sc->ah;
3262 struct ath_common *common = ath5k_hw_common(ah);
3263 unsigned long flags;
3265 mutex_lock(&sc->lock);
3267 if (changes & BSS_CHANGED_BSSID) {
3268 /* Cache for later use during resets */
3269 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
3271 ath5k_hw_set_bssid(ah);
3275 if (changes & BSS_CHANGED_BEACON_INT)
3276 sc->bintval = bss_conf->beacon_int;
3278 if (changes & BSS_CHANGED_ASSOC) {
3279 avf->assoc = bss_conf->assoc;
3280 if (bss_conf->assoc)
3281 sc->assoc = bss_conf->assoc;
3283 sc->assoc = ath_any_vif_assoc(sc);
3285 if (sc->opmode == NL80211_IFTYPE_STATION)
3286 set_beacon_filter(hw, sc->assoc);
3287 ath5k_hw_set_ledstate(sc->ah, sc->assoc ?
3288 AR5K_LED_ASSOC : AR5K_LED_INIT);
3289 if (bss_conf->assoc) {
3290 ATH5K_DBG(sc, ATH5K_DEBUG_ANY,
3291 "Bss Info ASSOC %d, bssid: %pM\n",
3292 bss_conf->aid, common->curbssid);
3293 common->curaid = bss_conf->aid;
3294 ath5k_hw_set_bssid(ah);
3295 /* Once ANI is available you would start it here */
3299 if (changes & BSS_CHANGED_BEACON) {
3300 spin_lock_irqsave(&sc->block, flags);
3301 ath5k_beacon_update(hw, vif);
3302 spin_unlock_irqrestore(&sc->block, flags);
3305 if (changes & BSS_CHANGED_BEACON_ENABLED)
3306 sc->enable_beacon = bss_conf->enable_beacon;
3308 if (changes & (BSS_CHANGED_BEACON | BSS_CHANGED_BEACON_ENABLED |
3309 BSS_CHANGED_BEACON_INT))
3310 ath5k_beacon_config(sc);
3312 mutex_unlock(&sc->lock);
3315 static void ath5k_sw_scan_start(struct ieee80211_hw *hw)
3317 struct ath5k_softc *sc = hw->priv;
3319 ath5k_hw_set_ledstate(sc->ah, AR5K_LED_SCAN);
3322 static void ath5k_sw_scan_complete(struct ieee80211_hw *hw)
3324 struct ath5k_softc *sc = hw->priv;
3325 ath5k_hw_set_ledstate(sc->ah, sc->assoc ?
3326 AR5K_LED_ASSOC : AR5K_LED_INIT);
3330 * ath5k_set_coverage_class - Set IEEE 802.11 coverage class
3332 * @hw: struct ieee80211_hw pointer
3333 * @coverage_class: IEEE 802.11 coverage class number
3335 * Mac80211 callback. Sets slot time, ACK timeout and CTS timeout for given
3336 * coverage class. The values are persistent, they are restored after device
3339 static void ath5k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class)
3341 struct ath5k_softc *sc = hw->priv;
3343 mutex_lock(&sc->lock);
3344 ath5k_hw_set_coverage_class(sc->ah, coverage_class);
3345 mutex_unlock(&sc->lock);
3348 static int ath5k_conf_tx(struct ieee80211_hw *hw, u16 queue,
3349 const struct ieee80211_tx_queue_params *params)
3351 struct ath5k_softc *sc = hw->priv;
3352 struct ath5k_hw *ah = sc->ah;
3353 struct ath5k_txq_info qi;
3356 if (queue >= ah->ah_capabilities.cap_queues.q_tx_num)
3359 mutex_lock(&sc->lock);
3361 ath5k_hw_get_tx_queueprops(ah, queue, &qi);
3363 qi.tqi_aifs = params->aifs;
3364 qi.tqi_cw_min = params->cw_min;
3365 qi.tqi_cw_max = params->cw_max;
3366 qi.tqi_burst_time = params->txop;
3368 ATH5K_DBG(sc, ATH5K_DEBUG_ANY,
3369 "Configure tx [queue %d], "
3370 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
3371 queue, params->aifs, params->cw_min,
3372 params->cw_max, params->txop);
3374 if (ath5k_hw_set_tx_queueprops(ah, queue, &qi)) {
3376 "Unable to update hardware queue %u!\n", queue);
3379 ath5k_hw_reset_tx_queue(ah, queue);
3381 mutex_unlock(&sc->lock);
3386 static const struct ieee80211_ops ath5k_hw_ops = {
3388 .start = ath5k_start,
3390 .add_interface = ath5k_add_interface,
3391 .remove_interface = ath5k_remove_interface,
3392 .config = ath5k_config,
3393 .prepare_multicast = ath5k_prepare_multicast,
3394 .configure_filter = ath5k_configure_filter,
3395 .set_key = ath5k_set_key,
3396 .get_stats = ath5k_get_stats,
3397 .get_survey = ath5k_get_survey,
3398 .conf_tx = ath5k_conf_tx,
3399 .get_tsf = ath5k_get_tsf,
3400 .set_tsf = ath5k_set_tsf,
3401 .reset_tsf = ath5k_reset_tsf,
3402 .bss_info_changed = ath5k_bss_info_changed,
3403 .sw_scan_start = ath5k_sw_scan_start,
3404 .sw_scan_complete = ath5k_sw_scan_complete,
3405 .set_coverage_class = ath5k_set_coverage_class,
3408 /********************\
3409 * PCI Initialization *
3410 \********************/
3412 static int __devinit
3413 ath5k_pci_probe(struct pci_dev *pdev,
3414 const struct pci_device_id *id)
3417 struct ath5k_softc *sc;
3418 struct ath_common *common;
3419 struct ieee80211_hw *hw;
3424 * L0s needs to be disabled on all ath5k cards.
3426 * For distributions shipping with CONFIG_PCIEASPM (this will be enabled
3427 * by default in the future in 2.6.36) this will also mean both L1 and
3428 * L0s will be disabled when a pre 1.1 PCIe device is detected. We do
3429 * know L1 works correctly even for all ath5k pre 1.1 PCIe devices
3430 * though but cannot currently undue the effect of a blacklist, for
3431 * details you can read pcie_aspm_sanity_check() and see how it adjusts
3432 * the device link capability.
3434 * It may be possible in the future to implement some PCI API to allow
3435 * drivers to override blacklists for pre 1.1 PCIe but for now it is
3436 * best to accept that both L0s and L1 will be disabled completely for
3437 * distributions shipping with CONFIG_PCIEASPM rather than having this
3438 * issue present. Motivation for adding this new API will be to help
3439 * with power consumption for some of these devices.
3441 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S);
3443 ret = pci_enable_device(pdev);
3445 dev_err(&pdev->dev, "can't enable device\n");
3449 /* XXX 32-bit addressing only */
3450 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3452 dev_err(&pdev->dev, "32-bit DMA not available\n");
3457 * Cache line size is used to size and align various
3458 * structures used to communicate with the hardware.
3460 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
3463 * Linux 2.4.18 (at least) writes the cache line size
3464 * register as a 16-bit wide register which is wrong.
3465 * We must have this setup properly for rx buffer
3466 * DMA to work so force a reasonable value here if it
3469 csz = L1_CACHE_BYTES >> 2;
3470 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
3473 * The default setting of latency timer yields poor results,
3474 * set it to the value used by other systems. It may be worth
3475 * tweaking this setting more.
3477 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
3479 /* Enable bus mastering */
3480 pci_set_master(pdev);
3483 * Disable the RETRY_TIMEOUT register (0x41) to keep
3484 * PCI Tx retries from interfering with C3 CPU state.
3486 pci_write_config_byte(pdev, 0x41, 0);
3488 ret = pci_request_region(pdev, 0, "ath5k");
3490 dev_err(&pdev->dev, "cannot reserve PCI memory region\n");
3494 mem = pci_iomap(pdev, 0, 0);
3496 dev_err(&pdev->dev, "cannot remap PCI memory region\n") ;
3502 * Allocate hw (mac80211 main struct)
3503 * and hw->priv (driver private data)
3505 hw = ieee80211_alloc_hw(sizeof(*sc), &ath5k_hw_ops);
3507 dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n");
3512 dev_info(&pdev->dev, "registered as '%s'\n", wiphy_name(hw->wiphy));
3514 /* Initialize driver private data */
3515 SET_IEEE80211_DEV(hw, &pdev->dev);
3516 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
3517 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
3518 IEEE80211_HW_SIGNAL_DBM;
3520 hw->wiphy->interface_modes =
3521 BIT(NL80211_IFTYPE_AP) |
3522 BIT(NL80211_IFTYPE_STATION) |
3523 BIT(NL80211_IFTYPE_ADHOC) |
3524 BIT(NL80211_IFTYPE_MESH_POINT);
3526 hw->extra_tx_headroom = 2;
3527 hw->channel_change_time = 5000;
3532 ath5k_debug_init_device(sc);
3535 * Mark the device as detached to avoid processing
3536 * interrupts until setup is complete.
3538 __set_bit(ATH_STAT_INVALID, sc->status);
3540 sc->iobase = mem; /* So we can unmap it on detach */
3541 sc->opmode = NL80211_IFTYPE_STATION;
3543 mutex_init(&sc->lock);
3544 spin_lock_init(&sc->rxbuflock);
3545 spin_lock_init(&sc->txbuflock);
3546 spin_lock_init(&sc->block);
3548 /* Set private data */
3549 pci_set_drvdata(pdev, sc);
3551 /* Setup interrupt handler */
3552 ret = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
3554 ATH5K_ERR(sc, "request_irq failed\n");
3558 /* If we passed the test, malloc an ath5k_hw struct */
3559 sc->ah = kzalloc(sizeof(struct ath5k_hw), GFP_KERNEL);
3562 ATH5K_ERR(sc, "out of memory\n");
3567 sc->ah->ah_iobase = sc->iobase;
3568 common = ath5k_hw_common(sc->ah);
3569 common->ops = &ath5k_common_ops;
3570 common->ah = sc->ah;
3572 common->cachelsz = csz << 2; /* convert to bytes */
3574 /* Initialize device */
3575 ret = ath5k_hw_attach(sc);
3580 /* set up multi-rate retry capabilities */
3581 if (sc->ah->ah_version == AR5K_AR5212) {
3583 hw->max_rate_tries = 11;
3586 hw->vif_data_size = sizeof(struct ath5k_vif);
3588 /* Finish private driver data initialization */
3589 ret = ath5k_attach(pdev, hw);
3593 ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
3594 ath5k_chip_name(AR5K_VERSION_MAC, sc->ah->ah_mac_srev),
3595 sc->ah->ah_mac_srev,
3596 sc->ah->ah_phy_revision);
3598 if (!sc->ah->ah_single_chip) {
3599 /* Single chip radio (!RF5111) */
3600 if (sc->ah->ah_radio_5ghz_revision &&
3601 !sc->ah->ah_radio_2ghz_revision) {
3602 /* No 5GHz support -> report 2GHz radio */
3603 if (!test_bit(AR5K_MODE_11A,
3604 sc->ah->ah_capabilities.cap_mode)) {
3605 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
3606 ath5k_chip_name(AR5K_VERSION_RAD,
3607 sc->ah->ah_radio_5ghz_revision),
3608 sc->ah->ah_radio_5ghz_revision);
3609 /* No 2GHz support (5110 and some
3610 * 5Ghz only cards) -> report 5Ghz radio */
3611 } else if (!test_bit(AR5K_MODE_11B,
3612 sc->ah->ah_capabilities.cap_mode)) {
3613 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
3614 ath5k_chip_name(AR5K_VERSION_RAD,
3615 sc->ah->ah_radio_5ghz_revision),
3616 sc->ah->ah_radio_5ghz_revision);
3617 /* Multiband radio */
3619 ATH5K_INFO(sc, "RF%s multiband radio found"
3621 ath5k_chip_name(AR5K_VERSION_RAD,
3622 sc->ah->ah_radio_5ghz_revision),
3623 sc->ah->ah_radio_5ghz_revision);
3626 /* Multi chip radio (RF5111 - RF2111) ->
3627 * report both 2GHz/5GHz radios */
3628 else if (sc->ah->ah_radio_5ghz_revision &&
3629 sc->ah->ah_radio_2ghz_revision){
3630 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
3631 ath5k_chip_name(AR5K_VERSION_RAD,
3632 sc->ah->ah_radio_5ghz_revision),
3633 sc->ah->ah_radio_5ghz_revision);
3634 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
3635 ath5k_chip_name(AR5K_VERSION_RAD,
3636 sc->ah->ah_radio_2ghz_revision),
3637 sc->ah->ah_radio_2ghz_revision);
3642 /* ready to process interrupts */
3643 __clear_bit(ATH_STAT_INVALID, sc->status);
3647 ath5k_hw_detach(sc->ah);
3651 free_irq(pdev->irq, sc);
3653 ieee80211_free_hw(hw);
3655 pci_iounmap(pdev, mem);
3657 pci_release_region(pdev, 0);
3659 pci_disable_device(pdev);
3664 static void __devexit
3665 ath5k_pci_remove(struct pci_dev *pdev)
3667 struct ath5k_softc *sc = pci_get_drvdata(pdev);
3669 ath5k_debug_finish_device(sc);
3670 ath5k_detach(pdev, sc->hw);
3671 ath5k_hw_detach(sc->ah);
3673 free_irq(pdev->irq, sc);
3674 pci_iounmap(pdev, sc->iobase);
3675 pci_release_region(pdev, 0);
3676 pci_disable_device(pdev);
3677 ieee80211_free_hw(sc->hw);
3680 #ifdef CONFIG_PM_SLEEP
3681 static int ath5k_pci_suspend(struct device *dev)
3683 struct ath5k_softc *sc = pci_get_drvdata(to_pci_dev(dev));
3689 static int ath5k_pci_resume(struct device *dev)
3691 struct pci_dev *pdev = to_pci_dev(dev);
3692 struct ath5k_softc *sc = pci_get_drvdata(pdev);
3695 * Suspend/Resume resets the PCI configuration space, so we have to
3696 * re-disable the RETRY_TIMEOUT register (0x41) to keep
3697 * PCI Tx retries from interfering with C3 CPU state
3699 pci_write_config_byte(pdev, 0x41, 0);
3701 ath5k_led_enable(sc);
3705 static SIMPLE_DEV_PM_OPS(ath5k_pm_ops, ath5k_pci_suspend, ath5k_pci_resume);
3706 #define ATH5K_PM_OPS (&ath5k_pm_ops)
3708 #define ATH5K_PM_OPS NULL
3709 #endif /* CONFIG_PM_SLEEP */
3711 static struct pci_driver ath5k_pci_driver = {
3712 .name = KBUILD_MODNAME,
3713 .id_table = ath5k_pci_id_table,
3714 .probe = ath5k_pci_probe,
3715 .remove = __devexit_p(ath5k_pci_remove),
3716 .driver.pm = ATH5K_PM_OPS,
3720 * Module init/exit functions
3723 init_ath5k_pci(void)
3729 ret = pci_register_driver(&ath5k_pci_driver);
3731 printk(KERN_ERR "ath5k_pci: can't register pci driver\n");
3739 exit_ath5k_pci(void)
3741 pci_unregister_driver(&ath5k_pci_driver);
3743 ath5k_debug_finish();
3746 module_init(init_ath5k_pci);
3747 module_exit(exit_ath5k_pci);