2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
4 * Copyright (c) 2006 Devicescape Software, Inc.
5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39 * THE POSSIBILITY OF SUCH DAMAGES.
43 #include <linux/module.h>
44 #include <linux/delay.h>
45 #include <linux/hardirq.h>
48 #include <linux/netdevice.h>
49 #include <linux/cache.h>
50 #include <linux/ethtool.h>
51 #include <linux/uaccess.h>
52 #include <linux/slab.h>
53 #include <linux/etherdevice.h>
55 #include <net/ieee80211_radiotap.h>
57 #include <asm/unaligned.h>
64 static int modparam_nohwcrypt;
65 module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
66 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
68 static int modparam_all_channels;
69 module_param_named(all_channels, modparam_all_channels, bool, S_IRUGO);
70 MODULE_PARM_DESC(all_channels, "Expose all channels the device can use.");
73 MODULE_AUTHOR("Jiri Slaby");
74 MODULE_AUTHOR("Nick Kossifidis");
75 MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
76 MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
77 MODULE_LICENSE("Dual BSD/GPL");
79 static int ath5k_init(struct ieee80211_hw *hw);
80 static int ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan,
82 static int ath5k_beacon_update(struct ieee80211_hw *hw,
83 struct ieee80211_vif *vif);
84 static void ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf);
87 static const struct ath5k_srev_name srev_names[] = {
88 #ifdef CONFIG_ATHEROS_AR231X
89 { "5312", AR5K_VERSION_MAC, AR5K_SREV_AR5312_R2 },
90 { "5312", AR5K_VERSION_MAC, AR5K_SREV_AR5312_R7 },
91 { "2313", AR5K_VERSION_MAC, AR5K_SREV_AR2313_R8 },
92 { "2315", AR5K_VERSION_MAC, AR5K_SREV_AR2315_R6 },
93 { "2315", AR5K_VERSION_MAC, AR5K_SREV_AR2315_R7 },
94 { "2317", AR5K_VERSION_MAC, AR5K_SREV_AR2317_R1 },
95 { "2317", AR5K_VERSION_MAC, AR5K_SREV_AR2317_R2 },
97 { "5210", AR5K_VERSION_MAC, AR5K_SREV_AR5210 },
98 { "5311", AR5K_VERSION_MAC, AR5K_SREV_AR5311 },
99 { "5311A", AR5K_VERSION_MAC, AR5K_SREV_AR5311A },
100 { "5311B", AR5K_VERSION_MAC, AR5K_SREV_AR5311B },
101 { "5211", AR5K_VERSION_MAC, AR5K_SREV_AR5211 },
102 { "5212", AR5K_VERSION_MAC, AR5K_SREV_AR5212 },
103 { "5213", AR5K_VERSION_MAC, AR5K_SREV_AR5213 },
104 { "5213A", AR5K_VERSION_MAC, AR5K_SREV_AR5213A },
105 { "2413", AR5K_VERSION_MAC, AR5K_SREV_AR2413 },
106 { "2414", AR5K_VERSION_MAC, AR5K_SREV_AR2414 },
107 { "5424", AR5K_VERSION_MAC, AR5K_SREV_AR5424 },
108 { "5413", AR5K_VERSION_MAC, AR5K_SREV_AR5413 },
109 { "5414", AR5K_VERSION_MAC, AR5K_SREV_AR5414 },
110 { "2415", AR5K_VERSION_MAC, AR5K_SREV_AR2415 },
111 { "5416", AR5K_VERSION_MAC, AR5K_SREV_AR5416 },
112 { "5418", AR5K_VERSION_MAC, AR5K_SREV_AR5418 },
113 { "2425", AR5K_VERSION_MAC, AR5K_SREV_AR2425 },
114 { "2417", AR5K_VERSION_MAC, AR5K_SREV_AR2417 },
116 { "xxxxx", AR5K_VERSION_MAC, AR5K_SREV_UNKNOWN },
117 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 },
118 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 },
119 { "5111A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111A },
120 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 },
121 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 },
122 { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A },
123 { "5112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112B },
124 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 },
125 { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A },
126 { "2112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112B },
127 { "2413", AR5K_VERSION_RAD, AR5K_SREV_RAD_2413 },
128 { "5413", AR5K_VERSION_RAD, AR5K_SREV_RAD_5413 },
129 { "5424", AR5K_VERSION_RAD, AR5K_SREV_RAD_5424 },
130 { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 },
131 #ifdef CONFIG_ATHEROS_AR231X
132 { "2316", AR5K_VERSION_RAD, AR5K_SREV_RAD_2316 },
133 { "2317", AR5K_VERSION_RAD, AR5K_SREV_RAD_2317 },
135 { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN },
138 static const struct ieee80211_rate ath5k_rates[] = {
140 .hw_value = ATH5K_RATE_CODE_1M, },
142 .hw_value = ATH5K_RATE_CODE_2M,
143 .hw_value_short = ATH5K_RATE_CODE_2M | AR5K_SET_SHORT_PREAMBLE,
144 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
146 .hw_value = ATH5K_RATE_CODE_5_5M,
147 .hw_value_short = ATH5K_RATE_CODE_5_5M | AR5K_SET_SHORT_PREAMBLE,
148 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
150 .hw_value = ATH5K_RATE_CODE_11M,
151 .hw_value_short = ATH5K_RATE_CODE_11M | AR5K_SET_SHORT_PREAMBLE,
152 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
154 .hw_value = ATH5K_RATE_CODE_6M,
157 .hw_value = ATH5K_RATE_CODE_9M,
160 .hw_value = ATH5K_RATE_CODE_12M,
163 .hw_value = ATH5K_RATE_CODE_18M,
166 .hw_value = ATH5K_RATE_CODE_24M,
169 .hw_value = ATH5K_RATE_CODE_36M,
172 .hw_value = ATH5K_RATE_CODE_48M,
175 .hw_value = ATH5K_RATE_CODE_54M,
180 static inline void ath5k_txbuf_free_skb(struct ath5k_softc *sc,
181 struct ath5k_buf *bf)
186 dma_unmap_single(sc->dev, bf->skbaddr, bf->skb->len,
188 dev_kfree_skb_any(bf->skb);
191 bf->desc->ds_data = 0;
194 static inline void ath5k_rxbuf_free_skb(struct ath5k_softc *sc,
195 struct ath5k_buf *bf)
197 struct ath5k_hw *ah = sc->ah;
198 struct ath_common *common = ath5k_hw_common(ah);
203 dma_unmap_single(sc->dev, bf->skbaddr, common->rx_bufsize,
205 dev_kfree_skb_any(bf->skb);
208 bf->desc->ds_data = 0;
212 static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
214 u64 tsf = ath5k_hw_get_tsf64(ah);
216 if ((tsf & 0x7fff) < rstamp)
219 return (tsf & ~0x7fff) | rstamp;
223 ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val)
225 const char *name = "xxxxx";
228 for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
229 if (srev_names[i].sr_type != type)
232 if ((val & 0xf0) == srev_names[i].sr_val)
233 name = srev_names[i].sr_name;
235 if ((val & 0xff) == srev_names[i].sr_val) {
236 name = srev_names[i].sr_name;
243 static unsigned int ath5k_ioread32(void *hw_priv, u32 reg_offset)
245 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv;
246 return ath5k_hw_reg_read(ah, reg_offset);
249 static void ath5k_iowrite32(void *hw_priv, u32 val, u32 reg_offset)
251 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv;
252 ath5k_hw_reg_write(ah, val, reg_offset);
255 static const struct ath_ops ath5k_common_ops = {
256 .read = ath5k_ioread32,
257 .write = ath5k_iowrite32,
260 /***********************\
261 * Driver Initialization *
262 \***********************/
264 static int ath5k_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request)
266 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
267 struct ath5k_softc *sc = hw->priv;
268 struct ath_regulatory *regulatory = ath5k_hw_regulatory(sc->ah);
270 return ath_reg_notifier_apply(wiphy, request, regulatory);
273 /********************\
274 * Channel/mode setup *
275 \********************/
278 * Convert IEEE channel number to MHz frequency.
281 ath5k_ieee2mhz(short chan)
283 if (chan <= 14 || chan >= 27)
284 return ieee80211chan2mhz(chan);
286 return 2212 + chan * 20;
290 * Returns true for the channel numbers used without all_channels modparam.
292 static bool ath5k_is_standard_channel(short chan)
294 return ((chan <= 14) ||
296 ((chan & 3) == 0 && chan >= 36 && chan <= 64) ||
298 ((chan & 3) == 0 && chan >= 100 && chan <= 140) ||
300 ((chan & 3) == 1 && chan >= 149 && chan <= 165));
304 ath5k_copy_channels(struct ath5k_hw *ah,
305 struct ieee80211_channel *channels,
309 unsigned int i, count, size, chfreq, freq, ch;
311 if (!test_bit(mode, ah->ah_modes))
316 /* 1..220, but 2GHz frequencies are filtered by check_channel */
318 chfreq = CHANNEL_5GHZ;
323 chfreq = CHANNEL_2GHZ;
326 ATH5K_WARN(ah->ah_sc, "bad mode, not copying channels\n");
330 for (i = 0, count = 0; i < size && max > 0; i++) {
332 freq = ath5k_ieee2mhz(ch);
334 /* Check if channel is supported by the chipset */
335 if (!ath5k_channel_ok(ah, freq, chfreq))
338 if (!modparam_all_channels && !ath5k_is_standard_channel(ch))
341 /* Write channel info and increment counter */
342 channels[count].center_freq = freq;
343 channels[count].band = (chfreq == CHANNEL_2GHZ) ?
344 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
348 channels[count].hw_value = chfreq | CHANNEL_OFDM;
351 channels[count].hw_value = CHANNEL_B;
362 ath5k_setup_rate_idx(struct ath5k_softc *sc, struct ieee80211_supported_band *b)
366 for (i = 0; i < AR5K_MAX_RATES; i++)
367 sc->rate_idx[b->band][i] = -1;
369 for (i = 0; i < b->n_bitrates; i++) {
370 sc->rate_idx[b->band][b->bitrates[i].hw_value] = i;
371 if (b->bitrates[i].hw_value_short)
372 sc->rate_idx[b->band][b->bitrates[i].hw_value_short] = i;
377 ath5k_setup_bands(struct ieee80211_hw *hw)
379 struct ath5k_softc *sc = hw->priv;
380 struct ath5k_hw *ah = sc->ah;
381 struct ieee80211_supported_band *sband;
382 int max_c, count_c = 0;
385 BUILD_BUG_ON(ARRAY_SIZE(sc->sbands) < IEEE80211_NUM_BANDS);
386 max_c = ARRAY_SIZE(sc->channels);
389 sband = &sc->sbands[IEEE80211_BAND_2GHZ];
390 sband->band = IEEE80211_BAND_2GHZ;
391 sband->bitrates = &sc->rates[IEEE80211_BAND_2GHZ][0];
393 if (test_bit(AR5K_MODE_11G, sc->ah->ah_capabilities.cap_mode)) {
395 memcpy(sband->bitrates, &ath5k_rates[0],
396 sizeof(struct ieee80211_rate) * 12);
397 sband->n_bitrates = 12;
399 sband->channels = sc->channels;
400 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
401 AR5K_MODE_11G, max_c);
403 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
404 count_c = sband->n_channels;
406 } else if (test_bit(AR5K_MODE_11B, sc->ah->ah_capabilities.cap_mode)) {
408 memcpy(sband->bitrates, &ath5k_rates[0],
409 sizeof(struct ieee80211_rate) * 4);
410 sband->n_bitrates = 4;
412 /* 5211 only supports B rates and uses 4bit rate codes
413 * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B)
416 if (ah->ah_version == AR5K_AR5211) {
417 for (i = 0; i < 4; i++) {
418 sband->bitrates[i].hw_value =
419 sband->bitrates[i].hw_value & 0xF;
420 sband->bitrates[i].hw_value_short =
421 sband->bitrates[i].hw_value_short & 0xF;
425 sband->channels = sc->channels;
426 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
427 AR5K_MODE_11B, max_c);
429 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
430 count_c = sband->n_channels;
433 ath5k_setup_rate_idx(sc, sband);
435 /* 5GHz band, A mode */
436 if (test_bit(AR5K_MODE_11A, sc->ah->ah_capabilities.cap_mode)) {
437 sband = &sc->sbands[IEEE80211_BAND_5GHZ];
438 sband->band = IEEE80211_BAND_5GHZ;
439 sband->bitrates = &sc->rates[IEEE80211_BAND_5GHZ][0];
441 memcpy(sband->bitrates, &ath5k_rates[4],
442 sizeof(struct ieee80211_rate) * 8);
443 sband->n_bitrates = 8;
445 sband->channels = &sc->channels[count_c];
446 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
447 AR5K_MODE_11A, max_c);
449 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband;
451 ath5k_setup_rate_idx(sc, sband);
453 ath5k_debug_dump_bands(sc);
459 * Set/change channels. We always reset the chip.
460 * To accomplish this we must first cleanup any pending DMA,
461 * then restart stuff after a la ath5k_init.
463 * Called with sc->lock.
466 ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan)
468 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
469 "channel set, resetting (%u -> %u MHz)\n",
470 sc->curchan->center_freq, chan->center_freq);
473 * To switch channels clear any pending DMA operations;
474 * wait long enough for the RX fifo to drain, reset the
475 * hardware at the new frequency, and then re-enable
476 * the relevant bits of the h/w.
478 return ath5k_reset(sc, chan, true);
482 ath5k_setcurmode(struct ath5k_softc *sc, unsigned int mode)
486 if (mode == AR5K_MODE_11A) {
487 sc->curband = &sc->sbands[IEEE80211_BAND_5GHZ];
489 sc->curband = &sc->sbands[IEEE80211_BAND_2GHZ];
493 struct ath_vif_iter_data {
494 const u8 *hw_macaddr;
496 u8 active_mac[ETH_ALEN]; /* first active MAC */
497 bool need_set_hw_addr;
500 enum nl80211_iftype opmode;
503 static void ath_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
505 struct ath_vif_iter_data *iter_data = data;
507 struct ath5k_vif *avf = (void *)vif->drv_priv;
509 if (iter_data->hw_macaddr)
510 for (i = 0; i < ETH_ALEN; i++)
511 iter_data->mask[i] &=
512 ~(iter_data->hw_macaddr[i] ^ mac[i]);
514 if (!iter_data->found_active) {
515 iter_data->found_active = true;
516 memcpy(iter_data->active_mac, mac, ETH_ALEN);
519 if (iter_data->need_set_hw_addr && iter_data->hw_macaddr)
520 if (compare_ether_addr(iter_data->hw_macaddr, mac) == 0)
521 iter_data->need_set_hw_addr = false;
523 if (!iter_data->any_assoc) {
525 iter_data->any_assoc = true;
528 /* Calculate combined mode - when APs are active, operate in AP mode.
529 * Otherwise use the mode of the new interface. This can currently
530 * only deal with combinations of APs and STAs. Only one ad-hoc
531 * interfaces is allowed.
533 if (avf->opmode == NL80211_IFTYPE_AP)
534 iter_data->opmode = NL80211_IFTYPE_AP;
536 if (iter_data->opmode == NL80211_IFTYPE_UNSPECIFIED)
537 iter_data->opmode = avf->opmode;
540 static void ath5k_update_bssid_mask_and_opmode(struct ath5k_softc *sc,
541 struct ieee80211_vif *vif)
543 struct ath_common *common = ath5k_hw_common(sc->ah);
544 struct ath_vif_iter_data iter_data;
547 * Use the hardware MAC address as reference, the hardware uses it
548 * together with the BSSID mask when matching addresses.
550 iter_data.hw_macaddr = common->macaddr;
551 memset(&iter_data.mask, 0xff, ETH_ALEN);
552 iter_data.found_active = false;
553 iter_data.need_set_hw_addr = true;
554 iter_data.opmode = NL80211_IFTYPE_UNSPECIFIED;
557 ath_vif_iter(&iter_data, vif->addr, vif);
559 /* Get list of all active MAC addresses */
560 ieee80211_iterate_active_interfaces_atomic(sc->hw, ath_vif_iter,
562 memcpy(sc->bssidmask, iter_data.mask, ETH_ALEN);
564 sc->opmode = iter_data.opmode;
565 if (sc->opmode == NL80211_IFTYPE_UNSPECIFIED)
566 /* Nothing active, default to station mode */
567 sc->opmode = NL80211_IFTYPE_STATION;
569 ath5k_hw_set_opmode(sc->ah, sc->opmode);
570 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "mode setup opmode %d (%s)\n",
571 sc->opmode, ath_opmode_to_string(sc->opmode));
573 if (iter_data.need_set_hw_addr && iter_data.found_active)
574 ath5k_hw_set_lladdr(sc->ah, iter_data.active_mac);
576 if (ath5k_hw_hasbssidmask(sc->ah))
577 ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask);
581 ath5k_mode_setup(struct ath5k_softc *sc, struct ieee80211_vif *vif)
583 struct ath5k_hw *ah = sc->ah;
586 /* configure rx filter */
587 rfilt = sc->filter_flags;
588 ath5k_hw_set_rx_filter(ah, rfilt);
589 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
591 ath5k_update_bssid_mask_and_opmode(sc, vif);
595 ath5k_hw_to_driver_rix(struct ath5k_softc *sc, int hw_rix)
599 /* return base rate on errors */
600 if (WARN(hw_rix < 0 || hw_rix >= AR5K_MAX_RATES,
601 "hw_rix out of bounds: %x\n", hw_rix))
604 rix = sc->rate_idx[sc->curband->band][hw_rix];
605 if (WARN(rix < 0, "invalid hw_rix: %x\n", hw_rix))
616 struct sk_buff *ath5k_rx_skb_alloc(struct ath5k_softc *sc, dma_addr_t *skb_addr)
618 struct ath_common *common = ath5k_hw_common(sc->ah);
622 * Allocate buffer with headroom_needed space for the
623 * fake physical layer header at the start.
625 skb = ath_rxbuf_alloc(common,
630 ATH5K_ERR(sc, "can't alloc skbuff of size %u\n",
635 *skb_addr = dma_map_single(sc->dev,
636 skb->data, common->rx_bufsize,
639 if (unlikely(dma_mapping_error(sc->dev, *skb_addr))) {
640 ATH5K_ERR(sc, "%s: DMA mapping failed\n", __func__);
648 ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
650 struct ath5k_hw *ah = sc->ah;
651 struct sk_buff *skb = bf->skb;
652 struct ath5k_desc *ds;
656 skb = ath5k_rx_skb_alloc(sc, &bf->skbaddr);
663 * Setup descriptors. For receive we always terminate
664 * the descriptor list with a self-linked entry so we'll
665 * not get overrun under high load (as can happen with a
666 * 5212 when ANI processing enables PHY error frames).
668 * To ensure the last descriptor is self-linked we create
669 * each descriptor as self-linked and add it to the end. As
670 * each additional descriptor is added the previous self-linked
671 * entry is "fixed" naturally. This should be safe even
672 * if DMA is happening. When processing RX interrupts we
673 * never remove/process the last, self-linked, entry on the
674 * descriptor list. This ensures the hardware always has
675 * someplace to write a new frame.
678 ds->ds_link = bf->daddr; /* link to self */
679 ds->ds_data = bf->skbaddr;
680 ret = ath5k_hw_setup_rx_desc(ah, ds, ah->common.rx_bufsize, 0);
682 ATH5K_ERR(sc, "%s: could not setup RX desc\n", __func__);
686 if (sc->rxlink != NULL)
687 *sc->rxlink = bf->daddr;
688 sc->rxlink = &ds->ds_link;
692 static enum ath5k_pkt_type get_hw_packet_type(struct sk_buff *skb)
694 struct ieee80211_hdr *hdr;
695 enum ath5k_pkt_type htype;
698 hdr = (struct ieee80211_hdr *)skb->data;
699 fc = hdr->frame_control;
701 if (ieee80211_is_beacon(fc))
702 htype = AR5K_PKT_TYPE_BEACON;
703 else if (ieee80211_is_probe_resp(fc))
704 htype = AR5K_PKT_TYPE_PROBE_RESP;
705 else if (ieee80211_is_atim(fc))
706 htype = AR5K_PKT_TYPE_ATIM;
707 else if (ieee80211_is_pspoll(fc))
708 htype = AR5K_PKT_TYPE_PSPOLL;
710 htype = AR5K_PKT_TYPE_NORMAL;
716 ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf,
717 struct ath5k_txq *txq, int padsize)
719 struct ath5k_hw *ah = sc->ah;
720 struct ath5k_desc *ds = bf->desc;
721 struct sk_buff *skb = bf->skb;
722 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
723 unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID;
724 struct ieee80211_rate *rate;
725 unsigned int mrr_rate[3], mrr_tries[3];
732 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
735 bf->skbaddr = dma_map_single(sc->dev, skb->data, skb->len,
738 rate = ieee80211_get_tx_rate(sc->hw, info);
744 if (info->flags & IEEE80211_TX_CTL_NO_ACK)
745 flags |= AR5K_TXDESC_NOACK;
747 rc_flags = info->control.rates[0].flags;
748 hw_rate = (rc_flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) ?
749 rate->hw_value_short : rate->hw_value;
753 /* FIXME: If we are in g mode and rate is a CCK rate
754 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
755 * from tx power (value is in dB units already) */
756 if (info->control.hw_key) {
757 keyidx = info->control.hw_key->hw_key_idx;
758 pktlen += info->control.hw_key->icv_len;
760 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
761 flags |= AR5K_TXDESC_RTSENA;
762 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
763 duration = le16_to_cpu(ieee80211_rts_duration(sc->hw,
764 info->control.vif, pktlen, info));
766 if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
767 flags |= AR5K_TXDESC_CTSENA;
768 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
769 duration = le16_to_cpu(ieee80211_ctstoself_duration(sc->hw,
770 info->control.vif, pktlen, info));
772 ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
773 ieee80211_get_hdrlen_from_skb(skb), padsize,
774 get_hw_packet_type(skb),
775 (sc->power_level * 2),
777 info->control.rates[0].count, keyidx, ah->ah_tx_ant, flags,
782 memset(mrr_rate, 0, sizeof(mrr_rate));
783 memset(mrr_tries, 0, sizeof(mrr_tries));
784 for (i = 0; i < 3; i++) {
785 rate = ieee80211_get_alt_retry_rate(sc->hw, info, i);
789 mrr_rate[i] = rate->hw_value;
790 mrr_tries[i] = info->control.rates[i + 1].count;
793 ath5k_hw_setup_mrr_tx_desc(ah, ds,
794 mrr_rate[0], mrr_tries[0],
795 mrr_rate[1], mrr_tries[1],
796 mrr_rate[2], mrr_tries[2]);
799 ds->ds_data = bf->skbaddr;
801 spin_lock_bh(&txq->lock);
802 list_add_tail(&bf->list, &txq->q);
804 if (txq->link == NULL) /* is this first packet? */
805 ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr);
806 else /* no, so only link it */
807 *txq->link = bf->daddr;
809 txq->link = &ds->ds_link;
810 ath5k_hw_start_tx_dma(ah, txq->qnum);
812 spin_unlock_bh(&txq->lock);
816 dma_unmap_single(sc->dev, bf->skbaddr, skb->len, DMA_TO_DEVICE);
820 /*******************\
821 * Descriptors setup *
822 \*******************/
825 ath5k_desc_alloc(struct ath5k_softc *sc)
827 struct ath5k_desc *ds;
828 struct ath5k_buf *bf;
833 /* allocate descriptors */
834 sc->desc_len = sizeof(struct ath5k_desc) *
835 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
837 sc->desc = dma_alloc_coherent(sc->dev, sc->desc_len,
838 &sc->desc_daddr, GFP_KERNEL);
839 if (sc->desc == NULL) {
840 ATH5K_ERR(sc, "can't allocate descriptors\n");
846 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
847 ds, sc->desc_len, (unsigned long long)sc->desc_daddr);
849 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
850 sizeof(struct ath5k_buf), GFP_KERNEL);
852 ATH5K_ERR(sc, "can't allocate bufptr\n");
858 INIT_LIST_HEAD(&sc->rxbuf);
859 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
862 list_add_tail(&bf->list, &sc->rxbuf);
865 INIT_LIST_HEAD(&sc->txbuf);
866 sc->txbuf_len = ATH_TXBUF;
867 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++,
871 list_add_tail(&bf->list, &sc->txbuf);
875 INIT_LIST_HEAD(&sc->bcbuf);
876 for (i = 0; i < ATH_BCBUF; i++, bf++, ds++, da += sizeof(*ds)) {
879 list_add_tail(&bf->list, &sc->bcbuf);
884 dma_free_coherent(sc->dev, sc->desc_len, sc->desc, sc->desc_daddr);
891 ath5k_desc_free(struct ath5k_softc *sc)
893 struct ath5k_buf *bf;
895 list_for_each_entry(bf, &sc->txbuf, list)
896 ath5k_txbuf_free_skb(sc, bf);
897 list_for_each_entry(bf, &sc->rxbuf, list)
898 ath5k_rxbuf_free_skb(sc, bf);
899 list_for_each_entry(bf, &sc->bcbuf, list)
900 ath5k_txbuf_free_skb(sc, bf);
902 /* Free memory associated with all descriptors */
903 dma_free_coherent(sc->dev, sc->desc_len, sc->desc, sc->desc_daddr);
916 static struct ath5k_txq *
917 ath5k_txq_setup(struct ath5k_softc *sc,
918 int qtype, int subtype)
920 struct ath5k_hw *ah = sc->ah;
921 struct ath5k_txq *txq;
922 struct ath5k_txq_info qi = {
923 .tqi_subtype = subtype,
924 /* XXX: default values not correct for B and XR channels,
926 .tqi_aifs = AR5K_TUNE_AIFS,
927 .tqi_cw_min = AR5K_TUNE_CWMIN,
928 .tqi_cw_max = AR5K_TUNE_CWMAX
933 * Enable interrupts only for EOL and DESC conditions.
934 * We mark tx descriptors to receive a DESC interrupt
935 * when a tx queue gets deep; otherwise we wait for the
936 * EOL to reap descriptors. Note that this is done to
937 * reduce interrupt load and this only defers reaping
938 * descriptors, never transmitting frames. Aside from
939 * reducing interrupts this also permits more concurrency.
940 * The only potential downside is if the tx queue backs
941 * up in which case the top half of the kernel may backup
942 * due to a lack of tx descriptors.
944 qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
945 AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
946 qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi);
949 * NB: don't print a message, this happens
950 * normally on parts with too few tx queues
952 return ERR_PTR(qnum);
954 if (qnum >= ARRAY_SIZE(sc->txqs)) {
955 ATH5K_ERR(sc, "hw qnum %u out of range, max %tu!\n",
956 qnum, ARRAY_SIZE(sc->txqs));
957 ath5k_hw_release_tx_queue(ah, qnum);
958 return ERR_PTR(-EINVAL);
960 txq = &sc->txqs[qnum];
964 INIT_LIST_HEAD(&txq->q);
965 spin_lock_init(&txq->lock);
968 txq->txq_poll_mark = false;
971 return &sc->txqs[qnum];
975 ath5k_beaconq_setup(struct ath5k_hw *ah)
977 struct ath5k_txq_info qi = {
978 /* XXX: default values not correct for B and XR channels,
980 .tqi_aifs = AR5K_TUNE_AIFS,
981 .tqi_cw_min = AR5K_TUNE_CWMIN,
982 .tqi_cw_max = AR5K_TUNE_CWMAX,
983 /* NB: for dynamic turbo, don't enable any other interrupts */
984 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE
987 return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi);
991 ath5k_beaconq_config(struct ath5k_softc *sc)
993 struct ath5k_hw *ah = sc->ah;
994 struct ath5k_txq_info qi;
997 ret = ath5k_hw_get_tx_queueprops(ah, sc->bhalq, &qi);
1001 if (sc->opmode == NL80211_IFTYPE_AP ||
1002 sc->opmode == NL80211_IFTYPE_MESH_POINT) {
1004 * Always burst out beacon and CAB traffic
1005 * (aifs = cwmin = cwmax = 0)
1010 } else if (sc->opmode == NL80211_IFTYPE_ADHOC) {
1012 * Adhoc mode; backoff between 0 and (2 * cw_min).
1016 qi.tqi_cw_max = 2 * AR5K_TUNE_CWMIN;
1019 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1020 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
1021 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max);
1023 ret = ath5k_hw_set_tx_queueprops(ah, sc->bhalq, &qi);
1025 ATH5K_ERR(sc, "%s: unable to update parameters for beacon "
1026 "hardware queue!\n", __func__);
1029 ret = ath5k_hw_reset_tx_queue(ah, sc->bhalq); /* push to h/w */
1033 /* reconfigure cabq with ready time to 80% of beacon_interval */
1034 ret = ath5k_hw_get_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi);
1038 qi.tqi_ready_time = (sc->bintval * 80) / 100;
1039 ret = ath5k_hw_set_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi);
1043 ret = ath5k_hw_reset_tx_queue(ah, AR5K_TX_QUEUE_ID_CAB);
1049 * ath5k_drain_tx_buffs - Empty tx buffers
1051 * @sc The &struct ath5k_softc
1053 * Empty tx buffers from all queues in preparation
1054 * of a reset or during shutdown.
1056 * NB: this assumes output has been stopped and
1057 * we do not need to block ath5k_tx_tasklet
1060 ath5k_drain_tx_buffs(struct ath5k_softc *sc)
1062 struct ath5k_txq *txq;
1063 struct ath5k_buf *bf, *bf0;
1066 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++) {
1067 if (sc->txqs[i].setup) {
1069 spin_lock_bh(&txq->lock);
1070 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1071 ath5k_debug_printtxbuf(sc, bf);
1073 ath5k_txbuf_free_skb(sc, bf);
1075 spin_lock_bh(&sc->txbuflock);
1076 list_move_tail(&bf->list, &sc->txbuf);
1079 spin_unlock_bh(&sc->txbuflock);
1082 txq->txq_poll_mark = false;
1083 spin_unlock_bh(&txq->lock);
1089 ath5k_txq_release(struct ath5k_softc *sc)
1091 struct ath5k_txq *txq = sc->txqs;
1094 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++)
1096 ath5k_hw_release_tx_queue(sc->ah, txq->qnum);
1107 * Enable the receive h/w following a reset.
1110 ath5k_rx_start(struct ath5k_softc *sc)
1112 struct ath5k_hw *ah = sc->ah;
1113 struct ath_common *common = ath5k_hw_common(ah);
1114 struct ath5k_buf *bf;
1117 common->rx_bufsize = roundup(IEEE80211_MAX_FRAME_LEN, common->cachelsz);
1119 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "cachelsz %u rx_bufsize %u\n",
1120 common->cachelsz, common->rx_bufsize);
1122 spin_lock_bh(&sc->rxbuflock);
1124 list_for_each_entry(bf, &sc->rxbuf, list) {
1125 ret = ath5k_rxbuf_setup(sc, bf);
1127 spin_unlock_bh(&sc->rxbuflock);
1131 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1132 ath5k_hw_set_rxdp(ah, bf->daddr);
1133 spin_unlock_bh(&sc->rxbuflock);
1135 ath5k_hw_start_rx_dma(ah); /* enable recv descriptors */
1136 ath5k_mode_setup(sc, NULL); /* set filters, etc. */
1137 ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */
1145 * Disable the receive logic on PCU (DRU)
1146 * In preparation for a shutdown.
1148 * Note: Doesn't stop rx DMA, ath5k_hw_dma_stop
1152 ath5k_rx_stop(struct ath5k_softc *sc)
1154 struct ath5k_hw *ah = sc->ah;
1156 ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */
1157 ath5k_hw_stop_rx_pcu(ah); /* disable PCU */
1159 ath5k_debug_printrxbuffs(sc, ah);
1163 ath5k_rx_decrypted(struct ath5k_softc *sc, struct sk_buff *skb,
1164 struct ath5k_rx_status *rs)
1166 struct ath5k_hw *ah = sc->ah;
1167 struct ath_common *common = ath5k_hw_common(ah);
1168 struct ieee80211_hdr *hdr = (void *)skb->data;
1169 unsigned int keyix, hlen;
1171 if (!(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1172 rs->rs_keyix != AR5K_RXKEYIX_INVALID)
1173 return RX_FLAG_DECRYPTED;
1175 /* Apparently when a default key is used to decrypt the packet
1176 the hw does not set the index used to decrypt. In such cases
1177 get the index from the packet. */
1178 hlen = ieee80211_hdrlen(hdr->frame_control);
1179 if (ieee80211_has_protected(hdr->frame_control) &&
1180 !(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1181 skb->len >= hlen + 4) {
1182 keyix = skb->data[hlen + 3] >> 6;
1184 if (test_bit(keyix, common->keymap))
1185 return RX_FLAG_DECRYPTED;
1193 ath5k_check_ibss_tsf(struct ath5k_softc *sc, struct sk_buff *skb,
1194 struct ieee80211_rx_status *rxs)
1196 struct ath_common *common = ath5k_hw_common(sc->ah);
1199 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1201 if (ieee80211_is_beacon(mgmt->frame_control) &&
1202 le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS &&
1203 memcmp(mgmt->bssid, common->curbssid, ETH_ALEN) == 0) {
1205 * Received an IBSS beacon with the same BSSID. Hardware *must*
1206 * have updated the local TSF. We have to work around various
1207 * hardware bugs, though...
1209 tsf = ath5k_hw_get_tsf64(sc->ah);
1210 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp);
1211 hw_tu = TSF_TO_TU(tsf);
1213 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1214 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
1215 (unsigned long long)bc_tstamp,
1216 (unsigned long long)rxs->mactime,
1217 (unsigned long long)(rxs->mactime - bc_tstamp),
1218 (unsigned long long)tsf);
1221 * Sometimes the HW will give us a wrong tstamp in the rx
1222 * status, causing the timestamp extension to go wrong.
1223 * (This seems to happen especially with beacon frames bigger
1224 * than 78 byte (incl. FCS))
1225 * But we know that the receive timestamp must be later than the
1226 * timestamp of the beacon since HW must have synced to that.
1228 * NOTE: here we assume mactime to be after the frame was
1229 * received, not like mac80211 which defines it at the start.
1231 if (bc_tstamp > rxs->mactime) {
1232 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1233 "fixing mactime from %llx to %llx\n",
1234 (unsigned long long)rxs->mactime,
1235 (unsigned long long)tsf);
1240 * Local TSF might have moved higher than our beacon timers,
1241 * in that case we have to update them to continue sending
1242 * beacons. This also takes care of synchronizing beacon sending
1243 * times with other stations.
1245 if (hw_tu >= sc->nexttbtt)
1246 ath5k_beacon_update_timers(sc, bc_tstamp);
1248 /* Check if the beacon timers are still correct, because a TSF
1249 * update might have created a window between them - for a
1250 * longer description see the comment of this function: */
1251 if (!ath5k_hw_check_beacon_timers(sc->ah, sc->bintval)) {
1252 ath5k_beacon_update_timers(sc, bc_tstamp);
1253 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1254 "fixed beacon timers after beacon receive\n");
1260 ath5k_update_beacon_rssi(struct ath5k_softc *sc, struct sk_buff *skb, int rssi)
1262 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1263 struct ath5k_hw *ah = sc->ah;
1264 struct ath_common *common = ath5k_hw_common(ah);
1266 /* only beacons from our BSSID */
1267 if (!ieee80211_is_beacon(mgmt->frame_control) ||
1268 memcmp(mgmt->bssid, common->curbssid, ETH_ALEN) != 0)
1271 ewma_add(&ah->ah_beacon_rssi_avg, rssi);
1273 /* in IBSS mode we should keep RSSI statistics per neighbour */
1274 /* le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS */
1278 * Compute padding position. skb must contain an IEEE 802.11 frame
1280 static int ath5k_common_padpos(struct sk_buff *skb)
1282 struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data;
1283 __le16 frame_control = hdr->frame_control;
1286 if (ieee80211_has_a4(frame_control)) {
1289 if (ieee80211_is_data_qos(frame_control)) {
1290 padpos += IEEE80211_QOS_CTL_LEN;
1297 * This function expects an 802.11 frame and returns the number of
1298 * bytes added, or -1 if we don't have enough header room.
1300 static int ath5k_add_padding(struct sk_buff *skb)
1302 int padpos = ath5k_common_padpos(skb);
1303 int padsize = padpos & 3;
1305 if (padsize && skb->len>padpos) {
1307 if (skb_headroom(skb) < padsize)
1310 skb_push(skb, padsize);
1311 memmove(skb->data, skb->data+padsize, padpos);
1319 * The MAC header is padded to have 32-bit boundary if the
1320 * packet payload is non-zero. The general calculation for
1321 * padsize would take into account odd header lengths:
1322 * padsize = 4 - (hdrlen & 3); however, since only
1323 * even-length headers are used, padding can only be 0 or 2
1324 * bytes and we can optimize this a bit. We must not try to
1325 * remove padding from short control frames that do not have a
1328 * This function expects an 802.11 frame and returns the number of
1331 static int ath5k_remove_padding(struct sk_buff *skb)
1333 int padpos = ath5k_common_padpos(skb);
1334 int padsize = padpos & 3;
1336 if (padsize && skb->len>=padpos+padsize) {
1337 memmove(skb->data + padsize, skb->data, padpos);
1338 skb_pull(skb, padsize);
1346 ath5k_receive_frame(struct ath5k_softc *sc, struct sk_buff *skb,
1347 struct ath5k_rx_status *rs)
1349 struct ieee80211_rx_status *rxs;
1351 ath5k_remove_padding(skb);
1353 rxs = IEEE80211_SKB_RXCB(skb);
1356 if (unlikely(rs->rs_status & AR5K_RXERR_MIC))
1357 rxs->flag |= RX_FLAG_MMIC_ERROR;
1360 * always extend the mac timestamp, since this information is
1361 * also needed for proper IBSS merging.
1363 * XXX: it might be too late to do it here, since rs_tstamp is
1364 * 15bit only. that means TSF extension has to be done within
1365 * 32768usec (about 32ms). it might be necessary to move this to
1366 * the interrupt handler, like it is done in madwifi.
1368 * Unfortunately we don't know when the hardware takes the rx
1369 * timestamp (beginning of phy frame, data frame, end of rx?).
1370 * The only thing we know is that it is hardware specific...
1371 * On AR5213 it seems the rx timestamp is at the end of the
1372 * frame, but i'm not sure.
1374 * NOTE: mac80211 defines mactime at the beginning of the first
1375 * data symbol. Since we don't have any time references it's
1376 * impossible to comply to that. This affects IBSS merge only
1377 * right now, so it's not too bad...
1379 rxs->mactime = ath5k_extend_tsf(sc->ah, rs->rs_tstamp);
1380 rxs->flag |= RX_FLAG_TSFT;
1382 rxs->freq = sc->curchan->center_freq;
1383 rxs->band = sc->curband->band;
1385 rxs->signal = sc->ah->ah_noise_floor + rs->rs_rssi;
1387 rxs->antenna = rs->rs_antenna;
1389 if (rs->rs_antenna > 0 && rs->rs_antenna < 5)
1390 sc->stats.antenna_rx[rs->rs_antenna]++;
1392 sc->stats.antenna_rx[0]++; /* invalid */
1394 rxs->rate_idx = ath5k_hw_to_driver_rix(sc, rs->rs_rate);
1395 rxs->flag |= ath5k_rx_decrypted(sc, skb, rs);
1397 if (rxs->rate_idx >= 0 && rs->rs_rate ==
1398 sc->curband->bitrates[rxs->rate_idx].hw_value_short)
1399 rxs->flag |= RX_FLAG_SHORTPRE;
1401 ath5k_debug_dump_skb(sc, skb, "RX ", 0);
1403 ath5k_update_beacon_rssi(sc, skb, rs->rs_rssi);
1405 /* check beacons in IBSS mode */
1406 if (sc->opmode == NL80211_IFTYPE_ADHOC)
1407 ath5k_check_ibss_tsf(sc, skb, rxs);
1409 ieee80211_rx(sc->hw, skb);
1412 /** ath5k_frame_receive_ok() - Do we want to receive this frame or not?
1414 * Check if we want to further process this frame or not. Also update
1415 * statistics. Return true if we want this frame, false if not.
1418 ath5k_receive_frame_ok(struct ath5k_softc *sc, struct ath5k_rx_status *rs)
1420 sc->stats.rx_all_count++;
1421 sc->stats.rx_bytes_count += rs->rs_datalen;
1423 if (unlikely(rs->rs_status)) {
1424 if (rs->rs_status & AR5K_RXERR_CRC)
1425 sc->stats.rxerr_crc++;
1426 if (rs->rs_status & AR5K_RXERR_FIFO)
1427 sc->stats.rxerr_fifo++;
1428 if (rs->rs_status & AR5K_RXERR_PHY) {
1429 sc->stats.rxerr_phy++;
1430 if (rs->rs_phyerr > 0 && rs->rs_phyerr < 32)
1431 sc->stats.rxerr_phy_code[rs->rs_phyerr]++;
1434 if (rs->rs_status & AR5K_RXERR_DECRYPT) {
1436 * Decrypt error. If the error occurred
1437 * because there was no hardware key, then
1438 * let the frame through so the upper layers
1439 * can process it. This is necessary for 5210
1440 * parts which have no way to setup a ``clear''
1443 * XXX do key cache faulting
1445 sc->stats.rxerr_decrypt++;
1446 if (rs->rs_keyix == AR5K_RXKEYIX_INVALID &&
1447 !(rs->rs_status & AR5K_RXERR_CRC))
1450 if (rs->rs_status & AR5K_RXERR_MIC) {
1451 sc->stats.rxerr_mic++;
1455 /* reject any frames with non-crypto errors */
1456 if (rs->rs_status & ~(AR5K_RXERR_DECRYPT))
1460 if (unlikely(rs->rs_more)) {
1461 sc->stats.rxerr_jumbo++;
1468 ath5k_tasklet_rx(unsigned long data)
1470 struct ath5k_rx_status rs = {};
1471 struct sk_buff *skb, *next_skb;
1472 dma_addr_t next_skb_addr;
1473 struct ath5k_softc *sc = (void *)data;
1474 struct ath5k_hw *ah = sc->ah;
1475 struct ath_common *common = ath5k_hw_common(ah);
1476 struct ath5k_buf *bf;
1477 struct ath5k_desc *ds;
1480 spin_lock(&sc->rxbuflock);
1481 if (list_empty(&sc->rxbuf)) {
1482 ATH5K_WARN(sc, "empty rx buf pool\n");
1486 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1487 BUG_ON(bf->skb == NULL);
1491 /* bail if HW is still using self-linked descriptor */
1492 if (ath5k_hw_get_rxdp(sc->ah) == bf->daddr)
1495 ret = sc->ah->ah_proc_rx_desc(sc->ah, ds, &rs);
1496 if (unlikely(ret == -EINPROGRESS))
1498 else if (unlikely(ret)) {
1499 ATH5K_ERR(sc, "error in processing rx descriptor\n");
1500 sc->stats.rxerr_proc++;
1504 if (ath5k_receive_frame_ok(sc, &rs)) {
1505 next_skb = ath5k_rx_skb_alloc(sc, &next_skb_addr);
1508 * If we can't replace bf->skb with a new skb under
1509 * memory pressure, just skip this packet
1514 dma_unmap_single(sc->dev, bf->skbaddr,
1518 skb_put(skb, rs.rs_datalen);
1520 ath5k_receive_frame(sc, skb, &rs);
1523 bf->skbaddr = next_skb_addr;
1526 list_move_tail(&bf->list, &sc->rxbuf);
1527 } while (ath5k_rxbuf_setup(sc, bf) == 0);
1529 spin_unlock(&sc->rxbuflock);
1537 static int ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb,
1538 struct ath5k_txq *txq)
1540 struct ath5k_softc *sc = hw->priv;
1541 struct ath5k_buf *bf;
1542 unsigned long flags;
1545 ath5k_debug_dump_skb(sc, skb, "TX ", 1);
1548 * The hardware expects the header padded to 4 byte boundaries.
1549 * If this is not the case, we add the padding after the header.
1551 padsize = ath5k_add_padding(skb);
1553 ATH5K_ERR(sc, "tx hdrlen not %%4: not enough"
1554 " headroom to pad");
1558 if (txq->txq_len >= ATH5K_TXQ_LEN_MAX)
1559 ieee80211_stop_queue(hw, txq->qnum);
1561 spin_lock_irqsave(&sc->txbuflock, flags);
1562 if (list_empty(&sc->txbuf)) {
1563 ATH5K_ERR(sc, "no further txbuf available, dropping packet\n");
1564 spin_unlock_irqrestore(&sc->txbuflock, flags);
1565 ieee80211_stop_queues(hw);
1568 bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list);
1569 list_del(&bf->list);
1571 if (list_empty(&sc->txbuf))
1572 ieee80211_stop_queues(hw);
1573 spin_unlock_irqrestore(&sc->txbuflock, flags);
1577 if (ath5k_txbuf_setup(sc, bf, txq, padsize)) {
1579 spin_lock_irqsave(&sc->txbuflock, flags);
1580 list_add_tail(&bf->list, &sc->txbuf);
1582 spin_unlock_irqrestore(&sc->txbuflock, flags);
1585 return NETDEV_TX_OK;
1588 dev_kfree_skb_any(skb);
1589 return NETDEV_TX_OK;
1593 ath5k_tx_frame_completed(struct ath5k_softc *sc, struct sk_buff *skb,
1594 struct ath5k_tx_status *ts)
1596 struct ieee80211_tx_info *info;
1599 sc->stats.tx_all_count++;
1600 sc->stats.tx_bytes_count += skb->len;
1601 info = IEEE80211_SKB_CB(skb);
1603 ieee80211_tx_info_clear_status(info);
1604 for (i = 0; i < 4; i++) {
1605 struct ieee80211_tx_rate *r =
1606 &info->status.rates[i];
1608 if (ts->ts_rate[i]) {
1609 r->idx = ath5k_hw_to_driver_rix(sc, ts->ts_rate[i]);
1610 r->count = ts->ts_retry[i];
1617 /* count the successful attempt as well */
1618 info->status.rates[ts->ts_final_idx].count++;
1620 if (unlikely(ts->ts_status)) {
1621 sc->stats.ack_fail++;
1622 if (ts->ts_status & AR5K_TXERR_FILT) {
1623 info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
1624 sc->stats.txerr_filt++;
1626 if (ts->ts_status & AR5K_TXERR_XRETRY)
1627 sc->stats.txerr_retry++;
1628 if (ts->ts_status & AR5K_TXERR_FIFO)
1629 sc->stats.txerr_fifo++;
1631 info->flags |= IEEE80211_TX_STAT_ACK;
1632 info->status.ack_signal = ts->ts_rssi;
1636 * Remove MAC header padding before giving the frame
1639 ath5k_remove_padding(skb);
1641 if (ts->ts_antenna > 0 && ts->ts_antenna < 5)
1642 sc->stats.antenna_tx[ts->ts_antenna]++;
1644 sc->stats.antenna_tx[0]++; /* invalid */
1646 ieee80211_tx_status(sc->hw, skb);
1650 ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1652 struct ath5k_tx_status ts = {};
1653 struct ath5k_buf *bf, *bf0;
1654 struct ath5k_desc *ds;
1655 struct sk_buff *skb;
1658 spin_lock(&txq->lock);
1659 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1661 txq->txq_poll_mark = false;
1663 /* skb might already have been processed last time. */
1664 if (bf->skb != NULL) {
1667 ret = sc->ah->ah_proc_tx_desc(sc->ah, ds, &ts);
1668 if (unlikely(ret == -EINPROGRESS))
1670 else if (unlikely(ret)) {
1672 "error %d while processing "
1673 "queue %u\n", ret, txq->qnum);
1680 dma_unmap_single(sc->dev, bf->skbaddr, skb->len,
1682 ath5k_tx_frame_completed(sc, skb, &ts);
1686 * It's possible that the hardware can say the buffer is
1687 * completed when it hasn't yet loaded the ds_link from
1688 * host memory and moved on.
1689 * Always keep the last descriptor to avoid HW races...
1691 if (ath5k_hw_get_txdp(sc->ah, txq->qnum) != bf->daddr) {
1692 spin_lock(&sc->txbuflock);
1693 list_move_tail(&bf->list, &sc->txbuf);
1696 spin_unlock(&sc->txbuflock);
1699 spin_unlock(&txq->lock);
1700 if (txq->txq_len < ATH5K_TXQ_LEN_LOW && txq->qnum < 4)
1701 ieee80211_wake_queue(sc->hw, txq->qnum);
1705 ath5k_tasklet_tx(unsigned long data)
1708 struct ath5k_softc *sc = (void *)data;
1710 for (i=0; i < AR5K_NUM_TX_QUEUES; i++)
1711 if (sc->txqs[i].setup && (sc->ah->ah_txq_isr & BIT(i)))
1712 ath5k_tx_processq(sc, &sc->txqs[i]);
1721 * Setup the beacon frame for transmit.
1724 ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1726 struct sk_buff *skb = bf->skb;
1727 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1728 struct ath5k_hw *ah = sc->ah;
1729 struct ath5k_desc *ds;
1733 const int padsize = 0;
1735 bf->skbaddr = dma_map_single(sc->dev, skb->data, skb->len,
1737 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
1738 "skbaddr %llx\n", skb, skb->data, skb->len,
1739 (unsigned long long)bf->skbaddr);
1741 if (dma_mapping_error(sc->dev, bf->skbaddr)) {
1742 ATH5K_ERR(sc, "beacon DMA mapping failed\n");
1747 antenna = ah->ah_tx_ant;
1749 flags = AR5K_TXDESC_NOACK;
1750 if (sc->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) {
1751 ds->ds_link = bf->daddr; /* self-linked */
1752 flags |= AR5K_TXDESC_VEOL;
1757 * If we use multiple antennas on AP and use
1758 * the Sectored AP scenario, switch antenna every
1759 * 4 beacons to make sure everybody hears our AP.
1760 * When a client tries to associate, hw will keep
1761 * track of the tx antenna to be used for this client
1762 * automaticaly, based on ACKed packets.
1764 * Note: AP still listens and transmits RTS on the
1765 * default antenna which is supposed to be an omni.
1767 * Note2: On sectored scenarios it's possible to have
1768 * multiple antennas (1 omni -- the default -- and 14
1769 * sectors), so if we choose to actually support this
1770 * mode, we need to allow the user to set how many antennas
1771 * we have and tweak the code below to send beacons
1774 if (ah->ah_ant_mode == AR5K_ANTMODE_SECTOR_AP)
1775 antenna = sc->bsent & 4 ? 2 : 1;
1778 /* FIXME: If we are in g mode and rate is a CCK rate
1779 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
1780 * from tx power (value is in dB units already) */
1781 ds->ds_data = bf->skbaddr;
1782 ret = ah->ah_setup_tx_desc(ah, ds, skb->len,
1783 ieee80211_get_hdrlen_from_skb(skb), padsize,
1784 AR5K_PKT_TYPE_BEACON, (sc->power_level * 2),
1785 ieee80211_get_tx_rate(sc->hw, info)->hw_value,
1786 1, AR5K_TXKEYIX_INVALID,
1787 antenna, flags, 0, 0);
1793 dma_unmap_single(sc->dev, bf->skbaddr, skb->len, DMA_TO_DEVICE);
1798 * Updates the beacon that is sent by ath5k_beacon_send. For adhoc,
1799 * this is called only once at config_bss time, for AP we do it every
1800 * SWBA interrupt so that the TIM will reflect buffered frames.
1802 * Called with the beacon lock.
1805 ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
1808 struct ath5k_softc *sc = hw->priv;
1809 struct ath5k_vif *avf = (void *)vif->drv_priv;
1810 struct sk_buff *skb;
1812 if (WARN_ON(!vif)) {
1817 skb = ieee80211_beacon_get(hw, vif);
1824 ath5k_debug_dump_skb(sc, skb, "BC ", 1);
1826 ath5k_txbuf_free_skb(sc, avf->bbuf);
1827 avf->bbuf->skb = skb;
1828 ret = ath5k_beacon_setup(sc, avf->bbuf);
1830 avf->bbuf->skb = NULL;
1836 * Transmit a beacon frame at SWBA. Dynamic updates to the
1837 * frame contents are done as needed and the slot time is
1838 * also adjusted based on current state.
1840 * This is called from software irq context (beacontq tasklets)
1841 * or user context from ath5k_beacon_config.
1844 ath5k_beacon_send(struct ath5k_softc *sc)
1846 struct ath5k_hw *ah = sc->ah;
1847 struct ieee80211_vif *vif;
1848 struct ath5k_vif *avf;
1849 struct ath5k_buf *bf;
1850 struct sk_buff *skb;
1852 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "in beacon_send\n");
1855 * Check if the previous beacon has gone out. If
1856 * not, don't don't try to post another: skip this
1857 * period and wait for the next. Missed beacons
1858 * indicate a problem and should not occur. If we
1859 * miss too many consecutive beacons reset the device.
1861 if (unlikely(ath5k_hw_num_tx_pending(ah, sc->bhalq) != 0)) {
1863 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1864 "missed %u consecutive beacons\n", sc->bmisscount);
1865 if (sc->bmisscount > 10) { /* NB: 10 is a guess */
1866 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1867 "stuck beacon time (%u missed)\n",
1869 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
1870 "stuck beacon, resetting\n");
1871 ieee80211_queue_work(sc->hw, &sc->reset_work);
1875 if (unlikely(sc->bmisscount != 0)) {
1876 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1877 "resume beacon xmit after %u misses\n",
1882 if (sc->opmode == NL80211_IFTYPE_AP && sc->num_ap_vifs > 1) {
1883 u64 tsf = ath5k_hw_get_tsf64(ah);
1884 u32 tsftu = TSF_TO_TU(tsf);
1885 int slot = ((tsftu % sc->bintval) * ATH_BCBUF) / sc->bintval;
1886 vif = sc->bslot[(slot + 1) % ATH_BCBUF];
1887 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1888 "tsf %llx tsftu %x intval %u slot %u vif %p\n",
1889 (unsigned long long)tsf, tsftu, sc->bintval, slot, vif);
1890 } else /* only one interface */
1896 avf = (void *)vif->drv_priv;
1898 if (unlikely(bf->skb == NULL || sc->opmode == NL80211_IFTYPE_STATION ||
1899 sc->opmode == NL80211_IFTYPE_MONITOR)) {
1900 ATH5K_WARN(sc, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL);
1905 * Stop any current dma and put the new frame on the queue.
1906 * This should never fail since we check above that no frames
1907 * are still pending on the queue.
1909 if (unlikely(ath5k_hw_stop_beacon_queue(ah, sc->bhalq))) {
1910 ATH5K_WARN(sc, "beacon queue %u didn't start/stop ?\n", sc->bhalq);
1911 /* NB: hw still stops DMA, so proceed */
1914 /* refresh the beacon for AP mode */
1915 if (sc->opmode == NL80211_IFTYPE_AP)
1916 ath5k_beacon_update(sc->hw, vif);
1918 ath5k_hw_set_txdp(ah, sc->bhalq, bf->daddr);
1919 ath5k_hw_start_tx_dma(ah, sc->bhalq);
1920 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
1921 sc->bhalq, (unsigned long long)bf->daddr, bf->desc);
1923 skb = ieee80211_get_buffered_bc(sc->hw, vif);
1925 ath5k_tx_queue(sc->hw, skb, sc->cabq);
1926 skb = ieee80211_get_buffered_bc(sc->hw, vif);
1933 * ath5k_beacon_update_timers - update beacon timers
1935 * @sc: struct ath5k_softc pointer we are operating on
1936 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
1937 * beacon timer update based on the current HW TSF.
1939 * Calculate the next target beacon transmit time (TBTT) based on the timestamp
1940 * of a received beacon or the current local hardware TSF and write it to the
1941 * beacon timer registers.
1943 * This is called in a variety of situations, e.g. when a beacon is received,
1944 * when a TSF update has been detected, but also when an new IBSS is created or
1945 * when we otherwise know we have to update the timers, but we keep it in this
1946 * function to have it all together in one place.
1949 ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
1951 struct ath5k_hw *ah = sc->ah;
1952 u32 nexttbtt, intval, hw_tu, bc_tu;
1955 intval = sc->bintval & AR5K_BEACON_PERIOD;
1956 if (sc->opmode == NL80211_IFTYPE_AP && sc->num_ap_vifs > 1) {
1957 intval /= ATH_BCBUF; /* staggered multi-bss beacons */
1959 ATH5K_WARN(sc, "intval %u is too low, min 15\n",
1962 if (WARN_ON(!intval))
1965 /* beacon TSF converted to TU */
1966 bc_tu = TSF_TO_TU(bc_tsf);
1968 /* current TSF converted to TU */
1969 hw_tsf = ath5k_hw_get_tsf64(ah);
1970 hw_tu = TSF_TO_TU(hw_tsf);
1972 #define FUDGE AR5K_TUNE_SW_BEACON_RESP + 3
1973 /* We use FUDGE to make sure the next TBTT is ahead of the current TU.
1974 * Since we later substract AR5K_TUNE_SW_BEACON_RESP (10) in the timer
1975 * configuration we need to make sure it is bigger than that. */
1979 * no beacons received, called internally.
1980 * just need to refresh timers based on HW TSF.
1982 nexttbtt = roundup(hw_tu + FUDGE, intval);
1983 } else if (bc_tsf == 0) {
1985 * no beacon received, probably called by ath5k_reset_tsf().
1986 * reset TSF to start with 0.
1989 intval |= AR5K_BEACON_RESET_TSF;
1990 } else if (bc_tsf > hw_tsf) {
1992 * beacon received, SW merge happend but HW TSF not yet updated.
1993 * not possible to reconfigure timers yet, but next time we
1994 * receive a beacon with the same BSSID, the hardware will
1995 * automatically update the TSF and then we need to reconfigure
1998 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1999 "need to wait for HW TSF sync\n");
2003 * most important case for beacon synchronization between STA.
2005 * beacon received and HW TSF has been already updated by HW.
2006 * update next TBTT based on the TSF of the beacon, but make
2007 * sure it is ahead of our local TSF timer.
2009 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval);
2013 sc->nexttbtt = nexttbtt;
2015 intval |= AR5K_BEACON_ENA;
2016 ath5k_hw_init_beacon(ah, nexttbtt, intval);
2019 * debugging output last in order to preserve the time critical aspect
2023 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2024 "reconfigured timers based on HW TSF\n");
2025 else if (bc_tsf == 0)
2026 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2027 "reset HW TSF and timers\n");
2029 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2030 "updated timers based on beacon TSF\n");
2032 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2033 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2034 (unsigned long long) bc_tsf,
2035 (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt);
2036 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "intval %u %s %s\n",
2037 intval & AR5K_BEACON_PERIOD,
2038 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "",
2039 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : "");
2043 * ath5k_beacon_config - Configure the beacon queues and interrupts
2045 * @sc: struct ath5k_softc pointer we are operating on
2047 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
2048 * interrupts to detect TSF updates only.
2051 ath5k_beacon_config(struct ath5k_softc *sc)
2053 struct ath5k_hw *ah = sc->ah;
2054 unsigned long flags;
2056 spin_lock_irqsave(&sc->block, flags);
2058 sc->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA);
2060 if (sc->enable_beacon) {
2062 * In IBSS mode we use a self-linked tx descriptor and let the
2063 * hardware send the beacons automatically. We have to load it
2065 * We use the SWBA interrupt only to keep track of the beacon
2066 * timers in order to detect automatic TSF updates.
2068 ath5k_beaconq_config(sc);
2070 sc->imask |= AR5K_INT_SWBA;
2072 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
2073 if (ath5k_hw_hasveol(ah))
2074 ath5k_beacon_send(sc);
2076 ath5k_beacon_update_timers(sc, -1);
2078 ath5k_hw_stop_beacon_queue(sc->ah, sc->bhalq);
2081 ath5k_hw_set_imr(ah, sc->imask);
2083 spin_unlock_irqrestore(&sc->block, flags);
2086 static void ath5k_tasklet_beacon(unsigned long data)
2088 struct ath5k_softc *sc = (struct ath5k_softc *) data;
2091 * Software beacon alert--time to send a beacon.
2093 * In IBSS mode we use this interrupt just to
2094 * keep track of the next TBTT (target beacon
2095 * transmission time) in order to detect wether
2096 * automatic TSF updates happened.
2098 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
2099 /* XXX: only if VEOL suppported */
2100 u64 tsf = ath5k_hw_get_tsf64(sc->ah);
2101 sc->nexttbtt += sc->bintval;
2102 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2103 "SWBA nexttbtt: %x hw_tu: %x "
2107 (unsigned long long) tsf);
2109 spin_lock(&sc->block);
2110 ath5k_beacon_send(sc);
2111 spin_unlock(&sc->block);
2116 /********************\
2117 * Interrupt handling *
2118 \********************/
2121 ath5k_intr_calibration_poll(struct ath5k_hw *ah)
2123 if (time_is_before_eq_jiffies(ah->ah_cal_next_ani) &&
2124 !(ah->ah_cal_mask & AR5K_CALIBRATION_FULL)) {
2125 /* run ANI only when full calibration is not active */
2126 ah->ah_cal_next_ani = jiffies +
2127 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_ANI);
2128 tasklet_schedule(&ah->ah_sc->ani_tasklet);
2130 } else if (time_is_before_eq_jiffies(ah->ah_cal_next_full)) {
2131 ah->ah_cal_next_full = jiffies +
2132 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_FULL);
2133 tasklet_schedule(&ah->ah_sc->calib);
2135 /* we could use SWI to generate enough interrupts to meet our
2136 * calibration interval requirements, if necessary:
2137 * AR5K_REG_ENABLE_BITS(ah, AR5K_CR, AR5K_CR_SWI); */
2141 ath5k_intr(int irq, void *dev_id)
2143 struct ath5k_softc *sc = dev_id;
2144 struct ath5k_hw *ah = sc->ah;
2145 enum ath5k_int status;
2146 unsigned int counter = 1000;
2148 if (unlikely(test_bit(ATH_STAT_INVALID, sc->status) ||
2149 ((ath5k_get_bus_type(ah) != ATH_AHB) &&
2150 !ath5k_hw_is_intr_pending(ah))))
2154 ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */
2155 ATH5K_DBG(sc, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
2157 if (unlikely(status & AR5K_INT_FATAL)) {
2159 * Fatal errors are unrecoverable.
2160 * Typically these are caused by DMA errors.
2162 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2163 "fatal int, resetting\n");
2164 ieee80211_queue_work(sc->hw, &sc->reset_work);
2165 } else if (unlikely(status & AR5K_INT_RXORN)) {
2167 * Receive buffers are full. Either the bus is busy or
2168 * the CPU is not fast enough to process all received
2170 * Older chipsets need a reset to come out of this
2171 * condition, but we treat it as RX for newer chips.
2172 * We don't know exactly which versions need a reset -
2173 * this guess is copied from the HAL.
2175 sc->stats.rxorn_intr++;
2176 if (ah->ah_mac_srev < AR5K_SREV_AR5212) {
2177 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2178 "rx overrun, resetting\n");
2179 ieee80211_queue_work(sc->hw, &sc->reset_work);
2182 tasklet_schedule(&sc->rxtq);
2184 if (status & AR5K_INT_SWBA) {
2185 tasklet_hi_schedule(&sc->beacontq);
2187 if (status & AR5K_INT_RXEOL) {
2189 * NB: the hardware should re-read the link when
2190 * RXE bit is written, but it doesn't work at
2191 * least on older hardware revs.
2193 sc->stats.rxeol_intr++;
2195 if (status & AR5K_INT_TXURN) {
2196 /* bump tx trigger level */
2197 ath5k_hw_update_tx_triglevel(ah, true);
2199 if (status & (AR5K_INT_RXOK | AR5K_INT_RXERR))
2200 tasklet_schedule(&sc->rxtq);
2201 if (status & (AR5K_INT_TXOK | AR5K_INT_TXDESC
2202 | AR5K_INT_TXERR | AR5K_INT_TXEOL))
2203 tasklet_schedule(&sc->txtq);
2204 if (status & AR5K_INT_BMISS) {
2207 if (status & AR5K_INT_MIB) {
2208 sc->stats.mib_intr++;
2209 ath5k_hw_update_mib_counters(ah);
2210 ath5k_ani_mib_intr(ah);
2212 if (status & AR5K_INT_GPIO)
2213 tasklet_schedule(&sc->rf_kill.toggleq);
2217 if (ath5k_get_bus_type(ah) == ATH_AHB)
2220 } while (ath5k_hw_is_intr_pending(ah) && --counter > 0);
2222 if (unlikely(!counter))
2223 ATH5K_WARN(sc, "too many interrupts, giving up for now\n");
2225 ath5k_intr_calibration_poll(ah);
2231 * Periodically recalibrate the PHY to account
2232 * for temperature/environment changes.
2235 ath5k_tasklet_calibrate(unsigned long data)
2237 struct ath5k_softc *sc = (void *)data;
2238 struct ath5k_hw *ah = sc->ah;
2240 /* Only full calibration for now */
2241 ah->ah_cal_mask |= AR5K_CALIBRATION_FULL;
2243 ATH5K_DBG(sc, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
2244 ieee80211_frequency_to_channel(sc->curchan->center_freq),
2245 sc->curchan->hw_value);
2247 if (ath5k_hw_gainf_calibrate(ah) == AR5K_RFGAIN_NEED_CHANGE) {
2249 * Rfgain is out of bounds, reset the chip
2250 * to load new gain values.
2252 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "calibration, resetting\n");
2253 ieee80211_queue_work(sc->hw, &sc->reset_work);
2255 if (ath5k_hw_phy_calibrate(ah, sc->curchan))
2256 ATH5K_ERR(sc, "calibration of channel %u failed\n",
2257 ieee80211_frequency_to_channel(
2258 sc->curchan->center_freq));
2260 /* Noise floor calibration interrupts rx/tx path while I/Q calibration
2262 * TODO: We should stop TX here, so that it doesn't interfere.
2263 * Note that stopping the queues is not enough to stop TX! */
2264 if (time_is_before_eq_jiffies(ah->ah_cal_next_nf)) {
2265 ah->ah_cal_next_nf = jiffies +
2266 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_NF);
2267 ath5k_hw_update_noise_floor(ah);
2270 ah->ah_cal_mask &= ~AR5K_CALIBRATION_FULL;
2275 ath5k_tasklet_ani(unsigned long data)
2277 struct ath5k_softc *sc = (void *)data;
2278 struct ath5k_hw *ah = sc->ah;
2280 ah->ah_cal_mask |= AR5K_CALIBRATION_ANI;
2281 ath5k_ani_calibration(ah);
2282 ah->ah_cal_mask &= ~AR5K_CALIBRATION_ANI;
2287 ath5k_tx_complete_poll_work(struct work_struct *work)
2289 struct ath5k_softc *sc = container_of(work, struct ath5k_softc,
2290 tx_complete_work.work);
2291 struct ath5k_txq *txq;
2293 bool needreset = false;
2295 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++) {
2296 if (sc->txqs[i].setup) {
2298 spin_lock_bh(&txq->lock);
2299 if (txq->txq_len > 1) {
2300 if (txq->txq_poll_mark) {
2301 ATH5K_DBG(sc, ATH5K_DEBUG_XMIT,
2302 "TX queue stuck %d\n",
2306 spin_unlock_bh(&txq->lock);
2309 txq->txq_poll_mark = true;
2312 spin_unlock_bh(&txq->lock);
2317 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2318 "TX queues stuck, resetting\n");
2319 ath5k_reset(sc, NULL, true);
2322 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work,
2323 msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT));
2327 /*************************\
2328 * Initialization routines *
2329 \*************************/
2332 ath5k_init_softc(struct ath5k_softc *sc, const struct ath_bus_ops *bus_ops)
2334 struct ieee80211_hw *hw = sc->hw;
2335 struct ath_common *common;
2339 /* Initialize driver private data */
2340 SET_IEEE80211_DEV(hw, sc->dev);
2341 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
2342 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2343 IEEE80211_HW_SIGNAL_DBM |
2344 IEEE80211_HW_REPORTS_TX_ACK_STATUS;
2346 hw->wiphy->interface_modes =
2347 BIT(NL80211_IFTYPE_AP) |
2348 BIT(NL80211_IFTYPE_STATION) |
2349 BIT(NL80211_IFTYPE_ADHOC) |
2350 BIT(NL80211_IFTYPE_MESH_POINT);
2352 hw->extra_tx_headroom = 2;
2353 hw->channel_change_time = 5000;
2356 * Mark the device as detached to avoid processing
2357 * interrupts until setup is complete.
2359 __set_bit(ATH_STAT_INVALID, sc->status);
2361 sc->opmode = NL80211_IFTYPE_STATION;
2363 mutex_init(&sc->lock);
2364 spin_lock_init(&sc->rxbuflock);
2365 spin_lock_init(&sc->txbuflock);
2366 spin_lock_init(&sc->block);
2369 /* Setup interrupt handler */
2370 ret = request_irq(sc->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
2372 ATH5K_ERR(sc, "request_irq failed\n");
2376 /* If we passed the test, malloc an ath5k_hw struct */
2377 sc->ah = kzalloc(sizeof(struct ath5k_hw), GFP_KERNEL);
2380 ATH5K_ERR(sc, "out of memory\n");
2385 sc->ah->ah_iobase = sc->iobase;
2386 common = ath5k_hw_common(sc->ah);
2387 common->ops = &ath5k_common_ops;
2388 common->bus_ops = bus_ops;
2389 common->ah = sc->ah;
2394 * Cache line size is used to size and align various
2395 * structures used to communicate with the hardware.
2397 ath5k_read_cachesize(common, &csz);
2398 common->cachelsz = csz << 2; /* convert to bytes */
2400 spin_lock_init(&common->cc_lock);
2402 /* Initialize device */
2403 ret = ath5k_hw_init(sc);
2407 /* set up multi-rate retry capabilities */
2408 if (sc->ah->ah_version == AR5K_AR5212) {
2410 hw->max_rate_tries = 11;
2413 hw->vif_data_size = sizeof(struct ath5k_vif);
2415 /* Finish private driver data initialization */
2416 ret = ath5k_init(hw);
2420 ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
2421 ath5k_chip_name(AR5K_VERSION_MAC, sc->ah->ah_mac_srev),
2422 sc->ah->ah_mac_srev,
2423 sc->ah->ah_phy_revision);
2425 if (!sc->ah->ah_single_chip) {
2426 /* Single chip radio (!RF5111) */
2427 if (sc->ah->ah_radio_5ghz_revision &&
2428 !sc->ah->ah_radio_2ghz_revision) {
2429 /* No 5GHz support -> report 2GHz radio */
2430 if (!test_bit(AR5K_MODE_11A,
2431 sc->ah->ah_capabilities.cap_mode)) {
2432 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
2433 ath5k_chip_name(AR5K_VERSION_RAD,
2434 sc->ah->ah_radio_5ghz_revision),
2435 sc->ah->ah_radio_5ghz_revision);
2436 /* No 2GHz support (5110 and some
2437 * 5Ghz only cards) -> report 5Ghz radio */
2438 } else if (!test_bit(AR5K_MODE_11B,
2439 sc->ah->ah_capabilities.cap_mode)) {
2440 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
2441 ath5k_chip_name(AR5K_VERSION_RAD,
2442 sc->ah->ah_radio_5ghz_revision),
2443 sc->ah->ah_radio_5ghz_revision);
2444 /* Multiband radio */
2446 ATH5K_INFO(sc, "RF%s multiband radio found"
2448 ath5k_chip_name(AR5K_VERSION_RAD,
2449 sc->ah->ah_radio_5ghz_revision),
2450 sc->ah->ah_radio_5ghz_revision);
2453 /* Multi chip radio (RF5111 - RF2111) ->
2454 * report both 2GHz/5GHz radios */
2455 else if (sc->ah->ah_radio_5ghz_revision &&
2456 sc->ah->ah_radio_2ghz_revision){
2457 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
2458 ath5k_chip_name(AR5K_VERSION_RAD,
2459 sc->ah->ah_radio_5ghz_revision),
2460 sc->ah->ah_radio_5ghz_revision);
2461 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
2462 ath5k_chip_name(AR5K_VERSION_RAD,
2463 sc->ah->ah_radio_2ghz_revision),
2464 sc->ah->ah_radio_2ghz_revision);
2468 ath5k_debug_init_device(sc);
2470 /* ready to process interrupts */
2471 __clear_bit(ATH_STAT_INVALID, sc->status);
2475 ath5k_hw_deinit(sc->ah);
2479 free_irq(sc->irq, sc);
2485 ath5k_stop_locked(struct ath5k_softc *sc)
2487 struct ath5k_hw *ah = sc->ah;
2489 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "invalid %u\n",
2490 test_bit(ATH_STAT_INVALID, sc->status));
2493 * Shutdown the hardware and driver:
2494 * stop output from above
2495 * disable interrupts
2497 * turn off the radio
2498 * clear transmit machinery
2499 * clear receive machinery
2500 * drain and release tx queues
2501 * reclaim beacon resources
2502 * power down hardware
2504 * Note that some of this work is not possible if the
2505 * hardware is gone (invalid).
2507 ieee80211_stop_queues(sc->hw);
2509 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2511 ath5k_hw_set_imr(ah, 0);
2512 synchronize_irq(sc->irq);
2514 ath5k_hw_dma_stop(ah);
2515 ath5k_drain_tx_buffs(sc);
2516 ath5k_hw_phy_disable(ah);
2523 ath5k_init_hw(struct ath5k_softc *sc)
2525 struct ath5k_hw *ah = sc->ah;
2526 struct ath_common *common = ath5k_hw_common(ah);
2529 mutex_lock(&sc->lock);
2531 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mode %d\n", sc->opmode);
2534 * Stop anything previously setup. This is safe
2535 * no matter this is the first time through or not.
2537 ath5k_stop_locked(sc);
2540 * The basic interface to setting the hardware in a good
2541 * state is ``reset''. On return the hardware is known to
2542 * be powered up and with interrupts disabled. This must
2543 * be followed by initialization of the appropriate bits
2544 * and then setup of the interrupt mask.
2546 sc->curchan = sc->hw->conf.channel;
2547 sc->curband = &sc->sbands[sc->curchan->band];
2548 sc->imask = AR5K_INT_RXOK | AR5K_INT_RXERR | AR5K_INT_RXEOL |
2549 AR5K_INT_RXORN | AR5K_INT_TXDESC | AR5K_INT_TXEOL |
2550 AR5K_INT_FATAL | AR5K_INT_GLOBAL | AR5K_INT_MIB;
2552 ret = ath5k_reset(sc, NULL, false);
2556 ath5k_rfkill_hw_start(ah);
2559 * Reset the key cache since some parts do not reset the
2560 * contents on initial power up or resume from suspend.
2562 for (i = 0; i < common->keymax; i++)
2563 ath_hw_keyreset(common, (u16) i);
2565 /* Use higher rates for acks instead of base
2567 ah->ah_ack_bitrate_high = true;
2569 for (i = 0; i < ARRAY_SIZE(sc->bslot); i++)
2570 sc->bslot[i] = NULL;
2575 mutex_unlock(&sc->lock);
2577 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work,
2578 msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT));
2583 static void stop_tasklets(struct ath5k_softc *sc)
2585 tasklet_kill(&sc->rxtq);
2586 tasklet_kill(&sc->txtq);
2587 tasklet_kill(&sc->calib);
2588 tasklet_kill(&sc->beacontq);
2589 tasklet_kill(&sc->ani_tasklet);
2593 * Stop the device, grabbing the top-level lock to protect
2594 * against concurrent entry through ath5k_init (which can happen
2595 * if another thread does a system call and the thread doing the
2596 * stop is preempted).
2599 ath5k_stop_hw(struct ath5k_softc *sc)
2603 mutex_lock(&sc->lock);
2604 ret = ath5k_stop_locked(sc);
2605 if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) {
2607 * Don't set the card in full sleep mode!
2609 * a) When the device is in this state it must be carefully
2610 * woken up or references to registers in the PCI clock
2611 * domain may freeze the bus (and system). This varies
2612 * by chip and is mostly an issue with newer parts
2613 * (madwifi sources mentioned srev >= 0x78) that go to
2614 * sleep more quickly.
2616 * b) On older chips full sleep results a weird behaviour
2617 * during wakeup. I tested various cards with srev < 0x78
2618 * and they don't wake up after module reload, a second
2619 * module reload is needed to bring the card up again.
2621 * Until we figure out what's going on don't enable
2622 * full chip reset on any chip (this is what Legacy HAL
2623 * and Sam's HAL do anyway). Instead Perform a full reset
2624 * on the device (same as initial state after attach) and
2625 * leave it idle (keep MAC/BB on warm reset) */
2626 ret = ath5k_hw_on_hold(sc->ah);
2628 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2629 "putting device to sleep\n");
2633 mutex_unlock(&sc->lock);
2637 cancel_delayed_work_sync(&sc->tx_complete_work);
2639 ath5k_rfkill_hw_stop(sc->ah);
2645 * Reset the hardware. If chan is not NULL, then also pause rx/tx
2646 * and change to the given channel.
2648 * This should be called with sc->lock.
2651 ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan,
2654 struct ath5k_hw *ah = sc->ah;
2657 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n");
2659 ath5k_hw_set_imr(ah, 0);
2660 synchronize_irq(sc->irq);
2663 /* Save ani mode and disable ANI durring
2664 * reset. If we don't we might get false
2665 * PHY error interrupts. */
2666 ani_mode = ah->ah_sc->ani_state.ani_mode;
2667 ath5k_ani_init(ah, ATH5K_ANI_MODE_OFF);
2669 /* We are going to empty hw queues
2670 * so we should also free any remaining
2672 ath5k_drain_tx_buffs(sc);
2675 sc->curband = &sc->sbands[chan->band];
2677 ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, chan != NULL,
2680 ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret);
2684 ret = ath5k_rx_start(sc);
2686 ATH5K_ERR(sc, "can't start recv logic\n");
2690 ath5k_ani_init(ah, ani_mode);
2692 ah->ah_cal_next_full = jiffies;
2693 ah->ah_cal_next_ani = jiffies;
2694 ah->ah_cal_next_nf = jiffies;
2695 ewma_init(&ah->ah_beacon_rssi_avg, 1024, 8);
2698 * Change channels and update the h/w rate map if we're switching;
2699 * e.g. 11a to 11b/g.
2701 * We may be doing a reset in response to an ioctl that changes the
2702 * channel so update any state that might change as a result.
2706 /* ath5k_chan_change(sc, c); */
2708 ath5k_beacon_config(sc);
2709 /* intrs are enabled by ath5k_beacon_config */
2711 ieee80211_wake_queues(sc->hw);
2718 static void ath5k_reset_work(struct work_struct *work)
2720 struct ath5k_softc *sc = container_of(work, struct ath5k_softc,
2723 mutex_lock(&sc->lock);
2724 ath5k_reset(sc, NULL, true);
2725 mutex_unlock(&sc->lock);
2729 ath5k_init(struct ieee80211_hw *hw)
2732 struct ath5k_softc *sc = hw->priv;
2733 struct ath5k_hw *ah = sc->ah;
2734 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah);
2735 struct ath5k_txq *txq;
2736 u8 mac[ETH_ALEN] = {};
2741 * Check if the MAC has multi-rate retry support.
2742 * We do this by trying to setup a fake extended
2743 * descriptor. MACs that don't have support will
2744 * return false w/o doing anything. MACs that do
2745 * support it will return true w/o doing anything.
2747 ret = ath5k_hw_setup_mrr_tx_desc(ah, NULL, 0, 0, 0, 0, 0, 0);
2752 __set_bit(ATH_STAT_MRRETRY, sc->status);
2755 * Collect the channel list. The 802.11 layer
2756 * is resposible for filtering this list based
2757 * on settings like the phy mode and regulatory
2758 * domain restrictions.
2760 ret = ath5k_setup_bands(hw);
2762 ATH5K_ERR(sc, "can't get channels\n");
2766 /* NB: setup here so ath5k_rate_update is happy */
2767 if (test_bit(AR5K_MODE_11A, ah->ah_modes))
2768 ath5k_setcurmode(sc, AR5K_MODE_11A);
2770 ath5k_setcurmode(sc, AR5K_MODE_11B);
2773 * Allocate tx+rx descriptors and populate the lists.
2775 ret = ath5k_desc_alloc(sc);
2777 ATH5K_ERR(sc, "can't allocate descriptors\n");
2782 * Allocate hardware transmit queues: one queue for
2783 * beacon frames and one data queue for each QoS
2784 * priority. Note that hw functions handle resetting
2785 * these queues at the needed time.
2787 ret = ath5k_beaconq_setup(ah);
2789 ATH5K_ERR(sc, "can't setup a beacon xmit queue\n");
2793 sc->cabq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_CAB, 0);
2794 if (IS_ERR(sc->cabq)) {
2795 ATH5K_ERR(sc, "can't setup cab queue\n");
2796 ret = PTR_ERR(sc->cabq);
2800 /* 5211 and 5212 usually support 10 queues but we better rely on the
2801 * capability information */
2802 if (ah->ah_capabilities.cap_queues.q_tx_num >= 6) {
2803 /* This order matches mac80211's queue priority, so we can
2804 * directly use the mac80211 queue number without any mapping */
2805 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VO);
2807 ATH5K_ERR(sc, "can't setup xmit queue\n");
2811 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VI);
2813 ATH5K_ERR(sc, "can't setup xmit queue\n");
2817 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BE);
2819 ATH5K_ERR(sc, "can't setup xmit queue\n");
2823 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
2825 ATH5K_ERR(sc, "can't setup xmit queue\n");
2831 /* older hardware (5210) can only support one data queue */
2832 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BE);
2834 ATH5K_ERR(sc, "can't setup xmit queue\n");
2841 tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc);
2842 tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc);
2843 tasklet_init(&sc->calib, ath5k_tasklet_calibrate, (unsigned long)sc);
2844 tasklet_init(&sc->beacontq, ath5k_tasklet_beacon, (unsigned long)sc);
2845 tasklet_init(&sc->ani_tasklet, ath5k_tasklet_ani, (unsigned long)sc);
2847 INIT_WORK(&sc->reset_work, ath5k_reset_work);
2848 INIT_DELAYED_WORK(&sc->tx_complete_work, ath5k_tx_complete_poll_work);
2850 ret = ath5k_eeprom_read_mac(ah, mac);
2852 ATH5K_ERR(sc, "unable to read address from EEPROM\n");
2856 SET_IEEE80211_PERM_ADDR(hw, mac);
2857 memcpy(&sc->lladdr, mac, ETH_ALEN);
2858 /* All MAC address bits matter for ACKs */
2859 ath5k_update_bssid_mask_and_opmode(sc, NULL);
2861 regulatory->current_rd = ah->ah_capabilities.cap_eeprom.ee_regdomain;
2862 ret = ath_regd_init(regulatory, hw->wiphy, ath5k_reg_notifier);
2864 ATH5K_ERR(sc, "can't initialize regulatory system\n");
2868 ret = ieee80211_register_hw(hw);
2870 ATH5K_ERR(sc, "can't register ieee80211 hw\n");
2874 if (!ath_is_world_regd(regulatory))
2875 regulatory_hint(hw->wiphy, regulatory->alpha2);
2877 ath5k_init_leds(sc);
2879 ath5k_sysfs_register(sc);
2883 ath5k_txq_release(sc);
2885 ath5k_hw_release_tx_queue(ah, sc->bhalq);
2887 ath5k_desc_free(sc);
2893 ath5k_deinit_softc(struct ath5k_softc *sc)
2895 struct ieee80211_hw *hw = sc->hw;
2898 * NB: the order of these is important:
2899 * o call the 802.11 layer before detaching ath5k_hw to
2900 * ensure callbacks into the driver to delete global
2901 * key cache entries can be handled
2902 * o reclaim the tx queue data structures after calling
2903 * the 802.11 layer as we'll get called back to reclaim
2904 * node state and potentially want to use them
2905 * o to cleanup the tx queues the hal is called, so detach
2907 * XXX: ??? detach ath5k_hw ???
2908 * Other than that, it's straightforward...
2910 ath5k_debug_finish_device(sc);
2911 ieee80211_unregister_hw(hw);
2912 ath5k_desc_free(sc);
2913 ath5k_txq_release(sc);
2914 ath5k_hw_release_tx_queue(sc->ah, sc->bhalq);
2915 ath5k_unregister_leds(sc);
2917 ath5k_sysfs_unregister(sc);
2919 * NB: can't reclaim these until after ieee80211_ifdetach
2920 * returns because we'll get called back to reclaim node
2921 * state and potentially want to use them.
2923 ath5k_hw_deinit(sc->ah);
2924 free_irq(sc->irq, sc);
2927 /********************\
2928 * Mac80211 functions *
2929 \********************/
2932 ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
2934 struct ath5k_softc *sc = hw->priv;
2935 u16 qnum = skb_get_queue_mapping(skb);
2937 if (WARN_ON(qnum >= sc->ah->ah_capabilities.cap_queues.q_tx_num)) {
2938 dev_kfree_skb_any(skb);
2942 return ath5k_tx_queue(hw, skb, &sc->txqs[qnum]);
2945 static int ath5k_start(struct ieee80211_hw *hw)
2947 return ath5k_init_hw(hw->priv);
2950 static void ath5k_stop(struct ieee80211_hw *hw)
2952 ath5k_stop_hw(hw->priv);
2955 static int ath5k_add_interface(struct ieee80211_hw *hw,
2956 struct ieee80211_vif *vif)
2958 struct ath5k_softc *sc = hw->priv;
2960 struct ath5k_vif *avf = (void *)vif->drv_priv;
2962 mutex_lock(&sc->lock);
2964 if ((vif->type == NL80211_IFTYPE_AP ||
2965 vif->type == NL80211_IFTYPE_ADHOC)
2966 && (sc->num_ap_vifs + sc->num_adhoc_vifs) >= ATH_BCBUF) {
2971 /* Don't allow other interfaces if one ad-hoc is configured.
2972 * TODO: Fix the problems with ad-hoc and multiple other interfaces.
2973 * We would need to operate the HW in ad-hoc mode to allow TSF updates
2974 * for the IBSS, but this breaks with additional AP or STA interfaces
2976 if (sc->num_adhoc_vifs ||
2977 (sc->nvifs && vif->type == NL80211_IFTYPE_ADHOC)) {
2978 ATH5K_ERR(sc, "Only one single ad-hoc interface is allowed.\n");
2983 switch (vif->type) {
2984 case NL80211_IFTYPE_AP:
2985 case NL80211_IFTYPE_STATION:
2986 case NL80211_IFTYPE_ADHOC:
2987 case NL80211_IFTYPE_MESH_POINT:
2988 avf->opmode = vif->type;
2996 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "add interface mode %d\n", avf->opmode);
2998 /* Assign the vap/adhoc to a beacon xmit slot. */
2999 if ((avf->opmode == NL80211_IFTYPE_AP) ||
3000 (avf->opmode == NL80211_IFTYPE_ADHOC)) {
3003 WARN_ON(list_empty(&sc->bcbuf));
3004 avf->bbuf = list_first_entry(&sc->bcbuf, struct ath5k_buf,
3006 list_del(&avf->bbuf->list);
3009 for (slot = 0; slot < ATH_BCBUF; slot++) {
3010 if (!sc->bslot[slot]) {
3015 BUG_ON(sc->bslot[avf->bslot] != NULL);
3016 sc->bslot[avf->bslot] = vif;
3017 if (avf->opmode == NL80211_IFTYPE_AP)
3020 sc->num_adhoc_vifs++;
3023 /* Any MAC address is fine, all others are included through the
3026 memcpy(&sc->lladdr, vif->addr, ETH_ALEN);
3027 ath5k_hw_set_lladdr(sc->ah, vif->addr);
3029 memcpy(&avf->lladdr, vif->addr, ETH_ALEN);
3031 ath5k_mode_setup(sc, vif);
3035 mutex_unlock(&sc->lock);
3040 ath5k_remove_interface(struct ieee80211_hw *hw,
3041 struct ieee80211_vif *vif)
3043 struct ath5k_softc *sc = hw->priv;
3044 struct ath5k_vif *avf = (void *)vif->drv_priv;
3047 mutex_lock(&sc->lock);
3051 ath5k_txbuf_free_skb(sc, avf->bbuf);
3052 list_add_tail(&avf->bbuf->list, &sc->bcbuf);
3053 for (i = 0; i < ATH_BCBUF; i++) {
3054 if (sc->bslot[i] == vif) {
3055 sc->bslot[i] = NULL;
3061 if (avf->opmode == NL80211_IFTYPE_AP)
3063 else if (avf->opmode == NL80211_IFTYPE_ADHOC)
3064 sc->num_adhoc_vifs--;
3066 ath5k_update_bssid_mask_and_opmode(sc, NULL);
3067 mutex_unlock(&sc->lock);
3071 * TODO: Phy disable/diversity etc
3074 ath5k_config(struct ieee80211_hw *hw, u32 changed)
3076 struct ath5k_softc *sc = hw->priv;
3077 struct ath5k_hw *ah = sc->ah;
3078 struct ieee80211_conf *conf = &hw->conf;
3081 mutex_lock(&sc->lock);
3083 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
3084 ret = ath5k_chan_set(sc, conf->channel);
3089 if ((changed & IEEE80211_CONF_CHANGE_POWER) &&
3090 (sc->power_level != conf->power_level)) {
3091 sc->power_level = conf->power_level;
3094 ath5k_hw_set_txpower_limit(ah, (conf->power_level * 2));
3098 * 1) Move this on config_interface and handle each case
3099 * separately eg. when we have only one STA vif, use
3100 * AR5K_ANTMODE_SINGLE_AP
3102 * 2) Allow the user to change antenna mode eg. when only
3103 * one antenna is present
3105 * 3) Allow the user to set default/tx antenna when possible
3107 * 4) Default mode should handle 90% of the cases, together
3108 * with fixed a/b and single AP modes we should be able to
3109 * handle 99%. Sectored modes are extreme cases and i still
3110 * haven't found a usage for them. If we decide to support them,
3111 * then we must allow the user to set how many tx antennas we
3114 ath5k_hw_set_antenna_mode(ah, ah->ah_ant_mode);
3117 mutex_unlock(&sc->lock);
3121 static u64 ath5k_prepare_multicast(struct ieee80211_hw *hw,
3122 struct netdev_hw_addr_list *mc_list)
3126 struct netdev_hw_addr *ha;
3131 netdev_hw_addr_list_for_each(ha, mc_list) {
3132 /* calculate XOR of eight 6-bit values */
3133 val = get_unaligned_le32(ha->addr + 0);
3134 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
3135 val = get_unaligned_le32(ha->addr + 3);
3136 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
3138 mfilt[pos / 32] |= (1 << (pos % 32));
3139 /* XXX: we might be able to just do this instead,
3140 * but not sure, needs testing, if we do use this we'd
3141 * neet to inform below to not reset the mcast */
3142 /* ath5k_hw_set_mcast_filterindex(ah,
3146 return ((u64)(mfilt[1]) << 32) | mfilt[0];
3149 static bool ath_any_vif_assoc(struct ath5k_softc *sc)
3151 struct ath_vif_iter_data iter_data;
3152 iter_data.hw_macaddr = NULL;
3153 iter_data.any_assoc = false;
3154 iter_data.need_set_hw_addr = false;
3155 iter_data.found_active = true;
3157 ieee80211_iterate_active_interfaces_atomic(sc->hw, ath_vif_iter,
3159 return iter_data.any_assoc;
3162 #define SUPPORTED_FIF_FLAGS \
3163 FIF_PROMISC_IN_BSS | FIF_ALLMULTI | FIF_FCSFAIL | \
3164 FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \
3165 FIF_BCN_PRBRESP_PROMISC
3167 * o always accept unicast, broadcast, and multicast traffic
3168 * o multicast traffic for all BSSIDs will be enabled if mac80211
3170 * o maintain current state of phy ofdm or phy cck error reception.
3171 * If the hardware detects any of these type of errors then
3172 * ath5k_hw_get_rx_filter() will pass to us the respective
3173 * hardware filters to be able to receive these type of frames.
3174 * o probe request frames are accepted only when operating in
3175 * hostap, adhoc, or monitor modes
3176 * o enable promiscuous mode according to the interface state
3178 * - when operating in adhoc mode so the 802.11 layer creates
3179 * node table entries for peers,
3180 * - when operating in station mode for collecting rssi data when
3181 * the station is otherwise quiet, or
3184 static void ath5k_configure_filter(struct ieee80211_hw *hw,
3185 unsigned int changed_flags,
3186 unsigned int *new_flags,
3189 struct ath5k_softc *sc = hw->priv;
3190 struct ath5k_hw *ah = sc->ah;
3191 u32 mfilt[2], rfilt;
3193 mutex_lock(&sc->lock);
3195 mfilt[0] = multicast;
3196 mfilt[1] = multicast >> 32;
3198 /* Only deal with supported flags */
3199 changed_flags &= SUPPORTED_FIF_FLAGS;
3200 *new_flags &= SUPPORTED_FIF_FLAGS;
3202 /* If HW detects any phy or radar errors, leave those filters on.
3203 * Also, always enable Unicast, Broadcasts and Multicast
3204 * XXX: move unicast, bssid broadcasts and multicast to mac80211 */
3205 rfilt = (ath5k_hw_get_rx_filter(ah) & (AR5K_RX_FILTER_PHYERR)) |
3206 (AR5K_RX_FILTER_UCAST | AR5K_RX_FILTER_BCAST |
3207 AR5K_RX_FILTER_MCAST);
3209 if (changed_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS)) {
3210 if (*new_flags & FIF_PROMISC_IN_BSS) {
3211 __set_bit(ATH_STAT_PROMISC, sc->status);
3213 __clear_bit(ATH_STAT_PROMISC, sc->status);
3217 if (test_bit(ATH_STAT_PROMISC, sc->status))
3218 rfilt |= AR5K_RX_FILTER_PROM;
3220 /* Note, AR5K_RX_FILTER_MCAST is already enabled */
3221 if (*new_flags & FIF_ALLMULTI) {
3226 /* This is the best we can do */
3227 if (*new_flags & (FIF_FCSFAIL | FIF_PLCPFAIL))
3228 rfilt |= AR5K_RX_FILTER_PHYERR;
3230 /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons
3231 * and probes for any BSSID */
3232 if ((*new_flags & FIF_BCN_PRBRESP_PROMISC) || (sc->nvifs > 1))
3233 rfilt |= AR5K_RX_FILTER_BEACON;
3235 /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not
3236 * set we should only pass on control frames for this
3237 * station. This needs testing. I believe right now this
3238 * enables *all* control frames, which is OK.. but
3239 * but we should see if we can improve on granularity */
3240 if (*new_flags & FIF_CONTROL)
3241 rfilt |= AR5K_RX_FILTER_CONTROL;
3243 /* Additional settings per mode -- this is per ath5k */
3245 /* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */
3247 switch (sc->opmode) {
3248 case NL80211_IFTYPE_MESH_POINT:
3249 rfilt |= AR5K_RX_FILTER_CONTROL |
3250 AR5K_RX_FILTER_BEACON |
3251 AR5K_RX_FILTER_PROBEREQ |
3252 AR5K_RX_FILTER_PROM;
3254 case NL80211_IFTYPE_AP:
3255 case NL80211_IFTYPE_ADHOC:
3256 rfilt |= AR5K_RX_FILTER_PROBEREQ |
3257 AR5K_RX_FILTER_BEACON;
3259 case NL80211_IFTYPE_STATION:
3261 rfilt |= AR5K_RX_FILTER_BEACON;
3267 ath5k_hw_set_rx_filter(ah, rfilt);
3269 /* Set multicast bits */
3270 ath5k_hw_set_mcast_filter(ah, mfilt[0], mfilt[1]);
3271 /* Set the cached hw filter flags, this will later actually
3273 sc->filter_flags = rfilt;
3275 mutex_unlock(&sc->lock);
3279 ath5k_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
3280 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
3281 struct ieee80211_key_conf *key)
3283 struct ath5k_softc *sc = hw->priv;
3284 struct ath5k_hw *ah = sc->ah;
3285 struct ath_common *common = ath5k_hw_common(ah);
3288 if (modparam_nohwcrypt)
3291 switch (key->cipher) {
3292 case WLAN_CIPHER_SUITE_WEP40:
3293 case WLAN_CIPHER_SUITE_WEP104:
3294 case WLAN_CIPHER_SUITE_TKIP:
3296 case WLAN_CIPHER_SUITE_CCMP:
3297 if (common->crypt_caps & ATH_CRYPT_CAP_CIPHER_AESCCM)
3305 mutex_lock(&sc->lock);
3309 ret = ath_key_config(common, vif, sta, key);
3311 key->hw_key_idx = ret;
3312 /* push IV and Michael MIC generation to stack */
3313 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
3314 if (key->cipher == WLAN_CIPHER_SUITE_TKIP)
3315 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
3316 if (key->cipher == WLAN_CIPHER_SUITE_CCMP)
3317 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
3322 ath_key_delete(common, key);
3329 mutex_unlock(&sc->lock);
3334 ath5k_get_stats(struct ieee80211_hw *hw,
3335 struct ieee80211_low_level_stats *stats)
3337 struct ath5k_softc *sc = hw->priv;
3340 ath5k_hw_update_mib_counters(sc->ah);
3342 stats->dot11ACKFailureCount = sc->stats.ack_fail;
3343 stats->dot11RTSFailureCount = sc->stats.rts_fail;
3344 stats->dot11RTSSuccessCount = sc->stats.rts_ok;
3345 stats->dot11FCSErrorCount = sc->stats.fcs_error;
3350 static int ath5k_get_survey(struct ieee80211_hw *hw, int idx,
3351 struct survey_info *survey)
3353 struct ath5k_softc *sc = hw->priv;
3354 struct ieee80211_conf *conf = &hw->conf;
3355 struct ath_common *common = ath5k_hw_common(sc->ah);
3356 struct ath_cycle_counters *cc = &common->cc_survey;
3357 unsigned int div = common->clockrate * 1000;
3362 survey->channel = conf->channel;
3363 survey->filled = SURVEY_INFO_NOISE_DBM;
3364 survey->noise = sc->ah->ah_noise_floor;
3366 spin_lock_bh(&common->cc_lock);
3367 ath_hw_cycle_counters_update(common);
3368 if (cc->cycles > 0) {
3369 survey->filled |= SURVEY_INFO_CHANNEL_TIME |
3370 SURVEY_INFO_CHANNEL_TIME_BUSY |
3371 SURVEY_INFO_CHANNEL_TIME_RX |
3372 SURVEY_INFO_CHANNEL_TIME_TX;
3373 survey->channel_time += cc->cycles / div;
3374 survey->channel_time_busy += cc->rx_busy / div;
3375 survey->channel_time_rx += cc->rx_frame / div;
3376 survey->channel_time_tx += cc->tx_frame / div;
3378 memset(cc, 0, sizeof(*cc));
3379 spin_unlock_bh(&common->cc_lock);
3385 ath5k_get_tsf(struct ieee80211_hw *hw)
3387 struct ath5k_softc *sc = hw->priv;
3389 return ath5k_hw_get_tsf64(sc->ah);
3393 ath5k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
3395 struct ath5k_softc *sc = hw->priv;
3397 ath5k_hw_set_tsf64(sc->ah, tsf);
3401 ath5k_reset_tsf(struct ieee80211_hw *hw)
3403 struct ath5k_softc *sc = hw->priv;
3406 * in IBSS mode we need to update the beacon timers too.
3407 * this will also reset the TSF if we call it with 0
3409 if (sc->opmode == NL80211_IFTYPE_ADHOC)
3410 ath5k_beacon_update_timers(sc, 0);
3412 ath5k_hw_reset_tsf(sc->ah);
3416 set_beacon_filter(struct ieee80211_hw *hw, bool enable)
3418 struct ath5k_softc *sc = hw->priv;
3419 struct ath5k_hw *ah = sc->ah;
3421 rfilt = ath5k_hw_get_rx_filter(ah);
3423 rfilt |= AR5K_RX_FILTER_BEACON;
3425 rfilt &= ~AR5K_RX_FILTER_BEACON;
3426 ath5k_hw_set_rx_filter(ah, rfilt);
3427 sc->filter_flags = rfilt;
3430 static void ath5k_bss_info_changed(struct ieee80211_hw *hw,
3431 struct ieee80211_vif *vif,
3432 struct ieee80211_bss_conf *bss_conf,
3435 struct ath5k_vif *avf = (void *)vif->drv_priv;
3436 struct ath5k_softc *sc = hw->priv;
3437 struct ath5k_hw *ah = sc->ah;
3438 struct ath_common *common = ath5k_hw_common(ah);
3439 unsigned long flags;
3441 mutex_lock(&sc->lock);
3443 if (changes & BSS_CHANGED_BSSID) {
3444 /* Cache for later use during resets */
3445 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
3447 ath5k_hw_set_bssid(ah);
3451 if (changes & BSS_CHANGED_BEACON_INT)
3452 sc->bintval = bss_conf->beacon_int;
3454 if (changes & BSS_CHANGED_ASSOC) {
3455 avf->assoc = bss_conf->assoc;
3456 if (bss_conf->assoc)
3457 sc->assoc = bss_conf->assoc;
3459 sc->assoc = ath_any_vif_assoc(sc);
3461 if (sc->opmode == NL80211_IFTYPE_STATION)
3462 set_beacon_filter(hw, sc->assoc);
3463 ath5k_hw_set_ledstate(sc->ah, sc->assoc ?
3464 AR5K_LED_ASSOC : AR5K_LED_INIT);
3465 if (bss_conf->assoc) {
3466 ATH5K_DBG(sc, ATH5K_DEBUG_ANY,
3467 "Bss Info ASSOC %d, bssid: %pM\n",
3468 bss_conf->aid, common->curbssid);
3469 common->curaid = bss_conf->aid;
3470 ath5k_hw_set_bssid(ah);
3471 /* Once ANI is available you would start it here */
3475 if (changes & BSS_CHANGED_BEACON) {
3476 spin_lock_irqsave(&sc->block, flags);
3477 ath5k_beacon_update(hw, vif);
3478 spin_unlock_irqrestore(&sc->block, flags);
3481 if (changes & BSS_CHANGED_BEACON_ENABLED)
3482 sc->enable_beacon = bss_conf->enable_beacon;
3484 if (changes & (BSS_CHANGED_BEACON | BSS_CHANGED_BEACON_ENABLED |
3485 BSS_CHANGED_BEACON_INT))
3486 ath5k_beacon_config(sc);
3488 mutex_unlock(&sc->lock);
3491 static void ath5k_sw_scan_start(struct ieee80211_hw *hw)
3493 struct ath5k_softc *sc = hw->priv;
3495 ath5k_hw_set_ledstate(sc->ah, AR5K_LED_SCAN);
3498 static void ath5k_sw_scan_complete(struct ieee80211_hw *hw)
3500 struct ath5k_softc *sc = hw->priv;
3501 ath5k_hw_set_ledstate(sc->ah, sc->assoc ?
3502 AR5K_LED_ASSOC : AR5K_LED_INIT);
3506 * ath5k_set_coverage_class - Set IEEE 802.11 coverage class
3508 * @hw: struct ieee80211_hw pointer
3509 * @coverage_class: IEEE 802.11 coverage class number
3511 * Mac80211 callback. Sets slot time, ACK timeout and CTS timeout for given
3512 * coverage class. The values are persistent, they are restored after device
3515 static void ath5k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class)
3517 struct ath5k_softc *sc = hw->priv;
3519 mutex_lock(&sc->lock);
3520 ath5k_hw_set_coverage_class(sc->ah, coverage_class);
3521 mutex_unlock(&sc->lock);
3524 static int ath5k_conf_tx(struct ieee80211_hw *hw, u16 queue,
3525 const struct ieee80211_tx_queue_params *params)
3527 struct ath5k_softc *sc = hw->priv;
3528 struct ath5k_hw *ah = sc->ah;
3529 struct ath5k_txq_info qi;
3532 if (queue >= ah->ah_capabilities.cap_queues.q_tx_num)
3535 mutex_lock(&sc->lock);
3537 ath5k_hw_get_tx_queueprops(ah, queue, &qi);
3539 qi.tqi_aifs = params->aifs;
3540 qi.tqi_cw_min = params->cw_min;
3541 qi.tqi_cw_max = params->cw_max;
3542 qi.tqi_burst_time = params->txop;
3544 ATH5K_DBG(sc, ATH5K_DEBUG_ANY,
3545 "Configure tx [queue %d], "
3546 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
3547 queue, params->aifs, params->cw_min,
3548 params->cw_max, params->txop);
3550 if (ath5k_hw_set_tx_queueprops(ah, queue, &qi)) {
3552 "Unable to update hardware queue %u!\n", queue);
3555 ath5k_hw_reset_tx_queue(ah, queue);
3557 mutex_unlock(&sc->lock);
3562 static int ath5k_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant)
3564 struct ath5k_softc *sc = hw->priv;
3566 if (tx_ant == 1 && rx_ant == 1)
3567 ath5k_hw_set_antenna_mode(sc->ah, AR5K_ANTMODE_FIXED_A);
3568 else if (tx_ant == 2 && rx_ant == 2)
3569 ath5k_hw_set_antenna_mode(sc->ah, AR5K_ANTMODE_FIXED_B);
3570 else if ((tx_ant & 3) == 3 && (rx_ant & 3) == 3)
3571 ath5k_hw_set_antenna_mode(sc->ah, AR5K_ANTMODE_DEFAULT);
3577 static int ath5k_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant)
3579 struct ath5k_softc *sc = hw->priv;
3581 switch (sc->ah->ah_ant_mode) {
3582 case AR5K_ANTMODE_FIXED_A:
3583 *tx_ant = 1; *rx_ant = 1; break;
3584 case AR5K_ANTMODE_FIXED_B:
3585 *tx_ant = 2; *rx_ant = 2; break;
3586 case AR5K_ANTMODE_DEFAULT:
3587 *tx_ant = 3; *rx_ant = 3; break;
3592 const struct ieee80211_ops ath5k_hw_ops = {
3594 .start = ath5k_start,
3596 .add_interface = ath5k_add_interface,
3597 .remove_interface = ath5k_remove_interface,
3598 .config = ath5k_config,
3599 .prepare_multicast = ath5k_prepare_multicast,
3600 .configure_filter = ath5k_configure_filter,
3601 .set_key = ath5k_set_key,
3602 .get_stats = ath5k_get_stats,
3603 .get_survey = ath5k_get_survey,
3604 .conf_tx = ath5k_conf_tx,
3605 .get_tsf = ath5k_get_tsf,
3606 .set_tsf = ath5k_set_tsf,
3607 .reset_tsf = ath5k_reset_tsf,
3608 .bss_info_changed = ath5k_bss_info_changed,
3609 .sw_scan_start = ath5k_sw_scan_start,
3610 .sw_scan_complete = ath5k_sw_scan_complete,
3611 .set_coverage_class = ath5k_set_coverage_class,
3612 .set_antenna = ath5k_set_antenna,
3613 .get_antenna = ath5k_get_antenna,