2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
4 * Copyright (c) 2006 Devicescape Software, Inc.
5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39 * THE POSSIBILITY OF SUCH DAMAGES.
43 #include <linux/module.h>
44 #include <linux/delay.h>
45 #include <linux/hardirq.h>
48 #include <linux/netdevice.h>
49 #include <linux/cache.h>
50 #include <linux/pci.h>
51 #include <linux/pci-aspm.h>
52 #include <linux/ethtool.h>
53 #include <linux/uaccess.h>
54 #include <linux/slab.h>
55 #include <linux/etherdevice.h>
57 #include <net/ieee80211_radiotap.h>
59 #include <asm/unaligned.h>
67 static int modparam_nohwcrypt;
68 module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
69 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
71 static int modparam_all_channels;
72 module_param_named(all_channels, modparam_all_channels, bool, S_IRUGO);
73 MODULE_PARM_DESC(all_channels, "Expose all channels the device can use.");
76 MODULE_AUTHOR("Jiri Slaby");
77 MODULE_AUTHOR("Nick Kossifidis");
78 MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
79 MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
80 MODULE_LICENSE("Dual BSD/GPL");
81 MODULE_VERSION("0.6.0 (EXPERIMENTAL)");
83 static int ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan);
84 static int ath5k_beacon_update(struct ieee80211_hw *hw,
85 struct ieee80211_vif *vif);
86 static void ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf);
89 static DEFINE_PCI_DEVICE_TABLE(ath5k_pci_id_table) = {
90 { PCI_VDEVICE(ATHEROS, 0x0207) }, /* 5210 early */
91 { PCI_VDEVICE(ATHEROS, 0x0007) }, /* 5210 */
92 { PCI_VDEVICE(ATHEROS, 0x0011) }, /* 5311 - this is on AHB bus !*/
93 { PCI_VDEVICE(ATHEROS, 0x0012) }, /* 5211 */
94 { PCI_VDEVICE(ATHEROS, 0x0013) }, /* 5212 */
95 { PCI_VDEVICE(3COM_2, 0x0013) }, /* 3com 5212 */
96 { PCI_VDEVICE(3COM, 0x0013) }, /* 3com 3CRDAG675 5212 */
97 { PCI_VDEVICE(ATHEROS, 0x1014) }, /* IBM minipci 5212 */
98 { PCI_VDEVICE(ATHEROS, 0x0014) }, /* 5212 combatible */
99 { PCI_VDEVICE(ATHEROS, 0x0015) }, /* 5212 combatible */
100 { PCI_VDEVICE(ATHEROS, 0x0016) }, /* 5212 combatible */
101 { PCI_VDEVICE(ATHEROS, 0x0017) }, /* 5212 combatible */
102 { PCI_VDEVICE(ATHEROS, 0x0018) }, /* 5212 combatible */
103 { PCI_VDEVICE(ATHEROS, 0x0019) }, /* 5212 combatible */
104 { PCI_VDEVICE(ATHEROS, 0x001a) }, /* 2413 Griffin-lite */
105 { PCI_VDEVICE(ATHEROS, 0x001b) }, /* 5413 Eagle */
106 { PCI_VDEVICE(ATHEROS, 0x001c) }, /* PCI-E cards */
107 { PCI_VDEVICE(ATHEROS, 0x001d) }, /* 2417 Nala */
110 MODULE_DEVICE_TABLE(pci, ath5k_pci_id_table);
113 static const struct ath5k_srev_name srev_names[] = {
114 { "5210", AR5K_VERSION_MAC, AR5K_SREV_AR5210 },
115 { "5311", AR5K_VERSION_MAC, AR5K_SREV_AR5311 },
116 { "5311A", AR5K_VERSION_MAC, AR5K_SREV_AR5311A },
117 { "5311B", AR5K_VERSION_MAC, AR5K_SREV_AR5311B },
118 { "5211", AR5K_VERSION_MAC, AR5K_SREV_AR5211 },
119 { "5212", AR5K_VERSION_MAC, AR5K_SREV_AR5212 },
120 { "5213", AR5K_VERSION_MAC, AR5K_SREV_AR5213 },
121 { "5213A", AR5K_VERSION_MAC, AR5K_SREV_AR5213A },
122 { "2413", AR5K_VERSION_MAC, AR5K_SREV_AR2413 },
123 { "2414", AR5K_VERSION_MAC, AR5K_SREV_AR2414 },
124 { "5424", AR5K_VERSION_MAC, AR5K_SREV_AR5424 },
125 { "5413", AR5K_VERSION_MAC, AR5K_SREV_AR5413 },
126 { "5414", AR5K_VERSION_MAC, AR5K_SREV_AR5414 },
127 { "2415", AR5K_VERSION_MAC, AR5K_SREV_AR2415 },
128 { "5416", AR5K_VERSION_MAC, AR5K_SREV_AR5416 },
129 { "5418", AR5K_VERSION_MAC, AR5K_SREV_AR5418 },
130 { "2425", AR5K_VERSION_MAC, AR5K_SREV_AR2425 },
131 { "2417", AR5K_VERSION_MAC, AR5K_SREV_AR2417 },
132 { "xxxxx", AR5K_VERSION_MAC, AR5K_SREV_UNKNOWN },
133 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 },
134 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 },
135 { "5111A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111A },
136 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 },
137 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 },
138 { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A },
139 { "5112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112B },
140 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 },
141 { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A },
142 { "2112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112B },
143 { "2413", AR5K_VERSION_RAD, AR5K_SREV_RAD_2413 },
144 { "5413", AR5K_VERSION_RAD, AR5K_SREV_RAD_5413 },
145 { "2316", AR5K_VERSION_RAD, AR5K_SREV_RAD_2316 },
146 { "2317", AR5K_VERSION_RAD, AR5K_SREV_RAD_2317 },
147 { "5424", AR5K_VERSION_RAD, AR5K_SREV_RAD_5424 },
148 { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 },
149 { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN },
152 static const struct ieee80211_rate ath5k_rates[] = {
154 .hw_value = ATH5K_RATE_CODE_1M, },
156 .hw_value = ATH5K_RATE_CODE_2M,
157 .hw_value_short = ATH5K_RATE_CODE_2M | AR5K_SET_SHORT_PREAMBLE,
158 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
160 .hw_value = ATH5K_RATE_CODE_5_5M,
161 .hw_value_short = ATH5K_RATE_CODE_5_5M | AR5K_SET_SHORT_PREAMBLE,
162 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
164 .hw_value = ATH5K_RATE_CODE_11M,
165 .hw_value_short = ATH5K_RATE_CODE_11M | AR5K_SET_SHORT_PREAMBLE,
166 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
168 .hw_value = ATH5K_RATE_CODE_6M,
171 .hw_value = ATH5K_RATE_CODE_9M,
174 .hw_value = ATH5K_RATE_CODE_12M,
177 .hw_value = ATH5K_RATE_CODE_18M,
180 .hw_value = ATH5K_RATE_CODE_24M,
183 .hw_value = ATH5K_RATE_CODE_36M,
186 .hw_value = ATH5K_RATE_CODE_48M,
189 .hw_value = ATH5K_RATE_CODE_54M,
194 static inline void ath5k_txbuf_free_skb(struct ath5k_softc *sc,
195 struct ath5k_buf *bf)
200 pci_unmap_single(sc->pdev, bf->skbaddr, bf->skb->len,
202 dev_kfree_skb_any(bf->skb);
205 bf->desc->ds_data = 0;
208 static inline void ath5k_rxbuf_free_skb(struct ath5k_softc *sc,
209 struct ath5k_buf *bf)
211 struct ath5k_hw *ah = sc->ah;
212 struct ath_common *common = ath5k_hw_common(ah);
217 pci_unmap_single(sc->pdev, bf->skbaddr, common->rx_bufsize,
219 dev_kfree_skb_any(bf->skb);
222 bf->desc->ds_data = 0;
226 static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
228 u64 tsf = ath5k_hw_get_tsf64(ah);
230 if ((tsf & 0x7fff) < rstamp)
233 return (tsf & ~0x7fff) | rstamp;
237 ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val)
239 const char *name = "xxxxx";
242 for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
243 if (srev_names[i].sr_type != type)
246 if ((val & 0xf0) == srev_names[i].sr_val)
247 name = srev_names[i].sr_name;
249 if ((val & 0xff) == srev_names[i].sr_val) {
250 name = srev_names[i].sr_name;
257 static unsigned int ath5k_ioread32(void *hw_priv, u32 reg_offset)
259 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv;
260 return ath5k_hw_reg_read(ah, reg_offset);
263 static void ath5k_iowrite32(void *hw_priv, u32 val, u32 reg_offset)
265 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv;
266 ath5k_hw_reg_write(ah, val, reg_offset);
269 static const struct ath_ops ath5k_common_ops = {
270 .read = ath5k_ioread32,
271 .write = ath5k_iowrite32,
274 /***********************\
275 * Driver Initialization *
276 \***********************/
278 static int ath5k_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request)
280 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
281 struct ath5k_softc *sc = hw->priv;
282 struct ath_regulatory *regulatory = ath5k_hw_regulatory(sc->ah);
284 return ath_reg_notifier_apply(wiphy, request, regulatory);
287 /********************\
288 * Channel/mode setup *
289 \********************/
292 * Convert IEEE channel number to MHz frequency.
295 ath5k_ieee2mhz(short chan)
297 if (chan <= 14 || chan >= 27)
298 return ieee80211chan2mhz(chan);
300 return 2212 + chan * 20;
304 * Returns true for the channel numbers used without all_channels modparam.
306 static bool ath5k_is_standard_channel(short chan)
308 return ((chan <= 14) ||
310 ((chan & 3) == 0 && chan >= 36 && chan <= 64) ||
312 ((chan & 3) == 0 && chan >= 100 && chan <= 140) ||
314 ((chan & 3) == 1 && chan >= 149 && chan <= 165));
318 ath5k_copy_channels(struct ath5k_hw *ah,
319 struct ieee80211_channel *channels,
323 unsigned int i, count, size, chfreq, freq, ch;
325 if (!test_bit(mode, ah->ah_modes))
330 case AR5K_MODE_11A_TURBO:
331 /* 1..220, but 2GHz frequencies are filtered by check_channel */
333 chfreq = CHANNEL_5GHZ;
337 case AR5K_MODE_11G_TURBO:
339 chfreq = CHANNEL_2GHZ;
342 ATH5K_WARN(ah->ah_sc, "bad mode, not copying channels\n");
346 for (i = 0, count = 0; i < size && max > 0; i++) {
348 freq = ath5k_ieee2mhz(ch);
350 /* Check if channel is supported by the chipset */
351 if (!ath5k_channel_ok(ah, freq, chfreq))
354 if (!modparam_all_channels && !ath5k_is_standard_channel(ch))
357 /* Write channel info and increment counter */
358 channels[count].center_freq = freq;
359 channels[count].band = (chfreq == CHANNEL_2GHZ) ?
360 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
364 channels[count].hw_value = chfreq | CHANNEL_OFDM;
366 case AR5K_MODE_11A_TURBO:
367 case AR5K_MODE_11G_TURBO:
368 channels[count].hw_value = chfreq |
369 CHANNEL_OFDM | CHANNEL_TURBO;
372 channels[count].hw_value = CHANNEL_B;
383 ath5k_setup_rate_idx(struct ath5k_softc *sc, struct ieee80211_supported_band *b)
387 for (i = 0; i < AR5K_MAX_RATES; i++)
388 sc->rate_idx[b->band][i] = -1;
390 for (i = 0; i < b->n_bitrates; i++) {
391 sc->rate_idx[b->band][b->bitrates[i].hw_value] = i;
392 if (b->bitrates[i].hw_value_short)
393 sc->rate_idx[b->band][b->bitrates[i].hw_value_short] = i;
398 ath5k_setup_bands(struct ieee80211_hw *hw)
400 struct ath5k_softc *sc = hw->priv;
401 struct ath5k_hw *ah = sc->ah;
402 struct ieee80211_supported_band *sband;
403 int max_c, count_c = 0;
406 BUILD_BUG_ON(ARRAY_SIZE(sc->sbands) < IEEE80211_NUM_BANDS);
407 max_c = ARRAY_SIZE(sc->channels);
410 sband = &sc->sbands[IEEE80211_BAND_2GHZ];
411 sband->band = IEEE80211_BAND_2GHZ;
412 sband->bitrates = &sc->rates[IEEE80211_BAND_2GHZ][0];
414 if (test_bit(AR5K_MODE_11G, sc->ah->ah_capabilities.cap_mode)) {
416 memcpy(sband->bitrates, &ath5k_rates[0],
417 sizeof(struct ieee80211_rate) * 12);
418 sband->n_bitrates = 12;
420 sband->channels = sc->channels;
421 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
422 AR5K_MODE_11G, max_c);
424 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
425 count_c = sband->n_channels;
427 } else if (test_bit(AR5K_MODE_11B, sc->ah->ah_capabilities.cap_mode)) {
429 memcpy(sband->bitrates, &ath5k_rates[0],
430 sizeof(struct ieee80211_rate) * 4);
431 sband->n_bitrates = 4;
433 /* 5211 only supports B rates and uses 4bit rate codes
434 * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B)
437 if (ah->ah_version == AR5K_AR5211) {
438 for (i = 0; i < 4; i++) {
439 sband->bitrates[i].hw_value =
440 sband->bitrates[i].hw_value & 0xF;
441 sband->bitrates[i].hw_value_short =
442 sband->bitrates[i].hw_value_short & 0xF;
446 sband->channels = sc->channels;
447 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
448 AR5K_MODE_11B, max_c);
450 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
451 count_c = sband->n_channels;
454 ath5k_setup_rate_idx(sc, sband);
456 /* 5GHz band, A mode */
457 if (test_bit(AR5K_MODE_11A, sc->ah->ah_capabilities.cap_mode)) {
458 sband = &sc->sbands[IEEE80211_BAND_5GHZ];
459 sband->band = IEEE80211_BAND_5GHZ;
460 sband->bitrates = &sc->rates[IEEE80211_BAND_5GHZ][0];
462 memcpy(sband->bitrates, &ath5k_rates[4],
463 sizeof(struct ieee80211_rate) * 8);
464 sband->n_bitrates = 8;
466 sband->channels = &sc->channels[count_c];
467 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
468 AR5K_MODE_11A, max_c);
470 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband;
472 ath5k_setup_rate_idx(sc, sband);
474 ath5k_debug_dump_bands(sc);
480 * Set/change channels. We always reset the chip.
481 * To accomplish this we must first cleanup any pending DMA,
482 * then restart stuff after a la ath5k_init.
484 * Called with sc->lock.
487 ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan)
489 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
490 "channel set, resetting (%u -> %u MHz)\n",
491 sc->curchan->center_freq, chan->center_freq);
494 * To switch channels clear any pending DMA operations;
495 * wait long enough for the RX fifo to drain, reset the
496 * hardware at the new frequency, and then re-enable
497 * the relevant bits of the h/w.
499 return ath5k_reset(sc, chan);
503 ath5k_setcurmode(struct ath5k_softc *sc, unsigned int mode)
507 if (mode == AR5K_MODE_11A) {
508 sc->curband = &sc->sbands[IEEE80211_BAND_5GHZ];
510 sc->curband = &sc->sbands[IEEE80211_BAND_2GHZ];
514 struct ath_vif_iter_data {
515 const u8 *hw_macaddr;
517 u8 active_mac[ETH_ALEN]; /* first active MAC */
518 bool need_set_hw_addr;
521 enum nl80211_iftype opmode;
524 static void ath_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
526 struct ath_vif_iter_data *iter_data = data;
528 struct ath5k_vif *avf = (void *)vif->drv_priv;
530 if (iter_data->hw_macaddr)
531 for (i = 0; i < ETH_ALEN; i++)
532 iter_data->mask[i] &=
533 ~(iter_data->hw_macaddr[i] ^ mac[i]);
535 if (!iter_data->found_active) {
536 iter_data->found_active = true;
537 memcpy(iter_data->active_mac, mac, ETH_ALEN);
540 if (iter_data->need_set_hw_addr && iter_data->hw_macaddr)
541 if (compare_ether_addr(iter_data->hw_macaddr, mac) == 0)
542 iter_data->need_set_hw_addr = false;
544 if (!iter_data->any_assoc) {
546 iter_data->any_assoc = true;
549 /* Calculate combined mode - when APs are active, operate in AP mode.
550 * Otherwise use the mode of the new interface. This can currently
551 * only deal with combinations of APs and STAs. Only one ad-hoc
552 * interfaces is allowed.
554 if (avf->opmode == NL80211_IFTYPE_AP)
555 iter_data->opmode = NL80211_IFTYPE_AP;
557 if (iter_data->opmode == NL80211_IFTYPE_UNSPECIFIED)
558 iter_data->opmode = avf->opmode;
561 static void ath5k_update_bssid_mask_and_opmode(struct ath5k_softc *sc,
562 struct ieee80211_vif *vif)
564 struct ath_common *common = ath5k_hw_common(sc->ah);
565 struct ath_vif_iter_data iter_data;
568 * Use the hardware MAC address as reference, the hardware uses it
569 * together with the BSSID mask when matching addresses.
571 iter_data.hw_macaddr = common->macaddr;
572 memset(&iter_data.mask, 0xff, ETH_ALEN);
573 iter_data.found_active = false;
574 iter_data.need_set_hw_addr = true;
575 iter_data.opmode = NL80211_IFTYPE_UNSPECIFIED;
578 ath_vif_iter(&iter_data, vif->addr, vif);
580 /* Get list of all active MAC addresses */
581 ieee80211_iterate_active_interfaces_atomic(sc->hw, ath_vif_iter,
583 memcpy(sc->bssidmask, iter_data.mask, ETH_ALEN);
585 sc->opmode = iter_data.opmode;
586 if (sc->opmode == NL80211_IFTYPE_UNSPECIFIED)
587 /* Nothing active, default to station mode */
588 sc->opmode = NL80211_IFTYPE_STATION;
590 ath5k_hw_set_opmode(sc->ah, sc->opmode);
591 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "mode setup opmode %d (%s)\n",
592 sc->opmode, ath_opmode_to_string(sc->opmode));
594 if (iter_data.need_set_hw_addr && iter_data.found_active)
595 ath5k_hw_set_lladdr(sc->ah, iter_data.active_mac);
597 if (ath5k_hw_hasbssidmask(sc->ah))
598 ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask);
602 ath5k_mode_setup(struct ath5k_softc *sc, struct ieee80211_vif *vif)
604 struct ath5k_hw *ah = sc->ah;
607 /* configure rx filter */
608 rfilt = sc->filter_flags;
609 ath5k_hw_set_rx_filter(ah, rfilt);
610 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
612 ath5k_update_bssid_mask_and_opmode(sc, vif);
616 ath5k_hw_to_driver_rix(struct ath5k_softc *sc, int hw_rix)
620 /* return base rate on errors */
621 if (WARN(hw_rix < 0 || hw_rix >= AR5K_MAX_RATES,
622 "hw_rix out of bounds: %x\n", hw_rix))
625 rix = sc->rate_idx[sc->curband->band][hw_rix];
626 if (WARN(rix < 0, "invalid hw_rix: %x\n", hw_rix))
637 struct sk_buff *ath5k_rx_skb_alloc(struct ath5k_softc *sc, dma_addr_t *skb_addr)
639 struct ath_common *common = ath5k_hw_common(sc->ah);
643 * Allocate buffer with headroom_needed space for the
644 * fake physical layer header at the start.
646 skb = ath_rxbuf_alloc(common,
651 ATH5K_ERR(sc, "can't alloc skbuff of size %u\n",
656 *skb_addr = pci_map_single(sc->pdev,
657 skb->data, common->rx_bufsize,
659 if (unlikely(pci_dma_mapping_error(sc->pdev, *skb_addr))) {
660 ATH5K_ERR(sc, "%s: DMA mapping failed\n", __func__);
668 ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
670 struct ath5k_hw *ah = sc->ah;
671 struct sk_buff *skb = bf->skb;
672 struct ath5k_desc *ds;
676 skb = ath5k_rx_skb_alloc(sc, &bf->skbaddr);
683 * Setup descriptors. For receive we always terminate
684 * the descriptor list with a self-linked entry so we'll
685 * not get overrun under high load (as can happen with a
686 * 5212 when ANI processing enables PHY error frames).
688 * To ensure the last descriptor is self-linked we create
689 * each descriptor as self-linked and add it to the end. As
690 * each additional descriptor is added the previous self-linked
691 * entry is "fixed" naturally. This should be safe even
692 * if DMA is happening. When processing RX interrupts we
693 * never remove/process the last, self-linked, entry on the
694 * descriptor list. This ensures the hardware always has
695 * someplace to write a new frame.
698 ds->ds_link = bf->daddr; /* link to self */
699 ds->ds_data = bf->skbaddr;
700 ret = ath5k_hw_setup_rx_desc(ah, ds, ah->common.rx_bufsize, 0);
702 ATH5K_ERR(sc, "%s: could not setup RX desc\n", __func__);
706 if (sc->rxlink != NULL)
707 *sc->rxlink = bf->daddr;
708 sc->rxlink = &ds->ds_link;
712 static enum ath5k_pkt_type get_hw_packet_type(struct sk_buff *skb)
714 struct ieee80211_hdr *hdr;
715 enum ath5k_pkt_type htype;
718 hdr = (struct ieee80211_hdr *)skb->data;
719 fc = hdr->frame_control;
721 if (ieee80211_is_beacon(fc))
722 htype = AR5K_PKT_TYPE_BEACON;
723 else if (ieee80211_is_probe_resp(fc))
724 htype = AR5K_PKT_TYPE_PROBE_RESP;
725 else if (ieee80211_is_atim(fc))
726 htype = AR5K_PKT_TYPE_ATIM;
727 else if (ieee80211_is_pspoll(fc))
728 htype = AR5K_PKT_TYPE_PSPOLL;
730 htype = AR5K_PKT_TYPE_NORMAL;
736 ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf,
737 struct ath5k_txq *txq, int padsize)
739 struct ath5k_hw *ah = sc->ah;
740 struct ath5k_desc *ds = bf->desc;
741 struct sk_buff *skb = bf->skb;
742 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
743 unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID;
744 struct ieee80211_rate *rate;
745 unsigned int mrr_rate[3], mrr_tries[3];
752 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
755 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
758 rate = ieee80211_get_tx_rate(sc->hw, info);
764 if (info->flags & IEEE80211_TX_CTL_NO_ACK)
765 flags |= AR5K_TXDESC_NOACK;
767 rc_flags = info->control.rates[0].flags;
768 hw_rate = (rc_flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) ?
769 rate->hw_value_short : rate->hw_value;
773 /* FIXME: If we are in g mode and rate is a CCK rate
774 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
775 * from tx power (value is in dB units already) */
776 if (info->control.hw_key) {
777 keyidx = info->control.hw_key->hw_key_idx;
778 pktlen += info->control.hw_key->icv_len;
780 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
781 flags |= AR5K_TXDESC_RTSENA;
782 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
783 duration = le16_to_cpu(ieee80211_rts_duration(sc->hw,
784 info->control.vif, pktlen, info));
786 if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
787 flags |= AR5K_TXDESC_CTSENA;
788 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
789 duration = le16_to_cpu(ieee80211_ctstoself_duration(sc->hw,
790 info->control.vif, pktlen, info));
792 ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
793 ieee80211_get_hdrlen_from_skb(skb), padsize,
794 get_hw_packet_type(skb),
795 (sc->power_level * 2),
797 info->control.rates[0].count, keyidx, ah->ah_tx_ant, flags,
802 memset(mrr_rate, 0, sizeof(mrr_rate));
803 memset(mrr_tries, 0, sizeof(mrr_tries));
804 for (i = 0; i < 3; i++) {
805 rate = ieee80211_get_alt_retry_rate(sc->hw, info, i);
809 mrr_rate[i] = rate->hw_value;
810 mrr_tries[i] = info->control.rates[i + 1].count;
813 ath5k_hw_setup_mrr_tx_desc(ah, ds,
814 mrr_rate[0], mrr_tries[0],
815 mrr_rate[1], mrr_tries[1],
816 mrr_rate[2], mrr_tries[2]);
819 ds->ds_data = bf->skbaddr;
821 spin_lock_bh(&txq->lock);
822 list_add_tail(&bf->list, &txq->q);
824 if (txq->link == NULL) /* is this first packet? */
825 ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr);
826 else /* no, so only link it */
827 *txq->link = bf->daddr;
829 txq->link = &ds->ds_link;
830 ath5k_hw_start_tx_dma(ah, txq->qnum);
832 spin_unlock_bh(&txq->lock);
836 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
840 /*******************\
841 * Descriptors setup *
842 \*******************/
845 ath5k_desc_alloc(struct ath5k_softc *sc, struct pci_dev *pdev)
847 struct ath5k_desc *ds;
848 struct ath5k_buf *bf;
853 /* allocate descriptors */
854 sc->desc_len = sizeof(struct ath5k_desc) *
855 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
856 sc->desc = pci_alloc_consistent(pdev, sc->desc_len, &sc->desc_daddr);
857 if (sc->desc == NULL) {
858 ATH5K_ERR(sc, "can't allocate descriptors\n");
864 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
865 ds, sc->desc_len, (unsigned long long)sc->desc_daddr);
867 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
868 sizeof(struct ath5k_buf), GFP_KERNEL);
870 ATH5K_ERR(sc, "can't allocate bufptr\n");
876 INIT_LIST_HEAD(&sc->rxbuf);
877 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
880 list_add_tail(&bf->list, &sc->rxbuf);
883 INIT_LIST_HEAD(&sc->txbuf);
884 sc->txbuf_len = ATH_TXBUF;
885 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++,
889 list_add_tail(&bf->list, &sc->txbuf);
893 INIT_LIST_HEAD(&sc->bcbuf);
894 for (i = 0; i < ATH_BCBUF; i++, bf++, ds++, da += sizeof(*ds)) {
897 list_add_tail(&bf->list, &sc->bcbuf);
902 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
909 ath5k_desc_free(struct ath5k_softc *sc, struct pci_dev *pdev)
911 struct ath5k_buf *bf;
913 list_for_each_entry(bf, &sc->txbuf, list)
914 ath5k_txbuf_free_skb(sc, bf);
915 list_for_each_entry(bf, &sc->rxbuf, list)
916 ath5k_rxbuf_free_skb(sc, bf);
917 list_for_each_entry(bf, &sc->bcbuf, list)
918 ath5k_txbuf_free_skb(sc, bf);
920 /* Free memory associated with all descriptors */
921 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
934 static struct ath5k_txq *
935 ath5k_txq_setup(struct ath5k_softc *sc,
936 int qtype, int subtype)
938 struct ath5k_hw *ah = sc->ah;
939 struct ath5k_txq *txq;
940 struct ath5k_txq_info qi = {
941 .tqi_subtype = subtype,
942 /* XXX: default values not correct for B and XR channels,
944 .tqi_aifs = AR5K_TUNE_AIFS,
945 .tqi_cw_min = AR5K_TUNE_CWMIN,
946 .tqi_cw_max = AR5K_TUNE_CWMAX
951 * Enable interrupts only for EOL and DESC conditions.
952 * We mark tx descriptors to receive a DESC interrupt
953 * when a tx queue gets deep; otherwise we wait for the
954 * EOL to reap descriptors. Note that this is done to
955 * reduce interrupt load and this only defers reaping
956 * descriptors, never transmitting frames. Aside from
957 * reducing interrupts this also permits more concurrency.
958 * The only potential downside is if the tx queue backs
959 * up in which case the top half of the kernel may backup
960 * due to a lack of tx descriptors.
962 qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
963 AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
964 qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi);
967 * NB: don't print a message, this happens
968 * normally on parts with too few tx queues
970 return ERR_PTR(qnum);
972 if (qnum >= ARRAY_SIZE(sc->txqs)) {
973 ATH5K_ERR(sc, "hw qnum %u out of range, max %tu!\n",
974 qnum, ARRAY_SIZE(sc->txqs));
975 ath5k_hw_release_tx_queue(ah, qnum);
976 return ERR_PTR(-EINVAL);
978 txq = &sc->txqs[qnum];
982 INIT_LIST_HEAD(&txq->q);
983 spin_lock_init(&txq->lock);
986 txq->txq_poll_mark = false;
989 return &sc->txqs[qnum];
993 ath5k_beaconq_setup(struct ath5k_hw *ah)
995 struct ath5k_txq_info qi = {
996 /* XXX: default values not correct for B and XR channels,
998 .tqi_aifs = AR5K_TUNE_AIFS,
999 .tqi_cw_min = AR5K_TUNE_CWMIN,
1000 .tqi_cw_max = AR5K_TUNE_CWMAX,
1001 /* NB: for dynamic turbo, don't enable any other interrupts */
1002 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE
1005 return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi);
1009 ath5k_beaconq_config(struct ath5k_softc *sc)
1011 struct ath5k_hw *ah = sc->ah;
1012 struct ath5k_txq_info qi;
1015 ret = ath5k_hw_get_tx_queueprops(ah, sc->bhalq, &qi);
1019 if (sc->opmode == NL80211_IFTYPE_AP ||
1020 sc->opmode == NL80211_IFTYPE_MESH_POINT) {
1022 * Always burst out beacon and CAB traffic
1023 * (aifs = cwmin = cwmax = 0)
1028 } else if (sc->opmode == NL80211_IFTYPE_ADHOC) {
1030 * Adhoc mode; backoff between 0 and (2 * cw_min).
1034 qi.tqi_cw_max = 2 * AR5K_TUNE_CWMIN;
1037 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1038 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
1039 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max);
1041 ret = ath5k_hw_set_tx_queueprops(ah, sc->bhalq, &qi);
1043 ATH5K_ERR(sc, "%s: unable to update parameters for beacon "
1044 "hardware queue!\n", __func__);
1047 ret = ath5k_hw_reset_tx_queue(ah, sc->bhalq); /* push to h/w */
1051 /* reconfigure cabq with ready time to 80% of beacon_interval */
1052 ret = ath5k_hw_get_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi);
1056 qi.tqi_ready_time = (sc->bintval * 80) / 100;
1057 ret = ath5k_hw_set_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi);
1061 ret = ath5k_hw_reset_tx_queue(ah, AR5K_TX_QUEUE_ID_CAB);
1067 ath5k_txq_drainq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1069 struct ath5k_buf *bf, *bf0;
1072 * NB: this assumes output has been stopped and
1073 * we do not need to block ath5k_tx_tasklet
1075 spin_lock_bh(&txq->lock);
1076 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1077 ath5k_debug_printtxbuf(sc, bf);
1079 ath5k_txbuf_free_skb(sc, bf);
1081 spin_lock_bh(&sc->txbuflock);
1082 list_move_tail(&bf->list, &sc->txbuf);
1085 spin_unlock_bh(&sc->txbuflock);
1088 txq->txq_poll_mark = false;
1089 spin_unlock_bh(&txq->lock);
1093 * Drain the transmit queues and reclaim resources.
1096 ath5k_txq_cleanup(struct ath5k_softc *sc)
1098 struct ath5k_hw *ah = sc->ah;
1101 /* XXX return value */
1102 if (likely(!test_bit(ATH_STAT_INVALID, sc->status))) {
1103 /* don't touch the hardware if marked invalid */
1104 ath5k_hw_stop_tx_dma(ah, sc->bhalq);
1105 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "beacon queue %x\n",
1106 ath5k_hw_get_txdp(ah, sc->bhalq));
1107 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1108 if (sc->txqs[i].setup) {
1109 ath5k_hw_stop_tx_dma(ah, sc->txqs[i].qnum);
1110 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "txq [%u] %x, "
1113 ath5k_hw_get_txdp(ah,
1119 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1120 if (sc->txqs[i].setup)
1121 ath5k_txq_drainq(sc, &sc->txqs[i]);
1125 ath5k_txq_release(struct ath5k_softc *sc)
1127 struct ath5k_txq *txq = sc->txqs;
1130 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++)
1132 ath5k_hw_release_tx_queue(sc->ah, txq->qnum);
1143 * Enable the receive h/w following a reset.
1146 ath5k_rx_start(struct ath5k_softc *sc)
1148 struct ath5k_hw *ah = sc->ah;
1149 struct ath_common *common = ath5k_hw_common(ah);
1150 struct ath5k_buf *bf;
1153 common->rx_bufsize = roundup(IEEE80211_MAX_FRAME_LEN, common->cachelsz);
1155 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "cachelsz %u rx_bufsize %u\n",
1156 common->cachelsz, common->rx_bufsize);
1158 spin_lock_bh(&sc->rxbuflock);
1160 list_for_each_entry(bf, &sc->rxbuf, list) {
1161 ret = ath5k_rxbuf_setup(sc, bf);
1163 spin_unlock_bh(&sc->rxbuflock);
1167 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1168 ath5k_hw_set_rxdp(ah, bf->daddr);
1169 spin_unlock_bh(&sc->rxbuflock);
1171 ath5k_hw_start_rx_dma(ah); /* enable recv descriptors */
1172 ath5k_mode_setup(sc, NULL); /* set filters, etc. */
1173 ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */
1181 * Disable the receive h/w in preparation for a reset.
1184 ath5k_rx_stop(struct ath5k_softc *sc)
1186 struct ath5k_hw *ah = sc->ah;
1188 ath5k_hw_stop_rx_pcu(ah); /* disable PCU */
1189 ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */
1190 ath5k_hw_stop_rx_dma(ah); /* disable DMA engine */
1192 ath5k_debug_printrxbuffs(sc, ah);
1196 ath5k_rx_decrypted(struct ath5k_softc *sc, struct sk_buff *skb,
1197 struct ath5k_rx_status *rs)
1199 struct ath5k_hw *ah = sc->ah;
1200 struct ath_common *common = ath5k_hw_common(ah);
1201 struct ieee80211_hdr *hdr = (void *)skb->data;
1202 unsigned int keyix, hlen;
1204 if (!(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1205 rs->rs_keyix != AR5K_RXKEYIX_INVALID)
1206 return RX_FLAG_DECRYPTED;
1208 /* Apparently when a default key is used to decrypt the packet
1209 the hw does not set the index used to decrypt. In such cases
1210 get the index from the packet. */
1211 hlen = ieee80211_hdrlen(hdr->frame_control);
1212 if (ieee80211_has_protected(hdr->frame_control) &&
1213 !(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1214 skb->len >= hlen + 4) {
1215 keyix = skb->data[hlen + 3] >> 6;
1217 if (test_bit(keyix, common->keymap))
1218 return RX_FLAG_DECRYPTED;
1226 ath5k_check_ibss_tsf(struct ath5k_softc *sc, struct sk_buff *skb,
1227 struct ieee80211_rx_status *rxs)
1229 struct ath_common *common = ath5k_hw_common(sc->ah);
1232 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1234 if (ieee80211_is_beacon(mgmt->frame_control) &&
1235 le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS &&
1236 memcmp(mgmt->bssid, common->curbssid, ETH_ALEN) == 0) {
1238 * Received an IBSS beacon with the same BSSID. Hardware *must*
1239 * have updated the local TSF. We have to work around various
1240 * hardware bugs, though...
1242 tsf = ath5k_hw_get_tsf64(sc->ah);
1243 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp);
1244 hw_tu = TSF_TO_TU(tsf);
1246 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1247 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
1248 (unsigned long long)bc_tstamp,
1249 (unsigned long long)rxs->mactime,
1250 (unsigned long long)(rxs->mactime - bc_tstamp),
1251 (unsigned long long)tsf);
1254 * Sometimes the HW will give us a wrong tstamp in the rx
1255 * status, causing the timestamp extension to go wrong.
1256 * (This seems to happen especially with beacon frames bigger
1257 * than 78 byte (incl. FCS))
1258 * But we know that the receive timestamp must be later than the
1259 * timestamp of the beacon since HW must have synced to that.
1261 * NOTE: here we assume mactime to be after the frame was
1262 * received, not like mac80211 which defines it at the start.
1264 if (bc_tstamp > rxs->mactime) {
1265 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1266 "fixing mactime from %llx to %llx\n",
1267 (unsigned long long)rxs->mactime,
1268 (unsigned long long)tsf);
1273 * Local TSF might have moved higher than our beacon timers,
1274 * in that case we have to update them to continue sending
1275 * beacons. This also takes care of synchronizing beacon sending
1276 * times with other stations.
1278 if (hw_tu >= sc->nexttbtt)
1279 ath5k_beacon_update_timers(sc, bc_tstamp);
1281 /* Check if the beacon timers are still correct, because a TSF
1282 * update might have created a window between them - for a
1283 * longer description see the comment of this function: */
1284 if (!ath5k_hw_check_beacon_timers(sc->ah, sc->bintval)) {
1285 ath5k_beacon_update_timers(sc, bc_tstamp);
1286 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1287 "fixed beacon timers after beacon receive\n");
1293 ath5k_update_beacon_rssi(struct ath5k_softc *sc, struct sk_buff *skb, int rssi)
1295 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1296 struct ath5k_hw *ah = sc->ah;
1297 struct ath_common *common = ath5k_hw_common(ah);
1299 /* only beacons from our BSSID */
1300 if (!ieee80211_is_beacon(mgmt->frame_control) ||
1301 memcmp(mgmt->bssid, common->curbssid, ETH_ALEN) != 0)
1304 ewma_add(&ah->ah_beacon_rssi_avg, rssi);
1306 /* in IBSS mode we should keep RSSI statistics per neighbour */
1307 /* le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS */
1311 * Compute padding position. skb must contain an IEEE 802.11 frame
1313 static int ath5k_common_padpos(struct sk_buff *skb)
1315 struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data;
1316 __le16 frame_control = hdr->frame_control;
1319 if (ieee80211_has_a4(frame_control)) {
1322 if (ieee80211_is_data_qos(frame_control)) {
1323 padpos += IEEE80211_QOS_CTL_LEN;
1330 * This function expects an 802.11 frame and returns the number of
1331 * bytes added, or -1 if we don't have enough header room.
1333 static int ath5k_add_padding(struct sk_buff *skb)
1335 int padpos = ath5k_common_padpos(skb);
1336 int padsize = padpos & 3;
1338 if (padsize && skb->len>padpos) {
1340 if (skb_headroom(skb) < padsize)
1343 skb_push(skb, padsize);
1344 memmove(skb->data, skb->data+padsize, padpos);
1352 * The MAC header is padded to have 32-bit boundary if the
1353 * packet payload is non-zero. The general calculation for
1354 * padsize would take into account odd header lengths:
1355 * padsize = 4 - (hdrlen & 3); however, since only
1356 * even-length headers are used, padding can only be 0 or 2
1357 * bytes and we can optimize this a bit. We must not try to
1358 * remove padding from short control frames that do not have a
1361 * This function expects an 802.11 frame and returns the number of
1364 static int ath5k_remove_padding(struct sk_buff *skb)
1366 int padpos = ath5k_common_padpos(skb);
1367 int padsize = padpos & 3;
1369 if (padsize && skb->len>=padpos+padsize) {
1370 memmove(skb->data + padsize, skb->data, padpos);
1371 skb_pull(skb, padsize);
1379 ath5k_receive_frame(struct ath5k_softc *sc, struct sk_buff *skb,
1380 struct ath5k_rx_status *rs)
1382 struct ieee80211_rx_status *rxs;
1384 ath5k_remove_padding(skb);
1386 rxs = IEEE80211_SKB_RXCB(skb);
1389 if (unlikely(rs->rs_status & AR5K_RXERR_MIC))
1390 rxs->flag |= RX_FLAG_MMIC_ERROR;
1393 * always extend the mac timestamp, since this information is
1394 * also needed for proper IBSS merging.
1396 * XXX: it might be too late to do it here, since rs_tstamp is
1397 * 15bit only. that means TSF extension has to be done within
1398 * 32768usec (about 32ms). it might be necessary to move this to
1399 * the interrupt handler, like it is done in madwifi.
1401 * Unfortunately we don't know when the hardware takes the rx
1402 * timestamp (beginning of phy frame, data frame, end of rx?).
1403 * The only thing we know is that it is hardware specific...
1404 * On AR5213 it seems the rx timestamp is at the end of the
1405 * frame, but i'm not sure.
1407 * NOTE: mac80211 defines mactime at the beginning of the first
1408 * data symbol. Since we don't have any time references it's
1409 * impossible to comply to that. This affects IBSS merge only
1410 * right now, so it's not too bad...
1412 rxs->mactime = ath5k_extend_tsf(sc->ah, rs->rs_tstamp);
1413 rxs->flag |= RX_FLAG_TSFT;
1415 rxs->freq = sc->curchan->center_freq;
1416 rxs->band = sc->curband->band;
1418 rxs->signal = sc->ah->ah_noise_floor + rs->rs_rssi;
1420 rxs->antenna = rs->rs_antenna;
1422 if (rs->rs_antenna > 0 && rs->rs_antenna < 5)
1423 sc->stats.antenna_rx[rs->rs_antenna]++;
1425 sc->stats.antenna_rx[0]++; /* invalid */
1427 rxs->rate_idx = ath5k_hw_to_driver_rix(sc, rs->rs_rate);
1428 rxs->flag |= ath5k_rx_decrypted(sc, skb, rs);
1430 if (rxs->rate_idx >= 0 && rs->rs_rate ==
1431 sc->curband->bitrates[rxs->rate_idx].hw_value_short)
1432 rxs->flag |= RX_FLAG_SHORTPRE;
1434 ath5k_debug_dump_skb(sc, skb, "RX ", 0);
1436 ath5k_update_beacon_rssi(sc, skb, rs->rs_rssi);
1438 /* check beacons in IBSS mode */
1439 if (sc->opmode == NL80211_IFTYPE_ADHOC)
1440 ath5k_check_ibss_tsf(sc, skb, rxs);
1442 ieee80211_rx(sc->hw, skb);
1445 /** ath5k_frame_receive_ok() - Do we want to receive this frame or not?
1447 * Check if we want to further process this frame or not. Also update
1448 * statistics. Return true if we want this frame, false if not.
1451 ath5k_receive_frame_ok(struct ath5k_softc *sc, struct ath5k_rx_status *rs)
1453 sc->stats.rx_all_count++;
1454 sc->stats.rx_bytes_count += rs->rs_datalen;
1456 if (unlikely(rs->rs_status)) {
1457 if (rs->rs_status & AR5K_RXERR_CRC)
1458 sc->stats.rxerr_crc++;
1459 if (rs->rs_status & AR5K_RXERR_FIFO)
1460 sc->stats.rxerr_fifo++;
1461 if (rs->rs_status & AR5K_RXERR_PHY) {
1462 sc->stats.rxerr_phy++;
1463 if (rs->rs_phyerr > 0 && rs->rs_phyerr < 32)
1464 sc->stats.rxerr_phy_code[rs->rs_phyerr]++;
1467 if (rs->rs_status & AR5K_RXERR_DECRYPT) {
1469 * Decrypt error. If the error occurred
1470 * because there was no hardware key, then
1471 * let the frame through so the upper layers
1472 * can process it. This is necessary for 5210
1473 * parts which have no way to setup a ``clear''
1476 * XXX do key cache faulting
1478 sc->stats.rxerr_decrypt++;
1479 if (rs->rs_keyix == AR5K_RXKEYIX_INVALID &&
1480 !(rs->rs_status & AR5K_RXERR_CRC))
1483 if (rs->rs_status & AR5K_RXERR_MIC) {
1484 sc->stats.rxerr_mic++;
1488 /* reject any frames with non-crypto errors */
1489 if (rs->rs_status & ~(AR5K_RXERR_DECRYPT))
1493 if (unlikely(rs->rs_more)) {
1494 sc->stats.rxerr_jumbo++;
1501 ath5k_tasklet_rx(unsigned long data)
1503 struct ath5k_rx_status rs = {};
1504 struct sk_buff *skb, *next_skb;
1505 dma_addr_t next_skb_addr;
1506 struct ath5k_softc *sc = (void *)data;
1507 struct ath5k_hw *ah = sc->ah;
1508 struct ath_common *common = ath5k_hw_common(ah);
1509 struct ath5k_buf *bf;
1510 struct ath5k_desc *ds;
1513 spin_lock(&sc->rxbuflock);
1514 if (list_empty(&sc->rxbuf)) {
1515 ATH5K_WARN(sc, "empty rx buf pool\n");
1519 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1520 BUG_ON(bf->skb == NULL);
1524 /* bail if HW is still using self-linked descriptor */
1525 if (ath5k_hw_get_rxdp(sc->ah) == bf->daddr)
1528 ret = sc->ah->ah_proc_rx_desc(sc->ah, ds, &rs);
1529 if (unlikely(ret == -EINPROGRESS))
1531 else if (unlikely(ret)) {
1532 ATH5K_ERR(sc, "error in processing rx descriptor\n");
1533 sc->stats.rxerr_proc++;
1537 if (ath5k_receive_frame_ok(sc, &rs)) {
1538 next_skb = ath5k_rx_skb_alloc(sc, &next_skb_addr);
1541 * If we can't replace bf->skb with a new skb under
1542 * memory pressure, just skip this packet
1547 pci_unmap_single(sc->pdev, bf->skbaddr,
1549 PCI_DMA_FROMDEVICE);
1551 skb_put(skb, rs.rs_datalen);
1553 ath5k_receive_frame(sc, skb, &rs);
1556 bf->skbaddr = next_skb_addr;
1559 list_move_tail(&bf->list, &sc->rxbuf);
1560 } while (ath5k_rxbuf_setup(sc, bf) == 0);
1562 spin_unlock(&sc->rxbuflock);
1570 static int ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb,
1571 struct ath5k_txq *txq)
1573 struct ath5k_softc *sc = hw->priv;
1574 struct ath5k_buf *bf;
1575 unsigned long flags;
1578 ath5k_debug_dump_skb(sc, skb, "TX ", 1);
1581 * The hardware expects the header padded to 4 byte boundaries.
1582 * If this is not the case, we add the padding after the header.
1584 padsize = ath5k_add_padding(skb);
1586 ATH5K_ERR(sc, "tx hdrlen not %%4: not enough"
1587 " headroom to pad");
1591 if (txq->txq_len >= ATH5K_TXQ_LEN_MAX)
1592 ieee80211_stop_queue(hw, txq->qnum);
1594 spin_lock_irqsave(&sc->txbuflock, flags);
1595 if (list_empty(&sc->txbuf)) {
1596 ATH5K_ERR(sc, "no further txbuf available, dropping packet\n");
1597 spin_unlock_irqrestore(&sc->txbuflock, flags);
1598 ieee80211_stop_queues(hw);
1601 bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list);
1602 list_del(&bf->list);
1604 if (list_empty(&sc->txbuf))
1605 ieee80211_stop_queues(hw);
1606 spin_unlock_irqrestore(&sc->txbuflock, flags);
1610 if (ath5k_txbuf_setup(sc, bf, txq, padsize)) {
1612 spin_lock_irqsave(&sc->txbuflock, flags);
1613 list_add_tail(&bf->list, &sc->txbuf);
1615 spin_unlock_irqrestore(&sc->txbuflock, flags);
1618 return NETDEV_TX_OK;
1621 dev_kfree_skb_any(skb);
1622 return NETDEV_TX_OK;
1626 ath5k_tx_frame_completed(struct ath5k_softc *sc, struct sk_buff *skb,
1627 struct ath5k_tx_status *ts)
1629 struct ieee80211_tx_info *info;
1632 sc->stats.tx_all_count++;
1633 sc->stats.tx_bytes_count += skb->len;
1634 info = IEEE80211_SKB_CB(skb);
1636 ieee80211_tx_info_clear_status(info);
1637 for (i = 0; i < 4; i++) {
1638 struct ieee80211_tx_rate *r =
1639 &info->status.rates[i];
1641 if (ts->ts_rate[i]) {
1642 r->idx = ath5k_hw_to_driver_rix(sc, ts->ts_rate[i]);
1643 r->count = ts->ts_retry[i];
1650 /* count the successful attempt as well */
1651 info->status.rates[ts->ts_final_idx].count++;
1653 if (unlikely(ts->ts_status)) {
1654 sc->stats.ack_fail++;
1655 if (ts->ts_status & AR5K_TXERR_FILT) {
1656 info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
1657 sc->stats.txerr_filt++;
1659 if (ts->ts_status & AR5K_TXERR_XRETRY)
1660 sc->stats.txerr_retry++;
1661 if (ts->ts_status & AR5K_TXERR_FIFO)
1662 sc->stats.txerr_fifo++;
1664 info->flags |= IEEE80211_TX_STAT_ACK;
1665 info->status.ack_signal = ts->ts_rssi;
1669 * Remove MAC header padding before giving the frame
1672 ath5k_remove_padding(skb);
1674 if (ts->ts_antenna > 0 && ts->ts_antenna < 5)
1675 sc->stats.antenna_tx[ts->ts_antenna]++;
1677 sc->stats.antenna_tx[0]++; /* invalid */
1679 ieee80211_tx_status(sc->hw, skb);
1683 ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1685 struct ath5k_tx_status ts = {};
1686 struct ath5k_buf *bf, *bf0;
1687 struct ath5k_desc *ds;
1688 struct sk_buff *skb;
1691 spin_lock(&txq->lock);
1692 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1694 txq->txq_poll_mark = false;
1696 /* skb might already have been processed last time. */
1697 if (bf->skb != NULL) {
1700 ret = sc->ah->ah_proc_tx_desc(sc->ah, ds, &ts);
1701 if (unlikely(ret == -EINPROGRESS))
1703 else if (unlikely(ret)) {
1705 "error %d while processing "
1706 "queue %u\n", ret, txq->qnum);
1712 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len,
1714 ath5k_tx_frame_completed(sc, skb, &ts);
1718 * It's possible that the hardware can say the buffer is
1719 * completed when it hasn't yet loaded the ds_link from
1720 * host memory and moved on.
1721 * Always keep the last descriptor to avoid HW races...
1723 if (ath5k_hw_get_txdp(sc->ah, txq->qnum) != bf->daddr) {
1724 spin_lock(&sc->txbuflock);
1725 list_move_tail(&bf->list, &sc->txbuf);
1728 spin_unlock(&sc->txbuflock);
1731 spin_unlock(&txq->lock);
1732 if (txq->txq_len < ATH5K_TXQ_LEN_LOW && txq->qnum < 4)
1733 ieee80211_wake_queue(sc->hw, txq->qnum);
1737 ath5k_tasklet_tx(unsigned long data)
1740 struct ath5k_softc *sc = (void *)data;
1742 for (i=0; i < AR5K_NUM_TX_QUEUES; i++)
1743 if (sc->txqs[i].setup && (sc->ah->ah_txq_isr & BIT(i)))
1744 ath5k_tx_processq(sc, &sc->txqs[i]);
1753 * Setup the beacon frame for transmit.
1756 ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1758 struct sk_buff *skb = bf->skb;
1759 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1760 struct ath5k_hw *ah = sc->ah;
1761 struct ath5k_desc *ds;
1765 const int padsize = 0;
1767 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1769 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
1770 "skbaddr %llx\n", skb, skb->data, skb->len,
1771 (unsigned long long)bf->skbaddr);
1772 if (pci_dma_mapping_error(sc->pdev, bf->skbaddr)) {
1773 ATH5K_ERR(sc, "beacon DMA mapping failed\n");
1778 antenna = ah->ah_tx_ant;
1780 flags = AR5K_TXDESC_NOACK;
1781 if (sc->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) {
1782 ds->ds_link = bf->daddr; /* self-linked */
1783 flags |= AR5K_TXDESC_VEOL;
1788 * If we use multiple antennas on AP and use
1789 * the Sectored AP scenario, switch antenna every
1790 * 4 beacons to make sure everybody hears our AP.
1791 * When a client tries to associate, hw will keep
1792 * track of the tx antenna to be used for this client
1793 * automaticaly, based on ACKed packets.
1795 * Note: AP still listens and transmits RTS on the
1796 * default antenna which is supposed to be an omni.
1798 * Note2: On sectored scenarios it's possible to have
1799 * multiple antennas (1 omni -- the default -- and 14
1800 * sectors), so if we choose to actually support this
1801 * mode, we need to allow the user to set how many antennas
1802 * we have and tweak the code below to send beacons
1805 if (ah->ah_ant_mode == AR5K_ANTMODE_SECTOR_AP)
1806 antenna = sc->bsent & 4 ? 2 : 1;
1809 /* FIXME: If we are in g mode and rate is a CCK rate
1810 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
1811 * from tx power (value is in dB units already) */
1812 ds->ds_data = bf->skbaddr;
1813 ret = ah->ah_setup_tx_desc(ah, ds, skb->len,
1814 ieee80211_get_hdrlen_from_skb(skb), padsize,
1815 AR5K_PKT_TYPE_BEACON, (sc->power_level * 2),
1816 ieee80211_get_tx_rate(sc->hw, info)->hw_value,
1817 1, AR5K_TXKEYIX_INVALID,
1818 antenna, flags, 0, 0);
1824 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
1829 * Updates the beacon that is sent by ath5k_beacon_send. For adhoc,
1830 * this is called only once at config_bss time, for AP we do it every
1831 * SWBA interrupt so that the TIM will reflect buffered frames.
1833 * Called with the beacon lock.
1836 ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
1839 struct ath5k_softc *sc = hw->priv;
1840 struct ath5k_vif *avf = (void *)vif->drv_priv;
1841 struct sk_buff *skb;
1843 if (WARN_ON(!vif)) {
1848 skb = ieee80211_beacon_get(hw, vif);
1855 ath5k_debug_dump_skb(sc, skb, "BC ", 1);
1857 ath5k_txbuf_free_skb(sc, avf->bbuf);
1858 avf->bbuf->skb = skb;
1859 ret = ath5k_beacon_setup(sc, avf->bbuf);
1861 avf->bbuf->skb = NULL;
1867 * Transmit a beacon frame at SWBA. Dynamic updates to the
1868 * frame contents are done as needed and the slot time is
1869 * also adjusted based on current state.
1871 * This is called from software irq context (beacontq tasklets)
1872 * or user context from ath5k_beacon_config.
1875 ath5k_beacon_send(struct ath5k_softc *sc)
1877 struct ath5k_hw *ah = sc->ah;
1878 struct ieee80211_vif *vif;
1879 struct ath5k_vif *avf;
1880 struct ath5k_buf *bf;
1881 struct sk_buff *skb;
1883 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "in beacon_send\n");
1886 * Check if the previous beacon has gone out. If
1887 * not, don't don't try to post another: skip this
1888 * period and wait for the next. Missed beacons
1889 * indicate a problem and should not occur. If we
1890 * miss too many consecutive beacons reset the device.
1892 if (unlikely(ath5k_hw_num_tx_pending(ah, sc->bhalq) != 0)) {
1894 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1895 "missed %u consecutive beacons\n", sc->bmisscount);
1896 if (sc->bmisscount > 10) { /* NB: 10 is a guess */
1897 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1898 "stuck beacon time (%u missed)\n",
1900 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
1901 "stuck beacon, resetting\n");
1902 ieee80211_queue_work(sc->hw, &sc->reset_work);
1906 if (unlikely(sc->bmisscount != 0)) {
1907 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1908 "resume beacon xmit after %u misses\n",
1913 if (sc->opmode == NL80211_IFTYPE_AP && sc->num_ap_vifs > 1) {
1914 u64 tsf = ath5k_hw_get_tsf64(ah);
1915 u32 tsftu = TSF_TO_TU(tsf);
1916 int slot = ((tsftu % sc->bintval) * ATH_BCBUF) / sc->bintval;
1917 vif = sc->bslot[(slot + 1) % ATH_BCBUF];
1918 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1919 "tsf %llx tsftu %x intval %u slot %u vif %p\n",
1920 (unsigned long long)tsf, tsftu, sc->bintval, slot, vif);
1921 } else /* only one interface */
1927 avf = (void *)vif->drv_priv;
1929 if (unlikely(bf->skb == NULL || sc->opmode == NL80211_IFTYPE_STATION ||
1930 sc->opmode == NL80211_IFTYPE_MONITOR)) {
1931 ATH5K_WARN(sc, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL);
1936 * Stop any current dma and put the new frame on the queue.
1937 * This should never fail since we check above that no frames
1938 * are still pending on the queue.
1940 if (unlikely(ath5k_hw_stop_tx_dma(ah, sc->bhalq))) {
1941 ATH5K_WARN(sc, "beacon queue %u didn't start/stop ?\n", sc->bhalq);
1942 /* NB: hw still stops DMA, so proceed */
1945 /* refresh the beacon for AP mode */
1946 if (sc->opmode == NL80211_IFTYPE_AP)
1947 ath5k_beacon_update(sc->hw, vif);
1949 ath5k_hw_set_txdp(ah, sc->bhalq, bf->daddr);
1950 ath5k_hw_start_tx_dma(ah, sc->bhalq);
1951 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
1952 sc->bhalq, (unsigned long long)bf->daddr, bf->desc);
1954 skb = ieee80211_get_buffered_bc(sc->hw, vif);
1956 ath5k_tx_queue(sc->hw, skb, sc->cabq);
1957 skb = ieee80211_get_buffered_bc(sc->hw, vif);
1964 * ath5k_beacon_update_timers - update beacon timers
1966 * @sc: struct ath5k_softc pointer we are operating on
1967 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
1968 * beacon timer update based on the current HW TSF.
1970 * Calculate the next target beacon transmit time (TBTT) based on the timestamp
1971 * of a received beacon or the current local hardware TSF and write it to the
1972 * beacon timer registers.
1974 * This is called in a variety of situations, e.g. when a beacon is received,
1975 * when a TSF update has been detected, but also when an new IBSS is created or
1976 * when we otherwise know we have to update the timers, but we keep it in this
1977 * function to have it all together in one place.
1980 ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
1982 struct ath5k_hw *ah = sc->ah;
1983 u32 nexttbtt, intval, hw_tu, bc_tu;
1986 intval = sc->bintval & AR5K_BEACON_PERIOD;
1987 if (sc->opmode == NL80211_IFTYPE_AP && sc->num_ap_vifs > 1) {
1988 intval /= ATH_BCBUF; /* staggered multi-bss beacons */
1990 ATH5K_WARN(sc, "intval %u is too low, min 15\n",
1993 if (WARN_ON(!intval))
1996 /* beacon TSF converted to TU */
1997 bc_tu = TSF_TO_TU(bc_tsf);
1999 /* current TSF converted to TU */
2000 hw_tsf = ath5k_hw_get_tsf64(ah);
2001 hw_tu = TSF_TO_TU(hw_tsf);
2003 #define FUDGE AR5K_TUNE_SW_BEACON_RESP + 3
2004 /* We use FUDGE to make sure the next TBTT is ahead of the current TU.
2005 * Since we later substract AR5K_TUNE_SW_BEACON_RESP (10) in the timer
2006 * configuration we need to make sure it is bigger than that. */
2010 * no beacons received, called internally.
2011 * just need to refresh timers based on HW TSF.
2013 nexttbtt = roundup(hw_tu + FUDGE, intval);
2014 } else if (bc_tsf == 0) {
2016 * no beacon received, probably called by ath5k_reset_tsf().
2017 * reset TSF to start with 0.
2020 intval |= AR5K_BEACON_RESET_TSF;
2021 } else if (bc_tsf > hw_tsf) {
2023 * beacon received, SW merge happend but HW TSF not yet updated.
2024 * not possible to reconfigure timers yet, but next time we
2025 * receive a beacon with the same BSSID, the hardware will
2026 * automatically update the TSF and then we need to reconfigure
2029 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2030 "need to wait for HW TSF sync\n");
2034 * most important case for beacon synchronization between STA.
2036 * beacon received and HW TSF has been already updated by HW.
2037 * update next TBTT based on the TSF of the beacon, but make
2038 * sure it is ahead of our local TSF timer.
2040 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval);
2044 sc->nexttbtt = nexttbtt;
2046 intval |= AR5K_BEACON_ENA;
2047 ath5k_hw_init_beacon(ah, nexttbtt, intval);
2050 * debugging output last in order to preserve the time critical aspect
2054 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2055 "reconfigured timers based on HW TSF\n");
2056 else if (bc_tsf == 0)
2057 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2058 "reset HW TSF and timers\n");
2060 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2061 "updated timers based on beacon TSF\n");
2063 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2064 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2065 (unsigned long long) bc_tsf,
2066 (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt);
2067 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "intval %u %s %s\n",
2068 intval & AR5K_BEACON_PERIOD,
2069 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "",
2070 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : "");
2074 * ath5k_beacon_config - Configure the beacon queues and interrupts
2076 * @sc: struct ath5k_softc pointer we are operating on
2078 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
2079 * interrupts to detect TSF updates only.
2082 ath5k_beacon_config(struct ath5k_softc *sc)
2084 struct ath5k_hw *ah = sc->ah;
2085 unsigned long flags;
2087 spin_lock_irqsave(&sc->block, flags);
2089 sc->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA);
2091 if (sc->enable_beacon) {
2093 * In IBSS mode we use a self-linked tx descriptor and let the
2094 * hardware send the beacons automatically. We have to load it
2096 * We use the SWBA interrupt only to keep track of the beacon
2097 * timers in order to detect automatic TSF updates.
2099 ath5k_beaconq_config(sc);
2101 sc->imask |= AR5K_INT_SWBA;
2103 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
2104 if (ath5k_hw_hasveol(ah))
2105 ath5k_beacon_send(sc);
2107 ath5k_beacon_update_timers(sc, -1);
2109 ath5k_hw_stop_tx_dma(sc->ah, sc->bhalq);
2112 ath5k_hw_set_imr(ah, sc->imask);
2114 spin_unlock_irqrestore(&sc->block, flags);
2117 static void ath5k_tasklet_beacon(unsigned long data)
2119 struct ath5k_softc *sc = (struct ath5k_softc *) data;
2122 * Software beacon alert--time to send a beacon.
2124 * In IBSS mode we use this interrupt just to
2125 * keep track of the next TBTT (target beacon
2126 * transmission time) in order to detect wether
2127 * automatic TSF updates happened.
2129 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
2130 /* XXX: only if VEOL suppported */
2131 u64 tsf = ath5k_hw_get_tsf64(sc->ah);
2132 sc->nexttbtt += sc->bintval;
2133 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2134 "SWBA nexttbtt: %x hw_tu: %x "
2138 (unsigned long long) tsf);
2140 spin_lock(&sc->block);
2141 ath5k_beacon_send(sc);
2142 spin_unlock(&sc->block);
2147 /********************\
2148 * Interrupt handling *
2149 \********************/
2152 ath5k_intr_calibration_poll(struct ath5k_hw *ah)
2154 if (time_is_before_eq_jiffies(ah->ah_cal_next_ani) &&
2155 !(ah->ah_cal_mask & AR5K_CALIBRATION_FULL)) {
2156 /* run ANI only when full calibration is not active */
2157 ah->ah_cal_next_ani = jiffies +
2158 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_ANI);
2159 tasklet_schedule(&ah->ah_sc->ani_tasklet);
2161 } else if (time_is_before_eq_jiffies(ah->ah_cal_next_full)) {
2162 ah->ah_cal_next_full = jiffies +
2163 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_FULL);
2164 tasklet_schedule(&ah->ah_sc->calib);
2166 /* we could use SWI to generate enough interrupts to meet our
2167 * calibration interval requirements, if necessary:
2168 * AR5K_REG_ENABLE_BITS(ah, AR5K_CR, AR5K_CR_SWI); */
2172 ath5k_intr(int irq, void *dev_id)
2174 struct ath5k_softc *sc = dev_id;
2175 struct ath5k_hw *ah = sc->ah;
2176 enum ath5k_int status;
2177 unsigned int counter = 1000;
2179 if (unlikely(test_bit(ATH_STAT_INVALID, sc->status) ||
2180 !ath5k_hw_is_intr_pending(ah)))
2184 ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */
2185 ATH5K_DBG(sc, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
2187 if (unlikely(status & AR5K_INT_FATAL)) {
2189 * Fatal errors are unrecoverable.
2190 * Typically these are caused by DMA errors.
2192 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2193 "fatal int, resetting\n");
2194 ieee80211_queue_work(sc->hw, &sc->reset_work);
2195 } else if (unlikely(status & AR5K_INT_RXORN)) {
2197 * Receive buffers are full. Either the bus is busy or
2198 * the CPU is not fast enough to process all received
2200 * Older chipsets need a reset to come out of this
2201 * condition, but we treat it as RX for newer chips.
2202 * We don't know exactly which versions need a reset -
2203 * this guess is copied from the HAL.
2205 sc->stats.rxorn_intr++;
2206 if (ah->ah_mac_srev < AR5K_SREV_AR5212) {
2207 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2208 "rx overrun, resetting\n");
2209 ieee80211_queue_work(sc->hw, &sc->reset_work);
2212 tasklet_schedule(&sc->rxtq);
2214 if (status & AR5K_INT_SWBA) {
2215 tasklet_hi_schedule(&sc->beacontq);
2217 if (status & AR5K_INT_RXEOL) {
2219 * NB: the hardware should re-read the link when
2220 * RXE bit is written, but it doesn't work at
2221 * least on older hardware revs.
2223 sc->stats.rxeol_intr++;
2225 if (status & AR5K_INT_TXURN) {
2226 /* bump tx trigger level */
2227 ath5k_hw_update_tx_triglevel(ah, true);
2229 if (status & (AR5K_INT_RXOK | AR5K_INT_RXERR))
2230 tasklet_schedule(&sc->rxtq);
2231 if (status & (AR5K_INT_TXOK | AR5K_INT_TXDESC
2232 | AR5K_INT_TXERR | AR5K_INT_TXEOL))
2233 tasklet_schedule(&sc->txtq);
2234 if (status & AR5K_INT_BMISS) {
2237 if (status & AR5K_INT_MIB) {
2238 sc->stats.mib_intr++;
2239 ath5k_hw_update_mib_counters(ah);
2240 ath5k_ani_mib_intr(ah);
2242 if (status & AR5K_INT_GPIO)
2243 tasklet_schedule(&sc->rf_kill.toggleq);
2246 } while (ath5k_hw_is_intr_pending(ah) && --counter > 0);
2248 if (unlikely(!counter))
2249 ATH5K_WARN(sc, "too many interrupts, giving up for now\n");
2251 ath5k_intr_calibration_poll(ah);
2257 * Periodically recalibrate the PHY to account
2258 * for temperature/environment changes.
2261 ath5k_tasklet_calibrate(unsigned long data)
2263 struct ath5k_softc *sc = (void *)data;
2264 struct ath5k_hw *ah = sc->ah;
2266 /* Only full calibration for now */
2267 ah->ah_cal_mask |= AR5K_CALIBRATION_FULL;
2269 ATH5K_DBG(sc, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
2270 ieee80211_frequency_to_channel(sc->curchan->center_freq),
2271 sc->curchan->hw_value);
2273 if (ath5k_hw_gainf_calibrate(ah) == AR5K_RFGAIN_NEED_CHANGE) {
2275 * Rfgain is out of bounds, reset the chip
2276 * to load new gain values.
2278 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "calibration, resetting\n");
2279 ieee80211_queue_work(sc->hw, &sc->reset_work);
2281 if (ath5k_hw_phy_calibrate(ah, sc->curchan))
2282 ATH5K_ERR(sc, "calibration of channel %u failed\n",
2283 ieee80211_frequency_to_channel(
2284 sc->curchan->center_freq));
2286 /* Noise floor calibration interrupts rx/tx path while I/Q calibration
2288 * TODO: We should stop TX here, so that it doesn't interfere.
2289 * Note that stopping the queues is not enough to stop TX! */
2290 if (time_is_before_eq_jiffies(ah->ah_cal_next_nf)) {
2291 ah->ah_cal_next_nf = jiffies +
2292 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_NF);
2293 ath5k_hw_update_noise_floor(ah);
2296 ah->ah_cal_mask &= ~AR5K_CALIBRATION_FULL;
2301 ath5k_tasklet_ani(unsigned long data)
2303 struct ath5k_softc *sc = (void *)data;
2304 struct ath5k_hw *ah = sc->ah;
2306 ah->ah_cal_mask |= AR5K_CALIBRATION_ANI;
2307 ath5k_ani_calibration(ah);
2308 ah->ah_cal_mask &= ~AR5K_CALIBRATION_ANI;
2313 ath5k_tx_complete_poll_work(struct work_struct *work)
2315 struct ath5k_softc *sc = container_of(work, struct ath5k_softc,
2316 tx_complete_work.work);
2317 struct ath5k_txq *txq;
2319 bool needreset = false;
2321 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++) {
2322 if (sc->txqs[i].setup) {
2324 spin_lock_bh(&txq->lock);
2325 if (txq->txq_len > 1) {
2326 if (txq->txq_poll_mark) {
2327 ATH5K_DBG(sc, ATH5K_DEBUG_XMIT,
2328 "TX queue stuck %d\n",
2332 spin_unlock_bh(&txq->lock);
2335 txq->txq_poll_mark = true;
2338 spin_unlock_bh(&txq->lock);
2343 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2344 "TX queues stuck, resetting\n");
2345 ath5k_reset(sc, sc->curchan);
2348 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work,
2349 msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT));
2353 /*************************\
2354 * Initialization routines *
2355 \*************************/
2358 ath5k_stop_locked(struct ath5k_softc *sc)
2360 struct ath5k_hw *ah = sc->ah;
2362 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "invalid %u\n",
2363 test_bit(ATH_STAT_INVALID, sc->status));
2366 * Shutdown the hardware and driver:
2367 * stop output from above
2368 * disable interrupts
2370 * turn off the radio
2371 * clear transmit machinery
2372 * clear receive machinery
2373 * drain and release tx queues
2374 * reclaim beacon resources
2375 * power down hardware
2377 * Note that some of this work is not possible if the
2378 * hardware is gone (invalid).
2380 ieee80211_stop_queues(sc->hw);
2382 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2384 ath5k_hw_set_imr(ah, 0);
2385 synchronize_irq(sc->pdev->irq);
2387 ath5k_txq_cleanup(sc);
2388 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2390 ath5k_hw_phy_disable(ah);
2397 ath5k_init(struct ath5k_softc *sc)
2399 struct ath5k_hw *ah = sc->ah;
2400 struct ath_common *common = ath5k_hw_common(ah);
2403 mutex_lock(&sc->lock);
2405 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mode %d\n", sc->opmode);
2408 * Stop anything previously setup. This is safe
2409 * no matter this is the first time through or not.
2411 ath5k_stop_locked(sc);
2414 * The basic interface to setting the hardware in a good
2415 * state is ``reset''. On return the hardware is known to
2416 * be powered up and with interrupts disabled. This must
2417 * be followed by initialization of the appropriate bits
2418 * and then setup of the interrupt mask.
2420 sc->curchan = sc->hw->conf.channel;
2421 sc->curband = &sc->sbands[sc->curchan->band];
2422 sc->imask = AR5K_INT_RXOK | AR5K_INT_RXERR | AR5K_INT_RXEOL |
2423 AR5K_INT_RXORN | AR5K_INT_TXDESC | AR5K_INT_TXEOL |
2424 AR5K_INT_FATAL | AR5K_INT_GLOBAL | AR5K_INT_MIB;
2426 ret = ath5k_reset(sc, NULL);
2430 ath5k_rfkill_hw_start(ah);
2433 * Reset the key cache since some parts do not reset the
2434 * contents on initial power up or resume from suspend.
2436 for (i = 0; i < common->keymax; i++)
2437 ath_hw_keyreset(common, (u16) i);
2439 ath5k_hw_set_ack_bitrate_high(ah, true);
2441 for (i = 0; i < ARRAY_SIZE(sc->bslot); i++)
2442 sc->bslot[i] = NULL;
2447 mutex_unlock(&sc->lock);
2449 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work,
2450 msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT));
2455 static void stop_tasklets(struct ath5k_softc *sc)
2457 tasklet_kill(&sc->rxtq);
2458 tasklet_kill(&sc->txtq);
2459 tasklet_kill(&sc->calib);
2460 tasklet_kill(&sc->beacontq);
2461 tasklet_kill(&sc->ani_tasklet);
2465 * Stop the device, grabbing the top-level lock to protect
2466 * against concurrent entry through ath5k_init (which can happen
2467 * if another thread does a system call and the thread doing the
2468 * stop is preempted).
2471 ath5k_stop_hw(struct ath5k_softc *sc)
2475 mutex_lock(&sc->lock);
2476 ret = ath5k_stop_locked(sc);
2477 if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) {
2479 * Don't set the card in full sleep mode!
2481 * a) When the device is in this state it must be carefully
2482 * woken up or references to registers in the PCI clock
2483 * domain may freeze the bus (and system). This varies
2484 * by chip and is mostly an issue with newer parts
2485 * (madwifi sources mentioned srev >= 0x78) that go to
2486 * sleep more quickly.
2488 * b) On older chips full sleep results a weird behaviour
2489 * during wakeup. I tested various cards with srev < 0x78
2490 * and they don't wake up after module reload, a second
2491 * module reload is needed to bring the card up again.
2493 * Until we figure out what's going on don't enable
2494 * full chip reset on any chip (this is what Legacy HAL
2495 * and Sam's HAL do anyway). Instead Perform a full reset
2496 * on the device (same as initial state after attach) and
2497 * leave it idle (keep MAC/BB on warm reset) */
2498 ret = ath5k_hw_on_hold(sc->ah);
2500 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2501 "putting device to sleep\n");
2505 mutex_unlock(&sc->lock);
2509 cancel_delayed_work_sync(&sc->tx_complete_work);
2511 ath5k_rfkill_hw_stop(sc->ah);
2517 * Reset the hardware. If chan is not NULL, then also pause rx/tx
2518 * and change to the given channel.
2520 * This should be called with sc->lock.
2523 ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan)
2525 struct ath5k_hw *ah = sc->ah;
2528 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n");
2530 ath5k_hw_set_imr(ah, 0);
2531 synchronize_irq(sc->pdev->irq);
2535 ath5k_txq_cleanup(sc);
2539 sc->curband = &sc->sbands[chan->band];
2541 ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, chan != NULL);
2543 ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret);
2547 ret = ath5k_rx_start(sc);
2549 ATH5K_ERR(sc, "can't start recv logic\n");
2553 ath5k_ani_init(ah, ah->ah_sc->ani_state.ani_mode);
2555 ah->ah_cal_next_full = jiffies;
2556 ah->ah_cal_next_ani = jiffies;
2557 ah->ah_cal_next_nf = jiffies;
2558 ewma_init(&ah->ah_beacon_rssi_avg, 1000, 8);
2561 * Change channels and update the h/w rate map if we're switching;
2562 * e.g. 11a to 11b/g.
2564 * We may be doing a reset in response to an ioctl that changes the
2565 * channel so update any state that might change as a result.
2569 /* ath5k_chan_change(sc, c); */
2571 ath5k_beacon_config(sc);
2572 /* intrs are enabled by ath5k_beacon_config */
2574 ieee80211_wake_queues(sc->hw);
2581 static void ath5k_reset_work(struct work_struct *work)
2583 struct ath5k_softc *sc = container_of(work, struct ath5k_softc,
2586 mutex_lock(&sc->lock);
2587 ath5k_reset(sc, sc->curchan);
2588 mutex_unlock(&sc->lock);
2592 ath5k_attach(struct pci_dev *pdev, struct ieee80211_hw *hw)
2594 struct ath5k_softc *sc = hw->priv;
2595 struct ath5k_hw *ah = sc->ah;
2596 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah);
2597 struct ath5k_txq *txq;
2598 u8 mac[ETH_ALEN] = {};
2601 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "devid 0x%x\n", pdev->device);
2604 * Check if the MAC has multi-rate retry support.
2605 * We do this by trying to setup a fake extended
2606 * descriptor. MACs that don't have support will
2607 * return false w/o doing anything. MACs that do
2608 * support it will return true w/o doing anything.
2610 ret = ath5k_hw_setup_mrr_tx_desc(ah, NULL, 0, 0, 0, 0, 0, 0);
2615 __set_bit(ATH_STAT_MRRETRY, sc->status);
2618 * Collect the channel list. The 802.11 layer
2619 * is resposible for filtering this list based
2620 * on settings like the phy mode and regulatory
2621 * domain restrictions.
2623 ret = ath5k_setup_bands(hw);
2625 ATH5K_ERR(sc, "can't get channels\n");
2629 /* NB: setup here so ath5k_rate_update is happy */
2630 if (test_bit(AR5K_MODE_11A, ah->ah_modes))
2631 ath5k_setcurmode(sc, AR5K_MODE_11A);
2633 ath5k_setcurmode(sc, AR5K_MODE_11B);
2636 * Allocate tx+rx descriptors and populate the lists.
2638 ret = ath5k_desc_alloc(sc, pdev);
2640 ATH5K_ERR(sc, "can't allocate descriptors\n");
2645 * Allocate hardware transmit queues: one queue for
2646 * beacon frames and one data queue for each QoS
2647 * priority. Note that hw functions handle resetting
2648 * these queues at the needed time.
2650 ret = ath5k_beaconq_setup(ah);
2652 ATH5K_ERR(sc, "can't setup a beacon xmit queue\n");
2656 sc->cabq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_CAB, 0);
2657 if (IS_ERR(sc->cabq)) {
2658 ATH5K_ERR(sc, "can't setup cab queue\n");
2659 ret = PTR_ERR(sc->cabq);
2663 /* This order matches mac80211's queue priority, so we can
2664 * directly use the mac80211 queue number without any mapping */
2665 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VO);
2667 ATH5K_ERR(sc, "can't setup xmit queue\n");
2671 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VI);
2673 ATH5K_ERR(sc, "can't setup xmit queue\n");
2677 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BE);
2679 ATH5K_ERR(sc, "can't setup xmit queue\n");
2683 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
2685 ATH5K_ERR(sc, "can't setup xmit queue\n");
2691 tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc);
2692 tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc);
2693 tasklet_init(&sc->calib, ath5k_tasklet_calibrate, (unsigned long)sc);
2694 tasklet_init(&sc->beacontq, ath5k_tasklet_beacon, (unsigned long)sc);
2695 tasklet_init(&sc->ani_tasklet, ath5k_tasklet_ani, (unsigned long)sc);
2697 INIT_WORK(&sc->reset_work, ath5k_reset_work);
2698 INIT_DELAYED_WORK(&sc->tx_complete_work, ath5k_tx_complete_poll_work);
2700 ret = ath5k_eeprom_read_mac(ah, mac);
2702 ATH5K_ERR(sc, "unable to read address from EEPROM: 0x%04x\n",
2707 SET_IEEE80211_PERM_ADDR(hw, mac);
2708 memcpy(&sc->lladdr, mac, ETH_ALEN);
2709 /* All MAC address bits matter for ACKs */
2710 ath5k_update_bssid_mask_and_opmode(sc, NULL);
2712 regulatory->current_rd = ah->ah_capabilities.cap_eeprom.ee_regdomain;
2713 ret = ath_regd_init(regulatory, hw->wiphy, ath5k_reg_notifier);
2715 ATH5K_ERR(sc, "can't initialize regulatory system\n");
2719 ret = ieee80211_register_hw(hw);
2721 ATH5K_ERR(sc, "can't register ieee80211 hw\n");
2725 if (!ath_is_world_regd(regulatory))
2726 regulatory_hint(hw->wiphy, regulatory->alpha2);
2728 ath5k_init_leds(sc);
2730 ath5k_sysfs_register(sc);
2734 ath5k_txq_release(sc);
2736 ath5k_hw_release_tx_queue(ah, sc->bhalq);
2738 ath5k_desc_free(sc, pdev);
2744 ath5k_detach(struct pci_dev *pdev, struct ieee80211_hw *hw)
2746 struct ath5k_softc *sc = hw->priv;
2749 * NB: the order of these is important:
2750 * o call the 802.11 layer before detaching ath5k_hw to
2751 * ensure callbacks into the driver to delete global
2752 * key cache entries can be handled
2753 * o reclaim the tx queue data structures after calling
2754 * the 802.11 layer as we'll get called back to reclaim
2755 * node state and potentially want to use them
2756 * o to cleanup the tx queues the hal is called, so detach
2758 * XXX: ??? detach ath5k_hw ???
2759 * Other than that, it's straightforward...
2761 ieee80211_unregister_hw(hw);
2762 ath5k_desc_free(sc, pdev);
2763 ath5k_txq_release(sc);
2764 ath5k_hw_release_tx_queue(sc->ah, sc->bhalq);
2765 ath5k_unregister_leds(sc);
2767 ath5k_sysfs_unregister(sc);
2769 * NB: can't reclaim these until after ieee80211_ifdetach
2770 * returns because we'll get called back to reclaim node
2771 * state and potentially want to use them.
2775 /********************\
2776 * Mac80211 functions *
2777 \********************/
2780 ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
2782 struct ath5k_softc *sc = hw->priv;
2783 u16 qnum = skb_get_queue_mapping(skb);
2785 if (WARN_ON(qnum >= sc->ah->ah_capabilities.cap_queues.q_tx_num)) {
2786 dev_kfree_skb_any(skb);
2790 return ath5k_tx_queue(hw, skb, &sc->txqs[qnum]);
2793 static int ath5k_start(struct ieee80211_hw *hw)
2795 return ath5k_init(hw->priv);
2798 static void ath5k_stop(struct ieee80211_hw *hw)
2800 ath5k_stop_hw(hw->priv);
2803 static int ath5k_add_interface(struct ieee80211_hw *hw,
2804 struct ieee80211_vif *vif)
2806 struct ath5k_softc *sc = hw->priv;
2808 struct ath5k_vif *avf = (void *)vif->drv_priv;
2810 mutex_lock(&sc->lock);
2812 if ((vif->type == NL80211_IFTYPE_AP ||
2813 vif->type == NL80211_IFTYPE_ADHOC)
2814 && (sc->num_ap_vifs + sc->num_adhoc_vifs) >= ATH_BCBUF) {
2819 /* Don't allow other interfaces if one ad-hoc is configured.
2820 * TODO: Fix the problems with ad-hoc and multiple other interfaces.
2821 * We would need to operate the HW in ad-hoc mode to allow TSF updates
2822 * for the IBSS, but this breaks with additional AP or STA interfaces
2824 if (sc->num_adhoc_vifs ||
2825 (sc->nvifs && vif->type == NL80211_IFTYPE_ADHOC)) {
2826 ATH5K_ERR(sc, "Only one single ad-hoc interface is allowed.\n");
2831 switch (vif->type) {
2832 case NL80211_IFTYPE_AP:
2833 case NL80211_IFTYPE_STATION:
2834 case NL80211_IFTYPE_ADHOC:
2835 case NL80211_IFTYPE_MESH_POINT:
2836 avf->opmode = vif->type;
2844 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "add interface mode %d\n", avf->opmode);
2846 /* Assign the vap/adhoc to a beacon xmit slot. */
2847 if ((avf->opmode == NL80211_IFTYPE_AP) ||
2848 (avf->opmode == NL80211_IFTYPE_ADHOC)) {
2851 WARN_ON(list_empty(&sc->bcbuf));
2852 avf->bbuf = list_first_entry(&sc->bcbuf, struct ath5k_buf,
2854 list_del(&avf->bbuf->list);
2857 for (slot = 0; slot < ATH_BCBUF; slot++) {
2858 if (!sc->bslot[slot]) {
2863 BUG_ON(sc->bslot[avf->bslot] != NULL);
2864 sc->bslot[avf->bslot] = vif;
2865 if (avf->opmode == NL80211_IFTYPE_AP)
2868 sc->num_adhoc_vifs++;
2871 /* Any MAC address is fine, all others are included through the
2874 memcpy(&sc->lladdr, vif->addr, ETH_ALEN);
2875 ath5k_hw_set_lladdr(sc->ah, vif->addr);
2877 memcpy(&avf->lladdr, vif->addr, ETH_ALEN);
2879 ath5k_mode_setup(sc, vif);
2883 mutex_unlock(&sc->lock);
2888 ath5k_remove_interface(struct ieee80211_hw *hw,
2889 struct ieee80211_vif *vif)
2891 struct ath5k_softc *sc = hw->priv;
2892 struct ath5k_vif *avf = (void *)vif->drv_priv;
2895 mutex_lock(&sc->lock);
2899 ath5k_txbuf_free_skb(sc, avf->bbuf);
2900 list_add_tail(&avf->bbuf->list, &sc->bcbuf);
2901 for (i = 0; i < ATH_BCBUF; i++) {
2902 if (sc->bslot[i] == vif) {
2903 sc->bslot[i] = NULL;
2909 if (avf->opmode == NL80211_IFTYPE_AP)
2911 else if (avf->opmode == NL80211_IFTYPE_ADHOC)
2912 sc->num_adhoc_vifs--;
2914 ath5k_update_bssid_mask_and_opmode(sc, NULL);
2915 mutex_unlock(&sc->lock);
2919 * TODO: Phy disable/diversity etc
2922 ath5k_config(struct ieee80211_hw *hw, u32 changed)
2924 struct ath5k_softc *sc = hw->priv;
2925 struct ath5k_hw *ah = sc->ah;
2926 struct ieee80211_conf *conf = &hw->conf;
2929 mutex_lock(&sc->lock);
2931 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
2932 ret = ath5k_chan_set(sc, conf->channel);
2937 if ((changed & IEEE80211_CONF_CHANGE_POWER) &&
2938 (sc->power_level != conf->power_level)) {
2939 sc->power_level = conf->power_level;
2942 ath5k_hw_set_txpower_limit(ah, (conf->power_level * 2));
2946 * 1) Move this on config_interface and handle each case
2947 * separately eg. when we have only one STA vif, use
2948 * AR5K_ANTMODE_SINGLE_AP
2950 * 2) Allow the user to change antenna mode eg. when only
2951 * one antenna is present
2953 * 3) Allow the user to set default/tx antenna when possible
2955 * 4) Default mode should handle 90% of the cases, together
2956 * with fixed a/b and single AP modes we should be able to
2957 * handle 99%. Sectored modes are extreme cases and i still
2958 * haven't found a usage for them. If we decide to support them,
2959 * then we must allow the user to set how many tx antennas we
2962 ath5k_hw_set_antenna_mode(ah, ah->ah_ant_mode);
2965 mutex_unlock(&sc->lock);
2969 static u64 ath5k_prepare_multicast(struct ieee80211_hw *hw,
2970 struct netdev_hw_addr_list *mc_list)
2974 struct netdev_hw_addr *ha;
2979 netdev_hw_addr_list_for_each(ha, mc_list) {
2980 /* calculate XOR of eight 6-bit values */
2981 val = get_unaligned_le32(ha->addr + 0);
2982 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2983 val = get_unaligned_le32(ha->addr + 3);
2984 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2986 mfilt[pos / 32] |= (1 << (pos % 32));
2987 /* XXX: we might be able to just do this instead,
2988 * but not sure, needs testing, if we do use this we'd
2989 * neet to inform below to not reset the mcast */
2990 /* ath5k_hw_set_mcast_filterindex(ah,
2994 return ((u64)(mfilt[1]) << 32) | mfilt[0];
2997 static bool ath_any_vif_assoc(struct ath5k_softc *sc)
2999 struct ath_vif_iter_data iter_data;
3000 iter_data.hw_macaddr = NULL;
3001 iter_data.any_assoc = false;
3002 iter_data.need_set_hw_addr = false;
3003 iter_data.found_active = true;
3005 ieee80211_iterate_active_interfaces_atomic(sc->hw, ath_vif_iter,
3007 return iter_data.any_assoc;
3010 #define SUPPORTED_FIF_FLAGS \
3011 FIF_PROMISC_IN_BSS | FIF_ALLMULTI | FIF_FCSFAIL | \
3012 FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \
3013 FIF_BCN_PRBRESP_PROMISC
3015 * o always accept unicast, broadcast, and multicast traffic
3016 * o multicast traffic for all BSSIDs will be enabled if mac80211
3018 * o maintain current state of phy ofdm or phy cck error reception.
3019 * If the hardware detects any of these type of errors then
3020 * ath5k_hw_get_rx_filter() will pass to us the respective
3021 * hardware filters to be able to receive these type of frames.
3022 * o probe request frames are accepted only when operating in
3023 * hostap, adhoc, or monitor modes
3024 * o enable promiscuous mode according to the interface state
3026 * - when operating in adhoc mode so the 802.11 layer creates
3027 * node table entries for peers,
3028 * - when operating in station mode for collecting rssi data when
3029 * the station is otherwise quiet, or
3032 static void ath5k_configure_filter(struct ieee80211_hw *hw,
3033 unsigned int changed_flags,
3034 unsigned int *new_flags,
3037 struct ath5k_softc *sc = hw->priv;
3038 struct ath5k_hw *ah = sc->ah;
3039 u32 mfilt[2], rfilt;
3041 mutex_lock(&sc->lock);
3043 mfilt[0] = multicast;
3044 mfilt[1] = multicast >> 32;
3046 /* Only deal with supported flags */
3047 changed_flags &= SUPPORTED_FIF_FLAGS;
3048 *new_flags &= SUPPORTED_FIF_FLAGS;
3050 /* If HW detects any phy or radar errors, leave those filters on.
3051 * Also, always enable Unicast, Broadcasts and Multicast
3052 * XXX: move unicast, bssid broadcasts and multicast to mac80211 */
3053 rfilt = (ath5k_hw_get_rx_filter(ah) & (AR5K_RX_FILTER_PHYERR)) |
3054 (AR5K_RX_FILTER_UCAST | AR5K_RX_FILTER_BCAST |
3055 AR5K_RX_FILTER_MCAST);
3057 if (changed_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS)) {
3058 if (*new_flags & FIF_PROMISC_IN_BSS) {
3059 __set_bit(ATH_STAT_PROMISC, sc->status);
3061 __clear_bit(ATH_STAT_PROMISC, sc->status);
3065 if (test_bit(ATH_STAT_PROMISC, sc->status))
3066 rfilt |= AR5K_RX_FILTER_PROM;
3068 /* Note, AR5K_RX_FILTER_MCAST is already enabled */
3069 if (*new_flags & FIF_ALLMULTI) {
3074 /* This is the best we can do */
3075 if (*new_flags & (FIF_FCSFAIL | FIF_PLCPFAIL))
3076 rfilt |= AR5K_RX_FILTER_PHYERR;
3078 /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons
3079 * and probes for any BSSID */
3080 if ((*new_flags & FIF_BCN_PRBRESP_PROMISC) || (sc->nvifs > 1))
3081 rfilt |= AR5K_RX_FILTER_BEACON;
3083 /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not
3084 * set we should only pass on control frames for this
3085 * station. This needs testing. I believe right now this
3086 * enables *all* control frames, which is OK.. but
3087 * but we should see if we can improve on granularity */
3088 if (*new_flags & FIF_CONTROL)
3089 rfilt |= AR5K_RX_FILTER_CONTROL;
3091 /* Additional settings per mode -- this is per ath5k */
3093 /* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */
3095 switch (sc->opmode) {
3096 case NL80211_IFTYPE_MESH_POINT:
3097 rfilt |= AR5K_RX_FILTER_CONTROL |
3098 AR5K_RX_FILTER_BEACON |
3099 AR5K_RX_FILTER_PROBEREQ |
3100 AR5K_RX_FILTER_PROM;
3102 case NL80211_IFTYPE_AP:
3103 case NL80211_IFTYPE_ADHOC:
3104 rfilt |= AR5K_RX_FILTER_PROBEREQ |
3105 AR5K_RX_FILTER_BEACON;
3107 case NL80211_IFTYPE_STATION:
3109 rfilt |= AR5K_RX_FILTER_BEACON;
3115 ath5k_hw_set_rx_filter(ah, rfilt);
3117 /* Set multicast bits */
3118 ath5k_hw_set_mcast_filter(ah, mfilt[0], mfilt[1]);
3119 /* Set the cached hw filter flags, this will later actually
3121 sc->filter_flags = rfilt;
3123 mutex_unlock(&sc->lock);
3127 ath5k_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
3128 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
3129 struct ieee80211_key_conf *key)
3131 struct ath5k_softc *sc = hw->priv;
3132 struct ath5k_hw *ah = sc->ah;
3133 struct ath_common *common = ath5k_hw_common(ah);
3136 if (modparam_nohwcrypt)
3139 switch (key->cipher) {
3140 case WLAN_CIPHER_SUITE_WEP40:
3141 case WLAN_CIPHER_SUITE_WEP104:
3142 case WLAN_CIPHER_SUITE_TKIP:
3144 case WLAN_CIPHER_SUITE_CCMP:
3145 if (common->crypt_caps & ATH_CRYPT_CAP_CIPHER_AESCCM)
3153 mutex_lock(&sc->lock);
3157 ret = ath_key_config(common, vif, sta, key);
3159 key->hw_key_idx = ret;
3160 /* push IV and Michael MIC generation to stack */
3161 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
3162 if (key->cipher == WLAN_CIPHER_SUITE_TKIP)
3163 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
3164 if (key->cipher == WLAN_CIPHER_SUITE_CCMP)
3165 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
3170 ath_key_delete(common, key);
3177 mutex_unlock(&sc->lock);
3182 ath5k_get_stats(struct ieee80211_hw *hw,
3183 struct ieee80211_low_level_stats *stats)
3185 struct ath5k_softc *sc = hw->priv;
3188 ath5k_hw_update_mib_counters(sc->ah);
3190 stats->dot11ACKFailureCount = sc->stats.ack_fail;
3191 stats->dot11RTSFailureCount = sc->stats.rts_fail;
3192 stats->dot11RTSSuccessCount = sc->stats.rts_ok;
3193 stats->dot11FCSErrorCount = sc->stats.fcs_error;
3198 static int ath5k_get_survey(struct ieee80211_hw *hw, int idx,
3199 struct survey_info *survey)
3201 struct ath5k_softc *sc = hw->priv;
3202 struct ieee80211_conf *conf = &hw->conf;
3203 struct ath_common *common = ath5k_hw_common(sc->ah);
3204 struct ath_cycle_counters *cc = &common->cc_survey;
3205 unsigned int div = common->clockrate * 1000;
3210 survey->channel = conf->channel;
3211 survey->filled = SURVEY_INFO_NOISE_DBM;
3212 survey->noise = sc->ah->ah_noise_floor;
3214 spin_lock_bh(&common->cc_lock);
3215 ath_hw_cycle_counters_update(common);
3216 if (cc->cycles > 0) {
3217 survey->filled |= SURVEY_INFO_CHANNEL_TIME |
3218 SURVEY_INFO_CHANNEL_TIME_BUSY |
3219 SURVEY_INFO_CHANNEL_TIME_RX |
3220 SURVEY_INFO_CHANNEL_TIME_TX;
3221 survey->channel_time += cc->cycles / div;
3222 survey->channel_time_busy += cc->rx_busy / div;
3223 survey->channel_time_rx += cc->rx_frame / div;
3224 survey->channel_time_tx += cc->tx_frame / div;
3226 memset(cc, 0, sizeof(*cc));
3227 spin_unlock_bh(&common->cc_lock);
3233 ath5k_get_tsf(struct ieee80211_hw *hw)
3235 struct ath5k_softc *sc = hw->priv;
3237 return ath5k_hw_get_tsf64(sc->ah);
3241 ath5k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
3243 struct ath5k_softc *sc = hw->priv;
3245 ath5k_hw_set_tsf64(sc->ah, tsf);
3249 ath5k_reset_tsf(struct ieee80211_hw *hw)
3251 struct ath5k_softc *sc = hw->priv;
3254 * in IBSS mode we need to update the beacon timers too.
3255 * this will also reset the TSF if we call it with 0
3257 if (sc->opmode == NL80211_IFTYPE_ADHOC)
3258 ath5k_beacon_update_timers(sc, 0);
3260 ath5k_hw_reset_tsf(sc->ah);
3264 set_beacon_filter(struct ieee80211_hw *hw, bool enable)
3266 struct ath5k_softc *sc = hw->priv;
3267 struct ath5k_hw *ah = sc->ah;
3269 rfilt = ath5k_hw_get_rx_filter(ah);
3271 rfilt |= AR5K_RX_FILTER_BEACON;
3273 rfilt &= ~AR5K_RX_FILTER_BEACON;
3274 ath5k_hw_set_rx_filter(ah, rfilt);
3275 sc->filter_flags = rfilt;
3278 static void ath5k_bss_info_changed(struct ieee80211_hw *hw,
3279 struct ieee80211_vif *vif,
3280 struct ieee80211_bss_conf *bss_conf,
3283 struct ath5k_vif *avf = (void *)vif->drv_priv;
3284 struct ath5k_softc *sc = hw->priv;
3285 struct ath5k_hw *ah = sc->ah;
3286 struct ath_common *common = ath5k_hw_common(ah);
3287 unsigned long flags;
3289 mutex_lock(&sc->lock);
3291 if (changes & BSS_CHANGED_BSSID) {
3292 /* Cache for later use during resets */
3293 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
3295 ath5k_hw_set_bssid(ah);
3299 if (changes & BSS_CHANGED_BEACON_INT)
3300 sc->bintval = bss_conf->beacon_int;
3302 if (changes & BSS_CHANGED_ASSOC) {
3303 avf->assoc = bss_conf->assoc;
3304 if (bss_conf->assoc)
3305 sc->assoc = bss_conf->assoc;
3307 sc->assoc = ath_any_vif_assoc(sc);
3309 if (sc->opmode == NL80211_IFTYPE_STATION)
3310 set_beacon_filter(hw, sc->assoc);
3311 ath5k_hw_set_ledstate(sc->ah, sc->assoc ?
3312 AR5K_LED_ASSOC : AR5K_LED_INIT);
3313 if (bss_conf->assoc) {
3314 ATH5K_DBG(sc, ATH5K_DEBUG_ANY,
3315 "Bss Info ASSOC %d, bssid: %pM\n",
3316 bss_conf->aid, common->curbssid);
3317 common->curaid = bss_conf->aid;
3318 ath5k_hw_set_bssid(ah);
3319 /* Once ANI is available you would start it here */
3323 if (changes & BSS_CHANGED_BEACON) {
3324 spin_lock_irqsave(&sc->block, flags);
3325 ath5k_beacon_update(hw, vif);
3326 spin_unlock_irqrestore(&sc->block, flags);
3329 if (changes & BSS_CHANGED_BEACON_ENABLED)
3330 sc->enable_beacon = bss_conf->enable_beacon;
3332 if (changes & (BSS_CHANGED_BEACON | BSS_CHANGED_BEACON_ENABLED |
3333 BSS_CHANGED_BEACON_INT))
3334 ath5k_beacon_config(sc);
3336 mutex_unlock(&sc->lock);
3339 static void ath5k_sw_scan_start(struct ieee80211_hw *hw)
3341 struct ath5k_softc *sc = hw->priv;
3343 ath5k_hw_set_ledstate(sc->ah, AR5K_LED_SCAN);
3346 static void ath5k_sw_scan_complete(struct ieee80211_hw *hw)
3348 struct ath5k_softc *sc = hw->priv;
3349 ath5k_hw_set_ledstate(sc->ah, sc->assoc ?
3350 AR5K_LED_ASSOC : AR5K_LED_INIT);
3354 * ath5k_set_coverage_class - Set IEEE 802.11 coverage class
3356 * @hw: struct ieee80211_hw pointer
3357 * @coverage_class: IEEE 802.11 coverage class number
3359 * Mac80211 callback. Sets slot time, ACK timeout and CTS timeout for given
3360 * coverage class. The values are persistent, they are restored after device
3363 static void ath5k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class)
3365 struct ath5k_softc *sc = hw->priv;
3367 mutex_lock(&sc->lock);
3368 ath5k_hw_set_coverage_class(sc->ah, coverage_class);
3369 mutex_unlock(&sc->lock);
3372 static int ath5k_conf_tx(struct ieee80211_hw *hw, u16 queue,
3373 const struct ieee80211_tx_queue_params *params)
3375 struct ath5k_softc *sc = hw->priv;
3376 struct ath5k_hw *ah = sc->ah;
3377 struct ath5k_txq_info qi;
3380 if (queue >= ah->ah_capabilities.cap_queues.q_tx_num)
3383 mutex_lock(&sc->lock);
3385 ath5k_hw_get_tx_queueprops(ah, queue, &qi);
3387 qi.tqi_aifs = params->aifs;
3388 qi.tqi_cw_min = params->cw_min;
3389 qi.tqi_cw_max = params->cw_max;
3390 qi.tqi_burst_time = params->txop;
3392 ATH5K_DBG(sc, ATH5K_DEBUG_ANY,
3393 "Configure tx [queue %d], "
3394 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
3395 queue, params->aifs, params->cw_min,
3396 params->cw_max, params->txop);
3398 if (ath5k_hw_set_tx_queueprops(ah, queue, &qi)) {
3400 "Unable to update hardware queue %u!\n", queue);
3403 ath5k_hw_reset_tx_queue(ah, queue);
3405 mutex_unlock(&sc->lock);
3410 static int ath5k_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant)
3412 struct ath5k_softc *sc = hw->priv;
3414 if (tx_ant == 1 && rx_ant == 1)
3415 ath5k_hw_set_antenna_mode(sc->ah, AR5K_ANTMODE_FIXED_A);
3416 else if (tx_ant == 2 && rx_ant == 2)
3417 ath5k_hw_set_antenna_mode(sc->ah, AR5K_ANTMODE_FIXED_B);
3418 else if ((tx_ant & 3) == 3 && (rx_ant & 3) == 3)
3419 ath5k_hw_set_antenna_mode(sc->ah, AR5K_ANTMODE_DEFAULT);
3425 static int ath5k_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant)
3427 struct ath5k_softc *sc = hw->priv;
3429 switch (sc->ah->ah_ant_mode) {
3430 case AR5K_ANTMODE_FIXED_A:
3431 *tx_ant = 1; *rx_ant = 1; break;
3432 case AR5K_ANTMODE_FIXED_B:
3433 *tx_ant = 2; *rx_ant = 2; break;
3434 case AR5K_ANTMODE_DEFAULT:
3435 *tx_ant = 3; *rx_ant = 3; break;
3440 static const struct ieee80211_ops ath5k_hw_ops = {
3442 .start = ath5k_start,
3444 .add_interface = ath5k_add_interface,
3445 .remove_interface = ath5k_remove_interface,
3446 .config = ath5k_config,
3447 .prepare_multicast = ath5k_prepare_multicast,
3448 .configure_filter = ath5k_configure_filter,
3449 .set_key = ath5k_set_key,
3450 .get_stats = ath5k_get_stats,
3451 .get_survey = ath5k_get_survey,
3452 .conf_tx = ath5k_conf_tx,
3453 .get_tsf = ath5k_get_tsf,
3454 .set_tsf = ath5k_set_tsf,
3455 .reset_tsf = ath5k_reset_tsf,
3456 .bss_info_changed = ath5k_bss_info_changed,
3457 .sw_scan_start = ath5k_sw_scan_start,
3458 .sw_scan_complete = ath5k_sw_scan_complete,
3459 .set_coverage_class = ath5k_set_coverage_class,
3460 .set_antenna = ath5k_set_antenna,
3461 .get_antenna = ath5k_get_antenna,
3464 /********************\
3465 * PCI Initialization *
3466 \********************/
3468 static int __devinit
3469 ath5k_pci_probe(struct pci_dev *pdev,
3470 const struct pci_device_id *id)
3473 struct ath5k_softc *sc;
3474 struct ath_common *common;
3475 struct ieee80211_hw *hw;
3480 * L0s needs to be disabled on all ath5k cards.
3482 * For distributions shipping with CONFIG_PCIEASPM (this will be enabled
3483 * by default in the future in 2.6.36) this will also mean both L1 and
3484 * L0s will be disabled when a pre 1.1 PCIe device is detected. We do
3485 * know L1 works correctly even for all ath5k pre 1.1 PCIe devices
3486 * though but cannot currently undue the effect of a blacklist, for
3487 * details you can read pcie_aspm_sanity_check() and see how it adjusts
3488 * the device link capability.
3490 * It may be possible in the future to implement some PCI API to allow
3491 * drivers to override blacklists for pre 1.1 PCIe but for now it is
3492 * best to accept that both L0s and L1 will be disabled completely for
3493 * distributions shipping with CONFIG_PCIEASPM rather than having this
3494 * issue present. Motivation for adding this new API will be to help
3495 * with power consumption for some of these devices.
3497 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S);
3499 ret = pci_enable_device(pdev);
3501 dev_err(&pdev->dev, "can't enable device\n");
3505 /* XXX 32-bit addressing only */
3506 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3508 dev_err(&pdev->dev, "32-bit DMA not available\n");
3513 * Cache line size is used to size and align various
3514 * structures used to communicate with the hardware.
3516 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
3519 * Linux 2.4.18 (at least) writes the cache line size
3520 * register as a 16-bit wide register which is wrong.
3521 * We must have this setup properly for rx buffer
3522 * DMA to work so force a reasonable value here if it
3525 csz = L1_CACHE_BYTES >> 2;
3526 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
3529 * The default setting of latency timer yields poor results,
3530 * set it to the value used by other systems. It may be worth
3531 * tweaking this setting more.
3533 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
3535 /* Enable bus mastering */
3536 pci_set_master(pdev);
3539 * Disable the RETRY_TIMEOUT register (0x41) to keep
3540 * PCI Tx retries from interfering with C3 CPU state.
3542 pci_write_config_byte(pdev, 0x41, 0);
3544 ret = pci_request_region(pdev, 0, "ath5k");
3546 dev_err(&pdev->dev, "cannot reserve PCI memory region\n");
3550 mem = pci_iomap(pdev, 0, 0);
3552 dev_err(&pdev->dev, "cannot remap PCI memory region\n") ;
3558 * Allocate hw (mac80211 main struct)
3559 * and hw->priv (driver private data)
3561 hw = ieee80211_alloc_hw(sizeof(*sc), &ath5k_hw_ops);
3563 dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n");
3568 dev_info(&pdev->dev, "registered as '%s'\n", wiphy_name(hw->wiphy));
3570 /* Initialize driver private data */
3571 SET_IEEE80211_DEV(hw, &pdev->dev);
3572 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
3573 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
3574 IEEE80211_HW_SIGNAL_DBM;
3576 hw->wiphy->interface_modes =
3577 BIT(NL80211_IFTYPE_AP) |
3578 BIT(NL80211_IFTYPE_STATION) |
3579 BIT(NL80211_IFTYPE_ADHOC) |
3580 BIT(NL80211_IFTYPE_MESH_POINT);
3582 hw->extra_tx_headroom = 2;
3583 hw->channel_change_time = 5000;
3589 * Mark the device as detached to avoid processing
3590 * interrupts until setup is complete.
3592 __set_bit(ATH_STAT_INVALID, sc->status);
3594 sc->iobase = mem; /* So we can unmap it on detach */
3595 sc->opmode = NL80211_IFTYPE_STATION;
3597 mutex_init(&sc->lock);
3598 spin_lock_init(&sc->rxbuflock);
3599 spin_lock_init(&sc->txbuflock);
3600 spin_lock_init(&sc->block);
3602 /* Set private data */
3603 pci_set_drvdata(pdev, sc);
3605 /* Setup interrupt handler */
3606 ret = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
3608 ATH5K_ERR(sc, "request_irq failed\n");
3612 /* If we passed the test, malloc an ath5k_hw struct */
3613 sc->ah = kzalloc(sizeof(struct ath5k_hw), GFP_KERNEL);
3616 ATH5K_ERR(sc, "out of memory\n");
3621 sc->ah->ah_iobase = sc->iobase;
3622 common = ath5k_hw_common(sc->ah);
3623 common->ops = &ath5k_common_ops;
3624 common->ah = sc->ah;
3626 common->cachelsz = csz << 2; /* convert to bytes */
3627 spin_lock_init(&common->cc_lock);
3629 /* Initialize device */
3630 ret = ath5k_hw_attach(sc);
3635 /* set up multi-rate retry capabilities */
3636 if (sc->ah->ah_version == AR5K_AR5212) {
3638 hw->max_rate_tries = 11;
3641 hw->vif_data_size = sizeof(struct ath5k_vif);
3643 /* Finish private driver data initialization */
3644 ret = ath5k_attach(pdev, hw);
3648 ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
3649 ath5k_chip_name(AR5K_VERSION_MAC, sc->ah->ah_mac_srev),
3650 sc->ah->ah_mac_srev,
3651 sc->ah->ah_phy_revision);
3653 if (!sc->ah->ah_single_chip) {
3654 /* Single chip radio (!RF5111) */
3655 if (sc->ah->ah_radio_5ghz_revision &&
3656 !sc->ah->ah_radio_2ghz_revision) {
3657 /* No 5GHz support -> report 2GHz radio */
3658 if (!test_bit(AR5K_MODE_11A,
3659 sc->ah->ah_capabilities.cap_mode)) {
3660 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
3661 ath5k_chip_name(AR5K_VERSION_RAD,
3662 sc->ah->ah_radio_5ghz_revision),
3663 sc->ah->ah_radio_5ghz_revision);
3664 /* No 2GHz support (5110 and some
3665 * 5Ghz only cards) -> report 5Ghz radio */
3666 } else if (!test_bit(AR5K_MODE_11B,
3667 sc->ah->ah_capabilities.cap_mode)) {
3668 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
3669 ath5k_chip_name(AR5K_VERSION_RAD,
3670 sc->ah->ah_radio_5ghz_revision),
3671 sc->ah->ah_radio_5ghz_revision);
3672 /* Multiband radio */
3674 ATH5K_INFO(sc, "RF%s multiband radio found"
3676 ath5k_chip_name(AR5K_VERSION_RAD,
3677 sc->ah->ah_radio_5ghz_revision),
3678 sc->ah->ah_radio_5ghz_revision);
3681 /* Multi chip radio (RF5111 - RF2111) ->
3682 * report both 2GHz/5GHz radios */
3683 else if (sc->ah->ah_radio_5ghz_revision &&
3684 sc->ah->ah_radio_2ghz_revision){
3685 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
3686 ath5k_chip_name(AR5K_VERSION_RAD,
3687 sc->ah->ah_radio_5ghz_revision),
3688 sc->ah->ah_radio_5ghz_revision);
3689 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
3690 ath5k_chip_name(AR5K_VERSION_RAD,
3691 sc->ah->ah_radio_2ghz_revision),
3692 sc->ah->ah_radio_2ghz_revision);
3696 ath5k_debug_init_device(sc);
3698 /* ready to process interrupts */
3699 __clear_bit(ATH_STAT_INVALID, sc->status);
3703 ath5k_hw_detach(sc->ah);
3707 free_irq(pdev->irq, sc);
3709 ieee80211_free_hw(hw);
3711 pci_iounmap(pdev, mem);
3713 pci_release_region(pdev, 0);
3715 pci_disable_device(pdev);
3720 static void __devexit
3721 ath5k_pci_remove(struct pci_dev *pdev)
3723 struct ath5k_softc *sc = pci_get_drvdata(pdev);
3725 ath5k_debug_finish_device(sc);
3726 ath5k_detach(pdev, sc->hw);
3727 ath5k_hw_detach(sc->ah);
3729 free_irq(pdev->irq, sc);
3730 pci_iounmap(pdev, sc->iobase);
3731 pci_release_region(pdev, 0);
3732 pci_disable_device(pdev);
3733 ieee80211_free_hw(sc->hw);
3736 #ifdef CONFIG_PM_SLEEP
3737 static int ath5k_pci_suspend(struct device *dev)
3739 struct ath5k_softc *sc = pci_get_drvdata(to_pci_dev(dev));
3745 static int ath5k_pci_resume(struct device *dev)
3747 struct pci_dev *pdev = to_pci_dev(dev);
3748 struct ath5k_softc *sc = pci_get_drvdata(pdev);
3751 * Suspend/Resume resets the PCI configuration space, so we have to
3752 * re-disable the RETRY_TIMEOUT register (0x41) to keep
3753 * PCI Tx retries from interfering with C3 CPU state
3755 pci_write_config_byte(pdev, 0x41, 0);
3757 ath5k_led_enable(sc);
3761 static SIMPLE_DEV_PM_OPS(ath5k_pm_ops, ath5k_pci_suspend, ath5k_pci_resume);
3762 #define ATH5K_PM_OPS (&ath5k_pm_ops)
3764 #define ATH5K_PM_OPS NULL
3765 #endif /* CONFIG_PM_SLEEP */
3767 static struct pci_driver ath5k_pci_driver = {
3768 .name = KBUILD_MODNAME,
3769 .id_table = ath5k_pci_id_table,
3770 .probe = ath5k_pci_probe,
3771 .remove = __devexit_p(ath5k_pci_remove),
3772 .driver.pm = ATH5K_PM_OPS,
3776 * Module init/exit functions
3779 init_ath5k_pci(void)
3783 ret = pci_register_driver(&ath5k_pci_driver);
3785 printk(KERN_ERR "ath5k_pci: can't register pci driver\n");
3793 exit_ath5k_pci(void)
3795 pci_unregister_driver(&ath5k_pci_driver);
3798 module_init(init_ath5k_pci);
3799 module_exit(exit_ath5k_pci);