2 * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
3 * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>
5 * Permission to use, copy, modify, and distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19 /*************************************\
20 * DMA and interrupt masking functions *
21 \*************************************/
24 * dma.c - DMA and interrupt masking functions
26 * Here we setup descriptor pointers (rxdp/txdp) start/stop dma engine and
27 * handle queue setup for 5210 chipset (rest are handled on qcu.c).
28 * Also we setup interrupt mask register (IMR) and read the various interrupt
29 * status registers (ISR).
31 * TODO: Handle SISR on 5211+ and introduce a function to return the queue
32 * number that resulted the interrupt.
45 * ath5k_hw_start_rx_dma - Start DMA receive
47 * @ah: The &struct ath5k_hw
49 void ath5k_hw_start_rx_dma(struct ath5k_hw *ah)
51 ath5k_hw_reg_write(ah, AR5K_CR_RXE, AR5K_CR);
52 ath5k_hw_reg_read(ah, AR5K_CR);
56 * ath5k_hw_stop_rx_dma - Stop DMA receive
58 * @ah: The &struct ath5k_hw
60 static int ath5k_hw_stop_rx_dma(struct ath5k_hw *ah)
64 ath5k_hw_reg_write(ah, AR5K_CR_RXD, AR5K_CR);
67 * It may take some time to disable the DMA receive unit
69 for (i = 1000; i > 0 &&
70 (ath5k_hw_reg_read(ah, AR5K_CR) & AR5K_CR_RXE) != 0;
75 ATH5K_DBG(ah, ATH5K_DEBUG_DMA,
76 "failed to stop RX DMA !\n");
78 return i ? 0 : -EBUSY;
82 * ath5k_hw_get_rxdp - Get RX Descriptor's address
84 * @ah: The &struct ath5k_hw
86 u32 ath5k_hw_get_rxdp(struct ath5k_hw *ah)
88 return ath5k_hw_reg_read(ah, AR5K_RXDP);
92 * ath5k_hw_set_rxdp - Set RX Descriptor's address
94 * @ah: The &struct ath5k_hw
95 * @phys_addr: RX descriptor address
97 * Returns -EIO if rx is active
99 int ath5k_hw_set_rxdp(struct ath5k_hw *ah, u32 phys_addr)
101 if (ath5k_hw_reg_read(ah, AR5K_CR) & AR5K_CR_RXE) {
102 ATH5K_DBG(ah, ATH5K_DEBUG_DMA,
103 "tried to set RXDP while rx was active !\n");
107 ath5k_hw_reg_write(ah, phys_addr, AR5K_RXDP);
117 * ath5k_hw_start_tx_dma - Start DMA transmit for a specific queue
119 * @ah: The &struct ath5k_hw
120 * @queue: The hw queue number
122 * Start DMA transmit for a specific queue and since 5210 doesn't have
123 * QCU/DCU, set up queue parameters for 5210 here based on queue type (one
124 * queue for normal data and one queue for beacons). For queue setup
125 * on newer chips check out qcu.c. Returns -EINVAL if queue number is out
126 * of range or if queue is already disabled.
128 * NOTE: Must be called after setting up tx control descriptor for that
131 int ath5k_hw_start_tx_dma(struct ath5k_hw *ah, unsigned int queue)
135 AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);
137 /* Return if queue is declared inactive */
138 if (ah->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE)
141 if (ah->ah_version == AR5K_AR5210) {
142 tx_queue = ath5k_hw_reg_read(ah, AR5K_CR);
145 * Set the queue by type on 5210
147 switch (ah->ah_txq[queue].tqi_type) {
148 case AR5K_TX_QUEUE_DATA:
149 tx_queue |= AR5K_CR_TXE0 & ~AR5K_CR_TXD0;
151 case AR5K_TX_QUEUE_BEACON:
152 tx_queue |= AR5K_CR_TXE1 & ~AR5K_CR_TXD1;
153 ath5k_hw_reg_write(ah, AR5K_BCR_TQ1V | AR5K_BCR_BDMAE,
156 case AR5K_TX_QUEUE_CAB:
157 tx_queue |= AR5K_CR_TXE1 & ~AR5K_CR_TXD1;
158 ath5k_hw_reg_write(ah, AR5K_BCR_TQ1FV | AR5K_BCR_TQ1V |
159 AR5K_BCR_BDMAE, AR5K_BSR);
165 ath5k_hw_reg_write(ah, tx_queue, AR5K_CR);
166 ath5k_hw_reg_read(ah, AR5K_CR);
168 /* Return if queue is disabled */
169 if (AR5K_REG_READ_Q(ah, AR5K_QCU_TXD, queue))
173 AR5K_REG_WRITE_Q(ah, AR5K_QCU_TXE, queue);
180 * ath5k_hw_stop_tx_dma - Stop DMA transmit on a specific queue
182 * @ah: The &struct ath5k_hw
183 * @queue: The hw queue number
185 * Stop DMA transmit on a specific hw queue and drain queue so we don't
186 * have any pending frames. Returns -EBUSY if we still have pending frames,
187 * -EINVAL if queue number is out of range or inactive.
190 static int ath5k_hw_stop_tx_dma(struct ath5k_hw *ah, unsigned int queue)
193 u32 tx_queue, pending;
195 AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);
197 /* Return if queue is declared inactive */
198 if (ah->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE)
201 if (ah->ah_version == AR5K_AR5210) {
202 tx_queue = ath5k_hw_reg_read(ah, AR5K_CR);
207 switch (ah->ah_txq[queue].tqi_type) {
208 case AR5K_TX_QUEUE_DATA:
209 tx_queue |= AR5K_CR_TXD0 & ~AR5K_CR_TXE0;
211 case AR5K_TX_QUEUE_BEACON:
212 case AR5K_TX_QUEUE_CAB:
214 tx_queue |= AR5K_CR_TXD1 & ~AR5K_CR_TXD1;
215 ath5k_hw_reg_write(ah, 0, AR5K_BSR);
222 ath5k_hw_reg_write(ah, tx_queue, AR5K_CR);
223 ath5k_hw_reg_read(ah, AR5K_CR);
227 * Enable DCU early termination to quickly
228 * flush any pending frames from QCU
230 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue),
231 AR5K_QCU_MISC_DCU_EARLY);
234 * Schedule TX disable and wait until queue is empty
236 AR5K_REG_WRITE_Q(ah, AR5K_QCU_TXD, queue);
238 /* Wait for queue to stop */
239 for (i = 1000; i > 0 &&
240 (AR5K_REG_READ_Q(ah, AR5K_QCU_TXE, queue) != 0);
244 if (AR5K_REG_READ_Q(ah, AR5K_QCU_TXE, queue))
245 ATH5K_DBG(ah, ATH5K_DEBUG_DMA,
246 "queue %i didn't stop !\n", queue);
248 /* Check for pending frames */
251 pending = ath5k_hw_reg_read(ah,
252 AR5K_QUEUE_STATUS(queue)) &
253 AR5K_QCU_STS_FRMPENDCNT;
255 } while (--i && pending);
257 /* For 2413+ order PCU to drop packets using
259 if (ah->ah_mac_version >= (AR5K_SREV_AR2414 >> 4) &&
261 /* Set periodicity and duration */
262 ath5k_hw_reg_write(ah,
263 AR5K_REG_SM(100, AR5K_QUIET_CTL2_QT_PER)|
264 AR5K_REG_SM(10, AR5K_QUIET_CTL2_QT_DUR),
267 /* Enable quiet period for current TSF */
268 ath5k_hw_reg_write(ah,
269 AR5K_QUIET_CTL1_QT_EN |
270 AR5K_REG_SM(ath5k_hw_reg_read(ah,
271 AR5K_TSF_L32_5211) >> 10,
272 AR5K_QUIET_CTL1_NEXT_QT_TSF),
275 /* Force channel idle high */
276 AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW_5211,
277 AR5K_DIAG_SW_CHANNEL_IDLE_HIGH);
279 /* Wait a while and disable mechanism */
281 AR5K_REG_DISABLE_BITS(ah, AR5K_QUIET_CTL1,
282 AR5K_QUIET_CTL1_QT_EN);
284 /* Re-check for pending frames */
287 pending = ath5k_hw_reg_read(ah,
288 AR5K_QUEUE_STATUS(queue)) &
289 AR5K_QCU_STS_FRMPENDCNT;
291 } while (--i && pending);
293 AR5K_REG_DISABLE_BITS(ah, AR5K_DIAG_SW_5211,
294 AR5K_DIAG_SW_CHANNEL_IDLE_HIGH);
297 ATH5K_DBG(ah, ATH5K_DEBUG_DMA,
298 "quiet mechanism didn't work q:%i !\n",
303 * Disable DCU early termination
305 AR5K_REG_DISABLE_BITS(ah, AR5K_QUEUE_MISC(queue),
306 AR5K_QCU_MISC_DCU_EARLY);
309 ath5k_hw_reg_write(ah, 0, AR5K_QCU_TXD);
311 ATH5K_DBG(ah, ATH5K_DEBUG_DMA,
312 "tx dma didn't stop (q:%i, frm:%i) !\n",
318 /* TODO: Check for success on 5210 else return error */
323 * ath5k_hw_stop_beacon_queue - Stop beacon queue
325 * @ah The &struct ath5k_hw
326 * @queue The queue number
328 * Returns -EIO if queue didn't stop
330 int ath5k_hw_stop_beacon_queue(struct ath5k_hw *ah, unsigned int queue)
333 ret = ath5k_hw_stop_tx_dma(ah, queue);
335 ATH5K_DBG(ah, ATH5K_DEBUG_DMA,
336 "beacon queue didn't stop !\n");
343 * ath5k_hw_get_txdp - Get TX Descriptor's address for a specific queue
345 * @ah: The &struct ath5k_hw
346 * @queue: The hw queue number
348 * Get TX descriptor's address for a specific queue. For 5210 we ignore
349 * the queue number and use tx queue type since we only have 2 queues.
350 * We use TXDP0 for normal data queue and TXDP1 for beacon queue.
351 * For newer chips with QCU/DCU we just read the corresponding TXDP register.
353 * XXX: Is TXDP read and clear ?
355 u32 ath5k_hw_get_txdp(struct ath5k_hw *ah, unsigned int queue)
359 AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);
362 * Get the transmit queue descriptor pointer from the selected queue
364 /*5210 doesn't have QCU*/
365 if (ah->ah_version == AR5K_AR5210) {
366 switch (ah->ah_txq[queue].tqi_type) {
367 case AR5K_TX_QUEUE_DATA:
368 tx_reg = AR5K_NOQCU_TXDP0;
370 case AR5K_TX_QUEUE_BEACON:
371 case AR5K_TX_QUEUE_CAB:
372 tx_reg = AR5K_NOQCU_TXDP1;
378 tx_reg = AR5K_QUEUE_TXDP(queue);
381 return ath5k_hw_reg_read(ah, tx_reg);
385 * ath5k_hw_set_txdp - Set TX Descriptor's address for a specific queue
387 * @ah: The &struct ath5k_hw
388 * @queue: The hw queue number
390 * Set TX descriptor's address for a specific queue. For 5210 we ignore
391 * the queue number and we use tx queue type since we only have 2 queues
392 * so as above we use TXDP0 for normal data queue and TXDP1 for beacon queue.
393 * For newer chips with QCU/DCU we just set the corresponding TXDP register.
394 * Returns -EINVAL if queue type is invalid for 5210 and -EIO if queue is still
397 int ath5k_hw_set_txdp(struct ath5k_hw *ah, unsigned int queue, u32 phys_addr)
401 AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);
404 * Set the transmit queue descriptor pointer register by type
407 if (ah->ah_version == AR5K_AR5210) {
408 switch (ah->ah_txq[queue].tqi_type) {
409 case AR5K_TX_QUEUE_DATA:
410 tx_reg = AR5K_NOQCU_TXDP0;
412 case AR5K_TX_QUEUE_BEACON:
413 case AR5K_TX_QUEUE_CAB:
414 tx_reg = AR5K_NOQCU_TXDP1;
421 * Set the transmit queue descriptor pointer for
422 * the selected queue on QCU for 5211+
423 * (this won't work if the queue is still active)
425 if (AR5K_REG_READ_Q(ah, AR5K_QCU_TXE, queue))
428 tx_reg = AR5K_QUEUE_TXDP(queue);
431 /* Set descriptor pointer */
432 ath5k_hw_reg_write(ah, phys_addr, tx_reg);
438 * ath5k_hw_update_tx_triglevel - Update tx trigger level
440 * @ah: The &struct ath5k_hw
441 * @increase: Flag to force increase of trigger level
443 * This function increases/decreases the tx trigger level for the tx fifo
444 * buffer (aka FIFO threshold) that is used to indicate when PCU flushes
445 * the buffer and transmits its data. Lowering this results sending small
446 * frames more quickly but can lead to tx underruns, raising it a lot can
447 * result other problems (i think bmiss is related). Right now we start with
448 * the lowest possible (64Bytes) and if we get tx underrun we increase it using
449 * the increase flag. Returns -EIO if we have reached maximum/minimum.
451 * XXX: Link this with tx DMA size ?
452 * XXX: Use it to save interrupts ?
453 * TODO: Needs testing, i think it's related to bmiss...
455 int ath5k_hw_update_tx_triglevel(struct ath5k_hw *ah, bool increase)
457 u32 trigger_level, imr;
461 * Disable interrupts by setting the mask
463 imr = ath5k_hw_set_imr(ah, ah->ah_imr & ~AR5K_INT_GLOBAL);
465 trigger_level = AR5K_REG_MS(ath5k_hw_reg_read(ah, AR5K_TXCFG),
469 if (--trigger_level < AR5K_TUNE_MIN_TX_FIFO_THRES)
473 ((AR5K_TUNE_MAX_TX_FIFO_THRES - trigger_level) / 2);
476 * Update trigger level on success
478 if (ah->ah_version == AR5K_AR5210)
479 ath5k_hw_reg_write(ah, trigger_level, AR5K_TRIG_LVL);
481 AR5K_REG_WRITE_BITS(ah, AR5K_TXCFG,
482 AR5K_TXCFG_TXFULL, trigger_level);
488 * Restore interrupt mask
490 ath5k_hw_set_imr(ah, imr);
496 /*******************\
497 * Interrupt masking *
498 \*******************/
501 * ath5k_hw_is_intr_pending - Check if we have pending interrupts
503 * @ah: The &struct ath5k_hw
505 * Check if we have pending interrupts to process. Returns 1 if we
506 * have pending interrupts and 0 if we haven't.
508 bool ath5k_hw_is_intr_pending(struct ath5k_hw *ah)
510 return ath5k_hw_reg_read(ah, AR5K_INTPEND) == 1 ? 1 : 0;
514 * ath5k_hw_get_isr - Get interrupt status
516 * @ah: The @struct ath5k_hw
517 * @interrupt_mask: Driver's interrupt mask used to filter out
520 * This function is used inside our interrupt handler to determine the reason
521 * for the interrupt by reading Primary Interrupt Status Register. Returns an
522 * abstract interrupt status mask which is mostly ISR with some uncommon bits
523 * being mapped on some standard non hw-specific positions
524 * (check out &ath5k_int).
526 * NOTE: We use read-and-clear register, so after this function is called ISR
529 int ath5k_hw_get_isr(struct ath5k_hw *ah, enum ath5k_int *interrupt_mask)
534 * Read interrupt status from the Interrupt Status register
537 if (ah->ah_version == AR5K_AR5210) {
538 data = ath5k_hw_reg_read(ah, AR5K_ISR);
539 if (unlikely(data == AR5K_INT_NOCARD)) {
540 *interrupt_mask = data;
545 * Read interrupt status from Interrupt
546 * Status Register shadow copy (Read And Clear)
548 * Note: PISR/SISR Not available on 5210
550 data = ath5k_hw_reg_read(ah, AR5K_RAC_PISR);
551 if (unlikely(data == AR5K_INT_NOCARD)) {
552 *interrupt_mask = data;
558 * Get abstract interrupt mask (driver-compatible)
560 *interrupt_mask = (data & AR5K_INT_COMMON) & ah->ah_imr;
562 if (ah->ah_version != AR5K_AR5210) {
563 u32 sisr2 = ath5k_hw_reg_read(ah, AR5K_RAC_SISR2);
565 /*HIU = Host Interface Unit (PCI etc)*/
566 if (unlikely(data & (AR5K_ISR_HIUERR)))
567 *interrupt_mask |= AR5K_INT_FATAL;
570 if (unlikely(data & (AR5K_ISR_BNR)))
571 *interrupt_mask |= AR5K_INT_BNR;
573 if (unlikely(sisr2 & (AR5K_SISR2_SSERR |
576 *interrupt_mask |= AR5K_INT_FATAL;
578 if (data & AR5K_ISR_TIM)
579 *interrupt_mask |= AR5K_INT_TIM;
581 if (data & AR5K_ISR_BCNMISC) {
582 if (sisr2 & AR5K_SISR2_TIM)
583 *interrupt_mask |= AR5K_INT_TIM;
584 if (sisr2 & AR5K_SISR2_DTIM)
585 *interrupt_mask |= AR5K_INT_DTIM;
586 if (sisr2 & AR5K_SISR2_DTIM_SYNC)
587 *interrupt_mask |= AR5K_INT_DTIM_SYNC;
588 if (sisr2 & AR5K_SISR2_BCN_TIMEOUT)
589 *interrupt_mask |= AR5K_INT_BCN_TIMEOUT;
590 if (sisr2 & AR5K_SISR2_CAB_TIMEOUT)
591 *interrupt_mask |= AR5K_INT_CAB_TIMEOUT;
594 if (data & AR5K_ISR_RXDOPPLER)
595 *interrupt_mask |= AR5K_INT_RX_DOPPLER;
596 if (data & AR5K_ISR_QCBRORN) {
597 *interrupt_mask |= AR5K_INT_QCBRORN;
598 ah->ah_txq_isr |= AR5K_REG_MS(
599 ath5k_hw_reg_read(ah, AR5K_RAC_SISR3),
602 if (data & AR5K_ISR_QCBRURN) {
603 *interrupt_mask |= AR5K_INT_QCBRURN;
604 ah->ah_txq_isr |= AR5K_REG_MS(
605 ath5k_hw_reg_read(ah, AR5K_RAC_SISR3),
608 if (data & AR5K_ISR_QTRIG) {
609 *interrupt_mask |= AR5K_INT_QTRIG;
610 ah->ah_txq_isr |= AR5K_REG_MS(
611 ath5k_hw_reg_read(ah, AR5K_RAC_SISR4),
615 if (data & AR5K_ISR_TXOK)
616 ah->ah_txq_isr |= AR5K_REG_MS(
617 ath5k_hw_reg_read(ah, AR5K_RAC_SISR0),
618 AR5K_SISR0_QCU_TXOK);
620 if (data & AR5K_ISR_TXDESC)
621 ah->ah_txq_isr |= AR5K_REG_MS(
622 ath5k_hw_reg_read(ah, AR5K_RAC_SISR0),
623 AR5K_SISR0_QCU_TXDESC);
625 if (data & AR5K_ISR_TXERR)
626 ah->ah_txq_isr |= AR5K_REG_MS(
627 ath5k_hw_reg_read(ah, AR5K_RAC_SISR1),
628 AR5K_SISR1_QCU_TXERR);
630 if (data & AR5K_ISR_TXEOL)
631 ah->ah_txq_isr |= AR5K_REG_MS(
632 ath5k_hw_reg_read(ah, AR5K_RAC_SISR1),
633 AR5K_SISR1_QCU_TXEOL);
635 if (data & AR5K_ISR_TXURN)
636 ah->ah_txq_isr |= AR5K_REG_MS(
637 ath5k_hw_reg_read(ah, AR5K_RAC_SISR2),
638 AR5K_SISR2_QCU_TXURN);
640 if (unlikely(data & (AR5K_ISR_SSERR | AR5K_ISR_MCABT
641 | AR5K_ISR_HIUERR | AR5K_ISR_DPERR)))
642 *interrupt_mask |= AR5K_INT_FATAL;
645 * XXX: BMISS interrupts may occur after association.
646 * I found this on 5210 code but it needs testing. If this is
647 * true we should disable them before assoc and re-enable them
648 * after a successful assoc + some jiffies.
649 interrupt_mask &= ~AR5K_INT_BMISS;
654 * In case we didn't handle anything,
655 * print the register value.
657 if (unlikely(*interrupt_mask == 0 && net_ratelimit()))
658 ATH5K_PRINTF("ISR: 0x%08x IMR: 0x%08x\n", data, ah->ah_imr);
664 * ath5k_hw_set_imr - Set interrupt mask
666 * @ah: The &struct ath5k_hw
667 * @new_mask: The new interrupt mask to be set
669 * Set the interrupt mask in hw to save interrupts. We do that by mapping
670 * ath5k_int bits to hw-specific bits to remove abstraction and writing
671 * Interrupt Mask Register.
673 enum ath5k_int ath5k_hw_set_imr(struct ath5k_hw *ah, enum ath5k_int new_mask)
675 enum ath5k_int old_mask, int_mask;
677 old_mask = ah->ah_imr;
680 * Disable card interrupts to prevent any race conditions
681 * (they will be re-enabled afterwards if AR5K_INT GLOBAL
682 * is set again on the new mask).
684 if (old_mask & AR5K_INT_GLOBAL) {
685 ath5k_hw_reg_write(ah, AR5K_IER_DISABLE, AR5K_IER);
686 ath5k_hw_reg_read(ah, AR5K_IER);
690 * Add additional, chipset-dependent interrupt mask flags
691 * and write them to the IMR (interrupt mask register).
693 int_mask = new_mask & AR5K_INT_COMMON;
695 if (ah->ah_version != AR5K_AR5210) {
696 /* Preserve per queue TXURN interrupt mask */
697 u32 simr2 = ath5k_hw_reg_read(ah, AR5K_SIMR2)
698 & AR5K_SIMR2_QCU_TXURN;
700 if (new_mask & AR5K_INT_FATAL) {
701 int_mask |= AR5K_IMR_HIUERR;
702 simr2 |= (AR5K_SIMR2_MCABT | AR5K_SIMR2_SSERR
707 if (new_mask & AR5K_INT_BNR)
708 int_mask |= AR5K_INT_BNR;
710 if (new_mask & AR5K_INT_TIM)
711 int_mask |= AR5K_IMR_TIM;
713 if (new_mask & AR5K_INT_TIM)
714 simr2 |= AR5K_SISR2_TIM;
715 if (new_mask & AR5K_INT_DTIM)
716 simr2 |= AR5K_SISR2_DTIM;
717 if (new_mask & AR5K_INT_DTIM_SYNC)
718 simr2 |= AR5K_SISR2_DTIM_SYNC;
719 if (new_mask & AR5K_INT_BCN_TIMEOUT)
720 simr2 |= AR5K_SISR2_BCN_TIMEOUT;
721 if (new_mask & AR5K_INT_CAB_TIMEOUT)
722 simr2 |= AR5K_SISR2_CAB_TIMEOUT;
724 if (new_mask & AR5K_INT_RX_DOPPLER)
725 int_mask |= AR5K_IMR_RXDOPPLER;
727 /* Note: Per queue interrupt masks
728 * are set via ath5k_hw_reset_tx_queue() (qcu.c) */
729 ath5k_hw_reg_write(ah, int_mask, AR5K_PIMR);
730 ath5k_hw_reg_write(ah, simr2, AR5K_SIMR2);
733 if (new_mask & AR5K_INT_FATAL)
734 int_mask |= (AR5K_IMR_SSERR | AR5K_IMR_MCABT
735 | AR5K_IMR_HIUERR | AR5K_IMR_DPERR);
737 ath5k_hw_reg_write(ah, int_mask, AR5K_IMR);
740 /* If RXNOFRM interrupt is masked disable it
741 * by setting AR5K_RXNOFRM to zero */
742 if (!(new_mask & AR5K_INT_RXNOFRM))
743 ath5k_hw_reg_write(ah, 0, AR5K_RXNOFRM);
745 /* Store new interrupt mask */
746 ah->ah_imr = new_mask;
748 /* ..re-enable interrupts if AR5K_INT_GLOBAL is set */
749 if (new_mask & AR5K_INT_GLOBAL) {
750 ath5k_hw_reg_write(ah, AR5K_IER_ENABLE, AR5K_IER);
751 ath5k_hw_reg_read(ah, AR5K_IER);
758 /********************\
760 \********************/
763 * ath5k_hw_dma_init - Initialize DMA unit
765 * @ah: The &struct ath5k_hw
767 * Set DMA size and pre-enable interrupts
768 * (driver handles tx/rx buffer setup and
771 * XXX: Save/restore RXDP/TXDP registers ?
773 void ath5k_hw_dma_init(struct ath5k_hw *ah)
776 * Set Rx/Tx DMA Configuration
778 * Set standard DMA size (128). Note that
779 * a DMA size of 512 causes rx overruns and tx errors
780 * on pci-e cards (tested on 5424 but since rx overruns
781 * also occur on 5416/5418 with madwifi we set 128
782 * for all PCI-E cards to be safe).
784 * XXX: need to check 5210 for this
785 * TODO: Check out tx trigger level, it's always 64 on dumps but I
786 * guess we can tweak it and see how it goes ;-)
788 if (ah->ah_version != AR5K_AR5210) {
789 AR5K_REG_WRITE_BITS(ah, AR5K_TXCFG,
790 AR5K_TXCFG_SDMAMR, AR5K_DMASIZE_128B);
791 AR5K_REG_WRITE_BITS(ah, AR5K_RXCFG,
792 AR5K_RXCFG_SDMAMW, AR5K_DMASIZE_128B);
795 /* Pre-enable interrupts on 5211/5212*/
796 if (ah->ah_version != AR5K_AR5210)
797 ath5k_hw_set_imr(ah, ah->ah_imr);
802 * ath5k_hw_dma_stop - stop DMA unit
804 * @ah: The &struct ath5k_hw
806 * Stop tx/rx DMA and interrupts. Returns
807 * -EBUSY if tx or rx dma failed to stop.
809 * XXX: Sometimes DMA unit hangs and we have
810 * stuck frames on tx queues, only a reset
813 int ath5k_hw_dma_stop(struct ath5k_hw *ah)
818 /* Disable interrupts */
819 ath5k_hw_set_imr(ah, 0);
822 err = ath5k_hw_stop_rx_dma(ah);
826 /* Clear any pending interrupts
827 * and disable tx dma */
828 if (ah->ah_version != AR5K_AR5210) {
829 ath5k_hw_reg_write(ah, 0xffffffff, AR5K_PISR);
830 qmax = AR5K_NUM_TX_QUEUES;
832 /* PISR/SISR Not available on 5210 */
833 ath5k_hw_reg_read(ah, AR5K_ISR);
834 qmax = AR5K_NUM_TX_QUEUES_NOQCU;
837 for (i = 0; i < qmax; i++) {
838 err = ath5k_hw_stop_tx_dma(ah, i);
839 /* -EINVAL -> queue inactive */
840 if (err && err != -EINVAL)