2 * Copyright (c) 2008-2009 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <linux/nl80211.h>
18 #include <linux/pci.h>
19 #include <linux/pci-aspm.h>
20 #include <linux/etherdevice.h>
28 static DEFINE_PCI_DEVICE_TABLE(ath5k_pci_id_table) = {
29 { PCI_VDEVICE(ATHEROS, 0x0207) }, /* 5210 early */
30 { PCI_VDEVICE(ATHEROS, 0x0007) }, /* 5210 */
31 { PCI_VDEVICE(ATHEROS, 0x0011) }, /* 5311 - this is on AHB bus !*/
32 { PCI_VDEVICE(ATHEROS, 0x0012) }, /* 5211 */
33 { PCI_VDEVICE(ATHEROS, 0x0013) }, /* 5212 */
34 { PCI_VDEVICE(3COM_2, 0x0013) }, /* 3com 5212 */
35 { PCI_VDEVICE(3COM, 0x0013) }, /* 3com 3CRDAG675 5212 */
36 { PCI_VDEVICE(ATHEROS, 0x1014) }, /* IBM minipci 5212 */
37 { PCI_VDEVICE(ATHEROS, 0x0014) }, /* 5212 combatible */
38 { PCI_VDEVICE(ATHEROS, 0x0015) }, /* 5212 combatible */
39 { PCI_VDEVICE(ATHEROS, 0x0016) }, /* 5212 combatible */
40 { PCI_VDEVICE(ATHEROS, 0x0017) }, /* 5212 combatible */
41 { PCI_VDEVICE(ATHEROS, 0x0018) }, /* 5212 combatible */
42 { PCI_VDEVICE(ATHEROS, 0x0019) }, /* 5212 combatible */
43 { PCI_VDEVICE(ATHEROS, 0x001a) }, /* 2413 Griffin-lite */
44 { PCI_VDEVICE(ATHEROS, 0x001b) }, /* 5413 Eagle */
45 { PCI_VDEVICE(ATHEROS, 0x001c) }, /* PCI-E cards */
46 { PCI_VDEVICE(ATHEROS, 0x001d) }, /* 2417 Nala */
49 MODULE_DEVICE_TABLE(pci, ath5k_pci_id_table);
51 /* return bus cachesize in 4B word units */
52 static void ath5k_pci_read_cachesize(struct ath_common *common, int *csz)
54 struct ath5k_softc *sc = (struct ath5k_softc *) common->priv;
57 pci_read_config_byte(sc->pdev, PCI_CACHE_LINE_SIZE, &u8tmp);
61 * This check was put in to avoid "unpleasant" consequences if
62 * the bootrom has not fully initialized all PCI devices.
63 * Sometimes the cache line size register is not set
67 *csz = L1_CACHE_BYTES >> 2; /* Use the default size */
74 ath5k_pci_eeprom_read(struct ath_common *common, u32 offset, u16 *data)
76 struct ath5k_hw *ah = (struct ath5k_hw *) common->ah;
80 * Initialize EEPROM access
82 if (ah->ah_version == AR5K_AR5210) {
83 AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, AR5K_PCICFG_EEAE);
84 (void)ath5k_hw_reg_read(ah, AR5K_EEPROM_BASE + (4 * offset));
86 ath5k_hw_reg_write(ah, offset, AR5K_EEPROM_BASE);
87 AR5K_REG_ENABLE_BITS(ah, AR5K_EEPROM_CMD,
88 AR5K_EEPROM_CMD_READ);
91 for (timeout = AR5K_TUNE_REGISTER_TIMEOUT; timeout > 0; timeout--) {
92 status = ath5k_hw_reg_read(ah, AR5K_EEPROM_STATUS);
93 if (status & AR5K_EEPROM_STAT_RDDONE) {
94 if (status & AR5K_EEPROM_STAT_RDERR)
96 *data = (u16)(ath5k_hw_reg_read(ah, AR5K_EEPROM_DATA) &
106 int ath5k_hw_read_srev(struct ath5k_hw *ah)
108 ah->ah_mac_srev = ath5k_hw_reg_read(ah, AR5K_SREV);
113 * Read the MAC address from eeprom or platform_data
115 static int ath5k_pci_eeprom_read_mac(struct ath5k_hw *ah, u8 *mac)
117 u8 mac_d[ETH_ALEN] = {};
122 AR5K_EEPROM_READ(0x20, data);
124 for (offset = 0x1f, octet = 0, total = 0; offset >= 0x1d; offset--) {
125 AR5K_EEPROM_READ(offset, data);
128 mac_d[octet + 1] = data & 0xff;
129 mac_d[octet] = data >> 8;
133 if (!total || total == 3 * 0xffff)
136 memcpy(mac, mac_d, ETH_ALEN);
142 /* Common ath_bus_opts structure */
143 static const struct ath_bus_ops ath_pci_bus_ops = {
144 .ath_bus_type = ATH_PCI,
145 .read_cachesize = ath5k_pci_read_cachesize,
146 .eeprom_read = ath5k_pci_eeprom_read,
147 .eeprom_read_mac = ath5k_pci_eeprom_read_mac,
150 /********************\
151 * PCI Initialization *
152 \********************/
155 ath5k_pci_probe(struct pci_dev *pdev,
156 const struct pci_device_id *id)
159 struct ath5k_softc *sc;
160 struct ieee80211_hw *hw;
165 * L0s needs to be disabled on all ath5k cards.
167 * For distributions shipping with CONFIG_PCIEASPM (this will be enabled
168 * by default in the future in 2.6.36) this will also mean both L1 and
169 * L0s will be disabled when a pre 1.1 PCIe device is detected. We do
170 * know L1 works correctly even for all ath5k pre 1.1 PCIe devices
171 * though but cannot currently undue the effect of a blacklist, for
172 * details you can read pcie_aspm_sanity_check() and see how it adjusts
173 * the device link capability.
175 * It may be possible in the future to implement some PCI API to allow
176 * drivers to override blacklists for pre 1.1 PCIe but for now it is
177 * best to accept that both L0s and L1 will be disabled completely for
178 * distributions shipping with CONFIG_PCIEASPM rather than having this
179 * issue present. Motivation for adding this new API will be to help
180 * with power consumption for some of these devices.
182 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S);
184 ret = pci_enable_device(pdev);
186 dev_err(&pdev->dev, "can't enable device\n");
190 /* XXX 32-bit addressing only */
191 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
193 dev_err(&pdev->dev, "32-bit DMA not available\n");
198 * Cache line size is used to size and align various
199 * structures used to communicate with the hardware.
201 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
204 * Linux 2.4.18 (at least) writes the cache line size
205 * register as a 16-bit wide register which is wrong.
206 * We must have this setup properly for rx buffer
207 * DMA to work so force a reasonable value here if it
210 csz = L1_CACHE_BYTES >> 2;
211 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
214 * The default setting of latency timer yields poor results,
215 * set it to the value used by other systems. It may be worth
216 * tweaking this setting more.
218 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
220 /* Enable bus mastering */
221 pci_set_master(pdev);
224 * Disable the RETRY_TIMEOUT register (0x41) to keep
225 * PCI Tx retries from interfering with C3 CPU state.
227 pci_write_config_byte(pdev, 0x41, 0);
229 ret = pci_request_region(pdev, 0, "ath5k");
231 dev_err(&pdev->dev, "cannot reserve PCI memory region\n");
235 mem = pci_iomap(pdev, 0, 0);
237 dev_err(&pdev->dev, "cannot remap PCI memory region\n");
243 * Allocate hw (mac80211 main struct)
244 * and hw->priv (driver private data)
246 hw = ieee80211_alloc_hw(sizeof(*sc), &ath5k_hw_ops);
248 dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n");
253 dev_info(&pdev->dev, "registered as '%s'\n", wiphy_name(hw->wiphy));
258 sc->dev = &pdev->dev;
260 sc->devid = id->device;
261 sc->iobase = mem; /* So we can unmap it on detach */
264 ret = ath5k_init_softc(sc, &ath_pci_bus_ops);
268 /* Set private data */
269 pci_set_drvdata(pdev, hw);
273 ieee80211_free_hw(hw);
275 pci_iounmap(pdev, mem);
277 pci_release_region(pdev, 0);
279 pci_disable_device(pdev);
284 static void __devexit
285 ath5k_pci_remove(struct pci_dev *pdev)
287 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
288 struct ath5k_softc *sc = hw->priv;
290 ath5k_deinit_softc(sc);
291 pci_iounmap(pdev, sc->iobase);
292 pci_release_region(pdev, 0);
293 pci_disable_device(pdev);
294 ieee80211_free_hw(hw);
297 #ifdef CONFIG_PM_SLEEP
298 static int ath5k_pci_suspend(struct device *dev)
300 struct pci_dev *pdev = to_pci_dev(dev);
301 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
302 struct ath5k_softc *sc = hw->priv;
308 static int ath5k_pci_resume(struct device *dev)
310 struct pci_dev *pdev = to_pci_dev(dev);
311 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
312 struct ath5k_softc *sc = hw->priv;
315 * Suspend/Resume resets the PCI configuration space, so we have to
316 * re-disable the RETRY_TIMEOUT register (0x41) to keep
317 * PCI Tx retries from interfering with C3 CPU state
319 pci_write_config_byte(pdev, 0x41, 0);
321 ath5k_led_enable(sc);
325 static SIMPLE_DEV_PM_OPS(ath5k_pm_ops, ath5k_pci_suspend, ath5k_pci_resume);
326 #define ATH5K_PM_OPS (&ath5k_pm_ops)
328 #define ATH5K_PM_OPS NULL
329 #endif /* CONFIG_PM_SLEEP */
331 static struct pci_driver ath5k_pci_driver = {
332 .name = KBUILD_MODNAME,
333 .id_table = ath5k_pci_id_table,
334 .probe = ath5k_pci_probe,
335 .remove = __devexit_p(ath5k_pci_remove),
336 .driver.pm = ATH5K_PM_OPS,
340 * Module init/exit functions
347 ret = pci_register_driver(&ath5k_pci_driver);
349 printk(KERN_ERR "ath5k_pci: can't register pci driver\n");
359 pci_unregister_driver(&ath5k_pci_driver);
362 module_init(init_ath5k_pci);
363 module_exit(exit_ath5k_pci);