4 * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org>
5 * Copyright (c) 2006-2009 Nick Kossifidis <mickflemm@gmail.com>
6 * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com>
7 * Copyright (c) 2008-2009 Felix Fietkau <nbd@openwrt.org>
9 * Permission to use, copy, modify, and distribute this software for any
10 * purpose with or without fee is hereby granted, provided that the above
11 * copyright notice and this permission notice appear in all copies.
13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
18 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
19 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
23 #include <linux/delay.h>
24 #include <linux/slab.h>
25 #include <asm/unaligned.h>
39 * Get the PHY Chip revision
41 u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, enum ieee80211_band band)
48 * Set the radio chip access register
51 case IEEE80211_BAND_2GHZ:
52 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_2GHZ, AR5K_PHY(0));
54 case IEEE80211_BAND_5GHZ:
55 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0));
63 /* ...wait until PHY is ready and read the selected radio revision */
64 ath5k_hw_reg_write(ah, 0x00001c16, AR5K_PHY(0x34));
66 for (i = 0; i < 8; i++)
67 ath5k_hw_reg_write(ah, 0x00010000, AR5K_PHY(0x20));
69 if (ah->ah_version == AR5K_AR5210) {
70 srev = ath5k_hw_reg_read(ah, AR5K_PHY(256) >> 28) & 0xf;
71 ret = (u16)ath5k_hw_bitswap(srev, 4) + 1;
73 srev = (ath5k_hw_reg_read(ah, AR5K_PHY(0x100)) >> 24) & 0xff;
74 ret = (u16)ath5k_hw_bitswap(((srev & 0xf0) >> 4) |
75 ((srev & 0x0f) << 4), 8);
78 /* Reset to the 5GHz mode */
79 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0));
85 * Check if a channel is supported
87 bool ath5k_channel_ok(struct ath5k_hw *ah, struct ieee80211_channel *channel)
89 u16 freq = channel->center_freq;
91 /* Check if the channel is in our supported range */
92 if (channel->band == IEEE80211_BAND_2GHZ) {
93 if ((freq >= ah->ah_capabilities.cap_range.range_2ghz_min) &&
94 (freq <= ah->ah_capabilities.cap_range.range_2ghz_max))
96 } else if (channel->band == IEEE80211_BAND_5GHZ)
97 if ((freq >= ah->ah_capabilities.cap_range.range_5ghz_min) &&
98 (freq <= ah->ah_capabilities.cap_range.range_5ghz_max))
104 bool ath5k_hw_chan_has_spur_noise(struct ath5k_hw *ah,
105 struct ieee80211_channel *channel)
109 if ((ah->ah_radio == AR5K_RF5112) ||
110 (ah->ah_radio == AR5K_RF5413) ||
111 (ah->ah_radio == AR5K_RF2413) ||
112 (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4)))
117 if ((channel->center_freq % refclk_freq != 0) &&
118 ((channel->center_freq % refclk_freq < 10) ||
119 (channel->center_freq % refclk_freq > 22)))
126 * Used to modify RF Banks before writing them to AR5K_RF_BUFFER
128 static unsigned int ath5k_hw_rfb_op(struct ath5k_hw *ah,
129 const struct ath5k_rf_reg *rf_regs,
130 u32 val, u8 reg_id, bool set)
132 const struct ath5k_rf_reg *rfreg = NULL;
133 u8 offset, bank, num_bits, col, position;
135 u32 mask, data, last_bit, bits_shifted, first_bit;
141 rfb = ah->ah_rf_banks;
143 for (i = 0; i < ah->ah_rf_regs_count; i++) {
144 if (rf_regs[i].index == reg_id) {
150 if (rfb == NULL || rfreg == NULL) {
151 ATH5K_PRINTF("Rf register not found!\n");
152 /* should not happen */
157 num_bits = rfreg->field.len;
158 first_bit = rfreg->field.pos;
159 col = rfreg->field.col;
161 /* first_bit is an offset from bank's
162 * start. Since we have all banks on
163 * the same array, we use this offset
164 * to mark each bank's start */
165 offset = ah->ah_offset[bank];
168 if (!(col <= 3 && num_bits <= 32 && first_bit + num_bits <= 319)) {
169 ATH5K_PRINTF("invalid values at offset %u\n", offset);
173 entry = ((first_bit - 1) / 8) + offset;
174 position = (first_bit - 1) % 8;
177 data = ath5k_hw_bitswap(val, num_bits);
179 for (bits_shifted = 0, bits_left = num_bits; bits_left > 0;
180 position = 0, entry++) {
182 last_bit = (position + bits_left > 8) ? 8 :
183 position + bits_left;
185 mask = (((1 << last_bit) - 1) ^ ((1 << position) - 1)) <<
190 rfb[entry] |= ((data << position) << (col * 8)) & mask;
191 data >>= (8 - position);
193 data |= (((rfb[entry] & mask) >> (col * 8)) >> position)
195 bits_shifted += last_bit - position;
198 bits_left -= 8 - position;
201 data = set ? 1 : ath5k_hw_bitswap(data, num_bits);
207 * ath5k_hw_write_ofdm_timings - set OFDM timings on AR5212
209 * @ah: the &struct ath5k_hw
210 * @channel: the currently set channel upon reset
212 * Write the delta slope coefficient (used on pilot tracking ?) for OFDM
213 * operation on the AR5212 upon reset. This is a helper for ath5k_hw_phy_init.
215 * Since delta slope is floating point we split it on its exponent and
216 * mantissa and provide these values on hw.
218 * For more infos i think this patent is related
219 * http://www.freepatentsonline.com/7184495.html
221 static inline int ath5k_hw_write_ofdm_timings(struct ath5k_hw *ah,
222 struct ieee80211_channel *channel)
224 /* Get exponent and mantissa and set it */
225 u32 coef_scaled, coef_exp, coef_man,
226 ds_coef_exp, ds_coef_man, clock;
228 BUG_ON(!(ah->ah_version == AR5K_AR5212) ||
229 (channel->hw_value == AR5K_MODE_11B));
232 * ALGO: coef = (5 * clock / carrier_freq) / 2
233 * we scale coef by shifting clock value by 24 for
234 * better precision since we use integers */
235 switch (ah->ah_bwmode) {
236 case AR5K_BWMODE_40MHZ:
239 case AR5K_BWMODE_10MHZ:
242 case AR5K_BWMODE_5MHZ:
249 coef_scaled = ((5 * (clock << 24)) / 2) / channel->center_freq;
252 * ALGO: coef_exp = 14 - highest set bit position */
253 coef_exp = ilog2(coef_scaled);
255 /* Doesn't make sense if it's zero*/
256 if (!coef_scaled || !coef_exp)
259 /* Note: we've shifted coef_scaled by 24 */
260 coef_exp = 14 - (coef_exp - 24);
263 /* Get mantissa (significant digits)
264 * ALGO: coef_mant = floor(coef_scaled* 2^coef_exp+0.5) */
265 coef_man = coef_scaled +
266 (1 << (24 - coef_exp - 1));
268 /* Calculate delta slope coefficient exponent
269 * and mantissa (remove scaling) and set them on hw */
270 ds_coef_man = coef_man >> (24 - coef_exp);
271 ds_coef_exp = coef_exp - 16;
273 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_3,
274 AR5K_PHY_TIMING_3_DSC_MAN, ds_coef_man);
275 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_3,
276 AR5K_PHY_TIMING_3_DSC_EXP, ds_coef_exp);
281 int ath5k_hw_phy_disable(struct ath5k_hw *ah)
284 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT);
290 * Wait for synth to settle
292 static void ath5k_hw_wait_for_synth(struct ath5k_hw *ah,
293 struct ieee80211_channel *channel)
296 * On 5211+ read activation -> rx delay
297 * and use it (100ns steps).
299 if (ah->ah_version != AR5K_AR5210) {
301 delay = ath5k_hw_reg_read(ah, AR5K_PHY_RX_DELAY) &
303 delay = (channel->hw_value == AR5K_MODE_11B) ?
304 ((delay << 2) / 22) : (delay / 10);
305 if (ah->ah_bwmode == AR5K_BWMODE_10MHZ)
307 if (ah->ah_bwmode == AR5K_BWMODE_5MHZ)
309 /* XXX: /2 on turbo ? Let's be safe
318 /**********************\
319 * RF Gain optimization *
320 \**********************/
323 * This code is used to optimize RF gain on different environments
324 * (temperature mostly) based on feedback from a power detector.
326 * It's only used on RF5111 and RF5112, later RF chips seem to have
327 * auto adjustment on hw -notice they have a much smaller BANK 7 and
328 * no gain optimization ladder-.
330 * For more infos check out this patent doc
331 * http://www.freepatentsonline.com/7400691.html
333 * This paper describes power drops as seen on the receiver due to
335 * http://www.cnri.dit.ie/publications/ICT08%20-%20Practical%20Issues
336 * %20of%20Power%20Control.pdf
338 * And this is the MadWiFi bug entry related to the above
339 * http://madwifi-project.org/ticket/1659
340 * with various measurements and diagrams
342 * TODO: Deal with power drops due to probes by setting an appropriate
343 * tx power on the probe packets ! Make this part of the calibration process.
346 /* Initialize ah_gain during attach */
347 int ath5k_hw_rfgain_opt_init(struct ath5k_hw *ah)
349 /* Initialize the gain optimization values */
350 switch (ah->ah_radio) {
352 ah->ah_gain.g_step_idx = rfgain_opt_5111.go_default;
353 ah->ah_gain.g_low = 20;
354 ah->ah_gain.g_high = 35;
355 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
358 ah->ah_gain.g_step_idx = rfgain_opt_5112.go_default;
359 ah->ah_gain.g_low = 20;
360 ah->ah_gain.g_high = 85;
361 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
370 /* Schedule a gain probe check on the next transmitted packet.
371 * That means our next packet is going to be sent with lower
372 * tx power and a Peak to Average Power Detector (PAPD) will try
373 * to measure the gain.
375 * XXX: How about forcing a tx packet (bypassing PCU arbitrator etc)
376 * just after we enable the probe so that we don't mess with
377 * standard traffic ? Maybe it's time to use sw interrupts and
378 * a probe tasklet !!!
380 static void ath5k_hw_request_rfgain_probe(struct ath5k_hw *ah)
383 /* Skip if gain calibration is inactive or
384 * we already handle a probe request */
385 if (ah->ah_gain.g_state != AR5K_RFGAIN_ACTIVE)
388 /* Send the packet with 2dB below max power as
389 * patent doc suggest */
390 ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txpower.txp_ofdm - 4,
391 AR5K_PHY_PAPD_PROBE_TXPOWER) |
392 AR5K_PHY_PAPD_PROBE_TX_NEXT, AR5K_PHY_PAPD_PROBE);
394 ah->ah_gain.g_state = AR5K_RFGAIN_READ_REQUESTED;
398 /* Calculate gain_F measurement correction
399 * based on the current step for RF5112 rev. 2 */
400 static u32 ath5k_hw_rf_gainf_corr(struct ath5k_hw *ah)
404 const struct ath5k_gain_opt *go;
405 const struct ath5k_gain_opt_step *g_step;
406 const struct ath5k_rf_reg *rf_regs;
408 /* Only RF5112 Rev. 2 supports it */
409 if ((ah->ah_radio != AR5K_RF5112) ||
410 (ah->ah_radio_5ghz_revision <= AR5K_SREV_RAD_5112A))
413 go = &rfgain_opt_5112;
414 rf_regs = rf_regs_5112a;
415 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112a);
417 g_step = &go->go_step[ah->ah_gain.g_step_idx];
419 if (ah->ah_rf_banks == NULL)
422 rf = ah->ah_rf_banks;
423 ah->ah_gain.g_f_corr = 0;
425 /* No VGA (Variable Gain Amplifier) override, skip */
426 if (ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXVGA_OVR, false) != 1)
429 /* Mix gain stepping */
430 step = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXGAIN_STEP, false);
432 /* Mix gain override */
433 mix = g_step->gos_param[0];
437 ah->ah_gain.g_f_corr = step * 2;
440 ah->ah_gain.g_f_corr = (step - 5) * 2;
443 ah->ah_gain.g_f_corr = step;
446 ah->ah_gain.g_f_corr = 0;
450 return ah->ah_gain.g_f_corr;
453 /* Check if current gain_F measurement is in the range of our
454 * power detector windows. If we get a measurement outside range
455 * we know it's not accurate (detectors can't measure anything outside
456 * their detection window) so we must ignore it */
457 static bool ath5k_hw_rf_check_gainf_readback(struct ath5k_hw *ah)
459 const struct ath5k_rf_reg *rf_regs;
460 u32 step, mix_ovr, level[4];
463 if (ah->ah_rf_banks == NULL)
466 rf = ah->ah_rf_banks;
468 if (ah->ah_radio == AR5K_RF5111) {
470 rf_regs = rf_regs_5111;
471 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5111);
473 step = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_RFGAIN_STEP,
477 level[1] = (step == 63) ? 50 : step + 4;
478 level[2] = (step != 63) ? 64 : level[0];
479 level[3] = level[2] + 50;
481 ah->ah_gain.g_high = level[3] -
482 (step == 63 ? AR5K_GAIN_DYN_ADJUST_HI_MARGIN : -5);
483 ah->ah_gain.g_low = level[0] +
484 (step == 63 ? AR5K_GAIN_DYN_ADJUST_LO_MARGIN : 0);
487 rf_regs = rf_regs_5112;
488 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112);
490 mix_ovr = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXVGA_OVR,
493 level[0] = level[2] = 0;
496 level[1] = level[3] = 83;
498 level[1] = level[3] = 107;
499 ah->ah_gain.g_high = 55;
503 return (ah->ah_gain.g_current >= level[0] &&
504 ah->ah_gain.g_current <= level[1]) ||
505 (ah->ah_gain.g_current >= level[2] &&
506 ah->ah_gain.g_current <= level[3]);
509 /* Perform gain_F adjustment by choosing the right set
510 * of parameters from RF gain optimization ladder */
511 static s8 ath5k_hw_rf_gainf_adjust(struct ath5k_hw *ah)
513 const struct ath5k_gain_opt *go;
514 const struct ath5k_gain_opt_step *g_step;
517 switch (ah->ah_radio) {
519 go = &rfgain_opt_5111;
522 go = &rfgain_opt_5112;
528 g_step = &go->go_step[ah->ah_gain.g_step_idx];
530 if (ah->ah_gain.g_current >= ah->ah_gain.g_high) {
532 /* Reached maximum */
533 if (ah->ah_gain.g_step_idx == 0)
536 for (ah->ah_gain.g_target = ah->ah_gain.g_current;
537 ah->ah_gain.g_target >= ah->ah_gain.g_high &&
538 ah->ah_gain.g_step_idx > 0;
539 g_step = &go->go_step[ah->ah_gain.g_step_idx])
540 ah->ah_gain.g_target -= 2 *
541 (go->go_step[--(ah->ah_gain.g_step_idx)].gos_gain -
548 if (ah->ah_gain.g_current <= ah->ah_gain.g_low) {
550 /* Reached minimum */
551 if (ah->ah_gain.g_step_idx == (go->go_steps_count - 1))
554 for (ah->ah_gain.g_target = ah->ah_gain.g_current;
555 ah->ah_gain.g_target <= ah->ah_gain.g_low &&
556 ah->ah_gain.g_step_idx < go->go_steps_count - 1;
557 g_step = &go->go_step[ah->ah_gain.g_step_idx])
558 ah->ah_gain.g_target -= 2 *
559 (go->go_step[++ah->ah_gain.g_step_idx].gos_gain -
567 ATH5K_DBG(ah, ATH5K_DEBUG_CALIBRATE,
568 "ret %d, gain step %u, current gain %u, target gain %u\n",
569 ret, ah->ah_gain.g_step_idx, ah->ah_gain.g_current,
570 ah->ah_gain.g_target);
575 /* Main callback for thermal RF gain calibration engine
576 * Check for a new gain reading and schedule an adjustment
579 * TODO: Use sw interrupt to schedule reset if gain_F needs
581 enum ath5k_rfgain ath5k_hw_gainf_calibrate(struct ath5k_hw *ah)
584 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
586 if (ah->ah_rf_banks == NULL ||
587 ah->ah_gain.g_state == AR5K_RFGAIN_INACTIVE)
588 return AR5K_RFGAIN_INACTIVE;
590 /* No check requested, either engine is inactive
591 * or an adjustment is already requested */
592 if (ah->ah_gain.g_state != AR5K_RFGAIN_READ_REQUESTED)
595 /* Read the PAPD (Peak to Average Power Detector)
597 data = ath5k_hw_reg_read(ah, AR5K_PHY_PAPD_PROBE);
599 /* No probe is scheduled, read gain_F measurement */
600 if (!(data & AR5K_PHY_PAPD_PROBE_TX_NEXT)) {
601 ah->ah_gain.g_current = data >> AR5K_PHY_PAPD_PROBE_GAINF_S;
602 type = AR5K_REG_MS(data, AR5K_PHY_PAPD_PROBE_TYPE);
604 /* If tx packet is CCK correct the gain_F measurement
605 * by cck ofdm gain delta */
606 if (type == AR5K_PHY_PAPD_PROBE_TYPE_CCK) {
607 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A)
608 ah->ah_gain.g_current +=
609 ee->ee_cck_ofdm_gain_delta;
611 ah->ah_gain.g_current +=
612 AR5K_GAIN_CCK_PROBE_CORR;
615 /* Further correct gain_F measurement for
617 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) {
618 ath5k_hw_rf_gainf_corr(ah);
619 ah->ah_gain.g_current =
620 ah->ah_gain.g_current >= ah->ah_gain.g_f_corr ?
621 (ah->ah_gain.g_current - ah->ah_gain.g_f_corr) :
625 /* Check if measurement is ok and if we need
626 * to adjust gain, schedule a gain adjustment,
627 * else switch back to the active state */
628 if (ath5k_hw_rf_check_gainf_readback(ah) &&
629 AR5K_GAIN_CHECK_ADJUST(&ah->ah_gain) &&
630 ath5k_hw_rf_gainf_adjust(ah)) {
631 ah->ah_gain.g_state = AR5K_RFGAIN_NEED_CHANGE;
633 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
638 return ah->ah_gain.g_state;
641 /* Write initial RF gain table to set the RF sensitivity
642 * this one works on all RF chips and has nothing to do
643 * with gain_F calibration */
644 static int ath5k_hw_rfgain_init(struct ath5k_hw *ah, enum ieee80211_band band)
646 const struct ath5k_ini_rfgain *ath5k_rfg;
647 unsigned int i, size, index;
649 switch (ah->ah_radio) {
651 ath5k_rfg = rfgain_5111;
652 size = ARRAY_SIZE(rfgain_5111);
655 ath5k_rfg = rfgain_5112;
656 size = ARRAY_SIZE(rfgain_5112);
659 ath5k_rfg = rfgain_2413;
660 size = ARRAY_SIZE(rfgain_2413);
663 ath5k_rfg = rfgain_2316;
664 size = ARRAY_SIZE(rfgain_2316);
667 ath5k_rfg = rfgain_5413;
668 size = ARRAY_SIZE(rfgain_5413);
672 ath5k_rfg = rfgain_2425;
673 size = ARRAY_SIZE(rfgain_2425);
679 index = (band == IEEE80211_BAND_2GHZ) ? 1 : 0;
681 for (i = 0; i < size; i++) {
683 ath5k_hw_reg_write(ah, ath5k_rfg[i].rfg_value[index],
684 (u32)ath5k_rfg[i].rfg_register);
692 /********************\
693 * RF Registers setup *
694 \********************/
697 * Setup RF registers by writing RF buffer on hw
699 static int ath5k_hw_rfregs_init(struct ath5k_hw *ah,
700 struct ieee80211_channel *channel, unsigned int mode)
702 const struct ath5k_rf_reg *rf_regs;
703 const struct ath5k_ini_rfbuffer *ini_rfb;
704 const struct ath5k_gain_opt *go = NULL;
705 const struct ath5k_gain_opt_step *g_step;
706 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
709 int i, obdb = -1, bank = -1;
711 switch (ah->ah_radio) {
713 rf_regs = rf_regs_5111;
714 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5111);
716 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5111);
717 go = &rfgain_opt_5111;
720 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) {
721 rf_regs = rf_regs_5112a;
722 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112a);
724 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5112a);
726 rf_regs = rf_regs_5112;
727 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112);
729 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5112);
731 go = &rfgain_opt_5112;
734 rf_regs = rf_regs_2413;
735 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2413);
737 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2413);
740 rf_regs = rf_regs_2316;
741 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2316);
743 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2316);
746 rf_regs = rf_regs_5413;
747 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5413);
749 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5413);
752 rf_regs = rf_regs_2425;
753 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2425);
755 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2317);
758 rf_regs = rf_regs_2425;
759 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2425);
760 if (ah->ah_mac_srev < AR5K_SREV_AR2417) {
762 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2425);
765 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2417);
772 /* If it's the first time we set RF buffer, allocate
773 * ah->ah_rf_banks based on ah->ah_rf_banks_size
775 if (ah->ah_rf_banks == NULL) {
776 ah->ah_rf_banks = kmalloc(sizeof(u32) * ah->ah_rf_banks_size,
778 if (ah->ah_rf_banks == NULL) {
779 ATH5K_ERR(ah, "out of memory\n");
784 /* Copy values to modify them */
785 rfb = ah->ah_rf_banks;
787 for (i = 0; i < ah->ah_rf_banks_size; i++) {
788 if (ini_rfb[i].rfb_bank >= AR5K_MAX_RF_BANKS) {
789 ATH5K_ERR(ah, "invalid bank\n");
793 /* Bank changed, write down the offset */
794 if (bank != ini_rfb[i].rfb_bank) {
795 bank = ini_rfb[i].rfb_bank;
796 ah->ah_offset[bank] = i;
799 rfb[i] = ini_rfb[i].rfb_mode_data[mode];
802 /* Set Output and Driver bias current (OB/DB) */
803 if (channel->band == IEEE80211_BAND_2GHZ) {
805 if (channel->hw_value == AR5K_MODE_11B)
806 ee_mode = AR5K_EEPROM_MODE_11B;
808 ee_mode = AR5K_EEPROM_MODE_11G;
810 /* For RF511X/RF211X combination we
811 * use b_OB and b_DB parameters stored
812 * in eeprom on ee->ee_ob[ee_mode][0]
814 * For all other chips we use OB/DB for 2GHz
815 * stored in the b/g modal section just like
816 * 802.11a on ee->ee_ob[ee_mode][1] */
817 if ((ah->ah_radio == AR5K_RF5111) ||
818 (ah->ah_radio == AR5K_RF5112))
823 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_ob[ee_mode][obdb],
824 AR5K_RF_OB_2GHZ, true);
826 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_db[ee_mode][obdb],
827 AR5K_RF_DB_2GHZ, true);
829 /* RF5111 always needs OB/DB for 5GHz, even if we use 2GHz */
830 } else if ((channel->band == IEEE80211_BAND_5GHZ) ||
831 (ah->ah_radio == AR5K_RF5111)) {
833 /* For 11a, Turbo and XR we need to choose
834 * OB/DB based on frequency range */
835 ee_mode = AR5K_EEPROM_MODE_11A;
836 obdb = channel->center_freq >= 5725 ? 3 :
837 (channel->center_freq >= 5500 ? 2 :
838 (channel->center_freq >= 5260 ? 1 :
839 (channel->center_freq > 4000 ? 0 : -1)));
844 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_ob[ee_mode][obdb],
845 AR5K_RF_OB_5GHZ, true);
847 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_db[ee_mode][obdb],
848 AR5K_RF_DB_5GHZ, true);
851 g_step = &go->go_step[ah->ah_gain.g_step_idx];
853 /* Set turbo mode (N/A on RF5413) */
854 if ((ah->ah_bwmode == AR5K_BWMODE_40MHZ) &&
855 (ah->ah_radio != AR5K_RF5413))
856 ath5k_hw_rfb_op(ah, rf_regs, 1, AR5K_RF_TURBO, false);
858 /* Bank Modifications (chip-specific) */
859 if (ah->ah_radio == AR5K_RF5111) {
861 /* Set gain_F settings according to current step */
862 if (channel->hw_value != AR5K_MODE_11B) {
864 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_FRAME_CTL,
865 AR5K_PHY_FRAME_CTL_TX_CLIP,
866 g_step->gos_param[0]);
868 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[1],
869 AR5K_RF_PWD_90, true);
871 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[2],
872 AR5K_RF_PWD_84, true);
874 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[3],
875 AR5K_RF_RFGAIN_SEL, true);
877 /* We programmed gain_F parameters, switch back
879 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
885 ath5k_hw_rfb_op(ah, rf_regs, !ee->ee_xpd[ee_mode],
886 AR5K_RF_PWD_XPD, true);
888 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_x_gain[ee_mode],
889 AR5K_RF_XPD_GAIN, true);
891 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_i_gain[ee_mode],
892 AR5K_RF_GAIN_I, true);
894 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_xpd[ee_mode],
895 AR5K_RF_PLO_SEL, true);
897 /* Tweak power detectors for half/quarter rate support */
898 if (ah->ah_bwmode == AR5K_BWMODE_5MHZ ||
899 ah->ah_bwmode == AR5K_BWMODE_10MHZ) {
902 ath5k_hw_rfb_op(ah, rf_regs, 0x1f,
903 AR5K_RF_WAIT_S, true);
905 wait_i = (ah->ah_bwmode == AR5K_BWMODE_5MHZ) ?
908 ath5k_hw_rfb_op(ah, rf_regs, wait_i,
909 AR5K_RF_WAIT_I, true);
910 ath5k_hw_rfb_op(ah, rf_regs, 3,
911 AR5K_RF_MAX_TIME, true);
916 if (ah->ah_radio == AR5K_RF5112) {
918 /* Set gain_F settings according to current step */
919 if (channel->hw_value != AR5K_MODE_11B) {
921 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[0],
922 AR5K_RF_MIXGAIN_OVR, true);
924 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[1],
925 AR5K_RF_PWD_138, true);
927 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[2],
928 AR5K_RF_PWD_137, true);
930 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[3],
931 AR5K_RF_PWD_136, true);
933 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[4],
934 AR5K_RF_PWD_132, true);
936 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[5],
937 AR5K_RF_PWD_131, true);
939 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[6],
940 AR5K_RF_PWD_130, true);
942 /* We programmed gain_F parameters, switch back
944 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
949 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_xpd[ee_mode],
950 AR5K_RF_XPD_SEL, true);
952 if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_5112A) {
953 /* Rev. 1 supports only one xpd */
954 ath5k_hw_rfb_op(ah, rf_regs,
955 ee->ee_x_gain[ee_mode],
956 AR5K_RF_XPD_GAIN, true);
959 u8 *pdg_curve_to_idx = ee->ee_pdc_to_idx[ee_mode];
960 if (ee->ee_pd_gains[ee_mode] > 1) {
961 ath5k_hw_rfb_op(ah, rf_regs,
963 AR5K_RF_PD_GAIN_LO, true);
964 ath5k_hw_rfb_op(ah, rf_regs,
966 AR5K_RF_PD_GAIN_HI, true);
968 ath5k_hw_rfb_op(ah, rf_regs,
970 AR5K_RF_PD_GAIN_LO, true);
971 ath5k_hw_rfb_op(ah, rf_regs,
973 AR5K_RF_PD_GAIN_HI, true);
976 /* Lower synth voltage on Rev 2 */
977 if (ah->ah_radio == AR5K_RF5112 &&
978 (ah->ah_radio_5ghz_revision & AR5K_SREV_REV) > 0) {
979 ath5k_hw_rfb_op(ah, rf_regs, 2,
980 AR5K_RF_HIGH_VC_CP, true);
982 ath5k_hw_rfb_op(ah, rf_regs, 2,
983 AR5K_RF_MID_VC_CP, true);
985 ath5k_hw_rfb_op(ah, rf_regs, 2,
986 AR5K_RF_LOW_VC_CP, true);
988 ath5k_hw_rfb_op(ah, rf_regs, 2,
989 AR5K_RF_PUSH_UP, true);
992 /* Decrease power consumption on 5213+ BaseBand */
993 if (ah->ah_phy_revision >= AR5K_SREV_PHY_5212A) {
994 ath5k_hw_rfb_op(ah, rf_regs, 1,
995 AR5K_RF_PAD2GND, true);
997 ath5k_hw_rfb_op(ah, rf_regs, 1,
998 AR5K_RF_XB2_LVL, true);
1000 ath5k_hw_rfb_op(ah, rf_regs, 1,
1001 AR5K_RF_XB5_LVL, true);
1003 ath5k_hw_rfb_op(ah, rf_regs, 1,
1004 AR5K_RF_PWD_167, true);
1006 ath5k_hw_rfb_op(ah, rf_regs, 1,
1007 AR5K_RF_PWD_166, true);
1011 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_i_gain[ee_mode],
1012 AR5K_RF_GAIN_I, true);
1014 /* Tweak power detector for half/quarter rates */
1015 if (ah->ah_bwmode == AR5K_BWMODE_5MHZ ||
1016 ah->ah_bwmode == AR5K_BWMODE_10MHZ) {
1019 pd_delay = (ah->ah_bwmode == AR5K_BWMODE_5MHZ) ?
1022 ath5k_hw_rfb_op(ah, rf_regs, pd_delay,
1023 AR5K_RF_PD_PERIOD_A, true);
1024 ath5k_hw_rfb_op(ah, rf_regs, 0xf,
1025 AR5K_RF_PD_DELAY_A, true);
1030 if (ah->ah_radio == AR5K_RF5413 &&
1031 channel->band == IEEE80211_BAND_2GHZ) {
1033 ath5k_hw_rfb_op(ah, rf_regs, 1, AR5K_RF_DERBY_CHAN_SEL_MODE,
1036 /* Set optimum value for early revisions (on pci-e chips) */
1037 if (ah->ah_mac_srev >= AR5K_SREV_AR5424 &&
1038 ah->ah_mac_srev < AR5K_SREV_AR5413)
1039 ath5k_hw_rfb_op(ah, rf_regs, ath5k_hw_bitswap(6, 3),
1040 AR5K_RF_PWD_ICLOBUF_2G, true);
1044 /* Write RF banks on hw */
1045 for (i = 0; i < ah->ah_rf_banks_size; i++) {
1047 ath5k_hw_reg_write(ah, rfb[i], ini_rfb[i].rfb_ctrl_register);
1054 /**************************\
1055 PHY/RF channel functions
1056 \**************************/
1059 * Conversion needed for RF5110
1061 static u32 ath5k_hw_rf5110_chan2athchan(struct ieee80211_channel *channel)
1066 * Convert IEEE channel/MHz to an internal channel value used
1067 * by the AR5210 chipset. This has not been verified with
1068 * newer chipsets like the AR5212A who have a completely
1069 * different RF/PHY part.
1071 athchan = (ath5k_hw_bitswap(
1072 (ieee80211_frequency_to_channel(
1073 channel->center_freq) - 24) / 2, 5)
1074 << 1) | (1 << 6) | 0x1;
1079 * Set channel on RF5110
1081 static int ath5k_hw_rf5110_channel(struct ath5k_hw *ah,
1082 struct ieee80211_channel *channel)
1087 * Set the channel and wait
1089 data = ath5k_hw_rf5110_chan2athchan(channel);
1090 ath5k_hw_reg_write(ah, data, AR5K_RF_BUFFER);
1091 ath5k_hw_reg_write(ah, 0, AR5K_RF_BUFFER_CONTROL_0);
1098 * Conversion needed for 5111
1100 static int ath5k_hw_rf5111_chan2athchan(unsigned int ieee,
1101 struct ath5k_athchan_2ghz *athchan)
1105 /* Cast this value to catch negative channel numbers (>= -19) */
1106 channel = (int)ieee;
1109 * Map 2GHz IEEE channel to 5GHz Atheros channel
1111 if (channel <= 13) {
1112 athchan->a2_athchan = 115 + channel;
1113 athchan->a2_flags = 0x46;
1114 } else if (channel == 14) {
1115 athchan->a2_athchan = 124;
1116 athchan->a2_flags = 0x44;
1117 } else if (channel >= 15 && channel <= 26) {
1118 athchan->a2_athchan = ((channel - 14) * 4) + 132;
1119 athchan->a2_flags = 0x46;
1127 * Set channel on 5111
1129 static int ath5k_hw_rf5111_channel(struct ath5k_hw *ah,
1130 struct ieee80211_channel *channel)
1132 struct ath5k_athchan_2ghz ath5k_channel_2ghz;
1133 unsigned int ath5k_channel =
1134 ieee80211_frequency_to_channel(channel->center_freq);
1135 u32 data0, data1, clock;
1139 * Set the channel on the RF5111 radio
1143 if (channel->band == IEEE80211_BAND_2GHZ) {
1144 /* Map 2GHz channel to 5GHz Atheros channel ID */
1145 ret = ath5k_hw_rf5111_chan2athchan(
1146 ieee80211_frequency_to_channel(channel->center_freq),
1147 &ath5k_channel_2ghz);
1151 ath5k_channel = ath5k_channel_2ghz.a2_athchan;
1152 data0 = ((ath5k_hw_bitswap(ath5k_channel_2ghz.a2_flags, 8) & 0xff)
1156 if (ath5k_channel < 145 || !(ath5k_channel & 1)) {
1158 data1 = ((ath5k_hw_bitswap(ath5k_channel - 24, 8) & 0xff) << 2) |
1159 (clock << 1) | (1 << 10) | 1;
1162 data1 = ((ath5k_hw_bitswap((ath5k_channel - 24) / 2, 8) & 0xff)
1163 << 2) | (clock << 1) | (1 << 10) | 1;
1166 ath5k_hw_reg_write(ah, (data1 & 0xff) | ((data0 & 0xff) << 8),
1168 ath5k_hw_reg_write(ah, ((data1 >> 8) & 0xff) | (data0 & 0xff00),
1169 AR5K_RF_BUFFER_CONTROL_3);
1175 * Set channel on 5112 and newer
1177 static int ath5k_hw_rf5112_channel(struct ath5k_hw *ah,
1178 struct ieee80211_channel *channel)
1180 u32 data, data0, data1, data2;
1183 data = data0 = data1 = data2 = 0;
1184 c = channel->center_freq;
1187 if (!((c - 2224) % 5)) {
1188 data0 = ((2 * (c - 704)) - 3040) / 10;
1190 } else if (!((c - 2192) % 5)) {
1191 data0 = ((2 * (c - 672)) - 3040) / 10;
1196 data0 = ath5k_hw_bitswap((data0 << 2) & 0xff, 8);
1197 } else if ((c % 5) != 2 || c > 5435) {
1198 if (!(c % 20) && c >= 5120) {
1199 data0 = ath5k_hw_bitswap(((c - 4800) / 20 << 2), 8);
1200 data2 = ath5k_hw_bitswap(3, 2);
1201 } else if (!(c % 10)) {
1202 data0 = ath5k_hw_bitswap(((c - 4800) / 10 << 1), 8);
1203 data2 = ath5k_hw_bitswap(2, 2);
1204 } else if (!(c % 5)) {
1205 data0 = ath5k_hw_bitswap((c - 4800) / 5, 8);
1206 data2 = ath5k_hw_bitswap(1, 2);
1210 data0 = ath5k_hw_bitswap((10 * (c - 2 - 4800)) / 25 + 1, 8);
1211 data2 = ath5k_hw_bitswap(0, 2);
1214 data = (data0 << 4) | (data1 << 1) | (data2 << 2) | 0x1001;
1216 ath5k_hw_reg_write(ah, data & 0xff, AR5K_RF_BUFFER);
1217 ath5k_hw_reg_write(ah, (data >> 8) & 0x7f, AR5K_RF_BUFFER_CONTROL_5);
1223 * Set the channel on the RF2425
1225 static int ath5k_hw_rf2425_channel(struct ath5k_hw *ah,
1226 struct ieee80211_channel *channel)
1228 u32 data, data0, data2;
1231 data = data0 = data2 = 0;
1232 c = channel->center_freq;
1235 data0 = ath5k_hw_bitswap((c - 2272), 8);
1238 } else if ((c % 5) != 2 || c > 5435) {
1239 if (!(c % 20) && c < 5120)
1240 data0 = ath5k_hw_bitswap(((c - 4800) / 20 << 2), 8);
1242 data0 = ath5k_hw_bitswap(((c - 4800) / 10 << 1), 8);
1244 data0 = ath5k_hw_bitswap((c - 4800) / 5, 8);
1247 data2 = ath5k_hw_bitswap(1, 2);
1249 data0 = ath5k_hw_bitswap((10 * (c - 2 - 4800)) / 25 + 1, 8);
1250 data2 = ath5k_hw_bitswap(0, 2);
1253 data = (data0 << 4) | data2 << 2 | 0x1001;
1255 ath5k_hw_reg_write(ah, data & 0xff, AR5K_RF_BUFFER);
1256 ath5k_hw_reg_write(ah, (data >> 8) & 0x7f, AR5K_RF_BUFFER_CONTROL_5);
1262 * Set a channel on the radio chip
1264 static int ath5k_hw_channel(struct ath5k_hw *ah,
1265 struct ieee80211_channel *channel)
1269 * Check bounds supported by the PHY (we don't care about regulatory
1270 * restrictions at this point).
1272 if (!ath5k_channel_ok(ah, channel)) {
1274 "channel frequency (%u MHz) out of supported "
1276 channel->center_freq);
1281 * Set the channel and wait
1283 switch (ah->ah_radio) {
1285 ret = ath5k_hw_rf5110_channel(ah, channel);
1288 ret = ath5k_hw_rf5111_channel(ah, channel);
1292 ret = ath5k_hw_rf2425_channel(ah, channel);
1295 ret = ath5k_hw_rf5112_channel(ah, channel);
1302 /* Set JAPAN setting for channel 14 */
1303 if (channel->center_freq == 2484) {
1304 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_CCKTXCTL,
1305 AR5K_PHY_CCKTXCTL_JAPAN);
1307 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_CCKTXCTL,
1308 AR5K_PHY_CCKTXCTL_WORLD);
1311 ah->ah_current_channel = channel;
1320 static s32 ath5k_hw_read_measured_noise_floor(struct ath5k_hw *ah)
1324 val = ath5k_hw_reg_read(ah, AR5K_PHY_NF);
1325 return sign_extend32(AR5K_REG_MS(val, AR5K_PHY_NF_MINCCA_PWR), 8);
1328 void ath5k_hw_init_nfcal_hist(struct ath5k_hw *ah)
1332 ah->ah_nfcal_hist.index = 0;
1333 for (i = 0; i < ATH5K_NF_CAL_HIST_MAX; i++)
1334 ah->ah_nfcal_hist.nfval[i] = AR5K_TUNE_CCA_MAX_GOOD_VALUE;
1337 static void ath5k_hw_update_nfcal_hist(struct ath5k_hw *ah, s16 noise_floor)
1339 struct ath5k_nfcal_hist *hist = &ah->ah_nfcal_hist;
1340 hist->index = (hist->index + 1) & (ATH5K_NF_CAL_HIST_MAX - 1);
1341 hist->nfval[hist->index] = noise_floor;
1344 static s16 ath5k_hw_get_median_noise_floor(struct ath5k_hw *ah)
1346 s16 sort[ATH5K_NF_CAL_HIST_MAX];
1350 memcpy(sort, ah->ah_nfcal_hist.nfval, sizeof(sort));
1351 for (i = 0; i < ATH5K_NF_CAL_HIST_MAX - 1; i++) {
1352 for (j = 1; j < ATH5K_NF_CAL_HIST_MAX - i; j++) {
1353 if (sort[j] > sort[j - 1]) {
1355 sort[j] = sort[j - 1];
1360 for (i = 0; i < ATH5K_NF_CAL_HIST_MAX; i++) {
1361 ATH5K_DBG(ah, ATH5K_DEBUG_CALIBRATE,
1362 "cal %d:%d\n", i, sort[i]);
1364 return sort[(ATH5K_NF_CAL_HIST_MAX - 1) / 2];
1368 * When we tell the hardware to perform a noise floor calibration
1369 * by setting the AR5K_PHY_AGCCTL_NF bit, it will periodically
1370 * sample-and-hold the minimum noise level seen at the antennas.
1371 * This value is then stored in a ring buffer of recently measured
1372 * noise floor values so we have a moving window of the last few
1375 * The median of the values in the history is then loaded into the
1376 * hardware for its own use for RSSI and CCA measurements.
1378 void ath5k_hw_update_noise_floor(struct ath5k_hw *ah)
1380 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1385 /* keep last value if calibration hasn't completed */
1386 if (ath5k_hw_reg_read(ah, AR5K_PHY_AGCCTL) & AR5K_PHY_AGCCTL_NF) {
1387 ATH5K_DBG(ah, ATH5K_DEBUG_CALIBRATE,
1388 "NF did not complete in calibration window\n");
1393 ee_mode = ath5k_eeprom_mode_from_channel(ah->ah_current_channel);
1395 /* completed NF calibration, test threshold */
1396 nf = ath5k_hw_read_measured_noise_floor(ah);
1397 threshold = ee->ee_noise_floor_thr[ee_mode];
1399 if (nf > threshold) {
1400 ATH5K_DBG(ah, ATH5K_DEBUG_CALIBRATE,
1401 "noise floor failure detected; "
1402 "read %d, threshold %d\n",
1405 nf = AR5K_TUNE_CCA_MAX_GOOD_VALUE;
1408 ath5k_hw_update_nfcal_hist(ah, nf);
1409 nf = ath5k_hw_get_median_noise_floor(ah);
1411 /* load noise floor (in .5 dBm) so the hardware will use it */
1412 val = ath5k_hw_reg_read(ah, AR5K_PHY_NF) & ~AR5K_PHY_NF_M;
1413 val |= (nf * 2) & AR5K_PHY_NF_M;
1414 ath5k_hw_reg_write(ah, val, AR5K_PHY_NF);
1416 AR5K_REG_MASKED_BITS(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_NF,
1417 ~(AR5K_PHY_AGCCTL_NF_EN | AR5K_PHY_AGCCTL_NF_NOUPDATE));
1419 ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_NF,
1423 * Load a high max CCA Power value (-50 dBm in .5 dBm units)
1424 * so that we're not capped by the median we just loaded.
1425 * This will be used as the initial value for the next noise
1426 * floor calibration.
1428 val = (val & ~AR5K_PHY_NF_M) | ((-50 * 2) & AR5K_PHY_NF_M);
1429 ath5k_hw_reg_write(ah, val, AR5K_PHY_NF);
1430 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
1431 AR5K_PHY_AGCCTL_NF_EN |
1432 AR5K_PHY_AGCCTL_NF_NOUPDATE |
1433 AR5K_PHY_AGCCTL_NF);
1435 ah->ah_noise_floor = nf;
1437 ATH5K_DBG(ah, ATH5K_DEBUG_CALIBRATE,
1438 "noise floor calibrated: %d\n", nf);
1442 * Perform a PHY calibration on RF5110
1443 * -Fix BPSK/QAM Constellation (I/Q correction)
1445 static int ath5k_hw_rf5110_calibrate(struct ath5k_hw *ah,
1446 struct ieee80211_channel *channel)
1448 u32 phy_sig, phy_agc, phy_sat, beacon;
1452 * Disable beacons and RX/TX queues, wait
1454 AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW_5210,
1455 AR5K_DIAG_SW_DIS_TX_5210 | AR5K_DIAG_SW_DIS_RX_5210);
1456 beacon = ath5k_hw_reg_read(ah, AR5K_BEACON_5210);
1457 ath5k_hw_reg_write(ah, beacon & ~AR5K_BEACON_ENABLE, AR5K_BEACON_5210);
1462 * Set the channel (with AGC turned off)
1464 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
1466 ret = ath5k_hw_channel(ah, channel);
1469 * Activate PHY and wait
1471 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT);
1474 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
1480 * Calibrate the radio chip
1483 /* Remember normal state */
1484 phy_sig = ath5k_hw_reg_read(ah, AR5K_PHY_SIG);
1485 phy_agc = ath5k_hw_reg_read(ah, AR5K_PHY_AGCCOARSE);
1486 phy_sat = ath5k_hw_reg_read(ah, AR5K_PHY_ADCSAT);
1488 /* Update radio registers */
1489 ath5k_hw_reg_write(ah, (phy_sig & ~(AR5K_PHY_SIG_FIRPWR)) |
1490 AR5K_REG_SM(-1, AR5K_PHY_SIG_FIRPWR), AR5K_PHY_SIG);
1492 ath5k_hw_reg_write(ah, (phy_agc & ~(AR5K_PHY_AGCCOARSE_HI |
1493 AR5K_PHY_AGCCOARSE_LO)) |
1494 AR5K_REG_SM(-1, AR5K_PHY_AGCCOARSE_HI) |
1495 AR5K_REG_SM(-127, AR5K_PHY_AGCCOARSE_LO), AR5K_PHY_AGCCOARSE);
1497 ath5k_hw_reg_write(ah, (phy_sat & ~(AR5K_PHY_ADCSAT_ICNT |
1498 AR5K_PHY_ADCSAT_THR)) |
1499 AR5K_REG_SM(2, AR5K_PHY_ADCSAT_ICNT) |
1500 AR5K_REG_SM(12, AR5K_PHY_ADCSAT_THR), AR5K_PHY_ADCSAT);
1504 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
1506 ath5k_hw_reg_write(ah, AR5K_PHY_RFSTG_DISABLE, AR5K_PHY_RFSTG);
1507 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
1512 * Enable calibration and wait until completion
1514 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_CAL);
1516 ret = ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL,
1517 AR5K_PHY_AGCCTL_CAL, 0, false);
1519 /* Reset to normal state */
1520 ath5k_hw_reg_write(ah, phy_sig, AR5K_PHY_SIG);
1521 ath5k_hw_reg_write(ah, phy_agc, AR5K_PHY_AGCCOARSE);
1522 ath5k_hw_reg_write(ah, phy_sat, AR5K_PHY_ADCSAT);
1525 ATH5K_ERR(ah, "calibration timeout (%uMHz)\n",
1526 channel->center_freq);
1531 * Re-enable RX/TX and beacons
1533 AR5K_REG_DISABLE_BITS(ah, AR5K_DIAG_SW_5210,
1534 AR5K_DIAG_SW_DIS_TX_5210 | AR5K_DIAG_SW_DIS_RX_5210);
1535 ath5k_hw_reg_write(ah, beacon, AR5K_BEACON_5210);
1541 * Perform I/Q calibration on RF5111/5112 and newer chips
1544 ath5k_hw_rf511x_iq_calibrate(struct ath5k_hw *ah)
1547 s32 iq_corr, i_coff, i_coffd, q_coff, q_coffd;
1550 if (!ah->ah_calibration ||
1551 ath5k_hw_reg_read(ah, AR5K_PHY_IQ) & AR5K_PHY_IQ_RUN)
1554 /* Calibration has finished, get the results and re-run */
1555 /* work around empty results which can apparently happen on 5212 */
1556 for (i = 0; i <= 10; i++) {
1557 iq_corr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_CORR);
1558 i_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_I);
1559 q_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_Q);
1560 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_CALIBRATE,
1561 "iq_corr:%x i_pwr:%x q_pwr:%x", iq_corr, i_pwr, q_pwr);
1566 i_coffd = ((i_pwr >> 1) + (q_pwr >> 1)) >> 7;
1568 if (ah->ah_version == AR5K_AR5211)
1569 q_coffd = q_pwr >> 6;
1571 q_coffd = q_pwr >> 7;
1573 /* protect against divide by 0 and loss of sign bits */
1574 if (i_coffd == 0 || q_coffd < 2)
1577 i_coff = (-iq_corr) / i_coffd;
1578 i_coff = clamp(i_coff, -32, 31); /* signed 6 bit */
1580 if (ah->ah_version == AR5K_AR5211)
1581 q_coff = (i_pwr / q_coffd) - 64;
1583 q_coff = (i_pwr / q_coffd) - 128;
1584 q_coff = clamp(q_coff, -16, 15); /* signed 5 bit */
1586 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_CALIBRATE,
1587 "new I:%d Q:%d (i_coffd:%x q_coffd:%x)",
1588 i_coff, q_coff, i_coffd, q_coffd);
1590 /* Commit new I/Q values (set enable bit last to match HAL sources) */
1591 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_Q_I_COFF, i_coff);
1592 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_Q_Q_COFF, q_coff);
1593 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_ENABLE);
1595 /* Re-enable calibration -if we don't we'll commit
1596 * the same values again and again */
1597 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ,
1598 AR5K_PHY_IQ_CAL_NUM_LOG_MAX, 15);
1599 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_RUN);
1605 * Perform a PHY calibration
1607 int ath5k_hw_phy_calibrate(struct ath5k_hw *ah,
1608 struct ieee80211_channel *channel)
1612 if (ah->ah_radio == AR5K_RF5110)
1613 return ath5k_hw_rf5110_calibrate(ah, channel);
1615 ret = ath5k_hw_rf511x_iq_calibrate(ah);
1617 if ((ah->ah_radio == AR5K_RF5111 || ah->ah_radio == AR5K_RF5112) &&
1618 (channel->hw_value != AR5K_MODE_11B))
1619 ath5k_hw_request_rfgain_probe(ah);
1625 /***************************\
1626 * Spur mitigation functions *
1627 \***************************/
1630 ath5k_hw_set_spur_mitigation_filter(struct ath5k_hw *ah,
1631 struct ieee80211_channel *channel)
1633 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1634 u32 mag_mask[4] = {0, 0, 0, 0};
1635 u32 pilot_mask[2] = {0, 0};
1636 /* Note: fbin values are scaled up by 2 */
1637 u16 spur_chan_fbin, chan_fbin, symbol_width, spur_detection_window;
1638 s32 spur_delta_phase, spur_freq_sigma_delta;
1639 s32 spur_offset, num_symbols_x16;
1640 u8 num_symbol_offsets, i, freq_band;
1642 /* Convert current frequency to fbin value (the same way channels
1643 * are stored on EEPROM, check out ath5k_eeprom_bin2freq) and scale
1644 * up by 2 so we can compare it later */
1645 if (channel->band == IEEE80211_BAND_2GHZ) {
1646 chan_fbin = (channel->center_freq - 2300) * 10;
1647 freq_band = AR5K_EEPROM_BAND_2GHZ;
1649 chan_fbin = (channel->center_freq - 4900) * 10;
1650 freq_band = AR5K_EEPROM_BAND_5GHZ;
1653 /* Check if any spur_chan_fbin from EEPROM is
1654 * within our current channel's spur detection range */
1655 spur_chan_fbin = AR5K_EEPROM_NO_SPUR;
1656 spur_detection_window = AR5K_SPUR_CHAN_WIDTH;
1657 /* XXX: Half/Quarter channels ?*/
1658 if (ah->ah_bwmode == AR5K_BWMODE_40MHZ)
1659 spur_detection_window *= 2;
1661 for (i = 0; i < AR5K_EEPROM_N_SPUR_CHANS; i++) {
1662 spur_chan_fbin = ee->ee_spur_chans[i][freq_band];
1664 /* Note: mask cleans AR5K_EEPROM_NO_SPUR flag
1665 * so it's zero if we got nothing from EEPROM */
1666 if (spur_chan_fbin == AR5K_EEPROM_NO_SPUR) {
1667 spur_chan_fbin &= AR5K_EEPROM_SPUR_CHAN_MASK;
1671 if ((chan_fbin - spur_detection_window <=
1672 (spur_chan_fbin & AR5K_EEPROM_SPUR_CHAN_MASK)) &&
1673 (chan_fbin + spur_detection_window >=
1674 (spur_chan_fbin & AR5K_EEPROM_SPUR_CHAN_MASK))) {
1675 spur_chan_fbin &= AR5K_EEPROM_SPUR_CHAN_MASK;
1680 /* We need to enable spur filter for this channel */
1681 if (spur_chan_fbin) {
1682 spur_offset = spur_chan_fbin - chan_fbin;
1685 * spur_freq_sigma_delta -> spur_offset / sample_freq << 21
1686 * spur_delta_phase -> spur_offset / chip_freq << 11
1687 * Note: Both values have 100Hz resolution
1689 switch (ah->ah_bwmode) {
1690 case AR5K_BWMODE_40MHZ:
1691 /* Both sample_freq and chip_freq are 80MHz */
1692 spur_delta_phase = (spur_offset << 16) / 25;
1693 spur_freq_sigma_delta = (spur_delta_phase >> 10);
1694 symbol_width = AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz * 2;
1696 case AR5K_BWMODE_10MHZ:
1697 /* Both sample_freq and chip_freq are 20MHz (?) */
1698 spur_delta_phase = (spur_offset << 18) / 25;
1699 spur_freq_sigma_delta = (spur_delta_phase >> 10);
1700 symbol_width = AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz / 2;
1701 case AR5K_BWMODE_5MHZ:
1702 /* Both sample_freq and chip_freq are 10MHz (?) */
1703 spur_delta_phase = (spur_offset << 19) / 25;
1704 spur_freq_sigma_delta = (spur_delta_phase >> 10);
1705 symbol_width = AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz / 4;
1707 if (channel->band == IEEE80211_BAND_5GHZ) {
1708 /* Both sample_freq and chip_freq are 40MHz */
1709 spur_delta_phase = (spur_offset << 17) / 25;
1710 spur_freq_sigma_delta =
1711 (spur_delta_phase >> 10);
1713 AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz;
1715 /* sample_freq -> 40MHz chip_freq -> 44MHz
1716 * (for b compatibility) */
1717 spur_delta_phase = (spur_offset << 17) / 25;
1718 spur_freq_sigma_delta =
1719 (spur_offset << 8) / 55;
1721 AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz;
1726 /* Calculate pilot and magnitude masks */
1728 /* Scale up spur_offset by 1000 to switch to 100HZ resolution
1729 * and divide by symbol_width to find how many symbols we have
1730 * Note: number of symbols is scaled up by 16 */
1731 num_symbols_x16 = ((spur_offset * 1000) << 4) / symbol_width;
1733 /* Spur is on a symbol if num_symbols_x16 % 16 is zero */
1734 if (!(num_symbols_x16 & 0xF))
1736 num_symbol_offsets = 3;
1739 num_symbol_offsets = 4;
1741 for (i = 0; i < num_symbol_offsets; i++) {
1743 /* Calculate pilot mask */
1745 (num_symbols_x16 / 16) + i + 25;
1747 /* Pilot magnitude mask seems to be a way to
1748 * declare the boundaries for our detection
1749 * window or something, it's 2 for the middle
1750 * value(s) where the symbol is expected to be
1751 * and 1 on the boundary values */
1753 (i == 0 || i == (num_symbol_offsets - 1))
1756 if (curr_sym_off >= 0 && curr_sym_off <= 32) {
1757 if (curr_sym_off <= 25)
1758 pilot_mask[0] |= 1 << curr_sym_off;
1759 else if (curr_sym_off >= 27)
1760 pilot_mask[0] |= 1 << (curr_sym_off - 1);
1761 } else if (curr_sym_off >= 33 && curr_sym_off <= 52)
1762 pilot_mask[1] |= 1 << (curr_sym_off - 33);
1764 /* Calculate magnitude mask (for viterbi decoder) */
1765 if (curr_sym_off >= -1 && curr_sym_off <= 14)
1767 plt_mag_map << (curr_sym_off + 1) * 2;
1768 else if (curr_sym_off >= 15 && curr_sym_off <= 30)
1770 plt_mag_map << (curr_sym_off - 15) * 2;
1771 else if (curr_sym_off >= 31 && curr_sym_off <= 46)
1773 plt_mag_map << (curr_sym_off - 31) * 2;
1774 else if (curr_sym_off >= 47 && curr_sym_off <= 53)
1776 plt_mag_map << (curr_sym_off - 47) * 2;
1780 /* Write settings on hw to enable spur filter */
1781 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL,
1782 AR5K_PHY_BIN_MASK_CTL_RATE, 0xff);
1783 /* XXX: Self correlator also ? */
1784 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ,
1785 AR5K_PHY_IQ_PILOT_MASK_EN |
1786 AR5K_PHY_IQ_CHAN_MASK_EN |
1787 AR5K_PHY_IQ_SPUR_FILT_EN);
1789 /* Set delta phase and freq sigma delta */
1790 ath5k_hw_reg_write(ah,
1791 AR5K_REG_SM(spur_delta_phase,
1792 AR5K_PHY_TIMING_11_SPUR_DELTA_PHASE) |
1793 AR5K_REG_SM(spur_freq_sigma_delta,
1794 AR5K_PHY_TIMING_11_SPUR_FREQ_SD) |
1795 AR5K_PHY_TIMING_11_USE_SPUR_IN_AGC,
1796 AR5K_PHY_TIMING_11);
1798 /* Write pilot masks */
1799 ath5k_hw_reg_write(ah, pilot_mask[0], AR5K_PHY_TIMING_7);
1800 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_8,
1801 AR5K_PHY_TIMING_8_PILOT_MASK_2,
1804 ath5k_hw_reg_write(ah, pilot_mask[0], AR5K_PHY_TIMING_9);
1805 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_10,
1806 AR5K_PHY_TIMING_10_PILOT_MASK_2,
1809 /* Write magnitude masks */
1810 ath5k_hw_reg_write(ah, mag_mask[0], AR5K_PHY_BIN_MASK_1);
1811 ath5k_hw_reg_write(ah, mag_mask[1], AR5K_PHY_BIN_MASK_2);
1812 ath5k_hw_reg_write(ah, mag_mask[2], AR5K_PHY_BIN_MASK_3);
1813 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL,
1814 AR5K_PHY_BIN_MASK_CTL_MASK_4,
1817 ath5k_hw_reg_write(ah, mag_mask[0], AR5K_PHY_BIN_MASK2_1);
1818 ath5k_hw_reg_write(ah, mag_mask[1], AR5K_PHY_BIN_MASK2_2);
1819 ath5k_hw_reg_write(ah, mag_mask[2], AR5K_PHY_BIN_MASK2_3);
1820 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK2_4,
1821 AR5K_PHY_BIN_MASK2_4_MASK_4,
1824 } else if (ath5k_hw_reg_read(ah, AR5K_PHY_IQ) &
1825 AR5K_PHY_IQ_SPUR_FILT_EN) {
1826 /* Clean up spur mitigation settings and disable filter */
1827 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL,
1828 AR5K_PHY_BIN_MASK_CTL_RATE, 0);
1829 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_IQ,
1830 AR5K_PHY_IQ_PILOT_MASK_EN |
1831 AR5K_PHY_IQ_CHAN_MASK_EN |
1832 AR5K_PHY_IQ_SPUR_FILT_EN);
1833 ath5k_hw_reg_write(ah, 0, AR5K_PHY_TIMING_11);
1835 /* Clear pilot masks */
1836 ath5k_hw_reg_write(ah, 0, AR5K_PHY_TIMING_7);
1837 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_8,
1838 AR5K_PHY_TIMING_8_PILOT_MASK_2,
1841 ath5k_hw_reg_write(ah, 0, AR5K_PHY_TIMING_9);
1842 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_10,
1843 AR5K_PHY_TIMING_10_PILOT_MASK_2,
1846 /* Clear magnitude masks */
1847 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK_1);
1848 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK_2);
1849 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK_3);
1850 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL,
1851 AR5K_PHY_BIN_MASK_CTL_MASK_4,
1854 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK2_1);
1855 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK2_2);
1856 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK2_3);
1857 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK2_4,
1858 AR5K_PHY_BIN_MASK2_4_MASK_4,
1868 static void /*TODO:Boundary check*/
1869 ath5k_hw_set_def_antenna(struct ath5k_hw *ah, u8 ant)
1871 if (ah->ah_version != AR5K_AR5210)
1872 ath5k_hw_reg_write(ah, ant & 0x7, AR5K_DEFAULT_ANTENNA);
1876 * Enable/disable fast rx antenna diversity
1879 ath5k_hw_set_fast_div(struct ath5k_hw *ah, u8 ee_mode, bool enable)
1882 case AR5K_EEPROM_MODE_11G:
1883 /* XXX: This is set to
1884 * disabled on initvals !!! */
1885 case AR5K_EEPROM_MODE_11A:
1887 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGCCTL,
1888 AR5K_PHY_AGCCTL_OFDM_DIV_DIS);
1890 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
1891 AR5K_PHY_AGCCTL_OFDM_DIV_DIS);
1893 case AR5K_EEPROM_MODE_11B:
1894 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
1895 AR5K_PHY_AGCCTL_OFDM_DIV_DIS);
1902 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RESTART,
1903 AR5K_PHY_RESTART_DIV_GC, 4);
1905 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_FAST_ANT_DIV,
1906 AR5K_PHY_FAST_ANT_DIV_EN);
1908 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RESTART,
1909 AR5K_PHY_RESTART_DIV_GC, 0);
1911 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_FAST_ANT_DIV,
1912 AR5K_PHY_FAST_ANT_DIV_EN);
1917 ath5k_hw_set_antenna_switch(struct ath5k_hw *ah, u8 ee_mode)
1922 * In case a fixed antenna was set as default
1923 * use the same switch table twice.
1925 if (ah->ah_ant_mode == AR5K_ANTMODE_FIXED_A)
1926 ant0 = ant1 = AR5K_ANT_SWTABLE_A;
1927 else if (ah->ah_ant_mode == AR5K_ANTMODE_FIXED_B)
1928 ant0 = ant1 = AR5K_ANT_SWTABLE_B;
1930 ant0 = AR5K_ANT_SWTABLE_A;
1931 ant1 = AR5K_ANT_SWTABLE_B;
1934 /* Set antenna idle switch table */
1935 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_ANT_CTL,
1936 AR5K_PHY_ANT_CTL_SWTABLE_IDLE,
1937 (ah->ah_ant_ctl[ee_mode][AR5K_ANT_CTL] |
1938 AR5K_PHY_ANT_CTL_TXRX_EN));
1940 /* Set antenna switch tables */
1941 ath5k_hw_reg_write(ah, ah->ah_ant_ctl[ee_mode][ant0],
1942 AR5K_PHY_ANT_SWITCH_TABLE_0);
1943 ath5k_hw_reg_write(ah, ah->ah_ant_ctl[ee_mode][ant1],
1944 AR5K_PHY_ANT_SWITCH_TABLE_1);
1948 * Set antenna operating mode
1951 ath5k_hw_set_antenna_mode(struct ath5k_hw *ah, u8 ant_mode)
1953 struct ieee80211_channel *channel = ah->ah_current_channel;
1954 bool use_def_for_tx, update_def_on_tx, use_def_for_rts, fast_div;
1955 bool use_def_for_sg;
1960 /* if channel is not initialized yet we can't set the antennas
1961 * so just store the mode. it will be set on the next reset */
1962 if (channel == NULL) {
1963 ah->ah_ant_mode = ant_mode;
1967 def_ant = ah->ah_def_ant;
1969 ee_mode = ath5k_eeprom_mode_from_channel(channel);
1972 "invalid channel: %d\n", channel->center_freq);
1977 case AR5K_ANTMODE_DEFAULT:
1979 use_def_for_tx = false;
1980 update_def_on_tx = false;
1981 use_def_for_rts = false;
1982 use_def_for_sg = false;
1985 case AR5K_ANTMODE_FIXED_A:
1988 use_def_for_tx = true;
1989 update_def_on_tx = false;
1990 use_def_for_rts = true;
1991 use_def_for_sg = true;
1994 case AR5K_ANTMODE_FIXED_B:
1997 use_def_for_tx = true;
1998 update_def_on_tx = false;
1999 use_def_for_rts = true;
2000 use_def_for_sg = true;
2003 case AR5K_ANTMODE_SINGLE_AP:
2004 def_ant = 1; /* updated on tx */
2006 use_def_for_tx = true;
2007 update_def_on_tx = true;
2008 use_def_for_rts = true;
2009 use_def_for_sg = true;
2012 case AR5K_ANTMODE_SECTOR_AP:
2013 tx_ant = 1; /* variable */
2014 use_def_for_tx = false;
2015 update_def_on_tx = false;
2016 use_def_for_rts = true;
2017 use_def_for_sg = false;
2020 case AR5K_ANTMODE_SECTOR_STA:
2021 tx_ant = 1; /* variable */
2022 use_def_for_tx = true;
2023 update_def_on_tx = false;
2024 use_def_for_rts = true;
2025 use_def_for_sg = false;
2028 case AR5K_ANTMODE_DEBUG:
2031 use_def_for_tx = false;
2032 update_def_on_tx = false;
2033 use_def_for_rts = false;
2034 use_def_for_sg = false;
2041 ah->ah_tx_ant = tx_ant;
2042 ah->ah_ant_mode = ant_mode;
2043 ah->ah_def_ant = def_ant;
2045 sta_id1 |= use_def_for_tx ? AR5K_STA_ID1_DEFAULT_ANTENNA : 0;
2046 sta_id1 |= update_def_on_tx ? AR5K_STA_ID1_DESC_ANTENNA : 0;
2047 sta_id1 |= use_def_for_rts ? AR5K_STA_ID1_RTS_DEF_ANTENNA : 0;
2048 sta_id1 |= use_def_for_sg ? AR5K_STA_ID1_SELFGEN_DEF_ANT : 0;
2050 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, AR5K_STA_ID1_ANTENNA_SETTINGS);
2053 AR5K_REG_ENABLE_BITS(ah, AR5K_STA_ID1, sta_id1);
2055 ath5k_hw_set_antenna_switch(ah, ee_mode);
2056 /* Note: set diversity before default antenna
2057 * because it won't work correctly */
2058 ath5k_hw_set_fast_div(ah, ee_mode, fast_div);
2059 ath5k_hw_set_def_antenna(ah, def_ant);
2072 * Do linear interpolation between two given (x, y) points
2075 ath5k_get_interpolated_value(s16 target, s16 x_left, s16 x_right,
2076 s16 y_left, s16 y_right)
2080 /* Avoid divide by zero and skip interpolation
2081 * if we have the same point */
2082 if ((x_left == x_right) || (y_left == y_right))
2086 * Since we use ints and not fps, we need to scale up in
2087 * order to get a sane ratio value (or else we 'll eg. get
2088 * always 1 instead of 1.25, 1.75 etc). We scale up by 100
2089 * to have some accuracy both for 0.5 and 0.25 steps.
2091 ratio = ((100 * y_right - 100 * y_left) / (x_right - x_left));
2093 /* Now scale down to be in range */
2094 result = y_left + (ratio * (target - x_left) / 100);
2100 * Find vertical boundary (min pwr) for the linear PCDAC curve.
2102 * Since we have the top of the curve and we draw the line below
2103 * until we reach 1 (1 pcdac step) we need to know which point
2104 * (x value) that is so that we don't go below y axis and have negative
2105 * pcdac values when creating the curve, or fill the table with zeroes.
2108 ath5k_get_linear_pcdac_min(const u8 *stepL, const u8 *stepR,
2109 const s16 *pwrL, const s16 *pwrR)
2112 s16 min_pwrL, min_pwrR;
2115 /* Some vendors write the same pcdac value twice !!! */
2116 if (stepL[0] == stepL[1] || stepR[0] == stepR[1])
2117 return max(pwrL[0], pwrR[0]);
2119 if (pwrL[0] == pwrL[1])
2125 tmp = (s8) ath5k_get_interpolated_value(pwr_i,
2127 stepL[0], stepL[1]);
2133 if (pwrR[0] == pwrR[1])
2139 tmp = (s8) ath5k_get_interpolated_value(pwr_i,
2141 stepR[0], stepR[1]);
2147 /* Keep the right boundary so that it works for both curves */
2148 return max(min_pwrL, min_pwrR);
2152 * Interpolate (pwr,vpd) points to create a Power to PDADC or a
2153 * Power to PCDAC curve.
2155 * Each curve has power on x axis (in 0.5dB units) and PCDAC/PDADC
2156 * steps (offsets) on y axis. Power can go up to 31.5dB and max
2157 * PCDAC/PDADC step for each curve is 64 but we can write more than
2158 * one curves on hw so we can go up to 128 (which is the max step we
2159 * can write on the final table).
2161 * We write y values (PCDAC/PDADC steps) on hw.
2164 ath5k_create_power_curve(s16 pmin, s16 pmax,
2165 const s16 *pwr, const u8 *vpd,
2167 u8 *vpd_table, u8 type)
2169 u8 idx[2] = { 0, 1 };
2170 s16 pwr_i = 2 * pmin;
2176 /* We want the whole line, so adjust boundaries
2177 * to cover the entire power range. Note that
2178 * power values are already 0.25dB so no need
2179 * to multiply pwr_i by 2 */
2180 if (type == AR5K_PWRTABLE_LINEAR_PCDAC) {
2186 /* Find surrounding turning points (TPs)
2187 * and interpolate between them */
2188 for (i = 0; (i <= (u16) (pmax - pmin)) &&
2189 (i < AR5K_EEPROM_POWER_TABLE_SIZE); i++) {
2191 /* We passed the right TP, move to the next set of TPs
2192 * if we pass the last TP, extrapolate above using the last
2193 * two TPs for ratio */
2194 if ((pwr_i > pwr[idx[1]]) && (idx[1] < num_points - 1)) {
2199 vpd_table[i] = (u8) ath5k_get_interpolated_value(pwr_i,
2200 pwr[idx[0]], pwr[idx[1]],
2201 vpd[idx[0]], vpd[idx[1]]);
2203 /* Increase by 0.5dB
2204 * (0.25 dB units) */
2210 * Get the surrounding per-channel power calibration piers
2211 * for a given frequency so that we can interpolate between
2212 * them and come up with an appropriate dataset for our current
2216 ath5k_get_chan_pcal_surrounding_piers(struct ath5k_hw *ah,
2217 struct ieee80211_channel *channel,
2218 struct ath5k_chan_pcal_info **pcinfo_l,
2219 struct ath5k_chan_pcal_info **pcinfo_r)
2221 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
2222 struct ath5k_chan_pcal_info *pcinfo;
2225 u32 target = channel->center_freq;
2230 switch (channel->hw_value) {
2231 case AR5K_EEPROM_MODE_11A:
2232 pcinfo = ee->ee_pwr_cal_a;
2233 mode = AR5K_EEPROM_MODE_11A;
2235 case AR5K_EEPROM_MODE_11B:
2236 pcinfo = ee->ee_pwr_cal_b;
2237 mode = AR5K_EEPROM_MODE_11B;
2239 case AR5K_EEPROM_MODE_11G:
2241 pcinfo = ee->ee_pwr_cal_g;
2242 mode = AR5K_EEPROM_MODE_11G;
2245 max = ee->ee_n_piers[mode] - 1;
2247 /* Frequency is below our calibrated
2248 * range. Use the lowest power curve
2250 if (target < pcinfo[0].freq) {
2255 /* Frequency is above our calibrated
2256 * range. Use the highest power curve
2258 if (target > pcinfo[max].freq) {
2259 idx_l = idx_r = max;
2263 /* Frequency is inside our calibrated
2264 * channel range. Pick the surrounding
2265 * calibration piers so that we can
2267 for (i = 0; i <= max; i++) {
2269 /* Frequency matches one of our calibration
2270 * piers, no need to interpolate, just use
2271 * that calibration pier */
2272 if (pcinfo[i].freq == target) {
2277 /* We found a calibration pier that's above
2278 * frequency, use this pier and the previous
2279 * one to interpolate */
2280 if (target < pcinfo[i].freq) {
2288 *pcinfo_l = &pcinfo[idx_l];
2289 *pcinfo_r = &pcinfo[idx_r];
2293 * Get the surrounding per-rate power calibration data
2294 * for a given frequency and interpolate between power
2295 * values to set max target power supported by hw for
2299 ath5k_get_rate_pcal_data(struct ath5k_hw *ah,
2300 struct ieee80211_channel *channel,
2301 struct ath5k_rate_pcal_info *rates)
2303 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
2304 struct ath5k_rate_pcal_info *rpinfo;
2307 u32 target = channel->center_freq;
2312 switch (channel->hw_value) {
2314 rpinfo = ee->ee_rate_tpwr_a;
2315 mode = AR5K_EEPROM_MODE_11A;
2318 rpinfo = ee->ee_rate_tpwr_b;
2319 mode = AR5K_EEPROM_MODE_11B;
2323 rpinfo = ee->ee_rate_tpwr_g;
2324 mode = AR5K_EEPROM_MODE_11G;
2327 max = ee->ee_rate_target_pwr_num[mode] - 1;
2329 /* Get the surrounding calibration
2330 * piers - same as above */
2331 if (target < rpinfo[0].freq) {
2336 if (target > rpinfo[max].freq) {
2337 idx_l = idx_r = max;
2341 for (i = 0; i <= max; i++) {
2343 if (rpinfo[i].freq == target) {
2348 if (target < rpinfo[i].freq) {
2356 /* Now interpolate power value, based on the frequency */
2357 rates->freq = target;
2359 rates->target_power_6to24 =
2360 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq,
2362 rpinfo[idx_l].target_power_6to24,
2363 rpinfo[idx_r].target_power_6to24);
2365 rates->target_power_36 =
2366 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq,
2368 rpinfo[idx_l].target_power_36,
2369 rpinfo[idx_r].target_power_36);
2371 rates->target_power_48 =
2372 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq,
2374 rpinfo[idx_l].target_power_48,
2375 rpinfo[idx_r].target_power_48);
2377 rates->target_power_54 =
2378 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq,
2380 rpinfo[idx_l].target_power_54,
2381 rpinfo[idx_r].target_power_54);
2385 * Get the max edge power for this channel if
2386 * we have such data from EEPROM's Conformance Test
2387 * Limits (CTL), and limit max power if needed.
2390 ath5k_get_max_ctl_power(struct ath5k_hw *ah,
2391 struct ieee80211_channel *channel)
2393 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah);
2394 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
2395 struct ath5k_edge_power *rep = ee->ee_ctl_pwr;
2396 u8 *ctl_val = ee->ee_ctl;
2397 s16 max_chan_pwr = ah->ah_txpower.txp_max_pwr / 4;
2402 u32 target = channel->center_freq;
2404 ctl_mode = ath_regd_get_band_ctl(regulatory, channel->band);
2406 switch (channel->hw_value) {
2408 if (ah->ah_bwmode == AR5K_BWMODE_40MHZ)
2409 ctl_mode |= AR5K_CTL_TURBO;
2411 ctl_mode |= AR5K_CTL_11A;
2414 if (ah->ah_bwmode == AR5K_BWMODE_40MHZ)
2415 ctl_mode |= AR5K_CTL_TURBOG;
2417 ctl_mode |= AR5K_CTL_11G;
2420 ctl_mode |= AR5K_CTL_11B;
2426 for (i = 0; i < ee->ee_ctls; i++) {
2427 if (ctl_val[i] == ctl_mode) {
2433 /* If we have a CTL dataset available grab it and find the
2434 * edge power for our frequency */
2435 if (ctl_idx == 0xFF)
2438 /* Edge powers are sorted by frequency from lower
2439 * to higher. Each CTL corresponds to 8 edge power
2441 rep_idx = ctl_idx * AR5K_EEPROM_N_EDGES;
2443 /* Don't do boundaries check because we
2444 * might have more that one bands defined
2447 /* Get the edge power that's closer to our
2449 for (i = 0; i < AR5K_EEPROM_N_EDGES; i++) {
2451 if (target <= rep[rep_idx].freq)
2452 edge_pwr = (s16) rep[rep_idx].edge;
2456 ah->ah_txpower.txp_max_pwr = 4 * min(edge_pwr, max_chan_pwr);
2461 * Power to PCDAC table functions
2465 * Fill Power to PCDAC table on RF5111
2467 * No further processing is needed for RF5111, the only thing we have to
2468 * do is fill the values below and above calibration range since eeprom data
2469 * may not cover the entire PCDAC table.
2472 ath5k_fill_pwr_to_pcdac_table(struct ath5k_hw *ah, s16* table_min,
2475 u8 *pcdac_out = ah->ah_txpower.txp_pd_table;
2476 u8 *pcdac_tmp = ah->ah_txpower.tmpL[0];
2477 u8 pcdac_0, pcdac_n, pcdac_i, pwr_idx, i;
2478 s16 min_pwr, max_pwr;
2480 /* Get table boundaries */
2481 min_pwr = table_min[0];
2482 pcdac_0 = pcdac_tmp[0];
2484 max_pwr = table_max[0];
2485 pcdac_n = pcdac_tmp[table_max[0] - table_min[0]];
2487 /* Extrapolate below minimum using pcdac_0 */
2489 for (i = 0; i < min_pwr; i++)
2490 pcdac_out[pcdac_i++] = pcdac_0;
2492 /* Copy values from pcdac_tmp */
2494 for (i = 0; pwr_idx <= max_pwr &&
2495 pcdac_i < AR5K_EEPROM_POWER_TABLE_SIZE; i++) {
2496 pcdac_out[pcdac_i++] = pcdac_tmp[i];
2500 /* Extrapolate above maximum */
2501 while (pcdac_i < AR5K_EEPROM_POWER_TABLE_SIZE)
2502 pcdac_out[pcdac_i++] = pcdac_n;
2507 * Combine available XPD Curves and fill Linear Power to PCDAC table
2510 * RFX112 can have up to 2 curves (one for low txpower range and one for
2511 * higher txpower range). We need to put them both on pcdac_out and place
2512 * them in the correct location. In case we only have one curve available
2513 * just fit it on pcdac_out (it's supposed to cover the entire range of
2514 * available pwr levels since it's always the higher power curve). Extrapolate
2515 * below and above final table if needed.
2518 ath5k_combine_linear_pcdac_curves(struct ath5k_hw *ah, s16* table_min,
2519 s16 *table_max, u8 pdcurves)
2521 u8 *pcdac_out = ah->ah_txpower.txp_pd_table;
2528 s16 mid_pwr_idx = 0;
2529 /* Edge flag turns on the 7nth bit on the PCDAC
2530 * to declare the higher power curve (force values
2531 * to be greater than 64). If we only have one curve
2532 * we don't need to set this, if we have 2 curves and
2533 * fill the table backwards this can also be used to
2534 * switch from higher power curve to lower power curve */
2538 /* When we have only one curve available
2539 * that's the higher power curve. If we have
2540 * two curves the first is the high power curve
2541 * and the next is the low power curve. */
2543 pcdac_low_pwr = ah->ah_txpower.tmpL[1];
2544 pcdac_high_pwr = ah->ah_txpower.tmpL[0];
2545 mid_pwr_idx = table_max[1] - table_min[1] - 1;
2546 max_pwr_idx = (table_max[0] - table_min[0]) / 2;
2548 /* If table size goes beyond 31.5dB, keep the
2549 * upper 31.5dB range when setting tx power.
2550 * Note: 126 = 31.5 dB in quarter dB steps */
2551 if (table_max[0] - table_min[1] > 126)
2552 min_pwr_idx = table_max[0] - 126;
2554 min_pwr_idx = table_min[1];
2556 /* Since we fill table backwards
2557 * start from high power curve */
2558 pcdac_tmp = pcdac_high_pwr;
2562 pcdac_low_pwr = ah->ah_txpower.tmpL[1]; /* Zeroed */
2563 pcdac_high_pwr = ah->ah_txpower.tmpL[0];
2564 min_pwr_idx = table_min[0];
2565 max_pwr_idx = (table_max[0] - table_min[0]) / 2;
2566 pcdac_tmp = pcdac_high_pwr;
2570 /* This is used when setting tx power*/
2571 ah->ah_txpower.txp_min_idx = min_pwr_idx / 2;
2573 /* Fill Power to PCDAC table backwards */
2575 for (i = 63; i >= 0; i--) {
2576 /* Entering lower power range, reset
2577 * edge flag and set pcdac_tmp to lower
2579 if (edge_flag == 0x40 &&
2580 (2 * pwr <= (table_max[1] - table_min[0]) || pwr == 0)) {
2582 pcdac_tmp = pcdac_low_pwr;
2583 pwr = mid_pwr_idx / 2;
2586 /* Don't go below 1, extrapolate below if we have
2587 * already switched to the lower power curve -or
2588 * we only have one curve and edge_flag is zero
2590 if (pcdac_tmp[pwr] < 1 && (edge_flag == 0x00)) {
2592 pcdac_out[i] = pcdac_out[i + 1];
2598 pcdac_out[i] = pcdac_tmp[pwr] | edge_flag;
2600 /* Extrapolate above if pcdac is greater than
2601 * 126 -this can happen because we OR pcdac_out
2602 * value with edge_flag on high power curve */
2603 if (pcdac_out[i] > 126)
2606 /* Decrease by a 0.5dB step */
2611 /* Write PCDAC values on hw */
2613 ath5k_write_pcdac_table(struct ath5k_hw *ah)
2615 u8 *pcdac_out = ah->ah_txpower.txp_pd_table;
2619 * Write TX power values
2621 for (i = 0; i < (AR5K_EEPROM_POWER_TABLE_SIZE / 2); i++) {
2622 ath5k_hw_reg_write(ah,
2623 (((pcdac_out[2 * i + 0] << 8 | 0xff) & 0xffff) << 0) |
2624 (((pcdac_out[2 * i + 1] << 8 | 0xff) & 0xffff) << 16),
2625 AR5K_PHY_PCDAC_TXPOWER(i));
2631 * Power to PDADC table functions
2635 * Set the gain boundaries and create final Power to PDADC table
2637 * We can have up to 4 pd curves, we need to do a similar process
2638 * as we do for RF5112. This time we don't have an edge_flag but we
2639 * set the gain boundaries on a separate register.
2642 ath5k_combine_pwr_to_pdadc_curves(struct ath5k_hw *ah,
2643 s16 *pwr_min, s16 *pwr_max, u8 pdcurves)
2645 u8 gain_boundaries[AR5K_EEPROM_N_PD_GAINS];
2646 u8 *pdadc_out = ah->ah_txpower.txp_pd_table;
2649 u8 pdadc_i, pdadc_n, pwr_step, pdg, max_idx, table_size;
2652 /* Note: Register value is initialized on initvals
2653 * there is no feedback from hw.
2654 * XXX: What about pd_gain_overlap from EEPROM ? */
2655 pd_gain_overlap = (u8) ath5k_hw_reg_read(ah, AR5K_PHY_TPC_RG5) &
2656 AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAP;
2658 /* Create final PDADC table */
2659 for (pdg = 0, pdadc_i = 0; pdg < pdcurves; pdg++) {
2660 pdadc_tmp = ah->ah_txpower.tmpL[pdg];
2662 if (pdg == pdcurves - 1)
2663 /* 2 dB boundary stretch for last
2664 * (higher power) curve */
2665 gain_boundaries[pdg] = pwr_max[pdg] + 4;
2667 /* Set gain boundary in the middle
2668 * between this curve and the next one */
2669 gain_boundaries[pdg] =
2670 (pwr_max[pdg] + pwr_min[pdg + 1]) / 2;
2672 /* Sanity check in case our 2 db stretch got out of
2674 if (gain_boundaries[pdg] > AR5K_TUNE_MAX_TXPOWER)
2675 gain_boundaries[pdg] = AR5K_TUNE_MAX_TXPOWER;
2677 /* For the first curve (lower power)
2678 * start from 0 dB */
2682 /* For the other curves use the gain overlap */
2683 pdadc_0 = (gain_boundaries[pdg - 1] - pwr_min[pdg]) -
2686 /* Force each power step to be at least 0.5 dB */
2687 if ((pdadc_tmp[1] - pdadc_tmp[0]) > 1)
2688 pwr_step = pdadc_tmp[1] - pdadc_tmp[0];
2692 /* If pdadc_0 is negative, we need to extrapolate
2693 * below this pdgain by a number of pwr_steps */
2694 while ((pdadc_0 < 0) && (pdadc_i < 128)) {
2695 s16 tmp = pdadc_tmp[0] + pdadc_0 * pwr_step;
2696 pdadc_out[pdadc_i++] = (tmp < 0) ? 0 : (u8) tmp;
2700 /* Set last pwr level, using gain boundaries */
2701 pdadc_n = gain_boundaries[pdg] + pd_gain_overlap - pwr_min[pdg];
2702 /* Limit it to be inside pwr range */
2703 table_size = pwr_max[pdg] - pwr_min[pdg];
2704 max_idx = (pdadc_n < table_size) ? pdadc_n : table_size;
2706 /* Fill pdadc_out table */
2707 while (pdadc_0 < max_idx && pdadc_i < 128)
2708 pdadc_out[pdadc_i++] = pdadc_tmp[pdadc_0++];
2710 /* Need to extrapolate above this pdgain? */
2711 if (pdadc_n <= max_idx)
2714 /* Force each power step to be at least 0.5 dB */
2715 if ((pdadc_tmp[table_size - 1] - pdadc_tmp[table_size - 2]) > 1)
2716 pwr_step = pdadc_tmp[table_size - 1] -
2717 pdadc_tmp[table_size - 2];
2721 /* Extrapolate above */
2722 while ((pdadc_0 < (s16) pdadc_n) &&
2723 (pdadc_i < AR5K_EEPROM_POWER_TABLE_SIZE * 2)) {
2724 s16 tmp = pdadc_tmp[table_size - 1] +
2725 (pdadc_0 - max_idx) * pwr_step;
2726 pdadc_out[pdadc_i++] = (tmp > 127) ? 127 : (u8) tmp;
2731 while (pdg < AR5K_EEPROM_N_PD_GAINS) {
2732 gain_boundaries[pdg] = gain_boundaries[pdg - 1];
2736 while (pdadc_i < AR5K_EEPROM_POWER_TABLE_SIZE * 2) {
2737 pdadc_out[pdadc_i] = pdadc_out[pdadc_i - 1];
2741 /* Set gain boundaries */
2742 ath5k_hw_reg_write(ah,
2743 AR5K_REG_SM(pd_gain_overlap,
2744 AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAP) |
2745 AR5K_REG_SM(gain_boundaries[0],
2746 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_1) |
2747 AR5K_REG_SM(gain_boundaries[1],
2748 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_2) |
2749 AR5K_REG_SM(gain_boundaries[2],
2750 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_3) |
2751 AR5K_REG_SM(gain_boundaries[3],
2752 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_4),
2755 /* Used for setting rate power table */
2756 ah->ah_txpower.txp_min_idx = pwr_min[0];
2760 /* Write PDADC values on hw */
2762 ath5k_write_pwr_to_pdadc_table(struct ath5k_hw *ah, u8 ee_mode)
2764 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
2765 u8 *pdadc_out = ah->ah_txpower.txp_pd_table;
2766 u8 *pdg_to_idx = ee->ee_pdc_to_idx[ee_mode];
2767 u8 pdcurves = ee->ee_pd_gains[ee_mode];
2771 /* Select the right pdgain curves */
2773 /* Clear current settings */
2774 reg = ath5k_hw_reg_read(ah, AR5K_PHY_TPC_RG1);
2775 reg &= ~(AR5K_PHY_TPC_RG1_PDGAIN_1 |
2776 AR5K_PHY_TPC_RG1_PDGAIN_2 |
2777 AR5K_PHY_TPC_RG1_PDGAIN_3 |
2778 AR5K_PHY_TPC_RG1_NUM_PD_GAIN);
2781 * Use pd_gains curve from eeprom
2783 * This overrides the default setting from initvals
2784 * in case some vendors (e.g. Zcomax) don't use the default
2785 * curves. If we don't honor their settings we 'll get a
2786 * 5dB (1 * gain overlap ?) drop.
2788 reg |= AR5K_REG_SM(pdcurves, AR5K_PHY_TPC_RG1_NUM_PD_GAIN);
2792 reg |= AR5K_REG_SM(pdg_to_idx[2], AR5K_PHY_TPC_RG1_PDGAIN_3);
2795 reg |= AR5K_REG_SM(pdg_to_idx[1], AR5K_PHY_TPC_RG1_PDGAIN_2);
2798 reg |= AR5K_REG_SM(pdg_to_idx[0], AR5K_PHY_TPC_RG1_PDGAIN_1);
2801 ath5k_hw_reg_write(ah, reg, AR5K_PHY_TPC_RG1);
2804 * Write TX power values
2806 for (i = 0; i < (AR5K_EEPROM_POWER_TABLE_SIZE / 2); i++) {
2807 u32 val = get_unaligned_le32(&pdadc_out[4 * i]);
2808 ath5k_hw_reg_write(ah, val, AR5K_PHY_PDADC_TXPOWER(i));
2814 * Common code for PCDAC/PDADC tables
2818 * This is the main function that uses all of the above
2819 * to set PCDAC/PDADC table on hw for the current channel.
2820 * This table is used for tx power calibration on the baseband,
2821 * without it we get weird tx power levels and in some cases
2822 * distorted spectral mask
2825 ath5k_setup_channel_powertable(struct ath5k_hw *ah,
2826 struct ieee80211_channel *channel,
2827 u8 ee_mode, u8 type)
2829 struct ath5k_pdgain_info *pdg_L, *pdg_R;
2830 struct ath5k_chan_pcal_info *pcinfo_L;
2831 struct ath5k_chan_pcal_info *pcinfo_R;
2832 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
2833 u8 *pdg_curve_to_idx = ee->ee_pdc_to_idx[ee_mode];
2834 s16 table_min[AR5K_EEPROM_N_PD_GAINS];
2835 s16 table_max[AR5K_EEPROM_N_PD_GAINS];
2838 u32 target = channel->center_freq;
2841 /* Get surrounding freq piers for this channel */
2842 ath5k_get_chan_pcal_surrounding_piers(ah, channel,
2846 /* Loop over pd gain curves on
2847 * surrounding freq piers by index */
2848 for (pdg = 0; pdg < ee->ee_pd_gains[ee_mode]; pdg++) {
2850 /* Fill curves in reverse order
2851 * from lower power (max gain)
2852 * to higher power. Use curve -> idx
2853 * backmapping we did on eeprom init */
2854 u8 idx = pdg_curve_to_idx[pdg];
2856 /* Grab the needed curves by index */
2857 pdg_L = &pcinfo_L->pd_curves[idx];
2858 pdg_R = &pcinfo_R->pd_curves[idx];
2860 /* Initialize the temp tables */
2861 tmpL = ah->ah_txpower.tmpL[pdg];
2862 tmpR = ah->ah_txpower.tmpR[pdg];
2864 /* Set curve's x boundaries and create
2865 * curves so that they cover the same
2866 * range (if we don't do that one table
2867 * will have values on some range and the
2868 * other one won't have any so interpolation
2870 table_min[pdg] = min(pdg_L->pd_pwr[0],
2871 pdg_R->pd_pwr[0]) / 2;
2873 table_max[pdg] = max(pdg_L->pd_pwr[pdg_L->pd_points - 1],
2874 pdg_R->pd_pwr[pdg_R->pd_points - 1]) / 2;
2876 /* Now create the curves on surrounding channels
2877 * and interpolate if needed to get the final
2878 * curve for this gain on this channel */
2880 case AR5K_PWRTABLE_LINEAR_PCDAC:
2881 /* Override min/max so that we don't loose
2882 * accuracy (don't divide by 2) */
2883 table_min[pdg] = min(pdg_L->pd_pwr[0],
2887 max(pdg_L->pd_pwr[pdg_L->pd_points - 1],
2888 pdg_R->pd_pwr[pdg_R->pd_points - 1]);
2890 /* Override minimum so that we don't get
2891 * out of bounds while extrapolating
2892 * below. Don't do this when we have 2
2893 * curves and we are on the high power curve
2894 * because table_min is ok in this case */
2895 if (!(ee->ee_pd_gains[ee_mode] > 1 && pdg == 0)) {
2898 ath5k_get_linear_pcdac_min(pdg_L->pd_step,
2903 /* Don't go too low because we will
2904 * miss the upper part of the curve.
2905 * Note: 126 = 31.5dB (max power supported)
2906 * in 0.25dB units */
2907 if (table_max[pdg] - table_min[pdg] > 126)
2908 table_min[pdg] = table_max[pdg] - 126;
2912 case AR5K_PWRTABLE_PWR_TO_PCDAC:
2913 case AR5K_PWRTABLE_PWR_TO_PDADC:
2915 ath5k_create_power_curve(table_min[pdg],
2919 pdg_L->pd_points, tmpL, type);
2921 /* We are in a calibration
2922 * pier, no need to interpolate
2923 * between freq piers */
2924 if (pcinfo_L == pcinfo_R)
2927 ath5k_create_power_curve(table_min[pdg],
2931 pdg_R->pd_points, tmpR, type);
2937 /* Interpolate between curves
2938 * of surrounding freq piers to
2939 * get the final curve for this
2940 * pd gain. Re-use tmpL for interpolation
2942 for (i = 0; (i < (u16) (table_max[pdg] - table_min[pdg])) &&
2943 (i < AR5K_EEPROM_POWER_TABLE_SIZE); i++) {
2944 tmpL[i] = (u8) ath5k_get_interpolated_value(target,
2945 (s16) pcinfo_L->freq,
2946 (s16) pcinfo_R->freq,
2952 /* Now we have a set of curves for this
2953 * channel on tmpL (x range is table_max - table_min
2954 * and y values are tmpL[pdg][]) sorted in the same
2955 * order as EEPROM (because we've used the backmapping).
2956 * So for RF5112 it's from higher power to lower power
2957 * and for RF2413 it's from lower power to higher power.
2958 * For RF5111 we only have one curve. */
2960 /* Fill min and max power levels for this
2961 * channel by interpolating the values on
2962 * surrounding channels to complete the dataset */
2963 ah->ah_txpower.txp_min_pwr = ath5k_get_interpolated_value(target,
2964 (s16) pcinfo_L->freq,
2965 (s16) pcinfo_R->freq,
2966 pcinfo_L->min_pwr, pcinfo_R->min_pwr);
2968 ah->ah_txpower.txp_max_pwr = ath5k_get_interpolated_value(target,
2969 (s16) pcinfo_L->freq,
2970 (s16) pcinfo_R->freq,
2971 pcinfo_L->max_pwr, pcinfo_R->max_pwr);
2973 /* Fill PCDAC/PDADC table */
2975 case AR5K_PWRTABLE_LINEAR_PCDAC:
2976 /* For RF5112 we can have one or two curves
2977 * and each curve covers a certain power lvl
2978 * range so we need to do some more processing */
2979 ath5k_combine_linear_pcdac_curves(ah, table_min, table_max,
2980 ee->ee_pd_gains[ee_mode]);
2982 /* Set txp.offset so that we can
2983 * match max power value with max
2985 ah->ah_txpower.txp_offset = 64 - (table_max[0] / 2);
2987 case AR5K_PWRTABLE_PWR_TO_PCDAC:
2988 /* We are done for RF5111 since it has only
2989 * one curve, just fit the curve on the table */
2990 ath5k_fill_pwr_to_pcdac_table(ah, table_min, table_max);
2992 /* No rate powertable adjustment for RF5111 */
2993 ah->ah_txpower.txp_min_idx = 0;
2994 ah->ah_txpower.txp_offset = 0;
2996 case AR5K_PWRTABLE_PWR_TO_PDADC:
2997 /* Set PDADC boundaries and fill
2998 * final PDADC table */
2999 ath5k_combine_pwr_to_pdadc_curves(ah, table_min, table_max,
3000 ee->ee_pd_gains[ee_mode]);
3002 /* Set txp.offset, note that table_min
3003 * can be negative */
3004 ah->ah_txpower.txp_offset = table_min[0];
3010 ah->ah_txpower.txp_setup = true;
3015 /* Write power table for current channel to hw */
3017 ath5k_write_channel_powertable(struct ath5k_hw *ah, u8 ee_mode, u8 type)
3019 if (type == AR5K_PWRTABLE_PWR_TO_PDADC)
3020 ath5k_write_pwr_to_pdadc_table(ah, ee_mode);
3022 ath5k_write_pcdac_table(ah);
3026 * Per-rate tx power setting
3028 * This is the code that sets the desired tx power (below
3029 * maximum) on hw for each rate (we also have TPC that sets
3030 * power per packet). We do that by providing an index on the
3031 * PCDAC/PDADC table we set up.
3035 * Set rate power table
3037 * For now we only limit txpower based on maximum tx power
3038 * supported by hw (what's inside rate_info). We need to limit
3039 * this even more, based on regulatory domain etc.
3041 * Rate power table contains indices to PCDAC/PDADC table (0.5dB steps)
3042 * and is indexed as follows:
3043 * rates[0] - rates[7] -> OFDM rates
3044 * rates[8] - rates[14] -> CCK rates
3045 * rates[15] -> XR rates (they all have the same power)
3048 ath5k_setup_rate_powertable(struct ath5k_hw *ah, u16 max_pwr,
3049 struct ath5k_rate_pcal_info *rate_info,
3055 /* max_pwr is power level we got from driver/user in 0.5dB
3056 * units, switch to 0.25dB units so we can compare */
3058 max_pwr = min(max_pwr, (u16) ah->ah_txpower.txp_max_pwr) / 2;
3060 /* apply rate limits */
3061 rates = ah->ah_txpower.txp_rates_power_table;
3063 /* OFDM rates 6 to 24Mb/s */
3064 for (i = 0; i < 5; i++)
3065 rates[i] = min(max_pwr, rate_info->target_power_6to24);
3067 /* Rest OFDM rates */
3068 rates[5] = min(rates[0], rate_info->target_power_36);
3069 rates[6] = min(rates[0], rate_info->target_power_48);
3070 rates[7] = min(rates[0], rate_info->target_power_54);
3074 rates[8] = min(rates[0], rate_info->target_power_6to24);
3076 rates[9] = min(rates[0], rate_info->target_power_36);
3078 rates[10] = min(rates[0], rate_info->target_power_36);
3080 rates[11] = min(rates[0], rate_info->target_power_48);
3082 rates[12] = min(rates[0], rate_info->target_power_48);
3084 rates[13] = min(rates[0], rate_info->target_power_54);
3086 rates[14] = min(rates[0], rate_info->target_power_54);
3089 rates[15] = min(rates[0], rate_info->target_power_6to24);
3091 /* CCK rates have different peak to average ratio
3092 * so we have to tweak their power so that gainf
3093 * correction works ok. For this we use OFDM to
3094 * CCK delta from eeprom */
3095 if ((ee_mode == AR5K_EEPROM_MODE_11G) &&
3096 (ah->ah_phy_revision < AR5K_SREV_PHY_5212A))
3097 for (i = 8; i <= 15; i++)
3098 rates[i] -= ah->ah_txpower.txp_cck_ofdm_gainf_delta;
3100 /* Now that we have all rates setup use table offset to
3101 * match the power range set by user with the power indices
3102 * on PCDAC/PDADC table */
3103 for (i = 0; i < 16; i++) {
3104 rates[i] += ah->ah_txpower.txp_offset;
3105 /* Don't get out of bounds */
3110 /* Min/max in 0.25dB units */
3111 ah->ah_txpower.txp_min_pwr = 2 * rates[7];
3112 ah->ah_txpower.txp_cur_pwr = 2 * rates[0];
3113 ah->ah_txpower.txp_ofdm = rates[7];
3118 * Set transmission power
3121 ath5k_hw_txpower(struct ath5k_hw *ah, struct ieee80211_channel *channel,
3124 struct ath5k_rate_pcal_info rate_info;
3125 struct ieee80211_channel *curr_channel = ah->ah_current_channel;
3130 if (txpower > AR5K_TUNE_MAX_TXPOWER) {
3131 ATH5K_ERR(ah, "invalid tx power: %u\n", txpower);
3135 ee_mode = ath5k_eeprom_mode_from_channel(channel);
3138 "invalid channel: %d\n", channel->center_freq);
3142 /* Initialize TX power table */
3143 switch (ah->ah_radio) {
3148 type = AR5K_PWRTABLE_PWR_TO_PCDAC;
3151 type = AR5K_PWRTABLE_LINEAR_PCDAC;
3158 type = AR5K_PWRTABLE_PWR_TO_PDADC;
3165 * If we don't change channel/mode skip tx powertable calculation
3166 * and use the cached one.
3168 if (!ah->ah_txpower.txp_setup ||
3169 (channel->hw_value != curr_channel->hw_value) ||
3170 (channel->center_freq != curr_channel->center_freq)) {
3171 /* Reset TX power values */
3172 memset(&ah->ah_txpower, 0, sizeof(ah->ah_txpower));
3173 ah->ah_txpower.txp_tpc = AR5K_TUNE_TPC_TXPOWER;
3175 /* Calculate the powertable */
3176 ret = ath5k_setup_channel_powertable(ah, channel,
3182 /* Write table on hw */
3183 ath5k_write_channel_powertable(ah, ee_mode, type);
3185 /* Limit max power if we have a CTL available */
3186 ath5k_get_max_ctl_power(ah, channel);
3188 /* FIXME: Antenna reduction stuff */
3190 /* FIXME: Limit power on turbo modes */
3192 /* FIXME: TPC scale reduction */
3194 /* Get surrounding channels for per-rate power table
3196 ath5k_get_rate_pcal_data(ah, channel, &rate_info);
3198 /* Setup rate power table */
3199 ath5k_setup_rate_powertable(ah, txpower, &rate_info, ee_mode);
3201 /* Write rate power table on hw */
3202 ath5k_hw_reg_write(ah, AR5K_TXPOWER_OFDM(3, 24) |
3203 AR5K_TXPOWER_OFDM(2, 16) | AR5K_TXPOWER_OFDM(1, 8) |
3204 AR5K_TXPOWER_OFDM(0, 0), AR5K_PHY_TXPOWER_RATE1);
3206 ath5k_hw_reg_write(ah, AR5K_TXPOWER_OFDM(7, 24) |
3207 AR5K_TXPOWER_OFDM(6, 16) | AR5K_TXPOWER_OFDM(5, 8) |
3208 AR5K_TXPOWER_OFDM(4, 0), AR5K_PHY_TXPOWER_RATE2);
3210 ath5k_hw_reg_write(ah, AR5K_TXPOWER_CCK(10, 24) |
3211 AR5K_TXPOWER_CCK(9, 16) | AR5K_TXPOWER_CCK(15, 8) |
3212 AR5K_TXPOWER_CCK(8, 0), AR5K_PHY_TXPOWER_RATE3);
3214 ath5k_hw_reg_write(ah, AR5K_TXPOWER_CCK(14, 24) |
3215 AR5K_TXPOWER_CCK(13, 16) | AR5K_TXPOWER_CCK(12, 8) |
3216 AR5K_TXPOWER_CCK(11, 0), AR5K_PHY_TXPOWER_RATE4);
3218 /* FIXME: TPC support */
3219 if (ah->ah_txpower.txp_tpc) {
3220 ath5k_hw_reg_write(ah, AR5K_PHY_TXPOWER_RATE_MAX_TPC_ENABLE |
3221 AR5K_TUNE_MAX_TXPOWER, AR5K_PHY_TXPOWER_RATE_MAX);
3223 ath5k_hw_reg_write(ah,
3224 AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER, AR5K_TPC_ACK) |
3225 AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER, AR5K_TPC_CTS) |
3226 AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER, AR5K_TPC_CHIRP),
3229 ath5k_hw_reg_write(ah, AR5K_PHY_TXPOWER_RATE_MAX |
3230 AR5K_TUNE_MAX_TXPOWER, AR5K_PHY_TXPOWER_RATE_MAX);
3236 int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, u8 txpower)
3238 ATH5K_DBG(ah, ATH5K_DEBUG_TXPOWER,
3239 "changing txpower to %d\n", txpower);
3241 return ath5k_hw_txpower(ah, ah->ah_current_channel, txpower);
3248 int ath5k_hw_phy_init(struct ath5k_hw *ah, struct ieee80211_channel *channel,
3251 struct ieee80211_channel *curr_channel;
3257 * Sanity check for fast flag
3258 * Don't try fast channel change when changing modulation
3259 * mode/band. We check for chip compatibility on
3262 curr_channel = ah->ah_current_channel;
3263 if (fast && (channel->hw_value != curr_channel->hw_value))
3267 * On fast channel change we only set the synth parameters
3268 * while PHY is running, enable calibration and skip the rest.
3271 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_RFBUS_REQ,
3272 AR5K_PHY_RFBUS_REQ_REQUEST);
3273 for (i = 0; i < 100; i++) {
3274 if (ath5k_hw_reg_read(ah, AR5K_PHY_RFBUS_GRANT))
3282 /* Set channel and wait for synth */
3283 ret = ath5k_hw_channel(ah, channel);
3287 ath5k_hw_wait_for_synth(ah, channel);
3293 * Note: We need to do that before we set
3294 * RF buffer settings on 5211/5212+ so that we
3295 * properly set curve indices.
3297 ret = ath5k_hw_txpower(ah, channel, ah->ah_txpower.txp_cur_pwr ?
3298 ah->ah_txpower.txp_cur_pwr / 2 : AR5K_TUNE_MAX_TXPOWER);
3302 /* Write OFDM timings on 5212*/
3303 if (ah->ah_version == AR5K_AR5212 &&
3304 channel->hw_value != AR5K_MODE_11B) {
3306 ret = ath5k_hw_write_ofdm_timings(ah, channel);
3310 /* Spur info is available only from EEPROM versions
3311 * greater than 5.3, but the EEPROM routines will use
3312 * static values for older versions */
3313 if (ah->ah_mac_srev >= AR5K_SREV_AR5424)
3314 ath5k_hw_set_spur_mitigation_filter(ah,
3318 /* If we used fast channel switching
3319 * we are done, release RF bus and
3320 * fire up NF calibration.
3322 * Note: Only NF calibration due to
3323 * channel change, not AGC calibration
3324 * since AGC is still running !
3328 * Release RF Bus grant
3330 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_RFBUS_REQ,
3331 AR5K_PHY_RFBUS_REQ_REQUEST);
3334 * Start NF calibration
3336 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
3337 AR5K_PHY_AGCCTL_NF);
3343 * For 5210 we do all initialization using
3344 * initvals, so we don't have to modify
3345 * any settings (5210 also only supports
3348 if (ah->ah_version != AR5K_AR5210) {
3351 * Write initial RF gain settings
3352 * This should work for both 5111/5112
3354 ret = ath5k_hw_rfgain_init(ah, channel->band);
3363 ret = ath5k_hw_rfregs_init(ah, channel, mode);
3367 /*Enable/disable 802.11b mode on 5111
3368 (enable 2111 frequency converter + CCK)*/
3369 if (ah->ah_radio == AR5K_RF5111) {
3370 if (mode == AR5K_MODE_11B)
3371 AR5K_REG_ENABLE_BITS(ah, AR5K_TXCFG,
3374 AR5K_REG_DISABLE_BITS(ah, AR5K_TXCFG,
3378 } else if (ah->ah_version == AR5K_AR5210) {
3380 /* Disable phy and wait */
3381 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT);
3385 /* Set channel on PHY */
3386 ret = ath5k_hw_channel(ah, channel);
3391 * Enable the PHY and wait until completion
3392 * This includes BaseBand and Synthesizer
3395 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT);
3397 ath5k_hw_wait_for_synth(ah, channel);
3400 * Perform ADC test to see if baseband is ready
3401 * Set tx hold and check adc test register
3403 phy_tst1 = ath5k_hw_reg_read(ah, AR5K_PHY_TST1);
3404 ath5k_hw_reg_write(ah, AR5K_PHY_TST1_TXHOLD, AR5K_PHY_TST1);
3405 for (i = 0; i <= 20; i++) {
3406 if (!(ath5k_hw_reg_read(ah, AR5K_PHY_ADC_TEST) & 0x10))
3410 ath5k_hw_reg_write(ah, phy_tst1, AR5K_PHY_TST1);
3413 * Start automatic gain control calibration
3415 * During AGC calibration RX path is re-routed to
3416 * a power detector so we don't receive anything.
3418 * This method is used to calibrate some static offsets
3419 * used together with on-the fly I/Q calibration (the
3420 * one performed via ath5k_hw_phy_calibrate), which doesn't
3421 * interrupt rx path.
3423 * While rx path is re-routed to the power detector we also
3424 * start a noise floor calibration to measure the
3425 * card's noise floor (the noise we measure when we are not
3426 * transmitting or receiving anything).
3428 * If we are in a noisy environment, AGC calibration may time
3429 * out and/or noise floor calibration might timeout.
3431 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
3432 AR5K_PHY_AGCCTL_CAL | AR5K_PHY_AGCCTL_NF);
3434 /* At the same time start I/Q calibration for QAM constellation
3435 * -no need for CCK- */
3436 ah->ah_calibration = false;
3437 if (!(mode == AR5K_MODE_11B)) {
3438 ah->ah_calibration = true;
3439 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ,
3440 AR5K_PHY_IQ_CAL_NUM_LOG_MAX, 15);
3441 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ,
3445 /* Wait for gain calibration to finish (we check for I/Q calibration
3446 * during ath5k_phy_calibrate) */
3447 if (ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL,
3448 AR5K_PHY_AGCCTL_CAL, 0, false)) {
3449 ATH5K_ERR(ah, "gain calibration timeout (%uMHz)\n",
3450 channel->center_freq);
3453 /* Restore antenna mode */
3454 ath5k_hw_set_antenna_mode(ah, ah->ah_ant_mode);