4 * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org>
5 * Copyright (c) 2006-2009 Nick Kossifidis <mickflemm@gmail.com>
6 * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com>
7 * Copyright (c) 2008-2009 Felix Fietkau <nbd@openwrt.org>
9 * Permission to use, copy, modify, and distribute this software for any
10 * purpose with or without fee is hereby granted, provided that the above
11 * copyright notice and this permission notice appear in all copies.
13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
18 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
19 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
23 #include <linux/delay.h>
24 #include <linux/slab.h>
33 * Used to modify RF Banks before writing them to AR5K_RF_BUFFER
35 static unsigned int ath5k_hw_rfb_op(struct ath5k_hw *ah,
36 const struct ath5k_rf_reg *rf_regs,
37 u32 val, u8 reg_id, bool set)
39 const struct ath5k_rf_reg *rfreg = NULL;
40 u8 offset, bank, num_bits, col, position;
42 u32 mask, data, last_bit, bits_shifted, first_bit;
48 rfb = ah->ah_rf_banks;
50 for (i = 0; i < ah->ah_rf_regs_count; i++) {
51 if (rf_regs[i].index == reg_id) {
57 if (rfb == NULL || rfreg == NULL) {
58 ATH5K_PRINTF("Rf register not found!\n");
59 /* should not happen */
64 num_bits = rfreg->field.len;
65 first_bit = rfreg->field.pos;
66 col = rfreg->field.col;
68 /* first_bit is an offset from bank's
69 * start. Since we have all banks on
70 * the same array, we use this offset
71 * to mark each bank's start */
72 offset = ah->ah_offset[bank];
75 if (!(col <= 3 && num_bits <= 32 && first_bit + num_bits <= 319)) {
76 ATH5K_PRINTF("invalid values at offset %u\n", offset);
80 entry = ((first_bit - 1) / 8) + offset;
81 position = (first_bit - 1) % 8;
84 data = ath5k_hw_bitswap(val, num_bits);
86 for (bits_shifted = 0, bits_left = num_bits; bits_left > 0;
87 position = 0, entry++) {
89 last_bit = (position + bits_left > 8) ? 8 :
92 mask = (((1 << last_bit) - 1) ^ ((1 << position) - 1)) <<
97 rfb[entry] |= ((data << position) << (col * 8)) & mask;
98 data >>= (8 - position);
100 data |= (((rfb[entry] & mask) >> (col * 8)) >> position)
102 bits_shifted += last_bit - position;
105 bits_left -= 8 - position;
108 data = set ? 1 : ath5k_hw_bitswap(data, num_bits);
113 /**********************\
114 * RF Gain optimization *
115 \**********************/
118 * This code is used to optimize rf gain on different environments
119 * (temperature mostly) based on feedback from a power detector.
121 * It's only used on RF5111 and RF5112, later RF chips seem to have
122 * auto adjustment on hw -notice they have a much smaller BANK 7 and
123 * no gain optimization ladder-.
125 * For more infos check out this patent doc
126 * http://www.freepatentsonline.com/7400691.html
128 * This paper describes power drops as seen on the receiver due to
130 * http://www.cnri.dit.ie/publications/ICT08%20-%20Practical%20Issues
131 * %20of%20Power%20Control.pdf
133 * And this is the MadWiFi bug entry related to the above
134 * http://madwifi-project.org/ticket/1659
135 * with various measurements and diagrams
137 * TODO: Deal with power drops due to probes by setting an apropriate
138 * tx power on the probe packets ! Make this part of the calibration process.
141 /* Initialize ah_gain durring attach */
142 int ath5k_hw_rfgain_opt_init(struct ath5k_hw *ah)
144 /* Initialize the gain optimization values */
145 switch (ah->ah_radio) {
147 ah->ah_gain.g_step_idx = rfgain_opt_5111.go_default;
148 ah->ah_gain.g_low = 20;
149 ah->ah_gain.g_high = 35;
150 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
153 ah->ah_gain.g_step_idx = rfgain_opt_5112.go_default;
154 ah->ah_gain.g_low = 20;
155 ah->ah_gain.g_high = 85;
156 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
165 /* Schedule a gain probe check on the next transmited packet.
166 * That means our next packet is going to be sent with lower
167 * tx power and a Peak to Average Power Detector (PAPD) will try
168 * to measure the gain.
170 * XXX: How about forcing a tx packet (bypassing PCU arbitrator etc)
171 * just after we enable the probe so that we don't mess with
172 * standard traffic ? Maybe it's time to use sw interrupts and
173 * a probe tasklet !!!
175 static void ath5k_hw_request_rfgain_probe(struct ath5k_hw *ah)
178 /* Skip if gain calibration is inactive or
179 * we already handle a probe request */
180 if (ah->ah_gain.g_state != AR5K_RFGAIN_ACTIVE)
183 /* Send the packet with 2dB below max power as
184 * patent doc suggest */
185 ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txpower.txp_ofdm - 4,
186 AR5K_PHY_PAPD_PROBE_TXPOWER) |
187 AR5K_PHY_PAPD_PROBE_TX_NEXT, AR5K_PHY_PAPD_PROBE);
189 ah->ah_gain.g_state = AR5K_RFGAIN_READ_REQUESTED;
193 /* Calculate gain_F measurement correction
194 * based on the current step for RF5112 rev. 2 */
195 static u32 ath5k_hw_rf_gainf_corr(struct ath5k_hw *ah)
199 const struct ath5k_gain_opt *go;
200 const struct ath5k_gain_opt_step *g_step;
201 const struct ath5k_rf_reg *rf_regs;
203 /* Only RF5112 Rev. 2 supports it */
204 if ((ah->ah_radio != AR5K_RF5112) ||
205 (ah->ah_radio_5ghz_revision <= AR5K_SREV_RAD_5112A))
208 go = &rfgain_opt_5112;
209 rf_regs = rf_regs_5112a;
210 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112a);
212 g_step = &go->go_step[ah->ah_gain.g_step_idx];
214 if (ah->ah_rf_banks == NULL)
217 rf = ah->ah_rf_banks;
218 ah->ah_gain.g_f_corr = 0;
220 /* No VGA (Variable Gain Amplifier) override, skip */
221 if (ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXVGA_OVR, false) != 1)
224 /* Mix gain stepping */
225 step = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXGAIN_STEP, false);
227 /* Mix gain override */
228 mix = g_step->gos_param[0];
232 ah->ah_gain.g_f_corr = step * 2;
235 ah->ah_gain.g_f_corr = (step - 5) * 2;
238 ah->ah_gain.g_f_corr = step;
241 ah->ah_gain.g_f_corr = 0;
245 return ah->ah_gain.g_f_corr;
248 /* Check if current gain_F measurement is in the range of our
249 * power detector windows. If we get a measurement outside range
250 * we know it's not accurate (detectors can't measure anything outside
251 * their detection window) so we must ignore it */
252 static bool ath5k_hw_rf_check_gainf_readback(struct ath5k_hw *ah)
254 const struct ath5k_rf_reg *rf_regs;
255 u32 step, mix_ovr, level[4];
258 if (ah->ah_rf_banks == NULL)
261 rf = ah->ah_rf_banks;
263 if (ah->ah_radio == AR5K_RF5111) {
265 rf_regs = rf_regs_5111;
266 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5111);
268 step = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_RFGAIN_STEP,
272 level[1] = (step == 63) ? 50 : step + 4;
273 level[2] = (step != 63) ? 64 : level[0];
274 level[3] = level[2] + 50 ;
276 ah->ah_gain.g_high = level[3] -
277 (step == 63 ? AR5K_GAIN_DYN_ADJUST_HI_MARGIN : -5);
278 ah->ah_gain.g_low = level[0] +
279 (step == 63 ? AR5K_GAIN_DYN_ADJUST_LO_MARGIN : 0);
282 rf_regs = rf_regs_5112;
283 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112);
285 mix_ovr = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXVGA_OVR,
288 level[0] = level[2] = 0;
291 level[1] = level[3] = 83;
293 level[1] = level[3] = 107;
294 ah->ah_gain.g_high = 55;
298 return (ah->ah_gain.g_current >= level[0] &&
299 ah->ah_gain.g_current <= level[1]) ||
300 (ah->ah_gain.g_current >= level[2] &&
301 ah->ah_gain.g_current <= level[3]);
304 /* Perform gain_F adjustment by choosing the right set
305 * of parameters from rf gain optimization ladder */
306 static s8 ath5k_hw_rf_gainf_adjust(struct ath5k_hw *ah)
308 const struct ath5k_gain_opt *go;
309 const struct ath5k_gain_opt_step *g_step;
312 switch (ah->ah_radio) {
314 go = &rfgain_opt_5111;
317 go = &rfgain_opt_5112;
323 g_step = &go->go_step[ah->ah_gain.g_step_idx];
325 if (ah->ah_gain.g_current >= ah->ah_gain.g_high) {
327 /* Reached maximum */
328 if (ah->ah_gain.g_step_idx == 0)
331 for (ah->ah_gain.g_target = ah->ah_gain.g_current;
332 ah->ah_gain.g_target >= ah->ah_gain.g_high &&
333 ah->ah_gain.g_step_idx > 0;
334 g_step = &go->go_step[ah->ah_gain.g_step_idx])
335 ah->ah_gain.g_target -= 2 *
336 (go->go_step[--(ah->ah_gain.g_step_idx)].gos_gain -
343 if (ah->ah_gain.g_current <= ah->ah_gain.g_low) {
345 /* Reached minimum */
346 if (ah->ah_gain.g_step_idx == (go->go_steps_count - 1))
349 for (ah->ah_gain.g_target = ah->ah_gain.g_current;
350 ah->ah_gain.g_target <= ah->ah_gain.g_low &&
351 ah->ah_gain.g_step_idx < go->go_steps_count-1;
352 g_step = &go->go_step[ah->ah_gain.g_step_idx])
353 ah->ah_gain.g_target -= 2 *
354 (go->go_step[++ah->ah_gain.g_step_idx].gos_gain -
362 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
363 "ret %d, gain step %u, current gain %u, target gain %u\n",
364 ret, ah->ah_gain.g_step_idx, ah->ah_gain.g_current,
365 ah->ah_gain.g_target);
370 /* Main callback for thermal rf gain calibration engine
371 * Check for a new gain reading and schedule an adjustment
374 * TODO: Use sw interrupt to schedule reset if gain_F needs
376 enum ath5k_rfgain ath5k_hw_gainf_calibrate(struct ath5k_hw *ah)
379 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
381 ATH5K_TRACE(ah->ah_sc);
383 if (ah->ah_rf_banks == NULL ||
384 ah->ah_gain.g_state == AR5K_RFGAIN_INACTIVE)
385 return AR5K_RFGAIN_INACTIVE;
387 /* No check requested, either engine is inactive
388 * or an adjustment is already requested */
389 if (ah->ah_gain.g_state != AR5K_RFGAIN_READ_REQUESTED)
392 /* Read the PAPD (Peak to Average Power Detector)
394 data = ath5k_hw_reg_read(ah, AR5K_PHY_PAPD_PROBE);
396 /* No probe is scheduled, read gain_F measurement */
397 if (!(data & AR5K_PHY_PAPD_PROBE_TX_NEXT)) {
398 ah->ah_gain.g_current = data >> AR5K_PHY_PAPD_PROBE_GAINF_S;
399 type = AR5K_REG_MS(data, AR5K_PHY_PAPD_PROBE_TYPE);
401 /* If tx packet is CCK correct the gain_F measurement
402 * by cck ofdm gain delta */
403 if (type == AR5K_PHY_PAPD_PROBE_TYPE_CCK) {
404 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A)
405 ah->ah_gain.g_current +=
406 ee->ee_cck_ofdm_gain_delta;
408 ah->ah_gain.g_current +=
409 AR5K_GAIN_CCK_PROBE_CORR;
412 /* Further correct gain_F measurement for
414 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) {
415 ath5k_hw_rf_gainf_corr(ah);
416 ah->ah_gain.g_current =
417 ah->ah_gain.g_current >= ah->ah_gain.g_f_corr ?
418 (ah->ah_gain.g_current-ah->ah_gain.g_f_corr) :
422 /* Check if measurement is ok and if we need
423 * to adjust gain, schedule a gain adjustment,
424 * else switch back to the acive state */
425 if (ath5k_hw_rf_check_gainf_readback(ah) &&
426 AR5K_GAIN_CHECK_ADJUST(&ah->ah_gain) &&
427 ath5k_hw_rf_gainf_adjust(ah)) {
428 ah->ah_gain.g_state = AR5K_RFGAIN_NEED_CHANGE;
430 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
435 return ah->ah_gain.g_state;
438 /* Write initial rf gain table to set the RF sensitivity
439 * this one works on all RF chips and has nothing to do
440 * with gain_F calibration */
441 int ath5k_hw_rfgain_init(struct ath5k_hw *ah, unsigned int freq)
443 const struct ath5k_ini_rfgain *ath5k_rfg;
444 unsigned int i, size;
446 switch (ah->ah_radio) {
448 ath5k_rfg = rfgain_5111;
449 size = ARRAY_SIZE(rfgain_5111);
452 ath5k_rfg = rfgain_5112;
453 size = ARRAY_SIZE(rfgain_5112);
456 ath5k_rfg = rfgain_2413;
457 size = ARRAY_SIZE(rfgain_2413);
460 ath5k_rfg = rfgain_2316;
461 size = ARRAY_SIZE(rfgain_2316);
464 ath5k_rfg = rfgain_5413;
465 size = ARRAY_SIZE(rfgain_5413);
469 ath5k_rfg = rfgain_2425;
470 size = ARRAY_SIZE(rfgain_2425);
477 case AR5K_INI_RFGAIN_2GHZ:
478 case AR5K_INI_RFGAIN_5GHZ:
484 for (i = 0; i < size; i++) {
486 ath5k_hw_reg_write(ah, ath5k_rfg[i].rfg_value[freq],
487 (u32)ath5k_rfg[i].rfg_register);
495 /********************\
496 * RF Registers setup *
497 \********************/
501 * Setup RF registers by writing rf buffer on hw
503 int ath5k_hw_rfregs_init(struct ath5k_hw *ah, struct ieee80211_channel *channel,
506 const struct ath5k_rf_reg *rf_regs;
507 const struct ath5k_ini_rfbuffer *ini_rfb;
508 const struct ath5k_gain_opt *go = NULL;
509 const struct ath5k_gain_opt_step *g_step;
510 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
513 int i, obdb = -1, bank = -1;
515 switch (ah->ah_radio) {
517 rf_regs = rf_regs_5111;
518 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5111);
520 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5111);
521 go = &rfgain_opt_5111;
524 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) {
525 rf_regs = rf_regs_5112a;
526 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112a);
528 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5112a);
530 rf_regs = rf_regs_5112;
531 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112);
533 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5112);
535 go = &rfgain_opt_5112;
538 rf_regs = rf_regs_2413;
539 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2413);
541 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2413);
544 rf_regs = rf_regs_2316;
545 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2316);
547 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2316);
550 rf_regs = rf_regs_5413;
551 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5413);
553 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5413);
556 rf_regs = rf_regs_2425;
557 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2425);
559 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2317);
562 rf_regs = rf_regs_2425;
563 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2425);
564 if (ah->ah_mac_srev < AR5K_SREV_AR2417) {
566 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2425);
569 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2417);
576 /* If it's the first time we set rf buffer, allocate
577 * ah->ah_rf_banks based on ah->ah_rf_banks_size
579 if (ah->ah_rf_banks == NULL) {
580 ah->ah_rf_banks = kmalloc(sizeof(u32) * ah->ah_rf_banks_size,
582 if (ah->ah_rf_banks == NULL) {
583 ATH5K_ERR(ah->ah_sc, "out of memory\n");
588 /* Copy values to modify them */
589 rfb = ah->ah_rf_banks;
591 for (i = 0; i < ah->ah_rf_banks_size; i++) {
592 if (ini_rfb[i].rfb_bank >= AR5K_MAX_RF_BANKS) {
593 ATH5K_ERR(ah->ah_sc, "invalid bank\n");
597 /* Bank changed, write down the offset */
598 if (bank != ini_rfb[i].rfb_bank) {
599 bank = ini_rfb[i].rfb_bank;
600 ah->ah_offset[bank] = i;
603 rfb[i] = ini_rfb[i].rfb_mode_data[mode];
606 /* Set Output and Driver bias current (OB/DB) */
607 if (channel->hw_value & CHANNEL_2GHZ) {
609 if (channel->hw_value & CHANNEL_CCK)
610 ee_mode = AR5K_EEPROM_MODE_11B;
612 ee_mode = AR5K_EEPROM_MODE_11G;
614 /* For RF511X/RF211X combination we
615 * use b_OB and b_DB parameters stored
616 * in eeprom on ee->ee_ob[ee_mode][0]
618 * For all other chips we use OB/DB for 2Ghz
619 * stored in the b/g modal section just like
620 * 802.11a on ee->ee_ob[ee_mode][1] */
621 if ((ah->ah_radio == AR5K_RF5111) ||
622 (ah->ah_radio == AR5K_RF5112))
627 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_ob[ee_mode][obdb],
628 AR5K_RF_OB_2GHZ, true);
630 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_db[ee_mode][obdb],
631 AR5K_RF_DB_2GHZ, true);
633 /* RF5111 always needs OB/DB for 5GHz, even if we use 2GHz */
634 } else if ((channel->hw_value & CHANNEL_5GHZ) ||
635 (ah->ah_radio == AR5K_RF5111)) {
637 /* For 11a, Turbo and XR we need to choose
638 * OB/DB based on frequency range */
639 ee_mode = AR5K_EEPROM_MODE_11A;
640 obdb = channel->center_freq >= 5725 ? 3 :
641 (channel->center_freq >= 5500 ? 2 :
642 (channel->center_freq >= 5260 ? 1 :
643 (channel->center_freq > 4000 ? 0 : -1)));
648 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_ob[ee_mode][obdb],
649 AR5K_RF_OB_5GHZ, true);
651 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_db[ee_mode][obdb],
652 AR5K_RF_DB_5GHZ, true);
655 g_step = &go->go_step[ah->ah_gain.g_step_idx];
657 /* Bank Modifications (chip-specific) */
658 if (ah->ah_radio == AR5K_RF5111) {
660 /* Set gain_F settings according to current step */
661 if (channel->hw_value & CHANNEL_OFDM) {
663 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_FRAME_CTL,
664 AR5K_PHY_FRAME_CTL_TX_CLIP,
665 g_step->gos_param[0]);
667 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[1],
668 AR5K_RF_PWD_90, true);
670 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[2],
671 AR5K_RF_PWD_84, true);
673 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[3],
674 AR5K_RF_RFGAIN_SEL, true);
676 /* We programmed gain_F parameters, switch back
678 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
684 ath5k_hw_rfb_op(ah, rf_regs, !ee->ee_xpd[ee_mode],
685 AR5K_RF_PWD_XPD, true);
687 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_x_gain[ee_mode],
688 AR5K_RF_XPD_GAIN, true);
690 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_i_gain[ee_mode],
691 AR5K_RF_GAIN_I, true);
693 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_xpd[ee_mode],
694 AR5K_RF_PLO_SEL, true);
696 /* TODO: Half/quarter channel support */
699 if (ah->ah_radio == AR5K_RF5112) {
701 /* Set gain_F settings according to current step */
702 if (channel->hw_value & CHANNEL_OFDM) {
704 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[0],
705 AR5K_RF_MIXGAIN_OVR, true);
707 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[1],
708 AR5K_RF_PWD_138, true);
710 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[2],
711 AR5K_RF_PWD_137, true);
713 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[3],
714 AR5K_RF_PWD_136, true);
716 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[4],
717 AR5K_RF_PWD_132, true);
719 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[5],
720 AR5K_RF_PWD_131, true);
722 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[6],
723 AR5K_RF_PWD_130, true);
725 /* We programmed gain_F parameters, switch back
727 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
732 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_xpd[ee_mode],
733 AR5K_RF_XPD_SEL, true);
735 if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_5112A) {
736 /* Rev. 1 supports only one xpd */
737 ath5k_hw_rfb_op(ah, rf_regs,
738 ee->ee_x_gain[ee_mode],
739 AR5K_RF_XPD_GAIN, true);
742 u8 *pdg_curve_to_idx = ee->ee_pdc_to_idx[ee_mode];
743 if (ee->ee_pd_gains[ee_mode] > 1) {
744 ath5k_hw_rfb_op(ah, rf_regs,
746 AR5K_RF_PD_GAIN_LO, true);
747 ath5k_hw_rfb_op(ah, rf_regs,
749 AR5K_RF_PD_GAIN_HI, true);
751 ath5k_hw_rfb_op(ah, rf_regs,
753 AR5K_RF_PD_GAIN_LO, true);
754 ath5k_hw_rfb_op(ah, rf_regs,
756 AR5K_RF_PD_GAIN_HI, true);
759 /* Lower synth voltage on Rev 2 */
760 ath5k_hw_rfb_op(ah, rf_regs, 2,
761 AR5K_RF_HIGH_VC_CP, true);
763 ath5k_hw_rfb_op(ah, rf_regs, 2,
764 AR5K_RF_MID_VC_CP, true);
766 ath5k_hw_rfb_op(ah, rf_regs, 2,
767 AR5K_RF_LOW_VC_CP, true);
769 ath5k_hw_rfb_op(ah, rf_regs, 2,
770 AR5K_RF_PUSH_UP, true);
772 /* Decrease power consumption on 5213+ BaseBand */
773 if (ah->ah_phy_revision >= AR5K_SREV_PHY_5212A) {
774 ath5k_hw_rfb_op(ah, rf_regs, 1,
775 AR5K_RF_PAD2GND, true);
777 ath5k_hw_rfb_op(ah, rf_regs, 1,
778 AR5K_RF_XB2_LVL, true);
780 ath5k_hw_rfb_op(ah, rf_regs, 1,
781 AR5K_RF_XB5_LVL, true);
783 ath5k_hw_rfb_op(ah, rf_regs, 1,
784 AR5K_RF_PWD_167, true);
786 ath5k_hw_rfb_op(ah, rf_regs, 1,
787 AR5K_RF_PWD_166, true);
791 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_i_gain[ee_mode],
792 AR5K_RF_GAIN_I, true);
794 /* TODO: Half/quarter channel support */
798 if (ah->ah_radio == AR5K_RF5413 &&
799 channel->hw_value & CHANNEL_2GHZ) {
801 ath5k_hw_rfb_op(ah, rf_regs, 1, AR5K_RF_DERBY_CHAN_SEL_MODE,
804 /* Set optimum value for early revisions (on pci-e chips) */
805 if (ah->ah_mac_srev >= AR5K_SREV_AR5424 &&
806 ah->ah_mac_srev < AR5K_SREV_AR5413)
807 ath5k_hw_rfb_op(ah, rf_regs, ath5k_hw_bitswap(6, 3),
808 AR5K_RF_PWD_ICLOBUF_2G, true);
812 /* Write RF banks on hw */
813 for (i = 0; i < ah->ah_rf_banks_size; i++) {
815 ath5k_hw_reg_write(ah, rfb[i], ini_rfb[i].rfb_ctrl_register);
822 /**************************\
823 PHY/RF channel functions
824 \**************************/
827 * Check if a channel is supported
829 bool ath5k_channel_ok(struct ath5k_hw *ah, u16 freq, unsigned int flags)
831 /* Check if the channel is in our supported range */
832 if (flags & CHANNEL_2GHZ) {
833 if ((freq >= ah->ah_capabilities.cap_range.range_2ghz_min) &&
834 (freq <= ah->ah_capabilities.cap_range.range_2ghz_max))
836 } else if (flags & CHANNEL_5GHZ)
837 if ((freq >= ah->ah_capabilities.cap_range.range_5ghz_min) &&
838 (freq <= ah->ah_capabilities.cap_range.range_5ghz_max))
845 * Convertion needed for RF5110
847 static u32 ath5k_hw_rf5110_chan2athchan(struct ieee80211_channel *channel)
852 * Convert IEEE channel/MHz to an internal channel value used
853 * by the AR5210 chipset. This has not been verified with
854 * newer chipsets like the AR5212A who have a completely
855 * different RF/PHY part.
857 athchan = (ath5k_hw_bitswap(
858 (ieee80211_frequency_to_channel(
859 channel->center_freq) - 24) / 2, 5)
860 << 1) | (1 << 6) | 0x1;
865 * Set channel on RF5110
867 static int ath5k_hw_rf5110_channel(struct ath5k_hw *ah,
868 struct ieee80211_channel *channel)
873 * Set the channel and wait
875 data = ath5k_hw_rf5110_chan2athchan(channel);
876 ath5k_hw_reg_write(ah, data, AR5K_RF_BUFFER);
877 ath5k_hw_reg_write(ah, 0, AR5K_RF_BUFFER_CONTROL_0);
884 * Convertion needed for 5111
886 static int ath5k_hw_rf5111_chan2athchan(unsigned int ieee,
887 struct ath5k_athchan_2ghz *athchan)
891 /* Cast this value to catch negative channel numbers (>= -19) */
895 * Map 2GHz IEEE channel to 5GHz Atheros channel
898 athchan->a2_athchan = 115 + channel;
899 athchan->a2_flags = 0x46;
900 } else if (channel == 14) {
901 athchan->a2_athchan = 124;
902 athchan->a2_flags = 0x44;
903 } else if (channel >= 15 && channel <= 26) {
904 athchan->a2_athchan = ((channel - 14) * 4) + 132;
905 athchan->a2_flags = 0x46;
913 * Set channel on 5111
915 static int ath5k_hw_rf5111_channel(struct ath5k_hw *ah,
916 struct ieee80211_channel *channel)
918 struct ath5k_athchan_2ghz ath5k_channel_2ghz;
919 unsigned int ath5k_channel =
920 ieee80211_frequency_to_channel(channel->center_freq);
921 u32 data0, data1, clock;
925 * Set the channel on the RF5111 radio
929 if (channel->hw_value & CHANNEL_2GHZ) {
930 /* Map 2GHz channel to 5GHz Atheros channel ID */
931 ret = ath5k_hw_rf5111_chan2athchan(
932 ieee80211_frequency_to_channel(channel->center_freq),
933 &ath5k_channel_2ghz);
937 ath5k_channel = ath5k_channel_2ghz.a2_athchan;
938 data0 = ((ath5k_hw_bitswap(ath5k_channel_2ghz.a2_flags, 8) & 0xff)
942 if (ath5k_channel < 145 || !(ath5k_channel & 1)) {
944 data1 = ((ath5k_hw_bitswap(ath5k_channel - 24, 8) & 0xff) << 2) |
945 (clock << 1) | (1 << 10) | 1;
948 data1 = ((ath5k_hw_bitswap((ath5k_channel - 24) / 2, 8) & 0xff)
949 << 2) | (clock << 1) | (1 << 10) | 1;
952 ath5k_hw_reg_write(ah, (data1 & 0xff) | ((data0 & 0xff) << 8),
954 ath5k_hw_reg_write(ah, ((data1 >> 8) & 0xff) | (data0 & 0xff00),
955 AR5K_RF_BUFFER_CONTROL_3);
961 * Set channel on 5112 and newer
963 static int ath5k_hw_rf5112_channel(struct ath5k_hw *ah,
964 struct ieee80211_channel *channel)
966 u32 data, data0, data1, data2;
969 data = data0 = data1 = data2 = 0;
970 c = channel->center_freq;
973 if (!((c - 2224) % 5)) {
974 data0 = ((2 * (c - 704)) - 3040) / 10;
976 } else if (!((c - 2192) % 5)) {
977 data0 = ((2 * (c - 672)) - 3040) / 10;
982 data0 = ath5k_hw_bitswap((data0 << 2) & 0xff, 8);
983 } else if ((c % 5) != 2 || c > 5435) {
984 if (!(c % 20) && c >= 5120) {
985 data0 = ath5k_hw_bitswap(((c - 4800) / 20 << 2), 8);
986 data2 = ath5k_hw_bitswap(3, 2);
987 } else if (!(c % 10)) {
988 data0 = ath5k_hw_bitswap(((c - 4800) / 10 << 1), 8);
989 data2 = ath5k_hw_bitswap(2, 2);
990 } else if (!(c % 5)) {
991 data0 = ath5k_hw_bitswap((c - 4800) / 5, 8);
992 data2 = ath5k_hw_bitswap(1, 2);
996 data0 = ath5k_hw_bitswap((10 * (c - 2 - 4800)) / 25 + 1, 8);
997 data2 = ath5k_hw_bitswap(0, 2);
1000 data = (data0 << 4) | (data1 << 1) | (data2 << 2) | 0x1001;
1002 ath5k_hw_reg_write(ah, data & 0xff, AR5K_RF_BUFFER);
1003 ath5k_hw_reg_write(ah, (data >> 8) & 0x7f, AR5K_RF_BUFFER_CONTROL_5);
1009 * Set the channel on the RF2425
1011 static int ath5k_hw_rf2425_channel(struct ath5k_hw *ah,
1012 struct ieee80211_channel *channel)
1014 u32 data, data0, data2;
1017 data = data0 = data2 = 0;
1018 c = channel->center_freq;
1021 data0 = ath5k_hw_bitswap((c - 2272), 8);
1024 } else if ((c % 5) != 2 || c > 5435) {
1025 if (!(c % 20) && c < 5120)
1026 data0 = ath5k_hw_bitswap(((c - 4800) / 20 << 2), 8);
1028 data0 = ath5k_hw_bitswap(((c - 4800) / 10 << 1), 8);
1030 data0 = ath5k_hw_bitswap((c - 4800) / 5, 8);
1033 data2 = ath5k_hw_bitswap(1, 2);
1035 data0 = ath5k_hw_bitswap((10 * (c - 2 - 4800)) / 25 + 1, 8);
1036 data2 = ath5k_hw_bitswap(0, 2);
1039 data = (data0 << 4) | data2 << 2 | 0x1001;
1041 ath5k_hw_reg_write(ah, data & 0xff, AR5K_RF_BUFFER);
1042 ath5k_hw_reg_write(ah, (data >> 8) & 0x7f, AR5K_RF_BUFFER_CONTROL_5);
1048 * Set a channel on the radio chip
1050 int ath5k_hw_channel(struct ath5k_hw *ah, struct ieee80211_channel *channel)
1054 * Check bounds supported by the PHY (we don't care about regultory
1055 * restrictions at this point). Note: hw_value already has the band
1056 * (CHANNEL_2GHZ, or CHANNEL_5GHZ) so we inform ath5k_channel_ok()
1057 * of the band by that */
1058 if (!ath5k_channel_ok(ah, channel->center_freq, channel->hw_value)) {
1059 ATH5K_ERR(ah->ah_sc,
1060 "channel frequency (%u MHz) out of supported "
1062 channel->center_freq);
1067 * Set the channel and wait
1069 switch (ah->ah_radio) {
1071 ret = ath5k_hw_rf5110_channel(ah, channel);
1074 ret = ath5k_hw_rf5111_channel(ah, channel);
1077 ret = ath5k_hw_rf2425_channel(ah, channel);
1080 ret = ath5k_hw_rf5112_channel(ah, channel);
1087 /* Set JAPAN setting for channel 14 */
1088 if (channel->center_freq == 2484) {
1089 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_CCKTXCTL,
1090 AR5K_PHY_CCKTXCTL_JAPAN);
1092 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_CCKTXCTL,
1093 AR5K_PHY_CCKTXCTL_WORLD);
1096 ah->ah_current_channel = channel;
1097 ah->ah_turbo = channel->hw_value == CHANNEL_T ? true : false;
1106 static int sign_extend(int val, const int nbits)
1108 int order = BIT(nbits-1);
1109 return (val ^ order) - order;
1112 static s32 ath5k_hw_read_measured_noise_floor(struct ath5k_hw *ah)
1116 val = ath5k_hw_reg_read(ah, AR5K_PHY_NF);
1117 return sign_extend(AR5K_REG_MS(val, AR5K_PHY_NF_MINCCA_PWR), 9);
1120 void ath5k_hw_init_nfcal_hist(struct ath5k_hw *ah)
1124 ah->ah_nfcal_hist.index = 0;
1125 for (i = 0; i < ATH5K_NF_CAL_HIST_MAX; i++)
1126 ah->ah_nfcal_hist.nfval[i] = AR5K_TUNE_CCA_MAX_GOOD_VALUE;
1129 static void ath5k_hw_update_nfcal_hist(struct ath5k_hw *ah, s16 noise_floor)
1131 struct ath5k_nfcal_hist *hist = &ah->ah_nfcal_hist;
1132 hist->index = (hist->index + 1) & (ATH5K_NF_CAL_HIST_MAX-1);
1133 hist->nfval[hist->index] = noise_floor;
1136 static s16 ath5k_hw_get_median_noise_floor(struct ath5k_hw *ah)
1138 s16 sort[ATH5K_NF_CAL_HIST_MAX];
1142 memcpy(sort, ah->ah_nfcal_hist.nfval, sizeof(sort));
1143 for (i = 0; i < ATH5K_NF_CAL_HIST_MAX - 1; i++) {
1144 for (j = 1; j < ATH5K_NF_CAL_HIST_MAX - i; j++) {
1145 if (sort[j] > sort[j-1]) {
1147 sort[j] = sort[j-1];
1152 for (i = 0; i < ATH5K_NF_CAL_HIST_MAX; i++) {
1153 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
1154 "cal %d:%d\n", i, sort[i]);
1156 return sort[(ATH5K_NF_CAL_HIST_MAX-1) / 2];
1160 * When we tell the hardware to perform a noise floor calibration
1161 * by setting the AR5K_PHY_AGCCTL_NF bit, it will periodically
1162 * sample-and-hold the minimum noise level seen at the antennas.
1163 * This value is then stored in a ring buffer of recently measured
1164 * noise floor values so we have a moving window of the last few
1167 * The median of the values in the history is then loaded into the
1168 * hardware for its own use for RSSI and CCA measurements.
1170 static void ath5k_hw_update_noise_floor(struct ath5k_hw *ah)
1172 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1177 /* keep last value if calibration hasn't completed */
1178 if (ath5k_hw_reg_read(ah, AR5K_PHY_AGCCTL) & AR5K_PHY_AGCCTL_NF) {
1179 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
1180 "NF did not complete in calibration window\n");
1185 switch (ah->ah_current_channel->hw_value & CHANNEL_MODES) {
1189 ee_mode = AR5K_EEPROM_MODE_11A;
1193 ee_mode = AR5K_EEPROM_MODE_11G;
1197 ee_mode = AR5K_EEPROM_MODE_11B;
1202 /* completed NF calibration, test threshold */
1203 nf = ath5k_hw_read_measured_noise_floor(ah);
1204 threshold = ee->ee_noise_floor_thr[ee_mode];
1206 if (nf > threshold) {
1207 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
1208 "noise floor failure detected; "
1209 "read %d, threshold %d\n",
1212 nf = AR5K_TUNE_CCA_MAX_GOOD_VALUE;
1215 ath5k_hw_update_nfcal_hist(ah, nf);
1216 nf = ath5k_hw_get_median_noise_floor(ah);
1218 /* load noise floor (in .5 dBm) so the hardware will use it */
1219 val = ath5k_hw_reg_read(ah, AR5K_PHY_NF) & ~AR5K_PHY_NF_M;
1220 val |= (nf * 2) & AR5K_PHY_NF_M;
1221 ath5k_hw_reg_write(ah, val, AR5K_PHY_NF);
1223 AR5K_REG_MASKED_BITS(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_NF,
1224 ~(AR5K_PHY_AGCCTL_NF_EN | AR5K_PHY_AGCCTL_NF_NOUPDATE));
1226 ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_NF,
1230 * Load a high max CCA Power value (-50 dBm in .5 dBm units)
1231 * so that we're not capped by the median we just loaded.
1232 * This will be used as the initial value for the next noise
1233 * floor calibration.
1235 val = (val & ~AR5K_PHY_NF_M) | ((-50 * 2) & AR5K_PHY_NF_M);
1236 ath5k_hw_reg_write(ah, val, AR5K_PHY_NF);
1237 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
1238 AR5K_PHY_AGCCTL_NF_EN |
1239 AR5K_PHY_AGCCTL_NF_NOUPDATE |
1240 AR5K_PHY_AGCCTL_NF);
1242 ah->ah_noise_floor = nf;
1244 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
1245 "noise floor calibrated: %d\n", nf);
1249 * Perform a PHY calibration on RF5110
1250 * -Fix BPSK/QAM Constellation (I/Q correction)
1251 * -Calculate Noise Floor
1253 static int ath5k_hw_rf5110_calibrate(struct ath5k_hw *ah,
1254 struct ieee80211_channel *channel)
1256 u32 phy_sig, phy_agc, phy_sat, beacon;
1260 * Disable beacons and RX/TX queues, wait
1262 AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW_5210,
1263 AR5K_DIAG_SW_DIS_TX | AR5K_DIAG_SW_DIS_RX_5210);
1264 beacon = ath5k_hw_reg_read(ah, AR5K_BEACON_5210);
1265 ath5k_hw_reg_write(ah, beacon & ~AR5K_BEACON_ENABLE, AR5K_BEACON_5210);
1270 * Set the channel (with AGC turned off)
1272 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
1274 ret = ath5k_hw_channel(ah, channel);
1277 * Activate PHY and wait
1279 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT);
1282 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
1288 * Calibrate the radio chip
1291 /* Remember normal state */
1292 phy_sig = ath5k_hw_reg_read(ah, AR5K_PHY_SIG);
1293 phy_agc = ath5k_hw_reg_read(ah, AR5K_PHY_AGCCOARSE);
1294 phy_sat = ath5k_hw_reg_read(ah, AR5K_PHY_ADCSAT);
1296 /* Update radio registers */
1297 ath5k_hw_reg_write(ah, (phy_sig & ~(AR5K_PHY_SIG_FIRPWR)) |
1298 AR5K_REG_SM(-1, AR5K_PHY_SIG_FIRPWR), AR5K_PHY_SIG);
1300 ath5k_hw_reg_write(ah, (phy_agc & ~(AR5K_PHY_AGCCOARSE_HI |
1301 AR5K_PHY_AGCCOARSE_LO)) |
1302 AR5K_REG_SM(-1, AR5K_PHY_AGCCOARSE_HI) |
1303 AR5K_REG_SM(-127, AR5K_PHY_AGCCOARSE_LO), AR5K_PHY_AGCCOARSE);
1305 ath5k_hw_reg_write(ah, (phy_sat & ~(AR5K_PHY_ADCSAT_ICNT |
1306 AR5K_PHY_ADCSAT_THR)) |
1307 AR5K_REG_SM(2, AR5K_PHY_ADCSAT_ICNT) |
1308 AR5K_REG_SM(12, AR5K_PHY_ADCSAT_THR), AR5K_PHY_ADCSAT);
1312 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
1314 ath5k_hw_reg_write(ah, AR5K_PHY_RFSTG_DISABLE, AR5K_PHY_RFSTG);
1315 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
1320 * Enable calibration and wait until completion
1322 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_CAL);
1324 ret = ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL,
1325 AR5K_PHY_AGCCTL_CAL, 0, false);
1327 /* Reset to normal state */
1328 ath5k_hw_reg_write(ah, phy_sig, AR5K_PHY_SIG);
1329 ath5k_hw_reg_write(ah, phy_agc, AR5K_PHY_AGCCOARSE);
1330 ath5k_hw_reg_write(ah, phy_sat, AR5K_PHY_ADCSAT);
1333 ATH5K_ERR(ah->ah_sc, "calibration timeout (%uMHz)\n",
1334 channel->center_freq);
1338 ath5k_hw_update_noise_floor(ah);
1341 * Re-enable RX/TX and beacons
1343 AR5K_REG_DISABLE_BITS(ah, AR5K_DIAG_SW_5210,
1344 AR5K_DIAG_SW_DIS_TX | AR5K_DIAG_SW_DIS_RX_5210);
1345 ath5k_hw_reg_write(ah, beacon, AR5K_BEACON_5210);
1351 * Perform a PHY calibration on RF5111/5112 and newer chips
1353 static int ath5k_hw_rf511x_calibrate(struct ath5k_hw *ah,
1354 struct ieee80211_channel *channel)
1357 s32 iq_corr, i_coff, i_coffd, q_coff, q_coffd;
1359 ATH5K_TRACE(ah->ah_sc);
1361 if (!ah->ah_calibration ||
1362 ath5k_hw_reg_read(ah, AR5K_PHY_IQ) & AR5K_PHY_IQ_RUN)
1365 /* Calibration has finished, get the results and re-run */
1367 /* work around empty results which can apparently happen on 5212 */
1368 for (i = 0; i <= 10; i++) {
1369 iq_corr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_CORR);
1370 i_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_I);
1371 q_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_Q);
1372 ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
1373 "iq_corr:%x i_pwr:%x q_pwr:%x", iq_corr, i_pwr, q_pwr);
1378 i_coffd = ((i_pwr >> 1) + (q_pwr >> 1)) >> 7;
1380 if (ah->ah_version == AR5K_AR5211)
1381 q_coffd = q_pwr >> 6;
1383 q_coffd = q_pwr >> 7;
1385 /* protect against divide by 0 and loss of sign bits */
1386 if (i_coffd == 0 || q_coffd < 2)
1389 i_coff = (-iq_corr) / i_coffd;
1390 i_coff = clamp(i_coff, -32, 31); /* signed 6 bit */
1392 if (ah->ah_version == AR5K_AR5211)
1393 q_coff = (i_pwr / q_coffd) - 64;
1395 q_coff = (i_pwr / q_coffd) - 128;
1396 q_coff = clamp(q_coff, -16, 15); /* signed 5 bit */
1398 ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
1399 "new I:%d Q:%d (i_coffd:%x q_coffd:%x)",
1400 i_coff, q_coff, i_coffd, q_coffd);
1402 /* Commit new I/Q values (set enable bit last to match HAL sources) */
1403 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_Q_I_COFF, i_coff);
1404 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_Q_Q_COFF, q_coff);
1405 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_ENABLE);
1407 /* Re-enable calibration -if we don't we'll commit
1408 * the same values again and again */
1409 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ,
1410 AR5K_PHY_IQ_CAL_NUM_LOG_MAX, 15);
1411 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_RUN);
1415 /* TODO: Separate noise floor calibration from I/Q calibration
1416 * since noise floor calibration interrupts rx path while I/Q
1417 * calibration doesn't. We don't need to run noise floor calibration
1418 * as often as I/Q calibration.*/
1419 ath5k_hw_update_noise_floor(ah);
1421 /* Initiate a gain_F calibration */
1422 ath5k_hw_request_rfgain_probe(ah);
1428 * Perform a PHY calibration
1430 int ath5k_hw_phy_calibrate(struct ath5k_hw *ah,
1431 struct ieee80211_channel *channel)
1435 if (ah->ah_radio == AR5K_RF5110)
1436 ret = ath5k_hw_rf5110_calibrate(ah, channel);
1438 ret = ath5k_hw_rf511x_calibrate(ah, channel);
1443 /***************************\
1444 * Spur mitigation functions *
1445 \***************************/
1447 bool ath5k_hw_chan_has_spur_noise(struct ath5k_hw *ah,
1448 struct ieee80211_channel *channel)
1452 if ((ah->ah_radio == AR5K_RF5112) ||
1453 (ah->ah_radio == AR5K_RF5413) ||
1454 (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4)))
1459 if ((channel->center_freq % refclk_freq != 0) &&
1460 ((channel->center_freq % refclk_freq < 10) ||
1461 (channel->center_freq % refclk_freq > 22)))
1468 ath5k_hw_set_spur_mitigation_filter(struct ath5k_hw *ah,
1469 struct ieee80211_channel *channel)
1471 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1472 u32 mag_mask[4] = {0, 0, 0, 0};
1473 u32 pilot_mask[2] = {0, 0};
1474 /* Note: fbin values are scaled up by 2 */
1475 u16 spur_chan_fbin, chan_fbin, symbol_width, spur_detection_window;
1476 s32 spur_delta_phase, spur_freq_sigma_delta;
1477 s32 spur_offset, num_symbols_x16;
1478 u8 num_symbol_offsets, i, freq_band;
1480 /* Convert current frequency to fbin value (the same way channels
1481 * are stored on EEPROM, check out ath5k_eeprom_bin2freq) and scale
1482 * up by 2 so we can compare it later */
1483 if (channel->hw_value & CHANNEL_2GHZ) {
1484 chan_fbin = (channel->center_freq - 2300) * 10;
1485 freq_band = AR5K_EEPROM_BAND_2GHZ;
1487 chan_fbin = (channel->center_freq - 4900) * 10;
1488 freq_band = AR5K_EEPROM_BAND_5GHZ;
1491 /* Check if any spur_chan_fbin from EEPROM is
1492 * within our current channel's spur detection range */
1493 spur_chan_fbin = AR5K_EEPROM_NO_SPUR;
1494 spur_detection_window = AR5K_SPUR_CHAN_WIDTH;
1495 /* XXX: Half/Quarter channels ?*/
1496 if (channel->hw_value & CHANNEL_TURBO)
1497 spur_detection_window *= 2;
1499 for (i = 0; i < AR5K_EEPROM_N_SPUR_CHANS; i++) {
1500 spur_chan_fbin = ee->ee_spur_chans[i][freq_band];
1502 /* Note: mask cleans AR5K_EEPROM_NO_SPUR flag
1503 * so it's zero if we got nothing from EEPROM */
1504 if (spur_chan_fbin == AR5K_EEPROM_NO_SPUR) {
1505 spur_chan_fbin &= AR5K_EEPROM_SPUR_CHAN_MASK;
1509 if ((chan_fbin - spur_detection_window <=
1510 (spur_chan_fbin & AR5K_EEPROM_SPUR_CHAN_MASK)) &&
1511 (chan_fbin + spur_detection_window >=
1512 (spur_chan_fbin & AR5K_EEPROM_SPUR_CHAN_MASK))) {
1513 spur_chan_fbin &= AR5K_EEPROM_SPUR_CHAN_MASK;
1518 /* We need to enable spur filter for this channel */
1519 if (spur_chan_fbin) {
1520 spur_offset = spur_chan_fbin - chan_fbin;
1523 * spur_freq_sigma_delta -> spur_offset / sample_freq << 21
1524 * spur_delta_phase -> spur_offset / chip_freq << 11
1525 * Note: Both values have 100KHz resolution
1527 /* XXX: Half/Quarter rate channels ? */
1528 switch (channel->hw_value) {
1530 /* Both sample_freq and chip_freq are 40MHz */
1531 spur_delta_phase = (spur_offset << 17) / 25;
1532 spur_freq_sigma_delta = (spur_delta_phase >> 10);
1533 symbol_width = AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz;
1536 /* sample_freq -> 40MHz chip_freq -> 44MHz
1537 * (for b compatibility) */
1538 spur_freq_sigma_delta = (spur_offset << 8) / 55;
1539 spur_delta_phase = (spur_offset << 17) / 25;
1540 symbol_width = AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz;
1544 /* Both sample_freq and chip_freq are 80MHz */
1545 spur_delta_phase = (spur_offset << 16) / 25;
1546 spur_freq_sigma_delta = (spur_delta_phase >> 10);
1547 symbol_width = AR5K_SPUR_SYMBOL_WIDTH_TURBO_100Hz;
1553 /* Calculate pilot and magnitude masks */
1555 /* Scale up spur_offset by 1000 to switch to 100HZ resolution
1556 * and divide by symbol_width to find how many symbols we have
1557 * Note: number of symbols is scaled up by 16 */
1558 num_symbols_x16 = ((spur_offset * 1000) << 4) / symbol_width;
1560 /* Spur is on a symbol if num_symbols_x16 % 16 is zero */
1561 if (!(num_symbols_x16 & 0xF))
1563 num_symbol_offsets = 3;
1566 num_symbol_offsets = 4;
1568 for (i = 0; i < num_symbol_offsets; i++) {
1570 /* Calculate pilot mask */
1572 (num_symbols_x16 / 16) + i + 25;
1574 /* Pilot magnitude mask seems to be a way to
1575 * declare the boundaries for our detection
1576 * window or something, it's 2 for the middle
1577 * value(s) where the symbol is expected to be
1578 * and 1 on the boundary values */
1580 (i == 0 || i == (num_symbol_offsets - 1))
1583 if (curr_sym_off >= 0 && curr_sym_off <= 32) {
1584 if (curr_sym_off <= 25)
1585 pilot_mask[0] |= 1 << curr_sym_off;
1586 else if (curr_sym_off >= 27)
1587 pilot_mask[0] |= 1 << (curr_sym_off - 1);
1588 } else if (curr_sym_off >= 33 && curr_sym_off <= 52)
1589 pilot_mask[1] |= 1 << (curr_sym_off - 33);
1591 /* Calculate magnitude mask (for viterbi decoder) */
1592 if (curr_sym_off >= -1 && curr_sym_off <= 14)
1594 plt_mag_map << (curr_sym_off + 1) * 2;
1595 else if (curr_sym_off >= 15 && curr_sym_off <= 30)
1597 plt_mag_map << (curr_sym_off - 15) * 2;
1598 else if (curr_sym_off >= 31 && curr_sym_off <= 46)
1600 plt_mag_map << (curr_sym_off - 31) * 2;
1601 else if (curr_sym_off >= 46 && curr_sym_off <= 53)
1603 plt_mag_map << (curr_sym_off - 47) * 2;
1607 /* Write settings on hw to enable spur filter */
1608 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL,
1609 AR5K_PHY_BIN_MASK_CTL_RATE, 0xff);
1610 /* XXX: Self correlator also ? */
1611 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ,
1612 AR5K_PHY_IQ_PILOT_MASK_EN |
1613 AR5K_PHY_IQ_CHAN_MASK_EN |
1614 AR5K_PHY_IQ_SPUR_FILT_EN);
1616 /* Set delta phase and freq sigma delta */
1617 ath5k_hw_reg_write(ah,
1618 AR5K_REG_SM(spur_delta_phase,
1619 AR5K_PHY_TIMING_11_SPUR_DELTA_PHASE) |
1620 AR5K_REG_SM(spur_freq_sigma_delta,
1621 AR5K_PHY_TIMING_11_SPUR_FREQ_SD) |
1622 AR5K_PHY_TIMING_11_USE_SPUR_IN_AGC,
1623 AR5K_PHY_TIMING_11);
1625 /* Write pilot masks */
1626 ath5k_hw_reg_write(ah, pilot_mask[0], AR5K_PHY_TIMING_7);
1627 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_8,
1628 AR5K_PHY_TIMING_8_PILOT_MASK_2,
1631 ath5k_hw_reg_write(ah, pilot_mask[0], AR5K_PHY_TIMING_9);
1632 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_10,
1633 AR5K_PHY_TIMING_10_PILOT_MASK_2,
1636 /* Write magnitude masks */
1637 ath5k_hw_reg_write(ah, mag_mask[0], AR5K_PHY_BIN_MASK_1);
1638 ath5k_hw_reg_write(ah, mag_mask[1], AR5K_PHY_BIN_MASK_2);
1639 ath5k_hw_reg_write(ah, mag_mask[2], AR5K_PHY_BIN_MASK_3);
1640 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL,
1641 AR5K_PHY_BIN_MASK_CTL_MASK_4,
1644 ath5k_hw_reg_write(ah, mag_mask[0], AR5K_PHY_BIN_MASK2_1);
1645 ath5k_hw_reg_write(ah, mag_mask[1], AR5K_PHY_BIN_MASK2_2);
1646 ath5k_hw_reg_write(ah, mag_mask[2], AR5K_PHY_BIN_MASK2_3);
1647 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK2_4,
1648 AR5K_PHY_BIN_MASK2_4_MASK_4,
1651 } else if (ath5k_hw_reg_read(ah, AR5K_PHY_IQ) &
1652 AR5K_PHY_IQ_SPUR_FILT_EN) {
1653 /* Clean up spur mitigation settings and disable fliter */
1654 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL,
1655 AR5K_PHY_BIN_MASK_CTL_RATE, 0);
1656 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_IQ,
1657 AR5K_PHY_IQ_PILOT_MASK_EN |
1658 AR5K_PHY_IQ_CHAN_MASK_EN |
1659 AR5K_PHY_IQ_SPUR_FILT_EN);
1660 ath5k_hw_reg_write(ah, 0, AR5K_PHY_TIMING_11);
1662 /* Clear pilot masks */
1663 ath5k_hw_reg_write(ah, 0, AR5K_PHY_TIMING_7);
1664 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_8,
1665 AR5K_PHY_TIMING_8_PILOT_MASK_2,
1668 ath5k_hw_reg_write(ah, 0, AR5K_PHY_TIMING_9);
1669 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_10,
1670 AR5K_PHY_TIMING_10_PILOT_MASK_2,
1673 /* Clear magnitude masks */
1674 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK_1);
1675 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK_2);
1676 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK_3);
1677 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL,
1678 AR5K_PHY_BIN_MASK_CTL_MASK_4,
1681 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK2_1);
1682 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK2_2);
1683 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK2_3);
1684 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK2_4,
1685 AR5K_PHY_BIN_MASK2_4_MASK_4,
1690 /********************\
1692 \********************/
1694 int ath5k_hw_phy_disable(struct ath5k_hw *ah)
1696 ATH5K_TRACE(ah->ah_sc);
1698 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT);
1704 * Get the PHY Chip revision
1706 u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, unsigned int chan)
1712 ATH5K_TRACE(ah->ah_sc);
1715 * Set the radio chip access register
1719 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_2GHZ, AR5K_PHY(0));
1722 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0));
1730 /* ...wait until PHY is ready and read the selected radio revision */
1731 ath5k_hw_reg_write(ah, 0x00001c16, AR5K_PHY(0x34));
1733 for (i = 0; i < 8; i++)
1734 ath5k_hw_reg_write(ah, 0x00010000, AR5K_PHY(0x20));
1736 if (ah->ah_version == AR5K_AR5210) {
1737 srev = ath5k_hw_reg_read(ah, AR5K_PHY(256) >> 28) & 0xf;
1738 ret = (u16)ath5k_hw_bitswap(srev, 4) + 1;
1740 srev = (ath5k_hw_reg_read(ah, AR5K_PHY(0x100)) >> 24) & 0xff;
1741 ret = (u16)ath5k_hw_bitswap(((srev & 0xf0) >> 4) |
1742 ((srev & 0x0f) << 4), 8);
1745 /* Reset to the 5GHz mode */
1746 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0));
1755 static void /*TODO:Boundary check*/
1756 ath5k_hw_set_def_antenna(struct ath5k_hw *ah, u8 ant)
1758 ATH5K_TRACE(ah->ah_sc);
1760 if (ah->ah_version != AR5K_AR5210)
1761 ath5k_hw_reg_write(ah, ant & 0x7, AR5K_DEFAULT_ANTENNA);
1765 * Enable/disable fast rx antenna diversity
1768 ath5k_hw_set_fast_div(struct ath5k_hw *ah, u8 ee_mode, bool enable)
1771 case AR5K_EEPROM_MODE_11G:
1772 /* XXX: This is set to
1773 * disabled on initvals !!! */
1774 case AR5K_EEPROM_MODE_11A:
1776 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGCCTL,
1777 AR5K_PHY_AGCCTL_OFDM_DIV_DIS);
1779 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
1780 AR5K_PHY_AGCCTL_OFDM_DIV_DIS);
1782 case AR5K_EEPROM_MODE_11B:
1783 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
1784 AR5K_PHY_AGCCTL_OFDM_DIV_DIS);
1791 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RESTART,
1792 AR5K_PHY_RESTART_DIV_GC, 0xc);
1794 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_FAST_ANT_DIV,
1795 AR5K_PHY_FAST_ANT_DIV_EN);
1797 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RESTART,
1798 AR5K_PHY_RESTART_DIV_GC, 0x8);
1800 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_FAST_ANT_DIV,
1801 AR5K_PHY_FAST_ANT_DIV_EN);
1806 * Set antenna operating mode
1809 ath5k_hw_set_antenna_mode(struct ath5k_hw *ah, u8 ant_mode)
1811 struct ieee80211_channel *channel = ah->ah_current_channel;
1812 bool use_def_for_tx, update_def_on_tx, use_def_for_rts, fast_div;
1813 bool use_def_for_sg;
1814 u8 def_ant, tx_ant, ee_mode;
1817 def_ant = ah->ah_def_ant;
1819 ATH5K_TRACE(ah->ah_sc);
1821 switch (channel->hw_value & CHANNEL_MODES) {
1825 ee_mode = AR5K_EEPROM_MODE_11A;
1829 ee_mode = AR5K_EEPROM_MODE_11G;
1832 ee_mode = AR5K_EEPROM_MODE_11B;
1835 ATH5K_ERR(ah->ah_sc,
1836 "invalid channel: %d\n", channel->center_freq);
1841 case AR5K_ANTMODE_DEFAULT:
1843 use_def_for_tx = false;
1844 update_def_on_tx = false;
1845 use_def_for_rts = false;
1846 use_def_for_sg = false;
1849 case AR5K_ANTMODE_FIXED_A:
1852 use_def_for_tx = true;
1853 update_def_on_tx = false;
1854 use_def_for_rts = true;
1855 use_def_for_sg = true;
1858 case AR5K_ANTMODE_FIXED_B:
1861 use_def_for_tx = true;
1862 update_def_on_tx = false;
1863 use_def_for_rts = true;
1864 use_def_for_sg = true;
1867 case AR5K_ANTMODE_SINGLE_AP:
1868 def_ant = 1; /* updated on tx */
1870 use_def_for_tx = true;
1871 update_def_on_tx = true;
1872 use_def_for_rts = true;
1873 use_def_for_sg = true;
1876 case AR5K_ANTMODE_SECTOR_AP:
1877 tx_ant = 1; /* variable */
1878 use_def_for_tx = false;
1879 update_def_on_tx = false;
1880 use_def_for_rts = true;
1881 use_def_for_sg = false;
1884 case AR5K_ANTMODE_SECTOR_STA:
1885 tx_ant = 1; /* variable */
1886 use_def_for_tx = true;
1887 update_def_on_tx = false;
1888 use_def_for_rts = true;
1889 use_def_for_sg = false;
1892 case AR5K_ANTMODE_DEBUG:
1895 use_def_for_tx = false;
1896 update_def_on_tx = false;
1897 use_def_for_rts = false;
1898 use_def_for_sg = false;
1905 ah->ah_tx_ant = tx_ant;
1906 ah->ah_ant_mode = ant_mode;
1907 ah->ah_def_ant = def_ant;
1909 sta_id1 |= use_def_for_tx ? AR5K_STA_ID1_DEFAULT_ANTENNA : 0;
1910 sta_id1 |= update_def_on_tx ? AR5K_STA_ID1_DESC_ANTENNA : 0;
1911 sta_id1 |= use_def_for_rts ? AR5K_STA_ID1_RTS_DEF_ANTENNA : 0;
1912 sta_id1 |= use_def_for_sg ? AR5K_STA_ID1_SELFGEN_DEF_ANT : 0;
1914 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, AR5K_STA_ID1_ANTENNA_SETTINGS);
1917 AR5K_REG_ENABLE_BITS(ah, AR5K_STA_ID1, sta_id1);
1919 /* Note: set diversity before default antenna
1920 * because it won't work correctly */
1921 ath5k_hw_set_fast_div(ah, ee_mode, fast_div);
1922 ath5k_hw_set_def_antenna(ah, def_ant);
1935 * Do linear interpolation between two given (x, y) points
1938 ath5k_get_interpolated_value(s16 target, s16 x_left, s16 x_right,
1939 s16 y_left, s16 y_right)
1943 /* Avoid divide by zero and skip interpolation
1944 * if we have the same point */
1945 if ((x_left == x_right) || (y_left == y_right))
1949 * Since we use ints and not fps, we need to scale up in
1950 * order to get a sane ratio value (or else we 'll eg. get
1951 * always 1 instead of 1.25, 1.75 etc). We scale up by 100
1952 * to have some accuracy both for 0.5 and 0.25 steps.
1954 ratio = ((100 * y_right - 100 * y_left)/(x_right - x_left));
1956 /* Now scale down to be in range */
1957 result = y_left + (ratio * (target - x_left) / 100);
1963 * Find vertical boundary (min pwr) for the linear PCDAC curve.
1965 * Since we have the top of the curve and we draw the line below
1966 * until we reach 1 (1 pcdac step) we need to know which point
1967 * (x value) that is so that we don't go below y axis and have negative
1968 * pcdac values when creating the curve, or fill the table with zeroes.
1971 ath5k_get_linear_pcdac_min(const u8 *stepL, const u8 *stepR,
1972 const s16 *pwrL, const s16 *pwrR)
1975 s16 min_pwrL, min_pwrR;
1978 /* Some vendors write the same pcdac value twice !!! */
1979 if (stepL[0] == stepL[1] || stepR[0] == stepR[1])
1980 return max(pwrL[0], pwrR[0]);
1982 if (pwrL[0] == pwrL[1])
1988 tmp = (s8) ath5k_get_interpolated_value(pwr_i,
1990 stepL[0], stepL[1]);
1996 if (pwrR[0] == pwrR[1])
2002 tmp = (s8) ath5k_get_interpolated_value(pwr_i,
2004 stepR[0], stepR[1]);
2010 /* Keep the right boundary so that it works for both curves */
2011 return max(min_pwrL, min_pwrR);
2015 * Interpolate (pwr,vpd) points to create a Power to PDADC or a
2016 * Power to PCDAC curve.
2018 * Each curve has power on x axis (in 0.5dB units) and PCDAC/PDADC
2019 * steps (offsets) on y axis. Power can go up to 31.5dB and max
2020 * PCDAC/PDADC step for each curve is 64 but we can write more than
2021 * one curves on hw so we can go up to 128 (which is the max step we
2022 * can write on the final table).
2024 * We write y values (PCDAC/PDADC steps) on hw.
2027 ath5k_create_power_curve(s16 pmin, s16 pmax,
2028 const s16 *pwr, const u8 *vpd,
2030 u8 *vpd_table, u8 type)
2032 u8 idx[2] = { 0, 1 };
2039 /* We want the whole line, so adjust boundaries
2040 * to cover the entire power range. Note that
2041 * power values are already 0.25dB so no need
2042 * to multiply pwr_i by 2 */
2043 if (type == AR5K_PWRTABLE_LINEAR_PCDAC) {
2049 /* Find surrounding turning points (TPs)
2050 * and interpolate between them */
2051 for (i = 0; (i <= (u16) (pmax - pmin)) &&
2052 (i < AR5K_EEPROM_POWER_TABLE_SIZE); i++) {
2054 /* We passed the right TP, move to the next set of TPs
2055 * if we pass the last TP, extrapolate above using the last
2056 * two TPs for ratio */
2057 if ((pwr_i > pwr[idx[1]]) && (idx[1] < num_points - 1)) {
2062 vpd_table[i] = (u8) ath5k_get_interpolated_value(pwr_i,
2063 pwr[idx[0]], pwr[idx[1]],
2064 vpd[idx[0]], vpd[idx[1]]);
2066 /* Increase by 0.5dB
2067 * (0.25 dB units) */
2073 * Get the surrounding per-channel power calibration piers
2074 * for a given frequency so that we can interpolate between
2075 * them and come up with an apropriate dataset for our current
2079 ath5k_get_chan_pcal_surrounding_piers(struct ath5k_hw *ah,
2080 struct ieee80211_channel *channel,
2081 struct ath5k_chan_pcal_info **pcinfo_l,
2082 struct ath5k_chan_pcal_info **pcinfo_r)
2084 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
2085 struct ath5k_chan_pcal_info *pcinfo;
2088 u32 target = channel->center_freq;
2093 if (!(channel->hw_value & CHANNEL_OFDM)) {
2094 pcinfo = ee->ee_pwr_cal_b;
2095 mode = AR5K_EEPROM_MODE_11B;
2096 } else if (channel->hw_value & CHANNEL_2GHZ) {
2097 pcinfo = ee->ee_pwr_cal_g;
2098 mode = AR5K_EEPROM_MODE_11G;
2100 pcinfo = ee->ee_pwr_cal_a;
2101 mode = AR5K_EEPROM_MODE_11A;
2103 max = ee->ee_n_piers[mode] - 1;
2105 /* Frequency is below our calibrated
2106 * range. Use the lowest power curve
2108 if (target < pcinfo[0].freq) {
2113 /* Frequency is above our calibrated
2114 * range. Use the highest power curve
2116 if (target > pcinfo[max].freq) {
2117 idx_l = idx_r = max;
2121 /* Frequency is inside our calibrated
2122 * channel range. Pick the surrounding
2123 * calibration piers so that we can
2125 for (i = 0; i <= max; i++) {
2127 /* Frequency matches one of our calibration
2128 * piers, no need to interpolate, just use
2129 * that calibration pier */
2130 if (pcinfo[i].freq == target) {
2135 /* We found a calibration pier that's above
2136 * frequency, use this pier and the previous
2137 * one to interpolate */
2138 if (target < pcinfo[i].freq) {
2146 *pcinfo_l = &pcinfo[idx_l];
2147 *pcinfo_r = &pcinfo[idx_r];
2153 * Get the surrounding per-rate power calibration data
2154 * for a given frequency and interpolate between power
2155 * values to set max target power supported by hw for
2159 ath5k_get_rate_pcal_data(struct ath5k_hw *ah,
2160 struct ieee80211_channel *channel,
2161 struct ath5k_rate_pcal_info *rates)
2163 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
2164 struct ath5k_rate_pcal_info *rpinfo;
2167 u32 target = channel->center_freq;
2172 if (!(channel->hw_value & CHANNEL_OFDM)) {
2173 rpinfo = ee->ee_rate_tpwr_b;
2174 mode = AR5K_EEPROM_MODE_11B;
2175 } else if (channel->hw_value & CHANNEL_2GHZ) {
2176 rpinfo = ee->ee_rate_tpwr_g;
2177 mode = AR5K_EEPROM_MODE_11G;
2179 rpinfo = ee->ee_rate_tpwr_a;
2180 mode = AR5K_EEPROM_MODE_11A;
2182 max = ee->ee_rate_target_pwr_num[mode] - 1;
2184 /* Get the surrounding calibration
2185 * piers - same as above */
2186 if (target < rpinfo[0].freq) {
2191 if (target > rpinfo[max].freq) {
2192 idx_l = idx_r = max;
2196 for (i = 0; i <= max; i++) {
2198 if (rpinfo[i].freq == target) {
2203 if (target < rpinfo[i].freq) {
2211 /* Now interpolate power value, based on the frequency */
2212 rates->freq = target;
2214 rates->target_power_6to24 =
2215 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq,
2217 rpinfo[idx_l].target_power_6to24,
2218 rpinfo[idx_r].target_power_6to24);
2220 rates->target_power_36 =
2221 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq,
2223 rpinfo[idx_l].target_power_36,
2224 rpinfo[idx_r].target_power_36);
2226 rates->target_power_48 =
2227 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq,
2229 rpinfo[idx_l].target_power_48,
2230 rpinfo[idx_r].target_power_48);
2232 rates->target_power_54 =
2233 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq,
2235 rpinfo[idx_l].target_power_54,
2236 rpinfo[idx_r].target_power_54);
2240 * Get the max edge power for this channel if
2241 * we have such data from EEPROM's Conformance Test
2242 * Limits (CTL), and limit max power if needed.
2245 ath5k_get_max_ctl_power(struct ath5k_hw *ah,
2246 struct ieee80211_channel *channel)
2248 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah);
2249 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
2250 struct ath5k_edge_power *rep = ee->ee_ctl_pwr;
2251 u8 *ctl_val = ee->ee_ctl;
2252 s16 max_chan_pwr = ah->ah_txpower.txp_max_pwr / 4;
2257 u32 target = channel->center_freq;
2259 ctl_mode = ath_regd_get_band_ctl(regulatory, channel->band);
2261 switch (channel->hw_value & CHANNEL_MODES) {
2263 ctl_mode |= AR5K_CTL_11A;
2266 ctl_mode |= AR5K_CTL_11G;
2269 ctl_mode |= AR5K_CTL_11B;
2272 ctl_mode |= AR5K_CTL_TURBO;
2275 ctl_mode |= AR5K_CTL_TURBOG;
2283 for (i = 0; i < ee->ee_ctls; i++) {
2284 if (ctl_val[i] == ctl_mode) {
2290 /* If we have a CTL dataset available grab it and find the
2291 * edge power for our frequency */
2292 if (ctl_idx == 0xFF)
2295 /* Edge powers are sorted by frequency from lower
2296 * to higher. Each CTL corresponds to 8 edge power
2298 rep_idx = ctl_idx * AR5K_EEPROM_N_EDGES;
2300 /* Don't do boundaries check because we
2301 * might have more that one bands defined
2304 /* Get the edge power that's closer to our
2306 for (i = 0; i < AR5K_EEPROM_N_EDGES; i++) {
2308 if (target <= rep[rep_idx].freq)
2309 edge_pwr = (s16) rep[rep_idx].edge;
2313 ah->ah_txpower.txp_max_pwr = 4*min(edge_pwr, max_chan_pwr);
2318 * Power to PCDAC table functions
2322 * Fill Power to PCDAC table on RF5111
2324 * No further processing is needed for RF5111, the only thing we have to
2325 * do is fill the values below and above calibration range since eeprom data
2326 * may not cover the entire PCDAC table.
2329 ath5k_fill_pwr_to_pcdac_table(struct ath5k_hw *ah, s16* table_min,
2332 u8 *pcdac_out = ah->ah_txpower.txp_pd_table;
2333 u8 *pcdac_tmp = ah->ah_txpower.tmpL[0];
2334 u8 pcdac_0, pcdac_n, pcdac_i, pwr_idx, i;
2335 s16 min_pwr, max_pwr;
2337 /* Get table boundaries */
2338 min_pwr = table_min[0];
2339 pcdac_0 = pcdac_tmp[0];
2341 max_pwr = table_max[0];
2342 pcdac_n = pcdac_tmp[table_max[0] - table_min[0]];
2344 /* Extrapolate below minimum using pcdac_0 */
2346 for (i = 0; i < min_pwr; i++)
2347 pcdac_out[pcdac_i++] = pcdac_0;
2349 /* Copy values from pcdac_tmp */
2351 for (i = 0 ; pwr_idx <= max_pwr &&
2352 pcdac_i < AR5K_EEPROM_POWER_TABLE_SIZE; i++) {
2353 pcdac_out[pcdac_i++] = pcdac_tmp[i];
2357 /* Extrapolate above maximum */
2358 while (pcdac_i < AR5K_EEPROM_POWER_TABLE_SIZE)
2359 pcdac_out[pcdac_i++] = pcdac_n;
2364 * Combine available XPD Curves and fill Linear Power to PCDAC table
2367 * RFX112 can have up to 2 curves (one for low txpower range and one for
2368 * higher txpower range). We need to put them both on pcdac_out and place
2369 * them in the correct location. In case we only have one curve available
2370 * just fit it on pcdac_out (it's supposed to cover the entire range of
2371 * available pwr levels since it's always the higher power curve). Extrapolate
2372 * below and above final table if needed.
2375 ath5k_combine_linear_pcdac_curves(struct ath5k_hw *ah, s16* table_min,
2376 s16 *table_max, u8 pdcurves)
2378 u8 *pcdac_out = ah->ah_txpower.txp_pd_table;
2385 s16 mid_pwr_idx = 0;
2386 /* Edge flag turs on the 7nth bit on the PCDAC
2387 * to delcare the higher power curve (force values
2388 * to be greater than 64). If we only have one curve
2389 * we don't need to set this, if we have 2 curves and
2390 * fill the table backwards this can also be used to
2391 * switch from higher power curve to lower power curve */
2395 /* When we have only one curve available
2396 * that's the higher power curve. If we have
2397 * two curves the first is the high power curve
2398 * and the next is the low power curve. */
2400 pcdac_low_pwr = ah->ah_txpower.tmpL[1];
2401 pcdac_high_pwr = ah->ah_txpower.tmpL[0];
2402 mid_pwr_idx = table_max[1] - table_min[1] - 1;
2403 max_pwr_idx = (table_max[0] - table_min[0]) / 2;
2405 /* If table size goes beyond 31.5dB, keep the
2406 * upper 31.5dB range when setting tx power.
2407 * Note: 126 = 31.5 dB in quarter dB steps */
2408 if (table_max[0] - table_min[1] > 126)
2409 min_pwr_idx = table_max[0] - 126;
2411 min_pwr_idx = table_min[1];
2413 /* Since we fill table backwards
2414 * start from high power curve */
2415 pcdac_tmp = pcdac_high_pwr;
2419 pcdac_low_pwr = ah->ah_txpower.tmpL[1]; /* Zeroed */
2420 pcdac_high_pwr = ah->ah_txpower.tmpL[0];
2421 min_pwr_idx = table_min[0];
2422 max_pwr_idx = (table_max[0] - table_min[0]) / 2;
2423 pcdac_tmp = pcdac_high_pwr;
2427 /* This is used when setting tx power*/
2428 ah->ah_txpower.txp_min_idx = min_pwr_idx/2;
2430 /* Fill Power to PCDAC table backwards */
2432 for (i = 63; i >= 0; i--) {
2433 /* Entering lower power range, reset
2434 * edge flag and set pcdac_tmp to lower
2436 if (edge_flag == 0x40 &&
2437 (2*pwr <= (table_max[1] - table_min[0]) || pwr == 0)) {
2439 pcdac_tmp = pcdac_low_pwr;
2440 pwr = mid_pwr_idx/2;
2443 /* Don't go below 1, extrapolate below if we have
2444 * already swithced to the lower power curve -or
2445 * we only have one curve and edge_flag is zero
2447 if (pcdac_tmp[pwr] < 1 && (edge_flag == 0x00)) {
2449 pcdac_out[i] = pcdac_out[i + 1];
2455 pcdac_out[i] = pcdac_tmp[pwr] | edge_flag;
2457 /* Extrapolate above if pcdac is greater than
2458 * 126 -this can happen because we OR pcdac_out
2459 * value with edge_flag on high power curve */
2460 if (pcdac_out[i] > 126)
2463 /* Decrease by a 0.5dB step */
2468 /* Write PCDAC values on hw */
2470 ath5k_setup_pcdac_table(struct ath5k_hw *ah)
2472 u8 *pcdac_out = ah->ah_txpower.txp_pd_table;
2476 * Write TX power values
2478 for (i = 0; i < (AR5K_EEPROM_POWER_TABLE_SIZE / 2); i++) {
2479 ath5k_hw_reg_write(ah,
2480 (((pcdac_out[2*i + 0] << 8 | 0xff) & 0xffff) << 0) |
2481 (((pcdac_out[2*i + 1] << 8 | 0xff) & 0xffff) << 16),
2482 AR5K_PHY_PCDAC_TXPOWER(i));
2488 * Power to PDADC table functions
2492 * Set the gain boundaries and create final Power to PDADC table
2494 * We can have up to 4 pd curves, we need to do a simmilar process
2495 * as we do for RF5112. This time we don't have an edge_flag but we
2496 * set the gain boundaries on a separate register.
2499 ath5k_combine_pwr_to_pdadc_curves(struct ath5k_hw *ah,
2500 s16 *pwr_min, s16 *pwr_max, u8 pdcurves)
2502 u8 gain_boundaries[AR5K_EEPROM_N_PD_GAINS];
2503 u8 *pdadc_out = ah->ah_txpower.txp_pd_table;
2506 u8 pdadc_i, pdadc_n, pwr_step, pdg, max_idx, table_size;
2509 /* Note: Register value is initialized on initvals
2510 * there is no feedback from hw.
2511 * XXX: What about pd_gain_overlap from EEPROM ? */
2512 pd_gain_overlap = (u8) ath5k_hw_reg_read(ah, AR5K_PHY_TPC_RG5) &
2513 AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAP;
2515 /* Create final PDADC table */
2516 for (pdg = 0, pdadc_i = 0; pdg < pdcurves; pdg++) {
2517 pdadc_tmp = ah->ah_txpower.tmpL[pdg];
2519 if (pdg == pdcurves - 1)
2520 /* 2 dB boundary stretch for last
2521 * (higher power) curve */
2522 gain_boundaries[pdg] = pwr_max[pdg] + 4;
2524 /* Set gain boundary in the middle
2525 * between this curve and the next one */
2526 gain_boundaries[pdg] =
2527 (pwr_max[pdg] + pwr_min[pdg + 1]) / 2;
2529 /* Sanity check in case our 2 db stretch got out of
2531 if (gain_boundaries[pdg] > AR5K_TUNE_MAX_TXPOWER)
2532 gain_boundaries[pdg] = AR5K_TUNE_MAX_TXPOWER;
2534 /* For the first curve (lower power)
2535 * start from 0 dB */
2539 /* For the other curves use the gain overlap */
2540 pdadc_0 = (gain_boundaries[pdg - 1] - pwr_min[pdg]) -
2543 /* Force each power step to be at least 0.5 dB */
2544 if ((pdadc_tmp[1] - pdadc_tmp[0]) > 1)
2545 pwr_step = pdadc_tmp[1] - pdadc_tmp[0];
2549 /* If pdadc_0 is negative, we need to extrapolate
2550 * below this pdgain by a number of pwr_steps */
2551 while ((pdadc_0 < 0) && (pdadc_i < 128)) {
2552 s16 tmp = pdadc_tmp[0] + pdadc_0 * pwr_step;
2553 pdadc_out[pdadc_i++] = (tmp < 0) ? 0 : (u8) tmp;
2557 /* Set last pwr level, using gain boundaries */
2558 pdadc_n = gain_boundaries[pdg] + pd_gain_overlap - pwr_min[pdg];
2559 /* Limit it to be inside pwr range */
2560 table_size = pwr_max[pdg] - pwr_min[pdg];
2561 max_idx = (pdadc_n < table_size) ? pdadc_n : table_size;
2563 /* Fill pdadc_out table */
2564 while (pdadc_0 < max_idx && pdadc_i < 128)
2565 pdadc_out[pdadc_i++] = pdadc_tmp[pdadc_0++];
2567 /* Need to extrapolate above this pdgain? */
2568 if (pdadc_n <= max_idx)
2571 /* Force each power step to be at least 0.5 dB */
2572 if ((pdadc_tmp[table_size - 1] - pdadc_tmp[table_size - 2]) > 1)
2573 pwr_step = pdadc_tmp[table_size - 1] -
2574 pdadc_tmp[table_size - 2];
2578 /* Extrapolate above */
2579 while ((pdadc_0 < (s16) pdadc_n) &&
2580 (pdadc_i < AR5K_EEPROM_POWER_TABLE_SIZE * 2)) {
2581 s16 tmp = pdadc_tmp[table_size - 1] +
2582 (pdadc_0 - max_idx) * pwr_step;
2583 pdadc_out[pdadc_i++] = (tmp > 127) ? 127 : (u8) tmp;
2588 while (pdg < AR5K_EEPROM_N_PD_GAINS) {
2589 gain_boundaries[pdg] = gain_boundaries[pdg - 1];
2593 while (pdadc_i < AR5K_EEPROM_POWER_TABLE_SIZE * 2) {
2594 pdadc_out[pdadc_i] = pdadc_out[pdadc_i - 1];
2598 /* Set gain boundaries */
2599 ath5k_hw_reg_write(ah,
2600 AR5K_REG_SM(pd_gain_overlap,
2601 AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAP) |
2602 AR5K_REG_SM(gain_boundaries[0],
2603 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_1) |
2604 AR5K_REG_SM(gain_boundaries[1],
2605 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_2) |
2606 AR5K_REG_SM(gain_boundaries[2],
2607 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_3) |
2608 AR5K_REG_SM(gain_boundaries[3],
2609 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_4),
2612 /* Used for setting rate power table */
2613 ah->ah_txpower.txp_min_idx = pwr_min[0];
2617 /* Write PDADC values on hw */
2619 ath5k_setup_pwr_to_pdadc_table(struct ath5k_hw *ah,
2620 u8 pdcurves, u8 *pdg_to_idx)
2622 u8 *pdadc_out = ah->ah_txpower.txp_pd_table;
2626 /* Select the right pdgain curves */
2628 /* Clear current settings */
2629 reg = ath5k_hw_reg_read(ah, AR5K_PHY_TPC_RG1);
2630 reg &= ~(AR5K_PHY_TPC_RG1_PDGAIN_1 |
2631 AR5K_PHY_TPC_RG1_PDGAIN_2 |
2632 AR5K_PHY_TPC_RG1_PDGAIN_3 |
2633 AR5K_PHY_TPC_RG1_NUM_PD_GAIN);
2636 * Use pd_gains curve from eeprom
2638 * This overrides the default setting from initvals
2639 * in case some vendors (e.g. Zcomax) don't use the default
2640 * curves. If we don't honor their settings we 'll get a
2641 * 5dB (1 * gain overlap ?) drop.
2643 reg |= AR5K_REG_SM(pdcurves, AR5K_PHY_TPC_RG1_NUM_PD_GAIN);
2647 reg |= AR5K_REG_SM(pdg_to_idx[2], AR5K_PHY_TPC_RG1_PDGAIN_3);
2650 reg |= AR5K_REG_SM(pdg_to_idx[1], AR5K_PHY_TPC_RG1_PDGAIN_2);
2653 reg |= AR5K_REG_SM(pdg_to_idx[0], AR5K_PHY_TPC_RG1_PDGAIN_1);
2656 ath5k_hw_reg_write(ah, reg, AR5K_PHY_TPC_RG1);
2659 * Write TX power values
2661 for (i = 0; i < (AR5K_EEPROM_POWER_TABLE_SIZE / 2); i++) {
2662 ath5k_hw_reg_write(ah,
2663 ((pdadc_out[4*i + 0] & 0xff) << 0) |
2664 ((pdadc_out[4*i + 1] & 0xff) << 8) |
2665 ((pdadc_out[4*i + 2] & 0xff) << 16) |
2666 ((pdadc_out[4*i + 3] & 0xff) << 24),
2667 AR5K_PHY_PDADC_TXPOWER(i));
2673 * Common code for PCDAC/PDADC tables
2677 * This is the main function that uses all of the above
2678 * to set PCDAC/PDADC table on hw for the current channel.
2679 * This table is used for tx power calibration on the basband,
2680 * without it we get weird tx power levels and in some cases
2681 * distorted spectral mask
2684 ath5k_setup_channel_powertable(struct ath5k_hw *ah,
2685 struct ieee80211_channel *channel,
2686 u8 ee_mode, u8 type)
2688 struct ath5k_pdgain_info *pdg_L, *pdg_R;
2689 struct ath5k_chan_pcal_info *pcinfo_L;
2690 struct ath5k_chan_pcal_info *pcinfo_R;
2691 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
2692 u8 *pdg_curve_to_idx = ee->ee_pdc_to_idx[ee_mode];
2693 s16 table_min[AR5K_EEPROM_N_PD_GAINS];
2694 s16 table_max[AR5K_EEPROM_N_PD_GAINS];
2697 u32 target = channel->center_freq;
2700 /* Get surounding freq piers for this channel */
2701 ath5k_get_chan_pcal_surrounding_piers(ah, channel,
2705 /* Loop over pd gain curves on
2706 * surounding freq piers by index */
2707 for (pdg = 0; pdg < ee->ee_pd_gains[ee_mode]; pdg++) {
2709 /* Fill curves in reverse order
2710 * from lower power (max gain)
2711 * to higher power. Use curve -> idx
2712 * backmapping we did on eeprom init */
2713 u8 idx = pdg_curve_to_idx[pdg];
2715 /* Grab the needed curves by index */
2716 pdg_L = &pcinfo_L->pd_curves[idx];
2717 pdg_R = &pcinfo_R->pd_curves[idx];
2719 /* Initialize the temp tables */
2720 tmpL = ah->ah_txpower.tmpL[pdg];
2721 tmpR = ah->ah_txpower.tmpR[pdg];
2723 /* Set curve's x boundaries and create
2724 * curves so that they cover the same
2725 * range (if we don't do that one table
2726 * will have values on some range and the
2727 * other one won't have any so interpolation
2729 table_min[pdg] = min(pdg_L->pd_pwr[0],
2730 pdg_R->pd_pwr[0]) / 2;
2732 table_max[pdg] = max(pdg_L->pd_pwr[pdg_L->pd_points - 1],
2733 pdg_R->pd_pwr[pdg_R->pd_points - 1]) / 2;
2735 /* Now create the curves on surrounding channels
2736 * and interpolate if needed to get the final
2737 * curve for this gain on this channel */
2739 case AR5K_PWRTABLE_LINEAR_PCDAC:
2740 /* Override min/max so that we don't loose
2741 * accuracy (don't divide by 2) */
2742 table_min[pdg] = min(pdg_L->pd_pwr[0],
2746 max(pdg_L->pd_pwr[pdg_L->pd_points - 1],
2747 pdg_R->pd_pwr[pdg_R->pd_points - 1]);
2749 /* Override minimum so that we don't get
2750 * out of bounds while extrapolating
2751 * below. Don't do this when we have 2
2752 * curves and we are on the high power curve
2753 * because table_min is ok in this case */
2754 if (!(ee->ee_pd_gains[ee_mode] > 1 && pdg == 0)) {
2757 ath5k_get_linear_pcdac_min(pdg_L->pd_step,
2762 /* Don't go too low because we will
2763 * miss the upper part of the curve.
2764 * Note: 126 = 31.5dB (max power supported)
2765 * in 0.25dB units */
2766 if (table_max[pdg] - table_min[pdg] > 126)
2767 table_min[pdg] = table_max[pdg] - 126;
2771 case AR5K_PWRTABLE_PWR_TO_PCDAC:
2772 case AR5K_PWRTABLE_PWR_TO_PDADC:
2774 ath5k_create_power_curve(table_min[pdg],
2778 pdg_L->pd_points, tmpL, type);
2780 /* We are in a calibration
2781 * pier, no need to interpolate
2782 * between freq piers */
2783 if (pcinfo_L == pcinfo_R)
2786 ath5k_create_power_curve(table_min[pdg],
2790 pdg_R->pd_points, tmpR, type);
2796 /* Interpolate between curves
2797 * of surounding freq piers to
2798 * get the final curve for this
2799 * pd gain. Re-use tmpL for interpolation
2801 for (i = 0; (i < (u16) (table_max[pdg] - table_min[pdg])) &&
2802 (i < AR5K_EEPROM_POWER_TABLE_SIZE); i++) {
2803 tmpL[i] = (u8) ath5k_get_interpolated_value(target,
2804 (s16) pcinfo_L->freq,
2805 (s16) pcinfo_R->freq,
2811 /* Now we have a set of curves for this
2812 * channel on tmpL (x range is table_max - table_min
2813 * and y values are tmpL[pdg][]) sorted in the same
2814 * order as EEPROM (because we've used the backmapping).
2815 * So for RF5112 it's from higher power to lower power
2816 * and for RF2413 it's from lower power to higher power.
2817 * For RF5111 we only have one curve. */
2819 /* Fill min and max power levels for this
2820 * channel by interpolating the values on
2821 * surounding channels to complete the dataset */
2822 ah->ah_txpower.txp_min_pwr = ath5k_get_interpolated_value(target,
2823 (s16) pcinfo_L->freq,
2824 (s16) pcinfo_R->freq,
2825 pcinfo_L->min_pwr, pcinfo_R->min_pwr);
2827 ah->ah_txpower.txp_max_pwr = ath5k_get_interpolated_value(target,
2828 (s16) pcinfo_L->freq,
2829 (s16) pcinfo_R->freq,
2830 pcinfo_L->max_pwr, pcinfo_R->max_pwr);
2832 /* We are ready to go, fill PCDAC/PDADC
2833 * table and write settings on hardware */
2835 case AR5K_PWRTABLE_LINEAR_PCDAC:
2836 /* For RF5112 we can have one or two curves
2837 * and each curve covers a certain power lvl
2838 * range so we need to do some more processing */
2839 ath5k_combine_linear_pcdac_curves(ah, table_min, table_max,
2840 ee->ee_pd_gains[ee_mode]);
2842 /* Set txp.offset so that we can
2843 * match max power value with max
2845 ah->ah_txpower.txp_offset = 64 - (table_max[0] / 2);
2847 /* Write settings on hw */
2848 ath5k_setup_pcdac_table(ah);
2850 case AR5K_PWRTABLE_PWR_TO_PCDAC:
2851 /* We are done for RF5111 since it has only
2852 * one curve, just fit the curve on the table */
2853 ath5k_fill_pwr_to_pcdac_table(ah, table_min, table_max);
2855 /* No rate powertable adjustment for RF5111 */
2856 ah->ah_txpower.txp_min_idx = 0;
2857 ah->ah_txpower.txp_offset = 0;
2859 /* Write settings on hw */
2860 ath5k_setup_pcdac_table(ah);
2862 case AR5K_PWRTABLE_PWR_TO_PDADC:
2863 /* Set PDADC boundaries and fill
2864 * final PDADC table */
2865 ath5k_combine_pwr_to_pdadc_curves(ah, table_min, table_max,
2866 ee->ee_pd_gains[ee_mode]);
2868 /* Write settings on hw */
2869 ath5k_setup_pwr_to_pdadc_table(ah, pdg, pdg_curve_to_idx);
2871 /* Set txp.offset, note that table_min
2872 * can be negative */
2873 ah->ah_txpower.txp_offset = table_min[0];
2884 * Per-rate tx power setting
2886 * This is the code that sets the desired tx power (below
2887 * maximum) on hw for each rate (we also have TPC that sets
2888 * power per packet). We do that by providing an index on the
2889 * PCDAC/PDADC table we set up.
2893 * Set rate power table
2895 * For now we only limit txpower based on maximum tx power
2896 * supported by hw (what's inside rate_info). We need to limit
2897 * this even more, based on regulatory domain etc.
2899 * Rate power table contains indices to PCDAC/PDADC table (0.5dB steps)
2900 * and is indexed as follows:
2901 * rates[0] - rates[7] -> OFDM rates
2902 * rates[8] - rates[14] -> CCK rates
2903 * rates[15] -> XR rates (they all have the same power)
2906 ath5k_setup_rate_powertable(struct ath5k_hw *ah, u16 max_pwr,
2907 struct ath5k_rate_pcal_info *rate_info,
2913 /* max_pwr is power level we got from driver/user in 0.5dB
2914 * units, switch to 0.25dB units so we can compare */
2916 max_pwr = min(max_pwr, (u16) ah->ah_txpower.txp_max_pwr) / 2;
2918 /* apply rate limits */
2919 rates = ah->ah_txpower.txp_rates_power_table;
2921 /* OFDM rates 6 to 24Mb/s */
2922 for (i = 0; i < 5; i++)
2923 rates[i] = min(max_pwr, rate_info->target_power_6to24);
2925 /* Rest OFDM rates */
2926 rates[5] = min(rates[0], rate_info->target_power_36);
2927 rates[6] = min(rates[0], rate_info->target_power_48);
2928 rates[7] = min(rates[0], rate_info->target_power_54);
2932 rates[8] = min(rates[0], rate_info->target_power_6to24);
2934 rates[9] = min(rates[0], rate_info->target_power_36);
2936 rates[10] = min(rates[0], rate_info->target_power_36);
2938 rates[11] = min(rates[0], rate_info->target_power_48);
2940 rates[12] = min(rates[0], rate_info->target_power_48);
2942 rates[13] = min(rates[0], rate_info->target_power_54);
2944 rates[14] = min(rates[0], rate_info->target_power_54);
2947 rates[15] = min(rates[0], rate_info->target_power_6to24);
2949 /* CCK rates have different peak to average ratio
2950 * so we have to tweak their power so that gainf
2951 * correction works ok. For this we use OFDM to
2952 * CCK delta from eeprom */
2953 if ((ee_mode == AR5K_EEPROM_MODE_11G) &&
2954 (ah->ah_phy_revision < AR5K_SREV_PHY_5212A))
2955 for (i = 8; i <= 15; i++)
2956 rates[i] -= ah->ah_txpower.txp_cck_ofdm_gainf_delta;
2958 /* Now that we have all rates setup use table offset to
2959 * match the power range set by user with the power indices
2960 * on PCDAC/PDADC table */
2961 for (i = 0; i < 16; i++) {
2962 rates[i] += ah->ah_txpower.txp_offset;
2963 /* Don't get out of bounds */
2968 /* Min/max in 0.25dB units */
2969 ah->ah_txpower.txp_min_pwr = 2 * rates[7];
2970 ah->ah_txpower.txp_max_pwr = 2 * rates[0];
2971 ah->ah_txpower.txp_ofdm = rates[7];
2976 * Set transmition power
2979 ath5k_hw_txpower(struct ath5k_hw *ah, struct ieee80211_channel *channel,
2980 u8 ee_mode, u8 txpower)
2982 struct ath5k_rate_pcal_info rate_info;
2986 ATH5K_TRACE(ah->ah_sc);
2987 if (txpower > AR5K_TUNE_MAX_TXPOWER) {
2988 ATH5K_ERR(ah->ah_sc, "invalid tx power: %u\n", txpower);
2992 /* Reset TX power values */
2993 memset(&ah->ah_txpower, 0, sizeof(ah->ah_txpower));
2994 ah->ah_txpower.txp_tpc = AR5K_TUNE_TPC_TXPOWER;
2995 ah->ah_txpower.txp_min_pwr = 0;
2996 ah->ah_txpower.txp_max_pwr = AR5K_TUNE_MAX_TXPOWER;
2998 /* Initialize TX power table */
2999 switch (ah->ah_radio) {
3001 type = AR5K_PWRTABLE_PWR_TO_PCDAC;
3004 type = AR5K_PWRTABLE_LINEAR_PCDAC;
3011 type = AR5K_PWRTABLE_PWR_TO_PDADC;
3017 /* FIXME: Only on channel/mode change */
3018 ret = ath5k_setup_channel_powertable(ah, channel, ee_mode, type);
3022 /* Limit max power if we have a CTL available */
3023 ath5k_get_max_ctl_power(ah, channel);
3025 /* FIXME: Tx power limit for this regdomain
3026 * XXX: Mac80211/CRDA will do that anyway ? */
3028 /* FIXME: Antenna reduction stuff */
3030 /* FIXME: Limit power on turbo modes */
3032 /* FIXME: TPC scale reduction */
3034 /* Get surounding channels for per-rate power table
3036 ath5k_get_rate_pcal_data(ah, channel, &rate_info);
3038 /* Setup rate power table */
3039 ath5k_setup_rate_powertable(ah, txpower, &rate_info, ee_mode);
3041 /* Write rate power table on hw */
3042 ath5k_hw_reg_write(ah, AR5K_TXPOWER_OFDM(3, 24) |
3043 AR5K_TXPOWER_OFDM(2, 16) | AR5K_TXPOWER_OFDM(1, 8) |
3044 AR5K_TXPOWER_OFDM(0, 0), AR5K_PHY_TXPOWER_RATE1);
3046 ath5k_hw_reg_write(ah, AR5K_TXPOWER_OFDM(7, 24) |
3047 AR5K_TXPOWER_OFDM(6, 16) | AR5K_TXPOWER_OFDM(5, 8) |
3048 AR5K_TXPOWER_OFDM(4, 0), AR5K_PHY_TXPOWER_RATE2);
3050 ath5k_hw_reg_write(ah, AR5K_TXPOWER_CCK(10, 24) |
3051 AR5K_TXPOWER_CCK(9, 16) | AR5K_TXPOWER_CCK(15, 8) |
3052 AR5K_TXPOWER_CCK(8, 0), AR5K_PHY_TXPOWER_RATE3);
3054 ath5k_hw_reg_write(ah, AR5K_TXPOWER_CCK(14, 24) |
3055 AR5K_TXPOWER_CCK(13, 16) | AR5K_TXPOWER_CCK(12, 8) |
3056 AR5K_TXPOWER_CCK(11, 0), AR5K_PHY_TXPOWER_RATE4);
3058 /* FIXME: TPC support */
3059 if (ah->ah_txpower.txp_tpc) {
3060 ath5k_hw_reg_write(ah, AR5K_PHY_TXPOWER_RATE_MAX_TPC_ENABLE |
3061 AR5K_TUNE_MAX_TXPOWER, AR5K_PHY_TXPOWER_RATE_MAX);
3063 ath5k_hw_reg_write(ah,
3064 AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER, AR5K_TPC_ACK) |
3065 AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER, AR5K_TPC_CTS) |
3066 AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER, AR5K_TPC_CHIRP),
3069 ath5k_hw_reg_write(ah, AR5K_PHY_TXPOWER_RATE_MAX |
3070 AR5K_TUNE_MAX_TXPOWER, AR5K_PHY_TXPOWER_RATE_MAX);
3076 int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, u8 txpower)
3079 struct ieee80211_channel *channel = ah->ah_current_channel;
3082 ATH5K_TRACE(ah->ah_sc);
3084 switch (channel->hw_value & CHANNEL_MODES) {
3088 ee_mode = AR5K_EEPROM_MODE_11A;
3092 ee_mode = AR5K_EEPROM_MODE_11G;
3095 ee_mode = AR5K_EEPROM_MODE_11B;
3098 ATH5K_ERR(ah->ah_sc,
3099 "invalid channel: %d\n", channel->center_freq);
3103 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_TXPOWER,
3104 "changing txpower to %d\n", txpower);
3106 return ath5k_hw_txpower(ah, channel, ee_mode, txpower);