2 * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
3 * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>
4 * Copyright (c) 2007-2008 Luis Rodriguez <mcgrof@winlab.rutgers.edu>
5 * Copyright (c) 2007-2008 Pavel Roskin <proski@gnu.org>
6 * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com>
8 * Permission to use, copy, modify, and distribute this software for any
9 * purpose with or without fee is hereby granted, provided that the above
10 * copyright notice and this permission notice appear in all copies.
12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
22 /*****************************\
23 Reset functions and helpers
24 \*****************************/
26 #include <asm/unaligned.h>
28 #include <linux/pci.h> /* To determine if a card is pci-e */
29 #include <linux/log2.h>
30 #include <linux/platform_device.h>
42 * Check if a register write has been completed
44 int ath5k_hw_register_timeout(struct ath5k_hw *ah, u32 reg, u32 flag, u32 val,
50 for (i = AR5K_TUNE_REGISTER_TIMEOUT; i > 0; i--) {
51 data = ath5k_hw_reg_read(ah, reg);
52 if (is_set && (data & flag))
54 else if ((data & flag) == val)
59 return (i <= 0) ? -EAGAIN : 0;
63 /*************************\
64 * Clock related functions *
65 \*************************/
68 * ath5k_hw_htoclock - Translate usec to hw clock units
70 * @ah: The &struct ath5k_hw
71 * @usec: value in microseconds
73 unsigned int ath5k_hw_htoclock(struct ath5k_hw *ah, unsigned int usec)
75 struct ath_common *common = ath5k_hw_common(ah);
76 return usec * common->clockrate;
80 * ath5k_hw_clocktoh - Translate hw clock units to usec
81 * @clock: value in hw clock units
83 unsigned int ath5k_hw_clocktoh(struct ath5k_hw *ah, unsigned int clock)
85 struct ath_common *common = ath5k_hw_common(ah);
86 return clock / common->clockrate;
90 * ath5k_hw_init_core_clock - Initialize core clock
92 * @ah The &struct ath5k_hw
94 * Initialize core clock parameters (usec, usec32, latencies etc).
96 static void ath5k_hw_init_core_clock(struct ath5k_hw *ah)
98 struct ieee80211_channel *channel = ah->ah_current_channel;
99 struct ath_common *common = ath5k_hw_common(ah);
100 u32 usec_reg, txlat, rxlat, usec, clock, sclock, txf2txs;
103 * Set core clock frequency
105 if (channel->hw_value & CHANNEL_5GHZ)
106 clock = 40; /* 802.11a */
107 else if (channel->hw_value & CHANNEL_CCK)
108 clock = 22; /* 802.11b */
110 clock = 44; /* 802.11g */
112 /* Use clock multiplier for non-default
114 switch (ah->ah_bwmode) {
115 case AR5K_BWMODE_40MHZ:
118 case AR5K_BWMODE_10MHZ:
121 case AR5K_BWMODE_5MHZ:
128 common->clockrate = clock;
131 * Set USEC parameters
133 /* Set USEC counter on PCU*/
135 usec = AR5K_REG_SM(usec, AR5K_USEC_1);
137 /* Set usec duration on DCU */
138 if (ah->ah_version != AR5K_AR5210)
139 AR5K_REG_WRITE_BITS(ah, AR5K_DCU_GBL_IFS_MISC,
140 AR5K_DCU_GBL_IFS_MISC_USEC_DUR,
143 /* Set 32MHz USEC counter */
144 if ((ah->ah_radio == AR5K_RF5112) ||
145 (ah->ah_radio == AR5K_RF5413) ||
146 (ah->ah_radio == AR5K_RF2316) ||
147 (ah->ah_radio == AR5K_RF2317))
148 /* Remain on 40MHz clock ? */
152 sclock = AR5K_REG_SM(sclock, AR5K_USEC_32);
155 * Set tx/rx latencies
157 usec_reg = ath5k_hw_reg_read(ah, AR5K_USEC_5211);
158 txlat = AR5K_REG_MS(usec_reg, AR5K_USEC_TX_LATENCY_5211);
159 rxlat = AR5K_REG_MS(usec_reg, AR5K_USEC_RX_LATENCY_5211);
162 * 5210 initvals don't include usec settings
163 * so we need to use magic values here for
166 if (ah->ah_version == AR5K_AR5210) {
168 txlat = AR5K_INIT_TX_LATENCY_5210;
169 rxlat = AR5K_INIT_RX_LATENCY_5210;
172 if (ah->ah_mac_srev < AR5K_SREV_AR5211) {
173 /* 5311 has different tx/rx latency masks
174 * from 5211, since we deal 5311 the same
175 * as 5211 when setting initvals, shift
176 * values here to their proper locations
178 * Note: Initvals indicate tx/rx/ latencies
179 * are the same for turbo mode */
180 txlat = AR5K_REG_SM(txlat, AR5K_USEC_TX_LATENCY_5210);
181 rxlat = AR5K_REG_SM(rxlat, AR5K_USEC_RX_LATENCY_5210);
183 switch (ah->ah_bwmode) {
184 case AR5K_BWMODE_10MHZ:
185 txlat = AR5K_REG_SM(txlat * 2,
186 AR5K_USEC_TX_LATENCY_5211);
187 rxlat = AR5K_REG_SM(AR5K_INIT_RX_LAT_MAX,
188 AR5K_USEC_RX_LATENCY_5211);
189 txf2txs = AR5K_INIT_TXF2TXD_START_DELAY_10MHZ;
191 case AR5K_BWMODE_5MHZ:
192 txlat = AR5K_REG_SM(txlat * 4,
193 AR5K_USEC_TX_LATENCY_5211);
194 rxlat = AR5K_REG_SM(AR5K_INIT_RX_LAT_MAX,
195 AR5K_USEC_RX_LATENCY_5211);
196 txf2txs = AR5K_INIT_TXF2TXD_START_DELAY_5MHZ;
198 case AR5K_BWMODE_40MHZ:
199 txlat = AR5K_INIT_TX_LAT_MIN;
200 rxlat = AR5K_REG_SM(rxlat / 2,
201 AR5K_USEC_RX_LATENCY_5211);
202 txf2txs = AR5K_INIT_TXF2TXD_START_DEFAULT;
208 usec_reg = (usec | sclock | txlat | rxlat);
209 ath5k_hw_reg_write(ah, usec_reg, AR5K_USEC);
211 /* On 5112 set tx frane to tx data start delay */
212 if (ah->ah_radio == AR5K_RF5112) {
213 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RF_CTL2,
214 AR5K_PHY_RF_CTL2_TXF2TXD_START,
220 * If there is an external 32KHz crystal available, use it
221 * as ref. clock instead of 32/40MHz clock and baseband clocks
222 * to save power during sleep or restore normal 32/40MHz
225 * XXX: When operating on 32KHz certain PHY registers (27 - 31,
226 * 123 - 127) require delay on access.
228 static void ath5k_hw_set_sleep_clock(struct ath5k_hw *ah, bool enable)
230 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
233 /* Only set 32KHz settings if we have an external
234 * 32KHz crystal present */
235 if ((AR5K_EEPROM_HAS32KHZCRYSTAL(ee->ee_misc1) ||
236 AR5K_EEPROM_HAS32KHZCRYSTAL_OLD(ee->ee_misc1)) &&
240 AR5K_REG_WRITE_BITS(ah, AR5K_USEC_5211, AR5K_USEC_32, 1);
241 /* Set up tsf increment on each cycle */
242 AR5K_REG_WRITE_BITS(ah, AR5K_TSF_PARM, AR5K_TSF_PARM_INC, 61);
244 /* Set baseband sleep control registers
245 * and sleep control rate */
246 ath5k_hw_reg_write(ah, 0x1f, AR5K_PHY_SCR);
248 if ((ah->ah_radio == AR5K_RF5112) ||
249 (ah->ah_radio == AR5K_RF5413) ||
250 (ah->ah_radio == AR5K_RF2316) ||
251 (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4)))
255 ath5k_hw_reg_write(ah, spending, AR5K_PHY_SPENDING);
257 if ((ah->ah_radio == AR5K_RF5112) ||
258 (ah->ah_radio == AR5K_RF5413) ||
259 (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))) {
260 ath5k_hw_reg_write(ah, 0x26, AR5K_PHY_SLMT);
261 ath5k_hw_reg_write(ah, 0x0d, AR5K_PHY_SCAL);
262 ath5k_hw_reg_write(ah, 0x07, AR5K_PHY_SCLOCK);
263 ath5k_hw_reg_write(ah, 0x3f, AR5K_PHY_SDELAY);
264 AR5K_REG_WRITE_BITS(ah, AR5K_PCICFG,
265 AR5K_PCICFG_SLEEP_CLOCK_RATE, 0x02);
267 ath5k_hw_reg_write(ah, 0x0a, AR5K_PHY_SLMT);
268 ath5k_hw_reg_write(ah, 0x0c, AR5K_PHY_SCAL);
269 ath5k_hw_reg_write(ah, 0x03, AR5K_PHY_SCLOCK);
270 ath5k_hw_reg_write(ah, 0x20, AR5K_PHY_SDELAY);
271 AR5K_REG_WRITE_BITS(ah, AR5K_PCICFG,
272 AR5K_PCICFG_SLEEP_CLOCK_RATE, 0x03);
275 /* Enable sleep clock operation */
276 AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG,
277 AR5K_PCICFG_SLEEP_CLOCK_EN);
281 /* Disable sleep clock operation and
282 * restore default parameters */
283 AR5K_REG_DISABLE_BITS(ah, AR5K_PCICFG,
284 AR5K_PCICFG_SLEEP_CLOCK_EN);
286 AR5K_REG_WRITE_BITS(ah, AR5K_PCICFG,
287 AR5K_PCICFG_SLEEP_CLOCK_RATE, 0);
289 /* Set DAC/ADC delays */
290 ath5k_hw_reg_write(ah, 0x1f, AR5K_PHY_SCR);
291 ath5k_hw_reg_write(ah, AR5K_PHY_SLMT_32MHZ, AR5K_PHY_SLMT);
293 if (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))
294 scal = AR5K_PHY_SCAL_32MHZ_2417;
295 else if (ee->ee_is_hb63)
296 scal = AR5K_PHY_SCAL_32MHZ_HB63;
298 scal = AR5K_PHY_SCAL_32MHZ;
299 ath5k_hw_reg_write(ah, scal, AR5K_PHY_SCAL);
301 ath5k_hw_reg_write(ah, AR5K_PHY_SCLOCK_32MHZ, AR5K_PHY_SCLOCK);
302 ath5k_hw_reg_write(ah, AR5K_PHY_SDELAY_32MHZ, AR5K_PHY_SDELAY);
304 if ((ah->ah_radio == AR5K_RF5112) ||
305 (ah->ah_radio == AR5K_RF5413) ||
306 (ah->ah_radio == AR5K_RF2316) ||
307 (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4)))
311 ath5k_hw_reg_write(ah, spending, AR5K_PHY_SPENDING);
313 /* Set up tsf increment on each cycle */
314 AR5K_REG_WRITE_BITS(ah, AR5K_TSF_PARM, AR5K_TSF_PARM_INC, 1);
319 /*********************\
320 * Reset/Sleep control *
321 \*********************/
326 static int ath5k_hw_nic_reset(struct ath5k_hw *ah, u32 val)
329 u32 mask = val ? val : ~0U;
331 /* Read-and-clear RX Descriptor Pointer*/
332 ath5k_hw_reg_read(ah, AR5K_RXDP);
335 * Reset the device and wait until success
337 ath5k_hw_reg_write(ah, val, AR5K_RESET_CTL);
339 /* Wait at least 128 PCI clocks */
342 if (ah->ah_version == AR5K_AR5210) {
343 val &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_DMA
344 | AR5K_RESET_CTL_MAC | AR5K_RESET_CTL_PHY;
345 mask &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_DMA
346 | AR5K_RESET_CTL_MAC | AR5K_RESET_CTL_PHY;
348 val &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_BASEBAND;
349 mask &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_BASEBAND;
352 ret = ath5k_hw_register_timeout(ah, AR5K_RESET_CTL, mask, val, false);
355 * Reset configuration register (for hw byte-swap). Note that this
356 * is only set for big endian. We do the necessary magic in
359 if ((val & AR5K_RESET_CTL_PCU) == 0)
360 ath5k_hw_reg_write(ah, AR5K_INIT_CFG, AR5K_CFG);
367 * AR5K_RESET_CTL_PCU flag resets WMAC
368 * AR5K_RESET_CTL_BASEBAND flag resets WBB
370 static int ath5k_hw_wisoc_reset(struct ath5k_hw *ah, u32 flags)
372 u32 mask = flags ? flags : ~0U;
377 /* ah->ah_mac_srev is not available at this point yet */
378 if (ah->ah_sc->devid >= AR5K_SREV_AR2315_R6) {
379 reg = (u32 *) AR5K_AR2315_RESET;
380 if (mask & AR5K_RESET_CTL_PCU)
381 val |= AR5K_AR2315_RESET_WMAC;
382 if (mask & AR5K_RESET_CTL_BASEBAND)
383 val |= AR5K_AR2315_RESET_BB_WARM;
385 reg = (u32 *) AR5K_AR5312_RESET;
386 if (to_platform_device(ah->ah_sc->dev)->id == 0) {
387 if (mask & AR5K_RESET_CTL_PCU)
388 val |= AR5K_AR5312_RESET_WMAC0;
389 if (mask & AR5K_RESET_CTL_BASEBAND)
390 val |= AR5K_AR5312_RESET_BB0_COLD |
391 AR5K_AR5312_RESET_BB0_WARM;
393 if (mask & AR5K_RESET_CTL_PCU)
394 val |= AR5K_AR5312_RESET_WMAC1;
395 if (mask & AR5K_RESET_CTL_BASEBAND)
396 val |= AR5K_AR5312_RESET_BB1_COLD |
397 AR5K_AR5312_RESET_BB1_WARM;
401 /* Put BB/MAC into reset */
402 regval = __raw_readl(reg);
403 __raw_writel(regval | val, reg);
404 regval = __raw_readl(reg);
407 /* Bring BB/MAC out of reset */
408 __raw_writel(regval & ~val, reg);
409 regval = __raw_readl(reg);
412 * Reset configuration register (for hw byte-swap). Note that this
413 * is only set for big endian. We do the necessary magic in
416 if ((flags & AR5K_RESET_CTL_PCU) == 0)
417 ath5k_hw_reg_write(ah, AR5K_INIT_CFG, AR5K_CFG);
426 static int ath5k_hw_set_power(struct ath5k_hw *ah, enum ath5k_power_mode mode,
427 bool set_chip, u16 sleep_duration)
432 staid = ath5k_hw_reg_read(ah, AR5K_STA_ID1);
436 staid &= ~AR5K_STA_ID1_DEFAULT_ANTENNA;
438 case AR5K_PM_NETWORK_SLEEP:
440 ath5k_hw_reg_write(ah,
441 AR5K_SLEEP_CTL_SLE_ALLOW |
445 staid |= AR5K_STA_ID1_PWR_SV;
448 case AR5K_PM_FULL_SLEEP:
450 ath5k_hw_reg_write(ah, AR5K_SLEEP_CTL_SLE_SLP,
453 staid |= AR5K_STA_ID1_PWR_SV;
458 staid &= ~AR5K_STA_ID1_PWR_SV;
463 data = ath5k_hw_reg_read(ah, AR5K_SLEEP_CTL);
465 /* If card is down we 'll get 0xffff... so we
466 * need to clean this up before we write the register
468 if (data & 0xffc00000)
471 /* Preserve sleep duration etc */
472 data = data & ~AR5K_SLEEP_CTL_SLE;
474 ath5k_hw_reg_write(ah, data | AR5K_SLEEP_CTL_SLE_WAKE,
478 for (i = 200; i > 0; i--) {
479 /* Check if the chip did wake up */
480 if ((ath5k_hw_reg_read(ah, AR5K_PCICFG) &
481 AR5K_PCICFG_SPWR_DN) == 0)
484 /* Wait a bit and retry */
486 ath5k_hw_reg_write(ah, data | AR5K_SLEEP_CTL_SLE_WAKE,
490 /* Fail if the chip didn't wake up */
501 ath5k_hw_reg_write(ah, staid, AR5K_STA_ID1);
509 * Put MAC and Baseband on warm reset and
510 * keep that state (don't clean sleep control
511 * register). After this MAC and Baseband are
512 * disabled and a full reset is needed to come
513 * back. This way we save as much power as possible
514 * without putting the card on full sleep.
516 int ath5k_hw_on_hold(struct ath5k_hw *ah)
518 struct pci_dev *pdev = ah->ah_sc->pdev;
522 if (ath5k_get_bus_type(ah) == ATH_AHB)
525 /* Make sure device is awake */
526 ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0);
528 ATH5K_ERR(ah->ah_sc, "failed to wakeup the MAC Chip\n");
533 * Put chipset on warm reset...
535 * Note: putting PCI core on warm reset on PCI-E cards
536 * results card to hang and always return 0xffff... so
537 * we ingore that flag for PCI-E cards. On PCI cards
538 * this flag gets cleared after 64 PCI clocks.
540 bus_flags = (pdev && pdev->is_pcie) ? 0 : AR5K_RESET_CTL_PCI;
542 if (ah->ah_version == AR5K_AR5210) {
543 ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU |
544 AR5K_RESET_CTL_MAC | AR5K_RESET_CTL_DMA |
545 AR5K_RESET_CTL_PHY | AR5K_RESET_CTL_PCI);
548 ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU |
549 AR5K_RESET_CTL_BASEBAND | bus_flags);
553 ATH5K_ERR(ah->ah_sc, "failed to put device on warm reset\n");
557 /* ...wakeup again!*/
558 ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0);
560 ATH5K_ERR(ah->ah_sc, "failed to put device on hold\n");
568 * Bring up MAC + PHY Chips and program PLL
570 int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, bool initial)
572 struct pci_dev *pdev = ah->ah_sc->pdev;
573 u32 turbo, mode, clock, bus_flags;
580 if ((ath5k_get_bus_type(ah) != ATH_AHB) || !initial) {
581 /* Wakeup the device */
582 ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0);
584 ATH5K_ERR(ah->ah_sc, "failed to wakeup the MAC Chip\n");
590 * Put chipset on warm reset...
592 * Note: putting PCI core on warm reset on PCI-E cards
593 * results card to hang and always return 0xffff... so
594 * we ingore that flag for PCI-E cards. On PCI cards
595 * this flag gets cleared after 64 PCI clocks.
597 bus_flags = (pdev && pdev->is_pcie) ? 0 : AR5K_RESET_CTL_PCI;
599 if (ah->ah_version == AR5K_AR5210) {
600 ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU |
601 AR5K_RESET_CTL_MAC | AR5K_RESET_CTL_DMA |
602 AR5K_RESET_CTL_PHY | AR5K_RESET_CTL_PCI);
605 if (ath5k_get_bus_type(ah) == ATH_AHB)
606 ret = ath5k_hw_wisoc_reset(ah, AR5K_RESET_CTL_PCU |
607 AR5K_RESET_CTL_BASEBAND);
609 ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU |
610 AR5K_RESET_CTL_BASEBAND | bus_flags);
614 ATH5K_ERR(ah->ah_sc, "failed to reset the MAC Chip\n");
618 /* ...wakeup again!...*/
619 ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0);
621 ATH5K_ERR(ah->ah_sc, "failed to resume the MAC Chip\n");
625 /* ...reset configuration regiter on Wisoc ...
626 * ...clear reset control register and pull device out of
627 * warm reset on others */
628 if (ath5k_get_bus_type(ah) == ATH_AHB)
629 ret = ath5k_hw_wisoc_reset(ah, 0);
631 ret = ath5k_hw_nic_reset(ah, 0);
634 ATH5K_ERR(ah->ah_sc, "failed to warm reset the MAC Chip\n");
638 /* On initialization skip PLL programming since we don't have
639 * a channel / mode set yet */
643 if (ah->ah_version != AR5K_AR5210) {
645 * Get channel mode flags
648 if (ah->ah_radio >= AR5K_RF5112) {
649 mode = AR5K_PHY_MODE_RAD_RF5112;
650 clock = AR5K_PHY_PLL_RF5112;
652 mode = AR5K_PHY_MODE_RAD_RF5111; /*Zero*/
653 clock = AR5K_PHY_PLL_RF5111; /*Zero*/
656 if (flags & CHANNEL_2GHZ) {
657 mode |= AR5K_PHY_MODE_FREQ_2GHZ;
658 clock |= AR5K_PHY_PLL_44MHZ;
660 if (flags & CHANNEL_CCK) {
661 mode |= AR5K_PHY_MODE_MOD_CCK;
662 } else if (flags & CHANNEL_OFDM) {
663 /* XXX Dynamic OFDM/CCK is not supported by the
664 * AR5211 so we set MOD_OFDM for plain g (no
665 * CCK headers) operation. We need to test
666 * this, 5211 might support ofdm-only g after
667 * all, there are also initial register values
668 * in the code for g mode (see initvals.c).
670 if (ah->ah_version == AR5K_AR5211)
671 mode |= AR5K_PHY_MODE_MOD_OFDM;
673 mode |= AR5K_PHY_MODE_MOD_DYN;
676 "invalid radio modulation mode\n");
679 } else if (flags & CHANNEL_5GHZ) {
680 mode |= AR5K_PHY_MODE_FREQ_5GHZ;
682 /* Different PLL setting for 5413 */
683 if (ah->ah_radio == AR5K_RF5413)
684 clock = AR5K_PHY_PLL_40MHZ_5413;
686 clock |= AR5K_PHY_PLL_40MHZ;
688 if (flags & CHANNEL_OFDM)
689 mode |= AR5K_PHY_MODE_MOD_OFDM;
692 "invalid radio modulation mode\n");
696 ATH5K_ERR(ah->ah_sc, "invalid radio frequency mode\n");
700 /*XXX: Can bwmode be used with dynamic mode ?
701 * (I don't think it supports 44MHz) */
702 /* On 2425 initvals TURBO_SHORT is not pressent */
703 if (ah->ah_bwmode == AR5K_BWMODE_40MHZ) {
704 turbo = AR5K_PHY_TURBO_MODE |
705 (ah->ah_radio == AR5K_RF2425) ? 0 :
706 AR5K_PHY_TURBO_SHORT;
707 } else if (ah->ah_bwmode != AR5K_BWMODE_DEFAULT) {
708 if (ah->ah_radio == AR5K_RF5413) {
709 mode |= (ah->ah_bwmode == AR5K_BWMODE_10MHZ) ?
710 AR5K_PHY_MODE_HALF_RATE :
711 AR5K_PHY_MODE_QUARTER_RATE;
712 } else if (ah->ah_version == AR5K_AR5212) {
713 clock |= (ah->ah_bwmode == AR5K_BWMODE_10MHZ) ?
714 AR5K_PHY_PLL_HALF_RATE :
715 AR5K_PHY_PLL_QUARTER_RATE;
719 } else { /* Reset the device */
721 /* ...enable Atheros turbo mode if requested */
722 if (ah->ah_bwmode == AR5K_BWMODE_40MHZ)
723 ath5k_hw_reg_write(ah, AR5K_PHY_TURBO_MODE,
727 if (ah->ah_version != AR5K_AR5210) {
729 /* ...update PLL if needed */
730 if (ath5k_hw_reg_read(ah, AR5K_PHY_PLL) != clock) {
731 ath5k_hw_reg_write(ah, clock, AR5K_PHY_PLL);
735 /* ...set the PHY operating mode */
736 ath5k_hw_reg_write(ah, mode, AR5K_PHY_MODE);
737 ath5k_hw_reg_write(ah, turbo, AR5K_PHY_TURBO);
744 /**************************************\
745 * Post-initvals register modifications *
746 \**************************************/
748 /* TODO: Half/Quarter rate */
749 static void ath5k_hw_tweak_initval_settings(struct ath5k_hw *ah,
750 struct ieee80211_channel *channel)
752 if (ah->ah_version == AR5K_AR5212 &&
753 ah->ah_phy_revision >= AR5K_SREV_PHY_5212A) {
755 /* Setup ADC control */
756 ath5k_hw_reg_write(ah,
758 AR5K_PHY_ADC_CTL_INBUFGAIN_OFF) |
760 AR5K_PHY_ADC_CTL_INBUFGAIN_ON) |
761 AR5K_PHY_ADC_CTL_PWD_DAC_OFF |
762 AR5K_PHY_ADC_CTL_PWD_ADC_OFF),
767 /* Disable barker RSSI threshold */
768 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_DAG_CCK_CTL,
769 AR5K_PHY_DAG_CCK_CTL_EN_RSSI_THR);
771 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DAG_CCK_CTL,
772 AR5K_PHY_DAG_CCK_CTL_RSSI_THR, 2);
774 /* Set the mute mask */
775 ath5k_hw_reg_write(ah, 0x0000000f, AR5K_SEQ_MASK);
778 /* Clear PHY_BLUETOOTH to allow RX_CLEAR line debug */
779 if (ah->ah_phy_revision >= AR5K_SREV_PHY_5212B)
780 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BLUETOOTH);
782 /* Enable DCU double buffering */
783 if (ah->ah_phy_revision > AR5K_SREV_PHY_5212B)
784 AR5K_REG_DISABLE_BITS(ah, AR5K_TXCFG,
785 AR5K_TXCFG_DCU_DBL_BUF_DIS);
788 if ((ah->ah_radio == AR5K_RF5413) ||
789 (ah->ah_radio == AR5K_RF2317) ||
790 (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))) {
793 if (channel->center_freq == 2462 ||
794 channel->center_freq == 2467)
797 /* Only update if needed */
798 if (ath5k_hw_reg_read(ah, AR5K_PHY_FAST_ADC) != fast_adc)
799 ath5k_hw_reg_write(ah, fast_adc,
803 /* Fix for first revision of the RF5112 RF chipset */
804 if (ah->ah_radio == AR5K_RF5112 &&
805 ah->ah_radio_5ghz_revision <
806 AR5K_SREV_RAD_5112A) {
808 ath5k_hw_reg_write(ah, AR5K_PHY_CCKTXCTL_WORLD,
810 if (channel->hw_value & CHANNEL_5GHZ)
814 ath5k_hw_reg_write(ah, data, AR5K_PHY_FRAME_CTL);
817 if (ah->ah_mac_srev < AR5K_SREV_AR5211) {
818 /* Clear QCU/DCU clock gating register */
819 ath5k_hw_reg_write(ah, 0, AR5K_QCUDCU_CLKGT);
820 /* Set DAC/ADC delays */
821 ath5k_hw_reg_write(ah, AR5K_PHY_SCAL_32MHZ_5311,
823 /* Enable PCU FIFO corruption ECO */
824 AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW_5211,
825 AR5K_DIAG_SW_ECO_ENABLE);
829 /* Increase PHY switch and AGC settling time
830 * on turbo mode (ath5k_hw_commit_eeprom_settings
831 * will override settling time if available) */
832 if (ah->ah_bwmode == AR5K_BWMODE_40MHZ) {
834 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_SETTLING,
835 AR5K_PHY_SETTLING_AGC,
836 AR5K_AGC_SETTLING_TURBO);
838 /* XXX: Initvals indicate we only increase
839 * switch time on AR5212, 5211 and 5210
840 * only change agc time (bug?) */
841 if (ah->ah_version == AR5K_AR5212)
842 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_SETTLING,
843 AR5K_PHY_SETTLING_SWITCH,
844 AR5K_SWITCH_SETTLING_TURBO);
846 if (ah->ah_version == AR5K_AR5210) {
847 /* Set Frame Control Register */
848 ath5k_hw_reg_write(ah,
849 (AR5K_PHY_FRAME_CTL_INI |
850 AR5K_PHY_TURBO_MODE |
851 AR5K_PHY_TURBO_SHORT | 0x2020),
852 AR5K_PHY_FRAME_CTL_5210);
854 /* On 5413 PHY force window length for half/quarter rate*/
855 } else if ((ah->ah_mac_srev >= AR5K_SREV_AR5424) &&
856 (ah->ah_mac_srev <= AR5K_SREV_AR5414)) {
857 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_FRAME_CTL_5211,
858 AR5K_PHY_FRAME_CTL_WIN_LEN,
861 } else if (ah->ah_version == AR5K_AR5210) {
862 /* Set Frame Control Register for normal operation */
863 ath5k_hw_reg_write(ah, (AR5K_PHY_FRAME_CTL_INI | 0x1020),
864 AR5K_PHY_FRAME_CTL_5210);
868 static void ath5k_hw_commit_eeprom_settings(struct ath5k_hw *ah,
869 struct ieee80211_channel *channel, u8 ee_mode)
871 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
872 s16 cck_ofdm_pwr_delta;
874 /* TODO: Add support for AR5210 EEPROM */
875 if (ah->ah_version == AR5K_AR5210)
878 /* Adjust power delta for channel 14 */
879 if (channel->center_freq == 2484)
881 ((ee->ee_cck_ofdm_power_delta -
882 ee->ee_scaled_cck_delta) * 2) / 10;
885 (ee->ee_cck_ofdm_power_delta * 2) / 10;
887 /* Set CCK to OFDM power delta on tx power
888 * adjustment register */
889 if (ah->ah_phy_revision >= AR5K_SREV_PHY_5212A) {
890 if (channel->hw_value == CHANNEL_G)
891 ath5k_hw_reg_write(ah,
892 AR5K_REG_SM((ee->ee_cck_ofdm_gain_delta * -1),
893 AR5K_PHY_TX_PWR_ADJ_CCK_GAIN_DELTA) |
894 AR5K_REG_SM((cck_ofdm_pwr_delta * -1),
895 AR5K_PHY_TX_PWR_ADJ_CCK_PCDAC_INDEX),
896 AR5K_PHY_TX_PWR_ADJ);
898 ath5k_hw_reg_write(ah, 0, AR5K_PHY_TX_PWR_ADJ);
900 /* For older revs we scale power on sw during tx power
902 ah->ah_txpower.txp_cck_ofdm_pwr_delta = cck_ofdm_pwr_delta;
903 ah->ah_txpower.txp_cck_ofdm_gainf_delta =
904 ee->ee_cck_ofdm_gain_delta;
907 /* XXX: necessary here? is called from ath5k_hw_set_antenna_mode()
909 ath5k_hw_set_antenna_switch(ah, ee_mode);
911 /* Noise floor threshold */
912 ath5k_hw_reg_write(ah,
913 AR5K_PHY_NF_SVAL(ee->ee_noise_floor_thr[ee_mode]),
916 if ((ah->ah_bwmode == AR5K_BWMODE_40MHZ) &&
917 (ah->ah_ee_version >= AR5K_EEPROM_VERSION_5_0)) {
918 /* Switch settling time (Turbo) */
919 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_SETTLING,
920 AR5K_PHY_SETTLING_SWITCH,
921 ee->ee_switch_settling_turbo[ee_mode]);
923 /* Tx/Rx attenuation (Turbo) */
924 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_GAIN,
925 AR5K_PHY_GAIN_TXRX_ATTEN,
926 ee->ee_atn_tx_rx_turbo[ee_mode]);
928 /* ADC/PGA desired size (Turbo) */
929 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DESIRED_SIZE,
930 AR5K_PHY_DESIRED_SIZE_ADC,
931 ee->ee_adc_desired_size_turbo[ee_mode]);
933 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DESIRED_SIZE,
934 AR5K_PHY_DESIRED_SIZE_PGA,
935 ee->ee_pga_desired_size_turbo[ee_mode]);
937 /* Tx/Rx margin (Turbo) */
938 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_GAIN_2GHZ,
939 AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX,
940 ee->ee_margin_tx_rx_turbo[ee_mode]);
943 /* Switch settling time */
944 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_SETTLING,
945 AR5K_PHY_SETTLING_SWITCH,
946 ee->ee_switch_settling[ee_mode]);
948 /* Tx/Rx attenuation */
949 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_GAIN,
950 AR5K_PHY_GAIN_TXRX_ATTEN,
951 ee->ee_atn_tx_rx[ee_mode]);
953 /* ADC/PGA desired size */
954 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DESIRED_SIZE,
955 AR5K_PHY_DESIRED_SIZE_ADC,
956 ee->ee_adc_desired_size[ee_mode]);
958 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DESIRED_SIZE,
959 AR5K_PHY_DESIRED_SIZE_PGA,
960 ee->ee_pga_desired_size[ee_mode]);
963 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_1)
964 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_GAIN_2GHZ,
965 AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX,
966 ee->ee_margin_tx_rx[ee_mode]);
970 ath5k_hw_reg_write(ah,
971 (ee->ee_tx_end2xpa_disable[ee_mode] << 24) |
972 (ee->ee_tx_end2xpa_disable[ee_mode] << 16) |
973 (ee->ee_tx_frm2xpa_enable[ee_mode] << 8) |
974 (ee->ee_tx_frm2xpa_enable[ee_mode]), AR5K_PHY_RF_CTL4);
977 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RF_CTL3,
978 AR5K_PHY_RF_CTL3_TXE2XLNA_ON,
979 ee->ee_tx_end2xlna_enable[ee_mode]);
982 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_NF,
983 AR5K_PHY_NF_THRESH62,
984 ee->ee_thr_62[ee_mode]);
986 /* False detect backoff for channels
987 * that have spur noise. Write the new
988 * cyclic power RSSI threshold. */
989 if (ath5k_hw_chan_has_spur_noise(ah, channel))
990 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_OFDM_SELFCORR,
991 AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1,
992 AR5K_INIT_CYCRSSI_THR1 +
993 ee->ee_false_detect[ee_mode]);
995 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_OFDM_SELFCORR,
996 AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1,
997 AR5K_INIT_CYCRSSI_THR1);
999 /* I/Q correction (set enable bit last to match HAL sources) */
1000 /* TODO: Per channel i/q infos ? */
1001 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) {
1002 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_Q_I_COFF,
1003 ee->ee_i_cal[ee_mode]);
1004 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_Q_Q_COFF,
1005 ee->ee_q_cal[ee_mode]);
1006 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_ENABLE);
1009 /* Heavy clipping -disable for now */
1010 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_5_1)
1011 ath5k_hw_reg_write(ah, 0, AR5K_PHY_HEAVY_CLIP_ENABLE);
1015 /*********************\
1016 * Main reset function *
1017 \*********************/
1019 int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode,
1020 struct ieee80211_channel *channel, bool fast, bool skip_pcu)
1022 u32 s_seq[10], s_led[3], tsf_up, tsf_lo;
1023 u8 mode, freq, ee_mode;
1033 * Sanity check for fast flag
1034 * Fast channel change only available
1037 if (fast && (ah->ah_radio != AR5K_RF2413) &&
1038 (ah->ah_radio != AR5K_RF5413))
1041 /* Disable sleep clock operation
1042 * to avoid register access delay on certain
1044 if (ah->ah_version == AR5K_AR5212)
1045 ath5k_hw_set_sleep_clock(ah, false);
1050 ath5k_hw_stop_rx_pcu(ah);
1055 * Note: If DMA didn't stop continue
1056 * since only a reset will fix it.
1058 ret = ath5k_hw_dma_stop(ah);
1060 /* RF Bus grant won't work if we have pending
1063 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_RESET,
1064 "DMA didn't stop, falling back to normal reset\n");
1066 /* Non fatal, just continue with
1071 switch (channel->hw_value & CHANNEL_MODES) {
1073 mode = AR5K_MODE_11A;
1074 freq = AR5K_INI_RFGAIN_5GHZ;
1075 ee_mode = AR5K_EEPROM_MODE_11A;
1079 if (ah->ah_version <= AR5K_AR5211) {
1080 ATH5K_ERR(ah->ah_sc,
1081 "G mode not available on 5210/5211");
1085 mode = AR5K_MODE_11G;
1086 freq = AR5K_INI_RFGAIN_2GHZ;
1087 ee_mode = AR5K_EEPROM_MODE_11G;
1091 if (ah->ah_version < AR5K_AR5211) {
1092 ATH5K_ERR(ah->ah_sc,
1093 "B mode not available on 5210");
1097 mode = AR5K_MODE_11B;
1098 freq = AR5K_INI_RFGAIN_2GHZ;
1099 ee_mode = AR5K_EEPROM_MODE_11B;
1102 if (ah->ah_version == AR5K_AR5211) {
1103 ATH5K_ERR(ah->ah_sc,
1104 "XR mode not available on 5211");
1107 mode = AR5K_MODE_XR;
1108 freq = AR5K_INI_RFGAIN_5GHZ;
1109 ee_mode = AR5K_EEPROM_MODE_11A;
1112 ATH5K_ERR(ah->ah_sc,
1113 "invalid channel: %d\n", channel->center_freq);
1118 * If driver requested fast channel change and DMA has stopped
1119 * go on. If it fails continue with a normal reset.
1122 ret = ath5k_hw_phy_init(ah, channel, mode,
1123 ee_mode, freq, true);
1125 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_RESET,
1126 "fast chan change failed, falling back to normal reset\n");
1127 /* Non fatal, can happen eg.
1135 * Save some registers before a reset
1137 if (ah->ah_version != AR5K_AR5210) {
1139 * Save frame sequence count
1140 * For revs. after Oahu, only save
1141 * seq num for DCU 0 (Global seq num)
1143 if (ah->ah_mac_srev < AR5K_SREV_AR5211) {
1145 for (i = 0; i < 10; i++)
1146 s_seq[i] = ath5k_hw_reg_read(ah,
1147 AR5K_QUEUE_DCU_SEQNUM(i));
1150 s_seq[0] = ath5k_hw_reg_read(ah,
1151 AR5K_QUEUE_DCU_SEQNUM(0));
1154 /* TSF accelerates on AR5211 during reset
1155 * As a workaround save it here and restore
1156 * it later so that it's back in time after
1157 * reset. This way it'll get re-synced on the
1158 * next beacon without breaking ad-hoc.
1160 * On AR5212 TSF is almost preserved across a
1161 * reset so it stays back in time anyway and
1162 * we don't have to save/restore it.
1164 * XXX: Since this breaks power saving we have
1165 * to disable power saving until we receive the
1166 * next beacon, so we can resync beacon timers */
1167 if (ah->ah_version == AR5K_AR5211) {
1168 tsf_up = ath5k_hw_reg_read(ah, AR5K_TSF_U32);
1169 tsf_lo = ath5k_hw_reg_read(ah, AR5K_TSF_L32);
1175 s_led[0] = ath5k_hw_reg_read(ah, AR5K_PCICFG) &
1176 AR5K_PCICFG_LEDSTATE;
1177 s_led[1] = ath5k_hw_reg_read(ah, AR5K_GPIOCR);
1178 s_led[2] = ath5k_hw_reg_read(ah, AR5K_GPIODO);
1182 * Since we are going to write rf buffer
1183 * check if we have any pending gain_F
1184 * optimization settings
1186 if (ah->ah_version == AR5K_AR5212 &&
1187 (ah->ah_radio <= AR5K_RF5112)) {
1188 if (!fast && ah->ah_rf_banks != NULL)
1189 ath5k_hw_gainf_calibrate(ah);
1192 /* Wakeup the device */
1193 ret = ath5k_hw_nic_wakeup(ah, channel->hw_value, false);
1197 /* PHY access enable */
1198 if (ah->ah_mac_srev >= AR5K_SREV_AR5211)
1199 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0));
1201 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ | 0x40,
1204 /* Write initial settings */
1205 ret = ath5k_hw_write_initvals(ah, mode, skip_pcu);
1209 /* Initialize core clock settings */
1210 ath5k_hw_init_core_clock(ah);
1213 * Tweak initval settings for revised
1214 * chipsets and add some more config
1217 ath5k_hw_tweak_initval_settings(ah, channel);
1219 /* Commit values from EEPROM */
1220 ath5k_hw_commit_eeprom_settings(ah, channel, ee_mode);
1224 * Restore saved values
1228 if (ah->ah_version != AR5K_AR5210) {
1229 if (ah->ah_mac_srev < AR5K_SREV_AR5211) {
1230 for (i = 0; i < 10; i++)
1231 ath5k_hw_reg_write(ah, s_seq[i],
1232 AR5K_QUEUE_DCU_SEQNUM(i));
1234 ath5k_hw_reg_write(ah, s_seq[0],
1235 AR5K_QUEUE_DCU_SEQNUM(0));
1238 if (ah->ah_version == AR5K_AR5211) {
1239 ath5k_hw_reg_write(ah, tsf_up, AR5K_TSF_U32);
1240 ath5k_hw_reg_write(ah, tsf_lo, AR5K_TSF_L32);
1245 AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, s_led[0]);
1248 ath5k_hw_reg_write(ah, s_led[1], AR5K_GPIOCR);
1249 ath5k_hw_reg_write(ah, s_led[2], AR5K_GPIODO);
1254 ath5k_hw_pcu_init(ah, op_mode, mode);
1259 ret = ath5k_hw_phy_init(ah, channel, mode, ee_mode, freq, false);
1261 ATH5K_ERR(ah->ah_sc,
1262 "failed to initialize PHY (%i) !\n", ret);
1267 * Configure QCUs/DCUs
1269 ret = ath5k_hw_init_queues(ah);
1275 * Initialize DMA/Interrupts
1277 ath5k_hw_dma_init(ah);
1280 /* Enable 32KHz clock function for AR5212+ chips
1281 * Set clocks to 32KHz operation and use an
1282 * external 32KHz crystal when sleeping if one
1284 if (ah->ah_version == AR5K_AR5212 &&
1285 op_mode != NL80211_IFTYPE_AP)
1286 ath5k_hw_set_sleep_clock(ah, true);
1289 * Disable beacons and reset the TSF
1291 AR5K_REG_DISABLE_BITS(ah, AR5K_BEACON, AR5K_BEACON_ENABLE);
1292 ath5k_hw_reset_tsf(ah);